From: "Rafael J. Wysocki" <rafael@kernel.org>
To: Hans de Goede <hdegoede@redhat.com>
Cc: "Thierry Reding" <thierry.reding@gmail.com>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
"Len Brown" <lenb@kernel.org>,
"Linux PWM List" <linux-pwm@vger.kernel.org>,
intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
"ACPI Devel Maling List" <linux-acpi@vger.kernel.org>
Subject: Re: [PATCH v3 01/15] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase
Date: Mon, 22 Jun 2020 18:03:17 +0200 [thread overview]
Message-ID: <CAJZ5v0hheU2SaebNiLgRdxwC_dV44uSFWgAx2pr3w5ENeEF7EQ@mail.gmail.com> (raw)
In-Reply-To: <20200620121758.14836-2-hdegoede@redhat.com>
On Sat, Jun 20, 2020 at 2:18 PM Hans de Goede <hdegoede@redhat.com> wrote:
>
> The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM
> controller gets poked from the _PS0 method of the graphics-card device:
>
> Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */
> If (((Local0 & 0x03) == 0x03))
> {
> PSAT &= 0xFFFFFFFC
> Local1 = PSAT /* \_SB_.PCI0.GFX0.PSAT */
> RSTA = Zero
> RSTF = Zero
> RSTA = One
> RSTF = One
> PWMB |= 0xC0000000
> PWMC = PWMB /* \_SB_.PCI0.GFX0.PWMB */
> }
>
> Where PSAT is the power-status register of the PWM controller, so if it
> is in D3 when the GFX0 device's PS0 method runs then it will turn it on
> and restore the PWM ctrl register value it saved from its PS3 handler.
> Note not only does it restore it, it ors it with 0xC0000000 turning it
> on at a time where we may not want it to get turned on at all.
>
> The pwm_get call which the i915 driver does to get a reference to the
> PWM controller, already adds a device-link making the GFX0 device a
> consumer of the PWM device. So it should already have been resumed when
> the above AML runs and the AML should thus not do its undesirable poking
> of the PWM controller register.
>
> But the PCI core powers on PCI devices in the no-irq resume phase and
> thus calls the troublesome PS0 method in the no-irq resume phase.
> Where as LPSS devices by default are resumed in the early resume phase.
>
> This commit sets the resume_from_noirq flag in the bsw_pwm_dev_desc
> struct, so that Cherry Trail PWM controllers will be resumed in the
> no-irq phase. Together with the device-link added by the pwm-get this
> ensures that the PWM controller will be on when the troublesome PS0
> method runs, which stops it from poking the PWM controller.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> ---
> drivers/acpi/acpi_lpss.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
> index c5a5a179f49d..446e666b3466 100644
> --- a/drivers/acpi/acpi_lpss.c
> +++ b/drivers/acpi/acpi_lpss.c
> @@ -257,6 +257,7 @@ static const struct lpss_device_desc bsw_pwm_dev_desc = {
> .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
> .prv_offset = 0x800,
> .setup = bsw_pwm_setup,
> + .resume_from_noirq = true,
> };
>
> static const struct lpss_device_desc byt_uart_dev_desc = {
> --
> 2.26.2
>
WARNING: multiple messages have this Message-ID (diff)
From: "Rafael J. Wysocki" <rafael@kernel.org>
To: Hans de Goede <hdegoede@redhat.com>
Cc: "Linux PWM List" <linux-pwm@vger.kernel.org>,
intel-gfx <intel-gfx@lists.freedesktop.org>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
"ACPI Devel Maling List" <linux-acpi@vger.kernel.org>,
"Thierry Reding" <thierry.reding@gmail.com>,
dri-devel <dri-devel@lists.freedesktop.org>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
"Len Brown" <lenb@kernel.org>
Subject: Re: [PATCH v3 01/15] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase
Date: Mon, 22 Jun 2020 18:03:17 +0200 [thread overview]
Message-ID: <CAJZ5v0hheU2SaebNiLgRdxwC_dV44uSFWgAx2pr3w5ENeEF7EQ@mail.gmail.com> (raw)
In-Reply-To: <20200620121758.14836-2-hdegoede@redhat.com>
On Sat, Jun 20, 2020 at 2:18 PM Hans de Goede <hdegoede@redhat.com> wrote:
>
> The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM
> controller gets poked from the _PS0 method of the graphics-card device:
>
> Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */
> If (((Local0 & 0x03) == 0x03))
> {
> PSAT &= 0xFFFFFFFC
> Local1 = PSAT /* \_SB_.PCI0.GFX0.PSAT */
> RSTA = Zero
> RSTF = Zero
> RSTA = One
> RSTF = One
> PWMB |= 0xC0000000
> PWMC = PWMB /* \_SB_.PCI0.GFX0.PWMB */
> }
>
> Where PSAT is the power-status register of the PWM controller, so if it
> is in D3 when the GFX0 device's PS0 method runs then it will turn it on
> and restore the PWM ctrl register value it saved from its PS3 handler.
> Note not only does it restore it, it ors it with 0xC0000000 turning it
> on at a time where we may not want it to get turned on at all.
>
> The pwm_get call which the i915 driver does to get a reference to the
> PWM controller, already adds a device-link making the GFX0 device a
> consumer of the PWM device. So it should already have been resumed when
> the above AML runs and the AML should thus not do its undesirable poking
> of the PWM controller register.
>
> But the PCI core powers on PCI devices in the no-irq resume phase and
> thus calls the troublesome PS0 method in the no-irq resume phase.
> Where as LPSS devices by default are resumed in the early resume phase.
>
> This commit sets the resume_from_noirq flag in the bsw_pwm_dev_desc
> struct, so that Cherry Trail PWM controllers will be resumed in the
> no-irq phase. Together with the device-link added by the pwm-get this
> ensures that the PWM controller will be on when the troublesome PS0
> method runs, which stops it from poking the PWM controller.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> ---
> drivers/acpi/acpi_lpss.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
> index c5a5a179f49d..446e666b3466 100644
> --- a/drivers/acpi/acpi_lpss.c
> +++ b/drivers/acpi/acpi_lpss.c
> @@ -257,6 +257,7 @@ static const struct lpss_device_desc bsw_pwm_dev_desc = {
> .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
> .prv_offset = 0x800,
> .setup = bsw_pwm_setup,
> + .resume_from_noirq = true,
> };
>
> static const struct lpss_device_desc byt_uart_dev_desc = {
> --
> 2.26.2
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: "Rafael J. Wysocki" <rafael@kernel.org>
To: Hans de Goede <hdegoede@redhat.com>
Cc: "Linux PWM List" <linux-pwm@vger.kernel.org>,
intel-gfx <intel-gfx@lists.freedesktop.org>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
"ACPI Devel Maling List" <linux-acpi@vger.kernel.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
"Len Brown" <lenb@kernel.org>
Subject: Re: [Intel-gfx] [PATCH v3 01/15] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase
Date: Mon, 22 Jun 2020 18:03:17 +0200 [thread overview]
Message-ID: <CAJZ5v0hheU2SaebNiLgRdxwC_dV44uSFWgAx2pr3w5ENeEF7EQ@mail.gmail.com> (raw)
In-Reply-To: <20200620121758.14836-2-hdegoede@redhat.com>
On Sat, Jun 20, 2020 at 2:18 PM Hans de Goede <hdegoede@redhat.com> wrote:
>
> The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM
> controller gets poked from the _PS0 method of the graphics-card device:
>
> Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */
> If (((Local0 & 0x03) == 0x03))
> {
> PSAT &= 0xFFFFFFFC
> Local1 = PSAT /* \_SB_.PCI0.GFX0.PSAT */
> RSTA = Zero
> RSTF = Zero
> RSTA = One
> RSTF = One
> PWMB |= 0xC0000000
> PWMC = PWMB /* \_SB_.PCI0.GFX0.PWMB */
> }
>
> Where PSAT is the power-status register of the PWM controller, so if it
> is in D3 when the GFX0 device's PS0 method runs then it will turn it on
> and restore the PWM ctrl register value it saved from its PS3 handler.
> Note not only does it restore it, it ors it with 0xC0000000 turning it
> on at a time where we may not want it to get turned on at all.
>
> The pwm_get call which the i915 driver does to get a reference to the
> PWM controller, already adds a device-link making the GFX0 device a
> consumer of the PWM device. So it should already have been resumed when
> the above AML runs and the AML should thus not do its undesirable poking
> of the PWM controller register.
>
> But the PCI core powers on PCI devices in the no-irq resume phase and
> thus calls the troublesome PS0 method in the no-irq resume phase.
> Where as LPSS devices by default are resumed in the early resume phase.
>
> This commit sets the resume_from_noirq flag in the bsw_pwm_dev_desc
> struct, so that Cherry Trail PWM controllers will be resumed in the
> no-irq phase. Together with the device-link added by the pwm-get this
> ensures that the PWM controller will be on when the troublesome PS0
> method runs, which stops it from poking the PWM controller.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> ---
> drivers/acpi/acpi_lpss.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
> index c5a5a179f49d..446e666b3466 100644
> --- a/drivers/acpi/acpi_lpss.c
> +++ b/drivers/acpi/acpi_lpss.c
> @@ -257,6 +257,7 @@ static const struct lpss_device_desc bsw_pwm_dev_desc = {
> .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
> .prv_offset = 0x800,
> .setup = bsw_pwm_setup,
> + .resume_from_noirq = true,
> };
>
> static const struct lpss_device_desc byt_uart_dev_desc = {
> --
> 2.26.2
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-06-22 16:03 UTC|newest]
Thread overview: 114+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-20 12:17 [PATCH v3 00/15] acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 01/15] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-22 16:03 ` Rafael J. Wysocki [this message]
2020-06-22 16:03 ` [Intel-gfx] " Rafael J. Wysocki
2020-06-22 16:03 ` Rafael J. Wysocki
2020-06-20 12:17 ` [PATCH v3 02/15] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-22 16:04 ` Rafael J. Wysocki
2020-06-22 16:04 ` [Intel-gfx] " Rafael J. Wysocki
2020-06-22 16:04 ` Rafael J. Wysocki
2020-06-20 12:17 ` [PATCH v3 03/15] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-22 7:25 ` Uwe Kleine-König
2020-06-22 7:25 ` [Intel-gfx] " Uwe Kleine-König
2020-06-22 7:25 ` Uwe Kleine-König
2020-06-20 12:17 ` [PATCH v3 04/15] pwm: lpss: Add range limit check for the base_unit register value Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-22 7:35 ` Uwe Kleine-König
2020-06-22 7:35 ` [Intel-gfx] " Uwe Kleine-König
2020-06-22 7:35 ` Uwe Kleine-König
2020-07-06 20:53 ` Hans de Goede
2020-07-06 20:53 ` [Intel-gfx] " Hans de Goede
2020-07-06 20:53 ` Hans de Goede
2020-07-07 7:34 ` Uwe Kleine-König
2020-07-07 7:34 ` [Intel-gfx] " Uwe Kleine-König
2020-07-07 7:34 ` Uwe Kleine-König
2020-07-07 8:04 ` Hans de Goede
2020-07-07 8:04 ` [Intel-gfx] " Hans de Goede
2020-07-07 8:04 ` Hans de Goede
2020-07-07 17:31 ` Hans de Goede
2020-07-07 17:31 ` [Intel-gfx] " Hans de Goede
2020-07-07 17:31 ` Hans de Goede
2020-07-07 19:09 ` Uwe Kleine-König
2020-07-07 19:09 ` [Intel-gfx] " Uwe Kleine-König
2020-07-07 19:09 ` Uwe Kleine-König
2020-07-07 19:41 ` Hans de Goede
2020-07-07 19:41 ` [Intel-gfx] " Hans de Goede
2020-07-07 19:41 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 05/15] pwm: lpss: Use pwm_lpss_apply() when restoring state on resume Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 06/15] pwm: crc: Fix period / duty_cycle times being off by a factor of 256 Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 07/15] pwm: crc: Fix off-by-one error in the clock-divider calculations Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 08/15] pwm: crc: Fix period changes not having any effect Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 09/15] pwm: crc: Enable/disable PWM output on enable/disable Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-22 7:55 ` Uwe Kleine-König
2020-06-22 7:55 ` [Intel-gfx] " Uwe Kleine-König
2020-06-22 7:55 ` Uwe Kleine-König
2020-07-06 21:03 ` Hans de Goede
2020-07-06 21:03 ` [Intel-gfx] " Hans de Goede
2020-07-06 21:03 ` Hans de Goede
2020-07-07 7:26 ` Uwe Kleine-König
2020-07-07 7:26 ` [Intel-gfx] " Uwe Kleine-König
2020-07-07 7:26 ` Uwe Kleine-König
2020-06-20 12:17 ` [PATCH v3 10/15] pwm: crc: Implement apply() method to support the new atomic PWM API Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 11/15] pwm: crc: Implement get_state() method Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-22 7:57 ` Uwe Kleine-König
2020-06-22 7:57 ` [Intel-gfx] " Uwe Kleine-König
2020-06-22 7:57 ` Uwe Kleine-König
2020-07-06 21:05 ` Hans de Goede
2020-07-06 21:05 ` [Intel-gfx] " Hans de Goede
2020-07-06 21:05 ` Hans de Goede
2020-07-06 21:05 ` Hans de Goede
2020-07-07 7:24 ` Uwe Kleine-König
2020-07-07 7:24 ` [Intel-gfx] " Uwe Kleine-König
2020-07-07 7:24 ` Uwe Kleine-König
2020-06-20 12:17 ` [PATCH v3 12/15] drm/i915: panel: Add get_vbt_pwm_freq() helper Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 13/15] drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 14/15] drm/i915: panel: Honor the VBT PWM min setting " Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 15/15] drm/i915: panel: Use atomic PWM API " Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-07-07 7:50 ` Uwe Kleine-König
2020-07-07 7:50 ` [Intel-gfx] " Uwe Kleine-König
2020-07-07 7:50 ` Uwe Kleine-König
2020-07-07 19:21 ` Hans de Goede
2020-07-07 19:21 ` [Intel-gfx] " Hans de Goede
2020-07-07 19:21 ` Hans de Goede
2020-06-20 12:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Patchwork
2020-06-20 13:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-20 14:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-06-30 13:51 ` [PATCH v3 00/15] " Jani Nikula
2020-06-30 13:51 ` [Intel-gfx] " Jani Nikula
2020-06-30 13:51 ` Jani Nikula
2020-06-30 13:51 ` Jani Nikula
2020-07-06 20:53 ` Hans de Goede
2020-07-06 20:53 ` [Intel-gfx] " Hans de Goede
2020-07-06 20:53 ` Hans de Goede
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