From: Hans de Goede <hdegoede@redhat.com>
To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Cc: "Thierry Reding" <thierry.reding@gmail.com>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
"Len Brown" <lenb@kernel.org>,
linux-pwm@vger.kernel.org,
intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel@lists.freedesktop.org,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
linux-acpi@vger.kernel.org
Subject: Re: [PATCH v3 04/15] pwm: lpss: Add range limit check for the base_unit register value
Date: Tue, 7 Jul 2020 10:04:58 +0200 [thread overview]
Message-ID: <c2143daa-cdc0-0a72-196f-f27d1677278f@redhat.com> (raw)
In-Reply-To: <20200707073424.w6vd6e4bhl56kosd@pengutronix.de>
Hi,
On 7/7/20 9:34 AM, Uwe Kleine-König wrote:
> On Mon, Jul 06, 2020 at 10:53:08PM +0200, Hans de Goede wrote:
>> Hi,
>>
>> Thank you for your review and sorry for the slow reply.
>
> No problem for me, I didn't hold my breath :-)
>
>>>> diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
>>>> index 43b1fc634af1..80d0f9c64f9d 100644
>>>> --- a/drivers/pwm/pwm-lpss.c
>>>> +++ b/drivers/pwm/pwm-lpss.c
>>>> @@ -97,6 +97,9 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
>>>> freq *= base_unit_range;
>>>> base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
>>>
>>> DIV_ROUND_CLOSEST_ULL is most probably wrong, too. But I didn't spend
>>> the time to actually confirm that.
>>
>> Yes I saw your comment elsewhere that the PWM API defines rounding
>> in a certain direction, but fixing that falls outside of this patch.
>
> Yeah, sure.
>
>> [...]
>> I hope this helps to explain what is going on a bit.
>
> I will try to make sense of that and reply to the patch directly when I
> succeeded.
In case it helps here is the datasheet for the LPSS PWM controller
(somewhat hard to find if you don't know what you are looking for):
https://cdrdv2.intel.com/v1/dl/getcontent/332065
https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-2.pdf
The first link contains a description about how the PWM controller works in
section 17.5 "SIO - Pulse Width Modulation (PWM)", the second link contains
all register definitions for the SoC and is not all that interesting other
then for verifying the existing register bits defines.
Regards,
Hans
>
>> ###
>>
>> As for the behavior on base_unit==0 in the get_state method,
>> as mentioned above I wrote that when I did not fully understood
>> how the controller works.
>>
>> We really should never encounter this.
>>
>> But if we do then I think closest to the truth would be:
>>
>> state->period = UINT_MAX;
>> state->duty_cycle = 0;
>
> I'd say state->period = 1 & state->duty_cycle = 0 is a better
> representation.
>
> Best regards
> Uwe
>
WARNING: multiple messages have this Message-ID (diff)
From: Hans de Goede <hdegoede@redhat.com>
To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Cc: linux-pwm@vger.kernel.org,
intel-gfx <intel-gfx@lists.freedesktop.org>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
linux-acpi@vger.kernel.org,
Thierry Reding <thierry.reding@gmail.com>,
dri-devel@lists.freedesktop.org,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Len Brown <lenb@kernel.org>
Subject: Re: [PATCH v3 04/15] pwm: lpss: Add range limit check for the base_unit register value
Date: Tue, 7 Jul 2020 10:04:58 +0200 [thread overview]
Message-ID: <c2143daa-cdc0-0a72-196f-f27d1677278f@redhat.com> (raw)
In-Reply-To: <20200707073424.w6vd6e4bhl56kosd@pengutronix.de>
Hi,
On 7/7/20 9:34 AM, Uwe Kleine-König wrote:
> On Mon, Jul 06, 2020 at 10:53:08PM +0200, Hans de Goede wrote:
>> Hi,
>>
>> Thank you for your review and sorry for the slow reply.
>
> No problem for me, I didn't hold my breath :-)
>
>>>> diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
>>>> index 43b1fc634af1..80d0f9c64f9d 100644
>>>> --- a/drivers/pwm/pwm-lpss.c
>>>> +++ b/drivers/pwm/pwm-lpss.c
>>>> @@ -97,6 +97,9 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
>>>> freq *= base_unit_range;
>>>> base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
>>>
>>> DIV_ROUND_CLOSEST_ULL is most probably wrong, too. But I didn't spend
>>> the time to actually confirm that.
>>
>> Yes I saw your comment elsewhere that the PWM API defines rounding
>> in a certain direction, but fixing that falls outside of this patch.
>
> Yeah, sure.
>
>> [...]
>> I hope this helps to explain what is going on a bit.
>
> I will try to make sense of that and reply to the patch directly when I
> succeeded.
In case it helps here is the datasheet for the LPSS PWM controller
(somewhat hard to find if you don't know what you are looking for):
https://cdrdv2.intel.com/v1/dl/getcontent/332065
https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-2.pdf
The first link contains a description about how the PWM controller works in
section 17.5 "SIO - Pulse Width Modulation (PWM)", the second link contains
all register definitions for the SoC and is not all that interesting other
then for verifying the existing register bits defines.
Regards,
Hans
>
>> ###
>>
>> As for the behavior on base_unit==0 in the get_state method,
>> as mentioned above I wrote that when I did not fully understood
>> how the controller works.
>>
>> We really should never encounter this.
>>
>> But if we do then I think closest to the truth would be:
>>
>> state->period = UINT_MAX;
>> state->duty_cycle = 0;
>
> I'd say state->period = 1 & state->duty_cycle = 0 is a better
> representation.
>
> Best regards
> Uwe
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Hans de Goede <hdegoede@redhat.com>
To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Cc: linux-pwm@vger.kernel.org,
intel-gfx <intel-gfx@lists.freedesktop.org>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
linux-acpi@vger.kernel.org, dri-devel@lists.freedesktop.org,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Len Brown <lenb@kernel.org>
Subject: Re: [Intel-gfx] [PATCH v3 04/15] pwm: lpss: Add range limit check for the base_unit register value
Date: Tue, 7 Jul 2020 10:04:58 +0200 [thread overview]
Message-ID: <c2143daa-cdc0-0a72-196f-f27d1677278f@redhat.com> (raw)
In-Reply-To: <20200707073424.w6vd6e4bhl56kosd@pengutronix.de>
Hi,
On 7/7/20 9:34 AM, Uwe Kleine-König wrote:
> On Mon, Jul 06, 2020 at 10:53:08PM +0200, Hans de Goede wrote:
>> Hi,
>>
>> Thank you for your review and sorry for the slow reply.
>
> No problem for me, I didn't hold my breath :-)
>
>>>> diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
>>>> index 43b1fc634af1..80d0f9c64f9d 100644
>>>> --- a/drivers/pwm/pwm-lpss.c
>>>> +++ b/drivers/pwm/pwm-lpss.c
>>>> @@ -97,6 +97,9 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
>>>> freq *= base_unit_range;
>>>> base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
>>>
>>> DIV_ROUND_CLOSEST_ULL is most probably wrong, too. But I didn't spend
>>> the time to actually confirm that.
>>
>> Yes I saw your comment elsewhere that the PWM API defines rounding
>> in a certain direction, but fixing that falls outside of this patch.
>
> Yeah, sure.
>
>> [...]
>> I hope this helps to explain what is going on a bit.
>
> I will try to make sense of that and reply to the patch directly when I
> succeeded.
In case it helps here is the datasheet for the LPSS PWM controller
(somewhat hard to find if you don't know what you are looking for):
https://cdrdv2.intel.com/v1/dl/getcontent/332065
https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-2.pdf
The first link contains a description about how the PWM controller works in
section 17.5 "SIO - Pulse Width Modulation (PWM)", the second link contains
all register definitions for the SoC and is not all that interesting other
then for verifying the existing register bits defines.
Regards,
Hans
>
>> ###
>>
>> As for the behavior on base_unit==0 in the get_state method,
>> as mentioned above I wrote that when I did not fully understood
>> how the controller works.
>>
>> We really should never encounter this.
>>
>> But if we do then I think closest to the truth would be:
>>
>> state->period = UINT_MAX;
>> state->duty_cycle = 0;
>
> I'd say state->period = 1 & state->duty_cycle = 0 is a better
> representation.
>
> Best regards
> Uwe
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-07-07 8:05 UTC|newest]
Thread overview: 114+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-20 12:17 [PATCH v3 00/15] acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 01/15] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-22 16:03 ` Rafael J. Wysocki
2020-06-22 16:03 ` [Intel-gfx] " Rafael J. Wysocki
2020-06-22 16:03 ` Rafael J. Wysocki
2020-06-20 12:17 ` [PATCH v3 02/15] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-22 16:04 ` Rafael J. Wysocki
2020-06-22 16:04 ` [Intel-gfx] " Rafael J. Wysocki
2020-06-22 16:04 ` Rafael J. Wysocki
2020-06-20 12:17 ` [PATCH v3 03/15] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-22 7:25 ` Uwe Kleine-König
2020-06-22 7:25 ` [Intel-gfx] " Uwe Kleine-König
2020-06-22 7:25 ` Uwe Kleine-König
2020-06-20 12:17 ` [PATCH v3 04/15] pwm: lpss: Add range limit check for the base_unit register value Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-22 7:35 ` Uwe Kleine-König
2020-06-22 7:35 ` [Intel-gfx] " Uwe Kleine-König
2020-06-22 7:35 ` Uwe Kleine-König
2020-07-06 20:53 ` Hans de Goede
2020-07-06 20:53 ` [Intel-gfx] " Hans de Goede
2020-07-06 20:53 ` Hans de Goede
2020-07-07 7:34 ` Uwe Kleine-König
2020-07-07 7:34 ` [Intel-gfx] " Uwe Kleine-König
2020-07-07 7:34 ` Uwe Kleine-König
2020-07-07 8:04 ` Hans de Goede [this message]
2020-07-07 8:04 ` [Intel-gfx] " Hans de Goede
2020-07-07 8:04 ` Hans de Goede
2020-07-07 17:31 ` Hans de Goede
2020-07-07 17:31 ` [Intel-gfx] " Hans de Goede
2020-07-07 17:31 ` Hans de Goede
2020-07-07 19:09 ` Uwe Kleine-König
2020-07-07 19:09 ` [Intel-gfx] " Uwe Kleine-König
2020-07-07 19:09 ` Uwe Kleine-König
2020-07-07 19:41 ` Hans de Goede
2020-07-07 19:41 ` [Intel-gfx] " Hans de Goede
2020-07-07 19:41 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 05/15] pwm: lpss: Use pwm_lpss_apply() when restoring state on resume Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 06/15] pwm: crc: Fix period / duty_cycle times being off by a factor of 256 Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 07/15] pwm: crc: Fix off-by-one error in the clock-divider calculations Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 08/15] pwm: crc: Fix period changes not having any effect Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 09/15] pwm: crc: Enable/disable PWM output on enable/disable Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-22 7:55 ` Uwe Kleine-König
2020-06-22 7:55 ` [Intel-gfx] " Uwe Kleine-König
2020-06-22 7:55 ` Uwe Kleine-König
2020-07-06 21:03 ` Hans de Goede
2020-07-06 21:03 ` [Intel-gfx] " Hans de Goede
2020-07-06 21:03 ` Hans de Goede
2020-07-07 7:26 ` Uwe Kleine-König
2020-07-07 7:26 ` [Intel-gfx] " Uwe Kleine-König
2020-07-07 7:26 ` Uwe Kleine-König
2020-06-20 12:17 ` [PATCH v3 10/15] pwm: crc: Implement apply() method to support the new atomic PWM API Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 11/15] pwm: crc: Implement get_state() method Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-22 7:57 ` Uwe Kleine-König
2020-06-22 7:57 ` [Intel-gfx] " Uwe Kleine-König
2020-06-22 7:57 ` Uwe Kleine-König
2020-07-06 21:05 ` Hans de Goede
2020-07-06 21:05 ` [Intel-gfx] " Hans de Goede
2020-07-06 21:05 ` Hans de Goede
2020-07-06 21:05 ` Hans de Goede
2020-07-07 7:24 ` Uwe Kleine-König
2020-07-07 7:24 ` [Intel-gfx] " Uwe Kleine-König
2020-07-07 7:24 ` Uwe Kleine-König
2020-06-20 12:17 ` [PATCH v3 12/15] drm/i915: panel: Add get_vbt_pwm_freq() helper Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 13/15] drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 14/15] drm/i915: panel: Honor the VBT PWM min setting " Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-06-20 12:17 ` [PATCH v3 15/15] drm/i915: panel: Use atomic PWM API " Hans de Goede
2020-06-20 12:17 ` [Intel-gfx] " Hans de Goede
2020-06-20 12:17 ` Hans de Goede
2020-07-07 7:50 ` Uwe Kleine-König
2020-07-07 7:50 ` [Intel-gfx] " Uwe Kleine-König
2020-07-07 7:50 ` Uwe Kleine-König
2020-07-07 19:21 ` Hans de Goede
2020-07-07 19:21 ` [Intel-gfx] " Hans de Goede
2020-07-07 19:21 ` Hans de Goede
2020-06-20 12:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Patchwork
2020-06-20 13:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-20 14:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-06-30 13:51 ` [PATCH v3 00/15] " Jani Nikula
2020-06-30 13:51 ` [Intel-gfx] " Jani Nikula
2020-06-30 13:51 ` Jani Nikula
2020-06-30 13:51 ` Jani Nikula
2020-07-06 20:53 ` Hans de Goede
2020-07-06 20:53 ` [Intel-gfx] " Hans de Goede
2020-07-06 20:53 ` Hans de Goede
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