All of lore.kernel.org
 help / color / mirror / Atom feed
From: <ilialin@codeaurora.org>
To: 'Viresh Kumar' <viresh.kumar@linaro.org>
Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
	mark.rutland@arm.com, nm@ti.com, lgirdwood@gmail.com,
	broonie@kernel.org, andy.gross@linaro.org,
	david.brown@linaro.org, catalin.marinas@arm.com,
	will.deacon@arm.com, rjw@rjwysocki.net,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
	linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, rnayak@codeaurora.org,
	amit.kucheria@linaro.org, nicolas.dechesne@linaro.org,
	celster@codeaurora.org, tfinkel@codeaurora.org
Subject: RE: [PATCH v8 10/15] cpufreq: Add Kryo CPU scaling driver
Date: Mon, 21 May 2018 12:00:09 +0300	[thread overview]
Message-ID: <000501d3f0e2$23500c00$69f02400$@codeaurora.org> (raw)
In-Reply-To: <20180521044938.bnr2sdkmvdorfxqm@vireshk-i7>

Final version (addressing Russel's comment as well):




// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 */

/*
 * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
 * the CPU frequency subset and voltage value of each OPP varies
 * based on the silicon variant in use. Qualcomm Process Voltage Scaling
Tables
 * defines the voltage and frequency value based on the msm-id in SMEM
 * and speedbin blown in the efuse combination.
 * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the
SoC
 * to provide the OPP framework with required information.
 * This is used to determine the voltage and frequency value for each OPP of
 * operating-points-v2 table when it is parsed by the OPP framework.
 */

#include <linux/cpu.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/slab.h>
#include <linux/soc/qcom/smem.h>

#define MSM_ID_SMEM	137
#define SILVER_LEAD	0
#define GOLD_LEAD	2

enum _msm_id {
	MSM8996V3 = 0xF6ul,
	APQ8096V3 = 0x123ul,
	MSM8996SG = 0x131ul,
	APQ8096SG = 0x138ul,
};

enum _msm8996_version {
	MSM8996_V3,
	MSM8996_SG,
	NUM_OF_MSM8996_VERSIONS,
};

static enum _msm8996_version __init qcom_cpufreq_kryo_get_msm_id(void)
{
	size_t len;
	u32 *msm_id;
	enum _msm8996_version version;

	msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len);
	/* The first 4 bytes are format, next to them is the actual msm-id
*/
	msm_id++;

	switch ((enum _msm_id)*msm_id) {
	case MSM8996V3:
	case APQ8096V3:
		version = MSM8996_V3;
		break;
	case MSM8996SG:
	case APQ8096SG:
		version = MSM8996_SG;
		break;
	default:
		version = NUM_OF_MSM8996_VERSIONS;
	}

	return version;
}

static int __init qcom_cpufreq_kryo_driver_init(void)
{
	struct device *cpu_dev_silver, *cpu_dev_gold;
	struct opp_table *opp_silver, *opp_gold;
	enum _msm8996_version msm8996_version;
	struct nvmem_cell *speedbin_nvmem;
	struct platform_device *pdev;
	struct device_node *np;
	u8 *speedbin;
	u32 versions;
	size_t len;
	int ret;

	cpu_dev_silver = get_cpu_device(SILVER_LEAD);
	if (NULL == cpu_dev_silver)
		return -ENODEV;

	cpu_dev_gold = get_cpu_device(SILVER_LEAD);
	if (NULL == cpu_dev_gold)
		return -ENODEV;

	msm8996_version = qcom_cpufreq_kryo_get_msm_id();
	if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
		dev_err(cpu_dev_silver, "Not Snapdragon 820/821!");
		return -ENODEV;
	}

	np = dev_pm_opp_of_get_opp_desc_node(cpu_dev_silver);
	if (IS_ERR(np))
		return PTR_ERR(np);

	if (!of_device_is_compatible(np, "operating-points-v2-kryo-cpu")) {
		ret = -ENOENT;
		goto free_np;
	}

	speedbin_nvmem = of_nvmem_cell_get(np, NULL);
	if (IS_ERR(speedbin_nvmem)) {
		ret = PTR_ERR(speedbin_nvmem);
		dev_err(cpu_dev_silver, "Could not get nvmem cell: %d\n",
ret);
		goto free_np;
	}

	speedbin = nvmem_cell_read(speedbin_nvmem, &len);
	nvmem_cell_put(speedbin_nvmem);

	switch (msm8996_version) {
	case MSM8996_V3:
		versions = 1 << (unsigned int)(*speedbin);
		break;
	case MSM8996_SG:
		versions = 1 << ((unsigned int)(*speedbin) + 4);
		break;
	default:
		BUG();
		break;
	}

	opp_silver =
dev_pm_opp_set_supported_hw(cpu_dev_silver,&versions,1);
	if (IS_ERR(opp_silver)) {
		dev_err(cpu_dev_silver, "Failed to set supported
hardware\n");
		ret = PTR_ERR(opp_silver);
		goto free_np;
	}

	opp_gold = dev_pm_opp_set_supported_hw(cpu_dev_gold,&versions,1);
	if (IS_ERR(opp_gold)) {
		dev_err(cpu_dev_gold, "Failed to set supported hardware\n");
		ret = PTR_ERR(opp_gold);
		goto free_opp_silver;
	}

	pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
	if (!IS_ERR(pdev))
		return 0;

	ret = PTR_ERR(pdev);
	dev_err(cpu_dev_silver, "Failed to register platform device\n");
	dev_pm_opp_put_supported_hw(opp_gold);

free_opp_silver:
	dev_pm_opp_put_supported_hw(opp_silver);

free_np:
	of_node_put(np);

	return ret;
}
late_initcall(qcom_cpufreq_kryo_driver_init);

MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq driver");
MODULE_LICENSE("GPL v2");






> -----Original Message-----
> From: Viresh Kumar <viresh.kumar@linaro.org>
> Sent: Monday, May 21, 2018 07:50
> To: ilialin@codeaurora.org
> Cc: mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org;
> mark.rutland@arm.com; nm@ti.com; lgirdwood@gmail.com;
> broonie@kernel.org; andy.gross@linaro.org; david.brown@linaro.org;
> catalin.marinas@arm.com; will.deacon@arm.com; rjw@rjwysocki.net; linux-
> clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-pm@vger.kernel.org; linux-arm-
> msm@vger.kernel.org; linux-soc@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; rnayak@codeaurora.org;
> amit.kucheria@linaro.org; nicolas.dechesne@linaro.org;
> celster@codeaurora.org; tfinkel@codeaurora.org
> Subject: Re: [PATCH v8 10/15] cpufreq: Add Kryo CPU scaling driver
> 
> On 19-05-18, 14:45, ilialin@codeaurora.org wrote:
> > Hi Viresh,
> >
> > If I send patches in reply, it will produce new patches, instead of
> > answers in the thread. Please find below the file dump.
> 
> There is one email from you which appears to be just fine and appears to
be
> in reply to this thread only. Maybe its your email client that screwed it
up for
> you ? Things look good in mutt.
> 
> --
> viresh

WARNING: multiple messages have this Message-ID (diff)
From: <ilialin@codeaurora.org>
To: "'Viresh Kumar'" <viresh.kumar@linaro.org>
Cc: <mturquette@baylibre.com>, <sboyd@kernel.org>, <robh@kernel.org>,
	<mark.rutland@arm.com>, <nm@ti.com>, <lgirdwood@gmail.com>,
	<broonie@kernel.org>, <andy.gross@linaro.org>,
	<david.brown@linaro.org>, <catalin.marinas@arm.com>,
	<will.deacon@arm.com>, <rjw@rjwysocki.net>,
	<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-pm@vger.kernel.org>,
	<linux-arm-msm@vger.kernel.org>, <linux-soc@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <rnayak@codeaurora.org>,
	<amit.kucheria@linaro.org>, <nicolas.dechesne@linaro.org>,
	<celster@codeaurora.org>, <tfinkel@codeaurora.org>
Subject: RE: [PATCH v8 10/15] cpufreq: Add Kryo CPU scaling driver
Date: Mon, 21 May 2018 12:00:09 +0300	[thread overview]
Message-ID: <000501d3f0e2$23500c00$69f02400$@codeaurora.org> (raw)
In-Reply-To: <20180521044938.bnr2sdkmvdorfxqm@vireshk-i7>

Final version (addressing Russel's comment as well):




// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 */

/*
 * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
 * the CPU frequency subset and voltage value of each OPP varies
 * based on the silicon variant in use. Qualcomm Process Voltage Scaling
Tables
 * defines the voltage and frequency value based on the msm-id in SMEM
 * and speedbin blown in the efuse combination.
 * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the
SoC
 * to provide the OPP framework with required information.
 * This is used to determine the voltage and frequency value for each OPP of
 * operating-points-v2 table when it is parsed by the OPP framework.
 */

#include <linux/cpu.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/slab.h>
#include <linux/soc/qcom/smem.h>

#define MSM_ID_SMEM	137
#define SILVER_LEAD	0
#define GOLD_LEAD	2

enum _msm_id {
	MSM8996V3 = 0xF6ul,
	APQ8096V3 = 0x123ul,
	MSM8996SG = 0x131ul,
	APQ8096SG = 0x138ul,
};

enum _msm8996_version {
	MSM8996_V3,
	MSM8996_SG,
	NUM_OF_MSM8996_VERSIONS,
};

static enum _msm8996_version __init qcom_cpufreq_kryo_get_msm_id(void)
{
	size_t len;
	u32 *msm_id;
	enum _msm8996_version version;

	msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len);
	/* The first 4 bytes are format, next to them is the actual msm-id
*/
	msm_id++;

	switch ((enum _msm_id)*msm_id) {
	case MSM8996V3:
	case APQ8096V3:
		version = MSM8996_V3;
		break;
	case MSM8996SG:
	case APQ8096SG:
		version = MSM8996_SG;
		break;
	default:
		version = NUM_OF_MSM8996_VERSIONS;
	}

	return version;
}

static int __init qcom_cpufreq_kryo_driver_init(void)
{
	struct device *cpu_dev_silver, *cpu_dev_gold;
	struct opp_table *opp_silver, *opp_gold;
	enum _msm8996_version msm8996_version;
	struct nvmem_cell *speedbin_nvmem;
	struct platform_device *pdev;
	struct device_node *np;
	u8 *speedbin;
	u32 versions;
	size_t len;
	int ret;

	cpu_dev_silver = get_cpu_device(SILVER_LEAD);
	if (NULL == cpu_dev_silver)
		return -ENODEV;

	cpu_dev_gold = get_cpu_device(SILVER_LEAD);
	if (NULL == cpu_dev_gold)
		return -ENODEV;

	msm8996_version = qcom_cpufreq_kryo_get_msm_id();
	if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
		dev_err(cpu_dev_silver, "Not Snapdragon 820/821!");
		return -ENODEV;
	}

	np = dev_pm_opp_of_get_opp_desc_node(cpu_dev_silver);
	if (IS_ERR(np))
		return PTR_ERR(np);

	if (!of_device_is_compatible(np, "operating-points-v2-kryo-cpu")) {
		ret = -ENOENT;
		goto free_np;
	}

	speedbin_nvmem = of_nvmem_cell_get(np, NULL);
	if (IS_ERR(speedbin_nvmem)) {
		ret = PTR_ERR(speedbin_nvmem);
		dev_err(cpu_dev_silver, "Could not get nvmem cell: %d\n",
ret);
		goto free_np;
	}

	speedbin = nvmem_cell_read(speedbin_nvmem, &len);
	nvmem_cell_put(speedbin_nvmem);

	switch (msm8996_version) {
	case MSM8996_V3:
		versions = 1 << (unsigned int)(*speedbin);
		break;
	case MSM8996_SG:
		versions = 1 << ((unsigned int)(*speedbin) + 4);
		break;
	default:
		BUG();
		break;
	}

	opp_silver =
dev_pm_opp_set_supported_hw(cpu_dev_silver,&versions,1);
	if (IS_ERR(opp_silver)) {
		dev_err(cpu_dev_silver, "Failed to set supported
hardware\n");
		ret = PTR_ERR(opp_silver);
		goto free_np;
	}

	opp_gold = dev_pm_opp_set_supported_hw(cpu_dev_gold,&versions,1);
	if (IS_ERR(opp_gold)) {
		dev_err(cpu_dev_gold, "Failed to set supported hardware\n");
		ret = PTR_ERR(opp_gold);
		goto free_opp_silver;
	}

	pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
	if (!IS_ERR(pdev))
		return 0;

	ret = PTR_ERR(pdev);
	dev_err(cpu_dev_silver, "Failed to register platform device\n");
	dev_pm_opp_put_supported_hw(opp_gold);

free_opp_silver:
	dev_pm_opp_put_supported_hw(opp_silver);

free_np:
	of_node_put(np);

	return ret;
}
late_initcall(qcom_cpufreq_kryo_driver_init);

MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq driver");
MODULE_LICENSE("GPL v2");






> -----Original Message-----
> From: Viresh Kumar <viresh.kumar@linaro.org>
> Sent: Monday, May 21, 2018 07:50
> To: ilialin@codeaurora.org
> Cc: mturquette@baylibre.com; sboyd@kernel.org; robh@kernel.org;
> mark.rutland@arm.com; nm@ti.com; lgirdwood@gmail.com;
> broonie@kernel.org; andy.gross@linaro.org; david.brown@linaro.org;
> catalin.marinas@arm.com; will.deacon@arm.com; rjw@rjwysocki.net; linux-
> clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-pm@vger.kernel.org; linux-arm-
> msm@vger.kernel.org; linux-soc@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; rnayak@codeaurora.org;
> amit.kucheria@linaro.org; nicolas.dechesne@linaro.org;
> celster@codeaurora.org; tfinkel@codeaurora.org
> Subject: Re: [PATCH v8 10/15] cpufreq: Add Kryo CPU scaling driver
> 
> On 19-05-18, 14:45, ilialin@codeaurora.org wrote:
> > Hi Viresh,
> >
> > If I send patches in reply, it will produce new patches, instead of
> > answers in the thread. Please find below the file dump.
> 
> There is one email from you which appears to be just fine and appears to
be
> in reply to this thread only. Maybe its your email client that screwed it
up for
> you ? Things look good in mutt.
> 
> --
> viresh

WARNING: multiple messages have this Message-ID (diff)
From: ilialin@codeaurora.org (ilialin at codeaurora.org)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v8 10/15] cpufreq: Add Kryo CPU scaling driver
Date: Mon, 21 May 2018 12:00:09 +0300	[thread overview]
Message-ID: <000501d3f0e2$23500c00$69f02400$@codeaurora.org> (raw)
In-Reply-To: <20180521044938.bnr2sdkmvdorfxqm@vireshk-i7>

Final version (addressing Russel's comment as well):




// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 */

/*
 * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
 * the CPU frequency subset and voltage value of each OPP varies
 * based on the silicon variant in use. Qualcomm Process Voltage Scaling
Tables
 * defines the voltage and frequency value based on the msm-id in SMEM
 * and speedbin blown in the efuse combination.
 * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the
SoC
 * to provide the OPP framework with required information.
 * This is used to determine the voltage and frequency value for each OPP of
 * operating-points-v2 table when it is parsed by the OPP framework.
 */

#include <linux/cpu.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/slab.h>
#include <linux/soc/qcom/smem.h>

#define MSM_ID_SMEM	137
#define SILVER_LEAD	0
#define GOLD_LEAD	2

enum _msm_id {
	MSM8996V3 = 0xF6ul,
	APQ8096V3 = 0x123ul,
	MSM8996SG = 0x131ul,
	APQ8096SG = 0x138ul,
};

enum _msm8996_version {
	MSM8996_V3,
	MSM8996_SG,
	NUM_OF_MSM8996_VERSIONS,
};

static enum _msm8996_version __init qcom_cpufreq_kryo_get_msm_id(void)
{
	size_t len;
	u32 *msm_id;
	enum _msm8996_version version;

	msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len);
	/* The first 4 bytes are format, next to them is the actual msm-id
*/
	msm_id++;

	switch ((enum _msm_id)*msm_id) {
	case MSM8996V3:
	case APQ8096V3:
		version = MSM8996_V3;
		break;
	case MSM8996SG:
	case APQ8096SG:
		version = MSM8996_SG;
		break;
	default:
		version = NUM_OF_MSM8996_VERSIONS;
	}

	return version;
}

static int __init qcom_cpufreq_kryo_driver_init(void)
{
	struct device *cpu_dev_silver, *cpu_dev_gold;
	struct opp_table *opp_silver, *opp_gold;
	enum _msm8996_version msm8996_version;
	struct nvmem_cell *speedbin_nvmem;
	struct platform_device *pdev;
	struct device_node *np;
	u8 *speedbin;
	u32 versions;
	size_t len;
	int ret;

	cpu_dev_silver = get_cpu_device(SILVER_LEAD);
	if (NULL == cpu_dev_silver)
		return -ENODEV;

	cpu_dev_gold = get_cpu_device(SILVER_LEAD);
	if (NULL == cpu_dev_gold)
		return -ENODEV;

	msm8996_version = qcom_cpufreq_kryo_get_msm_id();
	if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
		dev_err(cpu_dev_silver, "Not Snapdragon 820/821!");
		return -ENODEV;
	}

	np = dev_pm_opp_of_get_opp_desc_node(cpu_dev_silver);
	if (IS_ERR(np))
		return PTR_ERR(np);

	if (!of_device_is_compatible(np, "operating-points-v2-kryo-cpu")) {
		ret = -ENOENT;
		goto free_np;
	}

	speedbin_nvmem = of_nvmem_cell_get(np, NULL);
	if (IS_ERR(speedbin_nvmem)) {
		ret = PTR_ERR(speedbin_nvmem);
		dev_err(cpu_dev_silver, "Could not get nvmem cell: %d\n",
ret);
		goto free_np;
	}

	speedbin = nvmem_cell_read(speedbin_nvmem, &len);
	nvmem_cell_put(speedbin_nvmem);

	switch (msm8996_version) {
	case MSM8996_V3:
		versions = 1 << (unsigned int)(*speedbin);
		break;
	case MSM8996_SG:
		versions = 1 << ((unsigned int)(*speedbin) + 4);
		break;
	default:
		BUG();
		break;
	}

	opp_silver =
dev_pm_opp_set_supported_hw(cpu_dev_silver,&versions,1);
	if (IS_ERR(opp_silver)) {
		dev_err(cpu_dev_silver, "Failed to set supported
hardware\n");
		ret = PTR_ERR(opp_silver);
		goto free_np;
	}

	opp_gold = dev_pm_opp_set_supported_hw(cpu_dev_gold,&versions,1);
	if (IS_ERR(opp_gold)) {
		dev_err(cpu_dev_gold, "Failed to set supported hardware\n");
		ret = PTR_ERR(opp_gold);
		goto free_opp_silver;
	}

	pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
	if (!IS_ERR(pdev))
		return 0;

	ret = PTR_ERR(pdev);
	dev_err(cpu_dev_silver, "Failed to register platform device\n");
	dev_pm_opp_put_supported_hw(opp_gold);

free_opp_silver:
	dev_pm_opp_put_supported_hw(opp_silver);

free_np:
	of_node_put(np);

	return ret;
}
late_initcall(qcom_cpufreq_kryo_driver_init);

MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq driver");
MODULE_LICENSE("GPL v2");






> -----Original Message-----
> From: Viresh Kumar <viresh.kumar@linaro.org>
> Sent: Monday, May 21, 2018 07:50
> To: ilialin at codeaurora.org
> Cc: mturquette at baylibre.com; sboyd at kernel.org; robh at kernel.org;
> mark.rutland at arm.com; nm at ti.com; lgirdwood at gmail.com;
> broonie at kernel.org; andy.gross at linaro.org; david.brown at linaro.org;
> catalin.marinas at arm.com; will.deacon at arm.com; rjw at rjwysocki.net; linux-
> clk at vger.kernel.org; devicetree at vger.kernel.org; linux-
> kernel at vger.kernel.org; linux-pm at vger.kernel.org; linux-arm-
> msm at vger.kernel.org; linux-soc at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; rnayak at codeaurora.org;
> amit.kucheria at linaro.org; nicolas.dechesne at linaro.org;
> celster at codeaurora.org; tfinkel at codeaurora.org
> Subject: Re: [PATCH v8 10/15] cpufreq: Add Kryo CPU scaling driver
> 
> On 19-05-18, 14:45, ilialin at codeaurora.org wrote:
> > Hi Viresh,
> >
> > If I send patches in reply, it will produce new patches, instead of
> > answers in the thread. Please find below the file dump.
> 
> There is one email from you which appears to be just fine and appears to
be
> in reply to this thread only. Maybe its your email client that screwed it
up for
> you ? Things look good in mutt.
> 
> --
> viresh

  reply	other threads:[~2018-05-21  9:00 UTC|newest]

Thread overview: 114+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-17 11:19 [PATCH v8 00/15] CPU scaling support for msm8996 Ilia Lin
2018-05-17 11:19 ` Ilia Lin
2018-05-17 11:19 ` [PATCH v8 01/15] soc: qcom: Separate kryo l2 accessors from PMU driver Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-17 11:19 ` [PATCH v8 02/15] clk: qcom: Make clk_alpha_pll_configure available to modules Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-17 11:19 ` [PATCH v8 03/15] clk: Use devm_ in the register fixed factor clock Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-17 11:19 ` [PATCH v8 04/15] clk: qcom: Add CPU clock driver for msm8996 Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-22 13:49   ` kbuild test robot
2018-05-22 13:49     ` kbuild test robot
2018-05-22 13:49     ` kbuild test robot
2018-05-17 11:19 ` [PATCH v8 05/15] dt-bindings: clk: qcom: Add bindings for CPU clock " Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-17 11:19 ` [PATCH v8 06/15] clk: qcom: cpu-8996: Add support to switch to alternate PLL Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-17 11:19 ` [PATCH v8 07/15] clk: qcom: cpu-8996: Add support to switch below 600Mhz Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-17 11:19 ` [PATCH v8 08/15] clk: qcom: Add ACD path to CPU clock driver for msm8996 Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-17 11:19 ` [PATCH v8 09/15] dt: qcom: Add opp and thermal to the msm8996 Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-17 11:19 ` [PATCH v8 10/15] cpufreq: Add Kryo CPU scaling driver Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-18  1:45   ` Viresh Kumar
2018-05-18  1:45     ` Viresh Kumar
2018-05-19 11:09     ` ilialin
2018-05-19 11:09       ` ilialin at codeaurora.org
2018-05-19 11:09       ` ilialin
2018-05-19 11:54       ` Russell King - ARM Linux
2018-05-19 11:54         ` Russell King - ARM Linux
2018-05-19 11:41     ` ilialin
2018-05-19 11:41       ` ilialin at codeaurora.org
2018-05-19 11:41       ` ilialin
2018-05-19 11:45     ` ilialin
2018-05-19 11:45       ` ilialin at codeaurora.org
2018-05-19 11:45       ` ilialin
2018-05-21  4:49       ` Viresh Kumar
2018-05-21  4:49         ` Viresh Kumar
2018-05-21  9:00         ` ilialin [this message]
2018-05-21  9:00           ` ilialin at codeaurora.org
2018-05-21  9:00           ` ilialin
2018-05-21  9:05           ` Viresh Kumar
2018-05-21  9:05             ` Viresh Kumar
2018-05-19 11:35   ` [PATCH] " Ilia Lin
2018-05-19 11:35     ` Ilia Lin
2018-05-21  5:04     ` Viresh Kumar
2018-05-21  5:04       ` Viresh Kumar
2018-05-21 12:50     ` Sudeep Holla
2018-05-21 12:50       ` Sudeep Holla
2018-05-21 12:57       ` ilialin
2018-05-21 12:57         ` ilialin at codeaurora.org
2018-05-21 12:57         ` ilialin
2018-05-21 12:57         ` ilialin
2018-05-21 13:04         ` Sudeep Holla
2018-05-21 13:04           ` Sudeep Holla
2018-05-22  6:56           ` ilialin
2018-05-22  6:56             ` ilialin at codeaurora.org
2018-05-22  6:56             ` ilialin
2018-05-22  6:56             ` ilialin
2018-05-22  9:12             ` Sudeep Holla
2018-05-22  9:12               ` Sudeep Holla
2018-05-22  7:59           ` ilialin
2018-05-22  7:59             ` ilialin at codeaurora.org
2018-05-22  7:59             ` ilialin
2018-05-22  7:59             ` ilialin
2018-05-22  9:18             ` Sudeep Holla
2018-05-22  9:18               ` Sudeep Holla
2018-05-22  9:38             ` Viresh Kumar
2018-05-22  9:38               ` Viresh Kumar
2018-05-22 11:29     ` Ilia Lin
2018-05-22 11:29       ` Ilia Lin
2018-05-22 13:07       ` Sudeep Holla
2018-05-22 13:07         ` Sudeep Holla
2018-05-23  5:44         ` Viresh Kumar
2018-05-23  5:44           ` Viresh Kumar
2018-05-23  9:05     ` Ilia Lin
2018-05-23  9:05       ` Ilia Lin
2018-05-23  9:32       ` Viresh Kumar
2018-05-23  9:32         ` Viresh Kumar
2018-05-23  9:40       ` Russell King - ARM Linux
2018-05-23  9:40         ` Russell King - ARM Linux
2018-05-23  9:59         ` Viresh Kumar
2018-05-23  9:59           ` Viresh Kumar
2018-05-21 10:31   ` Ilia Lin
2018-05-21 10:31     ` Ilia Lin
2018-05-21 10:37     ` Viresh Kumar
2018-05-21 10:37       ` Viresh Kumar
2018-05-21 10:54     ` Russell King - ARM Linux
2018-05-21 10:54       ` Russell King - ARM Linux
2018-05-21 11:05       ` ilialin
2018-05-21 11:05         ` ilialin at codeaurora.org
2018-05-21 11:05         ` ilialin
2018-05-21 12:11         ` Russell King - ARM Linux
2018-05-21 12:11           ` Russell King - ARM Linux
2018-05-21 12:35           ` ilialin
2018-05-21 12:35             ` ilialin at codeaurora.org
2018-05-21 12:35             ` ilialin
2018-05-21 12:41             ` Russell King - ARM Linux
2018-05-21 12:41               ` Russell King - ARM Linux
2018-05-17 11:19 ` [PATCH v8 11/15] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-18 14:26   ` Rob Herring
2018-05-18 14:26     ` Rob Herring
2018-05-17 11:19 ` [PATCH v8 12/15] dt: qcom: Add qcom-cpufreq-kryo driver configuration Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-17 11:19 ` [PATCH v8 13/15] regulator: qcom_spmi: Add support for SAW Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-17 11:19 ` [PATCH v8 14/15] dt-bindings: qcom_spmi: Document SAW support Ilia Lin
2018-05-17 11:19   ` Ilia Lin
2018-05-17 11:19 ` [PATCH v8 15/15] dt: qcom: Add SAW regulator for 8x96 CPUs Ilia Lin
2018-05-17 11:19   ` Ilia Lin

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='000501d3f0e2$23500c00$69f02400$@codeaurora.org' \
    --to=ilialin@codeaurora.org \
    --cc=amit.kucheria@linaro.org \
    --cc=andy.gross@linaro.org \
    --cc=broonie@kernel.org \
    --cc=catalin.marinas@arm.com \
    --cc=celster@codeaurora.org \
    --cc=david.brown@linaro.org \
    --cc=devicetree@vger.kernel.org \
    --cc=lgirdwood@gmail.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pm@vger.kernel.org \
    --cc=linux-soc@vger.kernel.org \
    --cc=mark.rutland@arm.com \
    --cc=mturquette@baylibre.com \
    --cc=nicolas.dechesne@linaro.org \
    --cc=nm@ti.com \
    --cc=rjw@rjwysocki.net \
    --cc=rnayak@codeaurora.org \
    --cc=robh@kernel.org \
    --cc=sboyd@kernel.org \
    --cc=tfinkel@codeaurora.org \
    --cc=viresh.kumar@linaro.org \
    --cc=will.deacon@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.