From: Ilia Lin <ilialin@codeaurora.org> To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, mark.rutland@arm.com, viresh.kumar@linaro.org, nm@ti.com, lgirdwood@gmail.com, broonie@kernel.org, andy.gross@linaro.org, david.brown@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, rjw@rjwysocki.net, linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, rnayak@codeaurora.org, ilialin@codeaurora.org, amit.kucheria@linaro.org, nicolas.dechesne@linaro.org, celster@codeaurora.org, tfinkel@codeaurora.org Subject: [PATCH v8 07/15] clk: qcom: cpu-8996: Add support to switch below 600Mhz Date: Thu, 17 May 2018 14:19:07 +0300 [thread overview] Message-ID: <1526555955-29960-8-git-send-email-ilialin@codeaurora.org> (raw) In-Reply-To: <1526555955-29960-1-git-send-email-ilialin@codeaurora.org> The CPU clock controller's primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX. So for frequencies above 600MHz we follow the following path Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk and for frequencies between 300MHz and 600MHz we follow Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Ilia Lin <ilialin@codeaurora.org> --- drivers/clk/qcom/clk-cpu-8996.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 620fdc2..ff5c0a5 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -68,6 +68,8 @@ enum _pmux_input { NUM_OF_PMUX_INPUTS }; +#define DIV_2_THRESHOLD 600000000 + static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = { [PLL_OFF_L_VAL] = 0x04, [PLL_OFF_ALPHA_VAL] = 0x08, @@ -95,10 +97,11 @@ enum _pmux_input { static const struct alpha_pll_config hfpll_config = { .l = 60, - .config_ctl_val = 0x200d4828, + .config_ctl_val = 0x200d4aa8, .config_ctl_hi_val = 0x006, .pre_div_mask = BIT(12), .post_div_mask = 0x3 << 8, + .post_div_val = 0x1 << 8, .main_output_mask = BIT(0), .early_output_mask = BIT(3), }; @@ -140,7 +143,7 @@ enum _pmux_input { .vco_mask = 0x3 << 20, .config_ctl_val = 0x4001051b, .post_div_mask = 0x3 << 8, - .post_div_val = 0x1, + .post_div_val = 0x1 << 8, .main_output_mask = BIT(0), .early_output_mask = BIT(3), }; @@ -181,6 +184,7 @@ struct clk_cpu_8996_mux { u8 width; struct notifier_block nb; struct clk_hw *pll; + struct clk_hw *pll_div_2; struct clk_regmap clkr; }; @@ -226,6 +230,13 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); struct clk_hw *parent = cpuclk->pll; + if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) { + if (req->rate < (DIV_2_THRESHOLD / 2)) + return -EINVAL; + + parent = cpuclk->pll_div_2; + } + req->best_parent_rate = clk_hw_round_rate(parent, req->rate); req->best_parent_hw = parent; @@ -237,13 +248,19 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, { int ret; struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb); + struct clk_notifier_data *cnd = data; switch (event) { case PRE_RATE_CHANGE: ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX); break; case POST_RATE_CHANGE: - ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, PLL_INDEX); + if (cnd->new_rate < DIV_2_THRESHOLD) + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, + DIV_2_INDEX); + else + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, + PLL_INDEX); break; default: ret = 0; @@ -295,6 +312,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, .shift = 0, .width = 2, .pll = &pwrcl_pll.clkr.hw, + .pll_div_2 = &pwrcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_pmux", @@ -315,6 +333,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, .shift = 0, .width = 2, .pll = &perfcl_pll.clkr.hw, + .pll_div_2 = &perfcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_pmux", -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: ilialin@codeaurora.org (Ilia Lin) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 07/15] clk: qcom: cpu-8996: Add support to switch below 600Mhz Date: Thu, 17 May 2018 14:19:07 +0300 [thread overview] Message-ID: <1526555955-29960-8-git-send-email-ilialin@codeaurora.org> (raw) In-Reply-To: <1526555955-29960-1-git-send-email-ilialin@codeaurora.org> The CPU clock controller's primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX. So for frequencies above 600MHz we follow the following path Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk and for frequencies between 300MHz and 600MHz we follow Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Ilia Lin <ilialin@codeaurora.org> --- drivers/clk/qcom/clk-cpu-8996.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 620fdc2..ff5c0a5 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -68,6 +68,8 @@ enum _pmux_input { NUM_OF_PMUX_INPUTS }; +#define DIV_2_THRESHOLD 600000000 + static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = { [PLL_OFF_L_VAL] = 0x04, [PLL_OFF_ALPHA_VAL] = 0x08, @@ -95,10 +97,11 @@ enum _pmux_input { static const struct alpha_pll_config hfpll_config = { .l = 60, - .config_ctl_val = 0x200d4828, + .config_ctl_val = 0x200d4aa8, .config_ctl_hi_val = 0x006, .pre_div_mask = BIT(12), .post_div_mask = 0x3 << 8, + .post_div_val = 0x1 << 8, .main_output_mask = BIT(0), .early_output_mask = BIT(3), }; @@ -140,7 +143,7 @@ enum _pmux_input { .vco_mask = 0x3 << 20, .config_ctl_val = 0x4001051b, .post_div_mask = 0x3 << 8, - .post_div_val = 0x1, + .post_div_val = 0x1 << 8, .main_output_mask = BIT(0), .early_output_mask = BIT(3), }; @@ -181,6 +184,7 @@ struct clk_cpu_8996_mux { u8 width; struct notifier_block nb; struct clk_hw *pll; + struct clk_hw *pll_div_2; struct clk_regmap clkr; }; @@ -226,6 +230,13 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); struct clk_hw *parent = cpuclk->pll; + if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) { + if (req->rate < (DIV_2_THRESHOLD / 2)) + return -EINVAL; + + parent = cpuclk->pll_div_2; + } + req->best_parent_rate = clk_hw_round_rate(parent, req->rate); req->best_parent_hw = parent; @@ -237,13 +248,19 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, { int ret; struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb); + struct clk_notifier_data *cnd = data; switch (event) { case PRE_RATE_CHANGE: ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX); break; case POST_RATE_CHANGE: - ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, PLL_INDEX); + if (cnd->new_rate < DIV_2_THRESHOLD) + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, + DIV_2_INDEX); + else + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, + PLL_INDEX); break; default: ret = 0; @@ -295,6 +312,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, .shift = 0, .width = 2, .pll = &pwrcl_pll.clkr.hw, + .pll_div_2 = &pwrcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_pmux", @@ -315,6 +333,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, .shift = 0, .width = 2, .pll = &perfcl_pll.clkr.hw, + .pll_div_2 = &perfcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_pmux", -- 1.9.1
next prev parent reply other threads:[~2018-05-17 11:19 UTC|newest] Thread overview: 114+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-05-17 11:19 [PATCH v8 00/15] CPU scaling support for msm8996 Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-17 11:19 ` [PATCH v8 01/15] soc: qcom: Separate kryo l2 accessors from PMU driver Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-17 11:19 ` [PATCH v8 02/15] clk: qcom: Make clk_alpha_pll_configure available to modules Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-17 11:19 ` [PATCH v8 03/15] clk: Use devm_ in the register fixed factor clock Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-17 11:19 ` [PATCH v8 04/15] clk: qcom: Add CPU clock driver for msm8996 Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-22 13:49 ` kbuild test robot 2018-05-22 13:49 ` kbuild test robot 2018-05-22 13:49 ` kbuild test robot 2018-05-17 11:19 ` [PATCH v8 05/15] dt-bindings: clk: qcom: Add bindings for CPU clock " Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-17 11:19 ` [PATCH v8 06/15] clk: qcom: cpu-8996: Add support to switch to alternate PLL Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-17 11:19 ` Ilia Lin [this message] 2018-05-17 11:19 ` [PATCH v8 07/15] clk: qcom: cpu-8996: Add support to switch below 600Mhz Ilia Lin 2018-05-17 11:19 ` [PATCH v8 08/15] clk: qcom: Add ACD path to CPU clock driver for msm8996 Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-17 11:19 ` [PATCH v8 09/15] dt: qcom: Add opp and thermal to the msm8996 Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-17 11:19 ` [PATCH v8 10/15] cpufreq: Add Kryo CPU scaling driver Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-18 1:45 ` Viresh Kumar 2018-05-18 1:45 ` Viresh Kumar 2018-05-19 11:09 ` ilialin 2018-05-19 11:09 ` ilialin at codeaurora.org 2018-05-19 11:09 ` ilialin 2018-05-19 11:54 ` Russell King - ARM Linux 2018-05-19 11:54 ` Russell King - ARM Linux 2018-05-19 11:41 ` ilialin 2018-05-19 11:41 ` ilialin at codeaurora.org 2018-05-19 11:41 ` ilialin 2018-05-19 11:45 ` ilialin 2018-05-19 11:45 ` ilialin at codeaurora.org 2018-05-19 11:45 ` ilialin 2018-05-21 4:49 ` Viresh Kumar 2018-05-21 4:49 ` Viresh Kumar 2018-05-21 9:00 ` ilialin 2018-05-21 9:00 ` ilialin at codeaurora.org 2018-05-21 9:00 ` ilialin 2018-05-21 9:05 ` Viresh Kumar 2018-05-21 9:05 ` Viresh Kumar 2018-05-19 11:35 ` [PATCH] " Ilia Lin 2018-05-19 11:35 ` Ilia Lin 2018-05-21 5:04 ` Viresh Kumar 2018-05-21 5:04 ` Viresh Kumar 2018-05-21 12:50 ` Sudeep Holla 2018-05-21 12:50 ` Sudeep Holla 2018-05-21 12:57 ` ilialin 2018-05-21 12:57 ` ilialin at codeaurora.org 2018-05-21 12:57 ` ilialin 2018-05-21 12:57 ` ilialin 2018-05-21 13:04 ` Sudeep Holla 2018-05-21 13:04 ` Sudeep Holla 2018-05-22 6:56 ` ilialin 2018-05-22 6:56 ` ilialin at codeaurora.org 2018-05-22 6:56 ` ilialin 2018-05-22 6:56 ` ilialin 2018-05-22 9:12 ` Sudeep Holla 2018-05-22 9:12 ` Sudeep Holla 2018-05-22 7:59 ` ilialin 2018-05-22 7:59 ` ilialin at codeaurora.org 2018-05-22 7:59 ` ilialin 2018-05-22 7:59 ` ilialin 2018-05-22 9:18 ` Sudeep Holla 2018-05-22 9:18 ` Sudeep Holla 2018-05-22 9:38 ` Viresh Kumar 2018-05-22 9:38 ` Viresh Kumar 2018-05-22 11:29 ` Ilia Lin 2018-05-22 11:29 ` Ilia Lin 2018-05-22 13:07 ` Sudeep Holla 2018-05-22 13:07 ` Sudeep Holla 2018-05-23 5:44 ` Viresh Kumar 2018-05-23 5:44 ` Viresh Kumar 2018-05-23 9:05 ` Ilia Lin 2018-05-23 9:05 ` Ilia Lin 2018-05-23 9:32 ` Viresh Kumar 2018-05-23 9:32 ` Viresh Kumar 2018-05-23 9:40 ` Russell King - ARM Linux 2018-05-23 9:40 ` Russell King - ARM Linux 2018-05-23 9:59 ` Viresh Kumar 2018-05-23 9:59 ` Viresh Kumar 2018-05-21 10:31 ` Ilia Lin 2018-05-21 10:31 ` Ilia Lin 2018-05-21 10:37 ` Viresh Kumar 2018-05-21 10:37 ` Viresh Kumar 2018-05-21 10:54 ` Russell King - ARM Linux 2018-05-21 10:54 ` Russell King - ARM Linux 2018-05-21 11:05 ` ilialin 2018-05-21 11:05 ` ilialin at codeaurora.org 2018-05-21 11:05 ` ilialin 2018-05-21 12:11 ` Russell King - ARM Linux 2018-05-21 12:11 ` Russell King - ARM Linux 2018-05-21 12:35 ` ilialin 2018-05-21 12:35 ` ilialin at codeaurora.org 2018-05-21 12:35 ` ilialin 2018-05-21 12:41 ` Russell King - ARM Linux 2018-05-21 12:41 ` Russell King - ARM Linux 2018-05-17 11:19 ` [PATCH v8 11/15] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-18 14:26 ` Rob Herring 2018-05-18 14:26 ` Rob Herring 2018-05-17 11:19 ` [PATCH v8 12/15] dt: qcom: Add qcom-cpufreq-kryo driver configuration Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-17 11:19 ` [PATCH v8 13/15] regulator: qcom_spmi: Add support for SAW Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-17 11:19 ` [PATCH v8 14/15] dt-bindings: qcom_spmi: Document SAW support Ilia Lin 2018-05-17 11:19 ` Ilia Lin 2018-05-17 11:19 ` [PATCH v8 15/15] dt: qcom: Add SAW regulator for 8x96 CPUs Ilia Lin 2018-05-17 11:19 ` Ilia Lin
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