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From: Michal Simek <michal.simek@xilinx.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [RFC PATCH 4/4] arm: zynq: spl: implement FPGA load from FIT
Date: Thu, 19 Jul 2018 08:15:56 +0200	[thread overview]
Message-ID: <0705398a-e315-766c-2157-b7a0f25f9530@xilinx.com> (raw)
In-Reply-To: <CAHbBuxq+HwnDyMgrvqt7K7SgWPSQBGK_WNv=kT73fFPjGQGnRQ@mail.gmail.com>

Hi,

On 18.7.2018 20:14, Luis Araneda wrote:
> Hi Michal,
> 
> On Wed, Jul 18, 2018 at 9:22 AM Michal Simek <michal.simek@xilinx.com> wrote:
>> I was playing  with this a little bit. There is no reason to allocate
>> any space in malloc area because its/fit should already contain load
>> address which you should use instead.
> 
> I initially thought the same, but unfortunately the load address is
> not a parameter passed to the function, nor can it be extracted from
> the spl_load_info structure.
> Like you have probably discovered by now, the spl_load_fpga_image()
> function was introduced to support the use case of  boards with
> uninitialized DRAM, so the load address was not necessary.
> On the other hand, the zynpl driver doesn't have functions to program
> the FPGA by chunks, so I had to allocate memory.

Feel free to join that thread with Marek.
I think that what we have in u-boot source code is not correct and it is
one ugly hack which has no user and nothing is broken because support
hasn't been merged to mainline.
I have played with that yesterday and send this patch which should be
enough for you to go.
https://lists.denx.de/pipermail/u-boot/2018-July/335169.html

Also on zc706 without FULL_FIT my path in spl_load_fit_image is not
jumping to "if (external_data) {" branch where spl_load_fpga_image is
which is kind of interesting because it looks like you are going there.

Thanks,
Michal

  reply	other threads:[~2018-07-19  6:15 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-18  7:41 [U-Boot] [RFC PATCH 0/4] arm: zynq: implement FPGA load from SPL Luis Araneda
2018-07-18  7:41 ` [U-Boot] [RFC PATCH 1/4] spl: fit: display a message when an FPGA image is loaded Luis Araneda
2018-07-18 13:55   ` Michal Simek
2018-07-18  7:41 ` [U-Boot] [RFC PATCH 2/4] drivers: fpga: zynqpl: fix compilation with SPL Luis Araneda
2018-07-18 13:55   ` Michal Simek
2018-07-18  7:41 ` [U-Boot] [RFC PATCH 3/4] arm: zynq: spl: fix FPGA initialization Luis Araneda
2018-07-18 13:55   ` Michal Simek
2018-07-18  7:41 ` [U-Boot] [RFC PATCH 4/4] arm: zynq: spl: implement FPGA load from FIT Luis Araneda
2018-07-18 13:22   ` Michal Simek
2018-07-18 18:14     ` Luis Araneda
2018-07-19  6:15       ` Michal Simek [this message]
2018-07-19 17:22         ` Luis Araneda
2018-07-20 10:34           ` Michal Simek
2018-07-18  8:00 ` [U-Boot] [RFC PATCH 0/4] arm: zynq: implement FPGA load from SPL Michal Simek
2018-07-18 18:02   ` Luis Araneda
2018-07-19  6:22     ` Michal Simek
2018-07-19 23:37       ` Luis Araneda
2018-07-20 10:38         ` Michal Simek
2018-07-20 16:17           ` Luis Araneda
2018-07-24 13:42             ` Michal Simek

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