From: Luis Araneda <luaraneda@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [RFC PATCH 0/4] arm: zynq: implement FPGA load from SPL
Date: Wed, 18 Jul 2018 03:41:37 -0400 [thread overview]
Message-ID: <20180718074141.16539-1-luaraneda@gmail.com> (raw)
This series implements FPGA bitstream loading from SPL.
Programming the FPGA from the SPL is necessary on some boards,
like the Zybo, because the FPGA fabric routes the I2C bus to an
EEPROM for reading the Ethernet MAC address.
The bitstream is loaded from a FIT image into a dynamically-allocated
memory before programming the FPGA.
Additionally, some fixes are applied to compile the zynqpl driver
for SPL, and to properly detect an FPGA from the SPL.
I'm not sure if the fixes are correct or I'm missing something,
hence the RFC.
Tested on a Digilent Zybo Z7-20 board
Luis Araneda (4):
spl: fit: display a message when an FPGA image is loaded
drivers: fpga: zynqpl: fix compilation with SPL
arm: zynq: spl: fix FPGA initialization
arm: zynq: spl: implement FPGA load from FIT
arch/arm/mach-zynq/spl.c | 42 ++++++++++++++++++++++++++++++++++++++++
common/spl/spl_fit.c | 1 +
drivers/fpga/zynqpl.c | 4 ++--
3 files changed, 45 insertions(+), 2 deletions(-)
--
2.18.0
next reply other threads:[~2018-07-18 7:41 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-18 7:41 Luis Araneda [this message]
2018-07-18 7:41 ` [U-Boot] [RFC PATCH 1/4] spl: fit: display a message when an FPGA image is loaded Luis Araneda
2018-07-18 13:55 ` Michal Simek
2018-07-18 7:41 ` [U-Boot] [RFC PATCH 2/4] drivers: fpga: zynqpl: fix compilation with SPL Luis Araneda
2018-07-18 13:55 ` Michal Simek
2018-07-18 7:41 ` [U-Boot] [RFC PATCH 3/4] arm: zynq: spl: fix FPGA initialization Luis Araneda
2018-07-18 13:55 ` Michal Simek
2018-07-18 7:41 ` [U-Boot] [RFC PATCH 4/4] arm: zynq: spl: implement FPGA load from FIT Luis Araneda
2018-07-18 13:22 ` Michal Simek
2018-07-18 18:14 ` Luis Araneda
2018-07-19 6:15 ` Michal Simek
2018-07-19 17:22 ` Luis Araneda
2018-07-20 10:34 ` Michal Simek
2018-07-18 8:00 ` [U-Boot] [RFC PATCH 0/4] arm: zynq: implement FPGA load from SPL Michal Simek
2018-07-18 18:02 ` Luis Araneda
2018-07-19 6:22 ` Michal Simek
2018-07-19 23:37 ` Luis Araneda
2018-07-20 10:38 ` Michal Simek
2018-07-20 16:17 ` Luis Araneda
2018-07-24 13:42 ` Michal Simek
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