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From: John Garry <john.garry@huawei.com>
To: <broonie@kernel.org>, <marek.vasut@gmail.com>,
	<tudor.ambarus@microchip.com>
Cc: <linuxarm@huawei.com>, <linux-kernel@vger.kernel.org>,
	<linux-mtd@lists.infradead.org>, <linux-spi@vger.kernel.org>,
	<xuejiancheng@hisilicon.com>, <fengsheng5@huawei.com>,
	<chenxiang66@hisilicon.com>
Subject: Re: [PATCH v2 2/3] spi: Add HiSilicon v3xx SPI NOR flash controller driver
Date: Thu, 9 Jan 2020 15:54:00 +0000	[thread overview]
Message-ID: <0dc5cb2e-b765-9e13-b05e-9e3c835c5985@huawei.com> (raw)
In-Reply-To: <1575900490-74467-3-git-send-email-john.garry@huawei.com>

On 09/12/2019 14:08, John Garry wrote:
> +	if (ret)
> +		return ret;
> +
> +	if (op->data.dir == SPI_MEM_DATA_IN)
> +		hisi_sfc_v3xx_read_databuf(host, op->data.buf.in, len);
> +
> +	return 0;
> +}
> +
> +static int hisi_sfc_v3xx_exec_op(struct spi_mem *mem,
> +				 const struct spi_mem_op *op)
> +{
> +	struct hisi_sfc_v3xx_host *host;
> +	struct spi_device *spi = mem->spi;
> +	u8 chip_select = spi->chip_select;
> +
> +	host = spi_controller_get_devdata(spi->master);
> +
> +	return hisi_sfc_v3xx_generic_exec_op(host, op, chip_select);
> +}
> +
> +static const struct spi_controller_mem_ops hisi_sfc_v3xx_mem_ops = {
> +	.adjust_op_size = hisi_sfc_v3xx_adjust_op_size,
> +	.exec_op = hisi_sfc_v3xx_exec_op,
> +};
> +
> +static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct hisi_sfc_v3xx_host *host;
> +	struct spi_controller *ctlr;
> +	u32 version;
> +	int ret;
> +
> +	ctlr = spi_alloc_master(&pdev->dev, sizeof(*host));
> +	if (!ctlr)
> +		return -ENOMEM;
> +


Hi Mark,

> +	ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
> +			  SPI_TX_DUAL | SPI_TX_QUAD;

I have an issue with dual/quad support. I naively thought that setting 
these bits would give me the highest protocol available.

However, now I notice that spi_device.mode needs to be set for supported 
protocols for the slave - I'm using the generic spi mem ops to check if 
protocols are supported based on this value.

 From checking acpi_spi_add_resource() or anywhere else, I cannot see 
how SPI_RX_DUAL or the others are set for spi_device.mode. What am I 
missing? Are these just not supported yet for ACPI? Or should the 
spi-nor code not be relying on this since we should be able to get this 
info from the SPI NOR part?

Cheers,
John

> +
> +	host = spi_controller_get_devdata(ctlr);
> +	host->dev = dev;
> +
> +	platform_set_drvdata(pdev, host);
> +
> +	host->regbase = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(host->regbase)) {
> +		ret = PTR_ERR(host->regbase);
> +		goto err_put_master;


WARNING: multiple messages have this Message-ID (diff)
From: John Garry <john.garry@huawei.com>
To: <broonie@kernel.org>, <marek.vasut@gmail.com>,
	<tudor.ambarus@microchip.com>
Cc: chenxiang66@hisilicon.com, linux-kernel@vger.kernel.org,
	linuxarm@huawei.com, fengsheng5@huawei.com,
	linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org,
	xuejiancheng@hisilicon.com
Subject: Re: [PATCH v2 2/3] spi: Add HiSilicon v3xx SPI NOR flash controller driver
Date: Thu, 9 Jan 2020 15:54:00 +0000	[thread overview]
Message-ID: <0dc5cb2e-b765-9e13-b05e-9e3c835c5985@huawei.com> (raw)
In-Reply-To: <1575900490-74467-3-git-send-email-john.garry@huawei.com>

On 09/12/2019 14:08, John Garry wrote:
> +	if (ret)
> +		return ret;
> +
> +	if (op->data.dir == SPI_MEM_DATA_IN)
> +		hisi_sfc_v3xx_read_databuf(host, op->data.buf.in, len);
> +
> +	return 0;
> +}
> +
> +static int hisi_sfc_v3xx_exec_op(struct spi_mem *mem,
> +				 const struct spi_mem_op *op)
> +{
> +	struct hisi_sfc_v3xx_host *host;
> +	struct spi_device *spi = mem->spi;
> +	u8 chip_select = spi->chip_select;
> +
> +	host = spi_controller_get_devdata(spi->master);
> +
> +	return hisi_sfc_v3xx_generic_exec_op(host, op, chip_select);
> +}
> +
> +static const struct spi_controller_mem_ops hisi_sfc_v3xx_mem_ops = {
> +	.adjust_op_size = hisi_sfc_v3xx_adjust_op_size,
> +	.exec_op = hisi_sfc_v3xx_exec_op,
> +};
> +
> +static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct hisi_sfc_v3xx_host *host;
> +	struct spi_controller *ctlr;
> +	u32 version;
> +	int ret;
> +
> +	ctlr = spi_alloc_master(&pdev->dev, sizeof(*host));
> +	if (!ctlr)
> +		return -ENOMEM;
> +


Hi Mark,

> +	ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
> +			  SPI_TX_DUAL | SPI_TX_QUAD;

I have an issue with dual/quad support. I naively thought that setting 
these bits would give me the highest protocol available.

However, now I notice that spi_device.mode needs to be set for supported 
protocols for the slave - I'm using the generic spi mem ops to check if 
protocols are supported based on this value.

 From checking acpi_spi_add_resource() or anywhere else, I cannot see 
how SPI_RX_DUAL or the others are set for spi_device.mode. What am I 
missing? Are these just not supported yet for ACPI? Or should the 
spi-nor code not be relying on this since we should be able to get this 
info from the SPI NOR part?

Cheers,
John

> +
> +	host = spi_controller_get_devdata(ctlr);
> +	host->dev = dev;
> +
> +	platform_set_drvdata(pdev, host);
> +
> +	host->regbase = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(host->regbase)) {
> +		ret = PTR_ERR(host->regbase);
> +		goto err_put_master;


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

  reply	other threads:[~2020-01-09 15:54 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-09 14:08 [PATCH v2 0/3] HiSilicon v3xx SFC driver John Garry
2019-12-09 14:08 ` John Garry
2019-12-09 14:08 ` [PATCH v2 1/3] mtd: spi-nor: hisi-sfc: Try to provide some clarity on which SFC we are John Garry
2019-12-09 14:08   ` John Garry
2020-01-16 11:03   ` Tudor.Ambarus
2020-01-16 11:03     ` Tudor.Ambarus
2019-12-09 14:08 ` [PATCH v2 2/3] spi: Add HiSilicon v3xx SPI NOR flash controller driver John Garry
2019-12-09 14:08   ` John Garry
2020-01-09 15:54   ` John Garry [this message]
2020-01-09 15:54     ` John Garry
2020-01-09 21:28     ` Mark Brown
2020-01-09 21:28       ` Mark Brown
2020-01-10 11:55       ` John Garry
2020-01-10 11:55         ` John Garry
2020-01-10 11:55         ` John Garry
2020-01-10 14:07         ` Mark Brown
2020-01-10 14:07           ` Mark Brown
2020-01-10 14:07           ` Mark Brown
2020-01-10 14:58           ` John Garry
2020-01-10 14:58             ` John Garry
2020-01-10 15:12             ` Mark Brown
2020-01-10 15:12               ` Mark Brown
2020-01-10 16:09               ` John Garry
2020-01-10 16:09                 ` John Garry
2020-01-10 19:31             ` Andy Shevchenko
2020-01-10 19:31               ` Andy Shevchenko
2020-01-10 19:31               ` Andy Shevchenko
2020-01-13 10:09               ` John Garry
2020-01-13 10:09                 ` John Garry
2020-01-13 11:42                 ` Mark Brown
2020-01-13 11:42                   ` Mark Brown
2020-01-13 13:01                   ` John Garry
2020-01-13 13:01                     ` John Garry
2020-01-13 14:06                     ` Mark Brown
2020-01-13 14:06                       ` Mark Brown
2020-01-13 14:17                       ` Andy Shevchenko
2020-01-13 14:17                         ` Andy Shevchenko
2020-01-13 14:17                         ` Andy Shevchenko
2020-01-13 14:27                         ` Mark Brown
2020-01-13 14:27                           ` Mark Brown
2020-01-13 14:27                           ` Mark Brown
2020-01-13 14:34                           ` Andy Shevchenko
2020-01-13 14:34                             ` Andy Shevchenko
2020-01-13 14:34                             ` Andy Shevchenko
2020-01-31 10:08                             ` John Garry
2020-01-31 10:08                               ` John Garry
2020-01-31 11:39                               ` Andy Shevchenko
2020-01-31 11:39                                 ` Andy Shevchenko
2020-01-31 11:39                                 ` Andy Shevchenko
2020-01-31 12:03                                 ` John Garry
2020-01-31 12:03                                   ` John Garry
2020-01-31 12:03                                   ` John Garry
2020-01-31 15:46                                   ` Andy Shevchenko
2020-01-31 15:46                                     ` Andy Shevchenko
2020-01-31 15:46                                     ` Andy Shevchenko
2020-01-31 16:26                                     ` John Garry
2020-01-31 16:26                                       ` John Garry
2020-01-31 16:26                                       ` John Garry
2020-02-01 11:34                                       ` Mark Brown
2020-02-01 11:34                                         ` Mark Brown
2020-02-01 11:32                                     ` Mark Brown
2020-02-01 11:32                                       ` Mark Brown
2020-01-10 19:59   ` Applied "spi: Add HiSilicon v3xx SPI NOR flash controller driver" to the spi tree Mark Brown
2020-01-10 19:59     ` Mark Brown
2020-01-10 19:59     ` Mark Brown
2019-12-09 14:08 ` [PATCH v2 3/3] MAINTAINERS: Add a maintainer for the HiSilicon v3xx SFC driver John Garry
2019-12-09 14:08   ` John Garry
2020-01-10 19:59   ` Applied "MAINTAINERS: Add a maintainer for the HiSilicon v3xx SFC driver" to the spi tree Mark Brown
2020-01-10 19:59     ` Mark Brown
2020-01-10 19:59     ` Mark Brown
2019-12-16 14:52 ` [PATCH v2 0/3] HiSilicon v3xx SFC driver John Garry
2019-12-16 14:52   ` John Garry
2019-12-16 14:56   ` Mark Brown
2019-12-16 14:56     ` Mark Brown

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