From: Hal Feng <hal.feng@starfivetech.com> To: Conor Dooley <conor@kernel.org> Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Stephen Boyd <sboyd@kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, <linux-kernel@vger.kernel.org> Subject: Re: [PATCH v3 08/11] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator Date: Fri, 17 Feb 2023 01:19:20 +0800 [thread overview] Message-ID: <10c2bcb2-e8ca-572f-9e35-84bc8dbf699e@starfivetech.com> (raw) In-Reply-To: <Y6JC6PZaRMYxZG5Z@spud> On Tue, 20 Dec 2022 23:19:04 +0000, Conor Dooley wrote: > On Tue, Dec 20, 2022 at 08:50:51AM +0800, Hal Feng wrote: >> From: Emil Renner Berthing <kernel@esmil.dk> >> >> Add bindings for the always-on clock and reset generator (AONCRG) on the >> JH7110 RISC-V SoC by StarFive Ltd. >> >> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> >> --- >> .../clock/starfive,jh7110-aoncrg.yaml | 76 +++++++++++++++++++ >> .../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++++ >> .../dt-bindings/reset/starfive,jh7110-crg.h | 12 +++ >> 3 files changed, 106 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml >> >> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml >> new file mode 100644 >> index 000000000000..a3cf0570d950 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml >> @@ -0,0 +1,76 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: StarFive JH7110 Always-On Clock and Reset Generator >> + >> +maintainers: >> + - Emil Renner Berthing <kernel@esmil.dk> >> + >> +properties: >> + compatible: >> + const: starfive,jh7110-aoncrg >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: Main Oscillator (24 MHz) >> + - description: RTC Oscillator (32.768 kHz) >> + - description: GMAC0 RMII reference >> + - description: GMAC0 RGMII RX > > Gotta ask the same question here about the muxing - are all of these > clocks truly required? Please see the following clock tree. enable prepare protect duty hardware clock count count count rate accuracy phase cycle enable ------------------------------------------------------------------------------------------------------- *rtc_osc* 0 0 0 32768 0 0 50000 Y rtc_32k 0 0 0 32768 0 0 50000 Y *gmac0_rgmii_rxin* 0 0 0 125000000 0 0 50000 Y gmac0_rx 0 0 0 125000000 0 0 50000 Y gmac0_rx_inv 0 0 0 125000000 0 180 50000 Y *gmac0_rmii_refin* 0 0 0 50000000 0 0 50000 Y gmac0_rmii_rtx 0 0 0 25000000 0 0 50000 Y gmac0_tx 0 0 0 25000000 0 0 50000 N gmac0_tx_inv 0 0 0 25000000 0 180 50000 Y *osc* 3 3 0 24000000 0 0 50000 Y rtc_cal 0 0 0 24000000 0 0 50000 N rtc_internal 0 0 0 32000 0 0 50000 Y apb_func 0 0 0 24000000 0 0 50000 Y osc_div4 0 0 0 6000000 0 0 50000 Y pll2_out 2 2 0 1188000000 0 0 50000 Y bus_root 1 1 0 1188000000 0 0 50000 Y axi_cfg0 2 2 0 396000000 0 0 50000 Y *stg_axiahb* 3 3 0 198000000 0 0 50000 Y gmac0_axi 0 0 0 198000000 0 0 50000 N gmac0_ahb 0 0 0 198000000 0 0 50000 N *apb_bus* 2 2 0 49500000 0 0 50000 Y rtc_apb 0 0 0 49500000 0 0 50000 Y otpc_apb 0 0 0 49500000 0 0 50000 Y pll0_out 1 1 0 1250000000 0 0 50000 Y *gmac0_gtxclk* 0 0 0 156250000 0 0 50000 N gmac0_gtxc 0 0 0 156250000 0 0 50000 N Most input clocks are used as parent of the clocks registered in aon clock driver (patch 10) except the clock "gmac0_gtxclk". But I still think there is no harm in building a complete clock tree, so we can adjust the parent clocks easily. > >> + - description: STG AXI/AHB >> + - description: APB Bus >> + - description: GMAC0 GTX >> + >> + clock-names: >> + items: >> + - const: osc >> + - const: rtc_osc >> + - const: gmac0_rmii_refin >> + - const: gmac0_rgmii_rxin >> + - const: stg_axiahb >> + - const: apb_bus >> + - const: gmac0_gtxclk > > And if they are, is this actually needed since the order must be as > above? Will remove "clock-names" in the binding and device tree. Thanks. Best regards, Hal > > As I said in the previous patch, I've probably missed something... >
WARNING: multiple messages have this Message-ID (diff)
From: Hal Feng <hal.feng@starfivetech.com> To: Conor Dooley <conor@kernel.org> Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Stephen Boyd <sboyd@kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, <linux-kernel@vger.kernel.org> Subject: Re: [PATCH v3 08/11] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator Date: Fri, 17 Feb 2023 01:19:20 +0800 [thread overview] Message-ID: <10c2bcb2-e8ca-572f-9e35-84bc8dbf699e@starfivetech.com> (raw) In-Reply-To: <Y6JC6PZaRMYxZG5Z@spud> On Tue, 20 Dec 2022 23:19:04 +0000, Conor Dooley wrote: > On Tue, Dec 20, 2022 at 08:50:51AM +0800, Hal Feng wrote: >> From: Emil Renner Berthing <kernel@esmil.dk> >> >> Add bindings for the always-on clock and reset generator (AONCRG) on the >> JH7110 RISC-V SoC by StarFive Ltd. >> >> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> >> --- >> .../clock/starfive,jh7110-aoncrg.yaml | 76 +++++++++++++++++++ >> .../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++++ >> .../dt-bindings/reset/starfive,jh7110-crg.h | 12 +++ >> 3 files changed, 106 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml >> >> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml >> new file mode 100644 >> index 000000000000..a3cf0570d950 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml >> @@ -0,0 +1,76 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: StarFive JH7110 Always-On Clock and Reset Generator >> + >> +maintainers: >> + - Emil Renner Berthing <kernel@esmil.dk> >> + >> +properties: >> + compatible: >> + const: starfive,jh7110-aoncrg >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: Main Oscillator (24 MHz) >> + - description: RTC Oscillator (32.768 kHz) >> + - description: GMAC0 RMII reference >> + - description: GMAC0 RGMII RX > > Gotta ask the same question here about the muxing - are all of these > clocks truly required? Please see the following clock tree. enable prepare protect duty hardware clock count count count rate accuracy phase cycle enable ------------------------------------------------------------------------------------------------------- *rtc_osc* 0 0 0 32768 0 0 50000 Y rtc_32k 0 0 0 32768 0 0 50000 Y *gmac0_rgmii_rxin* 0 0 0 125000000 0 0 50000 Y gmac0_rx 0 0 0 125000000 0 0 50000 Y gmac0_rx_inv 0 0 0 125000000 0 180 50000 Y *gmac0_rmii_refin* 0 0 0 50000000 0 0 50000 Y gmac0_rmii_rtx 0 0 0 25000000 0 0 50000 Y gmac0_tx 0 0 0 25000000 0 0 50000 N gmac0_tx_inv 0 0 0 25000000 0 180 50000 Y *osc* 3 3 0 24000000 0 0 50000 Y rtc_cal 0 0 0 24000000 0 0 50000 N rtc_internal 0 0 0 32000 0 0 50000 Y apb_func 0 0 0 24000000 0 0 50000 Y osc_div4 0 0 0 6000000 0 0 50000 Y pll2_out 2 2 0 1188000000 0 0 50000 Y bus_root 1 1 0 1188000000 0 0 50000 Y axi_cfg0 2 2 0 396000000 0 0 50000 Y *stg_axiahb* 3 3 0 198000000 0 0 50000 Y gmac0_axi 0 0 0 198000000 0 0 50000 N gmac0_ahb 0 0 0 198000000 0 0 50000 N *apb_bus* 2 2 0 49500000 0 0 50000 Y rtc_apb 0 0 0 49500000 0 0 50000 Y otpc_apb 0 0 0 49500000 0 0 50000 Y pll0_out 1 1 0 1250000000 0 0 50000 Y *gmac0_gtxclk* 0 0 0 156250000 0 0 50000 N gmac0_gtxc 0 0 0 156250000 0 0 50000 N Most input clocks are used as parent of the clocks registered in aon clock driver (patch 10) except the clock "gmac0_gtxclk". But I still think there is no harm in building a complete clock tree, so we can adjust the parent clocks easily. > >> + - description: STG AXI/AHB >> + - description: APB Bus >> + - description: GMAC0 GTX >> + >> + clock-names: >> + items: >> + - const: osc >> + - const: rtc_osc >> + - const: gmac0_rmii_refin >> + - const: gmac0_rgmii_rxin >> + - const: stg_axiahb >> + - const: apb_bus >> + - const: gmac0_gtxclk > > And if they are, is this actually needed since the order must be as > above? Will remove "clock-names" in the binding and device tree. Thanks. Best regards, Hal > > As I said in the previous patch, I've probably missed something... > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-02-16 17:19 UTC|newest] Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-20 0:50 [PATCH v3 00/11] Basic clock and reset support for StarFive JH7110 RISC-V SoC Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 01/11] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 21:54 ` Conor Dooley 2022-12-20 21:54 ` Conor Dooley 2022-12-20 0:50 ` [PATCH v3 02/11] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 22:08 ` Conor Dooley 2022-12-20 22:08 ` Conor Dooley 2022-12-23 6:23 ` Hal Feng 2022-12-23 6:23 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 03/11] reset: Create subdirectory for StarFive drivers Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 22:15 ` Conor Dooley 2022-12-20 22:15 ` Conor Dooley 2022-12-23 7:02 ` Hal Feng 2022-12-23 7:02 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 04/11] reset: starfive: Factor out common JH71X0 reset code Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 22:28 ` Conor Dooley 2022-12-20 22:28 ` Conor Dooley 2022-12-23 7:49 ` Hal Feng 2022-12-23 7:49 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 05/11] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 2:40 ` kernel test robot 2022-12-20 2:40 ` kernel test robot 2022-12-20 22:31 ` Conor Dooley 2022-12-20 22:31 ` Conor Dooley 2022-12-24 3:48 ` kernel test robot 2022-12-24 3:48 ` kernel test robot 2022-12-20 0:50 ` [PATCH v3 06/11] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 22:49 ` Conor Dooley 2022-12-20 22:49 ` Conor Dooley 2022-12-20 0:50 ` [PATCH v3 07/11] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 20:12 ` Rob Herring 2022-12-20 20:12 ` Rob Herring 2022-12-20 23:14 ` Conor Dooley 2022-12-20 23:14 ` Conor Dooley 2022-12-20 23:16 ` Conor Dooley 2022-12-20 23:16 ` Conor Dooley 2022-12-25 16:26 ` Hal Feng 2022-12-25 16:26 ` Hal Feng 2022-12-27 20:15 ` Conor Dooley 2022-12-27 20:15 ` Conor Dooley 2023-02-16 14:42 ` Hal Feng 2023-02-16 14:42 ` Hal Feng 2023-02-16 18:20 ` Conor Dooley 2023-02-16 18:20 ` Conor Dooley 2023-02-17 2:27 ` Hal Feng 2023-02-17 2:27 ` Hal Feng 2023-02-17 7:51 ` Conor Dooley 2023-02-17 7:51 ` Conor Dooley 2023-02-17 12:20 ` Hal Feng 2023-02-17 12:20 ` Hal Feng 2023-02-17 13:32 ` Conor Dooley 2023-02-17 13:32 ` Conor Dooley 2023-02-17 15:47 ` Krzysztof Kozlowski 2023-02-17 15:47 ` Krzysztof Kozlowski 2023-02-17 16:27 ` Conor Dooley 2023-02-17 16:27 ` Conor Dooley 2023-02-18 10:20 ` Krzysztof Kozlowski 2023-02-18 10:20 ` Krzysztof Kozlowski 2023-02-18 11:17 ` Conor Dooley 2023-02-18 11:17 ` Conor Dooley 2023-02-18 14:55 ` Krzysztof Kozlowski 2023-02-18 14:55 ` Krzysztof Kozlowski 2023-02-18 15:08 ` Conor Dooley 2023-02-18 15:08 ` Conor Dooley 2023-02-21 22:17 ` Stephen Boyd 2023-02-21 22:17 ` Stephen Boyd 2023-02-21 23:39 ` Conor Dooley 2023-02-21 23:39 ` Conor Dooley 2023-02-22 13:27 ` Hal Feng 2023-02-22 13:27 ` Hal Feng 2023-02-22 16:26 ` Conor Dooley 2023-02-22 16:26 ` Conor Dooley 2023-02-23 3:03 ` Hal Feng 2023-02-23 3:03 ` Hal Feng 2023-02-23 6:18 ` Conor Dooley 2023-02-23 6:18 ` Conor Dooley 2023-02-23 9:52 ` Hal Feng 2023-02-23 9:52 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 08/11] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 20:14 ` Rob Herring 2022-12-20 20:14 ` Rob Herring 2022-12-20 23:19 ` Conor Dooley 2022-12-20 23:19 ` Conor Dooley 2023-02-16 17:19 ` Hal Feng [this message] 2023-02-16 17:19 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 09/11] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-23 9:57 ` kernel test robot 2022-12-23 9:57 ` kernel test robot 2023-01-05 11:32 ` kernel test robot 2023-01-05 11:32 ` kernel test robot 2023-02-19 21:23 ` Emil Renner Berthing 2023-02-19 21:23 ` Emil Renner Berthing 2023-02-21 6:44 ` Hal Feng 2023-02-21 6:44 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 10/11] clk: starfive: Add StarFive JH7110 always-on " Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-23 11:28 ` kernel test robot 2022-12-23 11:28 ` kernel test robot 2023-01-05 13:44 ` kernel test robot 2023-01-05 13:44 ` kernel test robot 2022-12-20 0:50 ` [PATCH v3 11/11] reset: starfive: Add StarFive JH7110 reset driver Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 7:14 ` kernel test robot 2022-12-20 7:14 ` kernel test robot 2022-12-23 12:39 ` kernel test robot 2022-12-23 12:39 ` kernel test robot 2022-12-27 19:20 ` kernel test robot 2022-12-27 19:20 ` kernel test robot 2023-01-05 15:35 ` kernel test robot 2023-01-05 15:35 ` kernel test robot
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