From: Hal Feng <hal.feng@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org> Cc: Conor Dooley <conor@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, "Rob Herring" <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Stephen Boyd <sboyd@kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Hal Feng <hal.feng@starfivetech.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH v3 08/11] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator Date: Tue, 20 Dec 2022 08:50:51 +0800 [thread overview] Message-ID: <20221220005054.34518-9-hal.feng@starfivetech.com> (raw) In-Reply-To: <20221220005054.34518-1-hal.feng@starfivetech.com> From: Emil Renner Berthing <kernel@esmil.dk> Add bindings for the always-on clock and reset generator (AONCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> --- .../clock/starfive,jh7110-aoncrg.yaml | 76 +++++++++++++++++++ .../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++++ .../dt-bindings/reset/starfive,jh7110-crg.h | 12 +++ 3 files changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml new file mode 100644 index 000000000000..a3cf0570d950 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Always-On Clock and Reset Generator + +maintainers: + - Emil Renner Berthing <kernel@esmil.dk> + +properties: + compatible: + const: starfive,jh7110-aoncrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: RTC Oscillator (32.768 kHz) + - description: GMAC0 RMII reference + - description: GMAC0 RGMII RX + - description: STG AXI/AHB + - description: APB Bus + - description: GMAC0 GTX + + clock-names: + items: + - const: osc + - const: rtc_osc + - const: gmac0_rmii_refin + - const: gmac0_rgmii_rxin + - const: stg_axiahb + - const: apb_bus + - const: gmac0_gtxclk + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + + clock-controller@17000000 { + compatible = "starfive,jh7110-aoncrg"; + reg = <0x17000000 0x10000>; + clocks = <&osc>, <&rtc_osc>, + <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_APB_BUS>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>; + clock-names = "osc", "rtc_osc", "gmac0_rmii_refin", + "gmac0_rgmii_rxin", "stg_axiahb", + "apb_bus", "gmac0_gtxclk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h index cda199084bcf..5e4f21ca0642 100644 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -204,4 +204,22 @@ #define JH7110_SYSCLK_END 193 +/* AONCRG clocks */ +#define JH7110_AONCLK_OSC_DIV4 0 +#define JH7110_AONCLK_APB_FUNC 1 +#define JH7110_AONCLK_GMAC0_AHB 2 +#define JH7110_AONCLK_GMAC0_AXI 3 +#define JH7110_AONCLK_GMAC0_RMII_RTX 4 +#define JH7110_AONCLK_GMAC0_TX 5 +#define JH7110_AONCLK_GMAC0_TX_INV 6 +#define JH7110_AONCLK_GMAC0_RX 7 +#define JH7110_AONCLK_GMAC0_RX_INV 8 +#define JH7110_AONCLK_OTPC_APB 9 +#define JH7110_AONCLK_RTC_APB 10 +#define JH7110_AONCLK_RTC_INTERNAL 11 +#define JH7110_AONCLK_RTC_32K 12 +#define JH7110_AONCLK_RTC_CAL 13 + +#define JH7110_AONCLK_END 14 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h index b88216a4fe40..d78e38690ceb 100644 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h @@ -139,4 +139,16 @@ #define JH7110_SYSRST_END 126 +/* AONCRG resets */ +#define JH7110_AONRST_GMAC0_AXI 0 +#define JH7110_AONRST_GMAC0_AHB 1 +#define JH7110_AONRST_IOMUX 2 +#define JH7110_AONRST_PMU_APB 3 +#define JH7110_AONRST_PMU_WKUP 4 +#define JH7110_AONRST_RTC_APB 5 +#define JH7110_AONRST_RTC_CAL 6 +#define JH7110_AONRST_RTC_32K 7 + +#define JH7110_AONRST_END 8 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ -- 2.38.1
WARNING: multiple messages have this Message-ID (diff)
From: Hal Feng <hal.feng@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org> Cc: Conor Dooley <conor@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, "Rob Herring" <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Stephen Boyd <sboyd@kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Hal Feng <hal.feng@starfivetech.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH v3 08/11] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator Date: Tue, 20 Dec 2022 08:50:51 +0800 [thread overview] Message-ID: <20221220005054.34518-9-hal.feng@starfivetech.com> (raw) In-Reply-To: <20221220005054.34518-1-hal.feng@starfivetech.com> From: Emil Renner Berthing <kernel@esmil.dk> Add bindings for the always-on clock and reset generator (AONCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> --- .../clock/starfive,jh7110-aoncrg.yaml | 76 +++++++++++++++++++ .../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++++ .../dt-bindings/reset/starfive,jh7110-crg.h | 12 +++ 3 files changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml new file mode 100644 index 000000000000..a3cf0570d950 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Always-On Clock and Reset Generator + +maintainers: + - Emil Renner Berthing <kernel@esmil.dk> + +properties: + compatible: + const: starfive,jh7110-aoncrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: RTC Oscillator (32.768 kHz) + - description: GMAC0 RMII reference + - description: GMAC0 RGMII RX + - description: STG AXI/AHB + - description: APB Bus + - description: GMAC0 GTX + + clock-names: + items: + - const: osc + - const: rtc_osc + - const: gmac0_rmii_refin + - const: gmac0_rgmii_rxin + - const: stg_axiahb + - const: apb_bus + - const: gmac0_gtxclk + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + + clock-controller@17000000 { + compatible = "starfive,jh7110-aoncrg"; + reg = <0x17000000 0x10000>; + clocks = <&osc>, <&rtc_osc>, + <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_APB_BUS>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>; + clock-names = "osc", "rtc_osc", "gmac0_rmii_refin", + "gmac0_rgmii_rxin", "stg_axiahb", + "apb_bus", "gmac0_gtxclk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h index cda199084bcf..5e4f21ca0642 100644 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -204,4 +204,22 @@ #define JH7110_SYSCLK_END 193 +/* AONCRG clocks */ +#define JH7110_AONCLK_OSC_DIV4 0 +#define JH7110_AONCLK_APB_FUNC 1 +#define JH7110_AONCLK_GMAC0_AHB 2 +#define JH7110_AONCLK_GMAC0_AXI 3 +#define JH7110_AONCLK_GMAC0_RMII_RTX 4 +#define JH7110_AONCLK_GMAC0_TX 5 +#define JH7110_AONCLK_GMAC0_TX_INV 6 +#define JH7110_AONCLK_GMAC0_RX 7 +#define JH7110_AONCLK_GMAC0_RX_INV 8 +#define JH7110_AONCLK_OTPC_APB 9 +#define JH7110_AONCLK_RTC_APB 10 +#define JH7110_AONCLK_RTC_INTERNAL 11 +#define JH7110_AONCLK_RTC_32K 12 +#define JH7110_AONCLK_RTC_CAL 13 + +#define JH7110_AONCLK_END 14 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h index b88216a4fe40..d78e38690ceb 100644 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h @@ -139,4 +139,16 @@ #define JH7110_SYSRST_END 126 +/* AONCRG resets */ +#define JH7110_AONRST_GMAC0_AXI 0 +#define JH7110_AONRST_GMAC0_AHB 1 +#define JH7110_AONRST_IOMUX 2 +#define JH7110_AONRST_PMU_APB 3 +#define JH7110_AONRST_PMU_WKUP 4 +#define JH7110_AONRST_RTC_APB 5 +#define JH7110_AONRST_RTC_CAL 6 +#define JH7110_AONRST_RTC_32K 7 + +#define JH7110_AONRST_END 8 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ -- 2.38.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-12-20 0:51 UTC|newest] Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-20 0:50 [PATCH v3 00/11] Basic clock and reset support for StarFive JH7110 RISC-V SoC Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 01/11] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 21:54 ` Conor Dooley 2022-12-20 21:54 ` Conor Dooley 2022-12-20 0:50 ` [PATCH v3 02/11] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 22:08 ` Conor Dooley 2022-12-20 22:08 ` Conor Dooley 2022-12-23 6:23 ` Hal Feng 2022-12-23 6:23 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 03/11] reset: Create subdirectory for StarFive drivers Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 22:15 ` Conor Dooley 2022-12-20 22:15 ` Conor Dooley 2022-12-23 7:02 ` Hal Feng 2022-12-23 7:02 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 04/11] reset: starfive: Factor out common JH71X0 reset code Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 22:28 ` Conor Dooley 2022-12-20 22:28 ` Conor Dooley 2022-12-23 7:49 ` Hal Feng 2022-12-23 7:49 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 05/11] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 2:40 ` kernel test robot 2022-12-20 2:40 ` kernel test robot 2022-12-20 22:31 ` Conor Dooley 2022-12-20 22:31 ` Conor Dooley 2022-12-24 3:48 ` kernel test robot 2022-12-24 3:48 ` kernel test robot 2022-12-20 0:50 ` [PATCH v3 06/11] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 22:49 ` Conor Dooley 2022-12-20 22:49 ` Conor Dooley 2022-12-20 0:50 ` [PATCH v3 07/11] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 20:12 ` Rob Herring 2022-12-20 20:12 ` Rob Herring 2022-12-20 23:14 ` Conor Dooley 2022-12-20 23:14 ` Conor Dooley 2022-12-20 23:16 ` Conor Dooley 2022-12-20 23:16 ` Conor Dooley 2022-12-25 16:26 ` Hal Feng 2022-12-25 16:26 ` Hal Feng 2022-12-27 20:15 ` Conor Dooley 2022-12-27 20:15 ` Conor Dooley 2023-02-16 14:42 ` Hal Feng 2023-02-16 14:42 ` Hal Feng 2023-02-16 18:20 ` Conor Dooley 2023-02-16 18:20 ` Conor Dooley 2023-02-17 2:27 ` Hal Feng 2023-02-17 2:27 ` Hal Feng 2023-02-17 7:51 ` Conor Dooley 2023-02-17 7:51 ` Conor Dooley 2023-02-17 12:20 ` Hal Feng 2023-02-17 12:20 ` Hal Feng 2023-02-17 13:32 ` Conor Dooley 2023-02-17 13:32 ` Conor Dooley 2023-02-17 15:47 ` Krzysztof Kozlowski 2023-02-17 15:47 ` Krzysztof Kozlowski 2023-02-17 16:27 ` Conor Dooley 2023-02-17 16:27 ` Conor Dooley 2023-02-18 10:20 ` Krzysztof Kozlowski 2023-02-18 10:20 ` Krzysztof Kozlowski 2023-02-18 11:17 ` Conor Dooley 2023-02-18 11:17 ` Conor Dooley 2023-02-18 14:55 ` Krzysztof Kozlowski 2023-02-18 14:55 ` Krzysztof Kozlowski 2023-02-18 15:08 ` Conor Dooley 2023-02-18 15:08 ` Conor Dooley 2023-02-21 22:17 ` Stephen Boyd 2023-02-21 22:17 ` Stephen Boyd 2023-02-21 23:39 ` Conor Dooley 2023-02-21 23:39 ` Conor Dooley 2023-02-22 13:27 ` Hal Feng 2023-02-22 13:27 ` Hal Feng 2023-02-22 16:26 ` Conor Dooley 2023-02-22 16:26 ` Conor Dooley 2023-02-23 3:03 ` Hal Feng 2023-02-23 3:03 ` Hal Feng 2023-02-23 6:18 ` Conor Dooley 2023-02-23 6:18 ` Conor Dooley 2023-02-23 9:52 ` Hal Feng 2023-02-23 9:52 ` Hal Feng 2022-12-20 0:50 ` Hal Feng [this message] 2022-12-20 0:50 ` [PATCH v3 08/11] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng 2022-12-20 20:14 ` Rob Herring 2022-12-20 20:14 ` Rob Herring 2022-12-20 23:19 ` Conor Dooley 2022-12-20 23:19 ` Conor Dooley 2023-02-16 17:19 ` Hal Feng 2023-02-16 17:19 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 09/11] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-23 9:57 ` kernel test robot 2022-12-23 9:57 ` kernel test robot 2023-01-05 11:32 ` kernel test robot 2023-01-05 11:32 ` kernel test robot 2023-02-19 21:23 ` Emil Renner Berthing 2023-02-19 21:23 ` Emil Renner Berthing 2023-02-21 6:44 ` Hal Feng 2023-02-21 6:44 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 10/11] clk: starfive: Add StarFive JH7110 always-on " Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-23 11:28 ` kernel test robot 2022-12-23 11:28 ` kernel test robot 2023-01-05 13:44 ` kernel test robot 2023-01-05 13:44 ` kernel test robot 2022-12-20 0:50 ` [PATCH v3 11/11] reset: starfive: Add StarFive JH7110 reset driver Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 7:14 ` kernel test robot 2022-12-20 7:14 ` kernel test robot 2022-12-23 12:39 ` kernel test robot 2022-12-23 12:39 ` kernel test robot 2022-12-27 19:20 ` kernel test robot 2022-12-27 19:20 ` kernel test robot 2023-01-05 15:35 ` kernel test robot 2023-01-05 15:35 ` kernel test robot
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