From: Hal Feng <hal.feng@starfivetech.com> To: Emil Renner Berthing <emil.renner.berthing@canonical.com> Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>, Conor Dooley <conor@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Stephen Boyd <sboyd@kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, <linux-kernel@vger.kernel.org> Subject: Re: [PATCH v3 09/11] clk: starfive: Add StarFive JH7110 system clock driver Date: Tue, 21 Feb 2023 14:44:10 +0800 [thread overview] Message-ID: <d7880fbb-ee6a-751b-4372-9d3154257c6c@starfivetech.com> (raw) In-Reply-To: <CAJM55Z-qpQkLjSFN33ELGE8DtoygY+vL6zi2raPh6POJ69pjbg@mail.gmail.com> On Sun, 19 Feb 2023 22:23:39 +0100, Emil Renner Berthing wrote: > On Tue, 20 Dec 2022 at 01:51, Hal Feng <hal.feng@starfivetech.com> wrote: >> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c >> new file mode 100644 >> index 000000000000..abc1c280bbe3 >> --- /dev/null >> +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c >> @@ -0,0 +1,448 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * StarFive JH7110 System Clock Driver [...] >> +static int __init jh7110_syscrg_probe(struct platform_device *pdev) >> +{ >> + struct jh71x0_clk_priv *priv; >> + unsigned int idx; >> + int ret; >> + >> + priv = devm_kzalloc(&pdev->dev, >> + struct_size(priv, reg, JH7110_SYSCLK_PLL0_OUT), >> + GFP_KERNEL); >> + if (!priv) >> + return -ENOMEM; >> + >> + spin_lock_init(&priv->rmw_lock); >> + priv->dev = &pdev->dev; >> + priv->base = devm_platform_ioremap_resource(pdev, 0); >> + if (IS_ERR(priv->base)) >> + return PTR_ERR(priv->base); >> + >> + dev_set_drvdata(priv->dev, priv->base); >> + >> + /* 24MHz -> 1250.0MHz */ >> + priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", >> + "osc", 0, 625, 12); >> + if (IS_ERR(priv->pll[0])) >> + return PTR_ERR(priv->pll[0]); > > Hi Hal, > > Are you sure this should be 1.25GHz and not 1GHz? I can't seem to make > the ethernet driver work unless I set it to 1GHz. This also makes > other derived clocks that should be 125MHz show up as such in the > clock tree. Eg. "usb_125m". > > Perhaps it's because I updated my board to the latest u-boot > release[1]. I know these PLLs are just placeholders until you add > proper code to control them, but until then it's important that these > values match the defaults or whatever the latest u-boot sets them to. > Please check the PLLs below with the latest u-boot too. > > /Emil > > [1]: https://github.com/starfive-tech/VisionFive2/releases After this series sent out, we found a bug in the u-boot when cpu running at 1.25 GHz, so now the cpu runs at 1GHz in the latest u-boot. I have updated it in v4. Thanks for reminding. What's more, we will support adjusting the cpu frequency in the future, so the cpu can run at a higher frequency. Best regards, Hal > >> + /* 24MHz -> 1066.0MHz */ >> + priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", >> + "osc", 0, 533, 12); >> + if (IS_ERR(priv->pll[1])) >> + return PTR_ERR(priv->pll[1]); >> + >> + /* 24MHz -> 1188.0MHz */ >> + priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", >> + "osc", 0, 99, 2); >> + if (IS_ERR(priv->pll[2])) >> + return PTR_ERR(priv->pll[2]);
WARNING: multiple messages have this Message-ID (diff)
From: Hal Feng <hal.feng@starfivetech.com> To: Emil Renner Berthing <emil.renner.berthing@canonical.com> Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>, Conor Dooley <conor@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Stephen Boyd <sboyd@kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, <linux-kernel@vger.kernel.org> Subject: Re: [PATCH v3 09/11] clk: starfive: Add StarFive JH7110 system clock driver Date: Tue, 21 Feb 2023 14:44:10 +0800 [thread overview] Message-ID: <d7880fbb-ee6a-751b-4372-9d3154257c6c@starfivetech.com> (raw) In-Reply-To: <CAJM55Z-qpQkLjSFN33ELGE8DtoygY+vL6zi2raPh6POJ69pjbg@mail.gmail.com> On Sun, 19 Feb 2023 22:23:39 +0100, Emil Renner Berthing wrote: > On Tue, 20 Dec 2022 at 01:51, Hal Feng <hal.feng@starfivetech.com> wrote: >> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c >> new file mode 100644 >> index 000000000000..abc1c280bbe3 >> --- /dev/null >> +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c >> @@ -0,0 +1,448 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * StarFive JH7110 System Clock Driver [...] >> +static int __init jh7110_syscrg_probe(struct platform_device *pdev) >> +{ >> + struct jh71x0_clk_priv *priv; >> + unsigned int idx; >> + int ret; >> + >> + priv = devm_kzalloc(&pdev->dev, >> + struct_size(priv, reg, JH7110_SYSCLK_PLL0_OUT), >> + GFP_KERNEL); >> + if (!priv) >> + return -ENOMEM; >> + >> + spin_lock_init(&priv->rmw_lock); >> + priv->dev = &pdev->dev; >> + priv->base = devm_platform_ioremap_resource(pdev, 0); >> + if (IS_ERR(priv->base)) >> + return PTR_ERR(priv->base); >> + >> + dev_set_drvdata(priv->dev, priv->base); >> + >> + /* 24MHz -> 1250.0MHz */ >> + priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", >> + "osc", 0, 625, 12); >> + if (IS_ERR(priv->pll[0])) >> + return PTR_ERR(priv->pll[0]); > > Hi Hal, > > Are you sure this should be 1.25GHz and not 1GHz? I can't seem to make > the ethernet driver work unless I set it to 1GHz. This also makes > other derived clocks that should be 125MHz show up as such in the > clock tree. Eg. "usb_125m". > > Perhaps it's because I updated my board to the latest u-boot > release[1]. I know these PLLs are just placeholders until you add > proper code to control them, but until then it's important that these > values match the defaults or whatever the latest u-boot sets them to. > Please check the PLLs below with the latest u-boot too. > > /Emil > > [1]: https://github.com/starfive-tech/VisionFive2/releases After this series sent out, we found a bug in the u-boot when cpu running at 1.25 GHz, so now the cpu runs at 1GHz in the latest u-boot. I have updated it in v4. Thanks for reminding. What's more, we will support adjusting the cpu frequency in the future, so the cpu can run at a higher frequency. Best regards, Hal > >> + /* 24MHz -> 1066.0MHz */ >> + priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", >> + "osc", 0, 533, 12); >> + if (IS_ERR(priv->pll[1])) >> + return PTR_ERR(priv->pll[1]); >> + >> + /* 24MHz -> 1188.0MHz */ >> + priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", >> + "osc", 0, 99, 2); >> + if (IS_ERR(priv->pll[2])) >> + return PTR_ERR(priv->pll[2]); _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-02-21 6:44 UTC|newest] Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-20 0:50 [PATCH v3 00/11] Basic clock and reset support for StarFive JH7110 RISC-V SoC Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 01/11] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 21:54 ` Conor Dooley 2022-12-20 21:54 ` Conor Dooley 2022-12-20 0:50 ` [PATCH v3 02/11] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 22:08 ` Conor Dooley 2022-12-20 22:08 ` Conor Dooley 2022-12-23 6:23 ` Hal Feng 2022-12-23 6:23 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 03/11] reset: Create subdirectory for StarFive drivers Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 22:15 ` Conor Dooley 2022-12-20 22:15 ` Conor Dooley 2022-12-23 7:02 ` Hal Feng 2022-12-23 7:02 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 04/11] reset: starfive: Factor out common JH71X0 reset code Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 22:28 ` Conor Dooley 2022-12-20 22:28 ` Conor Dooley 2022-12-23 7:49 ` Hal Feng 2022-12-23 7:49 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 05/11] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 2:40 ` kernel test robot 2022-12-20 2:40 ` kernel test robot 2022-12-20 22:31 ` Conor Dooley 2022-12-20 22:31 ` Conor Dooley 2022-12-24 3:48 ` kernel test robot 2022-12-24 3:48 ` kernel test robot 2022-12-20 0:50 ` [PATCH v3 06/11] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 22:49 ` Conor Dooley 2022-12-20 22:49 ` Conor Dooley 2022-12-20 0:50 ` [PATCH v3 07/11] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 20:12 ` Rob Herring 2022-12-20 20:12 ` Rob Herring 2022-12-20 23:14 ` Conor Dooley 2022-12-20 23:14 ` Conor Dooley 2022-12-20 23:16 ` Conor Dooley 2022-12-20 23:16 ` Conor Dooley 2022-12-25 16:26 ` Hal Feng 2022-12-25 16:26 ` Hal Feng 2022-12-27 20:15 ` Conor Dooley 2022-12-27 20:15 ` Conor Dooley 2023-02-16 14:42 ` Hal Feng 2023-02-16 14:42 ` Hal Feng 2023-02-16 18:20 ` Conor Dooley 2023-02-16 18:20 ` Conor Dooley 2023-02-17 2:27 ` Hal Feng 2023-02-17 2:27 ` Hal Feng 2023-02-17 7:51 ` Conor Dooley 2023-02-17 7:51 ` Conor Dooley 2023-02-17 12:20 ` Hal Feng 2023-02-17 12:20 ` Hal Feng 2023-02-17 13:32 ` Conor Dooley 2023-02-17 13:32 ` Conor Dooley 2023-02-17 15:47 ` Krzysztof Kozlowski 2023-02-17 15:47 ` Krzysztof Kozlowski 2023-02-17 16:27 ` Conor Dooley 2023-02-17 16:27 ` Conor Dooley 2023-02-18 10:20 ` Krzysztof Kozlowski 2023-02-18 10:20 ` Krzysztof Kozlowski 2023-02-18 11:17 ` Conor Dooley 2023-02-18 11:17 ` Conor Dooley 2023-02-18 14:55 ` Krzysztof Kozlowski 2023-02-18 14:55 ` Krzysztof Kozlowski 2023-02-18 15:08 ` Conor Dooley 2023-02-18 15:08 ` Conor Dooley 2023-02-21 22:17 ` Stephen Boyd 2023-02-21 22:17 ` Stephen Boyd 2023-02-21 23:39 ` Conor Dooley 2023-02-21 23:39 ` Conor Dooley 2023-02-22 13:27 ` Hal Feng 2023-02-22 13:27 ` Hal Feng 2023-02-22 16:26 ` Conor Dooley 2023-02-22 16:26 ` Conor Dooley 2023-02-23 3:03 ` Hal Feng 2023-02-23 3:03 ` Hal Feng 2023-02-23 6:18 ` Conor Dooley 2023-02-23 6:18 ` Conor Dooley 2023-02-23 9:52 ` Hal Feng 2023-02-23 9:52 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 08/11] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 20:14 ` Rob Herring 2022-12-20 20:14 ` Rob Herring 2022-12-20 23:19 ` Conor Dooley 2022-12-20 23:19 ` Conor Dooley 2023-02-16 17:19 ` Hal Feng 2023-02-16 17:19 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 09/11] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-23 9:57 ` kernel test robot 2022-12-23 9:57 ` kernel test robot 2023-01-05 11:32 ` kernel test robot 2023-01-05 11:32 ` kernel test robot 2023-02-19 21:23 ` Emil Renner Berthing 2023-02-19 21:23 ` Emil Renner Berthing 2023-02-21 6:44 ` Hal Feng [this message] 2023-02-21 6:44 ` Hal Feng 2022-12-20 0:50 ` [PATCH v3 10/11] clk: starfive: Add StarFive JH7110 always-on " Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-23 11:28 ` kernel test robot 2022-12-23 11:28 ` kernel test robot 2023-01-05 13:44 ` kernel test robot 2023-01-05 13:44 ` kernel test robot 2022-12-20 0:50 ` [PATCH v3 11/11] reset: starfive: Add StarFive JH7110 reset driver Hal Feng 2022-12-20 0:50 ` Hal Feng 2022-12-20 7:14 ` kernel test robot 2022-12-20 7:14 ` kernel test robot 2022-12-23 12:39 ` kernel test robot 2022-12-23 12:39 ` kernel test robot 2022-12-27 19:20 ` kernel test robot 2022-12-27 19:20 ` kernel test robot 2023-01-05 15:35 ` kernel test robot 2023-01-05 15:35 ` kernel test robot
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