From: Alexey Gerasimenko <x1917x@gmail.com>
To: xen-devel@lists.xenproject.org
Cc: Alexey Gerasimenko <x1917x@gmail.com>,
qemu-devel@nongnu.org,
Stefano Stabellini <sstabellini@kernel.org>,
Anthony Perard <anthony.perard@citrix.com>
Subject: [Qemu-devel] [RFC PATCH 26/30] xen/pt: add fixed-size PCIe Extended Capabilities descriptors
Date: Tue, 13 Mar 2018 04:34:11 +1000 [thread overview]
Message-ID: <1251abd57b81696c15e5d8effe224f7497f59418.1520867956.git.x1917x@gmail.com> (raw)
In-Reply-To: <cover.1520867740.git.x1917x@gmail.com>
In-Reply-To: <cover.1520867740.git.x1917x@gmail.com>
This adds description structures for all fixed-size PCIe Extended
Capabilities.
For every capability register group, only 2 registers are emulated
currently: Capability ID (16 bit) and Next Capability Offset/Version (16
bit). Both needed to implement selective capability hiding. All other
registers are passed through at the moment (unless they belong to
a "hardwired" capability which is hidden)
Signed-off-by: Alexey Gerasimenko <x1917x@gmail.com>
---
hw/xen/xen_pt_config_init.c | 183 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 183 insertions(+)
diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c
index 6e99b9ebd7..42296c08cc 100644
--- a/hw/xen/xen_pt_config_init.c
+++ b/hw/xen/xen_pt_config_init.c
@@ -1734,6 +1734,37 @@ static XenPTRegInfo xen_pt_ext_cap_emu_reg_vendor[] = {
};
+/* Common reg static information table for all passthru-type
+ * PCIe Extended Capabilities. Only Extended Cap ID and
+ * Next pointer are handled (to support capability hiding).
+ */
+static XenPTRegInfo xen_pt_ext_cap_emu_reg_dummy[] = {
+ {
+ .offset = XEN_PCIE_CAP_ID,
+ .size = 2,
+ .init_val = 0x0000,
+ .ro_mask = 0xFFFF,
+ .emu_mask = 0xFFFF,
+ .init = xen_pt_ext_cap_capid_reg_init,
+ .u.w.read = xen_pt_word_reg_read,
+ .u.w.write = xen_pt_word_reg_write,
+ },
+ {
+ .offset = XEN_PCIE_CAP_LIST_NEXT,
+ .size = 2,
+ .init_val = 0x0000,
+ .ro_mask = 0xFFFF,
+ .emu_mask = 0xFFFF,
+ .init = xen_pt_ext_cap_ptr_reg_init,
+ .u.w.read = xen_pt_word_reg_read,
+ .u.w.write = xen_pt_word_reg_write,
+ },
+ {
+ .size = 0,
+ },
+};
+
+
/****************************
* Capabilities
*/
@@ -2009,6 +2040,158 @@ static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = {
.size_init = xen_pt_ext_cap_vendor_size_init,
.emu_regs = xen_pt_ext_cap_emu_reg_vendor,
},
+ /* Device Serial Number Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_DSN),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_DSN_SIZEOF, /*0x0C*/
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Power Budgeting Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_PWR),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_PWR_SIZEOF, /*0x10*/
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Root Complex Internal Link Control Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_RCILC),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x0C,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Root Complex Event Collector Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_RCEC),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x08,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Root Complex Register Block Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_RCRB),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x14,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Configuration Access Correlation Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_CAC),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x08,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Alternate Routing ID Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_ARI),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_ARI_SIZEOF,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Address Translation Services Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_ATS),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_ATS_SIZEOF,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Single Root I/O Virtualization Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_SRIOV),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_SRIOV_SIZEOF,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Page Request Interface Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_PRI),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_PRI_SIZEOF,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Latency Tolerance Reporting Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_LTR),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_LTR_SIZEOF,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Secondary PCIe Capability Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_SECPCI),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x10,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Process Address Space ID Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_PASID),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_PASID_SIZEOF,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* L1 PM Substates Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_L1SS),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x10,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Precision Time Measurement Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_PTM),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x0C,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* M-PCIe Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(0x20),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x1C,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* LN Requester (LNR) Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(0x1C),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x08,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Function Readiness Status (FRS) Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(0x21),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x10,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Readiness Time Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(0x22),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x0C,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
{
.grp_size = 0,
},
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: Alexey Gerasimenko <x1917x@gmail.com>
To: xen-devel@lists.xenproject.org
Cc: Anthony Perard <anthony.perard@citrix.com>,
Stefano Stabellini <sstabellini@kernel.org>,
Alexey Gerasimenko <x1917x@gmail.com>,
qemu-devel@nongnu.org
Subject: [RFC PATCH 26/30] xen/pt: add fixed-size PCIe Extended Capabilities descriptors
Date: Tue, 13 Mar 2018 04:34:11 +1000 [thread overview]
Message-ID: <1251abd57b81696c15e5d8effe224f7497f59418.1520867956.git.x1917x@gmail.com> (raw)
In-Reply-To: <cover.1520867740.git.x1917x@gmail.com>
In-Reply-To: <cover.1520867740.git.x1917x@gmail.com>
This adds description structures for all fixed-size PCIe Extended
Capabilities.
For every capability register group, only 2 registers are emulated
currently: Capability ID (16 bit) and Next Capability Offset/Version (16
bit). Both needed to implement selective capability hiding. All other
registers are passed through at the moment (unless they belong to
a "hardwired" capability which is hidden)
Signed-off-by: Alexey Gerasimenko <x1917x@gmail.com>
---
hw/xen/xen_pt_config_init.c | 183 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 183 insertions(+)
diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c
index 6e99b9ebd7..42296c08cc 100644
--- a/hw/xen/xen_pt_config_init.c
+++ b/hw/xen/xen_pt_config_init.c
@@ -1734,6 +1734,37 @@ static XenPTRegInfo xen_pt_ext_cap_emu_reg_vendor[] = {
};
+/* Common reg static information table for all passthru-type
+ * PCIe Extended Capabilities. Only Extended Cap ID and
+ * Next pointer are handled (to support capability hiding).
+ */
+static XenPTRegInfo xen_pt_ext_cap_emu_reg_dummy[] = {
+ {
+ .offset = XEN_PCIE_CAP_ID,
+ .size = 2,
+ .init_val = 0x0000,
+ .ro_mask = 0xFFFF,
+ .emu_mask = 0xFFFF,
+ .init = xen_pt_ext_cap_capid_reg_init,
+ .u.w.read = xen_pt_word_reg_read,
+ .u.w.write = xen_pt_word_reg_write,
+ },
+ {
+ .offset = XEN_PCIE_CAP_LIST_NEXT,
+ .size = 2,
+ .init_val = 0x0000,
+ .ro_mask = 0xFFFF,
+ .emu_mask = 0xFFFF,
+ .init = xen_pt_ext_cap_ptr_reg_init,
+ .u.w.read = xen_pt_word_reg_read,
+ .u.w.write = xen_pt_word_reg_write,
+ },
+ {
+ .size = 0,
+ },
+};
+
+
/****************************
* Capabilities
*/
@@ -2009,6 +2040,158 @@ static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = {
.size_init = xen_pt_ext_cap_vendor_size_init,
.emu_regs = xen_pt_ext_cap_emu_reg_vendor,
},
+ /* Device Serial Number Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_DSN),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_DSN_SIZEOF, /*0x0C*/
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Power Budgeting Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_PWR),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_PWR_SIZEOF, /*0x10*/
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Root Complex Internal Link Control Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_RCILC),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x0C,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Root Complex Event Collector Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_RCEC),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x08,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Root Complex Register Block Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_RCRB),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x14,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Configuration Access Correlation Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_CAC),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x08,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Alternate Routing ID Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_ARI),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_ARI_SIZEOF,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Address Translation Services Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_ATS),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_ATS_SIZEOF,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Single Root I/O Virtualization Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_SRIOV),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_SRIOV_SIZEOF,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Page Request Interface Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_PRI),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_PRI_SIZEOF,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Latency Tolerance Reporting Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_LTR),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_LTR_SIZEOF,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Secondary PCIe Capability Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_SECPCI),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x10,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Process Address Space ID Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_PASID),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = PCI_EXT_CAP_PASID_SIZEOF,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* L1 PM Substates Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_L1SS),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x10,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Precision Time Measurement Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_PTM),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x0C,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* M-PCIe Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(0x20),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x1C,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* LN Requester (LNR) Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(0x1C),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x08,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Function Readiness Status (FRS) Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(0x21),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x10,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
+ /* Readiness Time Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(0x22),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0x0C,
+ .size_init = xen_pt_reg_grp_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_dummy,
+ },
{
.grp_size = 0,
},
--
2.11.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
next prev parent reply other threads:[~2018-03-12 18:36 UTC|newest]
Thread overview: 183+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-12 18:33 [Qemu-devel] [RFC PATCH 00/30] Xen Q35 Bringup patches + support for PCIe Extended Capabilities for passed through devices Alexey Gerasimenko
2018-03-12 18:33 ` Alexey Gerasimenko
2018-03-12 18:33 ` [RFC PATCH 01/12] libacpi: new DSDT ACPI table for Q35 Alexey Gerasimenko
2018-03-12 19:38 ` Konrad Rzeszutek Wilk
2018-03-12 20:10 ` Alexey G
2018-03-12 20:32 ` Konrad Rzeszutek Wilk
2018-03-12 21:19 ` Alexey G
2018-03-13 2:41 ` Tian, Kevin
2018-03-19 12:43 ` Roger Pau Monné
2018-03-19 13:57 ` Alexey G
2018-03-12 18:33 ` [RFC PATCH 02/12] Makefile: build and use new DSDT " Alexey Gerasimenko
2018-03-19 12:46 ` Roger Pau Monné
2018-03-19 14:18 ` Alexey G
2018-03-19 13:07 ` Jan Beulich
2018-03-19 14:10 ` Alexey G
2018-03-12 18:33 ` [RFC PATCH 03/12] hvmloader: add function to query an emulated machine type (i440/Q35) Alexey Gerasimenko
2018-03-13 17:26 ` Wei Liu
2018-03-13 17:58 ` Alexey G
2018-03-13 18:04 ` Wei Liu
2018-03-19 12:56 ` Roger Pau Monné
2018-03-19 16:26 ` Alexey G
2018-03-12 18:33 ` [RFC PATCH 04/12] hvmloader: add ACPI enabling for Q35 Alexey Gerasimenko
2018-03-13 17:26 ` Wei Liu
2018-03-19 13:01 ` Roger Pau Monné
2018-03-19 23:59 ` Alexey G
2018-03-12 18:33 ` [RFC PATCH 05/12] hvmloader: add Q35 DSDT table loading Alexey Gerasimenko
2018-03-19 14:45 ` Roger Pau Monné
2018-03-20 0:15 ` Alexey G
2018-03-12 18:33 ` [RFC PATCH 06/12] hvmloader: add basic Q35 support Alexey Gerasimenko
2018-03-19 15:30 ` Roger Pau Monné
2018-03-19 23:44 ` Alexey G
2018-03-20 9:20 ` Roger Pau Monné
2018-03-20 21:23 ` Alexey G
2018-03-12 18:33 ` [RFC PATCH 07/12] hvmloader: allocate MMCONFIG area in the MMIO hole + minor code refactoring Alexey Gerasimenko
2018-03-19 15:58 ` Roger Pau Monné
2018-03-19 19:49 ` Alexey G
2018-03-20 8:50 ` Roger Pau Monné
2018-03-20 9:25 ` Paul Durrant
2018-03-21 0:58 ` Alexey G
2018-03-21 9:09 ` Roger Pau Monné
2018-03-21 9:36 ` Paul Durrant
2018-03-21 14:35 ` Alexey G
2018-03-21 14:58 ` Paul Durrant
2018-03-21 14:25 ` Alexey G
2018-03-21 14:54 ` Paul Durrant
2018-03-21 17:41 ` Alexey G
2018-03-21 15:20 ` Roger Pau Monné
2018-03-21 16:56 ` Alexey G
2018-03-21 17:06 ` Paul Durrant
2018-03-22 0:31 ` Alexey G
2018-03-22 9:04 ` Jan Beulich
2018-03-22 9:55 ` Alexey G
2018-03-22 10:06 ` Paul Durrant
2018-03-22 11:56 ` Alexey G
2018-03-22 12:09 ` Jan Beulich
2018-03-22 13:05 ` Alexey G
2018-03-22 13:20 ` Jan Beulich
2018-03-22 14:34 ` Alexey G
2018-03-22 14:42 ` Jan Beulich
2018-03-22 15:08 ` Alexey G
2018-03-23 13:57 ` Paul Durrant
2018-03-23 22:32 ` Alexey G
2018-03-26 9:24 ` Roger Pau Monné
2018-03-26 19:42 ` Alexey G
2018-03-27 8:45 ` Roger Pau Monné
2018-03-27 15:37 ` Alexey G
2018-03-28 9:30 ` Roger Pau Monné
2018-03-28 11:42 ` Alexey G
2018-03-28 12:05 ` Paul Durrant
2018-03-28 10:03 ` Paul Durrant
2018-03-28 14:14 ` Alexey G
2018-03-21 17:15 ` Roger Pau Monné
2018-03-21 22:49 ` Alexey G
2018-03-22 9:29 ` Paul Durrant
2018-03-22 10:05 ` Roger Pau Monné
2018-03-22 10:09 ` Paul Durrant
2018-03-22 11:36 ` Alexey G
2018-03-22 10:50 ` Alexey G
2018-03-22 9:57 ` Roger Pau Monné
2018-03-22 12:29 ` Alexey G
2018-03-22 12:44 ` Roger Pau Monné
2018-03-22 15:31 ` Alexey G
2018-03-23 10:29 ` Paul Durrant
2018-03-23 11:38 ` Jan Beulich
2018-03-23 13:52 ` Paul Durrant
2018-05-29 14:23 ` Jan Beulich
2018-05-29 17:56 ` Alexey G
2018-05-29 18:47 ` Alexey G
2018-05-30 4:32 ` Alexey G
2018-05-30 8:13 ` Jan Beulich
2018-05-31 4:25 ` Alexey G
2018-05-30 8:12 ` Jan Beulich
2018-05-31 5:15 ` Alexey G
2018-06-01 5:30 ` Jan Beulich
2018-06-01 15:53 ` Alexey G
2018-03-12 18:33 ` [RFC PATCH 08/12] libxl: Q35 support (new option device_model_machine) Alexey Gerasimenko
2018-03-13 17:25 ` Wei Liu
2018-03-13 17:32 ` Anthony PERARD
2018-03-19 17:01 ` Roger Pau Monné
2018-03-19 22:11 ` Alexey G
2018-03-20 9:11 ` Roger Pau Monné
2018-03-21 16:27 ` Wei Liu
2018-03-21 17:03 ` Anthony PERARD
2018-03-21 16:25 ` Wei Liu
2018-03-12 18:33 ` [RFC PATCH 09/12] libxl: Xen Platform device support for Q35 Alexey Gerasimenko
2018-03-19 15:05 ` Alexey G
2018-03-21 16:32 ` Wei Liu
2018-03-12 18:33 ` [RFC PATCH 10/12] libacpi: build ACPI MCFG table if requested Alexey Gerasimenko
2018-03-19 17:33 ` Roger Pau Monné
2018-03-19 21:46 ` Alexey G
2018-03-20 9:03 ` Roger Pau Monné
2018-03-20 21:06 ` Alexey G
2018-05-29 14:36 ` Jan Beulich
2018-05-29 18:20 ` Alexey G
2018-03-12 18:33 ` [RFC PATCH 11/12] hvmloader: use libacpi to build MCFG table Alexey Gerasimenko
2018-03-14 17:48 ` Alexey G
2018-03-19 17:49 ` Roger Pau Monné
2018-03-19 21:20 ` Alexey G
2018-03-20 8:58 ` Roger Pau Monné
2018-03-20 9:36 ` Jan Beulich
2018-03-20 20:53 ` Alexey G
2018-03-21 7:36 ` Jan Beulich
2018-05-29 14:46 ` Jan Beulich
2018-05-29 17:26 ` Alexey G
2018-03-12 18:33 ` [RFC PATCH 12/12] docs: provide description for device_model_machine option Alexey Gerasimenko
2018-03-12 18:33 ` [Qemu-devel] [RFC PATCH 13/30] pc/xen: Xen Q35 support: provide IRQ handling for PCI devices Alexey Gerasimenko
2018-03-12 18:33 ` Alexey Gerasimenko
2018-03-14 10:48 ` [Qemu-devel] " Paolo Bonzini
2018-03-14 11:28 ` Alexey G
2018-03-14 11:28 ` Alexey G
2018-03-14 10:48 ` Paolo Bonzini
2018-03-12 18:33 ` [Qemu-devel] [RFC PATCH 14/30] pc/q35: Apply PCI bus BSEL property for Xen PCI device hotplug Alexey Gerasimenko
2018-03-12 18:33 ` Alexey Gerasimenko
2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 15/30] q35/acpi/xen: Provide ACPI PCI hotplug interface for Xen on Q35 Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko
2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 16/30] q35/xen: Add Xen platform device support for Q35 Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko
2018-03-12 19:44 ` [Qemu-devel] " Eduardo Habkost
2018-03-12 20:56 ` Alexey G
2018-03-12 20:56 ` Alexey G
2018-03-12 21:44 ` Eduardo Habkost
2018-03-12 21:44 ` [Qemu-devel] " Eduardo Habkost
2018-03-13 23:49 ` Alexey G
2018-03-13 23:49 ` Alexey G
2018-03-12 19:44 ` Eduardo Habkost
2018-03-13 9:24 ` [Qemu-devel] " Daniel P. Berrangé
2018-03-13 9:24 ` Daniel P. Berrangé
2018-03-12 18:34 ` [RFC PATCH 17/30] q35: Fix incorrect values for PCIEXBAR masks Alexey Gerasimenko
2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 18/30] xen/pt: XenHostPCIDevice: provide functions for PCI Capabilities and PCIe Extended Capabilities enumeration Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko
2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 19/30] xen/pt: avoid reading PCIe device type and cap version multiple times Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko
2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 20/30] xen/pt: determine the legacy/PCIe mode for a passed through device Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko
2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 21/30] xen/pt: Xen PCIe passthrough support for Q35: bypass PCIe topology check Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko
2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 22/30] xen/pt: add support for PCIe Extended Capabilities and larger config space Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko
2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 23/30] xen/pt: handle PCIe Extended Capabilities Next register Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko
2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 24/30] xen/pt: allow to hide PCIe Extended Capabilities Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko
2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 25/30] xen/pt: add Vendor-specific PCIe Extended Capability descriptor and sizing Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko [this message]
2018-03-12 18:34 ` [RFC PATCH 26/30] xen/pt: add fixed-size PCIe Extended Capabilities descriptors Alexey Gerasimenko
2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 27/30] xen/pt: add AER PCIe Extended Capability descriptor and sizing Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko
2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 28/30] xen/pt: add descriptors and size calculation for RCLD/ACS/PMUX/DPA/MCAST/TPH/DPC PCIe Extended Capabilities Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko
2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 29/30] xen/pt: add Resizable BAR PCIe Extended Capability descriptor and sizing Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko
2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 30/30] xen/pt: add VC/VC9/MFVC PCIe Extended Capabilities descriptors " Alexey Gerasimenko
2018-03-12 18:34 ` Alexey Gerasimenko
2018-03-13 9:21 ` [Qemu-devel] [RFC PATCH 00/30] Xen Q35 Bringup patches + support for PCIe Extended Capabilities for passed through devices Daniel P. Berrangé
2018-03-13 9:21 ` Daniel P. Berrangé
2018-03-13 11:37 ` Alexey G
2018-03-13 11:37 ` Alexey G
2018-03-13 11:44 ` Daniel P. Berrangé
2018-03-13 11:44 ` Daniel P. Berrangé
2018-03-16 17:34 ` Alexey G
2018-03-16 18:26 ` Stefano Stabellini
2018-03-16 18:36 ` Roger Pau Monné
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1251abd57b81696c15e5d8effe224f7497f59418.1520867956.git.x1917x@gmail.com \
--to=x1917x@gmail.com \
--cc=anthony.perard@citrix.com \
--cc=qemu-devel@nongnu.org \
--cc=sstabellini@kernel.org \
--cc=xen-devel@lists.xenproject.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.