From: Alexey Gerasimenko <x1917x@gmail.com> To: xen-devel@lists.xenproject.org Cc: Alexey Gerasimenko <x1917x@gmail.com>, qemu-devel@nongnu.org, Stefano Stabellini <sstabellini@kernel.org>, Anthony Perard <anthony.perard@citrix.com> Subject: [Qemu-devel] [RFC PATCH 28/30] xen/pt: add descriptors and size calculation for RCLD/ACS/PMUX/DPA/MCAST/TPH/DPC PCIe Extended Capabilities Date: Tue, 13 Mar 2018 04:34:13 +1000 [thread overview] Message-ID: <1253d9d553ef8d73af6f5c659f6756402ca28b06.1520867956.git.x1917x@gmail.com> (raw) In-Reply-To: <cover.1520867740.git.x1917x@gmail.com> In-Reply-To: <cover.1520867740.git.x1917x@gmail.com> Add few more PCIe Extended Capabilities entries to the xen_pt_emu_reg_grps[] array along with their corresponding *_size_init() functions. All these capabilities have non-fixed size but their size calculation is very simple, hence adding them in a single batch. For every capability register group, only 2 registers are emulated currently: Capability ID (16 bit) and Next Capability Offset/Version (16 bit). Both needed to implement the selective capability hiding. All other registers are passed through at the moment (unless they belong to a capability marked as "hardwired" which is hidden) Signed-off-by: Alexey Gerasimenko <x1917x@gmail.com> --- hw/xen/xen_pt_config_init.c | 224 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 224 insertions(+) diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c index 98aae3daca..326f5671ff 100644 --- a/hw/xen/xen_pt_config_init.c +++ b/hw/xen/xen_pt_config_init.c @@ -1988,6 +1988,174 @@ static int xen_pt_ext_cap_aer_size_init(XenPCIPassthroughState *s, return ret; } +/* get Root Complex Link Declaration Extended Capability register group size */ +#define RCLD_GET_NUM_ENTRIES(x) (((x) >> 8) & 0xFF) +static int xen_pt_ext_cap_rcld_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint32_t elem_self_descr = 0; + + int ret = xen_host_pci_get_long(&s->real_device, + base_offset + 4, + &elem_self_descr); + + *size = 0x10 + RCLD_GET_NUM_ENTRIES(elem_self_descr) * 0x10; + + log_pcie_extended_cap(s, "Root Complex Link Declaration", + base_offset, *size); + return ret; +} + +/* get Access Control Services Extended Capability register group size */ +#define ACS_VECTOR_SIZE_BITS(x) ((((x) >> 8) & 0xFF) ?: 256) +static int xen_pt_ext_cap_acs_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint16_t acs_caps = 0; + + int ret = xen_host_pci_get_word(&s->real_device, + base_offset + PCI_ACS_CAP, + &acs_caps); + + if (acs_caps & PCI_ACS_EC) { + uint32_t vector_sz = ACS_VECTOR_SIZE_BITS(acs_caps); + + *size = PCI_ACS_EGRESS_CTL_V + ((vector_sz + 7) & ~7) / 8; + } else { + *size = PCI_ACS_EGRESS_CTL_V; + } + + log_pcie_extended_cap(s, "ACS", base_offset, *size); + return ret; +} + +/* get Multicast Extended Capability register group size */ +static int xen_pt_ext_cap_multicast_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint8_t dev_type = get_pcie_device_type(s); + + switch (dev_type) { + case PCI_EXP_TYPE_ENDPOINT: + case PCI_EXP_TYPE_LEG_END: + case PCI_EXP_TYPE_RC_END: + case PCI_EXP_TYPE_RC_EC: + default: + *size = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF; + break; + + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_UPSTREAM: + case PCI_EXP_TYPE_DOWNSTREAM: + *size = 0x30; + break; + } + + log_pcie_extended_cap(s, "Multicast", base_offset, *size); + return 0; +} + +/* get Dynamic Power Allocation Extended Capability register group size */ +static int xen_pt_ext_cap_dpa_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint32_t dpa_caps = 0; + uint32_t num_entries; + + int ret = xen_host_pci_get_long(&s->real_device, + base_offset + PCI_DPA_CAP, + &dpa_caps); + + num_entries = (dpa_caps & PCI_DPA_CAP_SUBSTATE_MASK) + 1; + + *size = PCI_DPA_BASE_SIZEOF + num_entries /*byte-size registers*/; + + log_pcie_extended_cap(s, "Dynamic Power Allocation", base_offset, *size); + return ret; +} + +/* get TPH Requester Extended Capability register group size */ +static int xen_pt_ext_cap_tph_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint32_t tph_caps = 0; + uint32_t num_entries; + + int ret = xen_host_pci_get_long(&s->real_device, + base_offset + PCI_TPH_CAP, + &tph_caps); + + switch(tph_caps & PCI_TPH_CAP_LOC_MASK) { + case PCI_TPH_LOC_CAP: + num_entries = (tph_caps & PCI_TPH_CAP_ST_MASK) >> PCI_TPH_CAP_ST_SHIFT; + num_entries++; + break; + + case PCI_TPH_LOC_NONE: + case PCI_TPH_LOC_MSIX: + default: + /* not in the capability */ + num_entries = 0; + } + + *size = PCI_TPH_BASE_SIZEOF + num_entries * 2; + + log_pcie_extended_cap(s, "TPH Requester", base_offset, *size); + return ret; +} + +/* get Downstream Port Containment Extended Capability register group size */ +static int xen_pt_ext_cap_dpc_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint16_t dpc_caps = 0; + + int ret = xen_host_pci_get_word(&s->real_device, + base_offset + PCI_EXP_DPC_CAP, + &dpc_caps); + + if (dpc_caps & PCI_EXP_DPC_CAP_RP_EXT) { + *size = 0x20 + ((dpc_caps & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8) * 4; + } else { + *size = 0xC; + } + + log_pcie_extended_cap(s, "Downstream Port Containment", + base_offset, *size); + return ret; +} + +/* get Protocol Multiplexing Extended Capability register group size */ +#define PMUX_GET_NUM_ENTRIES(x) ((x) & 0x3F) +static int xen_pt_ext_cap_pmux_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint32_t pmux_caps = 0; + + int ret = xen_host_pci_get_long(&s->real_device, + base_offset + 4, + &pmux_caps); + + *size = 0x10 + PMUX_GET_NUM_ENTRIES(pmux_caps) * 4; + + log_pcie_extended_cap(s, "PMUX", base_offset, *size); + return ret; +} + static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = { /* Header Type0 reg group */ @@ -2264,6 +2432,62 @@ static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = { .size_init = xen_pt_ext_cap_aer_size_init, .emu_regs = xen_pt_ext_cap_emu_reg_dummy, }, + /* Root Complex Link Declaration Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_RCLD), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_rcld_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Access Control Services Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_ACS), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_acs_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Multicast Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_MCAST), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_multicast_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Dynamic Power Allocation Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_DPA), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_dpa_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* TPH Requester Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_TPH), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_tph_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Protocol Multiplexing Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_PMUX), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_pmux_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Downstream Port Containment Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_DPC), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_dpc_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, { .grp_size = 0, }, -- 2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: Alexey Gerasimenko <x1917x@gmail.com> To: xen-devel@lists.xenproject.org Cc: Anthony Perard <anthony.perard@citrix.com>, Stefano Stabellini <sstabellini@kernel.org>, Alexey Gerasimenko <x1917x@gmail.com>, qemu-devel@nongnu.org Subject: [RFC PATCH 28/30] xen/pt: add descriptors and size calculation for RCLD/ACS/PMUX/DPA/MCAST/TPH/DPC PCIe Extended Capabilities Date: Tue, 13 Mar 2018 04:34:13 +1000 [thread overview] Message-ID: <1253d9d553ef8d73af6f5c659f6756402ca28b06.1520867956.git.x1917x@gmail.com> (raw) In-Reply-To: <cover.1520867740.git.x1917x@gmail.com> In-Reply-To: <cover.1520867740.git.x1917x@gmail.com> Add few more PCIe Extended Capabilities entries to the xen_pt_emu_reg_grps[] array along with their corresponding *_size_init() functions. All these capabilities have non-fixed size but their size calculation is very simple, hence adding them in a single batch. For every capability register group, only 2 registers are emulated currently: Capability ID (16 bit) and Next Capability Offset/Version (16 bit). Both needed to implement the selective capability hiding. All other registers are passed through at the moment (unless they belong to a capability marked as "hardwired" which is hidden) Signed-off-by: Alexey Gerasimenko <x1917x@gmail.com> --- hw/xen/xen_pt_config_init.c | 224 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 224 insertions(+) diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c index 98aae3daca..326f5671ff 100644 --- a/hw/xen/xen_pt_config_init.c +++ b/hw/xen/xen_pt_config_init.c @@ -1988,6 +1988,174 @@ static int xen_pt_ext_cap_aer_size_init(XenPCIPassthroughState *s, return ret; } +/* get Root Complex Link Declaration Extended Capability register group size */ +#define RCLD_GET_NUM_ENTRIES(x) (((x) >> 8) & 0xFF) +static int xen_pt_ext_cap_rcld_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint32_t elem_self_descr = 0; + + int ret = xen_host_pci_get_long(&s->real_device, + base_offset + 4, + &elem_self_descr); + + *size = 0x10 + RCLD_GET_NUM_ENTRIES(elem_self_descr) * 0x10; + + log_pcie_extended_cap(s, "Root Complex Link Declaration", + base_offset, *size); + return ret; +} + +/* get Access Control Services Extended Capability register group size */ +#define ACS_VECTOR_SIZE_BITS(x) ((((x) >> 8) & 0xFF) ?: 256) +static int xen_pt_ext_cap_acs_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint16_t acs_caps = 0; + + int ret = xen_host_pci_get_word(&s->real_device, + base_offset + PCI_ACS_CAP, + &acs_caps); + + if (acs_caps & PCI_ACS_EC) { + uint32_t vector_sz = ACS_VECTOR_SIZE_BITS(acs_caps); + + *size = PCI_ACS_EGRESS_CTL_V + ((vector_sz + 7) & ~7) / 8; + } else { + *size = PCI_ACS_EGRESS_CTL_V; + } + + log_pcie_extended_cap(s, "ACS", base_offset, *size); + return ret; +} + +/* get Multicast Extended Capability register group size */ +static int xen_pt_ext_cap_multicast_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint8_t dev_type = get_pcie_device_type(s); + + switch (dev_type) { + case PCI_EXP_TYPE_ENDPOINT: + case PCI_EXP_TYPE_LEG_END: + case PCI_EXP_TYPE_RC_END: + case PCI_EXP_TYPE_RC_EC: + default: + *size = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF; + break; + + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_UPSTREAM: + case PCI_EXP_TYPE_DOWNSTREAM: + *size = 0x30; + break; + } + + log_pcie_extended_cap(s, "Multicast", base_offset, *size); + return 0; +} + +/* get Dynamic Power Allocation Extended Capability register group size */ +static int xen_pt_ext_cap_dpa_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint32_t dpa_caps = 0; + uint32_t num_entries; + + int ret = xen_host_pci_get_long(&s->real_device, + base_offset + PCI_DPA_CAP, + &dpa_caps); + + num_entries = (dpa_caps & PCI_DPA_CAP_SUBSTATE_MASK) + 1; + + *size = PCI_DPA_BASE_SIZEOF + num_entries /*byte-size registers*/; + + log_pcie_extended_cap(s, "Dynamic Power Allocation", base_offset, *size); + return ret; +} + +/* get TPH Requester Extended Capability register group size */ +static int xen_pt_ext_cap_tph_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint32_t tph_caps = 0; + uint32_t num_entries; + + int ret = xen_host_pci_get_long(&s->real_device, + base_offset + PCI_TPH_CAP, + &tph_caps); + + switch(tph_caps & PCI_TPH_CAP_LOC_MASK) { + case PCI_TPH_LOC_CAP: + num_entries = (tph_caps & PCI_TPH_CAP_ST_MASK) >> PCI_TPH_CAP_ST_SHIFT; + num_entries++; + break; + + case PCI_TPH_LOC_NONE: + case PCI_TPH_LOC_MSIX: + default: + /* not in the capability */ + num_entries = 0; + } + + *size = PCI_TPH_BASE_SIZEOF + num_entries * 2; + + log_pcie_extended_cap(s, "TPH Requester", base_offset, *size); + return ret; +} + +/* get Downstream Port Containment Extended Capability register group size */ +static int xen_pt_ext_cap_dpc_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint16_t dpc_caps = 0; + + int ret = xen_host_pci_get_word(&s->real_device, + base_offset + PCI_EXP_DPC_CAP, + &dpc_caps); + + if (dpc_caps & PCI_EXP_DPC_CAP_RP_EXT) { + *size = 0x20 + ((dpc_caps & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8) * 4; + } else { + *size = 0xC; + } + + log_pcie_extended_cap(s, "Downstream Port Containment", + base_offset, *size); + return ret; +} + +/* get Protocol Multiplexing Extended Capability register group size */ +#define PMUX_GET_NUM_ENTRIES(x) ((x) & 0x3F) +static int xen_pt_ext_cap_pmux_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint32_t pmux_caps = 0; + + int ret = xen_host_pci_get_long(&s->real_device, + base_offset + 4, + &pmux_caps); + + *size = 0x10 + PMUX_GET_NUM_ENTRIES(pmux_caps) * 4; + + log_pcie_extended_cap(s, "PMUX", base_offset, *size); + return ret; +} + static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = { /* Header Type0 reg group */ @@ -2264,6 +2432,62 @@ static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = { .size_init = xen_pt_ext_cap_aer_size_init, .emu_regs = xen_pt_ext_cap_emu_reg_dummy, }, + /* Root Complex Link Declaration Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_RCLD), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_rcld_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Access Control Services Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_ACS), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_acs_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Multicast Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_MCAST), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_multicast_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Dynamic Power Allocation Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_DPA), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_dpa_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* TPH Requester Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_TPH), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_tph_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Protocol Multiplexing Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_PMUX), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_pmux_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Downstream Port Containment Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_DPC), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_dpc_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, { .grp_size = 0, }, -- 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
next prev parent reply other threads:[~2018-03-12 18:36 UTC|newest] Thread overview: 183+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-03-12 18:33 [Qemu-devel] [RFC PATCH 00/30] Xen Q35 Bringup patches + support for PCIe Extended Capabilities for passed through devices Alexey Gerasimenko 2018-03-12 18:33 ` Alexey Gerasimenko 2018-03-12 18:33 ` [RFC PATCH 01/12] libacpi: new DSDT ACPI table for Q35 Alexey Gerasimenko 2018-03-12 19:38 ` Konrad Rzeszutek Wilk 2018-03-12 20:10 ` Alexey G 2018-03-12 20:32 ` Konrad Rzeszutek Wilk 2018-03-12 21:19 ` Alexey G 2018-03-13 2:41 ` Tian, Kevin 2018-03-19 12:43 ` Roger Pau Monné 2018-03-19 13:57 ` Alexey G 2018-03-12 18:33 ` [RFC PATCH 02/12] Makefile: build and use new DSDT " Alexey Gerasimenko 2018-03-19 12:46 ` Roger Pau Monné 2018-03-19 14:18 ` Alexey G 2018-03-19 13:07 ` Jan Beulich 2018-03-19 14:10 ` Alexey G 2018-03-12 18:33 ` [RFC PATCH 03/12] hvmloader: add function to query an emulated machine type (i440/Q35) Alexey Gerasimenko 2018-03-13 17:26 ` Wei Liu 2018-03-13 17:58 ` Alexey G 2018-03-13 18:04 ` Wei Liu 2018-03-19 12:56 ` Roger Pau Monné 2018-03-19 16:26 ` Alexey G 2018-03-12 18:33 ` [RFC PATCH 04/12] hvmloader: add ACPI enabling for Q35 Alexey Gerasimenko 2018-03-13 17:26 ` Wei Liu 2018-03-19 13:01 ` Roger Pau Monné 2018-03-19 23:59 ` Alexey G 2018-03-12 18:33 ` [RFC PATCH 05/12] hvmloader: add Q35 DSDT table loading Alexey Gerasimenko 2018-03-19 14:45 ` Roger Pau Monné 2018-03-20 0:15 ` Alexey G 2018-03-12 18:33 ` [RFC PATCH 06/12] hvmloader: add basic Q35 support Alexey Gerasimenko 2018-03-19 15:30 ` Roger Pau Monné 2018-03-19 23:44 ` Alexey G 2018-03-20 9:20 ` Roger Pau Monné 2018-03-20 21:23 ` Alexey G 2018-03-12 18:33 ` [RFC PATCH 07/12] hvmloader: allocate MMCONFIG area in the MMIO hole + minor code refactoring Alexey Gerasimenko 2018-03-19 15:58 ` Roger Pau Monné 2018-03-19 19:49 ` Alexey G 2018-03-20 8:50 ` Roger Pau Monné 2018-03-20 9:25 ` Paul Durrant 2018-03-21 0:58 ` Alexey G 2018-03-21 9:09 ` Roger Pau Monné 2018-03-21 9:36 ` Paul Durrant 2018-03-21 14:35 ` Alexey G 2018-03-21 14:58 ` Paul Durrant 2018-03-21 14:25 ` Alexey G 2018-03-21 14:54 ` Paul Durrant 2018-03-21 17:41 ` Alexey G 2018-03-21 15:20 ` Roger Pau Monné 2018-03-21 16:56 ` Alexey G 2018-03-21 17:06 ` Paul Durrant 2018-03-22 0:31 ` Alexey G 2018-03-22 9:04 ` Jan Beulich 2018-03-22 9:55 ` Alexey G 2018-03-22 10:06 ` Paul Durrant 2018-03-22 11:56 ` Alexey G 2018-03-22 12:09 ` Jan Beulich 2018-03-22 13:05 ` Alexey G 2018-03-22 13:20 ` Jan Beulich 2018-03-22 14:34 ` Alexey G 2018-03-22 14:42 ` Jan Beulich 2018-03-22 15:08 ` Alexey G 2018-03-23 13:57 ` Paul Durrant 2018-03-23 22:32 ` Alexey G 2018-03-26 9:24 ` Roger Pau Monné 2018-03-26 19:42 ` Alexey G 2018-03-27 8:45 ` Roger Pau Monné 2018-03-27 15:37 ` Alexey G 2018-03-28 9:30 ` Roger Pau Monné 2018-03-28 11:42 ` Alexey G 2018-03-28 12:05 ` Paul Durrant 2018-03-28 10:03 ` Paul Durrant 2018-03-28 14:14 ` Alexey G 2018-03-21 17:15 ` Roger Pau Monné 2018-03-21 22:49 ` Alexey G 2018-03-22 9:29 ` Paul Durrant 2018-03-22 10:05 ` Roger Pau Monné 2018-03-22 10:09 ` Paul Durrant 2018-03-22 11:36 ` Alexey G 2018-03-22 10:50 ` Alexey G 2018-03-22 9:57 ` Roger Pau Monné 2018-03-22 12:29 ` Alexey G 2018-03-22 12:44 ` Roger Pau Monné 2018-03-22 15:31 ` Alexey G 2018-03-23 10:29 ` Paul Durrant 2018-03-23 11:38 ` Jan Beulich 2018-03-23 13:52 ` Paul Durrant 2018-05-29 14:23 ` Jan Beulich 2018-05-29 17:56 ` Alexey G 2018-05-29 18:47 ` Alexey G 2018-05-30 4:32 ` Alexey G 2018-05-30 8:13 ` Jan Beulich 2018-05-31 4:25 ` Alexey G 2018-05-30 8:12 ` Jan Beulich 2018-05-31 5:15 ` Alexey G 2018-06-01 5:30 ` Jan Beulich 2018-06-01 15:53 ` Alexey G 2018-03-12 18:33 ` [RFC PATCH 08/12] libxl: Q35 support (new option device_model_machine) Alexey Gerasimenko 2018-03-13 17:25 ` Wei Liu 2018-03-13 17:32 ` Anthony PERARD 2018-03-19 17:01 ` Roger Pau Monné 2018-03-19 22:11 ` Alexey G 2018-03-20 9:11 ` Roger Pau Monné 2018-03-21 16:27 ` Wei Liu 2018-03-21 17:03 ` Anthony PERARD 2018-03-21 16:25 ` Wei Liu 2018-03-12 18:33 ` [RFC PATCH 09/12] libxl: Xen Platform device support for Q35 Alexey Gerasimenko 2018-03-19 15:05 ` Alexey G 2018-03-21 16:32 ` Wei Liu 2018-03-12 18:33 ` [RFC PATCH 10/12] libacpi: build ACPI MCFG table if requested Alexey Gerasimenko 2018-03-19 17:33 ` Roger Pau Monné 2018-03-19 21:46 ` Alexey G 2018-03-20 9:03 ` Roger Pau Monné 2018-03-20 21:06 ` Alexey G 2018-05-29 14:36 ` Jan Beulich 2018-05-29 18:20 ` Alexey G 2018-03-12 18:33 ` [RFC PATCH 11/12] hvmloader: use libacpi to build MCFG table Alexey Gerasimenko 2018-03-14 17:48 ` Alexey G 2018-03-19 17:49 ` Roger Pau Monné 2018-03-19 21:20 ` Alexey G 2018-03-20 8:58 ` Roger Pau Monné 2018-03-20 9:36 ` Jan Beulich 2018-03-20 20:53 ` Alexey G 2018-03-21 7:36 ` Jan Beulich 2018-05-29 14:46 ` Jan Beulich 2018-05-29 17:26 ` Alexey G 2018-03-12 18:33 ` [RFC PATCH 12/12] docs: provide description for device_model_machine option Alexey Gerasimenko 2018-03-12 18:33 ` [Qemu-devel] [RFC PATCH 13/30] pc/xen: Xen Q35 support: provide IRQ handling for PCI devices Alexey Gerasimenko 2018-03-12 18:33 ` Alexey Gerasimenko 2018-03-14 10:48 ` [Qemu-devel] " Paolo Bonzini 2018-03-14 11:28 ` Alexey G 2018-03-14 11:28 ` Alexey G 2018-03-14 10:48 ` Paolo Bonzini 2018-03-12 18:33 ` [Qemu-devel] [RFC PATCH 14/30] pc/q35: Apply PCI bus BSEL property for Xen PCI device hotplug Alexey Gerasimenko 2018-03-12 18:33 ` Alexey Gerasimenko 2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 15/30] q35/acpi/xen: Provide ACPI PCI hotplug interface for Xen on Q35 Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko 2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 16/30] q35/xen: Add Xen platform device support for Q35 Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko 2018-03-12 19:44 ` [Qemu-devel] " Eduardo Habkost 2018-03-12 20:56 ` Alexey G 2018-03-12 20:56 ` Alexey G 2018-03-12 21:44 ` Eduardo Habkost 2018-03-12 21:44 ` [Qemu-devel] " Eduardo Habkost 2018-03-13 23:49 ` Alexey G 2018-03-13 23:49 ` Alexey G 2018-03-12 19:44 ` Eduardo Habkost 2018-03-13 9:24 ` [Qemu-devel] " Daniel P. Berrangé 2018-03-13 9:24 ` Daniel P. Berrangé 2018-03-12 18:34 ` [RFC PATCH 17/30] q35: Fix incorrect values for PCIEXBAR masks Alexey Gerasimenko 2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 18/30] xen/pt: XenHostPCIDevice: provide functions for PCI Capabilities and PCIe Extended Capabilities enumeration Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko 2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 19/30] xen/pt: avoid reading PCIe device type and cap version multiple times Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko 2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 20/30] xen/pt: determine the legacy/PCIe mode for a passed through device Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko 2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 21/30] xen/pt: Xen PCIe passthrough support for Q35: bypass PCIe topology check Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko 2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 22/30] xen/pt: add support for PCIe Extended Capabilities and larger config space Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko 2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 23/30] xen/pt: handle PCIe Extended Capabilities Next register Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko 2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 24/30] xen/pt: allow to hide PCIe Extended Capabilities Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko 2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 25/30] xen/pt: add Vendor-specific PCIe Extended Capability descriptor and sizing Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko 2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 26/30] xen/pt: add fixed-size PCIe Extended Capabilities descriptors Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko 2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 27/30] xen/pt: add AER PCIe Extended Capability descriptor and sizing Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko [this message] 2018-03-12 18:34 ` [RFC PATCH 28/30] xen/pt: add descriptors and size calculation for RCLD/ACS/PMUX/DPA/MCAST/TPH/DPC PCIe Extended Capabilities Alexey Gerasimenko 2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 29/30] xen/pt: add Resizable BAR PCIe Extended Capability descriptor and sizing Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko 2018-03-12 18:34 ` [Qemu-devel] [RFC PATCH 30/30] xen/pt: add VC/VC9/MFVC PCIe Extended Capabilities descriptors " Alexey Gerasimenko 2018-03-12 18:34 ` Alexey Gerasimenko 2018-03-13 9:21 ` [Qemu-devel] [RFC PATCH 00/30] Xen Q35 Bringup patches + support for PCIe Extended Capabilities for passed through devices Daniel P. Berrangé 2018-03-13 9:21 ` Daniel P. Berrangé 2018-03-13 11:37 ` Alexey G 2018-03-13 11:37 ` Alexey G 2018-03-13 11:44 ` Daniel P. Berrangé 2018-03-13 11:44 ` Daniel P. Berrangé 2018-03-16 17:34 ` Alexey G 2018-03-16 18:26 ` Stefano Stabellini 2018-03-16 18:36 ` Roger Pau Monné
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