[U-Boot] [PATCH 0/3] SAMSUNG: SMDKC100: Add Ethernet support.

[U-Boot] [PATCH 0/3] SAMSUNG: SMDKC100: Add Ethernet support.

[Naveen Krishna Ch]

From: Naveen Krishna CH <ch.naveen@samsung.com>

This patch set Adds
A. A header file which contains the register description for
	memory subsystem in S5PC1XX based baords.
B. A function to configure SROMC registers
A. Net support for SMDKC100 board.

This patch set consists of the following patches.

[PATCH 1/3] S5PC100: Memory SubSystem Header file, register description(SROMC).
[PATCH 2/3] S5PC100: Function to configure the SROMC registers.
[PATCH 3/3] SAMSUNG-SMDKC100-Adds-ethernet-support.

TODO: Proper GPIO interface to be implemented.

Thanks & Best regards. 
Naveen

[U-Boot] [PATCH 1/3] S5PC100: Memory SubSystem Header file, register description(SROMC).

[Naveen Krishna Ch]

From: Naveen Krishna CH <ch.naveen@samsung.com>

Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand,
NAND Flash, DDRs.
mem.h is a common place for the register description of Memory subsystem
of S5PC100.
Note: Only SROM related registers are descibed now.

Signed-off-by: Naveen Krishna Ch <ch.naveen <at> samsung.com>
---
 include/asm-arm/arch-s5pc1xx/mem.h |   55 ++++++++++++++++++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)
 create mode 100644 include/asm-arm/arch-s5pc1xx/mem.h

diff --git a/include/asm-arm/arch-s5pc1xx/mem.h b/include/asm-arm/arch-s5pc1xx/mem.h
new file mode 100644
index 0000000..66272ff
--- /dev/null
+++ b/include/asm-arm/arch-s5pc1xx/mem.h
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: This file contains the register description for Memory subsystem
+ * 	 (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
+ *
+ * 	 Only SROMC is defined as of now
+ */
+
+#ifndef __ASM_ARCH_MEM_H_
+#define __ASM_ARCH_MEM_H_
+
+#define SROM_DATA16_WIDTH(x)    (1<<((x*4)+0))
+#define SROM_BYTE_ADDR_MODE(x)  (1<<((x*4)+1))  /* 0-> Half-word base address*/
+						/* 1-> Byte base address*/
+#define SROM_WAIT_ENABLE(x)     (1<<((x*4)+2))
+#define SROM_BYTE_ENABLE(x)     (1<<((x*4)+3))
+
+#define SMCBC_X_Tacs    (0x0)   /* 0clk         address set-up */
+#define SMCBC_X_Tcos    (0x4)   /* 4clk         chip selection set-up */
+#define SMCBC_X_Tacc    (0xe)   /* 14clk        access cycle */
+#define SMCBC_X_Tcoh    (0x1)   /* 1clk         chip selection hold */
+#define SMCBC_X_Tah     (0x4)   /* 4clk         address holding time */
+#define SMCBC_X_Tacp    (0x6)   /* 6clk         page mode access cycle */
+#define SMCBC_X_PMC     (0x0)   /* normal(1data)page mode configuration */
+
+#define SMC_BC_X_CON    ((SMCBC_X_Tacs<<28)|(SMCBC_X_Tcos<<24)| \
+			 (SMCBC_X_Tacc<<16)|(SMCBC_X_Tcoh<<12)| \
+			 (SMCBC_X_Tah<<8)|(SMCBC_X_Tacp<<4)|    \
+			 (SMCBC_X_PMC))
+
+#ifndef __ASSEMBLY__
+struct s5pc1xx_sromc {
+	unsigned int	smc_bw;
+	unsigned int	smc_bc[6];
+};
+#endif	/* __ASSEMBLY__ */
+
+#endif /* __ASM_ARCH_MEM_H_ */
-- 
1.6.6

[U-Boot] [PATCH 2/3] S5PC100: Function to configure the SROMC registers.

[Naveen Krishna Ch]

From: Naveen Krishna CH <ch.naveen@samsung.com>

Nand Flash, Ethernet, other features might need to configure the
SROMC registers accordingly.
The config_sromc() functions helps with this.

Signed-off-by: Naveen Krishna Ch <ch.naveen <at> samsung.com>
---
 cpu/arm_cortexa8/s5pc1xx/Makefile  |    1 +
 cpu/arm_cortexa8/s5pc1xx/sromc.c   |   49 ++++++++++++++++++++++++++++++++++++
 include/asm-arm/arch-s5pc1xx/mem.h |    3 ++
 3 files changed, 53 insertions(+), 0 deletions(-)
 create mode 100644 cpu/arm_cortexa8/s5pc1xx/sromc.c

diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile
index 4f922e6..0a6a9b4 100644
--- a/cpu/arm_cortexa8/s5pc1xx/Makefile
+++ b/cpu/arm_cortexa8/s5pc1xx/Makefile
@@ -34,6 +34,7 @@ SOBJS	+= reset.o
 COBJS	+= clock.o
 COBJS	+= cpu_info.o
 COBJS	+= timer.o
+COBJS	+= sromc.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c b/cpu/arm_cortexa8/s5pc1xx/sromc.c
new file mode 100644
index 0000000..96ca9e0
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+
+/*
+ * config_sromc() - select the proper SROMC Bank and configure the
+ * 		    band width control and bank control registers
+ * srom_bank	- SROM Bank 0 to 5
+ * smc_bw_conf  - SMC Band witdh reg configuration value
+ * smc_bc_conf  - SMC Bank Control reg configuration value
+ */
+void config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
+{
+	u32 tmp;
+	struct s5pc1xx_sromc *const srom =
+		(struct s5pc1xx_sromc *)S5PC100_SROMC_BASE;
+
+	/* Configure SMC_BW register to handle proper SROMC bank */
+	tmp = srom->smc_bw;
+	tmp &= ~(0xF << (srom_bank * 4));
+	tmp |= smc_bw_conf;
+	srom->smc_bw = tmp;
+
+	/* Configure SMC_BC register */
+	srom->smc_bc[srom_bank] = smc_bc_conf;
+}
diff --git a/include/asm-arm/arch-s5pc1xx/mem.h b/include/asm-arm/arch-s5pc1xx/mem.h
index 66272ff..99b2d2e 100644
--- a/include/asm-arm/arch-s5pc1xx/mem.h
+++ b/include/asm-arm/arch-s5pc1xx/mem.h
@@ -52,4 +52,7 @@ struct s5pc1xx_sromc {
 };
 #endif	/* __ASSEMBLY__ */
 
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
+
 #endif /* __ASM_ARCH_MEM_H_ */
-- 
1.6.6

[U-Boot] [PATCH 3/3] SAMSUNG: SMDKC100: Adds ethernet support.

[Naveen Krishna Ch]

From: Naveen Krishna CH <ch.naveen@samsung.com>

Add setup for ethernet on SMDKC100, allowing kernel/ramdisk to be
loaded over tftp.

The preinit function will configure GPIO (GPK0CON) & SROMC to look
for environment in SROM Bank 3.

Signed-off-by: Naveen Krishna Ch <ch.naveen <at> samsung.com>
---
 board/samsung/smdkc100/smdkc100.c |   37 +++++++++++++++++++++++++++++++++++++
 include/configs/smdkc100.h        |   30 +++++++++++++++++++++++++++++-
 2 files changed, 66 insertions(+), 1 deletions(-)

diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c
index 15a1a27..6e50f14 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -23,10 +23,38 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+
+#define GPK0CON_OFFSET          0x2A0
+#define GPK0CON                 (S5PC100_GPIO_BASE + GPK0CON_OFFSET)
+
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+static void smc9115_pre_init(void)
+{
+	u32 tmp;
+	u32 smc_bw_conf;
+
+	/* gpio configuration */
+	tmp = __raw_readl(GPK0CON);
+	tmp &= ~(0xf << CONFIG_ENV_SROM_BANK * 4);
+	tmp |=  (0x2 << CONFIG_ENV_SROM_BANK * 4);
+	__raw_writel(tmp, GPK0CON);
+
+	/* Ethernet needs bus width of 16 bits */
+	smc_bw_conf = SROM_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
+
+	/* Select and configure the SROMC bank */
+	config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, SMC_BC_X_CON);
+}
+
 int board_init(void)
 {
+	smc9115_pre_init();
 	gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
@@ -49,3 +77,12 @@ int checkboard(void)
 	return 0;
 }
 #endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index a8ba052..3de9da1 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -83,7 +83,7 @@
 #undef CONFIG_CMD_FLASH
 #undef CONFIG_CMD_IMLS
 #undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_NET
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot */
 
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_REGINFO
@@ -235,4 +235,32 @@
 
 #define CONFIG_DOS_PARTITION		1
 
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+/*
+ * Net Configurations
+ */
+#define CONFIG_ETHADDR          00 : 40 : 5c : 26 : 0a : 5b
+#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_IPADDR           192.168.0.20
+#define CONFIG_SERVERIP         192.168.0.10
+#define CONFIG_GATEWAYIP        192.168.0.1
+
+/*
+ * Ethernet Contoller driver
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X   	1	/* we have a SMC9115 on-board	*/
+#define CONFIG_SMC911X_16_BIT	1	/* SMC911X_16_BIT Mode		*/
+#define CONFIG_SMC911X_BASE	0x98800300	/* SMC911X Drive Base	*/
+#define CONFIG_ENV_SROM_BANK	3	/* Select SROM Bank-3 for Ethernet*/
+#endif /* CONFIG_CMD_NET */
+
 #endif	/* __CONFIG_H */
-- 
1.6.6

[U-Boot] [PATCH 3/3] SAMSUNG: SMDKC100: Adds ethernet support.

[Ben Warren]

Naveen,

On Tue, Feb 9, 2010 at 1:38 AM, Naveen Krishna Ch <ch.naveen@samsung.com>wrote:

> From: Naveen Krishna CH <ch.naveen@samsung.com>
>
> Add setup for ethernet on SMDKC100, allowing kernel/ramdisk to be
> loaded over tftp.
>
> The preinit function will configure GPIO (GPK0CON) & SROMC to look
> for environment in SROM Bank 3.
>
> Signed-off-by: Naveen Krishna Ch <ch.naveen <at> samsung.com>
> ---
>  board/samsung/smdkc100/smdkc100.c |   37
> +++++++++++++++++++++++++++++++++++++
>  include/configs/smdkc100.h        |   30 +++++++++++++++++++++++++++++-
>  2 files changed, 66 insertions(+), 1 deletions(-)
>
> diff --git a/board/samsung/smdkc100/smdkc100.c
> b/board/samsung/smdkc100/smdkc100.c
> index 15a1a27..6e50f14 100644
> --- a/board/samsung/smdkc100/smdkc100.c
> +++ b/board/samsung/smdkc100/smdkc100.c
> @@ -23,10 +23,38 @@
>  */
>
>  #include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/mem.h>
> +
> +#define GPK0CON_OFFSET          0x2A0
> +#define GPK0CON                 (S5PC100_GPIO_BASE + GPK0CON_OFFSET)
> +
>  DECLARE_GLOBAL_DATA_PTR;
>
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +static void smc9115_pre_init(void)
> +{
> +       u32 tmp;
> +       u32 smc_bw_conf;
> +
> +       /* gpio configuration */
> +       tmp = __raw_readl(GPK0CON);
> +       tmp &= ~(0xf << CONFIG_ENV_SROM_BANK * 4);
> +       tmp |=  (0x2 << CONFIG_ENV_SROM_BANK * 4);
> +       __raw_writel(tmp, GPK0CON);
> +
> +       /* Ethernet needs bus width of 16 bits */
> +       smc_bw_conf = SROM_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
> +
> +       /* Select and configure the SROMC bank */
> +       config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, SMC_BC_X_CON);
> +}
> +
>  int board_init(void)
>  {
> +       smc9115_pre_init();
>        gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;
>        gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
>
> @@ -49,3 +77,12 @@ int checkboard(void)
>        return 0;
>  }
>  #endif
> +
> +int board_eth_init(bd_t *bis)
> +{
> +       int rc = 0;
> +#ifdef CONFIG_SMC911X
> +       rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
> +#endif
> +       return rc;
> +}
> diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
> index a8ba052..3de9da1 100644
> --- a/include/configs/smdkc100.h
> +++ b/include/configs/smdkc100.h
> @@ -83,7 +83,7 @@
>  #undef CONFIG_CMD_FLASH
>  #undef CONFIG_CMD_IMLS
>  #undef CONFIG_CMD_NAND
> -#undef CONFIG_CMD_NET
> +#define CONFIG_CMD_NET         /* bootp, tftpboot, rarpboot */
>
>  #define CONFIG_CMD_CACHE
>  #define CONFIG_CMD_REGINFO
> @@ -235,4 +235,32 @@
>
>  #define CONFIG_DOS_PARTITION           1
>
> +/*
> + * BOOTP options
> + */
> +#define CONFIG_BOOTP_SUBNETMASK
> +#define CONFIG_BOOTP_GATEWAY
> +#define CONFIG_BOOTP_HOSTNAME
> +#define CONFIG_BOOTP_BOOTPATH
> +
> +/*
> + * Net Configurations
> + */
> +#define CONFIG_ETHADDR          00 : 40 : 5c : 26 : 0a : 5b
> +#define CONFIG_NETMASK          255.255.255.0
> +#define CONFIG_IPADDR           192.168.0.20
> +#define CONFIG_SERVERIP         192.168.0.10
> +#define CONFIG_GATEWAYIP        192.168.0.1
> +
>
Please remove all of these.  If you don't know why, search the archives.
 It's only been discussed 10000 times or so.

> +/*
> + * Ethernet Contoller driver
> + */
> +#ifdef CONFIG_CMD_NET
> +#define CONFIG_NET_MULTI
> +#define CONFIG_SMC911X         1       /* we have a SMC9115 on-board   */
> +#define CONFIG_SMC911X_16_BIT  1       /* SMC911X_16_BIT Mode          */
> +#define CONFIG_SMC911X_BASE    0x98800300      /* SMC911X Drive Base   */
> +#define CONFIG_ENV_SROM_BANK   3       /* Select SROM Bank-3 for
> Ethernet*/
> +#endif /* CONFIG_CMD_NET */
> +
>  #endif /* __CONFIG_H */
>
regards,
Ben

[U-Boot] [PATCH 0/3] SAMSUNG: SMDKC100: Add Ethernet support.

[Minkyu Kang]

Dear Naveen Krishna Ch,

On 9 February 2010 18:22, Naveen Krishna Ch <ch.naveen@samsung.com> wrote:
> From: Naveen Krishna CH <ch.naveen@samsung.com>
>
> This patch set Adds
> A. A header file which contains the register description for
> ? ? ? ?memory subsystem in S5PC1XX based baords.
> B. A function to configure SROMC registers
> A. Net support for SMDKC100 board.
>
> This patch set consists of the following patches.
>
> [PATCH 1/3] S5PC100: Memory SubSystem Header file, register description(SROMC).
> [PATCH 2/3] S5PC100: Function to configure the SROMC registers.
> [PATCH 3/3] SAMSUNG-SMDKC100-Adds-ethernet-support.
>
> TODO: Proper GPIO interface to be implemented.
>
I will post the GPIO Interface soon.
And patch0 is unnecessary.

Thanks
Minkyu Kang.
-- 
from. prom.
www.promsoft.net

[U-Boot] [PATCH 0/3] SAMSUNG: SMDKC100: Add Ethernet support.

[Naveen Krishna Ch]

Hi Kang,

On 10 February 2010 08:46, Minkyu Kang <promsoft@gmail.com> wrote:

> Dear Naveen Krishna Ch,
>
> On 9 February 2010 18:22, Naveen Krishna Ch <ch.naveen@samsung.com> wrote:
> > From: Naveen Krishna CH <ch.naveen@samsung.com>
> >
> > This patch set Adds
> > A. A header file which contains the register description for
> >        memory subsystem in S5PC1XX based baords.
> > B. A function to configure SROMC registers
> > A. Net support for SMDKC100 board.
> >
> > This patch set consists of the following patches.
> >
> > [PATCH 1/3] S5PC100: Memory SubSystem Header file, register
> description(SROMC).
> > [PATCH 2/3] S5PC100: Function to configure the SROMC registers.
> > [PATCH 3/3] SAMSUNG-SMDKC100-Adds-ethernet-support.
> >
> > TODO: Proper GPIO interface to be implemented.
> >
> I will post the GPIO Interface soon.
> And patch0 is unnecessary.

I thought of giving a description of patch set before posting them.,

>
> Thanks
> Minkyu Kang.
> --
> from. prom.
> www.promsoft.net
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>



-- 
Shine bright,
(: Naveen Krishna Ch :)

[U-Boot] [PATCH 3/3] SAMSUNG: SMDKC100: Adds ethernet support.

[Naveen Krishna Ch]

Hi Ben,

I think you wanted me to remove the CONFIG_BOOTP_* macros.
But the gmail is showing some other code under ur comments.

Any how i wil remove the CONFIG_BOOTP_* macros and submit a
V2 version of the patch.

On 9 February 2010 20:22, Ben Warren <biggerbadderben@gmail.com> wrote:

> Naveen,
>
> On Tue, Feb 9, 2010 at 1:38 AM, Naveen Krishna Ch <ch.naveen@samsung.com
> >wrote:
>
> > From: Naveen Krishna CH <ch.naveen@samsung.com>
> >
> > Add setup for ethernet on SMDKC100, allowing kernel/ramdisk to be
> > loaded over tftp.
> >
> > The preinit function will configure GPIO (GPK0CON) & SROMC to look
> > for environment in SROM Bank 3.
> >
> > Signed-off-by: Naveen Krishna Ch <ch.naveen <at> samsung.com>
> > ---
> >  board/samsung/smdkc100/smdkc100.c |   37
> > +++++++++++++++++++++++++++++++++++++
> >  include/configs/smdkc100.h        |   30 +++++++++++++++++++++++++++++-
> >  2 files changed, 66 insertions(+), 1 deletions(-)
> >
> > diff --git a/board/samsung/smdkc100/smdkc100.c
> > b/board/samsung/smdkc100/smdkc100.c
> > index 15a1a27..6e50f14 100644
> > --- a/board/samsung/smdkc100/smdkc100.c
> > +++ b/board/samsung/smdkc100/smdkc100.c
> > @@ -23,10 +23,38 @@
> >  */
> >
> >  #include <common.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/mem.h>
> > +
> > +#define GPK0CON_OFFSET          0x2A0
> > +#define GPK0CON                 (S5PC100_GPIO_BASE + GPK0CON_OFFSET)
> > +
> >  DECLARE_GLOBAL_DATA_PTR;
> >
> > +/*
> > + * Miscellaneous platform dependent initialisations
> > + */
> > +static void smc9115_pre_init(void)
> > +{
> > +       u32 tmp;
> > +       u32 smc_bw_conf;
> > +
> > +       /* gpio configuration */
> > +       tmp = __raw_readl(GPK0CON);
> > +       tmp &= ~(0xf << CONFIG_ENV_SROM_BANK * 4);
> > +       tmp |=  (0x2 << CONFIG_ENV_SROM_BANK * 4);
> > +       __raw_writel(tmp, GPK0CON);
> > +
> > +       /* Ethernet needs bus width of 16 bits */
> > +       smc_bw_conf = SROM_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
> > +
> > +       /* Select and configure the SROMC bank */
> > +       config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, SMC_BC_X_CON);
> > +}
> > +
> >  int board_init(void)
> >  {
> > +       smc9115_pre_init();
> >        gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;
> >        gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
> >
> > @@ -49,3 +77,12 @@ int checkboard(void)
> >        return 0;
> >  }
> >  #endif
> > +
> > +int board_eth_init(bd_t *bis)
> > +{
> > +       int rc = 0;
> > +#ifdef CONFIG_SMC911X
> > +       rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
> > +#endif
> > +       return rc;
> > +}
> > diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
> > index a8ba052..3de9da1 100644
> > --- a/include/configs/smdkc100.h
> > +++ b/include/configs/smdkc100.h
> > @@ -83,7 +83,7 @@
> >  #undef CONFIG_CMD_FLASH
> >  #undef CONFIG_CMD_IMLS
> >  #undef CONFIG_CMD_NAND
> > -#undef CONFIG_CMD_NET
> > +#define CONFIG_CMD_NET         /* bootp, tftpboot, rarpboot */
> >
> >  #define CONFIG_CMD_CACHE
> >  #define CONFIG_CMD_REGINFO
> > @@ -235,4 +235,32 @@
> >
> >  #define CONFIG_DOS_PARTITION           1
> >
>
> +/*
> > + * BOOTP options
> > + */
> > +#define CONFIG_BOOTP_SUBNETMASK
> > +#define CONFIG_BOOTP_GATEWAY
> > +#define CONFIG_BOOTP_HOSTNAME
> > +#define CONFIG_BOOTP_BOOTPATH
> > +
> > +/*
> > + * Net Configurations
> > + */
> > +#define CONFIG_ETHADDR          00 : 40 : 5c : 26 : 0a : 5b
> > +#define CONFIG_NETMASK          255.255.255.0
> > +#define CONFIG_IPADDR           192.168.0.20
> > +#define CONFIG_SERVERIP         192.168.0.10
> > +#define CONFIG_GATEWAYIP        192.168.0.1
> > +
> >
> Please remove all of these.  If you don't know why, search the archives.
>  It's only been discussed 10000 times or so.
>
I think you want me to remove macros starting from CONFIG_BOOTP_* macros
till CONFIG_GATWAYIP

>
> > +/*
> > + * Ethernet Contoller driver
> > + */
> > +#ifdef CONFIG_CMD_NET
> > +#define CONFIG_NET_MULTI
> > +#define CONFIG_SMC911X         1       /* we have a SMC9115 on-board
> */
> > +#define CONFIG_SMC911X_16_BIT  1       /* SMC911X_16_BIT Mode
>  */
> > +#define CONFIG_SMC911X_BASE    0x98800300      /* SMC911X Drive Base
> */
> > +#define CONFIG_ENV_SROM_BANK   3       /* Select SROM Bank-3 for
> > Ethernet*/
> > +#endif /* CONFIG_CMD_NET */
> > +
> >  #endif /* __CONFIG_H */
>
This is code is needed to enable the ethernet driver and tftp command.

Thank You Ben,

>  >
> regards,
> Ben
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
>


-- 
Shine bright,
(: Naveen Krishna Ch :)

[U-Boot] [PATCH 3/3] SAMSUNG: SMDKC100: Adds ethernet support.

[Ben Warren]

Hi Naveen,

On 2/9/2010 8:53 PM, Naveen Krishna Ch wrote:
> Hi Ben,
>
> I think you wanted me to remove the CONFIG_BOOTP_* macros.
> But the gmail is showing some other code under ur comments.
>
> Any how i wil remove the CONFIG_BOOTP_* macros and submit a
> V2 version of the patch.
>
I don't have a problem with the CONFIG_BOOTP macros as long as you put 
them there intentionally rather than as a cut&paste.  My quarrel was 
with the MAC and IP address assignments.  It looks like you've removed 
those, so it's all OK.

regards,
Ben

[U-Boot] [PATCH 1/3] S5PC100: Memory SubSystem Header file, register description(SROMC).

[Minkyu Kang]

Dear Naveen Krishna Ch,

On 9 February 2010 18:34, Naveen Krishna Ch <ch.naveen@samsung.com> wrote:
> From: Naveen Krishna CH <ch.naveen@samsung.com>
>
> Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand,
> NAND Flash, DDRs.
> mem.h is a common place for the register description of Memory subsystem
> of S5PC100.
> Note: Only SROM related registers are descibed now.
>
> Signed-off-by: Naveen Krishna Ch <ch.naveen <at> samsung.com>
> ---
> ?include/asm-arm/arch-s5pc1xx/mem.h | ? 55 ++++++++++++++++++++++++++++++++++++
> ?1 files changed, 55 insertions(+), 0 deletions(-)
> ?create mode 100644 include/asm-arm/arch-s5pc1xx/mem.h
>
> diff --git a/include/asm-arm/arch-s5pc1xx/mem.h b/include/asm-arm/arch-s5pc1xx/mem.h
> new file mode 100644
> index 0000000..66272ff
> --- /dev/null
> +++ b/include/asm-arm/arch-s5pc1xx/mem.h

I think srom.h is better than mem.h.

> @@ -0,0 +1,55 @@
> +/*
> + * (C) Copyright 2010 Samsung Electronics
> + * Naveen Krishna Ch <ch.naveen@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + *
> + * Note: This file contains the register description for Memory subsystem
> + * ? ? ?(SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
> + *
> + * ? ? ?Only SROMC is defined as of now
> + */
> +
> +#ifndef __ASM_ARCH_MEM_H_
> +#define __ASM_ARCH_MEM_H_
> +
> +#define SROM_DATA16_WIDTH(x) ? ?(1<<((x*4)+0))
> +#define SROM_BYTE_ADDR_MODE(x) ?(1<<((x*4)+1)) ?/* 0-> Half-word base address*/
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? /* 1-> Byte base address*/
> +#define SROM_WAIT_ENABLE(x) ? ? (1<<((x*4)+2))
> +#define SROM_BYTE_ENABLE(x) ? ? (1<<((x*4)+3))

Do you use all of these defines?

> +
> +#define SMCBC_X_Tacs ? ?(0x0) ? /* 0clk ? ? ? ? address set-up */
> +#define SMCBC_X_Tcos ? ?(0x4) ? /* 4clk ? ? ? ? chip selection set-up */
> +#define SMCBC_X_Tacc ? ?(0xe) ? /* 14clk ? ? ? ?access cycle */
> +#define SMCBC_X_Tcoh ? ?(0x1) ? /* 1clk ? ? ? ? chip selection hold */
> +#define SMCBC_X_Tah ? ? (0x4) ? /* 4clk ? ? ? ? address holding time */
> +#define SMCBC_X_Tacp ? ?(0x6) ? /* 6clk ? ? ? ? page mode access cycle */
> +#define SMCBC_X_PMC ? ? (0x0) ? /* normal(1data)page mode configuration */

Please don't use lowercase at define
and () is unnecessary.
and.. what mean X is?

> +
> +#define SMC_BC_X_CON ? ?((SMCBC_X_Tacs<<28)|(SMCBC_X_Tcos<<24)| \
> + ? ? ? ? ? ? ? ? ? ? ? ?(SMCBC_X_Tacc<<16)|(SMCBC_X_Tcoh<<12)| \
> + ? ? ? ? ? ? ? ? ? ? ? ?(SMCBC_X_Tah<<8)|(SMCBC_X_Tacp<<4)| ? ?\
> + ? ? ? ? ? ? ? ? ? ? ? ?(SMCBC_X_PMC))
> +
> +#ifndef __ASSEMBLY__
> +struct s5pc1xx_sromc {
> + ? ? ? unsigned int ? ?smc_bw;
> + ? ? ? unsigned int ? ?smc_bc[6];
> +};
> +#endif /* __ASSEMBLY__ */

smc_bw and smc_bc are already belong to sromc structure.
is "smc_" really need?
Please modify it to bw and bc or srom_bw and srom_bc (according to TRM)

> +
> +#endif /* __ASM_ARCH_MEM_H_ */
> --
> 1.6.6
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

Thanks,
Minkyu Kang.
-- 
from. prom.
www.promsoft.net

[U-Boot] [PATCH 2/3] S5PC100: Function to configure the SROMC registers.

[Minkyu Kang]

Dear Naveen Krishna Ch,

On 9 February 2010 18:38, Naveen Krishna Ch <ch.naveen@samsung.com> wrote:
> From: Naveen Krishna CH <ch.naveen@samsung.com>
>
> Nand Flash, Ethernet, other features might need to configure the
> SROMC registers accordingly.
> The config_sromc() functions helps with this.
>
> Signed-off-by: Naveen Krishna Ch <ch.naveen <at> samsung.com>

please fix ur e-mail address.

> ---
> ?cpu/arm_cortexa8/s5pc1xx/Makefile ?| ? ?1 +
> ?cpu/arm_cortexa8/s5pc1xx/sromc.c ? | ? 49 ++++++++++++++++++++++++++++++++++++
> ?include/asm-arm/arch-s5pc1xx/mem.h | ? ?3 ++
> ?3 files changed, 53 insertions(+), 0 deletions(-)
> ?create mode 100644 cpu/arm_cortexa8/s5pc1xx/sromc.c
>
> diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile
> index 4f922e6..0a6a9b4 100644
> --- a/cpu/arm_cortexa8/s5pc1xx/Makefile
> +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile
> @@ -34,6 +34,7 @@ SOBJS += reset.o
> ?COBJS ?+= clock.o
> ?COBJS ?+= cpu_info.o
> ?COBJS ?+= timer.o
> +COBJS ?+= sromc.o
>
> ?SRCS ? := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> ?OBJS ? := $(addprefix $(obj),$(COBJS) $(SOBJS))
> diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c b/cpu/arm_cortexa8/s5pc1xx/sromc.c
> new file mode 100644
> index 0000000..96ca9e0
> --- /dev/null
> +++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c
> @@ -0,0 +1,49 @@
> +/*
> + * Copyright (C) 2010 Samsung Electronics
> + * Naveen Krishna Ch <ch.naveen@samsung.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/mem.h>
> +
> +/*
> + * config_sromc() - select the proper SROMC Bank and configure the
> + * ? ? ? ? ? ? ? ? band width control and bank control registers
> + * srom_bank ? - SROM Bank 0 to 5
> + * smc_bw_conf ?- SMC Band witdh reg configuration value
> + * smc_bc_conf ?- SMC Bank Control reg configuration value
> + */
> +void config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
> +{
> + ? ? ? u32 tmp;
> + ? ? ? struct s5pc1xx_sromc *const srom =
> + ? ? ? ? ? ? ? (struct s5pc1xx_sromc *)S5PC100_SROMC_BASE;

Please adds support S5PC110 together.

> +
> + ? ? ? /* Configure SMC_BW register to handle proper SROMC bank */
> + ? ? ? tmp = srom->smc_bw;
> + ? ? ? tmp &= ~(0xF << (srom_bank * 4));
> + ? ? ? tmp |= smc_bw_conf;
> + ? ? ? srom->smc_bw = tmp;
> +
> + ? ? ? /* Configure SMC_BC register */
> + ? ? ? srom->smc_bc[srom_bank] = smc_bc_conf;
> +}
> diff --git a/include/asm-arm/arch-s5pc1xx/mem.h b/include/asm-arm/arch-s5pc1xx/mem.h
> index 66272ff..99b2d2e 100644
> --- a/include/asm-arm/arch-s5pc1xx/mem.h
> +++ b/include/asm-arm/arch-s5pc1xx/mem.h
> @@ -52,4 +52,7 @@ struct s5pc1xx_sromc {
> ?};
> ?#endif /* __ASSEMBLY__ */
>
> +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
> +void config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
> +
> ?#endif /* __ASM_ARCH_MEM_H_ */
> --
> 1.6.6
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

Thanks
Minkyu Kang
-- 
from. prom.
www.promsoft.net

[U-Boot] [PATCH 1/3] S5PC100: Memory SubSystem Header file, register description(SROMC).

[Naveen Krishna Ch]

Hi Kang,

On 10 February 2010 11:18, Minkyu Kang <promsoft@gmail.com> wrote:

> Dear Naveen Krishna Ch,
>
> On 9 February 2010 18:34, Naveen Krishna Ch <ch.naveen@samsung.com> wrote:
> > From: Naveen Krishna CH <ch.naveen@samsung.com>
> >
> > Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand,
> > NAND Flash, DDRs.
> > mem.h is a common place for the register description of Memory subsystem
> > of S5PC100.
> > Note: Only SROM related registers are descibed now.
> >
> > Signed-off-by: Naveen Krishna Ch <ch.naveen <at> samsung.com>
> > ---
> >  include/asm-arm/arch-s5pc1xx/mem.h |   55
> ++++++++++++++++++++++++++++++++++++
> >  1 files changed, 55 insertions(+), 0 deletions(-)
> >  create mode 100644 include/asm-arm/arch-s5pc1xx/mem.h
> >
> > diff --git a/include/asm-arm/arch-s5pc1xx/mem.h
> b/include/asm-arm/arch-s5pc1xx/mem.h
> > new file mode 100644
> > index 0000000..66272ff
> > --- /dev/null
> > +++ b/include/asm-arm/arch-s5pc1xx/mem.h
>
> I think srom.h is better than mem.h.
>
As the SMC of S5PC100 is supporting several memories SRAM, SROM, NAND, NOR,
DDR. I kept it as mem.h

>
> > @@ -0,0 +1,55 @@
> > +/*
> > + * (C) Copyright 2010 Samsung Electronics
> > + * Naveen Krishna Ch <ch.naveen@samsung.com>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + *
> > + * Note: This file contains the register description for Memory
> subsystem
> > + *      (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
> > + *
> > + *      Only SROMC is defined as of now
> > + */
> > +
> > +#ifndef __ASM_ARCH_MEM_H_
> > +#define __ASM_ARCH_MEM_H_
> > +
> > +#define SROM_DATA16_WIDTH(x)    (1<<((x*4)+0))
> > +#define SROM_BYTE_ADDR_MODE(x)  (1<<((x*4)+1))  /* 0-> Half-word base
> address*/
> > +                                               /* 1-> Byte base
> address*/
> > +#define SROM_WAIT_ENABLE(x)     (1<<((x*4)+2))
> > +#define SROM_BYTE_ENABLE(x)     (1<<((x*4)+3))
>
> Do you use all of these defines?
>
For Net support i use only  SROM_DATA16_WIDTH
But for NAND support we may need SROM_BYTE_ADDR_MODE
These Macros can serve for generic pupose.

>
> > +
> > +#define SMCBC_X_Tacs    (0x0)   /* 0clk         address set-up */
> > +#define SMCBC_X_Tcos    (0x4)   /* 4clk         chip selection set-up */
> > +#define SMCBC_X_Tacc    (0xe)   /* 14clk        access cycle */
> > +#define SMCBC_X_Tcoh    (0x1)   /* 1clk         chip selection hold */
> > +#define SMCBC_X_Tah     (0x4)   /* 4clk         address holding time */
> > +#define SMCBC_X_Tacp    (0x6)   /* 6clk         page mode access cycle
> */
> > +#define SMCBC_X_PMC     (0x0)   /* normal(1data)page mode configuration
> */
>
> Please don't use lowercase at define
>
I will change it.

> and () is unnecessary.
>
Should remove it

> and.. what mean X is?

The SROM has 6 banks, I used "X" to indicate that

>
> > +
> > +#define SMC_BC_X_CON    ((SMCBC_X_Tacs<<28)|(SMCBC_X_Tcos<<24)| \
> > +                        (SMCBC_X_Tacc<<16)|(SMCBC_X_Tcoh<<12)| \
> > +                        (SMCBC_X_Tah<<8)|(SMCBC_X_Tacp<<4)|    \
> > +                        (SMCBC_X_PMC))
> > +
> > +#ifndef __ASSEMBLY__
> > +struct s5pc1xx_sromc {
> > +       unsigned int    smc_bw;
> > +       unsigned int    smc_bc[6];
> > +};
> > +#endif /* __ASSEMBLY__ */
>
> smc_bw and smc_bc are already belong to sromc structure.
> is "smc_" really need?
> Please modify it to bw and bc or srom_bw and srom_bc (according to TRM)
>
I named it according to TRM. there it mentioned smc_bc.
I wil change it if u insist on srom_bc or so.

>
> > +
> > +#endif /* __ASM_ARCH_MEM_H_ */
> > --
> > 1.6.6
> >
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
> >
>
> Let me know your opinion

> Thanks,
> Minkyu Kang.

--
> from. prom.
> www.promsoft.net
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>



-- 
Shine bright,
(: Naveen Krishna Ch :)

[U-Boot] [PATCH 2/3] S5PC100: Function to configure the SROMC registers.

[Naveen Krishna Ch]

Hi Kang,

On 10 February 2010 11:43, Minkyu Kang <promsoft@gmail.com> wrote:

> Dear Naveen Krishna Ch,
>
> On 9 February 2010 18:38, Naveen Krishna Ch <ch.naveen@samsung.com> wrote:
> > From: Naveen Krishna CH <ch.naveen@samsung.com>
> >
> > Nand Flash, Ethernet, other features might need to configure the
> > SROMC registers accordingly.
> > The config_sromc() functions helps with this.
> >
> > Signed-off-by: Naveen Krishna Ch <ch.naveen <at> samsung.com>
>
> please fix ur e-mail address.
>
The Email ID is correct.

>
> > ---
> >  cpu/arm_cortexa8/s5pc1xx/Makefile  |    1 +
> >  cpu/arm_cortexa8/s5pc1xx/sromc.c   |   49
> ++++++++++++++++++++++++++++++++++++
> >  include/asm-arm/arch-s5pc1xx/mem.h |    3 ++
> >  3 files changed, 53 insertions(+), 0 deletions(-)
> >  create mode 100644 cpu/arm_cortexa8/s5pc1xx/sromc.c
> >
> > diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile
> b/cpu/arm_cortexa8/s5pc1xx/Makefile
> > index 4f922e6..0a6a9b4 100644
> > --- a/cpu/arm_cortexa8/s5pc1xx/Makefile
> > +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile
> > @@ -34,6 +34,7 @@ SOBJS += reset.o
> >  COBJS  += clock.o
> >  COBJS  += cpu_info.o
> >  COBJS  += timer.o
> > +COBJS  += sromc.o
> >
> >  SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> >  OBJS   := $(addprefix $(obj),$(COBJS) $(SOBJS))
> > diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c
> b/cpu/arm_cortexa8/s5pc1xx/sromc.c
> > new file mode 100644
> > index 0000000..96ca9e0
> > --- /dev/null
> > +++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c
> > @@ -0,0 +1,49 @@
> > +/*
> > + * Copyright (C) 2010 Samsung Electronics
> > + * Naveen Krishna Ch <ch.naveen@samsung.com>
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/mem.h>
> > +
> > +/*
> > + * config_sromc() - select the proper SROMC Bank and configure the
> > + *                 band width control and bank control registers
> > + * srom_bank   - SROM Bank 0 to 5
> > + * smc_bw_conf  - SMC Band witdh reg configuration value
> > + * smc_bc_conf  - SMC Bank Control reg configuration value
> > + */
> > +void config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
> > +{
> > +       u32 tmp;
> > +       struct s5pc1xx_sromc *const srom =
> > +               (struct s5pc1xx_sromc *)S5PC100_SROMC_BASE;
>
> Please adds support S5PC110 together.
>
I wil add this and resend the patch.

>
> > +
> > +       /* Configure SMC_BW register to handle proper SROMC bank */
> > +       tmp = srom->smc_bw;
> > +       tmp &= ~(0xF << (srom_bank * 4));
> > +       tmp |= smc_bw_conf;
> > +       srom->smc_bw = tmp;
> > +
> > +       /* Configure SMC_BC register */
> > +       srom->smc_bc[srom_bank] = smc_bc_conf;
> > +}
> > diff --git a/include/asm-arm/arch-s5pc1xx/mem.h
> b/include/asm-arm/arch-s5pc1xx/mem.h
> > index 66272ff..99b2d2e 100644
> > --- a/include/asm-arm/arch-s5pc1xx/mem.h
> > +++ b/include/asm-arm/arch-s5pc1xx/mem.h
> > @@ -52,4 +52,7 @@ struct s5pc1xx_sromc {
> >  };
> >  #endif /* __ASSEMBLY__ */
> >
> > +/* Configure the Band Width and Bank Control Regs for required SROMC
> Bank */
> > +void config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
> > +
> >  #endif /* __ASM_ARCH_MEM_H_ */
> > --
> > 1.6.6
> >
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
> >
>
> Thanks
> Minkyu Kang
> --
> from. prom.
> www.promsoft.net
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>



-- 
Shine bright,
(: Naveen Krishna Ch :)

[U-Boot] [PATCH 2/3] S5PC100: Function to configure the SROMC registers.

[Minkyu Kang]

Dear

On 10 February 2010 15:31, Naveen Krishna Ch <naveenkrishna.ch@gmail.com> wrote:
> Hi Kang,
>
> On 10 February 2010 11:43, Minkyu Kang <promsoft@gmail.com> wrote:
>>
>> Dear Naveen Krishna Ch,
>>
>> On 9 February 2010 18:38, Naveen Krishna Ch <ch.naveen@samsung.com> wrote:
>> > From: Naveen Krishna CH <ch.naveen@samsung.com>
>> >
>> > Nand Flash, Ethernet, other features might need to configure the
>> > SROMC registers accordingly.
>> > The config_sromc() functions helps with this.
>> >
>> > Signed-off-by: Naveen Krishna Ch <ch.naveen <at> samsung.com>
>>
>> please fix ur e-mail address.
>
> The Email ID is correct.

ch.naveen <at> samsung.com is correct?
Please modify it to ch.naveen at samsung.com

>>
>> > ---
>> > ?cpu/arm_cortexa8/s5pc1xx/Makefile ?| ? ?1 +
>> > ?cpu/arm_cortexa8/s5pc1xx/sromc.c ? | ? 49
>> > ++++++++++++++++++++++++++++++++++++
>> > ?include/asm-arm/arch-s5pc1xx/mem.h | ? ?3 ++
>> > ?3 files changed, 53 insertions(+), 0 deletions(-)
>> > ?create mode 100644 cpu/arm_cortexa8/s5pc1xx/sromc.c
>> >
>> > diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile
>> > b/cpu/arm_cortexa8/s5pc1xx/Makefile
>> > index 4f922e6..0a6a9b4 100644
>> > --- a/cpu/arm_cortexa8/s5pc1xx/Makefile
>> > +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile
>> > @@ -34,6 +34,7 @@ SOBJS += reset.o
>> > ?COBJS ?+= clock.o
>> > ?COBJS ?+= cpu_info.o
>> > ?COBJS ?+= timer.o
>> > +COBJS ?+= sromc.o
>> >
>> > ?SRCS ? := $(SOBJS:.o=.S) $(COBJS:.o=.c)
>> > ?OBJS ? := $(addprefix $(obj),$(COBJS) $(SOBJS))
>> > diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c
>> > b/cpu/arm_cortexa8/s5pc1xx/sromc.c
>> > new file mode 100644
>> > index 0000000..96ca9e0
>> > --- /dev/null
>> > +++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c
>> > @@ -0,0 +1,49 @@
>> > +/*
>> > + * Copyright (C) 2010 Samsung Electronics
>> > + * Naveen Krishna Ch <ch.naveen@samsung.com>
>> > + *
>> > + * See file CREDITS for list of people who contributed to this
>> > + * project.
>> > + *
>> > + * This program is free software; you can redistribute it and/or
>> > + * modify it under the terms of the GNU General Public License as
>> > + * published by the Free Software Foundation; either version 2 of
>> > + * the License, or (at your option) any later version.
>> > + *
>> > + * This program is distributed in the hope that it will be useful,
>> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
>> > + * GNU General Public License for more details.
>> > + *
>> > + * You should have received a copy of the GNU General Public License
>> > + * along with this program; if not, write to the Free Software
>> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> > + * MA 02111-1307 USA
>> > + */
>> > +
>> > +#include <common.h>
>> > +#include <asm/io.h>
>> > +#include <asm/arch/mem.h>
>> > +
>> > +/*
>> > + * config_sromc() - select the proper SROMC Bank and configure the
>> > + * ? ? ? ? ? ? ? ? band width control and bank control registers
>> > + * srom_bank ? - SROM Bank 0 to 5
>> > + * smc_bw_conf ?- SMC Band witdh reg configuration value
>> > + * smc_bc_conf ?- SMC Bank Control reg configuration value
>> > + */
>> > +void config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
>> > +{
>> > + ? ? ? u32 tmp;
>> > + ? ? ? struct s5pc1xx_sromc *const srom =
>> > + ? ? ? ? ? ? ? (struct s5pc1xx_sromc *)S5PC100_SROMC_BASE;
>>
>> Please adds support S5PC110 together.
>
> I wil add this and resend the patch.
>>
>> > +
>> > + ? ? ? /* Configure SMC_BW register to handle proper SROMC bank */
>> > + ? ? ? tmp = srom->smc_bw;
>> > + ? ? ? tmp &= ~(0xF << (srom_bank * 4));
>> > + ? ? ? tmp |= smc_bw_conf;
>> > + ? ? ? srom->smc_bw = tmp;
>> > +
>> > + ? ? ? /* Configure SMC_BC register */
>> > + ? ? ? srom->smc_bc[srom_bank] = smc_bc_conf;
>> > +}
>> > diff --git a/include/asm-arm/arch-s5pc1xx/mem.h
>> > b/include/asm-arm/arch-s5pc1xx/mem.h
>> > index 66272ff..99b2d2e 100644
>> > --- a/include/asm-arm/arch-s5pc1xx/mem.h
>> > +++ b/include/asm-arm/arch-s5pc1xx/mem.h
>> > @@ -52,4 +52,7 @@ struct s5pc1xx_sromc {
>> > ?};
>> > ?#endif /* __ASSEMBLY__ */
>> >
>> > +/* Configure the Band Width and Bank Control Regs for required SROMC
>> > Bank */
>> > +void config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
>> > +
>> > ?#endif /* __ASM_ARCH_MEM_H_ */
>> > --
>> > 1.6.6
>> >
>> > _______________________________________________
>> > U-Boot mailing list
>> > U-Boot at lists.denx.de
>> > http://lists.denx.de/mailman/listinfo/u-boot
>> >
>>
>> Thanks
>> Minkyu Kang
>> --
>> from. prom.
>> www.promsoft.net
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>
>
>
> --
> Shine bright,
> (: Naveen Krishna Ch :)
>

Thanks
Minkyu Kang
-- 
from. prom.
www.promsoft.net

[U-Boot] [PATCH 1/3] S5PC100: Memory SubSystem Header file, register description(SROMC).

[Minkyu Kang]

Dear Naveen Krishna Ch,

On 10 February 2010 15:16, Naveen Krishna Ch <naveenkrishna.ch@gmail.com> wrote:
> Hi Kang,
>
> On 10 February 2010 11:18, Minkyu Kang <promsoft@gmail.com> wrote:
>>
>> Dear Naveen Krishna Ch,
>>
>> On 9 February 2010 18:34, Naveen Krishna Ch <ch.naveen@samsung.com> wrote:
>> > From: Naveen Krishna CH <ch.naveen@samsung.com>
>> >
>> > Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand,
>> > NAND Flash, DDRs.
>> > mem.h is a common place for the register description of Memory subsystem
>> > of S5PC100.
>> > Note: Only SROM related registers are descibed now.
>> >
>> > Signed-off-by: Naveen Krishna Ch <ch.naveen <at> samsung.com>
>> > ---
>> > ?include/asm-arm/arch-s5pc1xx/mem.h | ? 55
>> > ++++++++++++++++++++++++++++++++++++
>> > ?1 files changed, 55 insertions(+), 0 deletions(-)
>> > ?create mode 100644 include/asm-arm/arch-s5pc1xx/mem.h
>> >
>> > diff --git a/include/asm-arm/arch-s5pc1xx/mem.h
>> > b/include/asm-arm/arch-s5pc1xx/mem.h
>> > new file mode 100644
>> > index 0000000..66272ff
>> > --- /dev/null
>> > +++ b/include/asm-arm/arch-s5pc1xx/mem.h
>>
>> I think srom.h is better than mem.h.
>
> As the SMC of S5PC100 is supporting several memories SRAM, SROM, NAND, NOR,
> DDR. I kept it as mem.h

So what?
This patch add about sromc. (not another memories)
If need,  separate each controller.

>>
>> > @@ -0,0 +1,55 @@
>> > +/*
>> > + * (C) Copyright 2010 Samsung Electronics
>> > + * Naveen Krishna Ch <ch.naveen@samsung.com>
>> > + *
>> > + * This program is free software; you can redistribute it and/or
>> > + * modify it under the terms of the GNU General Public License as
>> > + * published by the Free Software Foundation; either version 2 of
>> > + * the License, or (at your option) any later version.
>> > + *
>> > + * This program is distributed in the hope that it will be useful,
>> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
>> > + * GNU General Public License for more details.
>> > + *
>> > + * You should have received a copy of the GNU General Public License
>> > + * along with this program; if not, write to the Free Software
>> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> > + * MA 02111-1307 USA
>> > + *
>> > + * Note: This file contains the register description for Memory
>> > subsystem
>> > + * ? ? ?(SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
>> > + *
>> > + * ? ? ?Only SROMC is defined as of now
>> > + */
>> > +
>> > +#ifndef __ASM_ARCH_MEM_H_
>> > +#define __ASM_ARCH_MEM_H_
>> > +
>> > +#define SROM_DATA16_WIDTH(x) ? ?(1<<((x*4)+0))
>> > +#define SROM_BYTE_ADDR_MODE(x) ?(1<<((x*4)+1)) ?/* 0-> Half-word base
>> > address*/
>> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? /* 1-> Byte base
>> > address*/
>> > +#define SROM_WAIT_ENABLE(x) ? ? (1<<((x*4)+2))
>> > +#define SROM_BYTE_ENABLE(x) ? ? (1<<((x*4)+3))
>>
>> Do you use all of these defines?
>
> For Net support i use only ?SROM_DATA16_WIDTH
> But for NAND support we may need SROM_BYTE_ADDR_MODE
> These Macros can serve for generic pupose.
>>
>> > +
>> > +#define SMCBC_X_Tacs ? ?(0x0) ? /* 0clk ? ? ? ? address set-up */
>> > +#define SMCBC_X_Tcos ? ?(0x4) ? /* 4clk ? ? ? ? chip selection set-up
>> > */
>> > +#define SMCBC_X_Tacc ? ?(0xe) ? /* 14clk ? ? ? ?access cycle */
>> > +#define SMCBC_X_Tcoh ? ?(0x1) ? /* 1clk ? ? ? ? chip selection hold */
>> > +#define SMCBC_X_Tah ? ? (0x4) ? /* 4clk ? ? ? ? address holding time */
>> > +#define SMCBC_X_Tacp ? ?(0x6) ? /* 6clk ? ? ? ? page mode access cycle
>> > */
>> > +#define SMCBC_X_PMC ? ? (0x0) ? /* normal(1data)page mode configuration
>> > */
>>
>> Please don't use lowercase at define
>
> I will change it.
>>
>> and () is unnecessary.
>
> Should remove it
>>
>> and.. what mean X is?
>
> The SROM has 6 banks, I used "X" to indicate that

then, it must be different each banks.
but your code set same value at all banks (Almost hard code)
Please modify to can set values each banks.

And one more question, what mean SMCBC is?

>>
>> > +
>> > +#define SMC_BC_X_CON ? ?((SMCBC_X_Tacs<<28)|(SMCBC_X_Tcos<<24)| \
>> > + ? ? ? ? ? ? ? ? ? ? ? ?(SMCBC_X_Tacc<<16)|(SMCBC_X_Tcoh<<12)| \
>> > + ? ? ? ? ? ? ? ? ? ? ? ?(SMCBC_X_Tah<<8)|(SMCBC_X_Tacp<<4)| ? ?\
>> > + ? ? ? ? ? ? ? ? ? ? ? ?(SMCBC_X_PMC))
>> > +
>> > +#ifndef __ASSEMBLY__
>> > +struct s5pc1xx_sromc {
>> > + ? ? ? unsigned int ? ?smc_bw;
>> > + ? ? ? unsigned int ? ?smc_bc[6];
>> > +};
>> > +#endif /* __ASSEMBLY__ */
>>
>> smc_bw and smc_bc are already belong to sromc structure.
>> is "smc_" really need?
>> Please modify it to bw and bc or srom_bw and srom_bc (according to TRM)
>
> I named it according to TRM. there it mentioned smc_bc.
> I wil change it if u insist on srom_bc or so.

My TRM mentioned srom_bc. (what is your TRM version?)

>>
>> > +
>> > +#endif /* __ASM_ARCH_MEM_H_ */
>> > --
>> > 1.6.6
>> >
>> > _______________________________________________
>> > U-Boot mailing list
>> > U-Boot at lists.denx.de
>> > http://lists.denx.de/mailman/listinfo/u-boot
>> >
>>
> Let me know your opinion
>>
>> Thanks,
>> Minkyu Kang.
>>
>> --
>> from. prom.
>> www.promsoft.net
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>
>
>
> --
> Shine bright,
> (: Naveen Krishna Ch :)
>

Thanks
Minkyu Kang
-- 
from. prom.
www.promsoft.net

[U-Boot] [PATCH 2/3] S5PC100: Function to configure the SROMC registers.

[Minkyu Kang]

Naveen Krishna Ch,

On 10 February 2010 15:52, Minkyu Kang <promsoft@gmail.com> wrote:
> Dear
>
> On 10 February 2010 15:31, Naveen Krishna Ch <naveenkrishna.ch@gmail.com> wrote:
>> Hi Kang,
>>
>> On 10 February 2010 11:43, Minkyu Kang <promsoft@gmail.com> wrote:
>>>
>>> Dear Naveen Krishna Ch,
>>>
>>> On 9 February 2010 18:38, Naveen Krishna Ch <ch.naveen@samsung.com> wrote:
>>> > From: Naveen Krishna CH <ch.naveen@samsung.com>
>>> >
>>> > Nand Flash, Ethernet, other features might need to configure the
>>> > SROMC registers accordingly.
>>> > The config_sromc() functions helps with this.
>>> >
>>> > Signed-off-by: Naveen Krishna Ch <ch.naveen <at> samsung.com>
>>>
>>> please fix ur e-mail address.
>>
>> The Email ID is correct.
>
> ch.naveen <at> samsung.com is correct?
> Please modify it to ch.naveen at samsung.com
>
>>>
>>> > ---
>>> > ?cpu/arm_cortexa8/s5pc1xx/Makefile ?| ? ?1 +
>>> > ?cpu/arm_cortexa8/s5pc1xx/sromc.c ? | ? 49
>>> > ++++++++++++++++++++++++++++++++++++
>>> > ?include/asm-arm/arch-s5pc1xx/mem.h | ? ?3 ++
>>> > ?3 files changed, 53 insertions(+), 0 deletions(-)
>>> > ?create mode 100644 cpu/arm_cortexa8/s5pc1xx/sromc.c
>>> >
>>> > diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile
>>> > b/cpu/arm_cortexa8/s5pc1xx/Makefile
>>> > index 4f922e6..0a6a9b4 100644
>>> > --- a/cpu/arm_cortexa8/s5pc1xx/Makefile
>>> > +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile
>>> > @@ -34,6 +34,7 @@ SOBJS += reset.o
>>> > ?COBJS ?+= clock.o
>>> > ?COBJS ?+= cpu_info.o
>>> > ?COBJS ?+= timer.o
>>> > +COBJS ?+= sromc.o
>>> >
>>> > ?SRCS ? := $(SOBJS:.o=.S) $(COBJS:.o=.c)
>>> > ?OBJS ? := $(addprefix $(obj),$(COBJS) $(SOBJS))
>>> > diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c
>>> > b/cpu/arm_cortexa8/s5pc1xx/sromc.c
>>> > new file mode 100644
>>> > index 0000000..96ca9e0
>>> > --- /dev/null
>>> > +++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c
>>> > @@ -0,0 +1,49 @@
>>> > +/*
>>> > + * Copyright (C) 2010 Samsung Electronics
>>> > + * Naveen Krishna Ch <ch.naveen@samsung.com>
>>> > + *
>>> > + * See file CREDITS for list of people who contributed to this
>>> > + * project.
>>> > + *
>>> > + * This program is free software; you can redistribute it and/or
>>> > + * modify it under the terms of the GNU General Public License as
>>> > + * published by the Free Software Foundation; either version 2 of
>>> > + * the License, or (at your option) any later version.
>>> > + *
>>> > + * This program is distributed in the hope that it will be useful,
>>> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
>>> > + * GNU General Public License for more details.
>>> > + *
>>> > + * You should have received a copy of the GNU General Public License
>>> > + * along with this program; if not, write to the Free Software
>>> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>>> > + * MA 02111-1307 USA
>>> > + */
>>> > +
>>> > +#include <common.h>
>>> > +#include <asm/io.h>
>>> > +#include <asm/arch/mem.h>
>>> > +
>>> > +/*
>>> > + * config_sromc() - select the proper SROMC Bank and configure the
>>> > + * ? ? ? ? ? ? ? ? band width control and bank control registers
>>> > + * srom_bank ? - SROM Bank 0 to 5
>>> > + * smc_bw_conf ?- SMC Band witdh reg configuration value
>>> > + * smc_bc_conf ?- SMC Bank Control reg configuration value
>>> > + */
>>> > +void config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)

one more thing.
please add prefix like s5pc1xx_config_sromc.

>>> > +{
>>> > + ? ? ? u32 tmp;
>>> > + ? ? ? struct s5pc1xx_sromc *const srom =
>>> > + ? ? ? ? ? ? ? (struct s5pc1xx_sromc *)S5PC100_SROMC_BASE;
>>>
>>> Please adds support S5PC110 together.
>>
>> I wil add this and resend the patch.
>>>
>>> > +
>>> > + ? ? ? /* Configure SMC_BW register to handle proper SROMC bank */
>>> > + ? ? ? tmp = srom->smc_bw;
>>> > + ? ? ? tmp &= ~(0xF << (srom_bank * 4));
>>> > + ? ? ? tmp |= smc_bw_conf;
>>> > + ? ? ? srom->smc_bw = tmp;
>>> > +
>>> > + ? ? ? /* Configure SMC_BC register */
>>> > + ? ? ? srom->smc_bc[srom_bank] = smc_bc_conf;
>>> > +}
>>> > diff --git a/include/asm-arm/arch-s5pc1xx/mem.h
>>> > b/include/asm-arm/arch-s5pc1xx/mem.h
>>> > index 66272ff..99b2d2e 100644
>>> > --- a/include/asm-arm/arch-s5pc1xx/mem.h
>>> > +++ b/include/asm-arm/arch-s5pc1xx/mem.h
>>> > @@ -52,4 +52,7 @@ struct s5pc1xx_sromc {
>>> > ?};
>>> > ?#endif /* __ASSEMBLY__ */
>>> >
>>> > +/* Configure the Band Width and Bank Control Regs for required SROMC
>>> > Bank */
>>> > +void config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
>>> > +
>>> > ?#endif /* __ASM_ARCH_MEM_H_ */
>>> > --
>>> > 1.6.6
>>> >
>>> > _______________________________________________
>>> > U-Boot mailing list
>>> > U-Boot at lists.denx.de
>>> > http://lists.denx.de/mailman/listinfo/u-boot
>>> >
>>>
>>> Thanks
>>> Minkyu Kang
>>> --
>>> from. prom.
>>> www.promsoft.net
>>> _______________________________________________
>>> U-Boot mailing list
>>> U-Boot at lists.denx.de
>>> http://lists.denx.de/mailman/listinfo/u-boot
>>
>>
>>
>> --
>> Shine bright,
>> (: Naveen Krishna Ch :)
>>
>
> Thanks
> Minkyu Kang
> --
> from. prom.
> www.promsoft.net
>

Thanks
Minkyu Kang
-- 
from. prom.
www.promsoft.net

[U-Boot] [PATCH 2/3] S5PC100: Function to configure the SROMC registers.

[Naveen Krishna Ch]

Hi Kang,

On 10 February 2010 16:06, Minkyu Kang <promsoft@gmail.com> wrote:

> Naveen Krishna Ch,
>
> On 10 February 2010 15:52, Minkyu Kang <promsoft@gmail.com> wrote:
> > Dear
> >
> > On 10 February 2010 15:31, Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> wrote:
> >> Hi Kang,
> >>
> >> On 10 February 2010 11:43, Minkyu Kang <promsoft@gmail.com> wrote:
> >>>
> >>> Dear Naveen Krishna Ch,
> >>>
> >>> On 9 February 2010 18:38, Naveen Krishna Ch <ch.naveen@samsung.com>
> wrote:
> >>> > From: Naveen Krishna CH <ch.naveen@samsung.com>
> >>> >
> >>> > Nand Flash, Ethernet, other features might need to configure the
> >>> > SROMC registers accordingly.
> >>> > The config_sromc() functions helps with this.
> >>> >
> >>> > Signed-off-by: Naveen Krishna Ch <ch.naveen <at> samsung.com>
> >>>
> >>> please fix ur e-mail address.
> >>
> >> The Email ID is correct.
> >
> > ch.naveen <at> samsung.com is correct?
> > Please modify it to ch.naveen at samsung.com
>
I wil change it, thank you

>
> >
> >>>
> >>> > ---
> >>> >  cpu/arm_cortexa8/s5pc1xx/Makefile  |    1 +
> >>> >  cpu/arm_cortexa8/s5pc1xx/sromc.c   |   49
> >>> > ++++++++++++++++++++++++++++++++++++
> >>> >  include/asm-arm/arch-s5pc1xx/mem.h |    3 ++
> >>> >  3 files changed, 53 insertions(+), 0 deletions(-)
> >>> >  create mode 100644 cpu/arm_cortexa8/s5pc1xx/sromc.c
> >>> >
> >>> > diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile
> >>> > b/cpu/arm_cortexa8/s5pc1xx/Makefile
> >>> > index 4f922e6..0a6a9b4 100644
> >>> > --- a/cpu/arm_cortexa8/s5pc1xx/Makefile
> >>> > +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile
> >>> > @@ -34,6 +34,7 @@ SOBJS += reset.o
> >>> >  COBJS  += clock.o
> >>> >  COBJS  += cpu_info.o
> >>> >  COBJS  += timer.o
> >>> > +COBJS  += sromc.o
> >>> >
> >>> >  SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> >>> >  OBJS   := $(addprefix $(obj),$(COBJS) $(SOBJS))
> >>> > diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c
> >>> > b/cpu/arm_cortexa8/s5pc1xx/sromc.c
> >>> > new file mode 100644
> >>> > index 0000000..96ca9e0
> >>> > --- /dev/null
> >>> > +++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c
> >>> > @@ -0,0 +1,49 @@
> >>> > +/*
> >>> > + * Copyright (C) 2010 Samsung Electronics
> >>> > + * Naveen Krishna Ch <ch.naveen@samsung.com>
> >>> > + *
> >>> > + * See file CREDITS for list of people who contributed to this
> >>> > + * project.
> >>> > + *
> >>> > + * This program is free software; you can redistribute it and/or
> >>> > + * modify it under the terms of the GNU General Public License as
> >>> > + * published by the Free Software Foundation; either version 2 of
> >>> > + * the License, or (at your option) any later version.
> >>> > + *
> >>> > + * This program is distributed in the hope that it will be useful,
> >>> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >>> > + * GNU General Public License for more details.
> >>> > + *
> >>> > + * You should have received a copy of the GNU General Public License
> >>> > + * along with this program; if not, write to the Free Software
> >>> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> >>> > + * MA 02111-1307 USA
> >>> > + */
> >>> > +
> >>> > +#include <common.h>
> >>> > +#include <asm/io.h>
> >>> > +#include <asm/arch/mem.h>
> >>> > +
> >>> > +/*
> >>> > + * config_sromc() - select the proper SROMC Bank and configure the
> >>> > + *                 band width control and bank control registers
> >>> > + * srom_bank   - SROM Bank 0 to 5
> >>> > + * smc_bw_conf  - SMC Band witdh reg configuration value
> >>> > + * smc_bc_conf  - SMC Bank Control reg configuration value
> >>> > + */
> >>> > +void config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
>
> one more thing.
> please add prefix like s5pc1xx_config_sromc.
>
I wil change this too and resend all the patches.

>
> >>> > +{
> >>> > +       u32 tmp;
> >>> > +       struct s5pc1xx_sromc *const srom =
> >>> > +               (struct s5pc1xx_sromc *)S5PC100_SROMC_BASE;
> >>>
> >>> Please adds support S5PC110 together.
> >>
> >> I wil add this and resend the patch.
> >>>
> >>> > +
> >>> > +       /* Configure SMC_BW register to handle proper SROMC bank */
> >>> > +       tmp = srom->smc_bw;
> >>> > +       tmp &= ~(0xF << (srom_bank * 4));
> >>> > +       tmp |= smc_bw_conf;
> >>> > +       srom->smc_bw = tmp;
> >>> > +
> >>> > +       /* Configure SMC_BC register */
> >>> > +       srom->smc_bc[srom_bank] = smc_bc_conf;
> >>> > +}
> >>> > diff --git a/include/asm-arm/arch-s5pc1xx/mem.h
> >>> > b/include/asm-arm/arch-s5pc1xx/mem.h
> >>> > index 66272ff..99b2d2e 100644
> >>> > --- a/include/asm-arm/arch-s5pc1xx/mem.h
> >>> > +++ b/include/asm-arm/arch-s5pc1xx/mem.h
> >>> > @@ -52,4 +52,7 @@ struct s5pc1xx_sromc {
> >>> >  };
> >>> >  #endif /* __ASSEMBLY__ */
> >>> >
> >>> > +/* Configure the Band Width and Bank Control Regs for required SROMC
> >>> > Bank */
> >>> > +void config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
> >>> > +
> >>> >  #endif /* __ASM_ARCH_MEM_H_ */
> >>> > --
> >>> > 1.6.6
> >>> >
> >>> > _______________________________________________
> >>> > U-Boot mailing list
> >>> > U-Boot at lists.denx.de
> >>> > http://lists.denx.de/mailman/listinfo/u-boot
> >>> >
> >>>
> >>> Thanks
> >>> Minkyu Kang
> >>> --
> >>> from. prom.
> >>> www.promsoft.net
> >>> _______________________________________________
> >>> U-Boot mailing list
> >>> U-Boot at lists.denx.de
> >>> http://lists.denx.de/mailman/listinfo/u-boot
> >>
> >>
> >>
> >> --
> >> Shine bright,
> >> (: Naveen Krishna Ch :)
> >>
> >
> > Thanks
> > Minkyu Kang
> > --
> > from. prom.
> > www.promsoft.net
> >
>
> Thanks
> Minkyu Kang
> --
> from. prom.
> www.promsoft.net
>



-- 
Shine bright,
(: Naveen Krishna Ch :)

[U-Boot] [PATCH 1/3] S5PC100: Memory SubSystem Header file, register description(SROMC).

[Naveen Krishna Ch]

HI Kang,

On 10 February 2010 16:04, Minkyu Kang <promsoft@gmail.com> wrote:

> Dear Naveen Krishna Ch,
>
> On 10 February 2010 15:16, Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> wrote:
> > Hi Kang,
> >
> > On 10 February 2010 11:18, Minkyu Kang <promsoft@gmail.com> wrote:
> >>
> >> Dear Naveen Krishna Ch,
> >>
> >> On 9 February 2010 18:34, Naveen Krishna Ch <ch.naveen@samsung.com>
> wrote:
> >> > From: Naveen Krishna CH <ch.naveen@samsung.com>
> >> >
> >> > Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand,
> >> > NAND Flash, DDRs.
> >> > mem.h is a common place for the register description of Memory
> subsystem
> >> > of S5PC100.
> >> > Note: Only SROM related registers are descibed now.
> >> >
> >> > Signed-off-by: Naveen Krishna Ch <ch.naveen <at> samsung.com>
> >> > ---
> >> >  include/asm-arm/arch-s5pc1xx/mem.h |   55
> >> > ++++++++++++++++++++++++++++++++++++
> >> >  1 files changed, 55 insertions(+), 0 deletions(-)
> >> >  create mode 100644 include/asm-arm/arch-s5pc1xx/mem.h
> >> >
> >> > diff --git a/include/asm-arm/arch-s5pc1xx/mem.h
> >> > b/include/asm-arm/arch-s5pc1xx/mem.h
> >> > new file mode 100644
> >> > index 0000000..66272ff
> >> > --- /dev/null
> >> > +++ b/include/asm-arm/arch-s5pc1xx/mem.h
> >>
> >> I think srom.h is better than mem.h.
> >
> > As the SMC of S5PC100 is supporting several memories SRAM, SROM, NAND,
> NOR,
> > DDR. I kept it as mem.h
>
> So what?
> This patch add about sromc. (not another memories)
> If need,  separate each controller.
>
I have renamed it according to the TRM (smc.h) as it is SMC subsystem.

>
> >>
> >> > @@ -0,0 +1,55 @@
> >> > +/*
> >> > + * (C) Copyright 2010 Samsung Electronics
> >> > + * Naveen Krishna Ch <ch.naveen@samsung.com>
> >> > + *
> >> > + * This program is free software; you can redistribute it and/or
> >> > + * modify it under the terms of the GNU General Public License as
> >> > + * published by the Free Software Foundation; either version 2 of
> >> > + * the License, or (at your option) any later version.
> >> > + *
> >> > + * This program is distributed in the hope that it will be useful,
> >> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >> > + * GNU General Public License for more details.
> >> > + *
> >> > + * You should have received a copy of the GNU General Public License
> >> > + * along with this program; if not, write to the Free Software
> >> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> >> > + * MA 02111-1307 USA
> >> > + *
> >> > + * Note: This file contains the register description for Memory
> >> > subsystem
> >> > + *      (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
> >> > + *
> >> > + *      Only SROMC is defined as of now
> >> > + */
> >> > +
> >> > +#ifndef __ASM_ARCH_MEM_H_
> >> > +#define __ASM_ARCH_MEM_H_
> >> > +
> >> > +#define SROM_DATA16_WIDTH(x)    (1<<((x*4)+0))
> >> > +#define SROM_BYTE_ADDR_MODE(x)  (1<<((x*4)+1))  /* 0-> Half-word base
> >> > address*/
> >> > +                                               /* 1-> Byte base
> >> > address*/
> >> > +#define SROM_WAIT_ENABLE(x)     (1<<((x*4)+2))
> >> > +#define SROM_BYTE_ENABLE(x)     (1<<((x*4)+3))
> >>
> >> Do you use all of these defines?
> >
> > For Net support i use only  SROM_DATA16_WIDTH
> > But for NAND support we may need SROM_BYTE_ADDR_MODE
> > These Macros can serve for generic pupose.
> >>
> >> > +
> >> > +#define SMCBC_X_Tacs    (0x0)   /* 0clk         address set-up */
> >> > +#define SMCBC_X_Tcos    (0x4)   /* 4clk         chip selection set-up
> >> > */
> >> > +#define SMCBC_X_Tacc    (0xe)   /* 14clk        access cycle */
> >> > +#define SMCBC_X_Tcoh    (0x1)   /* 1clk         chip selection hold
> */
> >> > +#define SMCBC_X_Tah     (0x4)   /* 4clk         address holding time
> */
> >> > +#define SMCBC_X_Tacp    (0x6)   /* 6clk         page mode access
> cycle
> >> > */
> >> > +#define SMCBC_X_PMC     (0x0)   /* normal(1data)page mode
> configuration
> >> > */
> >>
> >> Please don't use lowercase at define
> >
> > I will change it.
> >>
> >> and () is unnecessary.
> >
> > Should remove it
> >>
> >> and.. what mean X is?
> >
> > The SROM has 6 banks, I used "X" to indicate that
>
> then, it must be different each banks.
> but your code set same value at all banks (Almost hard code)
> Please modify to can set values each banks.
>
For all the SROM bank configuration registers the values remains same.
As all the banks uses HCLK D0 as the base clock.
So, Same value is applicable to all SROM Banks.

>
> And one more question, what mean SMCBC is?
>
Sorry i changed it in V2 patch.

>
> >>
> >> > +
> >> > +#define SMC_BC_X_CON    ((SMCBC_X_Tacs<<28)|(SMCBC_X_Tcos<<24)| \
> >> > +                        (SMCBC_X_Tacc<<16)|(SMCBC_X_Tcoh<<12)| \
> >> > +                        (SMCBC_X_Tah<<8)|(SMCBC_X_Tacp<<4)|    \
> >> > +                        (SMCBC_X_PMC))
> >> > +
> >> > +#ifndef __ASSEMBLY__
> >> > +struct s5pc1xx_sromc {
> >> > +       unsigned int    smc_bw;
> >> > +       unsigned int    smc_bc[6];
> >> > +};
> >> > +#endif /* __ASSEMBLY__ */
> >>
> >> smc_bw and smc_bc are already belong to sromc structure.
> >> is "smc_" really need?
> >> Please modify it to bw and bc or srom_bw and srom_bc (according to TRM)
> >
> > I named it according to TRM. there it mentioned smc_bc.
> > I wil change it if u insist on srom_bc or so.
>
> My TRM mentioned srom_bc. (what is your TRM version?)
>
I have a TRM version 1.02 and it says SMC_BC/BW

>
> >>
> >> > +
> >> > +#endif /* __ASM_ARCH_MEM_H_ */
> >> > --
> >> > 1.6.6
> >> >
> >> > _______________________________________________
> >> > U-Boot mailing list
> >> > U-Boot at lists.denx.de
> >> > http://lists.denx.de/mailman/listinfo/u-boot
> >> >
> >>
> > Let me know your opinion
> >>
> >> Thanks,
> >> Minkyu Kang.
> >>
> >> --
> >> from. prom.
> >> www.promsoft.net
> >> _______________________________________________
> >> U-Boot mailing list
> >> U-Boot at lists.denx.de
> >> http://lists.denx.de/mailman/listinfo/u-boot
> >
> >
> >
> > --
> > Shine bright,
> > (: Naveen Krishna Ch :)
> >
>
> Thanks
> Minkyu Kang
> --
> from. prom.
> www.promsoft.net
>



-- 
Shine bright,
(: Naveen Krishna Ch :)