[PATCH 0/7] msm: Support for Qualcomm MSM8960

[PATCH 0/7] msm: Support for Qualcomm MSM8960

[Stepan Moskovchenko]

Add initial support for the Qualcomm MSM8960 target.

Stepan Moskovchenko (7):
  msm: io: I/O register definitions for MSM8960
  msm: Physical offset for MSM8960
  msm: irqs-8960: Interrupt map for MSM8960
  msm: Board file for MSM8960 simulator
  msm: timer: Timer support for MSM8960
  msm: Makefile cleanup
  msm: Build support for the MSM8960 target

 arch/arm/mach-msm/Kconfig                       |   16 ++
 arch/arm/mach-msm/Makefile                      |   20 +-
 arch/arm/mach-msm/board-msm8960.c               |   71 ++++++
 arch/arm/mach-msm/include/mach/io.h             |    1 +
 arch/arm/mach-msm/include/mach/irqs-8960.h      |  293 +++++++++++++++++++++++
 arch/arm/mach-msm/include/mach/irqs.h           |    2 +
 arch/arm/mach-msm/include/mach/memory.h         |    2 +
 arch/arm/mach-msm/include/mach/msm_iomap-8960.h |   55 +++++
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    2 +
 arch/arm/mach-msm/io.c                          |   14 +
 arch/arm/mach-msm/timer.c                       |    3 +-
 11 files changed, 466 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/mach-msm/board-msm8960.c
 create mode 100644 arch/arm/mach-msm/include/mach/irqs-8960.h
 create mode 100644 arch/arm/mach-msm/include/mach/msm_iomap-8960.h

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 0/7] msm: Support for Qualcomm MSM8960

[Stepan Moskovchenko]

Add initial support for the Qualcomm MSM8960 target.

Stepan Moskovchenko (7):
  msm: io: I/O register definitions for MSM8960
  msm: Physical offset for MSM8960
  msm: irqs-8960: Interrupt map for MSM8960
  msm: Board file for MSM8960 simulator
  msm: timer: Timer support for MSM8960
  msm: Makefile cleanup
  msm: Build support for the MSM8960 target

 arch/arm/mach-msm/Kconfig                       |   16 ++
 arch/arm/mach-msm/Makefile                      |   20 +-
 arch/arm/mach-msm/board-msm8960.c               |   71 ++++++
 arch/arm/mach-msm/include/mach/io.h             |    1 +
 arch/arm/mach-msm/include/mach/irqs-8960.h      |  293 +++++++++++++++++++++++
 arch/arm/mach-msm/include/mach/irqs.h           |    2 +
 arch/arm/mach-msm/include/mach/memory.h         |    2 +
 arch/arm/mach-msm/include/mach/msm_iomap-8960.h |   55 +++++
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    2 +
 arch/arm/mach-msm/io.c                          |   14 +
 arch/arm/mach-msm/timer.c                       |    3 +-
 11 files changed, 466 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/mach-msm/board-msm8960.c
 create mode 100644 arch/arm/mach-msm/include/mach/irqs-8960.h
 create mode 100644 arch/arm/mach-msm/include/mach/msm_iomap-8960.h

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Stepan Moskovchenko]

Add the register address definitions for the basic hardware
blocks on the Qualcomm MSM8960 chip.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/io.h             |    1 +
 arch/arm/mach-msm/include/mach/msm_iomap-8960.h |   55 +++++++++++++++++++++++
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    2 +
 arch/arm/mach-msm/io.c                          |   14 ++++++
 4 files changed, 72 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/include/mach/msm_iomap-8960.h

diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index 7386e73..dc1b928 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -29,6 +29,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m
 void msm_map_qsd8x50_io(void);
 void msm_map_msm7x30_io(void);
 void msm_map_msm8x60_io(void);
+void msm_map_msm8960_io(void);

 extern unsigned int msm_shared_ram_phys;

diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
new file mode 100644
index 0000000..ca6bf90
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * The MSM peripherals are spread all over across 768MB of physical
+ * space, which makes just having a simple IO_ADDRESS macro to slide
+ * them into the right virtual location rough.  Instead, we will
+ * provide a master phys->virt mapping for peripherals here.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IOMAP_8960_H
+#define __ASM_ARCH_MSM_IOMAP_8960_H
+
+/* Physical base address and size of peripherals.
+ * Ordered by the virtual base addresses they will be mapped at.
+ *
+ * If you add or remove entries here, you'll want to edit the
+ * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
+ * changes.
+ *
+ */
+
+
+#define MSM_QGIC_DIST_BASE	IOMEM(0xF0000000)
+#define MSM_QGIC_DIST_PHYS	0x02000000
+#define MSM_QGIC_DIST_SIZE	SZ_4K
+
+#define MSM_QGIC_CPU_BASE	IOMEM(0xF0001000)
+#define MSM_QGIC_CPU_PHYS	0x02002000
+#define MSM_QGIC_CPU_SIZE	SZ_4K
+
+#define MSM_TMR_BASE		IOMEM(0xF0100000)
+#define MSM_TMR_PHYS		0x0200A000
+#define MSM_TMR_SIZE		(SZ_4K)
+
+#define MSM_TMR0_BASE		IOMEM(0xF0101000)
+#define MSM_TMR0_PHYS		0x0208A000
+#define MSM_TMR0_SIZE		(SZ_4K)
+
+#define MSM_GPT_BASE		(MSM_TMR_BASE + 0x4)
+#define MSM_DGT_BASE		(MSM_TMR_BASE + 0x24)
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 8e24dd8..4154a0a 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -49,6 +49,8 @@
 #include "msm_iomap-8x50.h"
 #elif defined(CONFIG_ARCH_MSM8X60)
 #include "msm_iomap-8x60.h"
+#elif defined(CONFIG_ARCH_MSM8960)
+#include "msm_iomap-8960.h"
 #else
 #include "msm_iomap-7x00.h"
 #endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index b826b6b..8254fc4 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -116,6 +116,20 @@ void __init msm_map_msm8x60_io(void)
 }
 #endif /* CONFIG_ARCH_MSM8X60 */

+#ifdef CONFIG_ARCH_MSM8960
+static struct map_desc msm8960_io_desc[] __initdata = {
+	MSM_DEVICE(QGIC_DIST),
+	MSM_DEVICE(QGIC_CPU),
+	MSM_DEVICE(TMR),
+	MSM_DEVICE(TMR0),
+};
+
+void __init msm_map_msm8960_io(void)
+{
+	iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc));
+}
+#endif /* CONFIG_ARCH_MSM8960 */
+
 #ifdef CONFIG_ARCH_MSM7X30
 static struct map_desc msm7x30_io_desc[] __initdata = {
 	MSM_DEVICE(VIC),
--
1.7.0.2

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Stepan Moskovchenko]

Add the register address definitions for the basic hardware
blocks on the Qualcomm MSM8960 chip.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/io.h             |    1 +
 arch/arm/mach-msm/include/mach/msm_iomap-8960.h |   55 +++++++++++++++++++++++
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    2 +
 arch/arm/mach-msm/io.c                          |   14 ++++++
 4 files changed, 72 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/include/mach/msm_iomap-8960.h

diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index 7386e73..dc1b928 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -29,6 +29,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m
 void msm_map_qsd8x50_io(void);
 void msm_map_msm7x30_io(void);
 void msm_map_msm8x60_io(void);
+void msm_map_msm8960_io(void);

 extern unsigned int msm_shared_ram_phys;

diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
new file mode 100644
index 0000000..ca6bf90
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * The MSM peripherals are spread all over across 768MB of physical
+ * space, which makes just having a simple IO_ADDRESS macro to slide
+ * them into the right virtual location rough.  Instead, we will
+ * provide a master phys->virt mapping for peripherals here.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IOMAP_8960_H
+#define __ASM_ARCH_MSM_IOMAP_8960_H
+
+/* Physical base address and size of peripherals.
+ * Ordered by the virtual base addresses they will be mapped at.
+ *
+ * If you add or remove entries here, you'll want to edit the
+ * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
+ * changes.
+ *
+ */
+
+
+#define MSM_QGIC_DIST_BASE	IOMEM(0xF0000000)
+#define MSM_QGIC_DIST_PHYS	0x02000000
+#define MSM_QGIC_DIST_SIZE	SZ_4K
+
+#define MSM_QGIC_CPU_BASE	IOMEM(0xF0001000)
+#define MSM_QGIC_CPU_PHYS	0x02002000
+#define MSM_QGIC_CPU_SIZE	SZ_4K
+
+#define MSM_TMR_BASE		IOMEM(0xF0100000)
+#define MSM_TMR_PHYS		0x0200A000
+#define MSM_TMR_SIZE		(SZ_4K)
+
+#define MSM_TMR0_BASE		IOMEM(0xF0101000)
+#define MSM_TMR0_PHYS		0x0208A000
+#define MSM_TMR0_SIZE		(SZ_4K)
+
+#define MSM_GPT_BASE		(MSM_TMR_BASE + 0x4)
+#define MSM_DGT_BASE		(MSM_TMR_BASE + 0x24)
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 8e24dd8..4154a0a 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -49,6 +49,8 @@
 #include "msm_iomap-8x50.h"
 #elif defined(CONFIG_ARCH_MSM8X60)
 #include "msm_iomap-8x60.h"
+#elif defined(CONFIG_ARCH_MSM8960)
+#include "msm_iomap-8960.h"
 #else
 #include "msm_iomap-7x00.h"
 #endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index b826b6b..8254fc4 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -116,6 +116,20 @@ void __init msm_map_msm8x60_io(void)
 }
 #endif /* CONFIG_ARCH_MSM8X60 */

+#ifdef CONFIG_ARCH_MSM8960
+static struct map_desc msm8960_io_desc[] __initdata = {
+	MSM_DEVICE(QGIC_DIST),
+	MSM_DEVICE(QGIC_CPU),
+	MSM_DEVICE(TMR),
+	MSM_DEVICE(TMR0),
+};
+
+void __init msm_map_msm8960_io(void)
+{
+	iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc));
+}
+#endif /* CONFIG_ARCH_MSM8960 */
+
 #ifdef CONFIG_ARCH_MSM7X30
 static struct map_desc msm7x30_io_desc[] __initdata = {
 	MSM_DEVICE(VIC),
--
1.7.0.2

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 2/7] msm: Physical offset for MSM8960

[Stepan Moskovchenko]

Add the physical memory offset value for the Qualcomm
MSM8960 chip.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/memory.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
index 070e17d..014bbd3 100644
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -25,6 +25,8 @@
 #define PHYS_OFFSET		UL(0x00200000)
 #elif defined(CONFIG_ARCH_MSM8X60)
 #define PHYS_OFFSET		UL(0x40200000)
+#elif defined(CONFIG_ARCH_MSM8960)
+#define PHYS_OFFSET		UL(0x40200000)
 #else
 #define PHYS_OFFSET		UL(0x10000000)
 #endif
--
1.7.0.2

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 2/7] msm: Physical offset for MSM8960

[Stepan Moskovchenko]

Add the physical memory offset value for the Qualcomm
MSM8960 chip.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/memory.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
index 070e17d..014bbd3 100644
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -25,6 +25,8 @@
 #define PHYS_OFFSET		UL(0x00200000)
 #elif defined(CONFIG_ARCH_MSM8X60)
 #define PHYS_OFFSET		UL(0x40200000)
+#elif defined(CONFIG_ARCH_MSM8960)
+#define PHYS_OFFSET		UL(0x40200000)
 #else
 #define PHYS_OFFSET		UL(0x10000000)
 #endif
--
1.7.0.2

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 3/7] msm: irqs-8960: Interrupt map for MSM8960

[Stepan Moskovchenko]

Add the interrupt map for the Qualcomm MSM8960 chip. This
chip has an interrupt map that is different from previous
targets.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/irqs-8960.h |  293 ++++++++++++++++++++++++++++
 arch/arm/mach-msm/include/mach/irqs.h      |    2 +
 2 files changed, 295 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/include/mach/irqs-8960.h

diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h
new file mode 100644
index 0000000..f4d8593
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8960.h
@@ -0,0 +1,293 @@
+/* Copyright (c) 2010 Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_8960_H
+#define __ASM_ARCH_MSM_IRQS_8960_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15:  STI/SGI (software triggered/generated interrupts)
+   16-31: PPI (private peripheral interrupts)
+   32+:   SPI (shared peripheral interrupts) */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_VGIC				(GIC_PPI_START + 0)
+#define INT_DEBUG_TIMER_EXP			(GIC_PPI_START + 1)
+#define INT_GP_TIMER_EXP			(GIC_PPI_START + 2)
+#define INT_GP_TIMER2_EXP			(GIC_PPI_START + 3)
+#define WDT0_ACCSCSSNBARK_INT			(GIC_PPI_START + 4)
+#define WDT1_ACCSCSSNBARK_INT			(GIC_PPI_START + 5)
+#define AVS_SVICINT				(GIC_PPI_START + 6)
+#define AVS_SVICINTSWDONE			(GIC_PPI_START + 7)
+#define CPU_DBGCPUXCOMMRXFULL			(GIC_PPI_START + 8)
+#define CPU_DBGCPUXCOMMTXEMPTY			(GIC_PPI_START + 9)
+#define CPU_SICCPUXPERFMONIRPTREQ		(GIC_PPI_START + 10)
+#define SC_AVSCPUXDOWN				(GIC_PPI_START + 11)
+#define SC_AVSCPUXUP				(GIC_PPI_START + 12)
+#define SC_SICCPUXACGIRPTREQ			(GIC_PPI_START + 13)
+#define SC_SICCPUXEXTFAULTIRPTREQ		(GIC_PPI_START + 14)
+/* PPI 15 is unused */
+
+#define SC_SICMPUIRPTREQ			(GIC_SPI_START + 0)
+#define SC_SICL2IRPTREQ				(GIC_SPI_START + 1)
+#define SC_SICL2PERFMONIRPTREQ			(GIC_SPI_START + 2)
+#define SC_SICAGCIRPTREQ			(GIC_SPI_START + 3)
+#define TLMM_APCC_DIR_CONN_IRQ_0		(GIC_SPI_START + 4)
+#define TLMM_APCC_DIR_CONN_IRQ_1		(GIC_SPI_START + 5)
+#define TLMM_APCC_DIR_CONN_IRQ_2		(GIC_SPI_START + 6)
+#define TLMM_APCC_DIR_CONN_IRQ_3		(GIC_SPI_START + 7)
+#define TLMM_APCC_DIR_CONN_IRQ_4		(GIC_SPI_START + 8)
+#define TLMM_APCC_DIR_CONN_IRQ_5		(GIC_SPI_START + 9)
+#define TLMM_APCC_DIR_CONN_IRQ_6		(GIC_SPI_START + 10)
+#define TLMM_APCC_DIR_CONN_IRQ_7		(GIC_SPI_START + 11)
+#define TLMM_APCC_DIR_CONN_IRQ_8		(GIC_SPI_START + 12)
+#define TLMM_APCC_DIR_CONN_IRQ_9		(GIC_SPI_START + 13)
+#define PM8921_SEC_IRQ_103			(GIC_SPI_START + 14)
+#define PM8018_SEC_IRQ_106			(GIC_SPI_START + 15)
+#define TLMM_APCC_SUMMARY_IRQ			(GIC_SPI_START + 16)
+#define SPDM_RT_1_IRQ				(GIC_SPI_START + 17)
+#define SPDM_DIAG_IRQ				(GIC_SPI_START + 18)
+#define RPM_APCC_CPU0_GP_HIGH_IRQ		(GIC_SPI_START + 19)
+#define RPM_APCC_CPU0_GP_MEDIUM_IRQ		(GIC_SPI_START + 20)
+#define RPM_APCC_CPU0_GP_LOW_IRQ		(GIC_SPI_START + 21)
+#define RPM_APCC_CPU0_WAKE_UP_IRQ		(GIC_SPI_START + 22)
+#define RPM_APCC_CPU1_GP_HIGH_IRQ		(GIC_SPI_START + 23)
+#define RPM_APCC_CPU1_GP_MEDIUM_IRQ		(GIC_SPI_START + 24)
+#define RPM_APCC_CPU1_GP_LOW_IRQ		(GIC_SPI_START + 25)
+#define RPM_APCC_CPU1_WAKE_UP_IRQ		(GIC_SPI_START + 26)
+#define SSBI2_2_SC_CPU0_SECURE_IRQ		(GIC_SPI_START + 27)
+#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ		(GIC_SPI_START + 28)
+#define SSBI2_1_SC_CPU0_SECURE_IRQ		(GIC_SPI_START + 29)
+#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ		(GIC_SPI_START + 30)
+#define MSMC_SC_SEC_CE_IRQ			(GIC_SPI_START + 31)
+#define MSMC_SC_PRI_CE_IRQ			(GIC_SPI_START + 32)
+#define SLIMBUS0_CORE_EE1_IRQ			(GIC_SPI_START + 33)
+#define SLIMBUS0_BAM_EE1_IRQ			(GIC_SPI_START + 34)
+#define Q6FW_WDOG_EXPIRED_IRQ			(GIC_SPI_START + 35)
+#define Q6SW_WDOG_EXPIRED_IRQ			(GIC_SPI_START + 36)
+#define MSS_TO_APPS_IRQ_0			(GIC_SPI_START + 37)
+#define MSS_TO_APPS_IRQ_1			(GIC_SPI_START + 38)
+#define MSS_TO_APPS_IRQ_2			(GIC_SPI_START + 39)
+#define MSS_TO_APPS_IRQ_3			(GIC_SPI_START + 40)
+#define MSS_TO_APPS_IRQ_4			(GIC_SPI_START + 41)
+#define MSS_TO_APPS_IRQ_5			(GIC_SPI_START + 42)
+#define MSS_TO_APPS_IRQ_6			(GIC_SPI_START + 43)
+#define MSS_TO_APPS_IRQ_7			(GIC_SPI_START + 44)
+#define MSS_TO_APPS_IRQ_8			(GIC_SPI_START + 45)
+#define MSS_TO_APPS_IRQ_9			(GIC_SPI_START + 46)
+#define VPE_IRQ					(GIC_SPI_START + 47)
+#define VFE_IRQ					(GIC_SPI_START + 48)
+#define VCODEC_IRQ				(GIC_SPI_START + 49)
+#define TV_ENC_IRQ				(GIC_SPI_START + 50)
+#define SMMU_VPE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 51)
+#define SMMU_VPE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 52)
+#define SMMU_VFE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 53)
+#define SMMU_VFE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 54)
+#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ		(GIC_SPI_START + 55)
+#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 56)
+#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ		(GIC_SPI_START + 57)
+#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 58)
+#define SMMU_ROT_CB_SC_SECURE_IRQ		(GIC_SPI_START + 59)
+#define SMMU_ROT_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 60)
+#define SMMU_MDP1_CB_SC_SECURE_IRQ		(GIC_SPI_START + 61)
+#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 62)
+#define SMMU_MDP0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 63)
+#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 64)
+#define SMMU_JPEGD_CB_SC_SECURE_IRQ		(GIC_SPI_START + 65)
+#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 66)
+#define SMMU_IJPEG_CB_SC_SECURE_IRQ		(GIC_SPI_START + 67)
+#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 68)
+#define SMMU_GFX3D_CB_SC_SECURE_IRQ		(GIC_SPI_START + 69)
+#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 70)
+#define SMMU_GFX2D0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 71)
+#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 72)
+#define ROT_IRQ					(GIC_SPI_START + 73)
+#define MMSS_FABRIC_IRQ				(GIC_SPI_START + 74)
+#define MDP_IRQ					(GIC_SPI_START + 75)
+#define JPEGD_IRQ				(GIC_SPI_START + 76)
+#define JPEG_IRQ				(GIC_SPI_START + 77)
+#define MMSS_IMEM_IRQ				(GIC_SPI_START + 78)
+#define HDMI_IRQ				(GIC_SPI_START + 79)
+#define GFX3D_IRQ				(GIC_SPI_START + 80)
+#define GFX2D0_IRQ				(GIC_SPI_START + 81)
+#define DSI1_IRQ				(GIC_SPI_START + 82)
+#define CSI_1_IRQ				(GIC_SPI_START + 83)
+#define CSI_0_IRQ				(GIC_SPI_START + 84)
+#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ		(GIC_SPI_START + 85)
+#define LPASS_SCSS_MIDI_IRQ			(GIC_SPI_START + 86)
+#define LPASS_Q6SS_WDOG_EXPIRED			(GIC_SPI_START + 87)
+#define LPASS_SCSS_GP_LOW_IRQ			(GIC_SPI_START + 88)
+#define LPASS_SCSS_GP_MEDIUM_IRQ		(GIC_SPI_START + 89)
+#define LPASS_SCSS_GP_HIGH_IRQ			(GIC_SPI_START + 90)
+#define TOP_IMEM_IRQ				(GIC_SPI_START + 91)
+#define FABRIC_SYS_IRQ				(GIC_SPI_START + 92)
+#define FABRIC_APPS_IRQ				(GIC_SPI_START + 93)
+#define USB1_HS_BAM_IRQ				(GIC_SPI_START + 94)
+#define SDC4_BAM_IRQ				(GIC_SPI_START + 95)
+#define SDC3_BAM_IRQ				(GIC_SPI_START + 96)
+#define SDC2_BAM_IRQ				(GIC_SPI_START + 97)
+#define SDC1_BAM_IRQ				(GIC_SPI_START + 98)
+#define FABRIC_SPS_IRQ				(GIC_SPI_START + 99)
+#define USB1_HS_IRQ				(GIC_SPI_START + 100)
+#define SDC4_IRQ_0				(GIC_SPI_START + 101)
+#define SDC3_IRQ_0				(GIC_SPI_START + 102)
+#define SDC2_IRQ_0				(GIC_SPI_START + 103)
+#define SDC1_IRQ_0				(GIC_SPI_START + 104)
+#define SPS_BAM_DMA_IRQ				(GIC_SPI_START + 105)
+#define SPS_SEC_VIOL_IRQ			(GIC_SPI_START + 106)
+#define SPS_MTI_0				(GIC_SPI_START + 107)
+#define SPS_MTI_1				(GIC_SPI_START + 108)
+#define SPS_MTI_2				(GIC_SPI_START + 109)
+#define SPS_MTI_3				(GIC_SPI_START + 110)
+#define SPS_MTI_4				(GIC_SPI_START + 111)
+#define SPS_MTI_5				(GIC_SPI_START + 112)
+#define SPS_MTI_6				(GIC_SPI_START + 113)
+#define SPS_MTI_7				(GIC_SPI_START + 114)
+#define SPS_MTI_8				(GIC_SPI_START + 115)
+#define SPS_MTI_9				(GIC_SPI_START + 116)
+#define SPS_MTI_10				(GIC_SPI_START + 117)
+#define SPS_MTI_11				(GIC_SPI_START + 118)
+#define SPS_MTI_12				(GIC_SPI_START + 119)
+#define SPS_MTI_13				(GIC_SPI_START + 120)
+#define SPS_MTI_14				(GIC_SPI_START + 121)
+#define SPS_MTI_15				(GIC_SPI_START + 122)
+#define SPS_MTI_16				(GIC_SPI_START + 123)
+#define SPS_MTI_17				(GIC_SPI_START + 124)
+#define SPS_MTI_18				(GIC_SPI_START + 125)
+#define SPS_MTI_19				(GIC_SPI_START + 126)
+#define SPS_MTI_20				(GIC_SPI_START + 127)
+#define SPS_MTI_21				(GIC_SPI_START + 128)
+#define SPS_MTI_22				(GIC_SPI_START + 129)
+#define SPS_MTI_23				(GIC_SPI_START + 130)
+#define SPS_MTI_24				(GIC_SPI_START + 131)
+#define SPS_MTI_25				(GIC_SPI_START + 132)
+#define SPS_MTI_26				(GIC_SPI_START + 133)
+#define SPS_MTI_27				(GIC_SPI_START + 134)
+#define SPS_MTI_28				(GIC_SPI_START + 135)
+#define SPS_MTI_29				(GIC_SPI_START + 136)
+#define SPS_MTI_30				(GIC_SPI_START + 137)
+#define SPS_MTI_31				(GIC_SPI_START + 138)
+#define CSIPHY_2LN_IRQ				(GIC_SPI_START + 139)
+#define CSIPHY_4LN_IRQ				(GIC_SPI_START + 140)
+#define USB2_IRQ				(GIC_SPI_START + 141)
+#define USB1_IRQ				(GIC_SPI_START + 142)
+#define TSSC_SSBI_IRQ				(GIC_SPI_START + 143)
+#define TSSC_SAMPLE_IRQ				(GIC_SPI_START + 144)
+#define TSSC_PENUP_IRQ				(GIC_SPI_START + 145)
+#define GSBI1_UARTDM_IRQ			(GIC_SPI_START + 193)
+#define GSBI1_QUP_IRQ				(GIC_SPI_START + 194)
+#define GSBI2_UARTDM_IRQ			(GIC_SPI_START + 148)
+#define GSBI2_QUP_IRQ			        (GIC_SPI_START + 149)
+#define GSBI3_UARTDM_IRQ			(GIC_SPI_START + 150)
+#define GSBI3_QUP_IRQ				(GIC_SPI_START + 151)
+#define GSBI4_UARTDM_IRQ			(GIC_SPI_START + 152)
+#define GSBI4_QUP_IRQ				(GIC_SPI_START + 153)
+#define GSBI5_UARTDM_IRQ			(GIC_SPI_START + 154)
+#define GSBI5_QUP_IRQ				(GIC_SPI_START + 155)
+#define GSBI6_UARTDM_IRQ			(GIC_SPI_START + 156)
+#define GSBI6_QUP_IRQ				(GIC_SPI_START + 157)
+#define GSBI7_UARTDM_IRQ			(GIC_SPI_START + 158)
+#define GSBI7_QUP_IRQ				(GIC_SPI_START + 159)
+#define GSBI8_UARTDM_IRQ			(GIC_SPI_START + 160)
+#define GSBI8_QUP_IRQ				(GIC_SPI_START + 161)
+#define TSIF_TSPP_IRQ				(GIC_SPI_START + 162)
+#define TSIF_BAM_IRQ				(GIC_SPI_START + 163)
+#define TSIF2_IRQ				(GIC_SPI_START + 164)
+#define TSIF1_IRQ				(GIC_SPI_START + 165)
+#define DSI2_IRQ				(GIC_SPI_START + 166)
+#define ISPIF_IRQ				(GIC_SPI_START + 167)
+#define MSMC_SC_SEC_TMR_IRQ			(GIC_SPI_START + 168)
+#define MSMC_SC_SEC_WDOG_BARK_IRQ		(GIC_SPI_START + 169)
+#define INT_ADM0_SCSS_0_IRQ			(GIC_SPI_START + 170)
+#define INT_ADM0_SCSS_1_IRQ			(GIC_SPI_START + 171)
+#define INT_ADM0_SCSS_2_IRQ			(GIC_SPI_START + 172)
+#define INT_ADM0_SCSS_3_IRQ			(GIC_SPI_START + 173)
+#define CC_SCSS_WDT1CPU1BITEEXPIRED		(GIC_SPI_START + 174)
+#define CC_SCSS_WDT1CPU0BITEEXPIRED		(GIC_SPI_START + 175)
+#define CC_SCSS_WDT0CPU1BITEEXPIRED		(GIC_SPI_START + 176)
+#define CC_SCSS_WDT0CPU0BITEEXPIRED		(GIC_SPI_START + 177)
+#define TSENS_UPPER_LOWER_INT			(GIC_SPI_START + 178)
+#define SSBI2_2_SC_CPU1_SECURE_INT		(GIC_SPI_START + 179)
+#define SSBI2_2_SC_CPU1_NON_SECURE_INT		(GIC_SPI_START + 180)
+#define SSBI2_1_SC_CPU1_SECURE_INT		(GIC_SPI_START + 181)
+#define SSBI2_1_SC_CPU1_NON_SECURE_INT		(GIC_SPI_START + 182)
+#define XPU_SUMMARY_IRQ				(GIC_SPI_START + 183)
+#define BUS_EXCEPTION_SUMMARY_IRQ		(GIC_SPI_START + 184)
+#define HSDDRX_EBI1CH0_IRQ			(GIC_SPI_START + 185)
+#define HSDDRX_EBI1CH1_IRQ			(GIC_SPI_START + 186)
+#define SDC5_BAM_IRQ				(GIC_SPI_START + 187)
+#define SDC5_IRQ_0				(GIC_SPI_START + 188)
+#define GSBI9_UARTDM_IRQ			(GIC_SPI_START + 189)
+#define GSBI9_QUP_IRQ				(GIC_SPI_START + 190)
+#define GSBI10_UARTDM_IRQ			(GIC_SPI_START + 191)
+#define GSBI10_QUP_IRQ				(GIC_SPI_START + 192)
+#define GSBI11_UARTDM_IRQ			(GIC_SPI_START + 193)
+#define GSBI11_QUP_IRQ				(GIC_SPI_START + 194)
+#define GSBI12_UARTDM_IRQ			(GIC_SPI_START + 195)
+#define GSBI12_QUP_IRQ				(GIC_SPI_START + 196)
+#define RIVA_APSS_LTECOEX_IRQ			(GIC_SPI_START + 197)
+#define RIVA_APSS_SPARE_IRQ			(GIC_SPI_START + 198)
+#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ	(GIC_SPI_START + 199)
+#define RIVA_ASS_RESET_DONE_IRQ			(GIC_SPI_START + 200)
+#define RIVA_APSS_ASIC_IRQ			(GIC_SPI_START + 201)
+#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ	(GIC_SPI_START + 202)
+#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ	(GIC_SPI_START + 203)
+#define RIVA_APPS_WLAM_SMSM_IRQ			(GIC_SPI_START + 204)
+#define RIVA_APPS_LOG_CTRL_IRQ			(GIC_SPI_START + 205)
+#define RIVA_APPS_FM_CTRL_IRQ			(GIC_SPI_START + 206)
+#define RIVA_APPS_HCI_IRQ			(GIC_SPI_START + 207)
+#define RIVA_APPS_WLAN_CTRL_IRQ			(GIC_SPI_START + 208)
+#define A2_BAM_IRQ				(GIC_SPI_START + 209)
+#define SMMU_GFX2D1_CB_SC_SECURE_IRQ		(GIC_SPI_START + 210)
+#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 211)
+#define GFX2D1_IRQ				(GIC_SPI_START + 212)
+#define PPSS_WDOG_TIMER_IRQ			(GIC_SPI_START + 213)
+#define SPS_SLIMBUS_CORE_EE0_IRQ		(GIC_SPI_START + 214)
+#define SPS_SLIMBUS_BAM_EE0_IRQ			(GIC_SPI_START + 215)
+#define QDSS_ETB_IRQ				(GIC_SPI_START + 216)
+#define QDSS_CTI2KPSS_CPU1_IRQ			(GIC_SPI_START + 217)
+#define QDSS_CTI2KPSS_CPU0_IRQ			(GIC_SPI_START + 218)
+#define TLMM_APCC_DIR_CONN_IRQ_16		(GIC_SPI_START + 219)
+#define TLMM_APCC_DIR_CONN_IRQ_17		(GIC_SPI_START + 220)
+#define TLMM_APCC_DIR_CONN_IRQ_18		(GIC_SPI_START + 221)
+#define TLMM_APCC_DIR_CONN_IRQ_19		(GIC_SPI_START + 222)
+#define TLMM_APCC_DIR_CONN_IRQ_20		(GIC_SPI_START + 223)
+#define TLMM_APCC_DIR_CONN_IRQ_21		(GIC_SPI_START + 224)
+#define PM8921_SEC_IRQ_104			(GIC_SPI_START + 225)
+#define PM8018_SEC_IRQ_107			(GIC_SPI_START + 226)
+
+/* For now, use the maximum number of interrupts until a pending GIC issue
+ * is sorted out */
+#define NR_MSM_IRQS 1020
+#define NR_BOARD_IRQS 0
+#define NR_GPIO_IRQS 0
+
+#endif
+
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 8679a45..e2cb037 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -26,6 +26,8 @@
 #include "sirc.h"
 #elif defined(CONFIG_ARCH_MSM8X60)
 #include "irqs-8x60.h"
+#elif defined(CONFIG_ARCH_MSM8960)
+#include "irqs-8960.h"
 #elif defined(CONFIG_ARCH_MSM_ARM11)
 #include "irqs-7x00.h"
 #else
--
1.7.0.2

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 3/7] msm: irqs-8960: Interrupt map for MSM8960

[Stepan Moskovchenko]

Add the interrupt map for the Qualcomm MSM8960 chip. This
chip has an interrupt map that is different from previous
targets.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/irqs-8960.h |  293 ++++++++++++++++++++++++++++
 arch/arm/mach-msm/include/mach/irqs.h      |    2 +
 2 files changed, 295 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/include/mach/irqs-8960.h

diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h
new file mode 100644
index 0000000..f4d8593
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8960.h
@@ -0,0 +1,293 @@
+/* Copyright (c) 2010 Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_8960_H
+#define __ASM_ARCH_MSM_IRQS_8960_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15:  STI/SGI (software triggered/generated interrupts)
+   16-31: PPI (private peripheral interrupts)
+   32+:   SPI (shared peripheral interrupts) */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_VGIC				(GIC_PPI_START + 0)
+#define INT_DEBUG_TIMER_EXP			(GIC_PPI_START + 1)
+#define INT_GP_TIMER_EXP			(GIC_PPI_START + 2)
+#define INT_GP_TIMER2_EXP			(GIC_PPI_START + 3)
+#define WDT0_ACCSCSSNBARK_INT			(GIC_PPI_START + 4)
+#define WDT1_ACCSCSSNBARK_INT			(GIC_PPI_START + 5)
+#define AVS_SVICINT				(GIC_PPI_START + 6)
+#define AVS_SVICINTSWDONE			(GIC_PPI_START + 7)
+#define CPU_DBGCPUXCOMMRXFULL			(GIC_PPI_START + 8)
+#define CPU_DBGCPUXCOMMTXEMPTY			(GIC_PPI_START + 9)
+#define CPU_SICCPUXPERFMONIRPTREQ		(GIC_PPI_START + 10)
+#define SC_AVSCPUXDOWN				(GIC_PPI_START + 11)
+#define SC_AVSCPUXUP				(GIC_PPI_START + 12)
+#define SC_SICCPUXACGIRPTREQ			(GIC_PPI_START + 13)
+#define SC_SICCPUXEXTFAULTIRPTREQ		(GIC_PPI_START + 14)
+/* PPI 15 is unused */
+
+#define SC_SICMPUIRPTREQ			(GIC_SPI_START + 0)
+#define SC_SICL2IRPTREQ				(GIC_SPI_START + 1)
+#define SC_SICL2PERFMONIRPTREQ			(GIC_SPI_START + 2)
+#define SC_SICAGCIRPTREQ			(GIC_SPI_START + 3)
+#define TLMM_APCC_DIR_CONN_IRQ_0		(GIC_SPI_START + 4)
+#define TLMM_APCC_DIR_CONN_IRQ_1		(GIC_SPI_START + 5)
+#define TLMM_APCC_DIR_CONN_IRQ_2		(GIC_SPI_START + 6)
+#define TLMM_APCC_DIR_CONN_IRQ_3		(GIC_SPI_START + 7)
+#define TLMM_APCC_DIR_CONN_IRQ_4		(GIC_SPI_START + 8)
+#define TLMM_APCC_DIR_CONN_IRQ_5		(GIC_SPI_START + 9)
+#define TLMM_APCC_DIR_CONN_IRQ_6		(GIC_SPI_START + 10)
+#define TLMM_APCC_DIR_CONN_IRQ_7		(GIC_SPI_START + 11)
+#define TLMM_APCC_DIR_CONN_IRQ_8		(GIC_SPI_START + 12)
+#define TLMM_APCC_DIR_CONN_IRQ_9		(GIC_SPI_START + 13)
+#define PM8921_SEC_IRQ_103			(GIC_SPI_START + 14)
+#define PM8018_SEC_IRQ_106			(GIC_SPI_START + 15)
+#define TLMM_APCC_SUMMARY_IRQ			(GIC_SPI_START + 16)
+#define SPDM_RT_1_IRQ				(GIC_SPI_START + 17)
+#define SPDM_DIAG_IRQ				(GIC_SPI_START + 18)
+#define RPM_APCC_CPU0_GP_HIGH_IRQ		(GIC_SPI_START + 19)
+#define RPM_APCC_CPU0_GP_MEDIUM_IRQ		(GIC_SPI_START + 20)
+#define RPM_APCC_CPU0_GP_LOW_IRQ		(GIC_SPI_START + 21)
+#define RPM_APCC_CPU0_WAKE_UP_IRQ		(GIC_SPI_START + 22)
+#define RPM_APCC_CPU1_GP_HIGH_IRQ		(GIC_SPI_START + 23)
+#define RPM_APCC_CPU1_GP_MEDIUM_IRQ		(GIC_SPI_START + 24)
+#define RPM_APCC_CPU1_GP_LOW_IRQ		(GIC_SPI_START + 25)
+#define RPM_APCC_CPU1_WAKE_UP_IRQ		(GIC_SPI_START + 26)
+#define SSBI2_2_SC_CPU0_SECURE_IRQ		(GIC_SPI_START + 27)
+#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ		(GIC_SPI_START + 28)
+#define SSBI2_1_SC_CPU0_SECURE_IRQ		(GIC_SPI_START + 29)
+#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ		(GIC_SPI_START + 30)
+#define MSMC_SC_SEC_CE_IRQ			(GIC_SPI_START + 31)
+#define MSMC_SC_PRI_CE_IRQ			(GIC_SPI_START + 32)
+#define SLIMBUS0_CORE_EE1_IRQ			(GIC_SPI_START + 33)
+#define SLIMBUS0_BAM_EE1_IRQ			(GIC_SPI_START + 34)
+#define Q6FW_WDOG_EXPIRED_IRQ			(GIC_SPI_START + 35)
+#define Q6SW_WDOG_EXPIRED_IRQ			(GIC_SPI_START + 36)
+#define MSS_TO_APPS_IRQ_0			(GIC_SPI_START + 37)
+#define MSS_TO_APPS_IRQ_1			(GIC_SPI_START + 38)
+#define MSS_TO_APPS_IRQ_2			(GIC_SPI_START + 39)
+#define MSS_TO_APPS_IRQ_3			(GIC_SPI_START + 40)
+#define MSS_TO_APPS_IRQ_4			(GIC_SPI_START + 41)
+#define MSS_TO_APPS_IRQ_5			(GIC_SPI_START + 42)
+#define MSS_TO_APPS_IRQ_6			(GIC_SPI_START + 43)
+#define MSS_TO_APPS_IRQ_7			(GIC_SPI_START + 44)
+#define MSS_TO_APPS_IRQ_8			(GIC_SPI_START + 45)
+#define MSS_TO_APPS_IRQ_9			(GIC_SPI_START + 46)
+#define VPE_IRQ					(GIC_SPI_START + 47)
+#define VFE_IRQ					(GIC_SPI_START + 48)
+#define VCODEC_IRQ				(GIC_SPI_START + 49)
+#define TV_ENC_IRQ				(GIC_SPI_START + 50)
+#define SMMU_VPE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 51)
+#define SMMU_VPE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 52)
+#define SMMU_VFE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 53)
+#define SMMU_VFE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 54)
+#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ		(GIC_SPI_START + 55)
+#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 56)
+#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ		(GIC_SPI_START + 57)
+#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 58)
+#define SMMU_ROT_CB_SC_SECURE_IRQ		(GIC_SPI_START + 59)
+#define SMMU_ROT_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 60)
+#define SMMU_MDP1_CB_SC_SECURE_IRQ		(GIC_SPI_START + 61)
+#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 62)
+#define SMMU_MDP0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 63)
+#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 64)
+#define SMMU_JPEGD_CB_SC_SECURE_IRQ		(GIC_SPI_START + 65)
+#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 66)
+#define SMMU_IJPEG_CB_SC_SECURE_IRQ		(GIC_SPI_START + 67)
+#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 68)
+#define SMMU_GFX3D_CB_SC_SECURE_IRQ		(GIC_SPI_START + 69)
+#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 70)
+#define SMMU_GFX2D0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 71)
+#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 72)
+#define ROT_IRQ					(GIC_SPI_START + 73)
+#define MMSS_FABRIC_IRQ				(GIC_SPI_START + 74)
+#define MDP_IRQ					(GIC_SPI_START + 75)
+#define JPEGD_IRQ				(GIC_SPI_START + 76)
+#define JPEG_IRQ				(GIC_SPI_START + 77)
+#define MMSS_IMEM_IRQ				(GIC_SPI_START + 78)
+#define HDMI_IRQ				(GIC_SPI_START + 79)
+#define GFX3D_IRQ				(GIC_SPI_START + 80)
+#define GFX2D0_IRQ				(GIC_SPI_START + 81)
+#define DSI1_IRQ				(GIC_SPI_START + 82)
+#define CSI_1_IRQ				(GIC_SPI_START + 83)
+#define CSI_0_IRQ				(GIC_SPI_START + 84)
+#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ		(GIC_SPI_START + 85)
+#define LPASS_SCSS_MIDI_IRQ			(GIC_SPI_START + 86)
+#define LPASS_Q6SS_WDOG_EXPIRED			(GIC_SPI_START + 87)
+#define LPASS_SCSS_GP_LOW_IRQ			(GIC_SPI_START + 88)
+#define LPASS_SCSS_GP_MEDIUM_IRQ		(GIC_SPI_START + 89)
+#define LPASS_SCSS_GP_HIGH_IRQ			(GIC_SPI_START + 90)
+#define TOP_IMEM_IRQ				(GIC_SPI_START + 91)
+#define FABRIC_SYS_IRQ				(GIC_SPI_START + 92)
+#define FABRIC_APPS_IRQ				(GIC_SPI_START + 93)
+#define USB1_HS_BAM_IRQ				(GIC_SPI_START + 94)
+#define SDC4_BAM_IRQ				(GIC_SPI_START + 95)
+#define SDC3_BAM_IRQ				(GIC_SPI_START + 96)
+#define SDC2_BAM_IRQ				(GIC_SPI_START + 97)
+#define SDC1_BAM_IRQ				(GIC_SPI_START + 98)
+#define FABRIC_SPS_IRQ				(GIC_SPI_START + 99)
+#define USB1_HS_IRQ				(GIC_SPI_START + 100)
+#define SDC4_IRQ_0				(GIC_SPI_START + 101)
+#define SDC3_IRQ_0				(GIC_SPI_START + 102)
+#define SDC2_IRQ_0				(GIC_SPI_START + 103)
+#define SDC1_IRQ_0				(GIC_SPI_START + 104)
+#define SPS_BAM_DMA_IRQ				(GIC_SPI_START + 105)
+#define SPS_SEC_VIOL_IRQ			(GIC_SPI_START + 106)
+#define SPS_MTI_0				(GIC_SPI_START + 107)
+#define SPS_MTI_1				(GIC_SPI_START + 108)
+#define SPS_MTI_2				(GIC_SPI_START + 109)
+#define SPS_MTI_3				(GIC_SPI_START + 110)
+#define SPS_MTI_4				(GIC_SPI_START + 111)
+#define SPS_MTI_5				(GIC_SPI_START + 112)
+#define SPS_MTI_6				(GIC_SPI_START + 113)
+#define SPS_MTI_7				(GIC_SPI_START + 114)
+#define SPS_MTI_8				(GIC_SPI_START + 115)
+#define SPS_MTI_9				(GIC_SPI_START + 116)
+#define SPS_MTI_10				(GIC_SPI_START + 117)
+#define SPS_MTI_11				(GIC_SPI_START + 118)
+#define SPS_MTI_12				(GIC_SPI_START + 119)
+#define SPS_MTI_13				(GIC_SPI_START + 120)
+#define SPS_MTI_14				(GIC_SPI_START + 121)
+#define SPS_MTI_15				(GIC_SPI_START + 122)
+#define SPS_MTI_16				(GIC_SPI_START + 123)
+#define SPS_MTI_17				(GIC_SPI_START + 124)
+#define SPS_MTI_18				(GIC_SPI_START + 125)
+#define SPS_MTI_19				(GIC_SPI_START + 126)
+#define SPS_MTI_20				(GIC_SPI_START + 127)
+#define SPS_MTI_21				(GIC_SPI_START + 128)
+#define SPS_MTI_22				(GIC_SPI_START + 129)
+#define SPS_MTI_23				(GIC_SPI_START + 130)
+#define SPS_MTI_24				(GIC_SPI_START + 131)
+#define SPS_MTI_25				(GIC_SPI_START + 132)
+#define SPS_MTI_26				(GIC_SPI_START + 133)
+#define SPS_MTI_27				(GIC_SPI_START + 134)
+#define SPS_MTI_28				(GIC_SPI_START + 135)
+#define SPS_MTI_29				(GIC_SPI_START + 136)
+#define SPS_MTI_30				(GIC_SPI_START + 137)
+#define SPS_MTI_31				(GIC_SPI_START + 138)
+#define CSIPHY_2LN_IRQ				(GIC_SPI_START + 139)
+#define CSIPHY_4LN_IRQ				(GIC_SPI_START + 140)
+#define USB2_IRQ				(GIC_SPI_START + 141)
+#define USB1_IRQ				(GIC_SPI_START + 142)
+#define TSSC_SSBI_IRQ				(GIC_SPI_START + 143)
+#define TSSC_SAMPLE_IRQ				(GIC_SPI_START + 144)
+#define TSSC_PENUP_IRQ				(GIC_SPI_START + 145)
+#define GSBI1_UARTDM_IRQ			(GIC_SPI_START + 193)
+#define GSBI1_QUP_IRQ				(GIC_SPI_START + 194)
+#define GSBI2_UARTDM_IRQ			(GIC_SPI_START + 148)
+#define GSBI2_QUP_IRQ			        (GIC_SPI_START + 149)
+#define GSBI3_UARTDM_IRQ			(GIC_SPI_START + 150)
+#define GSBI3_QUP_IRQ				(GIC_SPI_START + 151)
+#define GSBI4_UARTDM_IRQ			(GIC_SPI_START + 152)
+#define GSBI4_QUP_IRQ				(GIC_SPI_START + 153)
+#define GSBI5_UARTDM_IRQ			(GIC_SPI_START + 154)
+#define GSBI5_QUP_IRQ				(GIC_SPI_START + 155)
+#define GSBI6_UARTDM_IRQ			(GIC_SPI_START + 156)
+#define GSBI6_QUP_IRQ				(GIC_SPI_START + 157)
+#define GSBI7_UARTDM_IRQ			(GIC_SPI_START + 158)
+#define GSBI7_QUP_IRQ				(GIC_SPI_START + 159)
+#define GSBI8_UARTDM_IRQ			(GIC_SPI_START + 160)
+#define GSBI8_QUP_IRQ				(GIC_SPI_START + 161)
+#define TSIF_TSPP_IRQ				(GIC_SPI_START + 162)
+#define TSIF_BAM_IRQ				(GIC_SPI_START + 163)
+#define TSIF2_IRQ				(GIC_SPI_START + 164)
+#define TSIF1_IRQ				(GIC_SPI_START + 165)
+#define DSI2_IRQ				(GIC_SPI_START + 166)
+#define ISPIF_IRQ				(GIC_SPI_START + 167)
+#define MSMC_SC_SEC_TMR_IRQ			(GIC_SPI_START + 168)
+#define MSMC_SC_SEC_WDOG_BARK_IRQ		(GIC_SPI_START + 169)
+#define INT_ADM0_SCSS_0_IRQ			(GIC_SPI_START + 170)
+#define INT_ADM0_SCSS_1_IRQ			(GIC_SPI_START + 171)
+#define INT_ADM0_SCSS_2_IRQ			(GIC_SPI_START + 172)
+#define INT_ADM0_SCSS_3_IRQ			(GIC_SPI_START + 173)
+#define CC_SCSS_WDT1CPU1BITEEXPIRED		(GIC_SPI_START + 174)
+#define CC_SCSS_WDT1CPU0BITEEXPIRED		(GIC_SPI_START + 175)
+#define CC_SCSS_WDT0CPU1BITEEXPIRED		(GIC_SPI_START + 176)
+#define CC_SCSS_WDT0CPU0BITEEXPIRED		(GIC_SPI_START + 177)
+#define TSENS_UPPER_LOWER_INT			(GIC_SPI_START + 178)
+#define SSBI2_2_SC_CPU1_SECURE_INT		(GIC_SPI_START + 179)
+#define SSBI2_2_SC_CPU1_NON_SECURE_INT		(GIC_SPI_START + 180)
+#define SSBI2_1_SC_CPU1_SECURE_INT		(GIC_SPI_START + 181)
+#define SSBI2_1_SC_CPU1_NON_SECURE_INT		(GIC_SPI_START + 182)
+#define XPU_SUMMARY_IRQ				(GIC_SPI_START + 183)
+#define BUS_EXCEPTION_SUMMARY_IRQ		(GIC_SPI_START + 184)
+#define HSDDRX_EBI1CH0_IRQ			(GIC_SPI_START + 185)
+#define HSDDRX_EBI1CH1_IRQ			(GIC_SPI_START + 186)
+#define SDC5_BAM_IRQ				(GIC_SPI_START + 187)
+#define SDC5_IRQ_0				(GIC_SPI_START + 188)
+#define GSBI9_UARTDM_IRQ			(GIC_SPI_START + 189)
+#define GSBI9_QUP_IRQ				(GIC_SPI_START + 190)
+#define GSBI10_UARTDM_IRQ			(GIC_SPI_START + 191)
+#define GSBI10_QUP_IRQ				(GIC_SPI_START + 192)
+#define GSBI11_UARTDM_IRQ			(GIC_SPI_START + 193)
+#define GSBI11_QUP_IRQ				(GIC_SPI_START + 194)
+#define GSBI12_UARTDM_IRQ			(GIC_SPI_START + 195)
+#define GSBI12_QUP_IRQ				(GIC_SPI_START + 196)
+#define RIVA_APSS_LTECOEX_IRQ			(GIC_SPI_START + 197)
+#define RIVA_APSS_SPARE_IRQ			(GIC_SPI_START + 198)
+#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ	(GIC_SPI_START + 199)
+#define RIVA_ASS_RESET_DONE_IRQ			(GIC_SPI_START + 200)
+#define RIVA_APSS_ASIC_IRQ			(GIC_SPI_START + 201)
+#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ	(GIC_SPI_START + 202)
+#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ	(GIC_SPI_START + 203)
+#define RIVA_APPS_WLAM_SMSM_IRQ			(GIC_SPI_START + 204)
+#define RIVA_APPS_LOG_CTRL_IRQ			(GIC_SPI_START + 205)
+#define RIVA_APPS_FM_CTRL_IRQ			(GIC_SPI_START + 206)
+#define RIVA_APPS_HCI_IRQ			(GIC_SPI_START + 207)
+#define RIVA_APPS_WLAN_CTRL_IRQ			(GIC_SPI_START + 208)
+#define A2_BAM_IRQ				(GIC_SPI_START + 209)
+#define SMMU_GFX2D1_CB_SC_SECURE_IRQ		(GIC_SPI_START + 210)
+#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 211)
+#define GFX2D1_IRQ				(GIC_SPI_START + 212)
+#define PPSS_WDOG_TIMER_IRQ			(GIC_SPI_START + 213)
+#define SPS_SLIMBUS_CORE_EE0_IRQ		(GIC_SPI_START + 214)
+#define SPS_SLIMBUS_BAM_EE0_IRQ			(GIC_SPI_START + 215)
+#define QDSS_ETB_IRQ				(GIC_SPI_START + 216)
+#define QDSS_CTI2KPSS_CPU1_IRQ			(GIC_SPI_START + 217)
+#define QDSS_CTI2KPSS_CPU0_IRQ			(GIC_SPI_START + 218)
+#define TLMM_APCC_DIR_CONN_IRQ_16		(GIC_SPI_START + 219)
+#define TLMM_APCC_DIR_CONN_IRQ_17		(GIC_SPI_START + 220)
+#define TLMM_APCC_DIR_CONN_IRQ_18		(GIC_SPI_START + 221)
+#define TLMM_APCC_DIR_CONN_IRQ_19		(GIC_SPI_START + 222)
+#define TLMM_APCC_DIR_CONN_IRQ_20		(GIC_SPI_START + 223)
+#define TLMM_APCC_DIR_CONN_IRQ_21		(GIC_SPI_START + 224)
+#define PM8921_SEC_IRQ_104			(GIC_SPI_START + 225)
+#define PM8018_SEC_IRQ_107			(GIC_SPI_START + 226)
+
+/* For now, use the maximum number of interrupts until a pending GIC issue
+ * is sorted out */
+#define NR_MSM_IRQS 1020
+#define NR_BOARD_IRQS 0
+#define NR_GPIO_IRQS 0
+
+#endif
+
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 8679a45..e2cb037 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -26,6 +26,8 @@
 #include "sirc.h"
 #elif defined(CONFIG_ARCH_MSM8X60)
 #include "irqs-8x60.h"
+#elif defined(CONFIG_ARCH_MSM8960)
+#include "irqs-8960.h"
 #elif defined(CONFIG_ARCH_MSM_ARM11)
 #include "irqs-7x00.h"
 #else
--
1.7.0.2

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 4/7] msm: Board file for MSM8960 simulator

[Stepan Moskovchenko]

Add a basic board file needed to boot the kernel on the
MSM8960 simulator.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
 arch/arm/mach-msm/board-msm8960.c |   71 +++++++++++++++++++++++++++++++++++++
 1 files changed, 71 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/board-msm8960.c

diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
new file mode 100644
index 0000000..7a1b80a
--- /dev/null
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -0,0 +1,71 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/board.h>
+#include <mach/msm_iomap.h>
+
+void __iomem *gic_cpu_base_addr;
+
+static void __init msm8960_map_io(void)
+{
+	msm_map_msm8960_io();
+}
+
+static void __init msm8960_init_irq(void)
+{
+	unsigned int i;
+
+	gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
+	gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
+	gic_cpu_init(0, MSM_QGIC_CPU_BASE);
+
+	/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
+	writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
+
+	/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
+	 * as they are configured as level, which does not play nice with
+	 * handle_percpu_irq.
+	 */
+	for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
+		if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
+			set_irq_handler(i, handle_percpu_irq);
+	}
+}
+
+static void __init msm8960_sim_init(void)
+{
+}
+
+MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
+#ifdef CONFIG_MSM_DEBUG_UART
+	.phys_io  = MSM_DEBUG_UART_PHYS,
+	.io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
+#endif
+	.map_io = msm8960_map_io,
+	.init_irq = msm8960_init_irq,
+	.init_machine = msm8960_sim_init,
+	.timer = &msm_timer,
+MACHINE_END
--
1.7.0.2

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 4/7] msm: Board file for MSM8960 simulator

[Stepan Moskovchenko]

Add a basic board file needed to boot the kernel on the
MSM8960 simulator.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
 arch/arm/mach-msm/board-msm8960.c |   71 +++++++++++++++++++++++++++++++++++++
 1 files changed, 71 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/board-msm8960.c

diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
new file mode 100644
index 0000000..7a1b80a
--- /dev/null
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -0,0 +1,71 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/board.h>
+#include <mach/msm_iomap.h>
+
+void __iomem *gic_cpu_base_addr;
+
+static void __init msm8960_map_io(void)
+{
+	msm_map_msm8960_io();
+}
+
+static void __init msm8960_init_irq(void)
+{
+	unsigned int i;
+
+	gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
+	gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
+	gic_cpu_init(0, MSM_QGIC_CPU_BASE);
+
+	/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
+	writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
+
+	/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
+	 * as they are configured as level, which does not play nice with
+	 * handle_percpu_irq.
+	 */
+	for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
+		if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
+			set_irq_handler(i, handle_percpu_irq);
+	}
+}
+
+static void __init msm8960_sim_init(void)
+{
+}
+
+MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
+#ifdef CONFIG_MSM_DEBUG_UART
+	.phys_io  = MSM_DEBUG_UART_PHYS,
+	.io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
+#endif
+	.map_io = msm8960_map_io,
+	.init_irq = msm8960_init_irq,
+	.init_machine = msm8960_sim_init,
+	.timer = &msm_timer,
+MACHINE_END
--
1.7.0.2

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 5/7] msm: timer: Timer support for MSM8960

[Stepan Moskovchenko]

Modify the macros in the MSM timer driver to support the
MSM8960 chip.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
 arch/arm/mach-msm/timer.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 1154292..c48a449 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -63,7 +63,8 @@ enum timer_location {
 #if defined(CONFIG_ARCH_QSD8X50)
 #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
 #define MSM_DGT_SHIFT (0)
-#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60)
+#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \
+				      defined(CONFIG_ARCH_MSM8960)
 #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
 #define MSM_DGT_SHIFT (0)
 #else
--
1.7.0.2

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 5/7] msm: timer: Timer support for MSM8960

[Stepan Moskovchenko]

Modify the macros in the MSM timer driver to support the
MSM8960 chip.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
 arch/arm/mach-msm/timer.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 1154292..c48a449 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -63,7 +63,8 @@ enum timer_location {
 #if defined(CONFIG_ARCH_QSD8X50)
 #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
 #define MSM_DGT_SHIFT (0)
-#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60)
+#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \
+				      defined(CONFIG_ARCH_MSM8960)
 #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
 #define MSM_DGT_SHIFT (0)
 #else
--
1.7.0.2

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 6/7] msm: Makefile cleanup

[Stepan Moskovchenko]

Clean up some of the conditionals in the Makefile in
preparation for adding build support for MSM8960.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
 arch/arm/mach-msm/Makefile |   18 ++++++------------
 1 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 1945f9c..8cd0b5b 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,21 +1,15 @@
 obj-y += io.o idle.o timer.o
-ifndef CONFIG_ARCH_MSM8X60
-obj-y += acpuclock-arm11.o
-obj-y += dma.o
-endif

-ifdef CONFIG_MSM_VIC
-obj-y += irq-vic.o
-else
-ifndef CONFIG_ARCH_MSM8X60
-obj-y += irq.o
-endif
-endif
+obj-$(CONFIG_MSM_VIC) += irq-vic.o

+obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
+obj-$(CONFIG_ARCH_MSM7X30) += dma.o
+obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
 obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
+
 obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
 obj-$(CONFIG_MSM_PROC_COMM) += clock.o
-obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
+
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
 obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
--
1.7.0.2

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 6/7] msm: Makefile cleanup

[Stepan Moskovchenko]

Clean up some of the conditionals in the Makefile in
preparation for adding build support for MSM8960.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
 arch/arm/mach-msm/Makefile |   18 ++++++------------
 1 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 1945f9c..8cd0b5b 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,21 +1,15 @@
 obj-y += io.o idle.o timer.o
-ifndef CONFIG_ARCH_MSM8X60
-obj-y += acpuclock-arm11.o
-obj-y += dma.o
-endif

-ifdef CONFIG_MSM_VIC
-obj-y += irq-vic.o
-else
-ifndef CONFIG_ARCH_MSM8X60
-obj-y += irq.o
-endif
-endif
+obj-$(CONFIG_MSM_VIC) += irq-vic.o

+obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
+obj-$(CONFIG_ARCH_MSM7X30) += dma.o
+obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
 obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
+
 obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
 obj-$(CONFIG_MSM_PROC_COMM) += clock.o
-obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
+
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
 obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
--
1.7.0.2

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 7/7] msm: Build support for the MSM8960 target

[Stepan Moskovchenko]

Add the Kconfig options and Makefile options needed to
build for the MSM8960 target. Only the simulator is
supported at this time.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
 arch/arm/mach-msm/Kconfig  |   16 ++++++++++++++++
 arch/arm/mach-msm/Makefile |    2 ++
 2 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 8c57425..ba5c955 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -47,6 +47,16 @@ config ARCH_MSM8X60
 	select MSM_GPIOMUX
 	select MSM_SCM if SMP

+config ARCH_MSM8960
+	bool "MSM8960"
+	select ARCH_MSM_SCORPIONMP
+	select MACH_MSM8960_SIM
+	select ARM_GIC
+	select CPU_V7
+	select MSM_V2_TLMM
+	select MSM_GPIOMUX
+	select MSM_SCM if SMP
+
 endchoice

 config MSM_SOC_REV_A
@@ -124,6 +134,12 @@ config MACH_MSM8X60_FFA
 	help
 	  Support for the Qualcomm MSM8x60 FFA eval board.

+config MACH_MSM8960_SIM
+	depends on ARCH_MSM8960
+	bool "MSM8960 Simulator"
+	help
+	  Support for the Qualcomm MSM8960 simulator.
+
 endmenu

 config MSM_DEBUG_UART
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 8cd0b5b..9e5717b 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
 obj-$(CONFIG_ARCH_MSM7X30) += dma.o
 obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
 obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
+obj-$(CONFIG_ARCH_MSM8960) += clock-dummy.o iommu.o iommu_dev.o

 obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
 obj-$(CONFIG_MSM_PROC_COMM) += clock.o
@@ -22,6 +23,7 @@ obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
 obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
+obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o

 obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
--
1.7.0.2

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 7/7] msm: Build support for the MSM8960 target

[Stepan Moskovchenko]

Add the Kconfig options and Makefile options needed to
build for the MSM8960 target. Only the simulator is
supported at this time.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
 arch/arm/mach-msm/Kconfig  |   16 ++++++++++++++++
 arch/arm/mach-msm/Makefile |    2 ++
 2 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 8c57425..ba5c955 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -47,6 +47,16 @@ config ARCH_MSM8X60
 	select MSM_GPIOMUX
 	select MSM_SCM if SMP

+config ARCH_MSM8960
+	bool "MSM8960"
+	select ARCH_MSM_SCORPIONMP
+	select MACH_MSM8960_SIM
+	select ARM_GIC
+	select CPU_V7
+	select MSM_V2_TLMM
+	select MSM_GPIOMUX
+	select MSM_SCM if SMP
+
 endchoice

 config MSM_SOC_REV_A
@@ -124,6 +134,12 @@ config MACH_MSM8X60_FFA
 	help
 	  Support for the Qualcomm MSM8x60 FFA eval board.

+config MACH_MSM8960_SIM
+	depends on ARCH_MSM8960
+	bool "MSM8960 Simulator"
+	help
+	  Support for the Qualcomm MSM8960 simulator.
+
 endmenu

 config MSM_DEBUG_UART
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 8cd0b5b..9e5717b 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
 obj-$(CONFIG_ARCH_MSM7X30) += dma.o
 obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
 obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
+obj-$(CONFIG_ARCH_MSM8960) += clock-dummy.o iommu.o iommu_dev.o

 obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
 obj-$(CONFIG_MSM_PROC_COMM) += clock.o
@@ -22,6 +23,7 @@ obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
 obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
+obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o

 obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
--
1.7.0.2

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH 2/7] msm: Physical offset for MSM8960

[Sergei Shtylyov]

Hello.

On 15-12-2010 6:49, Stepan Moskovchenko wrote:

> Add the physical memory offset value for the Qualcomm
> MSM8960 chip.

> Signed-off-by: Stepan Moskovchenko<stepanm@codeaurora.org>
[...]

> diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
> index 070e17d..014bbd3 100644
> --- a/arch/arm/mach-msm/include/mach/memory.h
> +++ b/arch/arm/mach-msm/include/mach/memory.h
> @@ -25,6 +25,8 @@
>  #define PHYS_OFFSET		UL(0x00200000)
>  #elif defined(CONFIG_ARCH_MSM8X60)
>  #define PHYS_OFFSET		UL(0x40200000)
> +#elif defined(CONFIG_ARCH_MSM8960)
> +#define PHYS_OFFSET		UL(0x40200000)

    Why not:

-#elif defined(CONFIG_ARCH_MSM8X60)
+#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)

WBR, Sergei

[PATCH 2/7] msm: Physical offset for MSM8960

[Sergei Shtylyov]

Hello.

On 15-12-2010 6:49, Stepan Moskovchenko wrote:

> Add the physical memory offset value for the Qualcomm
> MSM8960 chip.

> Signed-off-by: Stepan Moskovchenko<stepanm@codeaurora.org>
[...]

> diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
> index 070e17d..014bbd3 100644
> --- a/arch/arm/mach-msm/include/mach/memory.h
> +++ b/arch/arm/mach-msm/include/mach/memory.h
> @@ -25,6 +25,8 @@
>  #define PHYS_OFFSET		UL(0x00200000)
>  #elif defined(CONFIG_ARCH_MSM8X60)
>  #define PHYS_OFFSET		UL(0x40200000)
> +#elif defined(CONFIG_ARCH_MSM8960)
> +#define PHYS_OFFSET		UL(0x40200000)

    Why not:

-#elif defined(CONFIG_ARCH_MSM8X60)
+#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)

WBR, Sergei

Re: [PATCH 2/7] msm: Physical offset for MSM8960

[David Brown]

On Wed, Dec 15, 2010 at 04:17:48PM +0300, Sergei Shtylyov wrote:

> On 15-12-2010 6:49, Stepan Moskovchenko wrote:
> 
> > Add the physical memory offset value for the Qualcomm
> > MSM8960 chip.
> 
> > Signed-off-by: Stepan Moskovchenko<stepanm@codeaurora.org>
> [...]
> 
> > diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
> > index 070e17d..014bbd3 100644
> > --- a/arch/arm/mach-msm/include/mach/memory.h
> > +++ b/arch/arm/mach-msm/include/mach/memory.h
> > @@ -25,6 +25,8 @@
> >  #define PHYS_OFFSET		UL(0x00200000)
> >  #elif defined(CONFIG_ARCH_MSM8X60)
> >  #define PHYS_OFFSET		UL(0x40200000)
> > +#elif defined(CONFIG_ARCH_MSM8960)
> > +#define PHYS_OFFSET		UL(0x40200000)
> 
>     Why not:
> 
> -#elif defined(CONFIG_ARCH_MSM8X60)
> +#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)

I guess it's a matter of style, and what one is trying to emphasize.
Having each one listed makes it easier to change them individually.
The file is just a listing of the addresses of each chip, so I don't
see much reason to try and compact it.

Thanks,
David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 2/7] msm: Physical offset for MSM8960

[David Brown]

On Wed, Dec 15, 2010 at 04:17:48PM +0300, Sergei Shtylyov wrote:

> On 15-12-2010 6:49, Stepan Moskovchenko wrote:
> 
> > Add the physical memory offset value for the Qualcomm
> > MSM8960 chip.
> 
> > Signed-off-by: Stepan Moskovchenko<stepanm@codeaurora.org>
> [...]
> 
> > diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
> > index 070e17d..014bbd3 100644
> > --- a/arch/arm/mach-msm/include/mach/memory.h
> > +++ b/arch/arm/mach-msm/include/mach/memory.h
> > @@ -25,6 +25,8 @@
> >  #define PHYS_OFFSET		UL(0x00200000)
> >  #elif defined(CONFIG_ARCH_MSM8X60)
> >  #define PHYS_OFFSET		UL(0x40200000)
> > +#elif defined(CONFIG_ARCH_MSM8960)
> > +#define PHYS_OFFSET		UL(0x40200000)
> 
>     Why not:
> 
> -#elif defined(CONFIG_ARCH_MSM8X60)
> +#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)

I guess it's a matter of style, and what one is trying to emphasize.
Having each one listed makes it easier to change them individually.
The file is just a listing of the addresses of each chip, so I don't
see much reason to try and compact it.

Thanks,
David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH 2/7] msm: Physical offset for MSM8960

[Daniel Walker]

On Wed, 2010-12-15 at 05:55 -0800, David Brown wrote:
> On Wed, Dec 15, 2010 at 04:17:48PM +0300, Sergei Shtylyov wrote:
> 
> > On 15-12-2010 6:49, Stepan Moskovchenko wrote:
> > 
> > > Add the physical memory offset value for the Qualcomm
> > > MSM8960 chip.
> > 
> > > Signed-off-by: Stepan Moskovchenko<stepanm@codeaurora.org>
> > [...]
> > 
> > > diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
> > > index 070e17d..014bbd3 100644
> > > --- a/arch/arm/mach-msm/include/mach/memory.h
> > > +++ b/arch/arm/mach-msm/include/mach/memory.h
> > > @@ -25,6 +25,8 @@
> > >  #define PHYS_OFFSET		UL(0x00200000)
> > >  #elif defined(CONFIG_ARCH_MSM8X60)
> > >  #define PHYS_OFFSET		UL(0x40200000)
> > > +#elif defined(CONFIG_ARCH_MSM8960)
> > > +#define PHYS_OFFSET		UL(0x40200000)
> > 
> >     Why not:
> > 
> > -#elif defined(CONFIG_ARCH_MSM8X60)
> > +#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
> 
> I guess it's a matter of style, and what one is trying to emphasize.
> Having each one listed makes it easier to change them individually.
> The file is just a listing of the addresses of each chip, so I don't
> see much reason to try and compact it.

It just shows a deeper issue, that the namespace needs work. There's too
much duplication here vs. 8x60 .. If you look over this whole patchset
it looks very much like 8x60 was just copied over.

Daniel
-- 
Sent by an consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum.

[PATCH 2/7] msm: Physical offset for MSM8960

[Daniel Walker]

On Wed, 2010-12-15 at 05:55 -0800, David Brown wrote:
> On Wed, Dec 15, 2010 at 04:17:48PM +0300, Sergei Shtylyov wrote:
> 
> > On 15-12-2010 6:49, Stepan Moskovchenko wrote:
> > 
> > > Add the physical memory offset value for the Qualcomm
> > > MSM8960 chip.
> > 
> > > Signed-off-by: Stepan Moskovchenko<stepanm@codeaurora.org>
> > [...]
> > 
> > > diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
> > > index 070e17d..014bbd3 100644
> > > --- a/arch/arm/mach-msm/include/mach/memory.h
> > > +++ b/arch/arm/mach-msm/include/mach/memory.h
> > > @@ -25,6 +25,8 @@
> > >  #define PHYS_OFFSET		UL(0x00200000)
> > >  #elif defined(CONFIG_ARCH_MSM8X60)
> > >  #define PHYS_OFFSET		UL(0x40200000)
> > > +#elif defined(CONFIG_ARCH_MSM8960)
> > > +#define PHYS_OFFSET		UL(0x40200000)
> > 
> >     Why not:
> > 
> > -#elif defined(CONFIG_ARCH_MSM8X60)
> > +#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
> 
> I guess it's a matter of style, and what one is trying to emphasize.
> Having each one listed makes it easier to change them individually.
> The file is just a listing of the addresses of each chip, so I don't
> see much reason to try and compact it.

It just shows a deeper issue, that the namespace needs work. There's too
much duplication here vs. 8x60 .. If you look over this whole patchset
it looks very much like 8x60 was just copied over.

Daniel
-- 
Sent by an consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum.

Re: [PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Arnd Bergmann]

On Wednesday 15 December 2010, Stepan Moskovchenko wrote:
> diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
> index 8e24dd8..4154a0a 100644
> --- a/arch/arm/mach-msm/include/mach/msm_iomap.h
> +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
> @@ -49,6 +49,8 @@
>  #include "msm_iomap-8x50.h"
>  #elif defined(CONFIG_ARCH_MSM8X60)
>  #include "msm_iomap-8x60.h"
> +#elif defined(CONFIG_ARCH_MSM8960)
> +#include "msm_iomap-8960.h"
>  #else
>  #include "msm_iomap-7x00.h"
>  #endif

As a general comment, try to make the config options like this nonexclusive,
so you can build kernels to run on multiple CPUs.

In this particular case, it's rather confusing, because one would assume
that MSM8960 is a subset of MSM8X60!

	Arnd

[PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Arnd Bergmann]

On Wednesday 15 December 2010, Stepan Moskovchenko wrote:
> diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
> index 8e24dd8..4154a0a 100644
> --- a/arch/arm/mach-msm/include/mach/msm_iomap.h
> +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
> @@ -49,6 +49,8 @@
>  #include "msm_iomap-8x50.h"
>  #elif defined(CONFIG_ARCH_MSM8X60)
>  #include "msm_iomap-8x60.h"
> +#elif defined(CONFIG_ARCH_MSM8960)
> +#include "msm_iomap-8960.h"
>  #else
>  #include "msm_iomap-7x00.h"
>  #endif

As a general comment, try to make the config options like this nonexclusive,
so you can build kernels to run on multiple CPUs.

In this particular case, it's rather confusing, because one would assume
that MSM8960 is a subset of MSM8X60!

	Arnd

Re: [PATCH 7/7] msm: Build support for the MSM8960 target

[Arnd Bergmann]

On Wednesday 15 December 2010, Stepan Moskovchenko wrote:
> Add the Kconfig options and Makefile options needed to
> build for the MSM8960 target. Only the simulator is
> supported at this time.
> 
> Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>

There is no need to split the Makefile/Kconfig changes
from the actual files implementing the functionality.
It's better to keep these together, since neither of the
patches does anything meaningful by itself.

Splitting out the cleanup as you did is good though, it
helps with review and with possible bisection or rebase
of the patches.

	Arnd

[PATCH 7/7] msm: Build support for the MSM8960 target

[Arnd Bergmann]

On Wednesday 15 December 2010, Stepan Moskovchenko wrote:
> Add the Kconfig options and Makefile options needed to
> build for the MSM8960 target. Only the simulator is
> supported at this time.
> 
> Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>

There is no need to split the Makefile/Kconfig changes
from the actual files implementing the functionality.
It's better to keep these together, since neither of the
patches does anything meaningful by itself.

Splitting out the cleanup as you did is good though, it
helps with review and with possible bisection or rebase
of the patches.

	Arnd

Re: [PATCH 1/7] msm: io: I/O register definitions for MSM8960

[David Brown]

On Wed, Dec 15, 2010 at 04:31:11PM +0100, Arnd Bergmann wrote:
> On Wednesday 15 December 2010, Stepan Moskovchenko wrote:

> In this particular case, it's rather confusing, because one would assume
> that MSM8960 is a subset of MSM8X60!

Unfortunately, this is not the case, and I'm not sure what better name
to use for MSM8X60.  The MSM8X60 name covers MSM8260 and MSM8660, but
MSM8960 is quite a bit different.  Any ideas for better names?

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 1/7] msm: io: I/O register definitions for MSM8960

[David Brown]

On Wed, Dec 15, 2010 at 04:31:11PM +0100, Arnd Bergmann wrote:
> On Wednesday 15 December 2010, Stepan Moskovchenko wrote:

> In this particular case, it's rather confusing, because one would assume
> that MSM8960 is a subset of MSM8X60!

Unfortunately, this is not the case, and I'm not sure what better name
to use for MSM8X60.  The MSM8X60 name covers MSM8260 and MSM8660, but
MSM8960 is quite a bit different.  Any ideas for better names?

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH 4/7] msm: Board file for MSM8960 simulator

[Arnd Bergmann]

On Wednesday 15 December 2010, Stepan Moskovchenko wrote:
> +#ifdef CONFIG_MSM_DEBUG_UART
> +       .phys_io  = MSM_DEBUG_UART_PHYS,
> +       .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
> +#endif

These fields are no longer present in the machine description,
AFAICT.

	Arnd

[PATCH 4/7] msm: Board file for MSM8960 simulator

[Arnd Bergmann]

On Wednesday 15 December 2010, Stepan Moskovchenko wrote:
> +#ifdef CONFIG_MSM_DEBUG_UART
> +       .phys_io  = MSM_DEBUG_UART_PHYS,
> +       .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
> +#endif

These fields are no longer present in the machine description,
AFAICT.

	Arnd

Re: [PATCH 2/7] msm: Physical offset for MSM8960

[David Brown]

On Wed, Dec 15, 2010 at 06:40:54AM -0800, Daniel Walker wrote:

> > > -#elif defined(CONFIG_ARCH_MSM8X60)
> > > +#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
> > 
> > I guess it's a matter of style, and what one is trying to emphasize.
> > Having each one listed makes it easier to change them individually.
> > The file is just a listing of the addresses of each chip, so I don't
> > see much reason to try and compact it.
> 
> It just shows a deeper issue, that the namespace needs work. There's too
> much duplication here vs. 8x60 .. If you look over this whole patchset
> it looks very much like 8x60 was just copied over.

There's not very much copying here, in fact there isn't very much to
the 8960 support to begin with.  Despite the confusing names, 8960 is
quite a bit different from 8[26]60.  I agree we would probably be best
with different names, which might help make the difference clearer.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 2/7] msm: Physical offset for MSM8960

[David Brown]

On Wed, Dec 15, 2010 at 06:40:54AM -0800, Daniel Walker wrote:

> > > -#elif defined(CONFIG_ARCH_MSM8X60)
> > > +#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
> > 
> > I guess it's a matter of style, and what one is trying to emphasize.
> > Having each one listed makes it easier to change them individually.
> > The file is just a listing of the addresses of each chip, so I don't
> > see much reason to try and compact it.
> 
> It just shows a deeper issue, that the namespace needs work. There's too
> much duplication here vs. 8x60 .. If you look over this whole patchset
> it looks very much like 8x60 was just copied over.

There's not very much copying here, in fact there isn't very much to
the 8960 support to begin with.  Despite the confusing names, 8960 is
quite a bit different from 8[26]60.  I agree we would probably be best
with different names, which might help make the difference clearer.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Arnd Bergmann]

On Wednesday 15 December 2010, David Brown wrote:
> 
> On Wed, Dec 15, 2010 at 04:31:11PM +0100, Arnd Bergmann wrote:
> > On Wednesday 15 December 2010, Stepan Moskovchenko wrote:
> 
> > In this particular case, it's rather confusing, because one would assume
> > that MSM8960 is a subset of MSM8X60!
> 
> Unfortunately, this is not the case, and I'm not sure what better name
> to use for MSM8X60.  The MSM8X60 name covers MSM8260 and MSM8660, but
> MSM8960 is quite a bit different.  Any ideas for better names?

No, you probably lose there, unless you can fall back to code names
instead of product numbers.

My point was really that they should not be exclusive, even if they
are rather different. If the code is structured in a more modular
way, you can turn all MSM/QSD options from the "Qualcomm MSM SoC Type"
choice into separate "bool" config options. You probably don't want
to do that now for all the existing ones, but I would suggest you
try not add more to the pile ;-).

	Arnd

[PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Arnd Bergmann]

On Wednesday 15 December 2010, David Brown wrote:
> 
> On Wed, Dec 15, 2010 at 04:31:11PM +0100, Arnd Bergmann wrote:
> > On Wednesday 15 December 2010, Stepan Moskovchenko wrote:
> 
> > In this particular case, it's rather confusing, because one would assume
> > that MSM8960 is a subset of MSM8X60!
> 
> Unfortunately, this is not the case, and I'm not sure what better name
> to use for MSM8X60.  The MSM8X60 name covers MSM8260 and MSM8660, but
> MSM8960 is quite a bit different.  Any ideas for better names?

No, you probably lose there, unless you can fall back to code names
instead of product numbers.

My point was really that they should not be exclusive, even if they
are rather different. If the code is structured in a more modular
way, you can turn all MSM/QSD options from the "Qualcomm MSM SoC Type"
choice into separate "bool" config options. You probably don't want
to do that now for all the existing ones, but I would suggest you
try not add more to the pile ;-).

	Arnd

Re: [PATCH 2/7] msm: Physical offset for MSM8960

[Steve Muckle]

On 12/15/10 07:38, David Brown wrote:
> There's not very much copying here, in fact there isn't very much to
> the 8960 support to begin with.  Despite the confusing names, 8960 is
> quite a bit different from 8[26]60.  I agree we would probably be best
> with different names, which might help make the difference clearer.

A couple more comments here...

Currently it is the case that there is a lot of similarity between 8960
and 8660, however the two are expected to diverge as 8960 support
matures. This may include things like the physical offset so IMO it is
better to leave this things as per-ARCH rather than combining them.

During some previous discussions on the naming situation, one idea which
was floated was renaming 8x60 to 8660, which would help clarify the
difference from 8960. The only issue with that is that 8260, which is
for purposes of the kernel the same as 8660, would be left out and
probably just have to be mentioned in the Kconfig help text for 8660.

thanks,
Steve

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 2/7] msm: Physical offset for MSM8960

[Steve Muckle]

On 12/15/10 07:38, David Brown wrote:
> There's not very much copying here, in fact there isn't very much to
> the 8960 support to begin with.  Despite the confusing names, 8960 is
> quite a bit different from 8[26]60.  I agree we would probably be best
> with different names, which might help make the difference clearer.

A couple more comments here...

Currently it is the case that there is a lot of similarity between 8960
and 8660, however the two are expected to diverge as 8960 support
matures. This may include things like the physical offset so IMO it is
better to leave this things as per-ARCH rather than combining them.

During some previous discussions on the naming situation, one idea which
was floated was renaming 8x60 to 8660, which would help clarify the
difference from 8960. The only issue with that is that 8260, which is
for purposes of the kernel the same as 8660, would be left out and
probably just have to be mentioned in the Kconfig help text for 8660.

thanks,
Steve

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH 2/7] msm: Physical offset for MSM8960

[Daniel Walker]

On Wed, 2010-12-15 at 07:38 -0800, David Brown wrote:
> On Wed, Dec 15, 2010 at 06:40:54AM -0800, Daniel Walker wrote:
> 
> > > > -#elif defined(CONFIG_ARCH_MSM8X60)
> > > > +#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
> > > 
> > > I guess it's a matter of style, and what one is trying to emphasize.
> > > Having each one listed makes it easier to change them individually.
> > > The file is just a listing of the addresses of each chip, so I don't
> > > see much reason to try and compact it.
> > 
> > It just shows a deeper issue, that the namespace needs work. There's too
> > much duplication here vs. 8x60 .. If you look over this whole patchset
> > it looks very much like 8x60 was just copied over.
> 
> There's not very much copying here, in fact there isn't very much to
> the 8960 support to begin with.  Despite the confusing names, 8960 is
> quite a bit different from 8[26]60.  I agree we would probably be best
> with different names, which might help make the difference clearer.

The board file is very similar, plus the ifdefs. The code differences
are the io and irq's .. The naming issue and the duplication can be
simplified just by combining 8960 and 8660 .. If you create two new
Kconfig options,

config MACH_MSM8660
	bool
config MACH_MSM8960
	bool

and use ARCH_MSM8X60 for all the duplication .. That gives you the
ability to leverage the similarities, and enough macros to distinguish
between the two for the differences. If there's no duplication (but we
know there is) then you just don't use ARCH_MSM8X60. You could also have
board-msm8660.c and board-msm8960.c to hold board file differences and
board-msm8x60.c to hold the similarities.

I haven't explored this in great detail, but it seems like a better
naming scheme than what you have here.

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 2/7] msm: Physical offset for MSM8960

[Daniel Walker]

On Wed, 2010-12-15 at 07:38 -0800, David Brown wrote:
> On Wed, Dec 15, 2010 at 06:40:54AM -0800, Daniel Walker wrote:
> 
> > > > -#elif defined(CONFIG_ARCH_MSM8X60)
> > > > +#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
> > > 
> > > I guess it's a matter of style, and what one is trying to emphasize.
> > > Having each one listed makes it easier to change them individually.
> > > The file is just a listing of the addresses of each chip, so I don't
> > > see much reason to try and compact it.
> > 
> > It just shows a deeper issue, that the namespace needs work. There's too
> > much duplication here vs. 8x60 .. If you look over this whole patchset
> > it looks very much like 8x60 was just copied over.
> 
> There's not very much copying here, in fact there isn't very much to
> the 8960 support to begin with.  Despite the confusing names, 8960 is
> quite a bit different from 8[26]60.  I agree we would probably be best
> with different names, which might help make the difference clearer.

The board file is very similar, plus the ifdefs. The code differences
are the io and irq's .. The naming issue and the duplication can be
simplified just by combining 8960 and 8660 .. If you create two new
Kconfig options,

config MACH_MSM8660
	bool
config MACH_MSM8960
	bool

and use ARCH_MSM8X60 for all the duplication .. That gives you the
ability to leverage the similarities, and enough macros to distinguish
between the two for the differences. If there's no duplication (but we
know there is) then you just don't use ARCH_MSM8X60. You could also have
board-msm8660.c and board-msm8960.c to hold board file differences and
board-msm8x60.c to hold the similarities.

I haven't explored this in great detail, but it seems like a better
naming scheme than what you have here.

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH 2/7] msm: Physical offset for MSM8960

[Steve Muckle]

On 12/15/10 09:55, Daniel Walker wrote:
> The board file is very similar, plus the ifdefs. The code differences
> are the io and irq's .. The naming issue and the duplication can be

8x60 and 8960 are expected to diverge over time. It is not worth it to
try and make them common in this early stage where they are the same
simply because a very small amount of 8960 (and 8660 for that matter)
has been sent upstream.

> simplified just by combining 8960 and 8660 .. If you create two new
> Kconfig options,
> 
> config MACH_MSM8660
> 	bool
> config MACH_MSM8960
> 	bool

We currently use ARCH_MSM* for SoCs, and MACH_* for boards based on
those SoCs. For this reason I think this scheme will be confusing and
lead to machine_is_() calls everywhere.

I suggest we rename 8x60 to 8660 (SteveMo's idea actually) if the
current naming is largely considered unacceptable.

thanks,
Steve

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 2/7] msm: Physical offset for MSM8960

[Steve Muckle]

On 12/15/10 09:55, Daniel Walker wrote:
> The board file is very similar, plus the ifdefs. The code differences
> are the io and irq's .. The naming issue and the duplication can be

8x60 and 8960 are expected to diverge over time. It is not worth it to
try and make them common in this early stage where they are the same
simply because a very small amount of 8960 (and 8660 for that matter)
has been sent upstream.

> simplified just by combining 8960 and 8660 .. If you create two new
> Kconfig options,
> 
> config MACH_MSM8660
> 	bool
> config MACH_MSM8960
> 	bool

We currently use ARCH_MSM* for SoCs, and MACH_* for boards based on
those SoCs. For this reason I think this scheme will be confusing and
lead to machine_is_() calls everywhere.

I suggest we rename 8x60 to 8660 (SteveMo's idea actually) if the
current naming is largely considered unacceptable.

thanks,
Steve

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH 2/7] msm: Physical offset for MSM8960

[Daniel Walker]

On Wed, 2010-12-15 at 10:07 -0800, Steve Muckle wrote:
> On 12/15/10 09:55, Daniel Walker wrote:
> > The board file is very similar, plus the ifdefs. The code differences
> > are the io and irq's .. The naming issue and the duplication can be
> 
> 8x60 and 8960 are expected to diverge over time. It is not worth it to
> try and make them common in this early stage where they are the same
> simply because a very small amount of 8960 (and 8660 for that matter)
> has been sent upstream.

My scheme should deal with that .. 

> > simplified just by combining 8960 and 8660 .. If you create two new
> > Kconfig options,
> > 
> > config MACH_MSM8660
> > 	bool
> > config MACH_MSM8960
> > 	bool
> 
> We currently use ARCH_MSM* for SoCs, and MACH_* for boards based on
> those SoCs. For this reason I think this scheme will be confusing and
> lead to machine_is_() calls everywhere.

You just need to look at this a different way. It's actually not much
different than what we currently have, it just saves us the duplication
and eliminates the naming problem .. The current version shouldn't need
machine_is_() calls so then this new way shouldn't either. You just use
the ifdef's ..

> I suggest we rename 8x60 to 8660 (SteveMo's idea actually) if the
> current naming is largely considered unacceptable.

I wouldn't say it's unacceptable, it's just a open question if there's a
better way.

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 2/7] msm: Physical offset for MSM8960

[Daniel Walker]

On Wed, 2010-12-15 at 10:07 -0800, Steve Muckle wrote:
> On 12/15/10 09:55, Daniel Walker wrote:
> > The board file is very similar, plus the ifdefs. The code differences
> > are the io and irq's .. The naming issue and the duplication can be
> 
> 8x60 and 8960 are expected to diverge over time. It is not worth it to
> try and make them common in this early stage where they are the same
> simply because a very small amount of 8960 (and 8660 for that matter)
> has been sent upstream.

My scheme should deal with that .. 

> > simplified just by combining 8960 and 8660 .. If you create two new
> > Kconfig options,
> > 
> > config MACH_MSM8660
> > 	bool
> > config MACH_MSM8960
> > 	bool
> 
> We currently use ARCH_MSM* for SoCs, and MACH_* for boards based on
> those SoCs. For this reason I think this scheme will be confusing and
> lead to machine_is_() calls everywhere.

You just need to look at this a different way. It's actually not much
different than what we currently have, it just saves us the duplication
and eliminates the naming problem .. The current version shouldn't need
machine_is_() calls so then this new way shouldn't either. You just use
the ifdef's ..

> I suggest we rename 8x60 to 8660 (SteveMo's idea actually) if the
> current naming is largely considered unacceptable.

I wouldn't say it's unacceptable, it's just a open question if there's a
better way.

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH 1/7] msm: io: I/O register definitions for MSM8960

[David Brown]

On Wed, Dec 15, 2010 at 05:40:24PM +0100, Arnd Bergmann wrote:

> My point was really that they should not be exclusive, even if they
> are rather different. If the code is structured in a more modular
> way, you can turn all MSM/QSD options from the "Qualcomm MSM SoC Type"
> choice into separate "bool" config options. You probably don't want
> to do that now for all the existing ones, but I would suggest you
> try not add more to the pile ;-).

It's kind of hard to do too much of this, though, until ARM kernels
can be relocated.  They mostly all live at different base addresses
(and 8960 might also move).  Throw CPU differences into the mix and it
gets messier.

I'm not saying it isn't solvable, but there are a lot of things that
need to be done to get there.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 1/7] msm: io: I/O register definitions for MSM8960

[David Brown]

On Wed, Dec 15, 2010 at 05:40:24PM +0100, Arnd Bergmann wrote:

> My point was really that they should not be exclusive, even if they
> are rather different. If the code is structured in a more modular
> way, you can turn all MSM/QSD options from the "Qualcomm MSM SoC Type"
> choice into separate "bool" config options. You probably don't want
> to do that now for all the existing ones, but I would suggest you
> try not add more to the pile ;-).

It's kind of hard to do too much of this, though, until ARM kernels
can be relocated.  They mostly all live at different base addresses
(and 8960 might also move).  Throw CPU differences into the mix and it
gets messier.

I'm not saying it isn't solvable, but there are a lot of things that
need to be done to get there.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Arnd Bergmann]

On Wednesday 15 December 2010, David Brown wrote:
> 
> On Wed, Dec 15, 2010 at 05:40:24PM +0100, Arnd Bergmann wrote:
> 
> > My point was really that they should not be exclusive, even if they
> > are rather different. If the code is structured in a more modular
> > way, you can turn all MSM/QSD options from the "Qualcomm MSM SoC Type"
> > choice into separate "bool" config options. You probably don't want
> > to do that now for all the existing ones, but I would suggest you
> > try not add more to the pile ;-).
> 
> It's kind of hard to do too much of this, though, until ARM kernels
> can be relocated.  They mostly all live at different base addresses
> (and 8960 might also move).  Throw CPU differences into the mix and it
> gets messier.
> 
> I'm not saying it isn't solvable, but there are a lot of things that
> need to be done to get there.

Yes, I understand that it's hard for many reasons, but my impression
is that there is a general agreement on the idea. As I said, I don't
expect you to fix it all at once, but it shouldn't be too hard
to take care when adding new code.

We already have infrastructure that deals with different CPU cores
in one kernel binary, at least from v5 to v7, and some platforms
like omap and realview can already be built for a variety of very
different machines without such problems.

	Arnd

[PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Arnd Bergmann]

On Wednesday 15 December 2010, David Brown wrote:
> 
> On Wed, Dec 15, 2010 at 05:40:24PM +0100, Arnd Bergmann wrote:
> 
> > My point was really that they should not be exclusive, even if they
> > are rather different. If the code is structured in a more modular
> > way, you can turn all MSM/QSD options from the "Qualcomm MSM SoC Type"
> > choice into separate "bool" config options. You probably don't want
> > to do that now for all the existing ones, but I would suggest you
> > try not add more to the pile ;-).
> 
> It's kind of hard to do too much of this, though, until ARM kernels
> can be relocated.  They mostly all live at different base addresses
> (and 8960 might also move).  Throw CPU differences into the mix and it
> gets messier.
> 
> I'm not saying it isn't solvable, but there are a lot of things that
> need to be done to get there.

Yes, I understand that it's hard for many reasons, but my impression
is that there is a general agreement on the idea. As I said, I don't
expect you to fix it all at once, but it shouldn't be too hard
to take care when adding new code.

We already have infrastructure that deals with different CPU cores
in one kernel binary, at least from v5 to v7, and some platforms
like omap and realview can already be built for a variety of very
different machines without such problems.

	Arnd

Re: [PATCH 1/7] msm: io: I/O register definitions for MSM8960

[David Brown]

On Wed, Dec 15, 2010 at 11:37:19PM +0100, Arnd Bergmann wrote:

> Yes, I understand that it's hard for many reasons, but my impression
> is that there is a general agreement on the idea. As I said, I don't
> expect you to fix it all at once, but it shouldn't be too hard
> to take care when adding new code.
> 
> We already have infrastructure that deals with different CPU cores
> in one kernel binary, at least from v5 to v7, and some platforms
> like omap and realview can already be built for a variety of very
> different machines without such problems.

I agree with this goal, and I think I have a plan to get us there.

For example, the iomap constants.  To fix this, this data needs to be
moved into platform data, or something similar.  It seems to me to
make the most sense to move the individual devices out of the iomap
until at least the devices used so far on 8960 are all done
dynamically.  Then at least these constants aren't needed for this
target.

There are similar things that need to be done for irqs, and timer
offsets.

I'm not sure really what to do about PHYS_OFFSET.  This is kind of the
big thing that has kept us so far from making our SOCs multiply
selectable.  I could move this into a Kconfig option, but it would
still need to be selected by the SOC.  It is unfortunate that most of
our SOCs have different enough memory configurations that these are
mostly different.  Even 8960/8660 will probably have future variants
that are at different addresses.

My question, then is, should we hold off on getting 8960 support into
the kernel until enough things are improved to get rid of the 8960
ifdefs?  We can certainly do it that way, but it will keep the code
out of the kernel longer.

Thanks,
David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 1/7] msm: io: I/O register definitions for MSM8960

[David Brown]

On Wed, Dec 15, 2010 at 11:37:19PM +0100, Arnd Bergmann wrote:

> Yes, I understand that it's hard for many reasons, but my impression
> is that there is a general agreement on the idea. As I said, I don't
> expect you to fix it all at once, but it shouldn't be too hard
> to take care when adding new code.
> 
> We already have infrastructure that deals with different CPU cores
> in one kernel binary, at least from v5 to v7, and some platforms
> like omap and realview can already be built for a variety of very
> different machines without such problems.

I agree with this goal, and I think I have a plan to get us there.

For example, the iomap constants.  To fix this, this data needs to be
moved into platform data, or something similar.  It seems to me to
make the most sense to move the individual devices out of the iomap
until at least the devices used so far on 8960 are all done
dynamically.  Then at least these constants aren't needed for this
target.

There are similar things that need to be done for irqs, and timer
offsets.

I'm not sure really what to do about PHYS_OFFSET.  This is kind of the
big thing that has kept us so far from making our SOCs multiply
selectable.  I could move this into a Kconfig option, but it would
still need to be selected by the SOC.  It is unfortunate that most of
our SOCs have different enough memory configurations that these are
mostly different.  Even 8960/8660 will probably have future variants
that are at different addresses.

My question, then is, should we hold off on getting 8960 support into
the kernel until enough things are improved to get rid of the 8960
ifdefs?  We can certainly do it that way, but it will keep the code
out of the kernel longer.

Thanks,
David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Arnd Bergmann]

On Friday 17 December 2010, David Brown wrote:
> I agree with this goal, and I think I have a plan to get us there.
> 
> For example, the iomap constants.  To fix this, this data needs to be
> moved into platform data, or something similar.  It seems to me to
> make the most sense to move the individual devices out of the iomap
> until at least the devices used so far on 8960 are all done
> dynamically.  Then at least these constants aren't needed for this
> target.

This is something that would get a lot easier if we already had
device tree support, no idea if it's worth waiting for that for you.
Doing it with extensive platform data involves much of the same
work, but may be more of it.

> There are similar things that need to be done for irqs, and timer
> offsets.

Yes. Eric has spent a lot of time looking into all these issues,
he probably has a good overview of the potential problems.

> I'm not sure really what to do about PHYS_OFFSET.  This is kind of the
> big thing that has kept us so far from making our SOCs multiply
> selectable.  I could move this into a Kconfig option, but it would
> still need to be selected by the SOC.  It is unfortunate that most of
> our SOCs have different enough memory configurations that these are
> mostly different.  Even 8960/8660 will probably have future variants
> that are at different addresses.

I think there are people working on relocatable kernels already,
and we definitely need this for the other work in progress of
doing kernel binaries that work across different SoC families,
as well as for doing a single kernel that can be used both for
booting the system and for kdump.

You don't need to worry about PHYS_OFFSET at the platform level,
we'll get there in a few months for all ARM platforms.

> My question, then is, should we hold off on getting 8960 support into
> the kernel until enough things are improved to get rid of the 8960
> ifdefs?  We can certainly do it that way, but it will keep the code
> out of the kernel longer.

My personal recommendation would be to fix all the places that you
can do without significant reworks of the existing code, and
just add TODO comments in the other places, so we can find them
easily. There is no reason to hold up merging the code too long for
this, but I wouldn't add code now that I know needs to be changed
soon to something that can already be done easily.

	Arnd

[PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Arnd Bergmann]

On Friday 17 December 2010, David Brown wrote:
> I agree with this goal, and I think I have a plan to get us there.
> 
> For example, the iomap constants.  To fix this, this data needs to be
> moved into platform data, or something similar.  It seems to me to
> make the most sense to move the individual devices out of the iomap
> until at least the devices used so far on 8960 are all done
> dynamically.  Then at least these constants aren't needed for this
> target.

This is something that would get a lot easier if we already had
device tree support, no idea if it's worth waiting for that for you.
Doing it with extensive platform data involves much of the same
work, but may be more of it.

> There are similar things that need to be done for irqs, and timer
> offsets.

Yes. Eric has spent a lot of time looking into all these issues,
he probably has a good overview of the potential problems.

> I'm not sure really what to do about PHYS_OFFSET.  This is kind of the
> big thing that has kept us so far from making our SOCs multiply
> selectable.  I could move this into a Kconfig option, but it would
> still need to be selected by the SOC.  It is unfortunate that most of
> our SOCs have different enough memory configurations that these are
> mostly different.  Even 8960/8660 will probably have future variants
> that are at different addresses.

I think there are people working on relocatable kernels already,
and we definitely need this for the other work in progress of
doing kernel binaries that work across different SoC families,
as well as for doing a single kernel that can be used both for
booting the system and for kdump.

You don't need to worry about PHYS_OFFSET at the platform level,
we'll get there in a few months for all ARM platforms.

> My question, then is, should we hold off on getting 8960 support into
> the kernel until enough things are improved to get rid of the 8960
> ifdefs?  We can certainly do it that way, but it will keep the code
> out of the kernel longer.

My personal recommendation would be to fix all the places that you
can do without significant reworks of the existing code, and
just add TODO comments in the other places, so we can find them
easily. There is no reason to hold up merging the code too long for
this, but I wouldn't add code now that I know needs to be changed
soon to something that can already be done easily.

	Arnd

Re: [PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Nicolas Pitre]

On Fri, 24 Dec 2010, Arnd Bergmann wrote:

> On Friday 17 December 2010, David Brown wrote:
> > I'm not sure really what to do about PHYS_OFFSET.  This is kind of the
> > big thing that has kept us so far from making our SOCs multiply
> > selectable.  I could move this into a Kconfig option, but it would
> > still need to be selected by the SOC.  It is unfortunate that most of
> > our SOCs have different enough memory configurations that these are
> > mostly different.  Even 8960/8660 will probably have future variants
> > that are at different addresses.
> 
> I think there are people working on relocatable kernels already,
> and we definitely need this for the other work in progress of
> doing kernel binaries that work across different SoC families,
> as well as for doing a single kernel that can be used both for
> booting the system and for kdump.
> 
> You don't need to worry about PHYS_OFFSET at the platform level,
> we'll get there in a few months for all ARM platforms.

... or in a few days even.  I'm currently working on the patch making 
PHYS_OFFSET patched into the kernel at run time.  I'm currently looking 
at what is needed to make it work also with Thumb2.


Nicolas

[PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Nicolas Pitre]

On Fri, 24 Dec 2010, Arnd Bergmann wrote:

> On Friday 17 December 2010, David Brown wrote:
> > I'm not sure really what to do about PHYS_OFFSET.  This is kind of the
> > big thing that has kept us so far from making our SOCs multiply
> > selectable.  I could move this into a Kconfig option, but it would
> > still need to be selected by the SOC.  It is unfortunate that most of
> > our SOCs have different enough memory configurations that these are
> > mostly different.  Even 8960/8660 will probably have future variants
> > that are at different addresses.
> 
> I think there are people working on relocatable kernels already,
> and we definitely need this for the other work in progress of
> doing kernel binaries that work across different SoC families,
> as well as for doing a single kernel that can be used both for
> booting the system and for kdump.
> 
> You don't need to worry about PHYS_OFFSET at the platform level,
> we'll get there in a few months for all ARM platforms.

... or in a few days even.  I'm currently working on the patch making 
PHYS_OFFSET patched into the kernel at run time.  I'm currently looking 
at what is needed to make it work also with Thumb2.


Nicolas

Re: [PATCH 1/7] msm: io: I/O register definitions for MSM8960

[David Brown]

Arnd Bergmann <arnd@arndb.de> writes:

> On Friday 17 December 2010, David Brown wrote:

>> My question, then is, should we hold off on getting 8960 support into
>> the kernel until enough things are improved to get rid of the 8960
>> ifdefs?  We can certainly do it that way, but it will keep the code
>> out of the kernel longer.
>
> My personal recommendation would be to fix all the places that you
> can do without significant reworks of the existing code, and
> just add TODO comments in the other places, so we can find them
> easily. There is no reason to hold up merging the code too long for
> this, but I wouldn't add code now that I know needs to be changed
> soon to something that can already be done easily.

Sounds like a good plan.  I've already started going through the IO
mapping defines to make them not-ifdef based.  It's not that significant
of a change.  Of course, everyone is on break here who will be able to
test things, so we'll have this stuff early January.

Thanks,
David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH 1/7] msm: io: I/O register definitions for MSM8960

[David Brown]

Arnd Bergmann <arnd@arndb.de> writes:

> On Friday 17 December 2010, David Brown wrote:

>> My question, then is, should we hold off on getting 8960 support into
>> the kernel until enough things are improved to get rid of the 8960
>> ifdefs?  We can certainly do it that way, but it will keep the code
>> out of the kernel longer.
>
> My personal recommendation would be to fix all the places that you
> can do without significant reworks of the existing code, and
> just add TODO comments in the other places, so we can find them
> easily. There is no reason to hold up merging the code too long for
> this, but I wouldn't add code now that I know needs to be changed
> soon to something that can already be done easily.

Sounds like a good plan.  I've already started going through the IO
mapping defines to make them not-ifdef based.  It's not that significant
of a change.  Of course, everyone is on break here who will be able to
test things, so we'll have this stuff early January.

Thanks,
David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Russell King - ARM Linux]

On Sat, Dec 25, 2010 at 11:04:11AM -0500, Nicolas Pitre wrote:
> On Fri, 24 Dec 2010, Arnd Bergmann wrote:
> 
> > On Friday 17 December 2010, David Brown wrote:
> > > I'm not sure really what to do about PHYS_OFFSET.  This is kind of the
> > > big thing that has kept us so far from making our SOCs multiply
> > > selectable.  I could move this into a Kconfig option, but it would
> > > still need to be selected by the SOC.  It is unfortunate that most of
> > > our SOCs have different enough memory configurations that these are
> > > mostly different.  Even 8960/8660 will probably have future variants
> > > that are at different addresses.
> > 
> > I think there are people working on relocatable kernels already,
> > and we definitely need this for the other work in progress of
> > doing kernel binaries that work across different SoC families,
> > as well as for doing a single kernel that can be used both for
> > booting the system and for kdump.
> > 
> > You don't need to worry about PHYS_OFFSET at the platform level,
> > we'll get there in a few months for all ARM platforms.
> 
> ... or in a few days even.  I'm currently working on the patch making 
> PHYS_OFFSET patched into the kernel at run time.  I'm currently looking 
> at what is needed to make it work also with Thumb2.

So where do we stand with:

http://lists.arm.linux.org.uk/lurker/message/20101110.175549.62a0b058.en.html

Is this something which should be queued for this merge window?

[PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Russell King - ARM Linux]

On Sat, Dec 25, 2010 at 11:04:11AM -0500, Nicolas Pitre wrote:
> On Fri, 24 Dec 2010, Arnd Bergmann wrote:
> 
> > On Friday 17 December 2010, David Brown wrote:
> > > I'm not sure really what to do about PHYS_OFFSET.  This is kind of the
> > > big thing that has kept us so far from making our SOCs multiply
> > > selectable.  I could move this into a Kconfig option, but it would
> > > still need to be selected by the SOC.  It is unfortunate that most of
> > > our SOCs have different enough memory configurations that these are
> > > mostly different.  Even 8960/8660 will probably have future variants
> > > that are at different addresses.
> > 
> > I think there are people working on relocatable kernels already,
> > and we definitely need this for the other work in progress of
> > doing kernel binaries that work across different SoC families,
> > as well as for doing a single kernel that can be used both for
> > booting the system and for kdump.
> > 
> > You don't need to worry about PHYS_OFFSET at the platform level,
> > we'll get there in a few months for all ARM platforms.
> 
> ... or in a few days even.  I'm currently working on the patch making 
> PHYS_OFFSET patched into the kernel at run time.  I'm currently looking 
> at what is needed to make it work also with Thumb2.

So where do we stand with:

http://lists.arm.linux.org.uk/lurker/message/20101110.175549.62a0b058.en.html

Is this something which should be queued for this merge window?

Re: [PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Nicolas Pitre]

On Mon, 3 Jan 2011, Russell King - ARM Linux wrote:

> On Sat, Dec 25, 2010 at 11:04:11AM -0500, Nicolas Pitre wrote:
> > On Fri, 24 Dec 2010, Arnd Bergmann wrote:
> > 
> > > On Friday 17 December 2010, David Brown wrote:
> > > > I'm not sure really what to do about PHYS_OFFSET.  This is kind of the
> > > > big thing that has kept us so far from making our SOCs multiply
> > > > selectable.  I could move this into a Kconfig option, but it would
> > > > still need to be selected by the SOC.  It is unfortunate that most of
> > > > our SOCs have different enough memory configurations that these are
> > > > mostly different.  Even 8960/8660 will probably have future variants
> > > > that are at different addresses.
> > > 
> > > I think there are people working on relocatable kernels already,
> > > and we definitely need this for the other work in progress of
> > > doing kernel binaries that work across different SoC families,
> > > as well as for doing a single kernel that can be used both for
> > > booting the system and for kdump.
> > > 
> > > You don't need to worry about PHYS_OFFSET at the platform level,
> > > we'll get there in a few months for all ARM platforms.
> > 
> > ... or in a few days even.  I'm currently working on the patch making 
> > PHYS_OFFSET patched into the kernel at run time.  I'm currently looking 
> > at what is needed to make it work also with Thumb2.
> 
> So where do we stand with:
> 
> http://lists.arm.linux.org.uk/lurker/message/20101110.175549.62a0b058.en.html
> 
> Is this something which should be queued for this merge window?

I'm working on a patch series that includes a slightly modified version 
of the above plus a few fixes for issues that turned up during testing.

I hope to have something for you to queue by tomorrow or tuesday.  This 
is damn close to the merge window, but we don't have to turn it on by 
default.

Nicolas

[PATCH 1/7] msm: io: I/O register definitions for MSM8960

[Nicolas Pitre]

On Mon, 3 Jan 2011, Russell King - ARM Linux wrote:

> On Sat, Dec 25, 2010 at 11:04:11AM -0500, Nicolas Pitre wrote:
> > On Fri, 24 Dec 2010, Arnd Bergmann wrote:
> > 
> > > On Friday 17 December 2010, David Brown wrote:
> > > > I'm not sure really what to do about PHYS_OFFSET.  This is kind of the
> > > > big thing that has kept us so far from making our SOCs multiply
> > > > selectable.  I could move this into a Kconfig option, but it would
> > > > still need to be selected by the SOC.  It is unfortunate that most of
> > > > our SOCs have different enough memory configurations that these are
> > > > mostly different.  Even 8960/8660 will probably have future variants
> > > > that are at different addresses.
> > > 
> > > I think there are people working on relocatable kernels already,
> > > and we definitely need this for the other work in progress of
> > > doing kernel binaries that work across different SoC families,
> > > as well as for doing a single kernel that can be used both for
> > > booting the system and for kdump.
> > > 
> > > You don't need to worry about PHYS_OFFSET at the platform level,
> > > we'll get there in a few months for all ARM platforms.
> > 
> > ... or in a few days even.  I'm currently working on the patch making 
> > PHYS_OFFSET patched into the kernel at run time.  I'm currently looking 
> > at what is needed to make it work also with Thumb2.
> 
> So where do we stand with:
> 
> http://lists.arm.linux.org.uk/lurker/message/20101110.175549.62a0b058.en.html
> 
> Is this something which should be queued for this merge window?

I'm working on a patch series that includes a slightly modified version 
of the above plus a few fixes for issues that turned up during testing.

I hope to have something for you to queue by tomorrow or tuesday.  This 
is damn close to the merge window, but we don't have to turn it on by 
default.

Nicolas

[PATCH v2 00/11] msm: Add initial support for MSM8960

[David Brown]

This series adds initial support for the MSM8960.  Unfortunately, the
naming of this device is misleading, and it is not a particular
instance of the current MSM8x60 devices, but a rather different chip.
The MSM8x60 arch supports the 8260 and 8660 devices.  I may make a
future patch to rename this arch to be one of these names.

Patch versions:
v2 - Remove ifdefs for io mappings for the new target.  More need to
     be cleaned up for all targets, but this doesn't add new ones.
     The irq table still contains an ifdef, which will be cleaned up
     in an upcoming patch.

[PATCH v2 01/11] msm: Add CPU queries

[David Brown]

Create runtime queries to distinguish the various MSM targets.
Although these would probably be better named soc_is..., use
cpu_is... to match convention in the rest of the kernel.

Hard code the tests based on config options for now.  When runtime
device detection is implemented, these can be made dynamic.

Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/cpu.h |   48 ++++++++++++++++++++++++++++++++++
 1 files changed, 48 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/include/mach/cpu.h

diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h
new file mode 100644
index 0000000..e1ba9db
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/cpu.h
@@ -0,0 +1,48 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_CPU_H__
+#define __ARCH_ARM_MACH_MSM_CPU_H__
+
+/* TODO: For now, only one CPU can be compiled at a time. */
+
+#define cpu_is_msm7x01()	0
+#define cpu_is_msm7x30()	0
+#define cpu_is_qsd8x50()	0
+#define cpu_is_msm8x60()	0
+
+#ifdef CONFIG_ARCH_MSM7X00A
+# undef cpu_is_msm7x01
+# define cpu_is_msm7x01()	1
+#endif
+
+#ifdef CONFIG_ARCH_MSM7X30
+# undef cpu_is_msm7x30
+# define cpu_is_msm7x30()	1
+#endif
+
+#ifdef CONFIG_ARCH_QSD8X50
+# undef cpu_is_qsd8x50
+# define cpu_is_qsd8x50()	1
+#endif
+
+#ifdef CONFIG_ARCH_MSM8X60
+# undef cpu_is_msm8x60
+# define cpu_is_msm8x60()	1
+#endif
+
+#endif
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 01/11] msm: Add CPU queries

[David Brown]

Create runtime queries to distinguish the various MSM targets.
Although these would probably be better named soc_is..., use
cpu_is... to match convention in the rest of the kernel.

Hard code the tests based on config options for now.  When runtime
device detection is implemented, these can be made dynamic.

Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/cpu.h |   48 ++++++++++++++++++++++++++++++++++
 1 files changed, 48 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/include/mach/cpu.h

diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h
new file mode 100644
index 0000000..e1ba9db
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/cpu.h
@@ -0,0 +1,48 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_CPU_H__
+#define __ARCH_ARM_MACH_MSM_CPU_H__
+
+/* TODO: For now, only one CPU can be compiled at a time. */
+
+#define cpu_is_msm7x01()	0
+#define cpu_is_msm7x30()	0
+#define cpu_is_qsd8x50()	0
+#define cpu_is_msm8x60()	0
+
+#ifdef CONFIG_ARCH_MSM7X00A
+# undef cpu_is_msm7x01
+# define cpu_is_msm7x01()	1
+#endif
+
+#ifdef CONFIG_ARCH_MSM7X30
+# undef cpu_is_msm7x30
+# define cpu_is_msm7x30()	1
+#endif
+
+#ifdef CONFIG_ARCH_QSD8X50
+# undef cpu_is_qsd8x50
+# define cpu_is_qsd8x50()	1
+#endif
+
+#ifdef CONFIG_ARCH_MSM8X60
+# undef cpu_is_msm8x60
+# define cpu_is_msm8x60()	1
+#endif
+
+#endif
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 02/11] msm: Generalize timer register mappings

Allow the timer register to be determined dynamically instead of at
compile time.  Use common virtual addresses for the registers across
all MSM chips, and select the register mappings based on the detected
CPU.

Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/msm_iomap-7x00.h |   10 ++----
 arch/arm/mach-msm/include/mach/msm_iomap-7x30.h |   14 ++------
 arch/arm/mach-msm/include/mach/msm_iomap-8x50.h |   14 ++------
 arch/arm/mach-msm/include/mach/msm_iomap-8x60.h |   15 +++-----
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    7 +++-
 arch/arm/mach-msm/io.c                          |   22 ++++++------
 arch/arm/mach-msm/timer.c                       |   43 +++++++++++++---------
 7 files changed, 55 insertions(+), 70 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index cfff0e7..1e75ed7 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -1,6 +1,7 @@
 /* arch/arm/mach-msm/include/mach/msm_iomap.h
  *
  * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -47,13 +48,8 @@
 #define MSM_VIC_PHYS          0xC0000000
 #define MSM_VIC_SIZE          SZ_4K
 
-#define MSM_CSR_BASE          IOMEM(0xE0001000)
-#define MSM_CSR_PHYS          0xC0100000
-#define MSM_CSR_SIZE          SZ_4K
-
-#define MSM_GPT_PHYS          MSM_CSR_PHYS
-#define MSM_GPT_BASE          MSM_CSR_BASE
-#define MSM_GPT_SIZE          SZ_4K
+#define MSM7X00_CSR_PHYS      0xC0100000
+#define MSM7X00_CSR_SIZE      SZ_4K
 
 #define MSM_DMOV_BASE         IOMEM(0xE0002000)
 #define MSM_DMOV_PHYS         0xA9700000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index 0fd7b68..4d84be1 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -39,16 +39,8 @@
 #define MSM_VIC_PHYS          0xC0080000
 #define MSM_VIC_SIZE          SZ_4K
 
-#define MSM_CSR_BASE          IOMEM(0xE0001000)
-#define MSM_CSR_PHYS          0xC0100000
-#define MSM_CSR_SIZE          SZ_4K
-
-#define MSM_TMR_PHYS          MSM_CSR_PHYS
-#define MSM_TMR_BASE          MSM_CSR_BASE
-#define MSM_TMR_SIZE          SZ_4K
-
-#define MSM_GPT_BASE 	      (MSM_TMR_BASE + 0x4)
-#define MSM_DGT_BASE 	      (MSM_TMR_BASE + 0x24)
+#define MSM7X30_CSR_PHYS      0xC0100000
+#define MSM7X30_CSR_SIZE      SZ_4K
 
 #define MSM_DMOV_BASE         IOMEM(0xE0002000)
 #define MSM_DMOV_PHYS         0xAC400000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index acc819e..cf1c2df 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -39,16 +39,8 @@
 #define MSM_VIC_PHYS          0xAC000000
 #define MSM_VIC_SIZE          SZ_4K
 
-#define MSM_CSR_BASE          IOMEM(0xE0001000)
-#define MSM_CSR_PHYS          0xAC100000
-#define MSM_CSR_SIZE          SZ_4K
-
-#define MSM_TMR_PHYS          MSM_CSR_PHYS
-#define MSM_TMR_BASE          MSM_CSR_BASE
-#define MSM_TMR_SIZE          SZ_4K
-
-#define MSM_GPT_BASE          MSM_TMR_BASE
-#define MSM_DGT_BASE          (MSM_TMR_BASE + 0x10)
+#define QSD8X50_CSR_PHYS      0xAC100000
+#define QSD8X50_CSR_SIZE      SZ_4K
 
 #define MSM_DMOV_BASE         IOMEM(0xE0002000)
 #define MSM_DMOV_PHYS         0xA9700000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index a54e33b..d5482d6 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -58,16 +58,11 @@
 #define MSM_SHARED_RAM_BASE	IOMEM(0xF0100000)
 #define MSM_SHARED_RAM_SIZE	SZ_1M
 
-#define MSM_TMR_BASE		IOMEM(0xF0200000)
-#define MSM_TMR_PHYS		0x02000000
-#define MSM_TMR_SIZE		SZ_4K
+#define MSM8X60_TMR_PHYS	0x02000000
+#define MSM8X60_TMR_SIZE	SZ_4K
 
-#define MSM_TMR0_BASE		IOMEM(0xF0201000)
-#define MSM_TMR0_PHYS		0x02040000
-#define MSM_TMR0_SIZE		SZ_4K
-
-#define MSM_GPT_BASE		(MSM_TMR_BASE + 0x4)
-#define MSM_DGT_BASE		(MSM_TMR_BASE + 0x24)
+#define MSM8X60_TMR0_PHYS	0x02040000
+#define MSM8X60_TMR0_SIZE	SZ_4K
 
 #define MSM_IOMMU_JPEGD_PHYS	0x07300000
 #define MSM_IOMMU_JPEGD_SIZE	SZ_1M
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 8e24dd8..0243bd0 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -53,6 +53,9 @@
 #include "msm_iomap-7x00.h"
 #endif
 
-
+/* Virtual addressses shared across all MSM targets. */
+#define MSM_CSR_BASE		IOMEM(0xE0001000)
+#define MSM_TMR_BASE		IOMEM(0xF0200000)
+#define MSM_TMR0_BASE		IOMEM(0xF0201000)
 
 #endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 800f327..47d699f 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -3,7 +3,7 @@
  * MSM7K, QSD io support
  *
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -28,18 +28,20 @@
 
 #include <mach/board.h>
 
-#define MSM_DEVICE(name) { \
+#define MSM_CHIP_DEVICE(name, chip) {			      \
 		.virtual = (unsigned long) MSM_##name##_BASE, \
-		.pfn = __phys_to_pfn(MSM_##name##_PHYS), \
-		.length = MSM_##name##_SIZE, \
+		.pfn = __phys_to_pfn(chip##_##name##_PHYS), \
+		.length = chip##_##name##_SIZE, \
 		.type = MT_DEVICE_NONSHARED, \
 	 }
 
+#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
+
 #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
 	|| defined(CONFIG_ARCH_MSM7X25)
 static struct map_desc msm_io_desc[] __initdata = {
 	MSM_DEVICE(VIC),
-	MSM_DEVICE(CSR),
+	MSM_CHIP_DEVICE(CSR, MSM7X00),
 	MSM_DEVICE(GPT),
 	MSM_DEVICE(DMOV),
 	MSM_DEVICE(GPIO1),
@@ -73,8 +75,7 @@ void __init msm_map_common_io(void)
 #ifdef CONFIG_ARCH_QSD8X50
 static struct map_desc qsd8x50_io_desc[] __initdata = {
 	MSM_DEVICE(VIC),
-	MSM_DEVICE(CSR),
-	MSM_DEVICE(TMR),
+	MSM_CHIP_DEVICE(CSR, QSD8X50),
 	MSM_DEVICE(DMOV),
 	MSM_DEVICE(GPIO1),
 	MSM_DEVICE(GPIO2),
@@ -104,8 +105,8 @@ void __init msm_map_qsd8x50_io(void)
 static struct map_desc msm8x60_io_desc[] __initdata = {
 	MSM_DEVICE(QGIC_DIST),
 	MSM_DEVICE(QGIC_CPU),
-	MSM_DEVICE(TMR),
-	MSM_DEVICE(TMR0),
+	MSM_CHIP_DEVICE(TMR, MSM8X60),
+	MSM_CHIP_DEVICE(TMR0, MSM8X60),
 	MSM_DEVICE(ACC),
 	MSM_DEVICE(GCC),
 };
@@ -119,8 +120,7 @@ void __init msm_map_msm8x60_io(void)
 #ifdef CONFIG_ARCH_MSM7X30
 static struct map_desc msm7x30_io_desc[] __initdata = {
 	MSM_DEVICE(VIC),
-	MSM_DEVICE(CSR),
-	MSM_DEVICE(TMR),
+	MSM_CHIP_DEVICE(CSR, MSM7X30),
 	MSM_DEVICE(DMOV),
 	MSM_DEVICE(GPIO1),
 	MSM_DEVICE(GPIO2),
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index c105d28..5548b15 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -24,10 +24,7 @@
 
 #include <asm/mach/time.h>
 #include <mach/msm_iomap.h>
-
-#ifndef MSM_DGT_BASE
-#define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)
-#endif
+#include <mach/cpu.h>
 
 #define TIMER_MATCH_VAL         0x0000
 #define TIMER_COUNT_VAL         0x0004
@@ -52,14 +49,9 @@ enum timer_location {
 	GLOBAL_TIMER = 1,
 };
 
-#ifdef MSM_TMR0_BASE
-#define MSM_TMR_GLOBAL		(MSM_TMR0_BASE - MSM_TMR_BASE)
-#else
-#define MSM_TMR_GLOBAL		0
-#endif
-
 #define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
 
+/* TODO: Remove these ifdefs */
 #if defined(CONFIG_ARCH_QSD8X50)
 #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
 #define MSM_DGT_SHIFT (0)
@@ -177,11 +169,7 @@ static struct msm_clock msm_clocks[] = {
 			.dev_id  = &msm_clocks[0].clockevent,
 			.irq     = INT_GP_TIMER_EXP
 		},
-		.regbase = MSM_GPT_BASE,
 		.freq = GPT_HZ,
-		.local_counter = MSM_GPT_BASE + TIMER_COUNT_VAL,
-		.global_counter = MSM_GPT_BASE + TIMER_COUNT_VAL +
-			MSM_TMR_GLOBAL,
 	},
 	[MSM_CLOCK_DGT] = {
 		.clockevent = {
@@ -206,12 +194,8 @@ static struct msm_clock msm_clocks[] = {
 			.dev_id  = &msm_clocks[1].clockevent,
 			.irq     = INT_DEBUG_TIMER_EXP
 		},
-		.regbase = MSM_DGT_BASE,
 		.freq = DGT_HZ >> MSM_DGT_SHIFT,
 		.shift = MSM_DGT_SHIFT,
-		.local_counter = MSM_DGT_BASE + TIMER_COUNT_VAL,
-		.global_counter = MSM_DGT_BASE + TIMER_COUNT_VAL +
-			MSM_TMR_GLOBAL,
 	}
 };
 
@@ -219,6 +203,25 @@ static void __init msm_timer_init(void)
 {
 	int i;
 	int res;
+	int global_offset = 0;
+
+	if (cpu_is_msm7x01()) {
+		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
+		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
+	} else if (cpu_is_msm7x30()) {
+		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
+		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
+	} else if (cpu_is_qsd8x50()) {
+		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
+		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
+	} else if (cpu_is_msm8x60()) {
+		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
+		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
+
+		/* Use CPU0's timer as the global timer. */
+		global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
+	} else
+		BUG();
 
 #ifdef CONFIG_ARCH_MSM_SCORPIONMP
 	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
@@ -228,6 +231,10 @@ static void __init msm_timer_init(void)
 		struct msm_clock *clock = &msm_clocks[i];
 		struct clock_event_device *ce = &clock->clockevent;
 		struct clocksource *cs = &clock->clocksource;
+
+		clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
+		clock->global_counter = clock->local_counter + global_offset;
+
 		writel(0, clock->regbase + TIMER_ENABLE);
 		writel(0, clock->regbase + TIMER_CLEAR);
 		writel(~0, clock->regbase + TIMER_MATCH_VAL);
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 02/11] msm: Generalize timer register mappings

[David Brown]

Allow the timer register to be determined dynamically instead of at
compile time.  Use common virtual addresses for the registers across
all MSM chips, and select the register mappings based on the detected
CPU.

Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/msm_iomap-7x00.h |   10 ++----
 arch/arm/mach-msm/include/mach/msm_iomap-7x30.h |   14 ++------
 arch/arm/mach-msm/include/mach/msm_iomap-8x50.h |   14 ++------
 arch/arm/mach-msm/include/mach/msm_iomap-8x60.h |   15 +++-----
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    7 +++-
 arch/arm/mach-msm/io.c                          |   22 ++++++------
 arch/arm/mach-msm/timer.c                       |   43 +++++++++++++---------
 7 files changed, 55 insertions(+), 70 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index cfff0e7..1e75ed7 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -1,6 +1,7 @@
 /* arch/arm/mach-msm/include/mach/msm_iomap.h
  *
  * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -47,13 +48,8 @@
 #define MSM_VIC_PHYS          0xC0000000
 #define MSM_VIC_SIZE          SZ_4K
 
-#define MSM_CSR_BASE          IOMEM(0xE0001000)
-#define MSM_CSR_PHYS          0xC0100000
-#define MSM_CSR_SIZE          SZ_4K
-
-#define MSM_GPT_PHYS          MSM_CSR_PHYS
-#define MSM_GPT_BASE          MSM_CSR_BASE
-#define MSM_GPT_SIZE          SZ_4K
+#define MSM7X00_CSR_PHYS      0xC0100000
+#define MSM7X00_CSR_SIZE      SZ_4K
 
 #define MSM_DMOV_BASE         IOMEM(0xE0002000)
 #define MSM_DMOV_PHYS         0xA9700000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index 0fd7b68..4d84be1 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -39,16 +39,8 @@
 #define MSM_VIC_PHYS          0xC0080000
 #define MSM_VIC_SIZE          SZ_4K
 
-#define MSM_CSR_BASE          IOMEM(0xE0001000)
-#define MSM_CSR_PHYS          0xC0100000
-#define MSM_CSR_SIZE          SZ_4K
-
-#define MSM_TMR_PHYS          MSM_CSR_PHYS
-#define MSM_TMR_BASE          MSM_CSR_BASE
-#define MSM_TMR_SIZE          SZ_4K
-
-#define MSM_GPT_BASE 	      (MSM_TMR_BASE + 0x4)
-#define MSM_DGT_BASE 	      (MSM_TMR_BASE + 0x24)
+#define MSM7X30_CSR_PHYS      0xC0100000
+#define MSM7X30_CSR_SIZE      SZ_4K
 
 #define MSM_DMOV_BASE         IOMEM(0xE0002000)
 #define MSM_DMOV_PHYS         0xAC400000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index acc819e..cf1c2df 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -39,16 +39,8 @@
 #define MSM_VIC_PHYS          0xAC000000
 #define MSM_VIC_SIZE          SZ_4K
 
-#define MSM_CSR_BASE          IOMEM(0xE0001000)
-#define MSM_CSR_PHYS          0xAC100000
-#define MSM_CSR_SIZE          SZ_4K
-
-#define MSM_TMR_PHYS          MSM_CSR_PHYS
-#define MSM_TMR_BASE          MSM_CSR_BASE
-#define MSM_TMR_SIZE          SZ_4K
-
-#define MSM_GPT_BASE          MSM_TMR_BASE
-#define MSM_DGT_BASE          (MSM_TMR_BASE + 0x10)
+#define QSD8X50_CSR_PHYS      0xAC100000
+#define QSD8X50_CSR_SIZE      SZ_4K
 
 #define MSM_DMOV_BASE         IOMEM(0xE0002000)
 #define MSM_DMOV_PHYS         0xA9700000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index a54e33b..d5482d6 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -58,16 +58,11 @@
 #define MSM_SHARED_RAM_BASE	IOMEM(0xF0100000)
 #define MSM_SHARED_RAM_SIZE	SZ_1M
 
-#define MSM_TMR_BASE		IOMEM(0xF0200000)
-#define MSM_TMR_PHYS		0x02000000
-#define MSM_TMR_SIZE		SZ_4K
+#define MSM8X60_TMR_PHYS	0x02000000
+#define MSM8X60_TMR_SIZE	SZ_4K
 
-#define MSM_TMR0_BASE		IOMEM(0xF0201000)
-#define MSM_TMR0_PHYS		0x02040000
-#define MSM_TMR0_SIZE		SZ_4K
-
-#define MSM_GPT_BASE		(MSM_TMR_BASE + 0x4)
-#define MSM_DGT_BASE		(MSM_TMR_BASE + 0x24)
+#define MSM8X60_TMR0_PHYS	0x02040000
+#define MSM8X60_TMR0_SIZE	SZ_4K
 
 #define MSM_IOMMU_JPEGD_PHYS	0x07300000
 #define MSM_IOMMU_JPEGD_SIZE	SZ_1M
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 8e24dd8..0243bd0 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -53,6 +53,9 @@
 #include "msm_iomap-7x00.h"
 #endif
 
-
+/* Virtual addressses shared across all MSM targets. */
+#define MSM_CSR_BASE		IOMEM(0xE0001000)
+#define MSM_TMR_BASE		IOMEM(0xF0200000)
+#define MSM_TMR0_BASE		IOMEM(0xF0201000)
 
 #endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 800f327..47d699f 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -3,7 +3,7 @@
  * MSM7K, QSD io support
  *
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -28,18 +28,20 @@
 
 #include <mach/board.h>
 
-#define MSM_DEVICE(name) { \
+#define MSM_CHIP_DEVICE(name, chip) {			      \
 		.virtual = (unsigned long) MSM_##name##_BASE, \
-		.pfn = __phys_to_pfn(MSM_##name##_PHYS), \
-		.length = MSM_##name##_SIZE, \
+		.pfn = __phys_to_pfn(chip##_##name##_PHYS), \
+		.length = chip##_##name##_SIZE, \
 		.type = MT_DEVICE_NONSHARED, \
 	 }
 
+#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
+
 #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
 	|| defined(CONFIG_ARCH_MSM7X25)
 static struct map_desc msm_io_desc[] __initdata = {
 	MSM_DEVICE(VIC),
-	MSM_DEVICE(CSR),
+	MSM_CHIP_DEVICE(CSR, MSM7X00),
 	MSM_DEVICE(GPT),
 	MSM_DEVICE(DMOV),
 	MSM_DEVICE(GPIO1),
@@ -73,8 +75,7 @@ void __init msm_map_common_io(void)
 #ifdef CONFIG_ARCH_QSD8X50
 static struct map_desc qsd8x50_io_desc[] __initdata = {
 	MSM_DEVICE(VIC),
-	MSM_DEVICE(CSR),
-	MSM_DEVICE(TMR),
+	MSM_CHIP_DEVICE(CSR, QSD8X50),
 	MSM_DEVICE(DMOV),
 	MSM_DEVICE(GPIO1),
 	MSM_DEVICE(GPIO2),
@@ -104,8 +105,8 @@ void __init msm_map_qsd8x50_io(void)
 static struct map_desc msm8x60_io_desc[] __initdata = {
 	MSM_DEVICE(QGIC_DIST),
 	MSM_DEVICE(QGIC_CPU),
-	MSM_DEVICE(TMR),
-	MSM_DEVICE(TMR0),
+	MSM_CHIP_DEVICE(TMR, MSM8X60),
+	MSM_CHIP_DEVICE(TMR0, MSM8X60),
 	MSM_DEVICE(ACC),
 	MSM_DEVICE(GCC),
 };
@@ -119,8 +120,7 @@ void __init msm_map_msm8x60_io(void)
 #ifdef CONFIG_ARCH_MSM7X30
 static struct map_desc msm7x30_io_desc[] __initdata = {
 	MSM_DEVICE(VIC),
-	MSM_DEVICE(CSR),
-	MSM_DEVICE(TMR),
+	MSM_CHIP_DEVICE(CSR, MSM7X30),
 	MSM_DEVICE(DMOV),
 	MSM_DEVICE(GPIO1),
 	MSM_DEVICE(GPIO2),
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index c105d28..5548b15 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -24,10 +24,7 @@
 
 #include <asm/mach/time.h>
 #include <mach/msm_iomap.h>
-
-#ifndef MSM_DGT_BASE
-#define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)
-#endif
+#include <mach/cpu.h>
 
 #define TIMER_MATCH_VAL         0x0000
 #define TIMER_COUNT_VAL         0x0004
@@ -52,14 +49,9 @@ enum timer_location {
 	GLOBAL_TIMER = 1,
 };
 
-#ifdef MSM_TMR0_BASE
-#define MSM_TMR_GLOBAL		(MSM_TMR0_BASE - MSM_TMR_BASE)
-#else
-#define MSM_TMR_GLOBAL		0
-#endif
-
 #define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
 
+/* TODO: Remove these ifdefs */
 #if defined(CONFIG_ARCH_QSD8X50)
 #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
 #define MSM_DGT_SHIFT (0)
@@ -177,11 +169,7 @@ static struct msm_clock msm_clocks[] = {
 			.dev_id  = &msm_clocks[0].clockevent,
 			.irq     = INT_GP_TIMER_EXP
 		},
-		.regbase = MSM_GPT_BASE,
 		.freq = GPT_HZ,
-		.local_counter = MSM_GPT_BASE + TIMER_COUNT_VAL,
-		.global_counter = MSM_GPT_BASE + TIMER_COUNT_VAL +
-			MSM_TMR_GLOBAL,
 	},
 	[MSM_CLOCK_DGT] = {
 		.clockevent = {
@@ -206,12 +194,8 @@ static struct msm_clock msm_clocks[] = {
 			.dev_id  = &msm_clocks[1].clockevent,
 			.irq     = INT_DEBUG_TIMER_EXP
 		},
-		.regbase = MSM_DGT_BASE,
 		.freq = DGT_HZ >> MSM_DGT_SHIFT,
 		.shift = MSM_DGT_SHIFT,
-		.local_counter = MSM_DGT_BASE + TIMER_COUNT_VAL,
-		.global_counter = MSM_DGT_BASE + TIMER_COUNT_VAL +
-			MSM_TMR_GLOBAL,
 	}
 };
 
@@ -219,6 +203,25 @@ static void __init msm_timer_init(void)
 {
 	int i;
 	int res;
+	int global_offset = 0;
+
+	if (cpu_is_msm7x01()) {
+		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
+		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
+	} else if (cpu_is_msm7x30()) {
+		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
+		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
+	} else if (cpu_is_qsd8x50()) {
+		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
+		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
+	} else if (cpu_is_msm8x60()) {
+		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
+		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
+
+		/* Use CPU0's timer as the global timer. */
+		global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
+	} else
+		BUG();
 
 #ifdef CONFIG_ARCH_MSM_SCORPIONMP
 	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
@@ -228,6 +231,10 @@ static void __init msm_timer_init(void)
 		struct msm_clock *clock = &msm_clocks[i];
 		struct clock_event_device *ce = &clock->clockevent;
 		struct clocksource *cs = &clock->clocksource;
+
+		clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
+		clock->global_counter = clock->local_counter + global_offset;
+
 		writel(0, clock->regbase + TIMER_ENABLE);
 		writel(0, clock->regbase + TIMER_CLEAR);
 		writel(~0, clock->regbase + TIMER_MATCH_VAL);
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 03/11] msm: Generalize QGIC registers

[David Brown]

The QGIC registers are mapped to the same virtual addresses across
targets, only the physical address changes.  Move the BASE address out
of target-specific files, and add a SOC name to the base addresses.

Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/msm_iomap-8x60.h |   10 ++++------
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    2 ++
 arch/arm/mach-msm/io.c                          |    4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index d5482d6..5bd18db 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -35,13 +35,11 @@
  *
  */
 
-#define MSM_QGIC_DIST_BASE	IOMEM(0xF0000000)
-#define MSM_QGIC_DIST_PHYS	0x02080000
-#define MSM_QGIC_DIST_SIZE	SZ_4K
+#define MSM8X60_QGIC_DIST_PHYS	0x02080000
+#define MSM8X60_QGIC_DIST_SIZE	SZ_4K
 
-#define MSM_QGIC_CPU_BASE	IOMEM(0xF0001000)
-#define MSM_QGIC_CPU_PHYS	0x02081000
-#define MSM_QGIC_CPU_SIZE	SZ_4K
+#define MSM8X60_QGIC_CPU_PHYS	0x02081000
+#define MSM8X60_QGIC_CPU_SIZE	SZ_4K
 
 #define MSM_ACC_BASE		IOMEM(0xF0002000)
 #define MSM_ACC_PHYS		0x02001000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 0243bd0..bb42de3 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -55,6 +55,8 @@
 
 /* Virtual addressses shared across all MSM targets. */
 #define MSM_CSR_BASE		IOMEM(0xE0001000)
+#define MSM_QGIC_DIST_BASE	IOMEM(0xF0000000)
+#define MSM_QGIC_CPU_BASE	IOMEM(0xF0001000)
 #define MSM_TMR_BASE		IOMEM(0xF0200000)
 #define MSM_TMR0_BASE		IOMEM(0xF0201000)
 
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 47d699f..5dd0d1b9 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -103,8 +103,8 @@ void __init msm_map_qsd8x50_io(void)
 
 #ifdef CONFIG_ARCH_MSM8X60
 static struct map_desc msm8x60_io_desc[] __initdata = {
-	MSM_DEVICE(QGIC_DIST),
-	MSM_DEVICE(QGIC_CPU),
+	MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60),
+	MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60),
 	MSM_CHIP_DEVICE(TMR, MSM8X60),
 	MSM_CHIP_DEVICE(TMR0, MSM8X60),
 	MSM_DEVICE(ACC),
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 03/11] msm: Generalize QGIC registers

[David Brown]

The QGIC registers are mapped to the same virtual addresses across
targets, only the physical address changes.  Move the BASE address out
of target-specific files, and add a SOC name to the base addresses.

Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/msm_iomap-8x60.h |   10 ++++------
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    2 ++
 arch/arm/mach-msm/io.c                          |    4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index d5482d6..5bd18db 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -35,13 +35,11 @@
  *
  */
 
-#define MSM_QGIC_DIST_BASE	IOMEM(0xF0000000)
-#define MSM_QGIC_DIST_PHYS	0x02080000
-#define MSM_QGIC_DIST_SIZE	SZ_4K
+#define MSM8X60_QGIC_DIST_PHYS	0x02080000
+#define MSM8X60_QGIC_DIST_SIZE	SZ_4K
 
-#define MSM_QGIC_CPU_BASE	IOMEM(0xF0001000)
-#define MSM_QGIC_CPU_PHYS	0x02081000
-#define MSM_QGIC_CPU_SIZE	SZ_4K
+#define MSM8X60_QGIC_CPU_PHYS	0x02081000
+#define MSM8X60_QGIC_CPU_SIZE	SZ_4K
 
 #define MSM_ACC_BASE		IOMEM(0xF0002000)
 #define MSM_ACC_PHYS		0x02001000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 0243bd0..bb42de3 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -55,6 +55,8 @@
 
 /* Virtual addressses shared across all MSM targets. */
 #define MSM_CSR_BASE		IOMEM(0xE0001000)
+#define MSM_QGIC_DIST_BASE	IOMEM(0xF0000000)
+#define MSM_QGIC_CPU_BASE	IOMEM(0xF0001000)
 #define MSM_TMR_BASE		IOMEM(0xF0200000)
 #define MSM_TMR0_BASE		IOMEM(0xF0201000)
 
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 47d699f..5dd0d1b9 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -103,8 +103,8 @@ void __init msm_map_qsd8x50_io(void)
 
 #ifdef CONFIG_ARCH_MSM8X60
 static struct map_desc msm8x60_io_desc[] __initdata = {
-	MSM_DEVICE(QGIC_DIST),
-	MSM_DEVICE(QGIC_CPU),
+	MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60),
+	MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60),
 	MSM_CHIP_DEVICE(TMR, MSM8X60),
 	MSM_CHIP_DEVICE(TMR0, MSM8X60),
 	MSM_DEVICE(ACC),
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 04/11] msm: io: I/O register definitions for MSM8960

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Add the register address definitions for the basic hardware
blocks on the Qualcomm MSM8960 chip.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/io.h             |    1 +
 arch/arm/mach-msm/include/mach/msm_iomap-8960.h |   48 +++++++++++++++++++++++
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    2 +
 arch/arm/mach-msm/io.c                          |   14 +++++++
 4 files changed, 65 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/include/mach/msm_iomap-8960.h

diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index 7386e73..dc1b928 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -29,6 +29,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m
 void msm_map_qsd8x50_io(void);
 void msm_map_msm7x30_io(void);
 void msm_map_msm8x60_io(void);
+void msm_map_msm8960_io(void);
 
 extern unsigned int msm_shared_ram_phys;
 
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
new file mode 100644
index 0000000..3c9d960
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * The MSM peripherals are spread all over across 768MB of physical
+ * space, which makes just having a simple IO_ADDRESS macro to slide
+ * them into the right virtual location rough.  Instead, we will
+ * provide a master phys->virt mapping for peripherals here.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IOMAP_8960_H
+#define __ASM_ARCH_MSM_IOMAP_8960_H
+
+/* Physical base address and size of peripherals.
+ * Ordered by the virtual base addresses they will be mapped at.
+ *
+ * If you add or remove entries here, you'll want to edit the
+ * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
+ * changes.
+ *
+ */
+
+
+#define MSM8960_QGIC_DIST_PHYS	0x02000000
+#define MSM8960_QGIC_DIST_SIZE	SZ_4K
+
+#define MSM8960_QGIC_CPU_PHYS	0x02002000
+#define MSM8960_QGIC_CPU_SIZE	SZ_4K
+
+#define MSM8960_TMR_PHYS	0x0200A000
+#define MSM8960_TMR_SIZE	SZ_4K
+
+#define MSM8960_TMR0_PHYS	0x0208A000
+#define MSM8960_TMR0_SIZE	SZ_4K
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index bb42de3..c98c759 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -53,6 +53,8 @@
 #include "msm_iomap-7x00.h"
 #endif
 
+#include "msm_iomap-8960.h"
+
 /* Virtual addressses shared across all MSM targets. */
 #define MSM_CSR_BASE		IOMEM(0xE0001000)
 #define MSM_QGIC_DIST_BASE	IOMEM(0xF0000000)
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 5dd0d1b9..eea502e 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -117,6 +117,20 @@ void __init msm_map_msm8x60_io(void)
 }
 #endif /* CONFIG_ARCH_MSM8X60 */
 
+#ifdef CONFIG_ARCH_MSM8960
+static struct map_desc msm8960_io_desc[] __initdata = {
+	MSM_CHIP_DEVICE(QGIC_DIST, MSM8960),
+	MSM_CHIP_DEVICE(QGIC_CPU, MSM8960),
+	MSM_CHIP_DEVICE(TMR, MSM8960),
+	MSM_CHIP_DEVICE(TMR0, MSM8960),
+};
+
+void __init msm_map_msm8960_io(void)
+{
+	iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc));
+}
+#endif /* CONFIG_ARCH_MSM8960 */
+
 #ifdef CONFIG_ARCH_MSM7X30
 static struct map_desc msm7x30_io_desc[] __initdata = {
 	MSM_DEVICE(VIC),
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 04/11] msm: io: I/O register definitions for MSM8960

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Add the register address definitions for the basic hardware
blocks on the Qualcomm MSM8960 chip.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/io.h             |    1 +
 arch/arm/mach-msm/include/mach/msm_iomap-8960.h |   48 +++++++++++++++++++++++
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    2 +
 arch/arm/mach-msm/io.c                          |   14 +++++++
 4 files changed, 65 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/include/mach/msm_iomap-8960.h

diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index 7386e73..dc1b928 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -29,6 +29,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m
 void msm_map_qsd8x50_io(void);
 void msm_map_msm7x30_io(void);
 void msm_map_msm8x60_io(void);
+void msm_map_msm8960_io(void);
 
 extern unsigned int msm_shared_ram_phys;
 
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
new file mode 100644
index 0000000..3c9d960
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * The MSM peripherals are spread all over across 768MB of physical
+ * space, which makes just having a simple IO_ADDRESS macro to slide
+ * them into the right virtual location rough.  Instead, we will
+ * provide a master phys->virt mapping for peripherals here.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IOMAP_8960_H
+#define __ASM_ARCH_MSM_IOMAP_8960_H
+
+/* Physical base address and size of peripherals.
+ * Ordered by the virtual base addresses they will be mapped at.
+ *
+ * If you add or remove entries here, you'll want to edit the
+ * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
+ * changes.
+ *
+ */
+
+
+#define MSM8960_QGIC_DIST_PHYS	0x02000000
+#define MSM8960_QGIC_DIST_SIZE	SZ_4K
+
+#define MSM8960_QGIC_CPU_PHYS	0x02002000
+#define MSM8960_QGIC_CPU_SIZE	SZ_4K
+
+#define MSM8960_TMR_PHYS	0x0200A000
+#define MSM8960_TMR_SIZE	SZ_4K
+
+#define MSM8960_TMR0_PHYS	0x0208A000
+#define MSM8960_TMR0_SIZE	SZ_4K
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index bb42de3..c98c759 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -53,6 +53,8 @@
 #include "msm_iomap-7x00.h"
 #endif
 
+#include "msm_iomap-8960.h"
+
 /* Virtual addressses shared across all MSM targets. */
 #define MSM_CSR_BASE		IOMEM(0xE0001000)
 #define MSM_QGIC_DIST_BASE	IOMEM(0xF0000000)
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 5dd0d1b9..eea502e 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -117,6 +117,20 @@ void __init msm_map_msm8x60_io(void)
 }
 #endif /* CONFIG_ARCH_MSM8X60 */
 
+#ifdef CONFIG_ARCH_MSM8960
+static struct map_desc msm8960_io_desc[] __initdata = {
+	MSM_CHIP_DEVICE(QGIC_DIST, MSM8960),
+	MSM_CHIP_DEVICE(QGIC_CPU, MSM8960),
+	MSM_CHIP_DEVICE(TMR, MSM8960),
+	MSM_CHIP_DEVICE(TMR0, MSM8960),
+};
+
+void __init msm_map_msm8960_io(void)
+{
+	iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc));
+}
+#endif /* CONFIG_ARCH_MSM8960 */
+
 #ifdef CONFIG_ARCH_MSM7X30
 static struct map_desc msm7x30_io_desc[] __initdata = {
 	MSM_DEVICE(VIC),
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 05/11] msm: Physical offset for MSM8960

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Add the physical memory offset value for the Qualcomm
MSM8960 chip.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/memory.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
index 070e17d..014bbd3 100644
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -25,6 +25,8 @@
 #define PHYS_OFFSET		UL(0x00200000)
 #elif defined(CONFIG_ARCH_MSM8X60)
 #define PHYS_OFFSET		UL(0x40200000)
+#elif defined(CONFIG_ARCH_MSM8960)
+#define PHYS_OFFSET		UL(0x40200000)
 #else
 #define PHYS_OFFSET		UL(0x10000000)
 #endif
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 05/11] msm: Physical offset for MSM8960

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Add the physical memory offset value for the Qualcomm
MSM8960 chip.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/memory.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
index 070e17d..014bbd3 100644
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -25,6 +25,8 @@
 #define PHYS_OFFSET		UL(0x00200000)
 #elif defined(CONFIG_ARCH_MSM8X60)
 #define PHYS_OFFSET		UL(0x40200000)
+#elif defined(CONFIG_ARCH_MSM8960)
+#define PHYS_OFFSET		UL(0x40200000)
 #else
 #define PHYS_OFFSET		UL(0x10000000)
 #endif
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 05/11] msm: Physical offset for MSM8960

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Add the physical memory offset value for the Qualcomm
MSM8960 chip.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/memory.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
index 070e17d..014bbd3 100644
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -25,6 +25,8 @@
 #define PHYS_OFFSET		UL(0x00200000)
 #elif defined(CONFIG_ARCH_MSM8X60)
 #define PHYS_OFFSET		UL(0x40200000)
+#elif defined(CONFIG_ARCH_MSM8960)
+#define PHYS_OFFSET		UL(0x40200000)
 #else
 #define PHYS_OFFSET		UL(0x10000000)
 #endif
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 06/11] msm: irqs-8960: Interrupt map for MSM8960

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Add the interrupt map for the Qualcomm MSM8960 chip. This
chip has an interrupt map that is different from previous
targets.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/irqs-8960.h |  293 ++++++++++++++++++++++++++++
 arch/arm/mach-msm/include/mach/irqs.h      |    3 +
 2 files changed, 296 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/include/mach/irqs-8960.h

diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h
new file mode 100644
index 0000000..c7f083c
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8960.h
@@ -0,0 +1,293 @@
+/* Copyright (c) 2011 Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_8960_H
+#define __ASM_ARCH_MSM_IRQS_8960_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15:  STI/SGI (software triggered/generated interrupts)
+   16-31: PPI (private peripheral interrupts)
+   32+:   SPI (shared peripheral interrupts) */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_VGIC				(GIC_PPI_START + 0)
+#define INT_DEBUG_TIMER_EXP			(GIC_PPI_START + 1)
+#define INT_GP_TIMER_EXP			(GIC_PPI_START + 2)
+#define INT_GP_TIMER2_EXP			(GIC_PPI_START + 3)
+#define WDT0_ACCSCSSNBARK_INT			(GIC_PPI_START + 4)
+#define WDT1_ACCSCSSNBARK_INT			(GIC_PPI_START + 5)
+#define AVS_SVICINT				(GIC_PPI_START + 6)
+#define AVS_SVICINTSWDONE			(GIC_PPI_START + 7)
+#define CPU_DBGCPUXCOMMRXFULL			(GIC_PPI_START + 8)
+#define CPU_DBGCPUXCOMMTXEMPTY			(GIC_PPI_START + 9)
+#define CPU_SICCPUXPERFMONIRPTREQ		(GIC_PPI_START + 10)
+#define SC_AVSCPUXDOWN				(GIC_PPI_START + 11)
+#define SC_AVSCPUXUP				(GIC_PPI_START + 12)
+#define SC_SICCPUXACGIRPTREQ			(GIC_PPI_START + 13)
+#define SC_SICCPUXEXTFAULTIRPTREQ		(GIC_PPI_START + 14)
+/* PPI 15 is unused */
+
+#define SC_SICMPUIRPTREQ			(GIC_SPI_START + 0)
+#define SC_SICL2IRPTREQ				(GIC_SPI_START + 1)
+#define SC_SICL2PERFMONIRPTREQ			(GIC_SPI_START + 2)
+#define SC_SICAGCIRPTREQ			(GIC_SPI_START + 3)
+#define TLMM_APCC_DIR_CONN_IRQ_0		(GIC_SPI_START + 4)
+#define TLMM_APCC_DIR_CONN_IRQ_1		(GIC_SPI_START + 5)
+#define TLMM_APCC_DIR_CONN_IRQ_2		(GIC_SPI_START + 6)
+#define TLMM_APCC_DIR_CONN_IRQ_3		(GIC_SPI_START + 7)
+#define TLMM_APCC_DIR_CONN_IRQ_4		(GIC_SPI_START + 8)
+#define TLMM_APCC_DIR_CONN_IRQ_5		(GIC_SPI_START + 9)
+#define TLMM_APCC_DIR_CONN_IRQ_6		(GIC_SPI_START + 10)
+#define TLMM_APCC_DIR_CONN_IRQ_7		(GIC_SPI_START + 11)
+#define TLMM_APCC_DIR_CONN_IRQ_8		(GIC_SPI_START + 12)
+#define TLMM_APCC_DIR_CONN_IRQ_9		(GIC_SPI_START + 13)
+#define PM8921_SEC_IRQ_103			(GIC_SPI_START + 14)
+#define PM8018_SEC_IRQ_106			(GIC_SPI_START + 15)
+#define TLMM_APCC_SUMMARY_IRQ			(GIC_SPI_START + 16)
+#define SPDM_RT_1_IRQ				(GIC_SPI_START + 17)
+#define SPDM_DIAG_IRQ				(GIC_SPI_START + 18)
+#define RPM_APCC_CPU0_GP_HIGH_IRQ		(GIC_SPI_START + 19)
+#define RPM_APCC_CPU0_GP_MEDIUM_IRQ		(GIC_SPI_START + 20)
+#define RPM_APCC_CPU0_GP_LOW_IRQ		(GIC_SPI_START + 21)
+#define RPM_APCC_CPU0_WAKE_UP_IRQ		(GIC_SPI_START + 22)
+#define RPM_APCC_CPU1_GP_HIGH_IRQ		(GIC_SPI_START + 23)
+#define RPM_APCC_CPU1_GP_MEDIUM_IRQ		(GIC_SPI_START + 24)
+#define RPM_APCC_CPU1_GP_LOW_IRQ		(GIC_SPI_START + 25)
+#define RPM_APCC_CPU1_WAKE_UP_IRQ		(GIC_SPI_START + 26)
+#define SSBI2_2_SC_CPU0_SECURE_IRQ		(GIC_SPI_START + 27)
+#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ		(GIC_SPI_START + 28)
+#define SSBI2_1_SC_CPU0_SECURE_IRQ		(GIC_SPI_START + 29)
+#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ		(GIC_SPI_START + 30)
+#define MSMC_SC_SEC_CE_IRQ			(GIC_SPI_START + 31)
+#define MSMC_SC_PRI_CE_IRQ			(GIC_SPI_START + 32)
+#define SLIMBUS0_CORE_EE1_IRQ			(GIC_SPI_START + 33)
+#define SLIMBUS0_BAM_EE1_IRQ			(GIC_SPI_START + 34)
+#define Q6FW_WDOG_EXPIRED_IRQ			(GIC_SPI_START + 35)
+#define Q6SW_WDOG_EXPIRED_IRQ			(GIC_SPI_START + 36)
+#define MSS_TO_APPS_IRQ_0			(GIC_SPI_START + 37)
+#define MSS_TO_APPS_IRQ_1			(GIC_SPI_START + 38)
+#define MSS_TO_APPS_IRQ_2			(GIC_SPI_START + 39)
+#define MSS_TO_APPS_IRQ_3			(GIC_SPI_START + 40)
+#define MSS_TO_APPS_IRQ_4			(GIC_SPI_START + 41)
+#define MSS_TO_APPS_IRQ_5			(GIC_SPI_START + 42)
+#define MSS_TO_APPS_IRQ_6			(GIC_SPI_START + 43)
+#define MSS_TO_APPS_IRQ_7			(GIC_SPI_START + 44)
+#define MSS_TO_APPS_IRQ_8			(GIC_SPI_START + 45)
+#define MSS_TO_APPS_IRQ_9			(GIC_SPI_START + 46)
+#define VPE_IRQ					(GIC_SPI_START + 47)
+#define VFE_IRQ					(GIC_SPI_START + 48)
+#define VCODEC_IRQ				(GIC_SPI_START + 49)
+#define TV_ENC_IRQ				(GIC_SPI_START + 50)
+#define SMMU_VPE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 51)
+#define SMMU_VPE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 52)
+#define SMMU_VFE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 53)
+#define SMMU_VFE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 54)
+#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ		(GIC_SPI_START + 55)
+#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 56)
+#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ		(GIC_SPI_START + 57)
+#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 58)
+#define SMMU_ROT_CB_SC_SECURE_IRQ		(GIC_SPI_START + 59)
+#define SMMU_ROT_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 60)
+#define SMMU_MDP1_CB_SC_SECURE_IRQ		(GIC_SPI_START + 61)
+#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 62)
+#define SMMU_MDP0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 63)
+#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 64)
+#define SMMU_JPEGD_CB_SC_SECURE_IRQ		(GIC_SPI_START + 65)
+#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 66)
+#define SMMU_IJPEG_CB_SC_SECURE_IRQ		(GIC_SPI_START + 67)
+#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 68)
+#define SMMU_GFX3D_CB_SC_SECURE_IRQ		(GIC_SPI_START + 69)
+#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 70)
+#define SMMU_GFX2D0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 71)
+#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 72)
+#define ROT_IRQ					(GIC_SPI_START + 73)
+#define MMSS_FABRIC_IRQ				(GIC_SPI_START + 74)
+#define MDP_IRQ					(GIC_SPI_START + 75)
+#define JPEGD_IRQ				(GIC_SPI_START + 76)
+#define JPEG_IRQ				(GIC_SPI_START + 77)
+#define MMSS_IMEM_IRQ				(GIC_SPI_START + 78)
+#define HDMI_IRQ				(GIC_SPI_START + 79)
+#define GFX3D_IRQ				(GIC_SPI_START + 80)
+#define GFX2D0_IRQ				(GIC_SPI_START + 81)
+#define DSI1_IRQ				(GIC_SPI_START + 82)
+#define CSI_1_IRQ				(GIC_SPI_START + 83)
+#define CSI_0_IRQ				(GIC_SPI_START + 84)
+#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ		(GIC_SPI_START + 85)
+#define LPASS_SCSS_MIDI_IRQ			(GIC_SPI_START + 86)
+#define LPASS_Q6SS_WDOG_EXPIRED			(GIC_SPI_START + 87)
+#define LPASS_SCSS_GP_LOW_IRQ			(GIC_SPI_START + 88)
+#define LPASS_SCSS_GP_MEDIUM_IRQ		(GIC_SPI_START + 89)
+#define LPASS_SCSS_GP_HIGH_IRQ			(GIC_SPI_START + 90)
+#define TOP_IMEM_IRQ				(GIC_SPI_START + 91)
+#define FABRIC_SYS_IRQ				(GIC_SPI_START + 92)
+#define FABRIC_APPS_IRQ				(GIC_SPI_START + 93)
+#define USB1_HS_BAM_IRQ				(GIC_SPI_START + 94)
+#define SDC4_BAM_IRQ				(GIC_SPI_START + 95)
+#define SDC3_BAM_IRQ				(GIC_SPI_START + 96)
+#define SDC2_BAM_IRQ				(GIC_SPI_START + 97)
+#define SDC1_BAM_IRQ				(GIC_SPI_START + 98)
+#define FABRIC_SPS_IRQ				(GIC_SPI_START + 99)
+#define USB1_HS_IRQ				(GIC_SPI_START + 100)
+#define SDC4_IRQ_0				(GIC_SPI_START + 101)
+#define SDC3_IRQ_0				(GIC_SPI_START + 102)
+#define SDC2_IRQ_0				(GIC_SPI_START + 103)
+#define SDC1_IRQ_0				(GIC_SPI_START + 104)
+#define SPS_BAM_DMA_IRQ				(GIC_SPI_START + 105)
+#define SPS_SEC_VIOL_IRQ			(GIC_SPI_START + 106)
+#define SPS_MTI_0				(GIC_SPI_START + 107)
+#define SPS_MTI_1				(GIC_SPI_START + 108)
+#define SPS_MTI_2				(GIC_SPI_START + 109)
+#define SPS_MTI_3				(GIC_SPI_START + 110)
+#define SPS_MTI_4				(GIC_SPI_START + 111)
+#define SPS_MTI_5				(GIC_SPI_START + 112)
+#define SPS_MTI_6				(GIC_SPI_START + 113)
+#define SPS_MTI_7				(GIC_SPI_START + 114)
+#define SPS_MTI_8				(GIC_SPI_START + 115)
+#define SPS_MTI_9				(GIC_SPI_START + 116)
+#define SPS_MTI_10				(GIC_SPI_START + 117)
+#define SPS_MTI_11				(GIC_SPI_START + 118)
+#define SPS_MTI_12				(GIC_SPI_START + 119)
+#define SPS_MTI_13				(GIC_SPI_START + 120)
+#define SPS_MTI_14				(GIC_SPI_START + 121)
+#define SPS_MTI_15				(GIC_SPI_START + 122)
+#define SPS_MTI_16				(GIC_SPI_START + 123)
+#define SPS_MTI_17				(GIC_SPI_START + 124)
+#define SPS_MTI_18				(GIC_SPI_START + 125)
+#define SPS_MTI_19				(GIC_SPI_START + 126)
+#define SPS_MTI_20				(GIC_SPI_START + 127)
+#define SPS_MTI_21				(GIC_SPI_START + 128)
+#define SPS_MTI_22				(GIC_SPI_START + 129)
+#define SPS_MTI_23				(GIC_SPI_START + 130)
+#define SPS_MTI_24				(GIC_SPI_START + 131)
+#define SPS_MTI_25				(GIC_SPI_START + 132)
+#define SPS_MTI_26				(GIC_SPI_START + 133)
+#define SPS_MTI_27				(GIC_SPI_START + 134)
+#define SPS_MTI_28				(GIC_SPI_START + 135)
+#define SPS_MTI_29				(GIC_SPI_START + 136)
+#define SPS_MTI_30				(GIC_SPI_START + 137)
+#define SPS_MTI_31				(GIC_SPI_START + 138)
+#define CSIPHY_4LN_IRQ				(GIC_SPI_START + 139)
+#define CSIPHY_2LN_IRQ				(GIC_SPI_START + 140)
+#define USB2_IRQ				(GIC_SPI_START + 141)
+#define USB1_IRQ				(GIC_SPI_START + 142)
+#define TSSC_SSBI_IRQ				(GIC_SPI_START + 143)
+#define TSSC_SAMPLE_IRQ				(GIC_SPI_START + 144)
+#define TSSC_PENUP_IRQ				(GIC_SPI_START + 145)
+#define GSBI1_UARTDM_IRQ			(GIC_SPI_START + 146)
+#define GSBI1_QUP_IRQ				(GIC_SPI_START + 147)
+#define GSBI2_UARTDM_IRQ			(GIC_SPI_START + 148)
+#define GSBI2_QUP_IRQ			        (GIC_SPI_START + 149)
+#define GSBI3_UARTDM_IRQ			(GIC_SPI_START + 150)
+#define GSBI3_QUP_IRQ				(GIC_SPI_START + 151)
+#define GSBI4_UARTDM_IRQ			(GIC_SPI_START + 152)
+#define GSBI4_QUP_IRQ				(GIC_SPI_START + 153)
+#define GSBI5_UARTDM_IRQ			(GIC_SPI_START + 154)
+#define GSBI5_QUP_IRQ				(GIC_SPI_START + 155)
+#define GSBI6_UARTDM_IRQ			(GIC_SPI_START + 156)
+#define GSBI6_QUP_IRQ				(GIC_SPI_START + 157)
+#define GSBI7_UARTDM_IRQ			(GIC_SPI_START + 158)
+#define GSBI7_QUP_IRQ				(GIC_SPI_START + 159)
+#define GSBI8_UARTDM_IRQ			(GIC_SPI_START + 160)
+#define GSBI8_QUP_IRQ				(GIC_SPI_START + 161)
+#define TSIF_TSPP_IRQ				(GIC_SPI_START + 162)
+#define TSIF_BAM_IRQ				(GIC_SPI_START + 163)
+#define TSIF2_IRQ				(GIC_SPI_START + 164)
+#define TSIF1_IRQ				(GIC_SPI_START + 165)
+#define DSI2_IRQ				(GIC_SPI_START + 166)
+#define ISPIF_IRQ				(GIC_SPI_START + 167)
+#define MSMC_SC_SEC_TMR_IRQ			(GIC_SPI_START + 168)
+#define MSMC_SC_SEC_WDOG_BARK_IRQ		(GIC_SPI_START + 169)
+#define INT_ADM0_SCSS_0_IRQ			(GIC_SPI_START + 170)
+#define INT_ADM0_SCSS_1_IRQ			(GIC_SPI_START + 171)
+#define INT_ADM0_SCSS_2_IRQ			(GIC_SPI_START + 172)
+#define INT_ADM0_SCSS_3_IRQ			(GIC_SPI_START + 173)
+#define CC_SCSS_WDT1CPU1BITEEXPIRED		(GIC_SPI_START + 174)
+#define CC_SCSS_WDT1CPU0BITEEXPIRED		(GIC_SPI_START + 175)
+#define CC_SCSS_WDT0CPU1BITEEXPIRED		(GIC_SPI_START + 176)
+#define CC_SCSS_WDT0CPU0BITEEXPIRED		(GIC_SPI_START + 177)
+#define TSENS_UPPER_LOWER_INT			(GIC_SPI_START + 178)
+#define SSBI2_2_SC_CPU1_SECURE_INT		(GIC_SPI_START + 179)
+#define SSBI2_2_SC_CPU1_NON_SECURE_INT		(GIC_SPI_START + 180)
+#define SSBI2_1_SC_CPU1_SECURE_INT		(GIC_SPI_START + 181)
+#define SSBI2_1_SC_CPU1_NON_SECURE_INT		(GIC_SPI_START + 182)
+#define XPU_SUMMARY_IRQ				(GIC_SPI_START + 183)
+#define BUS_EXCEPTION_SUMMARY_IRQ		(GIC_SPI_START + 184)
+#define HSDDRX_EBI1CH0_IRQ			(GIC_SPI_START + 185)
+#define HSDDRX_EBI1CH1_IRQ			(GIC_SPI_START + 186)
+#define SDC5_BAM_IRQ				(GIC_SPI_START + 187)
+#define SDC5_IRQ_0				(GIC_SPI_START + 188)
+#define GSBI9_UARTDM_IRQ			(GIC_SPI_START + 189)
+#define GSBI9_QUP_IRQ				(GIC_SPI_START + 190)
+#define GSBI10_UARTDM_IRQ			(GIC_SPI_START + 191)
+#define GSBI10_QUP_IRQ				(GIC_SPI_START + 192)
+#define GSBI11_UARTDM_IRQ			(GIC_SPI_START + 193)
+#define GSBI11_QUP_IRQ				(GIC_SPI_START + 194)
+#define GSBI12_UARTDM_IRQ			(GIC_SPI_START + 195)
+#define GSBI12_QUP_IRQ				(GIC_SPI_START + 196)
+#define RIVA_APSS_LTECOEX_IRQ			(GIC_SPI_START + 197)
+#define RIVA_APSS_SPARE_IRQ			(GIC_SPI_START + 198)
+#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ	(GIC_SPI_START + 199)
+#define RIVA_ASS_RESET_DONE_IRQ			(GIC_SPI_START + 200)
+#define RIVA_APSS_ASIC_IRQ			(GIC_SPI_START + 201)
+#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ	(GIC_SPI_START + 202)
+#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ	(GIC_SPI_START + 203)
+#define RIVA_APPS_WLAM_SMSM_IRQ			(GIC_SPI_START + 204)
+#define RIVA_APPS_LOG_CTRL_IRQ			(GIC_SPI_START + 205)
+#define RIVA_APPS_FM_CTRL_IRQ			(GIC_SPI_START + 206)
+#define RIVA_APPS_HCI_IRQ			(GIC_SPI_START + 207)
+#define RIVA_APPS_WLAN_CTRL_IRQ			(GIC_SPI_START + 208)
+#define A2_BAM_IRQ				(GIC_SPI_START + 209)
+#define SMMU_GFX2D1_CB_SC_SECURE_IRQ		(GIC_SPI_START + 210)
+#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 211)
+#define GFX2D1_IRQ				(GIC_SPI_START + 212)
+#define PPSS_WDOG_TIMER_IRQ			(GIC_SPI_START + 213)
+#define SPS_SLIMBUS_CORE_EE0_IRQ		(GIC_SPI_START + 214)
+#define SPS_SLIMBUS_BAM_EE0_IRQ			(GIC_SPI_START + 215)
+#define QDSS_ETB_IRQ				(GIC_SPI_START + 216)
+#define QDSS_CTI2KPSS_CPU1_IRQ			(GIC_SPI_START + 217)
+#define QDSS_CTI2KPSS_CPU0_IRQ			(GIC_SPI_START + 218)
+#define TLMM_APCC_DIR_CONN_IRQ_16		(GIC_SPI_START + 219)
+#define TLMM_APCC_DIR_CONN_IRQ_17		(GIC_SPI_START + 220)
+#define TLMM_APCC_DIR_CONN_IRQ_18		(GIC_SPI_START + 221)
+#define TLMM_APCC_DIR_CONN_IRQ_19		(GIC_SPI_START + 222)
+#define TLMM_APCC_DIR_CONN_IRQ_20		(GIC_SPI_START + 223)
+#define TLMM_APCC_DIR_CONN_IRQ_21		(GIC_SPI_START + 224)
+#define PM8921_SEC_IRQ_104			(GIC_SPI_START + 225)
+#define PM8018_SEC_IRQ_107			(GIC_SPI_START + 226)
+
+/* For now, use the maximum number of interrupts until a pending GIC issue
+ * is sorted out */
+#define NR_MSM_IRQS 1020
+#define NR_BOARD_IRQS 0
+#define NR_GPIO_IRQS 0
+
+#endif
+
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 8679a45..3cd78b1 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -26,6 +26,9 @@
 #include "sirc.h"
 #elif defined(CONFIG_ARCH_MSM8X60)
 #include "irqs-8x60.h"
+#elif defined(CONFIG_ARCH_MSM8960)
+/* TODO: Make these not generic. */
+#include "irqs-8960.h"
 #elif defined(CONFIG_ARCH_MSM_ARM11)
 #include "irqs-7x00.h"
 #else
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 06/11] msm: irqs-8960: Interrupt map for MSM8960

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Add the interrupt map for the Qualcomm MSM8960 chip. This
chip has an interrupt map that is different from previous
targets.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/irqs-8960.h |  293 ++++++++++++++++++++++++++++
 arch/arm/mach-msm/include/mach/irqs.h      |    3 +
 2 files changed, 296 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/include/mach/irqs-8960.h

diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h
new file mode 100644
index 0000000..c7f083c
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8960.h
@@ -0,0 +1,293 @@
+/* Copyright (c) 2011 Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_8960_H
+#define __ASM_ARCH_MSM_IRQS_8960_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15:  STI/SGI (software triggered/generated interrupts)
+   16-31: PPI (private peripheral interrupts)
+   32+:   SPI (shared peripheral interrupts) */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_VGIC				(GIC_PPI_START + 0)
+#define INT_DEBUG_TIMER_EXP			(GIC_PPI_START + 1)
+#define INT_GP_TIMER_EXP			(GIC_PPI_START + 2)
+#define INT_GP_TIMER2_EXP			(GIC_PPI_START + 3)
+#define WDT0_ACCSCSSNBARK_INT			(GIC_PPI_START + 4)
+#define WDT1_ACCSCSSNBARK_INT			(GIC_PPI_START + 5)
+#define AVS_SVICINT				(GIC_PPI_START + 6)
+#define AVS_SVICINTSWDONE			(GIC_PPI_START + 7)
+#define CPU_DBGCPUXCOMMRXFULL			(GIC_PPI_START + 8)
+#define CPU_DBGCPUXCOMMTXEMPTY			(GIC_PPI_START + 9)
+#define CPU_SICCPUXPERFMONIRPTREQ		(GIC_PPI_START + 10)
+#define SC_AVSCPUXDOWN				(GIC_PPI_START + 11)
+#define SC_AVSCPUXUP				(GIC_PPI_START + 12)
+#define SC_SICCPUXACGIRPTREQ			(GIC_PPI_START + 13)
+#define SC_SICCPUXEXTFAULTIRPTREQ		(GIC_PPI_START + 14)
+/* PPI 15 is unused */
+
+#define SC_SICMPUIRPTREQ			(GIC_SPI_START + 0)
+#define SC_SICL2IRPTREQ				(GIC_SPI_START + 1)
+#define SC_SICL2PERFMONIRPTREQ			(GIC_SPI_START + 2)
+#define SC_SICAGCIRPTREQ			(GIC_SPI_START + 3)
+#define TLMM_APCC_DIR_CONN_IRQ_0		(GIC_SPI_START + 4)
+#define TLMM_APCC_DIR_CONN_IRQ_1		(GIC_SPI_START + 5)
+#define TLMM_APCC_DIR_CONN_IRQ_2		(GIC_SPI_START + 6)
+#define TLMM_APCC_DIR_CONN_IRQ_3		(GIC_SPI_START + 7)
+#define TLMM_APCC_DIR_CONN_IRQ_4		(GIC_SPI_START + 8)
+#define TLMM_APCC_DIR_CONN_IRQ_5		(GIC_SPI_START + 9)
+#define TLMM_APCC_DIR_CONN_IRQ_6		(GIC_SPI_START + 10)
+#define TLMM_APCC_DIR_CONN_IRQ_7		(GIC_SPI_START + 11)
+#define TLMM_APCC_DIR_CONN_IRQ_8		(GIC_SPI_START + 12)
+#define TLMM_APCC_DIR_CONN_IRQ_9		(GIC_SPI_START + 13)
+#define PM8921_SEC_IRQ_103			(GIC_SPI_START + 14)
+#define PM8018_SEC_IRQ_106			(GIC_SPI_START + 15)
+#define TLMM_APCC_SUMMARY_IRQ			(GIC_SPI_START + 16)
+#define SPDM_RT_1_IRQ				(GIC_SPI_START + 17)
+#define SPDM_DIAG_IRQ				(GIC_SPI_START + 18)
+#define RPM_APCC_CPU0_GP_HIGH_IRQ		(GIC_SPI_START + 19)
+#define RPM_APCC_CPU0_GP_MEDIUM_IRQ		(GIC_SPI_START + 20)
+#define RPM_APCC_CPU0_GP_LOW_IRQ		(GIC_SPI_START + 21)
+#define RPM_APCC_CPU0_WAKE_UP_IRQ		(GIC_SPI_START + 22)
+#define RPM_APCC_CPU1_GP_HIGH_IRQ		(GIC_SPI_START + 23)
+#define RPM_APCC_CPU1_GP_MEDIUM_IRQ		(GIC_SPI_START + 24)
+#define RPM_APCC_CPU1_GP_LOW_IRQ		(GIC_SPI_START + 25)
+#define RPM_APCC_CPU1_WAKE_UP_IRQ		(GIC_SPI_START + 26)
+#define SSBI2_2_SC_CPU0_SECURE_IRQ		(GIC_SPI_START + 27)
+#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ		(GIC_SPI_START + 28)
+#define SSBI2_1_SC_CPU0_SECURE_IRQ		(GIC_SPI_START + 29)
+#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ		(GIC_SPI_START + 30)
+#define MSMC_SC_SEC_CE_IRQ			(GIC_SPI_START + 31)
+#define MSMC_SC_PRI_CE_IRQ			(GIC_SPI_START + 32)
+#define SLIMBUS0_CORE_EE1_IRQ			(GIC_SPI_START + 33)
+#define SLIMBUS0_BAM_EE1_IRQ			(GIC_SPI_START + 34)
+#define Q6FW_WDOG_EXPIRED_IRQ			(GIC_SPI_START + 35)
+#define Q6SW_WDOG_EXPIRED_IRQ			(GIC_SPI_START + 36)
+#define MSS_TO_APPS_IRQ_0			(GIC_SPI_START + 37)
+#define MSS_TO_APPS_IRQ_1			(GIC_SPI_START + 38)
+#define MSS_TO_APPS_IRQ_2			(GIC_SPI_START + 39)
+#define MSS_TO_APPS_IRQ_3			(GIC_SPI_START + 40)
+#define MSS_TO_APPS_IRQ_4			(GIC_SPI_START + 41)
+#define MSS_TO_APPS_IRQ_5			(GIC_SPI_START + 42)
+#define MSS_TO_APPS_IRQ_6			(GIC_SPI_START + 43)
+#define MSS_TO_APPS_IRQ_7			(GIC_SPI_START + 44)
+#define MSS_TO_APPS_IRQ_8			(GIC_SPI_START + 45)
+#define MSS_TO_APPS_IRQ_9			(GIC_SPI_START + 46)
+#define VPE_IRQ					(GIC_SPI_START + 47)
+#define VFE_IRQ					(GIC_SPI_START + 48)
+#define VCODEC_IRQ				(GIC_SPI_START + 49)
+#define TV_ENC_IRQ				(GIC_SPI_START + 50)
+#define SMMU_VPE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 51)
+#define SMMU_VPE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 52)
+#define SMMU_VFE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 53)
+#define SMMU_VFE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 54)
+#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ		(GIC_SPI_START + 55)
+#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 56)
+#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ		(GIC_SPI_START + 57)
+#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 58)
+#define SMMU_ROT_CB_SC_SECURE_IRQ		(GIC_SPI_START + 59)
+#define SMMU_ROT_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 60)
+#define SMMU_MDP1_CB_SC_SECURE_IRQ		(GIC_SPI_START + 61)
+#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 62)
+#define SMMU_MDP0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 63)
+#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 64)
+#define SMMU_JPEGD_CB_SC_SECURE_IRQ		(GIC_SPI_START + 65)
+#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 66)
+#define SMMU_IJPEG_CB_SC_SECURE_IRQ		(GIC_SPI_START + 67)
+#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 68)
+#define SMMU_GFX3D_CB_SC_SECURE_IRQ		(GIC_SPI_START + 69)
+#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 70)
+#define SMMU_GFX2D0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 71)
+#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 72)
+#define ROT_IRQ					(GIC_SPI_START + 73)
+#define MMSS_FABRIC_IRQ				(GIC_SPI_START + 74)
+#define MDP_IRQ					(GIC_SPI_START + 75)
+#define JPEGD_IRQ				(GIC_SPI_START + 76)
+#define JPEG_IRQ				(GIC_SPI_START + 77)
+#define MMSS_IMEM_IRQ				(GIC_SPI_START + 78)
+#define HDMI_IRQ				(GIC_SPI_START + 79)
+#define GFX3D_IRQ				(GIC_SPI_START + 80)
+#define GFX2D0_IRQ				(GIC_SPI_START + 81)
+#define DSI1_IRQ				(GIC_SPI_START + 82)
+#define CSI_1_IRQ				(GIC_SPI_START + 83)
+#define CSI_0_IRQ				(GIC_SPI_START + 84)
+#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ		(GIC_SPI_START + 85)
+#define LPASS_SCSS_MIDI_IRQ			(GIC_SPI_START + 86)
+#define LPASS_Q6SS_WDOG_EXPIRED			(GIC_SPI_START + 87)
+#define LPASS_SCSS_GP_LOW_IRQ			(GIC_SPI_START + 88)
+#define LPASS_SCSS_GP_MEDIUM_IRQ		(GIC_SPI_START + 89)
+#define LPASS_SCSS_GP_HIGH_IRQ			(GIC_SPI_START + 90)
+#define TOP_IMEM_IRQ				(GIC_SPI_START + 91)
+#define FABRIC_SYS_IRQ				(GIC_SPI_START + 92)
+#define FABRIC_APPS_IRQ				(GIC_SPI_START + 93)
+#define USB1_HS_BAM_IRQ				(GIC_SPI_START + 94)
+#define SDC4_BAM_IRQ				(GIC_SPI_START + 95)
+#define SDC3_BAM_IRQ				(GIC_SPI_START + 96)
+#define SDC2_BAM_IRQ				(GIC_SPI_START + 97)
+#define SDC1_BAM_IRQ				(GIC_SPI_START + 98)
+#define FABRIC_SPS_IRQ				(GIC_SPI_START + 99)
+#define USB1_HS_IRQ				(GIC_SPI_START + 100)
+#define SDC4_IRQ_0				(GIC_SPI_START + 101)
+#define SDC3_IRQ_0				(GIC_SPI_START + 102)
+#define SDC2_IRQ_0				(GIC_SPI_START + 103)
+#define SDC1_IRQ_0				(GIC_SPI_START + 104)
+#define SPS_BAM_DMA_IRQ				(GIC_SPI_START + 105)
+#define SPS_SEC_VIOL_IRQ			(GIC_SPI_START + 106)
+#define SPS_MTI_0				(GIC_SPI_START + 107)
+#define SPS_MTI_1				(GIC_SPI_START + 108)
+#define SPS_MTI_2				(GIC_SPI_START + 109)
+#define SPS_MTI_3				(GIC_SPI_START + 110)
+#define SPS_MTI_4				(GIC_SPI_START + 111)
+#define SPS_MTI_5				(GIC_SPI_START + 112)
+#define SPS_MTI_6				(GIC_SPI_START + 113)
+#define SPS_MTI_7				(GIC_SPI_START + 114)
+#define SPS_MTI_8				(GIC_SPI_START + 115)
+#define SPS_MTI_9				(GIC_SPI_START + 116)
+#define SPS_MTI_10				(GIC_SPI_START + 117)
+#define SPS_MTI_11				(GIC_SPI_START + 118)
+#define SPS_MTI_12				(GIC_SPI_START + 119)
+#define SPS_MTI_13				(GIC_SPI_START + 120)
+#define SPS_MTI_14				(GIC_SPI_START + 121)
+#define SPS_MTI_15				(GIC_SPI_START + 122)
+#define SPS_MTI_16				(GIC_SPI_START + 123)
+#define SPS_MTI_17				(GIC_SPI_START + 124)
+#define SPS_MTI_18				(GIC_SPI_START + 125)
+#define SPS_MTI_19				(GIC_SPI_START + 126)
+#define SPS_MTI_20				(GIC_SPI_START + 127)
+#define SPS_MTI_21				(GIC_SPI_START + 128)
+#define SPS_MTI_22				(GIC_SPI_START + 129)
+#define SPS_MTI_23				(GIC_SPI_START + 130)
+#define SPS_MTI_24				(GIC_SPI_START + 131)
+#define SPS_MTI_25				(GIC_SPI_START + 132)
+#define SPS_MTI_26				(GIC_SPI_START + 133)
+#define SPS_MTI_27				(GIC_SPI_START + 134)
+#define SPS_MTI_28				(GIC_SPI_START + 135)
+#define SPS_MTI_29				(GIC_SPI_START + 136)
+#define SPS_MTI_30				(GIC_SPI_START + 137)
+#define SPS_MTI_31				(GIC_SPI_START + 138)
+#define CSIPHY_4LN_IRQ				(GIC_SPI_START + 139)
+#define CSIPHY_2LN_IRQ				(GIC_SPI_START + 140)
+#define USB2_IRQ				(GIC_SPI_START + 141)
+#define USB1_IRQ				(GIC_SPI_START + 142)
+#define TSSC_SSBI_IRQ				(GIC_SPI_START + 143)
+#define TSSC_SAMPLE_IRQ				(GIC_SPI_START + 144)
+#define TSSC_PENUP_IRQ				(GIC_SPI_START + 145)
+#define GSBI1_UARTDM_IRQ			(GIC_SPI_START + 146)
+#define GSBI1_QUP_IRQ				(GIC_SPI_START + 147)
+#define GSBI2_UARTDM_IRQ			(GIC_SPI_START + 148)
+#define GSBI2_QUP_IRQ			        (GIC_SPI_START + 149)
+#define GSBI3_UARTDM_IRQ			(GIC_SPI_START + 150)
+#define GSBI3_QUP_IRQ				(GIC_SPI_START + 151)
+#define GSBI4_UARTDM_IRQ			(GIC_SPI_START + 152)
+#define GSBI4_QUP_IRQ				(GIC_SPI_START + 153)
+#define GSBI5_UARTDM_IRQ			(GIC_SPI_START + 154)
+#define GSBI5_QUP_IRQ				(GIC_SPI_START + 155)
+#define GSBI6_UARTDM_IRQ			(GIC_SPI_START + 156)
+#define GSBI6_QUP_IRQ				(GIC_SPI_START + 157)
+#define GSBI7_UARTDM_IRQ			(GIC_SPI_START + 158)
+#define GSBI7_QUP_IRQ				(GIC_SPI_START + 159)
+#define GSBI8_UARTDM_IRQ			(GIC_SPI_START + 160)
+#define GSBI8_QUP_IRQ				(GIC_SPI_START + 161)
+#define TSIF_TSPP_IRQ				(GIC_SPI_START + 162)
+#define TSIF_BAM_IRQ				(GIC_SPI_START + 163)
+#define TSIF2_IRQ				(GIC_SPI_START + 164)
+#define TSIF1_IRQ				(GIC_SPI_START + 165)
+#define DSI2_IRQ				(GIC_SPI_START + 166)
+#define ISPIF_IRQ				(GIC_SPI_START + 167)
+#define MSMC_SC_SEC_TMR_IRQ			(GIC_SPI_START + 168)
+#define MSMC_SC_SEC_WDOG_BARK_IRQ		(GIC_SPI_START + 169)
+#define INT_ADM0_SCSS_0_IRQ			(GIC_SPI_START + 170)
+#define INT_ADM0_SCSS_1_IRQ			(GIC_SPI_START + 171)
+#define INT_ADM0_SCSS_2_IRQ			(GIC_SPI_START + 172)
+#define INT_ADM0_SCSS_3_IRQ			(GIC_SPI_START + 173)
+#define CC_SCSS_WDT1CPU1BITEEXPIRED		(GIC_SPI_START + 174)
+#define CC_SCSS_WDT1CPU0BITEEXPIRED		(GIC_SPI_START + 175)
+#define CC_SCSS_WDT0CPU1BITEEXPIRED		(GIC_SPI_START + 176)
+#define CC_SCSS_WDT0CPU0BITEEXPIRED		(GIC_SPI_START + 177)
+#define TSENS_UPPER_LOWER_INT			(GIC_SPI_START + 178)
+#define SSBI2_2_SC_CPU1_SECURE_INT		(GIC_SPI_START + 179)
+#define SSBI2_2_SC_CPU1_NON_SECURE_INT		(GIC_SPI_START + 180)
+#define SSBI2_1_SC_CPU1_SECURE_INT		(GIC_SPI_START + 181)
+#define SSBI2_1_SC_CPU1_NON_SECURE_INT		(GIC_SPI_START + 182)
+#define XPU_SUMMARY_IRQ				(GIC_SPI_START + 183)
+#define BUS_EXCEPTION_SUMMARY_IRQ		(GIC_SPI_START + 184)
+#define HSDDRX_EBI1CH0_IRQ			(GIC_SPI_START + 185)
+#define HSDDRX_EBI1CH1_IRQ			(GIC_SPI_START + 186)
+#define SDC5_BAM_IRQ				(GIC_SPI_START + 187)
+#define SDC5_IRQ_0				(GIC_SPI_START + 188)
+#define GSBI9_UARTDM_IRQ			(GIC_SPI_START + 189)
+#define GSBI9_QUP_IRQ				(GIC_SPI_START + 190)
+#define GSBI10_UARTDM_IRQ			(GIC_SPI_START + 191)
+#define GSBI10_QUP_IRQ				(GIC_SPI_START + 192)
+#define GSBI11_UARTDM_IRQ			(GIC_SPI_START + 193)
+#define GSBI11_QUP_IRQ				(GIC_SPI_START + 194)
+#define GSBI12_UARTDM_IRQ			(GIC_SPI_START + 195)
+#define GSBI12_QUP_IRQ				(GIC_SPI_START + 196)
+#define RIVA_APSS_LTECOEX_IRQ			(GIC_SPI_START + 197)
+#define RIVA_APSS_SPARE_IRQ			(GIC_SPI_START + 198)
+#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ	(GIC_SPI_START + 199)
+#define RIVA_ASS_RESET_DONE_IRQ			(GIC_SPI_START + 200)
+#define RIVA_APSS_ASIC_IRQ			(GIC_SPI_START + 201)
+#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ	(GIC_SPI_START + 202)
+#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ	(GIC_SPI_START + 203)
+#define RIVA_APPS_WLAM_SMSM_IRQ			(GIC_SPI_START + 204)
+#define RIVA_APPS_LOG_CTRL_IRQ			(GIC_SPI_START + 205)
+#define RIVA_APPS_FM_CTRL_IRQ			(GIC_SPI_START + 206)
+#define RIVA_APPS_HCI_IRQ			(GIC_SPI_START + 207)
+#define RIVA_APPS_WLAN_CTRL_IRQ			(GIC_SPI_START + 208)
+#define A2_BAM_IRQ				(GIC_SPI_START + 209)
+#define SMMU_GFX2D1_CB_SC_SECURE_IRQ		(GIC_SPI_START + 210)
+#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 211)
+#define GFX2D1_IRQ				(GIC_SPI_START + 212)
+#define PPSS_WDOG_TIMER_IRQ			(GIC_SPI_START + 213)
+#define SPS_SLIMBUS_CORE_EE0_IRQ		(GIC_SPI_START + 214)
+#define SPS_SLIMBUS_BAM_EE0_IRQ			(GIC_SPI_START + 215)
+#define QDSS_ETB_IRQ				(GIC_SPI_START + 216)
+#define QDSS_CTI2KPSS_CPU1_IRQ			(GIC_SPI_START + 217)
+#define QDSS_CTI2KPSS_CPU0_IRQ			(GIC_SPI_START + 218)
+#define TLMM_APCC_DIR_CONN_IRQ_16		(GIC_SPI_START + 219)
+#define TLMM_APCC_DIR_CONN_IRQ_17		(GIC_SPI_START + 220)
+#define TLMM_APCC_DIR_CONN_IRQ_18		(GIC_SPI_START + 221)
+#define TLMM_APCC_DIR_CONN_IRQ_19		(GIC_SPI_START + 222)
+#define TLMM_APCC_DIR_CONN_IRQ_20		(GIC_SPI_START + 223)
+#define TLMM_APCC_DIR_CONN_IRQ_21		(GIC_SPI_START + 224)
+#define PM8921_SEC_IRQ_104			(GIC_SPI_START + 225)
+#define PM8018_SEC_IRQ_107			(GIC_SPI_START + 226)
+
+/* For now, use the maximum number of interrupts until a pending GIC issue
+ * is sorted out */
+#define NR_MSM_IRQS 1020
+#define NR_BOARD_IRQS 0
+#define NR_GPIO_IRQS 0
+
+#endif
+
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 8679a45..3cd78b1 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -26,6 +26,9 @@
 #include "sirc.h"
 #elif defined(CONFIG_ARCH_MSM8X60)
 #include "irqs-8x60.h"
+#elif defined(CONFIG_ARCH_MSM8960)
+/* TODO: Make these not generic. */
+#include "irqs-8960.h"
 #elif defined(CONFIG_ARCH_MSM_ARM11)
 #include "irqs-7x00.h"
 #else
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 07/11] msm: Add MSM 8960 cpu_is check

[David Brown]

Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/cpu.h |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h
index e1ba9db..a9481b0 100644
--- a/arch/arm/mach-msm/include/mach/cpu.h
+++ b/arch/arm/mach-msm/include/mach/cpu.h
@@ -24,6 +24,7 @@
 #define cpu_is_msm7x30()	0
 #define cpu_is_qsd8x50()	0
 #define cpu_is_msm8x60()	0
+#define cpu_is_msm8960()	0
 
 #ifdef CONFIG_ARCH_MSM7X00A
 # undef cpu_is_msm7x01
@@ -45,4 +46,9 @@
 # define cpu_is_msm8x60()	1
 #endif
 
+#ifdef CONFIG_ARCH_MSM8960
+# undef cpu_is_msm8960
+# define cpu_is_msm8960()	1
+#endif
+
 #endif
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 07/11] msm: Add MSM 8960 cpu_is check

[David Brown]

Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/cpu.h |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h
index e1ba9db..a9481b0 100644
--- a/arch/arm/mach-msm/include/mach/cpu.h
+++ b/arch/arm/mach-msm/include/mach/cpu.h
@@ -24,6 +24,7 @@
 #define cpu_is_msm7x30()	0
 #define cpu_is_qsd8x50()	0
 #define cpu_is_msm8x60()	0
+#define cpu_is_msm8960()	0
 
 #ifdef CONFIG_ARCH_MSM7X00A
 # undef cpu_is_msm7x01
@@ -45,4 +46,9 @@
 # define cpu_is_msm8x60()	1
 #endif
 
+#ifdef CONFIG_ARCH_MSM8960
+# undef cpu_is_msm8960
+# define cpu_is_msm8960()	1
+#endif
+
 #endif
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 08/11] msm: timer: Timer support for MSM8960

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Modify the macros in the MSM timer driver to support the
MSM8960 chip.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/timer.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 5548b15..e7f8e5a 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -55,7 +55,8 @@ enum timer_location {
 #if defined(CONFIG_ARCH_QSD8X50)
 #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
 #define MSM_DGT_SHIFT (0)
-#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60)
+#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \
+				      defined(CONFIG_ARCH_MSM8960)
 #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
 #define MSM_DGT_SHIFT (0)
 #else
@@ -214,7 +215,7 @@ static void __init msm_timer_init(void)
 	} else if (cpu_is_qsd8x50()) {
 		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
 		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
-	} else if (cpu_is_msm8x60()) {
+	} else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
 		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
 		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
 
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 08/11] msm: timer: Timer support for MSM8960

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Modify the macros in the MSM timer driver to support the
MSM8960 chip.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/timer.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 5548b15..e7f8e5a 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -55,7 +55,8 @@ enum timer_location {
 #if defined(CONFIG_ARCH_QSD8X50)
 #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
 #define MSM_DGT_SHIFT (0)
-#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60)
+#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \
+				      defined(CONFIG_ARCH_MSM8960)
 #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
 #define MSM_DGT_SHIFT (0)
 #else
@@ -214,7 +215,7 @@ static void __init msm_timer_init(void)
 	} else if (cpu_is_qsd8x50()) {
 		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
 		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
-	} else if (cpu_is_msm8x60()) {
+	} else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
 		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
 		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
 
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 09/11] msm: Makefile cleanup

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Clean up some of the conditionals in the Makefile in
preparation for adding build support for MSM8960.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/Makefile |   18 ++++++------------
 1 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 94195c1..3e15ff3 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,21 +1,15 @@
 obj-y += io.o idle.o timer.o
-ifndef CONFIG_ARCH_MSM8X60
-obj-y += acpuclock-arm11.o
-obj-y += dma.o
-endif
 
-ifdef CONFIG_MSM_VIC
-obj-y += irq-vic.o
-else
-ifndef CONFIG_ARCH_MSM8X60
-obj-y += irq.o
-endif
-endif
+obj-$(CONFIG_MSM_VIC) += irq-vic.o
 
+obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
+obj-$(CONFIG_ARCH_MSM7X30) += dma.o
+obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
 obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
+
 obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
 obj-$(CONFIG_MSM_PROC_COMM) += clock.o
-obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
+
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
 obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 09/11] msm: Makefile cleanup

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Clean up some of the conditionals in the Makefile in
preparation for adding build support for MSM8960.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/Makefile |   18 ++++++------------
 1 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 94195c1..3e15ff3 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,21 +1,15 @@
 obj-y += io.o idle.o timer.o
-ifndef CONFIG_ARCH_MSM8X60
-obj-y += acpuclock-arm11.o
-obj-y += dma.o
-endif
 
-ifdef CONFIG_MSM_VIC
-obj-y += irq-vic.o
-else
-ifndef CONFIG_ARCH_MSM8X60
-obj-y += irq.o
-endif
-endif
+obj-$(CONFIG_MSM_VIC) += irq-vic.o
 
+obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
+obj-$(CONFIG_ARCH_MSM7X30) += dma.o
+obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
 obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
+
 obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
 obj-$(CONFIG_MSM_PROC_COMM) += clock.o
-obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
+
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
 obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 10/11] msm: Support for the MSM8960 Simulator target

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Add the board file, Kconfig options, and Makefile options
needed to build for the MSM8960 Simulator target.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/Kconfig         |   16 ++++++++++
 arch/arm/mach-msm/Makefile        |    5 +++
 arch/arm/mach-msm/board-msm8960.c |   58 +++++++++++++++++++++++++++++++++++++
 3 files changed, 79 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/board-msm8960.c

diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 5d3d9ad..adca96c 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -48,6 +48,16 @@ config ARCH_MSM8X60
 	select IOMMU_API
 	select MSM_SCM if SMP
 
+config ARCH_MSM8960
+	bool "MSM8960"
+	select ARCH_MSM_SCORPIONMP
+	select MACH_MSM8960_SIM
+	select ARM_GIC
+	select CPU_V7
+	select MSM_V2_TLMM
+	select MSM_GPIOMUX
+	select MSM_SCM if SMP
+
 endchoice
 
 config MSM_SOC_REV_A
@@ -125,6 +135,12 @@ config MACH_MSM8X60_FFA
 	help
 	  Support for the Qualcomm MSM8x60 FFA eval board.
 
+config MACH_MSM8960_SIM
+	depends on ARCH_MSM8960
+	bool "MSM8960 Simulator"
+	help
+	  Support for the Qualcomm MSM8960 simulator.
+
 endmenu
 
 config IOMMU_PGTABLES_L2
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 3e15ff3..0229427 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
 obj-$(CONFIG_ARCH_MSM7X30) += dma.o
 obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
 obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
+obj-$(CONFIG_ARCH_MSM8960) += clock-dummy.o
 
 obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
 obj-$(CONFIG_MSM_PROC_COMM) += clock.o
@@ -23,12 +24,16 @@ obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
 obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
+obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o
 
 obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
 ifdef CONFIG_MSM_V2_TLMM
+ifndef CONFIG_ARCH_MSM8960
+# TODO: TLMM Mapping issues need to be resolved
 obj-y	+= gpio-v2.o
+endif
 else
 obj-y	+= gpio.o
 endif
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
new file mode 100644
index 0000000..90efd54
--- /dev/null
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -0,0 +1,58 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/board.h>
+#include <mach/msm_iomap.h>
+
+static void __init msm8960_map_io(void)
+{
+	msm_map_msm8960_io();
+}
+
+static void __init msm8960_init_irq(void)
+{
+	unsigned int i;
+	gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
+		 (void *)MSM_QGIC_CPU_BASE);
+
+	/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
+	writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
+
+	/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
+	 * as they are configured as level, which does not play nice with
+	 * handle_percpu_irq.
+	 */
+	for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
+		if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
+			set_irq_handler(i, handle_percpu_irq);
+	}
+}
+
+MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
+	.map_io = msm8960_map_io,
+	.init_irq = msm8960_init_irq,
+	.timer = &msm_timer,
+MACHINE_END
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 10/11] msm: Support for the MSM8960 Simulator target

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Add the board file, Kconfig options, and Makefile options
needed to build for the MSM8960 Simulator target.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/Kconfig         |   16 ++++++++++
 arch/arm/mach-msm/Makefile        |    5 +++
 arch/arm/mach-msm/board-msm8960.c |   58 +++++++++++++++++++++++++++++++++++++
 3 files changed, 79 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/board-msm8960.c

diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 5d3d9ad..adca96c 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -48,6 +48,16 @@ config ARCH_MSM8X60
 	select IOMMU_API
 	select MSM_SCM if SMP
 
+config ARCH_MSM8960
+	bool "MSM8960"
+	select ARCH_MSM_SCORPIONMP
+	select MACH_MSM8960_SIM
+	select ARM_GIC
+	select CPU_V7
+	select MSM_V2_TLMM
+	select MSM_GPIOMUX
+	select MSM_SCM if SMP
+
 endchoice
 
 config MSM_SOC_REV_A
@@ -125,6 +135,12 @@ config MACH_MSM8X60_FFA
 	help
 	  Support for the Qualcomm MSM8x60 FFA eval board.
 
+config MACH_MSM8960_SIM
+	depends on ARCH_MSM8960
+	bool "MSM8960 Simulator"
+	help
+	  Support for the Qualcomm MSM8960 simulator.
+
 endmenu
 
 config IOMMU_PGTABLES_L2
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 3e15ff3..0229427 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
 obj-$(CONFIG_ARCH_MSM7X30) += dma.o
 obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
 obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
+obj-$(CONFIG_ARCH_MSM8960) += clock-dummy.o
 
 obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
 obj-$(CONFIG_MSM_PROC_COMM) += clock.o
@@ -23,12 +24,16 @@ obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
 obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
+obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o
 
 obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
 ifdef CONFIG_MSM_V2_TLMM
+ifndef CONFIG_ARCH_MSM8960
+# TODO: TLMM Mapping issues need to be resolved
 obj-y	+= gpio-v2.o
+endif
 else
 obj-y	+= gpio.o
 endif
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
new file mode 100644
index 0000000..90efd54
--- /dev/null
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -0,0 +1,58 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/board.h>
+#include <mach/msm_iomap.h>
+
+static void __init msm8960_map_io(void)
+{
+	msm_map_msm8960_io();
+}
+
+static void __init msm8960_init_irq(void)
+{
+	unsigned int i;
+	gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
+		 (void *)MSM_QGIC_CPU_BASE);
+
+	/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
+	writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
+
+	/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
+	 * as they are configured as level, which does not play nice with
+	 * handle_percpu_irq.
+	 */
+	for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
+		if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
+			set_irq_handler(i, handle_percpu_irq);
+	}
+}
+
+MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
+	.map_io = msm8960_map_io,
+	.init_irq = msm8960_init_irq,
+	.timer = &msm_timer,
+MACHINE_END
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 11/11] msm: Support for the MSM8960 RUMI3 target

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Add the machine record, init code, and build support for
the MSM8960 RUMI3.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/Kconfig         |    8 +++++++-
 arch/arm/mach-msm/board-msm8960.c |   10 ++++++++++
 2 files changed, 17 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index adca96c..df9d74e 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -51,7 +51,7 @@ config ARCH_MSM8X60
 config ARCH_MSM8960
 	bool "MSM8960"
 	select ARCH_MSM_SCORPIONMP
-	select MACH_MSM8960_SIM
+	select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3)
 	select ARM_GIC
 	select CPU_V7
 	select MSM_V2_TLMM
@@ -141,6 +141,12 @@ config MACH_MSM8960_SIM
 	help
 	  Support for the Qualcomm MSM8960 simulator.
 
+config MACH_MSM8960_RUMI3
+	depends on ARCH_MSM8960
+	bool "MSM8960 RUMI3"
+	help
+	  Support for the Qualcomm MSM8960 RUMI3 emulator.
+
 endmenu
 
 config IOMMU_PGTABLES_L2
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 90efd54..2b09573 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -41,6 +41,9 @@ static void __init msm8960_init_irq(void)
 	/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
 	writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
 
+	if (machine_is_msm8960_rumi3())
+		writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
+
 	/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
 	 * as they are configured as level, which does not play nice with
 	 * handle_percpu_irq.
@@ -56,3 +59,10 @@ MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
 	.init_irq = msm8960_init_irq,
 	.timer = &msm_timer,
 MACHINE_END
+
+MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
+	.map_io = msm8960_map_io,
+	.init_irq = msm8960_init_irq,
+	.timer = &msm_timer,
+MACHINE_END
+
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 11/11] msm: Support for the MSM8960 RUMI3 target

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Add the machine record, init code, and build support for
the MSM8960 RUMI3.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/Kconfig         |    8 +++++++-
 arch/arm/mach-msm/board-msm8960.c |   10 ++++++++++
 2 files changed, 17 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index adca96c..df9d74e 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -51,7 +51,7 @@ config ARCH_MSM8X60
 config ARCH_MSM8960
 	bool "MSM8960"
 	select ARCH_MSM_SCORPIONMP
-	select MACH_MSM8960_SIM
+	select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3)
 	select ARM_GIC
 	select CPU_V7
 	select MSM_V2_TLMM
@@ -141,6 +141,12 @@ config MACH_MSM8960_SIM
 	help
 	  Support for the Qualcomm MSM8960 simulator.
 
+config MACH_MSM8960_RUMI3
+	depends on ARCH_MSM8960
+	bool "MSM8960 RUMI3"
+	help
+	  Support for the Qualcomm MSM8960 RUMI3 emulator.
+
 endmenu
 
 config IOMMU_PGTABLES_L2
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 90efd54..2b09573 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -41,6 +41,9 @@ static void __init msm8960_init_irq(void)
 	/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
 	writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
 
+	if (machine_is_msm8960_rumi3())
+		writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
+
 	/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
 	 * as they are configured as level, which does not play nice with
 	 * handle_percpu_irq.
@@ -56,3 +59,10 @@ MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
 	.init_irq = msm8960_init_irq,
 	.timer = &msm_timer,
 MACHINE_END
+
+MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
+	.map_io = msm8960_map_io,
+	.init_irq = msm8960_init_irq,
+	.timer = &msm_timer,
+MACHINE_END
+
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 00/11] msm: Add initial support for MSM8960

[David Brown]

Resending with CC's actually present in the header.

This series adds initial support for the MSM8960.  Unfortunately, the
naming of this device is misleading, and it is not a particular
instance of the current MSM8x60 devices, but a rather different chip.
The MSM8x60 arch supports the 8260 and 8660 devices.  I may make a
future patch to rename this arch to be one of these names.

Patch versions:
v2 - Remove ifdefs for io mappings for the new target.  More need to
     be cleaned up for all targets, but this doesn't add new ones.
     The irq table still contains an ifdef, which will be cleaned up
     in an upcoming patch.

[PATCH v2 00/11] msm: Add initial support for MSM8960

[David Brown]

Resending with CC's actually present in the header.

This series adds initial support for the MSM8960.  Unfortunately, the
naming of this device is misleading, and it is not a particular
instance of the current MSM8x60 devices, but a rather different chip.
The MSM8x60 arch supports the 8260 and 8660 devices.  I may make a
future patch to rename this arch to be one of these names.

Patch versions:
v2 - Remove ifdefs for io mappings for the new target.  More need to
     be cleaned up for all targets, but this doesn't add new ones.
     The irq table still contains an ifdef, which will be cleaned up
     in an upcoming patch.

--
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Re: [PATCH v2 07/11] msm: Add MSM 8960 cpu_is check

[Daniel Walker]

On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> diff --git a/arch/arm/mach-msm/include/mach/cpu.h
> b/arch/arm/mach-msm/include/mach/cpu.h
> index e1ba9db..a9481b0 100644
> --- a/arch/arm/mach-msm/include/mach/cpu.h
> +++ b/arch/arm/mach-msm/include/mach/cpu.h
> @@ -24,6 +24,7 @@
>  #define cpu_is_msm7x30()       0
>  #define cpu_is_qsd8x50()       0
>  #define cpu_is_msm8x60()       0
> +#define cpu_is_msm8960()       0

The naming is just perverted even more here..

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 07/11] msm: Add MSM 8960 cpu_is check

[Daniel Walker]

On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> diff --git a/arch/arm/mach-msm/include/mach/cpu.h
> b/arch/arm/mach-msm/include/mach/cpu.h
> index e1ba9db..a9481b0 100644
> --- a/arch/arm/mach-msm/include/mach/cpu.h
> +++ b/arch/arm/mach-msm/include/mach/cpu.h
> @@ -24,6 +24,7 @@
>  #define cpu_is_msm7x30()       0
>  #define cpu_is_qsd8x50()       0
>  #define cpu_is_msm8x60()       0
> +#define cpu_is_msm8960()       0

The naming is just perverted even more here..

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 04/11] msm: io: I/O register definitions for MSM8960

[Daniel Walker]

On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> +/*
> + * Copyright (C) 2007 Google, Inc.
> + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
> + * Author: Brian Swetland <swetland@google.com>

Brian didn't really write this did he?

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 04/11] msm: io: I/O register definitions for MSM8960

[Daniel Walker]

On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> +/*
> + * Copyright (C) 2007 Google, Inc.
> + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
> + * Author: Brian Swetland <swetland@google.com>

Brian didn't really write this did he?

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 07/11] msm: Add MSM 8960 cpu_is check

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>> diff --git a/arch/arm/mach-msm/include/mach/cpu.h
>> b/arch/arm/mach-msm/include/mach/cpu.h
>> index e1ba9db..a9481b0 100644
>> --- a/arch/arm/mach-msm/include/mach/cpu.h
>> +++ b/arch/arm/mach-msm/include/mach/cpu.h
>> @@ -24,6 +24,7 @@
>>  #define cpu_is_msm7x30()       0
>>  #define cpu_is_qsd8x50()       0
>>  #define cpu_is_msm8x60()       0
>> +#define cpu_is_msm8960()       0
>
> The naming is just perverted even more here..

What do you want me to call it?

  #define cpu_is_97d0c886-3768-4998-8925-16f36209d0d1()

It's the name of the chip.  We've already been through this.  The names
are unfortunate, but it is what the devices are called.

At some point, I may change the msm8x60 to something more specific, such
as msm8260, or msm8660, one of the devices that it represents.  But this
isn't correct, either.  There really isn't a good answer.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 07/11] msm: Add MSM 8960 cpu_is check

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>> diff --git a/arch/arm/mach-msm/include/mach/cpu.h
>> b/arch/arm/mach-msm/include/mach/cpu.h
>> index e1ba9db..a9481b0 100644
>> --- a/arch/arm/mach-msm/include/mach/cpu.h
>> +++ b/arch/arm/mach-msm/include/mach/cpu.h
>> @@ -24,6 +24,7 @@
>>  #define cpu_is_msm7x30()       0
>>  #define cpu_is_qsd8x50()       0
>>  #define cpu_is_msm8x60()       0
>> +#define cpu_is_msm8960()       0
>
> The naming is just perverted even more here..

What do you want me to call it?

  #define cpu_is_97d0c886-3768-4998-8925-16f36209d0d1()

It's the name of the chip.  We've already been through this.  The names
are unfortunate, but it is what the devices are called.

At some point, I may change the msm8x60 to something more specific, such
as msm8260, or msm8660, one of the devices that it represents.  But this
isn't correct, either.  There really isn't a good answer.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 04/11] msm: io: I/O register definitions for MSM8960

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>> +/*
>> + * Copyright (C) 2007 Google, Inc.
>> + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
>> + * Author: Brian Swetland <swetland@google.com>
>
> Brian didn't really write this did he?

He wrote the code it is based off of.  The author line could probably be
removed.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 04/11] msm: io: I/O register definitions for MSM8960

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>> +/*
>> + * Copyright (C) 2007 Google, Inc.
>> + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
>> + * Author: Brian Swetland <swetland@google.com>
>
> Brian didn't really write this did he?

He wrote the code it is based off of.  The author line could probably be
removed.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 07/11] msm: Add MSM 8960 cpu_is check

[Daniel Walker]

On Mon, 2011-01-24 at 13:30 -0800, David Brown wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
> 
> > On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> >> diff --git a/arch/arm/mach-msm/include/mach/cpu.h
> >> b/arch/arm/mach-msm/include/mach/cpu.h
> >> index e1ba9db..a9481b0 100644
> >> --- a/arch/arm/mach-msm/include/mach/cpu.h
> >> +++ b/arch/arm/mach-msm/include/mach/cpu.h
> >> @@ -24,6 +24,7 @@
> >>  #define cpu_is_msm7x30()       0
> >>  #define cpu_is_qsd8x50()       0
> >>  #define cpu_is_msm8x60()       0
> >> +#define cpu_is_msm8960()       0
> >
> > The naming is just perverted even more here..
> 
> What do you want me to call it?
> 
>   #define cpu_is_97d0c886-3768-4998-8925-16f36209d0d1()

I want you to call it msm8x60 ..

> It's the name of the chip.  We've already been through this.  The names
> are unfortunate, but it is what the devices are called.

I think you can re-org things to mask all this.. I've been suggesting is
that we look into that ..

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 07/11] msm: Add MSM 8960 cpu_is check

[Daniel Walker]

On Mon, 2011-01-24 at 13:30 -0800, David Brown wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
> 
> > On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> >> diff --git a/arch/arm/mach-msm/include/mach/cpu.h
> >> b/arch/arm/mach-msm/include/mach/cpu.h
> >> index e1ba9db..a9481b0 100644
> >> --- a/arch/arm/mach-msm/include/mach/cpu.h
> >> +++ b/arch/arm/mach-msm/include/mach/cpu.h
> >> @@ -24,6 +24,7 @@
> >>  #define cpu_is_msm7x30()       0
> >>  #define cpu_is_qsd8x50()       0
> >>  #define cpu_is_msm8x60()       0
> >> +#define cpu_is_msm8960()       0
> >
> > The naming is just perverted even more here..
> 
> What do you want me to call it?
> 
>   #define cpu_is_97d0c886-3768-4998-8925-16f36209d0d1()

I want you to call it msm8x60 ..

> It's the name of the chip.  We've already been through this.  The names
> are unfortunate, but it is what the devices are called.

I think you can re-org things to mask all this.. I've been suggesting is
that we look into that ..

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 04/11] msm: io: I/O register definitions for MSM8960

[Daniel Walker]

On Mon, 2011-01-24 at 13:31 -0800, David Brown wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
> 
> > On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> >> +/*
> >> + * Copyright (C) 2007 Google, Inc.
> >> + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
> >> + * Author: Brian Swetland <swetland@google.com>
> >
> > Brian didn't really write this did he?
> 
> He wrote the code it is based off of.  The author line could probably be
> removed.

I think it's kind of like a total re-write.. So I'd assume removing him
is acceptable, besides he likely doesn't want to get email asking
questions about this thing he's never seen.

Daniel


-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 04/11] msm: io: I/O register definitions for MSM8960

[Daniel Walker]

On Mon, 2011-01-24 at 13:31 -0800, David Brown wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
> 
> > On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> >> +/*
> >> + * Copyright (C) 2007 Google, Inc.
> >> + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
> >> + * Author: Brian Swetland <swetland@google.com>
> >
> > Brian didn't really write this did he?
> 
> He wrote the code it is based off of.  The author line could probably be
> removed.

I think it's kind of like a total re-write.. So I'd assume removing him
is acceptable, besides he likely doesn't want to get email asking
questions about this thing he's never seen.

Daniel


-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 07/11] msm: Add MSM 8960 cpu_is check

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

>> What do you want me to call it?
>> 
>>   #define cpu_is_97d0c886-3768-4998-8925-16f36209d0d1()
>
> I want you to call it msm8x60 ..

msm8960 is not a subset of msm8x60.  It's just a misleading name.  It's
a very different device, and needs it's own identifier.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 07/11] msm: Add MSM 8960 cpu_is check

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

>> What do you want me to call it?
>> 
>>   #define cpu_is_97d0c886-3768-4998-8925-16f36209d0d1()
>
> I want you to call it msm8x60 ..

msm8960 is not a subset of msm8x60.  It's just a misleading name.  It's
a very different device, and needs it's own identifier.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 07/11] msm: Add MSM 8960 cpu_is check

[Daniel Walker]

On Mon, 2011-01-24 at 14:13 -0800, David Brown wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
> 
> >> What do you want me to call it?
> >> 
> >>   #define cpu_is_97d0c886-3768-4998-8925-16f36209d0d1()
> >
> > I want you to call it msm8x60 ..
> 
> msm8960 is not a subset of msm8x60.  It's just a misleading name.  It's
> a very different device, and needs it's own identifier.

Can you site reason why it's different .. My impression is that it's not
as different as you think it is.

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 07/11] msm: Add MSM 8960 cpu_is check

[Daniel Walker]

On Mon, 2011-01-24 at 14:13 -0800, David Brown wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
> 
> >> What do you want me to call it?
> >> 
> >>   #define cpu_is_97d0c886-3768-4998-8925-16f36209d0d1()
> >
> > I want you to call it msm8x60 ..
> 
> msm8960 is not a subset of msm8x60.  It's just a misleading name.  It's
> a very different device, and needs it's own identifier.

Can you site reason why it's different .. My impression is that it's not
as different as you think it is.

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 02/11] msm: Generalize timer register mappings

[Daniel Walker]

On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> +       int global_offset = 0;
> +
> +       if (cpu_is_msm7x01()) {
> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
> +       } else if (cpu_is_msm7x30()) {
> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
> +       } else if (cpu_is_qsd8x50()) {
> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
> +       } else if (cpu_is_msm8x60()) {
> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
> +
> +               /* Use CPU0's timer as the global timer. */
> +               global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
> +       } else
> +               BUG(); 

Ifdef's here would be OK I think, your already using the "runtime"
checks ..

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 02/11] msm: Generalize timer register mappings

[Daniel Walker]

On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> +       int global_offset = 0;
> +
> +       if (cpu_is_msm7x01()) {
> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
> +       } else if (cpu_is_msm7x30()) {
> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
> +       } else if (cpu_is_qsd8x50()) {
> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
> +       } else if (cpu_is_msm8x60()) {
> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
> +
> +               /* Use CPU0's timer as the global timer. */
> +               global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
> +       } else
> +               BUG(); 

Ifdef's here would be OK I think, your already using the "runtime"
checks ..

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 02/11] msm: Generalize timer register mappings

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>> +       int global_offset = 0;
>> +
>> +       if (cpu_is_msm7x01()) {
>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
>> +       } else if (cpu_is_msm7x30()) {
>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
>> +       } else if (cpu_is_qsd8x50()) {
>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
>> +       } else if (cpu_is_msm8x60()) {
>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
>> +
>> +               /* Use CPU0's timer as the global timer. */
>> +               global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
>> +       } else
>> +               BUG(); 
>
> Ifdef's here would be OK I think, your already using the "runtime"
> checks ..

The point of the change is to get rid of the ifdefs so that we can
dynamically detect which target we are on.  Yes, there are other places
where it doesn't work, but we'll get there gradually.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 02/11] msm: Generalize timer register mappings

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>> +       int global_offset = 0;
>> +
>> +       if (cpu_is_msm7x01()) {
>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
>> +       } else if (cpu_is_msm7x30()) {
>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
>> +       } else if (cpu_is_qsd8x50()) {
>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
>> +       } else if (cpu_is_msm8x60()) {
>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
>> +
>> +               /* Use CPU0's timer as the global timer. */
>> +               global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
>> +       } else
>> +               BUG(); 
>
> Ifdef's here would be OK I think, your already using the "runtime"
> checks ..

The point of the change is to get rid of the ifdefs so that we can
dynamically detect which target we are on.  Yes, there are other places
where it doesn't work, but we'll get there gradually.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 06/11] msm: irqs-8960: Interrupt map for MSM8960

[Daniel Walker]

On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> +#define INT_VGIC                               (GIC_PPI_START + 0)
> +#define INT_DEBUG_TIMER_EXP                    (GIC_PPI_START + 1)
> +#define INT_GP_TIMER_EXP                       (GIC_PPI_START + 2)
> +#define INT_GP_TIMER2_EXP                      (GIC_PPI_START + 3)
> +#define WDT0_ACCSCSSNBARK_INT                  (GIC_PPI_START + 4)
> +#define WDT1_ACCSCSSNBARK_INT                  (GIC_PPI_START + 5)
> +#define AVS_SVICINT                            (GIC_PPI_START + 6)
> +#define AVS_SVICINTSWDONE                      (GIC_PPI_START + 7)
> +#define CPU_DBGCPUXCOMMRXFULL                  (GIC_PPI_START + 8)
> +#define CPU_DBGCPUXCOMMTXEMPTY                 (GIC_PPI_START + 9)
> +#define CPU_SICCPUXPERFMONIRPTREQ              (GIC_PPI_START + 10)
> +#define SC_AVSCPUXDOWN                         (GIC_PPI_START + 11)
> +#define SC_AVSCPUXUP                           (GIC_PPI_START + 12)
> +#define SC_SICCPUXACGIRPTREQ                   (GIC_PPI_START + 13)
> +#define SC_SICCPUXEXTFAULTIRPTREQ              (GIC_PPI_START + 14)
> +/* PPI 15 is unused */ 

How are you handling this at runtime?

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 06/11] msm: irqs-8960: Interrupt map for MSM8960

[Daniel Walker]

On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> +#define INT_VGIC                               (GIC_PPI_START + 0)
> +#define INT_DEBUG_TIMER_EXP                    (GIC_PPI_START + 1)
> +#define INT_GP_TIMER_EXP                       (GIC_PPI_START + 2)
> +#define INT_GP_TIMER2_EXP                      (GIC_PPI_START + 3)
> +#define WDT0_ACCSCSSNBARK_INT                  (GIC_PPI_START + 4)
> +#define WDT1_ACCSCSSNBARK_INT                  (GIC_PPI_START + 5)
> +#define AVS_SVICINT                            (GIC_PPI_START + 6)
> +#define AVS_SVICINTSWDONE                      (GIC_PPI_START + 7)
> +#define CPU_DBGCPUXCOMMRXFULL                  (GIC_PPI_START + 8)
> +#define CPU_DBGCPUXCOMMTXEMPTY                 (GIC_PPI_START + 9)
> +#define CPU_SICCPUXPERFMONIRPTREQ              (GIC_PPI_START + 10)
> +#define SC_AVSCPUXDOWN                         (GIC_PPI_START + 11)
> +#define SC_AVSCPUXUP                           (GIC_PPI_START + 12)
> +#define SC_SICCPUXACGIRPTREQ                   (GIC_PPI_START + 13)
> +#define SC_SICCPUXEXTFAULTIRPTREQ              (GIC_PPI_START + 14)
> +/* PPI 15 is unused */ 

How are you handling this at runtime?

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 06/11] msm: irqs-8960: Interrupt map for MSM8960

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>> +#define SC_AVSCPUXUP                           (GIC_PPI_START + 12)
>> +#define SC_SICCPUXACGIRPTREQ                   (GIC_PPI_START + 13)
>> +#define SC_SICCPUXEXTFAULTIRPTREQ              (GIC_PPI_START + 14)
>> +/* PPI 15 is unused */ 
>
> How are you handling this at runtime?

We're not yet.  That's why it is marked as a TODO.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 06/11] msm: irqs-8960: Interrupt map for MSM8960

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>> +#define SC_AVSCPUXUP                           (GIC_PPI_START + 12)
>> +#define SC_SICCPUXACGIRPTREQ                   (GIC_PPI_START + 13)
>> +#define SC_SICCPUXEXTFAULTIRPTREQ              (GIC_PPI_START + 14)
>> +/* PPI 15 is unused */ 
>
> How are you handling this at runtime?

We're not yet.  That's why it is marked as a TODO.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 02/11] msm: Generalize timer register mappings

[Daniel Walker]

On Mon, 2011-01-24 at 14:44 -0800, David Brown wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
> 
> > On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> >> +       int global_offset = 0;
> >> +
> >> +       if (cpu_is_msm7x01()) {
> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
> >> +       } else if (cpu_is_msm7x30()) {
> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
> >> +       } else if (cpu_is_qsd8x50()) {
> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
> >> +       } else if (cpu_is_msm8x60()) {
> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
> >> +
> >> +               /* Use CPU0's timer as the global timer. */
> >> +               global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
> >> +       } else
> >> +               BUG(); 
> >
> > Ifdef's here would be OK I think, your already using the "runtime"
> > checks ..
> 
> The point of the change is to get rid of the ifdefs so that we can
> dynamically detect which target we are on.  Yes, there are other places
> where it doesn't work, but we'll get there gradually.

I'm not suggesting you do something you can't do right now ..

For instance you could make,

#define MSM_MSM7XXX_DGT_BASE          (MSM_TMR_BASE + 0x10)

and use that instead of what you have above.

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 02/11] msm: Generalize timer register mappings

[Daniel Walker]

On Mon, 2011-01-24 at 14:44 -0800, David Brown wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
> 
> > On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> >> +       int global_offset = 0;
> >> +
> >> +       if (cpu_is_msm7x01()) {
> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
> >> +       } else if (cpu_is_msm7x30()) {
> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
> >> +       } else if (cpu_is_qsd8x50()) {
> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
> >> +       } else if (cpu_is_msm8x60()) {
> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
> >> +
> >> +               /* Use CPU0's timer as the global timer. */
> >> +               global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
> >> +       } else
> >> +               BUG(); 
> >
> > Ifdef's here would be OK I think, your already using the "runtime"
> > checks ..
> 
> The point of the change is to get rid of the ifdefs so that we can
> dynamically detect which target we are on.  Yes, there are other places
> where it doesn't work, but we'll get there gradually.

I'm not suggesting you do something you can't do right now ..

For instance you could make,

#define MSM_MSM7XXX_DGT_BASE          (MSM_TMR_BASE + 0x10)

and use that instead of what you have above.

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 02/11] msm: Generalize timer register mappings

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

> On Mon, 2011-01-24 at 14:44 -0800, David Brown wrote:
>> On Mon, Jan 24 2011, Daniel Walker wrote:
>> 
>> > On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>> >> +       int global_offset = 0;
>> >> +
>> >> +       if (cpu_is_msm7x01()) {
>> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
>> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
>> >> +       } else if (cpu_is_msm7x30()) {
>> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
>> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
>> >> +       } else if (cpu_is_qsd8x50()) {
>> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
>> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
>> >> +       } else if (cpu_is_msm8x60()) {
>> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
>> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
>> >> +
>> >> +               /* Use CPU0's timer as the global timer. */
>> >> +               global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
>> >> +       } else
>> >> +               BUG(); 
>> >
>> > Ifdef's here would be OK I think, your already using the "runtime"
>> > checks ..
>> 
>> The point of the change is to get rid of the ifdefs so that we can
>> dynamically detect which target we are on.  Yes, there are other places
>> where it doesn't work, but we'll get there gradually.
>
> I'm not suggesting you do something you can't do right now ..
>
> For instance you could make,
>
> #define MSM_MSM7XXX_DGT_BASE          (MSM_TMR_BASE + 0x10)
>
> and use that instead of what you have above.

I did it this way intentionally.

I don't see how adding an extra level of indirection to the name helps
make it any clearer.  The register offsets are defined in only one
place, right in this block of code.  It is obvious which target and
which register is which.  Having an extra name defined somewhere else
just gives me another symbol I have to follow when I'm trying to read
the code later.

Avoiding magic numbers is fine in the code, when it actually helps.
Here, it doesn't do anything other than add a name that only gets used
once in a context that already describes what it is.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 02/11] msm: Generalize timer register mappings

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

> On Mon, 2011-01-24 at 14:44 -0800, David Brown wrote:
>> On Mon, Jan 24 2011, Daniel Walker wrote:
>> 
>> > On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>> >> +       int global_offset = 0;
>> >> +
>> >> +       if (cpu_is_msm7x01()) {
>> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
>> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
>> >> +       } else if (cpu_is_msm7x30()) {
>> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
>> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
>> >> +       } else if (cpu_is_qsd8x50()) {
>> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
>> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
>> >> +       } else if (cpu_is_msm8x60()) {
>> >> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
>> >> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
>> >> +
>> >> +               /* Use CPU0's timer as the global timer. */
>> >> +               global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
>> >> +       } else
>> >> +               BUG(); 
>> >
>> > Ifdef's here would be OK I think, your already using the "runtime"
>> > checks ..
>> 
>> The point of the change is to get rid of the ifdefs so that we can
>> dynamically detect which target we are on.  Yes, there are other places
>> where it doesn't work, but we'll get there gradually.
>
> I'm not suggesting you do something you can't do right now ..
>
> For instance you could make,
>
> #define MSM_MSM7XXX_DGT_BASE          (MSM_TMR_BASE + 0x10)
>
> and use that instead of what you have above.

I did it this way intentionally.

I don't see how adding an extra level of indirection to the name helps
make it any clearer.  The register offsets are defined in only one
place, right in this block of code.  It is obvious which target and
which register is which.  Having an extra name defined somewhere else
just gives me another symbol I have to follow when I'm trying to read
the code later.

Avoiding magic numbers is fine in the code, when it actually helps.
Here, it doesn't do anything other than add a name that only gets used
once in a context that already describes what it is.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 11/11] msm: Support for the MSM8960 RUMI3 target

[Russell King - ARM Linux]

On Wed, Jan 19, 2011 at 12:25:47PM -0800, David Brown wrote:
> --- a/arch/arm/mach-msm/board-msm8960.c
> +++ b/arch/arm/mach-msm/board-msm8960.c
> @@ -41,6 +41,9 @@ static void __init msm8960_init_irq(void)
>  	/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
>  	writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
>  
> +	if (machine_is_msm8960_rumi3())
> +		writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
> +

We really need to sort out the GIC initialization so that this kind of
stuff isn't scattered throughout platform files.

In fact, I thought we had already sorted out enabling the SGI interrupts
in the common gic code - it happens when you call gic_cpu_init().  So
I don't think the above is required.

As far as the edge triggering PPIs, that also needs sorting properly.

[PATCH v2 11/11] msm: Support for the MSM8960 RUMI3 target

[Russell King - ARM Linux]

On Wed, Jan 19, 2011 at 12:25:47PM -0800, David Brown wrote:
> --- a/arch/arm/mach-msm/board-msm8960.c
> +++ b/arch/arm/mach-msm/board-msm8960.c
> @@ -41,6 +41,9 @@ static void __init msm8960_init_irq(void)
>  	/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
>  	writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
>  
> +	if (machine_is_msm8960_rumi3())
> +		writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
> +

We really need to sort out the GIC initialization so that this kind of
stuff isn't scattered throughout platform files.

In fact, I thought we had already sorted out enabling the SGI interrupts
in the common gic code - it happens when you call gic_cpu_init().  So
I don't think the above is required.

As far as the edge triggering PPIs, that also needs sorting properly.

Re: [PATCH v2 05/11] msm: Physical offset for MSM8960

[Russell King - ARM Linux]

On Wed, Jan 19, 2011 at 12:25:41PM -0800, David Brown wrote:
> From: Stepan Moskovchenko <stepanm@codeaurora.org>
> 
> Add the physical memory offset value for the Qualcomm
> MSM8960 chip.
> 
> Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
> Signed-off-by: David Brown <davidb@codeaurora.org>
> ---
>  arch/arm/mach-msm/include/mach/memory.h |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
> index 070e17d..014bbd3 100644
> --- a/arch/arm/mach-msm/include/mach/memory.h
> +++ b/arch/arm/mach-msm/include/mach/memory.h
> @@ -25,6 +25,8 @@
>  #define PHYS_OFFSET		UL(0x00200000)
>  #elif defined(CONFIG_ARCH_MSM8X60)
>  #define PHYS_OFFSET		UL(0x40200000)
> +#elif defined(CONFIG_ARCH_MSM8960)
> +#define PHYS_OFFSET		UL(0x40200000)

Note that this will all change during the next merge window to
PLAT_PHYS_OFFSET.

[PATCH v2 05/11] msm: Physical offset for MSM8960

[Russell King - ARM Linux]

On Wed, Jan 19, 2011 at 12:25:41PM -0800, David Brown wrote:
> From: Stepan Moskovchenko <stepanm@codeaurora.org>
> 
> Add the physical memory offset value for the Qualcomm
> MSM8960 chip.
> 
> Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
> Signed-off-by: David Brown <davidb@codeaurora.org>
> ---
>  arch/arm/mach-msm/include/mach/memory.h |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
> index 070e17d..014bbd3 100644
> --- a/arch/arm/mach-msm/include/mach/memory.h
> +++ b/arch/arm/mach-msm/include/mach/memory.h
> @@ -25,6 +25,8 @@
>  #define PHYS_OFFSET		UL(0x00200000)
>  #elif defined(CONFIG_ARCH_MSM8X60)
>  #define PHYS_OFFSET		UL(0x40200000)
> +#elif defined(CONFIG_ARCH_MSM8960)
> +#define PHYS_OFFSET		UL(0x40200000)

Note that this will all change during the next merge window to
PLAT_PHYS_OFFSET.

Re: [PATCH v2 01/11] msm: Add CPU queries

[Daniel Walker]

On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> +#define cpu_is_msm7x01()       0
> +#define cpu_is_msm7x30()       0
> +#define cpu_is_qsd8x50()       0
> +#define cpu_is_msm8x60()       0

Now that I look at this again, why not drop the "x" all together ?

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 01/11] msm: Add CPU queries

[Daniel Walker]

On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> +#define cpu_is_msm7x01()       0
> +#define cpu_is_msm7x30()       0
> +#define cpu_is_qsd8x50()       0
> +#define cpu_is_msm8x60()       0

Now that I look at this again, why not drop the "x" all together ?

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 01/11] msm: Add CPU queries

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>> +#define cpu_is_msm7x01()       0
>> +#define cpu_is_msm7x30()       0
>> +#define cpu_is_qsd8x50()       0
>> +#define cpu_is_msm8x60()       0
>
> Now that I look at this again, why not drop the "x" all together ?

That might be better for the 8x60.  The complexity is that most of the
MSM chips have some variants, where the CPU running Linux isn't changed,
but the modem CPU is different (think CDMA/UMTS).  Until 8960, that was
distinguished by the second letter.

Either way doesn't quite match reality, unfortunately.  There are
devices using a MSM7201 and others using a MSM7601.  As far as Linux is
concerned, there isn't any difference between them.  If someone wanted
to try and identify the device they have with the code, it could be
confusing for either name chosen.

I was planning on turning msm8x60 into msm8660, since that seems to be
the most common one.  Perhaps the decoder ring should be put into the
help text for the options so people can at least figure out which is
which.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 01/11] msm: Add CPU queries

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>> +#define cpu_is_msm7x01()       0
>> +#define cpu_is_msm7x30()       0
>> +#define cpu_is_qsd8x50()       0
>> +#define cpu_is_msm8x60()       0
>
> Now that I look at this again, why not drop the "x" all together ?

That might be better for the 8x60.  The complexity is that most of the
MSM chips have some variants, where the CPU running Linux isn't changed,
but the modem CPU is different (think CDMA/UMTS).  Until 8960, that was
distinguished by the second letter.

Either way doesn't quite match reality, unfortunately.  There are
devices using a MSM7201 and others using a MSM7601.  As far as Linux is
concerned, there isn't any difference between them.  If someone wanted
to try and identify the device they have with the code, it could be
confusing for either name chosen.

I was planning on turning msm8x60 into msm8660, since that seems to be
the most common one.  Perhaps the decoder ring should be put into the
help text for the options so people can at least figure out which is
which.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 01/11] msm: Add CPU queries

[Daniel Walker]

On Mon, 2011-01-24 at 16:20 -0800, David Brown wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
> 
> > On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> >> +#define cpu_is_msm7x01()       0
> >> +#define cpu_is_msm7x30()       0
> >> +#define cpu_is_qsd8x50()       0
> >> +#define cpu_is_msm8x60()       0
> >
> > Now that I look at this again, why not drop the "x" all together ?
> 
> That might be better for the 8x60.  The complexity is that most of the
> MSM chips have some variants, where the CPU running Linux isn't changed,
> but the modem CPU is different (think CDMA/UMTS).  Until 8960, that was
> distinguished by the second letter.
> 
> Either way doesn't quite match reality, unfortunately.  There are
> devices using a MSM7201 and others using a MSM7601.  As far as Linux is
> concerned, there isn't any difference between them.  If someone wanted
> to try and identify the device they have with the code, it could be
> confusing for either name chosen.
> 
> I was planning on turning msm8x60 into msm8660, since that seems to be
> the most common one.  Perhaps the decoder ring should be put into the
> help text for the options so people can at least figure out which is
> which.

Are there any of those which do , right now, have Linux support for more
than one variant ?

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 01/11] msm: Add CPU queries

[Daniel Walker]

On Mon, 2011-01-24 at 16:20 -0800, David Brown wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
> 
> > On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> >> +#define cpu_is_msm7x01()       0
> >> +#define cpu_is_msm7x30()       0
> >> +#define cpu_is_qsd8x50()       0
> >> +#define cpu_is_msm8x60()       0
> >
> > Now that I look at this again, why not drop the "x" all together ?
> 
> That might be better for the 8x60.  The complexity is that most of the
> MSM chips have some variants, where the CPU running Linux isn't changed,
> but the modem CPU is different (think CDMA/UMTS).  Until 8960, that was
> distinguished by the second letter.
> 
> Either way doesn't quite match reality, unfortunately.  There are
> devices using a MSM7201 and others using a MSM7601.  As far as Linux is
> concerned, there isn't any difference between them.  If someone wanted
> to try and identify the device they have with the code, it could be
> confusing for either name chosen.
> 
> I was planning on turning msm8x60 into msm8660, since that seems to be
> the most common one.  Perhaps the decoder ring should be put into the
> help text for the options so people can at least figure out which is
> which.

Are there any of those which do , right now, have Linux support for more
than one variant ?

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 01/11] msm: Add CPU queries

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

> On Mon, 2011-01-24 at 16:20 -0800, David Brown wrote:
>> On Mon, Jan 24 2011, Daniel Walker wrote:
>> 
>> > On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>> >> +#define cpu_is_msm7x01()       0
>> >> +#define cpu_is_msm7x30()       0
>> >> +#define cpu_is_qsd8x50()       0
>> >> +#define cpu_is_msm8x60()       0
>> >
>> > Now that I look at this again, why not drop the "x" all together ?
>> 
>> That might be better for the 8x60.  The complexity is that most of the
>> MSM chips have some variants, where the CPU running Linux isn't changed,
>> but the modem CPU is different (think CDMA/UMTS).  Until 8960, that was
>> distinguished by the second letter.
>> 
>> Either way doesn't quite match reality, unfortunately.  There are
>> devices using a MSM7201 and others using a MSM7601.  As far as Linux is
>> concerned, there isn't any difference between them.  If someone wanted
>> to try and identify the device they have with the code, it could be
>> confusing for either name chosen.
>> 
>> I was planning on turning msm8x60 into msm8660, since that seems to be
>> the most common one.  Perhaps the decoder ring should be put into the
>> help text for the options so people can at least figure out which is
>> which.
>
> Are there any of those which do , right now, have Linux support for more
> than one variant ?

All of them, in fact.

MSM7201 and MSM7601 are identical as far as Linux is concerned.  Same
goes for MSM8250 and MSM8650.  Our dev boards are a somewhat random mix
of the two, and it doesn't matter which one you use.

MSM8960 is a completely different chip, it just shares a similar name,
to other chips.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 01/11] msm: Add CPU queries

[David Brown]

On Mon, Jan 24 2011, Daniel Walker wrote:

> On Mon, 2011-01-24 at 16:20 -0800, David Brown wrote:
>> On Mon, Jan 24 2011, Daniel Walker wrote:
>> 
>> > On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>> >> +#define cpu_is_msm7x01()       0
>> >> +#define cpu_is_msm7x30()       0
>> >> +#define cpu_is_qsd8x50()       0
>> >> +#define cpu_is_msm8x60()       0
>> >
>> > Now that I look at this again, why not drop the "x" all together ?
>> 
>> That might be better for the 8x60.  The complexity is that most of the
>> MSM chips have some variants, where the CPU running Linux isn't changed,
>> but the modem CPU is different (think CDMA/UMTS).  Until 8960, that was
>> distinguished by the second letter.
>> 
>> Either way doesn't quite match reality, unfortunately.  There are
>> devices using a MSM7201 and others using a MSM7601.  As far as Linux is
>> concerned, there isn't any difference between them.  If someone wanted
>> to try and identify the device they have with the code, it could be
>> confusing for either name chosen.
>> 
>> I was planning on turning msm8x60 into msm8660, since that seems to be
>> the most common one.  Perhaps the decoder ring should be put into the
>> help text for the options so people can at least figure out which is
>> which.
>
> Are there any of those which do , right now, have Linux support for more
> than one variant ?

All of them, in fact.

MSM7201 and MSM7601 are identical as far as Linux is concerned.  Same
goes for MSM8250 and MSM8650.  Our dev boards are a somewhat random mix
of the two, and it doesn't matter which one you use.

MSM8960 is a completely different chip, it just shares a similar name,
to other chips.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 01/11] msm: Add CPU queries

[Daniel Walker]

On Mon, 2011-01-24 at 16:57 -0800, David Brown wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
> 
> > On Mon, 2011-01-24 at 16:20 -0800, David Brown wrote:
> >> On Mon, Jan 24 2011, Daniel Walker wrote:
> >> 
> >> > On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> >> >> +#define cpu_is_msm7x01()       0
> >> >> +#define cpu_is_msm7x30()       0
> >> >> +#define cpu_is_qsd8x50()       0
> >> >> +#define cpu_is_msm8x60()       0
> >> >
> >> > Now that I look at this again, why not drop the "x" all together ?
> >> 
> >> That might be better for the 8x60.  The complexity is that most of the
> >> MSM chips have some variants, where the CPU running Linux isn't changed,
> >> but the modem CPU is different (think CDMA/UMTS).  Until 8960, that was
> >> distinguished by the second letter.
> >> 
> >> Either way doesn't quite match reality, unfortunately.  There are
> >> devices using a MSM7201 and others using a MSM7601.  As far as Linux is
> >> concerned, there isn't any difference between them.  If someone wanted
> >> to try and identify the device they have with the code, it could be
> >> confusing for either name chosen.
> >> 
> >> I was planning on turning msm8x60 into msm8660, since that seems to be
> >> the most common one.  Perhaps the decoder ring should be put into the
> >> help text for the options so people can at least figure out which is
> >> which.
> >
> > Are there any of those which do , right now, have Linux support for more
> > than one variant ?
> 
> All of them, in fact.
> 
> MSM7201 and MSM7601 are identical as far as Linux is concerned.  Same
> goes for MSM8250 and MSM8650.  Our dev boards are a somewhat random mix
> of the two, and it doesn't matter which one you use.
> 
> MSM8960 is a completely different chip, it just shares a similar name,
> to other chips.

If you break it down without the "x" then you can recreate the "x"
variant with the actual numerical identifier .. For 8660/8960 you just
would do as much of a unification as with the others.. You could still
use 8x60 to identify those two, you just wouldn't use it as often.

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 01/11] msm: Add CPU queries

[Daniel Walker]

On Mon, 2011-01-24 at 16:57 -0800, David Brown wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
> 
> > On Mon, 2011-01-24 at 16:20 -0800, David Brown wrote:
> >> On Mon, Jan 24 2011, Daniel Walker wrote:
> >> 
> >> > On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> >> >> +#define cpu_is_msm7x01()       0
> >> >> +#define cpu_is_msm7x30()       0
> >> >> +#define cpu_is_qsd8x50()       0
> >> >> +#define cpu_is_msm8x60()       0
> >> >
> >> > Now that I look at this again, why not drop the "x" all together ?
> >> 
> >> That might be better for the 8x60.  The complexity is that most of the
> >> MSM chips have some variants, where the CPU running Linux isn't changed,
> >> but the modem CPU is different (think CDMA/UMTS).  Until 8960, that was
> >> distinguished by the second letter.
> >> 
> >> Either way doesn't quite match reality, unfortunately.  There are
> >> devices using a MSM7201 and others using a MSM7601.  As far as Linux is
> >> concerned, there isn't any difference between them.  If someone wanted
> >> to try and identify the device they have with the code, it could be
> >> confusing for either name chosen.
> >> 
> >> I was planning on turning msm8x60 into msm8660, since that seems to be
> >> the most common one.  Perhaps the decoder ring should be put into the
> >> help text for the options so people can at least figure out which is
> >> which.
> >
> > Are there any of those which do , right now, have Linux support for more
> > than one variant ?
> 
> All of them, in fact.
> 
> MSM7201 and MSM7601 are identical as far as Linux is concerned.  Same
> goes for MSM8250 and MSM8650.  Our dev boards are a somewhat random mix
> of the two, and it doesn't matter which one you use.
> 
> MSM8960 is a completely different chip, it just shares a similar name,
> to other chips.

If you break it down without the "x" then you can recreate the "x"
variant with the actual numerical identifier .. For 8660/8960 you just
would do as much of a unification as with the others.. You could still
use 8x60 to identify those two, you just wouldn't use it as often.

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 02/11] msm: Generalize timer register mappings

[Carl Vanderlip]

On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> -#define MSM_GPT_PHYS          MSM_CSR_PHYS
> -#define MSM_GPT_BASE          MSM_CSR_BASE
> -#define MSM_GPT_SIZE          SZ_4K
...
> +#define MSM_CHIP_DEVICE(name, chip) {			      \
>  		.virtual = (unsigned long) MSM_##name##_BASE, \
> -		.pfn = __phys_to_pfn(MSM_##name##_PHYS), \
> -		.length = MSM_##name##_SIZE, \
> +		.pfn = __phys_to_pfn(chip##_##name##_PHYS), \
> +		.length = chip##_##name##_SIZE, \
>  		.type = MT_DEVICE_NONSHARED, \
>  	 }
>  
> +#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
> +
>  #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
>  	|| defined(CONFIG_ARCH_MSM7X25)
>  static struct map_desc msm_io_desc[] __initdata = {
>  	MSM_DEVICE(VIC),
> -	MSM_DEVICE(CSR),
> +	MSM_CHIP_DEVICE(CSR, MSM7X00),
>  	MSM_DEVICE(GPT),
>  	MSM_DEVICE(DMOV),
>  	MSM_DEVICE(GPIO1),

MSM_DEVICE(GPT) still references MSM_GPT_PHYS, MSM_GPT_SIZE and
MSM_GPT_BASE on the 7x00a though they are being removed.

---
Sent by an consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum.

[PATCH v2 02/11] msm: Generalize timer register mappings

[Carl Vanderlip]

On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
> -#define MSM_GPT_PHYS          MSM_CSR_PHYS
> -#define MSM_GPT_BASE          MSM_CSR_BASE
> -#define MSM_GPT_SIZE          SZ_4K
...
> +#define MSM_CHIP_DEVICE(name, chip) {			      \
>  		.virtual = (unsigned long) MSM_##name##_BASE, \
> -		.pfn = __phys_to_pfn(MSM_##name##_PHYS), \
> -		.length = MSM_##name##_SIZE, \
> +		.pfn = __phys_to_pfn(chip##_##name##_PHYS), \
> +		.length = chip##_##name##_SIZE, \
>  		.type = MT_DEVICE_NONSHARED, \
>  	 }
>  
> +#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
> +
>  #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
>  	|| defined(CONFIG_ARCH_MSM7X25)
>  static struct map_desc msm_io_desc[] __initdata = {
>  	MSM_DEVICE(VIC),
> -	MSM_DEVICE(CSR),
> +	MSM_CHIP_DEVICE(CSR, MSM7X00),
>  	MSM_DEVICE(GPT),
>  	MSM_DEVICE(DMOV),
>  	MSM_DEVICE(GPIO1),

MSM_DEVICE(GPT) still references MSM_GPT_PHYS, MSM_GPT_SIZE and
MSM_GPT_BASE on the 7x00a though they are being removed.

---
Sent by an consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum.

Re: [PATCH v2 01/11] msm: Add CPU queries

[David Brown]

On Tue, Jan 25 2011, Daniel Walker wrote:

> On Mon, 2011-01-24 at 16:57 -0800, David Brown wrote:
>> MSM7201 and MSM7601 are identical as far as Linux is concerned.  Same
>> goes for MSM8250 and MSM8650.  Our dev boards are a somewhat random mix
>> of the two, and it doesn't matter which one you use.
>> 
>> MSM8960 is a completely different chip, it just shares a similar name,
>> to other chips.
>
> If you break it down without the "x" then you can recreate the "x"
> variant with the actual numerical identifier .. For 8660/8960 you just
> would do as much of a unification as with the others.. You could still
> use 8x60 to identify those two, you just wouldn't use it as often.

There isn't any unification to do here.  There are two issues.  We make
some chips in groups where we have _identical_ silicon on the Linux
side, but happen to have different numbers.  That's what the X is
about.  There are other cases where we have completely different silicon
that happen to have similar numbers.

The whole point of the cpu_is tests is to tell us exactly which chip we
are on.  If there is _anything_ different between two chips, that query
needs to be different.  If there is any kind of unification, it can be
done at a higher level.  Otherwise, you have no way of making the
distinction that needs to be made.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 01/11] msm: Add CPU queries

[David Brown]

On Tue, Jan 25 2011, Daniel Walker wrote:

> On Mon, 2011-01-24 at 16:57 -0800, David Brown wrote:
>> MSM7201 and MSM7601 are identical as far as Linux is concerned.  Same
>> goes for MSM8250 and MSM8650.  Our dev boards are a somewhat random mix
>> of the two, and it doesn't matter which one you use.
>> 
>> MSM8960 is a completely different chip, it just shares a similar name,
>> to other chips.
>
> If you break it down without the "x" then you can recreate the "x"
> variant with the actual numerical identifier .. For 8660/8960 you just
> would do as much of a unification as with the others.. You could still
> use 8x60 to identify those two, you just wouldn't use it as often.

There isn't any unification to do here.  There are two issues.  We make
some chips in groups where we have _identical_ silicon on the Linux
side, but happen to have different numbers.  That's what the X is
about.  There are other cases where we have completely different silicon
that happen to have similar numbers.

The whole point of the cpu_is tests is to tell us exactly which chip we
are on.  If there is _anything_ different between two chips, that query
needs to be different.  If there is any kind of unification, it can be
done at a higher level.  Otherwise, you have no way of making the
distinction that needs to be made.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 02/11] msm: Generalize timer register mappings

[David Brown]

On Tue, Jan 25 2011, Carl Vanderlip wrote:

>>  #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
>>  	|| defined(CONFIG_ARCH_MSM7X25)
>>  static struct map_desc msm_io_desc[] __initdata = {
>>  	MSM_DEVICE(VIC),
>> -	MSM_DEVICE(CSR),
>> +	MSM_CHIP_DEVICE(CSR, MSM7X00),
>>  	MSM_DEVICE(GPT),
>>  	MSM_DEVICE(DMOV),
>>  	MSM_DEVICE(GPIO1),
>
> MSM_DEVICE(GPT) still references MSM_GPT_PHYS, MSM_GPT_SIZE and
> MSM_GPT_BASE on the 7x00a though they are being removed.

Shouldn't be too hard to fix.  I'll look at it later today.  It mostly
points out that I haven't been building against 7x00A.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 02/11] msm: Generalize timer register mappings

[David Brown]

On Tue, Jan 25 2011, Carl Vanderlip wrote:

>>  #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
>>  	|| defined(CONFIG_ARCH_MSM7X25)
>>  static struct map_desc msm_io_desc[] __initdata = {
>>  	MSM_DEVICE(VIC),
>> -	MSM_DEVICE(CSR),
>> +	MSM_CHIP_DEVICE(CSR, MSM7X00),
>>  	MSM_DEVICE(GPT),
>>  	MSM_DEVICE(DMOV),
>>  	MSM_DEVICE(GPIO1),
>
> MSM_DEVICE(GPT) still references MSM_GPT_PHYS, MSM_GPT_SIZE and
> MSM_GPT_BASE on the 7x00a though they are being removed.

Shouldn't be too hard to fix.  I'll look at it later today.  It mostly
points out that I haven't been building against 7x00A.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 01/11] msm: Add CPU queries

[Daniel Walker]

On Tue, 2011-01-25 at 11:17 -0800, David Brown wrote:
> On Tue, Jan 25 2011, Daniel Walker wrote:
> 
> > On Mon, 2011-01-24 at 16:57 -0800, David Brown wrote:
> >> MSM7201 and MSM7601 are identical as far as Linux is concerned.  Same
> >> goes for MSM8250 and MSM8650.  Our dev boards are a somewhat random mix
> >> of the two, and it doesn't matter which one you use.
> >> 
> >> MSM8960 is a completely different chip, it just shares a similar name,
> >> to other chips.
> >
> > If you break it down without the "x" then you can recreate the "x"
> > variant with the actual numerical identifier .. For 8660/8960 you just
> > would do as much of a unification as with the others.. You could still
> > use 8x60 to identify those two, you just wouldn't use it as often.
> 
> There isn't any unification to do here.  There are two issues.  We make
> some chips in groups where we have _identical_ silicon on the Linux
> side, but happen to have different numbers.  That's what the X is
> about.  There are other cases where we have completely different silicon
> that happen to have similar numbers.
> 
> The whole point of the cpu_is tests is to tell us exactly which chip we
> are on.  If there is _anything_ different between two chips, that query
> needs to be different.  If there is any kind of unification, it can be
> done at a higher level.  Otherwise, you have no way of making the
> distinction that needs to be made.

I suggesting we do it across the board because consistency is a good
thing .. It also allows us to use 8x60 when 8660 and 8960 are actually
similar .. You can't deny that 8960 is similar to 8660 because your
patches show some duplication due to it.

Daniel


-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 01/11] msm: Add CPU queries

[Daniel Walker]

On Tue, 2011-01-25 at 11:17 -0800, David Brown wrote:
> On Tue, Jan 25 2011, Daniel Walker wrote:
> 
> > On Mon, 2011-01-24 at 16:57 -0800, David Brown wrote:
> >> MSM7201 and MSM7601 are identical as far as Linux is concerned.  Same
> >> goes for MSM8250 and MSM8650.  Our dev boards are a somewhat random mix
> >> of the two, and it doesn't matter which one you use.
> >> 
> >> MSM8960 is a completely different chip, it just shares a similar name,
> >> to other chips.
> >
> > If you break it down without the "x" then you can recreate the "x"
> > variant with the actual numerical identifier .. For 8660/8960 you just
> > would do as much of a unification as with the others.. You could still
> > use 8x60 to identify those two, you just wouldn't use it as often.
> 
> There isn't any unification to do here.  There are two issues.  We make
> some chips in groups where we have _identical_ silicon on the Linux
> side, but happen to have different numbers.  That's what the X is
> about.  There are other cases where we have completely different silicon
> that happen to have similar numbers.
> 
> The whole point of the cpu_is tests is to tell us exactly which chip we
> are on.  If there is _anything_ different between two chips, that query
> needs to be different.  If there is any kind of unification, it can be
> done at a higher level.  Otherwise, you have no way of making the
> distinction that needs to be made.

I suggesting we do it across the board because consistency is a good
thing .. It also allows us to use 8x60 when 8660 and 8960 are actually
similar .. You can't deny that 8960 is similar to 8660 because your
patches show some duplication due to it.

Daniel


-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 01/11] msm: Add CPU queries

[David Brown]

On Tue, Jan 25 2011, Daniel Walker wrote:

> On Tue, 2011-01-25 at 11:17 -0800, David Brown wrote:

> I suggesting we do it across the board because consistency is a good
> thing .. It also allows us to use 8x60 when 8660 and 8960 are actually
> similar .. You can't deny that 8960 is similar to 8660 because your
> patches show some duplication due to it.

You're completely missing the point of these tests.  If _anything_ is
different, the macros need to be different.  I don't care if they're
similar, I need to know when they are different.  That is the point of
the macros.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 01/11] msm: Add CPU queries

[David Brown]

On Tue, Jan 25 2011, Daniel Walker wrote:

> On Tue, 2011-01-25 at 11:17 -0800, David Brown wrote:

> I suggesting we do it across the board because consistency is a good
> thing .. It also allows us to use 8x60 when 8660 and 8960 are actually
> similar .. You can't deny that 8960 is similar to 8660 because your
> patches show some duplication due to it.

You're completely missing the point of these tests.  If _anything_ is
different, the macros need to be different.  I don't care if they're
similar, I need to know when they are different.  That is the point of
the macros.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 01/11] msm: Add CPU queries

[Daniel Walker]

On Tue, 2011-01-25 at 11:45 -0800, David Brown wrote:
> On Tue, Jan 25 2011, Daniel Walker wrote:
> 
> > On Tue, 2011-01-25 at 11:17 -0800, David Brown wrote:
> 
> > I suggesting we do it across the board because consistency is a good
> > thing .. It also allows us to use 8x60 when 8660 and 8960 are actually
> > similar .. You can't deny that 8960 is similar to 8660 because your
> > patches show some duplication due to it.
> 
> You're completely missing the point of these tests.  If _anything_ is
> different, the macros need to be different.  I don't care if they're
> similar, I need to know when they are different.  That is the point of
> the macros.

I said you would have macros specifically for 8660 and 8960, so if you
need to know when they're different then you have macro's to do that. 

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 01/11] msm: Add CPU queries

[Daniel Walker]

On Tue, 2011-01-25 at 11:45 -0800, David Brown wrote:
> On Tue, Jan 25 2011, Daniel Walker wrote:
> 
> > On Tue, 2011-01-25 at 11:17 -0800, David Brown wrote:
> 
> > I suggesting we do it across the board because consistency is a good
> > thing .. It also allows us to use 8x60 when 8660 and 8960 are actually
> > similar .. You can't deny that 8960 is similar to 8660 because your
> > patches show some duplication due to it.
> 
> You're completely missing the point of these tests.  If _anything_ is
> different, the macros need to be different.  I don't care if they're
> similar, I need to know when they are different.  That is the point of
> the macros.

I said you would have macros specifically for 8660 and 8960, so if you
need to know when they're different then you have macro's to do that. 

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

RE: [PATCH v2 01/11] msm: Add CPU queries

[Zhaohui Wang]

Hi all

Maybe it's not appropriate to cut in your discussion.
Can anyone explain what's the difference between qsd8X50 and msm8x60? No msm8x50, right?

Many thanks.


Best Regards
David Wange


-----Original Message-----
From: linux-arm-msm-owner@vger.kernel.org [mailto:linux-arm-msm-owner@vger.kernel.org] On Behalf Of Daniel Walker
Sent: Tuesday, January 25, 2011 3:06 PM
To: David Brown
Cc: linux-arm-msm@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 01/11] msm: Add CPU queries

On Tue, 2011-01-25 at 11:45 -0800, David Brown wrote:
> On Tue, Jan 25 2011, Daniel Walker wrote:
> 
> > On Tue, 2011-01-25 at 11:17 -0800, David Brown wrote:
> 
> > I suggesting we do it across the board because consistency is a good 
> > thing .. It also allows us to use 8x60 when 8660 and 8960 are 
> > actually similar .. You can't deny that 8960 is similar to 8660 
> > because your patches show some duplication due to it.
> 
> You're completely missing the point of these tests.  If _anything_ is 
> different, the macros need to be different.  I don't care if they're 
> similar, I need to know when they are different.  That is the point of 
> the macros.

I said you would have macros specifically for 8660 and 8960, so if you need to know when they're different then you have macro's to do that. 

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

--
To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 01/11] msm: Add CPU queries

[Zhaohui Wang]

Hi all

Maybe it's not appropriate to cut in your discussion.
Can anyone explain what's the difference between qsd8X50 and msm8x60? No msm8x50, right?

Many thanks.


Best Regards
David Wange


-----Original Message-----
From: linux-arm-msm-owner@vger.kernel.org [mailto:linux-arm-msm-owner at vger.kernel.org] On Behalf Of Daniel Walker
Sent: Tuesday, January 25, 2011 3:06 PM
To: David Brown
Cc: linux-arm-msm at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH v2 01/11] msm: Add CPU queries

On Tue, 2011-01-25 at 11:45 -0800, David Brown wrote:
> On Tue, Jan 25 2011, Daniel Walker wrote:
> 
> > On Tue, 2011-01-25 at 11:17 -0800, David Brown wrote:
> 
> > I suggesting we do it across the board because consistency is a good 
> > thing .. It also allows us to use 8x60 when 8660 and 8960 are 
> > actually similar .. You can't deny that 8960 is similar to 8660 
> > because your patches show some duplication due to it.
> 
> You're completely missing the point of these tests.  If _anything_ is 
> different, the macros need to be different.  I don't care if they're 
> similar, I need to know when they are different.  That is the point of 
> the macros.

I said you would have macros specifically for 8660 and 8960, so if you need to know when they're different then you have macro's to do that. 

Daniel

-- 

Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

--
To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo at vger.kernel.org More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v2 01/11] msm: Add CPU queries

[David Brown]

On Tue, Jan 25 2011, Zhaohui Wang wrote:

> Maybe it's not appropriate to cut in your discussion.

It's quite appropriate.

> Can anyone explain what's the difference between qsd8X50 and msm8x60?
> No msm8x50, right?

Well, they're just part numbers, and the numbering isn't all that
consistent over time:
http://www.qualcomm.com/products_services/chipsets/snapdragon.html

The first snapdragon device was calls a QSD (8250 and 8660).  They are
identical as far as Linux is concerned (the modem is different).  There
is no MSM on these.  Only these two chips have used the QSD prefix.

The rest of the family went back to the original MSM prefix on the
names, most in pairs (2 and 6 in the second digit).

The names of the cpu_is macros come right off of the website above
(including the X).

The confusion is that a new chip is being called MSM8960 (web search
pulls up lots of hits about it).  Despite any possibile similarities in
the initial kernel support for this device, it is significantally
different than the MSM8660.  Even the CPU is different.

I've been debating whether to rename the msm8x60 tests to just pick one
of the devices (say msm8660) to avoid the confusion with the 8960.  That
would then, however, be confusing to someone with an MSM8260 device, so
there isn't a solid win.

The cpu_is_...() tests are the tests to distinguish which particular
chip the kernel is running on.  They are supposed to be unique, per
chip.

Classes of chips with similar features would have other tests (see
cpu_class_is_omap2()) made on top of these checks.

David

> Many thanks.
>
>
> Best Regards
> David Wange
>
>
> -----Original Message-----
> From: linux-arm-msm-owner@vger.kernel.org [mailto:linux-arm-msm-owner@vger.kernel.org] On Behalf Of Daniel Walker
> Sent: Tuesday, January 25, 2011 3:06 PM
> To: David Brown
> Cc: linux-arm-msm@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH v2 01/11] msm: Add CPU queries
>
> On Tue, 2011-01-25 at 11:45 -0800, David Brown wrote:
>> On Tue, Jan 25 2011, Daniel Walker wrote:
>> 
>> > On Tue, 2011-01-25 at 11:17 -0800, David Brown wrote:
>> 
>> > I suggesting we do it across the board because consistency is a good 
>> > thing .. It also allows us to use 8x60 when 8660 and 8960 are 
>> > actually similar .. You can't deny that 8960 is similar to 8660 
>> > because your patches show some duplication due to it.
>> 
>> You're completely missing the point of these tests.  If _anything_ is 
>> different, the macros need to be different.  I don't care if they're 
>> similar, I need to know when they are different.  That is the point of 
>> the macros.
>
> I said you would have macros specifically for 8660 and 8960, so if you need to know when they're different then you have macro's to do that. 
>
> Daniel

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 01/11] msm: Add CPU queries

[David Brown]

On Tue, Jan 25 2011, Zhaohui Wang wrote:

> Maybe it's not appropriate to cut in your discussion.

It's quite appropriate.

> Can anyone explain what's the difference between qsd8X50 and msm8x60?
> No msm8x50, right?

Well, they're just part numbers, and the numbering isn't all that
consistent over time:
http://www.qualcomm.com/products_services/chipsets/snapdragon.html

The first snapdragon device was calls a QSD (8250 and 8660).  They are
identical as far as Linux is concerned (the modem is different).  There
is no MSM on these.  Only these two chips have used the QSD prefix.

The rest of the family went back to the original MSM prefix on the
names, most in pairs (2 and 6 in the second digit).

The names of the cpu_is macros come right off of the website above
(including the X).

The confusion is that a new chip is being called MSM8960 (web search
pulls up lots of hits about it).  Despite any possibile similarities in
the initial kernel support for this device, it is significantally
different than the MSM8660.  Even the CPU is different.

I've been debating whether to rename the msm8x60 tests to just pick one
of the devices (say msm8660) to avoid the confusion with the 8960.  That
would then, however, be confusing to someone with an MSM8260 device, so
there isn't a solid win.

The cpu_is_...() tests are the tests to distinguish which particular
chip the kernel is running on.  They are supposed to be unique, per
chip.

Classes of chips with similar features would have other tests (see
cpu_class_is_omap2()) made on top of these checks.

David

> Many thanks.
>
>
> Best Regards
> David Wange
>
>
> -----Original Message-----
> From: linux-arm-msm-owner at vger.kernel.org [mailto:linux-arm-msm-owner at vger.kernel.org] On Behalf Of Daniel Walker
> Sent: Tuesday, January 25, 2011 3:06 PM
> To: David Brown
> Cc: linux-arm-msm at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH v2 01/11] msm: Add CPU queries
>
> On Tue, 2011-01-25 at 11:45 -0800, David Brown wrote:
>> On Tue, Jan 25 2011, Daniel Walker wrote:
>> 
>> > On Tue, 2011-01-25 at 11:17 -0800, David Brown wrote:
>> 
>> > I suggesting we do it across the board because consistency is a good 
>> > thing .. It also allows us to use 8x60 when 8660 and 8960 are 
>> > actually similar .. You can't deny that 8960 is similar to 8660 
>> > because your patches show some duplication due to it.
>> 
>> You're completely missing the point of these tests.  If _anything_ is 
>> different, the macros need to be different.  I don't care if they're 
>> similar, I need to know when they are different.  That is the point of 
>> the macros.
>
> I said you would have macros specifically for 8660 and 8960, so if you need to know when they're different then you have macro's to do that. 
>
> Daniel

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 01/11] msm: Add CPU queries

[Stepan Moskovchenko]

> On Tue, Jan 25 2011, Zhaohui Wang wrote:
>
>> Maybe it's not appropriate to cut in your discussion.
>
> It's quite appropriate.
>
>> Can anyone explain what's the difference between qsd8X50 and msm8x60?
>> No msm8x50, right?
>
> Well, they're just part numbers, and the numbering isn't all that
> consistent over time:
> http://www.qualcomm.com/products_services/chipsets/snapdragon.html
>
> The first snapdragon device was calls a QSD (8250 and 8660).  They are


David, I think you mean "8250 and 8650" here. QSD8250 and QSD8650 are
identical as far as Linux is concerned, whereas MSM8660 is different,
having two cores, etc.


> identical as far as Linux is concerned (the modem is different).  There
> is no MSM on these.  Only these two chips have used the QSD prefix.
>
> The rest of the family went back to the original MSM prefix on the
> names, most in pairs (2 and 6 in the second digit).
>
> The names of the cpu_is macros come right off of the website above
> (including the X).
>
> The confusion is that a new chip is being called MSM8960 (web search
> pulls up lots of hits about it).  Despite any possibile similarities in
> the initial kernel support for this device, it is significantally
> different than the MSM8660.  Even the CPU is different.
>
> I've been debating whether to rename the msm8x60 tests to just pick one
> of the devices (say msm8660) to avoid the confusion with the 8960.  That
> would then, however, be confusing to someone with an MSM8260 device, so
> there isn't a solid win.
>
> The cpu_is_...() tests are the tests to distinguish which particular
> chip the kernel is running on.  They are supposed to be unique, per
> chip.
>
> Classes of chips with similar features would have other tests (see
> cpu_class_is_omap2()) made on top of these checks.
>
> David
>
>> Many thanks.
>>
>>
>> Best Regards
>> David Wange
>>
>>
>> -----Original Message-----
>> From: linux-arm-msm-owner@vger.kernel.org
>> [mailto:linux-arm-msm-owner@vger.kernel.org] On Behalf Of Daniel Walker
>> Sent: Tuesday, January 25, 2011 3:06 PM
>> To: David Brown
>> Cc: linux-arm-msm@vger.kernel.org; linux-kernel@vger.kernel.org;
>> linux-arm-kernel@lists.infradead.org
>> Subject: Re: [PATCH v2 01/11] msm: Add CPU queries
>>
>> On Tue, 2011-01-25 at 11:45 -0800, David Brown wrote:
>>> On Tue, Jan 25 2011, Daniel Walker wrote:
>>>
>>> > On Tue, 2011-01-25 at 11:17 -0800, David Brown wrote:
>>>
>>> > I suggesting we do it across the board because consistency is a good
>>> > thing .. It also allows us to use 8x60 when 8660 and 8960 are
>>> > actually similar .. You can't deny that 8960 is similar to 8660
>>> > because your patches show some duplication due to it.
>>>
>>> You're completely missing the point of these tests.  If _anything_ is
>>> different, the macros need to be different.  I don't care if they're
>>> similar, I need to know when they are different.  That is the point of
>>> the macros.
>>
>> I said you would have macros specifically for 8660 and 8960, so if you
>> need to know when they're different then you have macro's to do that.
>>
>> Daniel
>
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm"
> in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 01/11] msm: Add CPU queries

[Stepan Moskovchenko]

> On Tue, Jan 25 2011, Zhaohui Wang wrote:
>
>> Maybe it's not appropriate to cut in your discussion.
>
> It's quite appropriate.
>
>> Can anyone explain what's the difference between qsd8X50 and msm8x60?
>> No msm8x50, right?
>
> Well, they're just part numbers, and the numbering isn't all that
> consistent over time:
> http://www.qualcomm.com/products_services/chipsets/snapdragon.html
>
> The first snapdragon device was calls a QSD (8250 and 8660).  They are


David, I think you mean "8250 and 8650" here. QSD8250 and QSD8650 are
identical as far as Linux is concerned, whereas MSM8660 is different,
having two cores, etc.


> identical as far as Linux is concerned (the modem is different).  There
> is no MSM on these.  Only these two chips have used the QSD prefix.
>
> The rest of the family went back to the original MSM prefix on the
> names, most in pairs (2 and 6 in the second digit).
>
> The names of the cpu_is macros come right off of the website above
> (including the X).
>
> The confusion is that a new chip is being called MSM8960 (web search
> pulls up lots of hits about it).  Despite any possibile similarities in
> the initial kernel support for this device, it is significantally
> different than the MSM8660.  Even the CPU is different.
>
> I've been debating whether to rename the msm8x60 tests to just pick one
> of the devices (say msm8660) to avoid the confusion with the 8960.  That
> would then, however, be confusing to someone with an MSM8260 device, so
> there isn't a solid win.
>
> The cpu_is_...() tests are the tests to distinguish which particular
> chip the kernel is running on.  They are supposed to be unique, per
> chip.
>
> Classes of chips with similar features would have other tests (see
> cpu_class_is_omap2()) made on top of these checks.
>
> David
>
>> Many thanks.
>>
>>
>> Best Regards
>> David Wange
>>
>>
>> -----Original Message-----
>> From: linux-arm-msm-owner at vger.kernel.org
>> [mailto:linux-arm-msm-owner at vger.kernel.org] On Behalf Of Daniel Walker
>> Sent: Tuesday, January 25, 2011 3:06 PM
>> To: David Brown
>> Cc: linux-arm-msm at vger.kernel.org; linux-kernel at vger.kernel.org;
>> linux-arm-kernel at lists.infradead.org
>> Subject: Re: [PATCH v2 01/11] msm: Add CPU queries
>>
>> On Tue, 2011-01-25 at 11:45 -0800, David Brown wrote:
>>> On Tue, Jan 25 2011, Daniel Walker wrote:
>>>
>>> > On Tue, 2011-01-25 at 11:17 -0800, David Brown wrote:
>>>
>>> > I suggesting we do it across the board because consistency is a good
>>> > thing .. It also allows us to use 8x60 when 8660 and 8960 are
>>> > actually similar .. You can't deny that 8960 is similar to 8660
>>> > because your patches show some duplication due to it.
>>>
>>> You're completely missing the point of these tests.  If _anything_ is
>>> different, the macros need to be different.  I don't care if they're
>>> similar, I need to know when they are different.  That is the point of
>>> the macros.
>>
>> I said you would have macros specifically for 8660 and 8960, so if you
>> need to know when they're different then you have macro's to do that.
>>
>> Daniel
>
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm"
> in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 01/11] msm: Add CPU queries

[David Brown]

On Tue, Jan 25 2011, Stepan Moskovchenko wrote:

>> On Tue, Jan 25 2011, Zhaohui Wang wrote:
>>
>>> Maybe it's not appropriate to cut in your discussion.
>>
>> It's quite appropriate.
>>
>>> Can anyone explain what's the difference between qsd8X50 and msm8x60?
>>> No msm8x50, right?
>>
>> Well, they're just part numbers, and the numbering isn't all that
>> consistent over time:
>> http://www.qualcomm.com/products_services/chipsets/snapdragon.html
>>
>> The first snapdragon device was calls a QSD (8250 and 8660).  They are
>
> David, I think you mean "8250 and 8650" here. QSD8250 and QSD8650 are
> identical as far as Linux is concerned, whereas MSM8660 is different,
> having two cores, etc.

Yes, thanks.

David

[PATCH v2 01/11] msm: Add CPU queries

[David Brown]

On Tue, Jan 25 2011, Stepan Moskovchenko wrote:

>> On Tue, Jan 25 2011, Zhaohui Wang wrote:
>>
>>> Maybe it's not appropriate to cut in your discussion.
>>
>> It's quite appropriate.
>>
>>> Can anyone explain what's the difference between qsd8X50 and msm8x60?
>>> No msm8x50, right?
>>
>> Well, they're just part numbers, and the numbering isn't all that
>> consistent over time:
>> http://www.qualcomm.com/products_services/chipsets/snapdragon.html
>>
>> The first snapdragon device was calls a QSD (8250 and 8660).  They are
>
> David, I think you mean "8250 and 8650" here. QSD8250 and QSD8650 are
> identical as far as Linux is concerned, whereas MSM8660 is different,
> having two cores, etc.

Yes, thanks.

David

Re: [PATCH v2 02/11] msm: Generalize timer register mappings

[Dima Zavin]

On Mon, Jan 24, 2011 at 2:44 PM, David Brown <davidb@codeaurora.org> wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
>
>> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>>> +       int global_offset = 0;
>>> +
>>> +       if (cpu_is_msm7x01()) {
>>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
>>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
>>> +       } else if (cpu_is_msm7x30()) {
>>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
>>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
>>> +       } else if (cpu_is_qsd8x50()) {
>>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
>>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
>>> +       } else if (cpu_is_msm8x60()) {
>>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
>>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
>>> +
>>> +               /* Use CPU0's timer as the global timer. */
>>> +               global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
>>> +       } else
>>> +               BUG();
>>
>> Ifdef's here would be OK I think, your already using the "runtime"
>> checks ..
>
> The point of the change is to get rid of the ifdefs so that we can
> dynamically detect which target we are on.  Yes, there are other places
> where it doesn't work, but we'll get there gradually.

To be honest I don't understand why you would want to do this at
runtime. You cannot select multiple SoCs in the kernel build anyway,
nor would you want to. Trying to have same kernel to boot on ARM v6
and ARM v7 would already be freaky enough. On top of that mixing 7201a
with all the baggage that it comes with 8x60 just wouldn't make sense.
These architectures are so different that it I can't see that ever
being useful. When would you ever envision building for multiple of
these SoCs at the same time?

--Dima

>
> David
>
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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Re: [PATCH v2 02/11] msm: Generalize timer register mappings

[Dima Zavin]

On Mon, Jan 24, 2011 at 2:44 PM, David Brown <davidb@codeaurora.org> wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
>
>> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>>> +       int global_offset = 0;
>>> +
>>> +       if (cpu_is_msm7x01()) {
>>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
>>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
>>> +       } else if (cpu_is_msm7x30()) {
>>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
>>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
>>> +       } else if (cpu_is_qsd8x50()) {
>>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
>>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
>>> +       } else if (cpu_is_msm8x60()) {
>>> +               msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
>>> +               msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
>>> +
>>> +               /* Use CPU0's timer as the global timer. */
>>> +               global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
>>> +       } else
>>> +               BUG();
>>
>> Ifdef's here would be OK I think, your already using the "runtime"
>> checks ..
>
> The point of the change is to get rid of the ifdefs so that we can
> dynamically detect which target we are on.  Yes, there are other places
> where it doesn't work, but we'll get there gradually.

To be honest I don't understand why you would want to do this at
runtime. You cannot select multiple SoCs in the kernel build anyway,
nor would you want to. Trying to have same kernel to boot on ARM v6
and ARM v7 would already be freaky enough. On top of that mixing 7201a
with all the baggage that it comes with 8x60 just wouldn't make sense.
These architectures are so different that it I can't see that ever
being useful. When would you ever envision building for multiple of
these SoCs at the same time?

--Dima

>
> David
>
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
>

[PATCH v2 02/11] msm: Generalize timer register mappings

[Dima Zavin]

On Mon, Jan 24, 2011 at 2:44 PM, David Brown <davidb@codeaurora.org> wrote:
> On Mon, Jan 24 2011, Daniel Walker wrote:
>
>> On Wed, 2011-01-19 at 12:25 -0800, David Brown wrote:
>>> + ? ? ? int global_offset = 0;
>>> +
>>> + ? ? ? if (cpu_is_msm7x01()) {
>>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
>>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
>>> + ? ? ? } else if (cpu_is_msm7x30()) {
>>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
>>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
>>> + ? ? ? } else if (cpu_is_qsd8x50()) {
>>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
>>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
>>> + ? ? ? } else if (cpu_is_msm8x60()) {
>>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
>>> + ? ? ? ? ? ? ? msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
>>> +
>>> + ? ? ? ? ? ? ? /* Use CPU0's timer as the global timer. */
>>> + ? ? ? ? ? ? ? global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
>>> + ? ? ? } else
>>> + ? ? ? ? ? ? ? BUG();
>>
>> Ifdef's here would be OK I think, your already using the "runtime"
>> checks ..
>
> The point of the change is to get rid of the ifdefs so that we can
> dynamically detect which target we are on. ?Yes, there are other places
> where it doesn't work, but we'll get there gradually.

To be honest I don't understand why you would want to do this at
runtime. You cannot select multiple SoCs in the kernel build anyway,
nor would you want to. Trying to have same kernel to boot on ARM v6
and ARM v7 would already be freaky enough. On top of that mixing 7201a
with all the baggage that it comes with 8x60 just wouldn't make sense.
These architectures are so different that it I can't see that ever
being useful. When would you ever envision building for multiple of
these SoCs at the same time?

--Dima

>
> David
>
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at ?http://www.tux.org/lkml/
>

Re: [PATCH v2 02/11] msm: Generalize timer register mappings

[David Brown]

On Wed, Jan 26 2011, Dima Zavin wrote:

> On Mon, Jan 24, 2011 at 2:44 PM, David Brown <davidb@codeaurora.org> wrote:

> To be honest I don't understand why you would want to do this at
> runtime. You cannot select multiple SoCs in the kernel build anyway,
> nor would you want to. Trying to have same kernel to boot on ARM v6
> and ARM v7 would already be freaky enough. On top of that mixing 7201a
> with all the baggage that it comes with 8x60 just wouldn't make sense.
> These architectures are so different that it I can't see that ever
> being useful. When would you ever envision building for multiple of
> these SoCs at the same time?

People (especially distributions) want to be able to build one arm
kernel rather than multiple ones.  The issues about CPU detection and
base addresses are being worked on now.

Other targets, especially omap, are already way ahead of MSM in this
area.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 02/11] msm: Generalize timer register mappings

[David Brown]

On Wed, Jan 26 2011, Dima Zavin wrote:

> On Mon, Jan 24, 2011 at 2:44 PM, David Brown <davidb@codeaurora.org> wrote:

> To be honest I don't understand why you would want to do this at
> runtime. You cannot select multiple SoCs in the kernel build anyway,
> nor would you want to. Trying to have same kernel to boot on ARM v6
> and ARM v7 would already be freaky enough. On top of that mixing 7201a
> with all the baggage that it comes with 8x60 just wouldn't make sense.
> These architectures are so different that it I can't see that ever
> being useful. When would you ever envision building for multiple of
> these SoCs at the same time?

People (especially distributions) want to be able to build one arm
kernel rather than multiple ones.  The issues about CPU detection and
base addresses are being worked on now.

Other targets, especially omap, are already way ahead of MSM in this
area.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

Re: [PATCH v2 02/11] msm: Generalize timer register mappings

[Russell King - ARM Linux]

On Wed, Jan 26, 2011 at 02:12:59PM -0800, Dima Zavin wrote:
> To be honest I don't understand why you would want to do this at
> runtime. You cannot select multiple SoCs in the kernel build anyway,
> nor would you want to. Trying to have same kernel to boot on ARM v6
> and ARM v7 would already be freaky enough.

Wrong.  We already have that working with mainline plus some additional
patches.  OMAP people want it, and it's precisely the direction which
quite a number of people within the ARM community want to move.

Building an ARM kernel to cover multiple different CPU types is something
which has always been possible, although with SMP and a few other things
it's become a little harder.  Not impossible though, and not impossible
to do efficiently either.

[PATCH v2 02/11] msm: Generalize timer register mappings

[Russell King - ARM Linux]

On Wed, Jan 26, 2011 at 02:12:59PM -0800, Dima Zavin wrote:
> To be honest I don't understand why you would want to do this at
> runtime. You cannot select multiple SoCs in the kernel build anyway,
> nor would you want to. Trying to have same kernel to boot on ARM v6
> and ARM v7 would already be freaky enough.

Wrong.  We already have that working with mainline plus some additional
patches.  OMAP people want it, and it's precisely the direction which
quite a number of people within the ARM community want to move.

Building an ARM kernel to cover multiple different CPU types is something
which has always been possible, although with SMP and a few other things
it's become a little harder.  Not impossible though, and not impossible
to do efficiently either.

Re: [PATCH v2 02/11] msm: Generalize timer register mappings

[Dima Zavin]

On Wed, Jan 26, 2011 at 2:41 PM, David Brown <davidb@codeaurora.org> wrote:
> On Wed, Jan 26 2011, Dima Zavin wrote:
>
>> On Mon, Jan 24, 2011 at 2:44 PM, David Brown <davidb@codeaurora.org> wrote:
>
>> To be honest I don't understand why you would want to do this at
>> runtime. You cannot select multiple SoCs in the kernel build anyway,
>> nor would you want to. Trying to have same kernel to boot on ARM v6
>> and ARM v7 would already be freaky enough. On top of that mixing 7201a
>> with all the baggage that it comes with 8x60 just wouldn't make sense.
>> These architectures are so different that it I can't see that ever
>> being useful. When would you ever envision building for multiple of
>> these SoCs at the same time?
>
> People (especially distributions) want to be able to build one arm
> kernel rather than multiple ones.  The issues about CPU detection and
> base addresses are being worked on now.

Yeah, you are right. I guess for distributions that would make a lot
of sense. Point taken.

I think the hard part for msm will be in the peripheral drivers and
not in core. The subtle ways in which all the bits move around in the
peripherals like the display and nand controllers made it very hard
without doing defines and build time. I'm not sure how much worse or
better it is in TI land?

--Dima

> Other targets, especially omap, are already way ahead of MSM in this
> area.


>
> David
>
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
>
--
To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v2 02/11] msm: Generalize timer register mappings

[Dima Zavin]

On Wed, Jan 26, 2011 at 2:41 PM, David Brown <davidb@codeaurora.org> wrote:
> On Wed, Jan 26 2011, Dima Zavin wrote:
>
>> On Mon, Jan 24, 2011 at 2:44 PM, David Brown <davidb@codeaurora.org> wrote:
>
>> To be honest I don't understand why you would want to do this at
>> runtime. You cannot select multiple SoCs in the kernel build anyway,
>> nor would you want to. Trying to have same kernel to boot on ARM v6
>> and ARM v7 would already be freaky enough. On top of that mixing 7201a
>> with all the baggage that it comes with 8x60 just wouldn't make sense.
>> These architectures are so different that it I can't see that ever
>> being useful. When would you ever envision building for multiple of
>> these SoCs at the same time?
>
> People (especially distributions) want to be able to build one arm
> kernel rather than multiple ones.  The issues about CPU detection and
> base addresses are being worked on now.

Yeah, you are right. I guess for distributions that would make a lot
of sense. Point taken.

I think the hard part for msm will be in the peripheral drivers and
not in core. The subtle ways in which all the bits move around in the
peripherals like the display and nand controllers made it very hard
without doing defines and build time. I'm not sure how much worse or
better it is in TI land?

--Dima

> Other targets, especially omap, are already way ahead of MSM in this
> area.


>
> David
>
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
>

[PATCH v2 02/11] msm: Generalize timer register mappings

[Dima Zavin]

On Wed, Jan 26, 2011 at 2:41 PM, David Brown <davidb@codeaurora.org> wrote:
> On Wed, Jan 26 2011, Dima Zavin wrote:
>
>> On Mon, Jan 24, 2011 at 2:44 PM, David Brown <davidb@codeaurora.org> wrote:
>
>> To be honest I don't understand why you would want to do this at
>> runtime. You cannot select multiple SoCs in the kernel build anyway,
>> nor would you want to. Trying to have same kernel to boot on ARM v6
>> and ARM v7 would already be freaky enough. On top of that mixing 7201a
>> with all the baggage that it comes with 8x60 just wouldn't make sense.
>> These architectures are so different that it I can't see that ever
>> being useful. When would you ever envision building for multiple of
>> these SoCs at the same time?
>
> People (especially distributions) want to be able to build one arm
> kernel rather than multiple ones. ?The issues about CPU detection and
> base addresses are being worked on now.

Yeah, you are right. I guess for distributions that would make a lot
of sense. Point taken.

I think the hard part for msm will be in the peripheral drivers and
not in core. The subtle ways in which all the bits move around in the
peripherals like the display and nand controllers made it very hard
without doing defines and build time. I'm not sure how much worse or
better it is in TI land?

--Dima

> Other targets, especially omap, are already way ahead of MSM in this
> area.


>
> David
>
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
>