[PATCH 00/41] [RFC] Haswell v2

[PATCH 00/41] [RFC] Haswell v2

[Eugeni Dodonov]

This is an updated set of patches for Haswell enablement. I tried to address
all the comments, and re-diffed the patches to simplify their inclusion into
Daniel's tree.

I have also split the PCI IDs definitions and their hook-up into the binding
tables as well. But I think we should wait on picking up those 2 patches for
now - the PCI ID allocation logic here will still receive some additional
changes I think.

Functionality-wise, those patches do detect digital outputs now, namely HDMI,
but said outputs do not (yet) work. The digital output detection process is
also different from what we had previously - we can detect the presence of a
connection on a port via DDI port feedback, but we cannot say if it is HDMI or
DP. So I am not quite certain on how to address this properly in the driver
yet. For now, I just blindly assume that it is HDMI as I don't have any DP
monitors or connectors to test :). But for all means, please consider that
support for digital outputs in this series is still unfinished and will change
considerable in the future. Nonetheless, any feedback on how to implement it
properly is much welcome.

Note that with the DDI buffers, the same port can drive DP and HDMI without any
buffer configuration changes; and we can drive FDI and HDMI likewise. So I've
split the DDI buffers settings into a separate patch to pre-configure the ports
to their suggested connection settings at the init time, which should work for
any combinations of outputs.

As for other changes, there are some comments improvements, some register name
changes, a new enum for DDI ports, some changes in SBI handchake handling, a
couple of new clocks we need for digital outputs and a bit of changes in the
DDI pipe settings handling code.

So Daniel, as we talked on irc, could you check which of those patches could be
early picked into your tree? This would reduce future patchbombs from my side -
I'd expect to have at least a half-dozen new patches until we'll have working
digital outputs in place..


Eugeni Dodonov (41):
  drm/i915: transform HAS_PCH_SPLIT in a feature check
  drm/i915: add Haswell devices and their PCI IDs
  drm/i915: hook Haswell devices in place
  drm/i915: add support for LynxPoint PCH
  drm/i915: add support for power wells
  drm/i915: add enumeration for DDI ports
  drm/i915: add DDI registers
  drm/i915: add DP_TP_CTL registers
  drm/i915: add DP_TP_STATUS registers
  drm/i915: add definitions for DDI_BUF_CTL registers
  drm/i915: add definition of DDI buffer translations regs
  drm/i915: add definition of LPT FDI port width registers
  drm/i915: add SBI registers
  drm/i915: add support for SBI ops
  drm/i915: add PIXCLK_GATE register
  drm/i915: add S PLL control
  drm/i915: add port clock selection support for HSW
  drm/i915: add SSC offsets for SBI access
  drm/i915: add LCPLL control registers
  drm/i915: add WRPLL clocks
  drm/i915: add WM_LINETIME registers
  drm/i915: add SFUSE_STRAP registers for digital port detection
  drm/i915: calculate same watermarks on Haswell as on Ivy Bridge
  drm/i915: share forcewaking code between IVB and HSW
  drm/i915: haswell has 3 pipes as well
  drm/i915: reuse Ivybridge interrupts code for Haswell
  drm/i915: share pipe count handling with Ivybridge
  drm/i915: share IVB cursor routine with Haswell
  drm/i915: show unknown sdvox registers on hdmi init
  drm/i915: enable power wells on haswell init
  drm/i915: disable rc6 on haswell for now
  drm/i915: program WM_LINETIME on Haswell
  drm/i915: initialize DDI buffer translations
  drm/i915: perform Haswell DDI link training in FDI mode
  drm/i915: disable pipe DDI function when disabling pipe
  drm/i915: do not use fdi_normal_train on haswell
  drm/i915: program iCLKIP on Lynx Point
  drm/i915: detect digital outputs on Haswell
  drm/i915: add support for DDI-controlled digital outputs
  drm/i915: prepare HDMI link for Haswell
  drm/i915: add debugging bits for haswell modesetting

 drivers/char/agp/intel-agp.c         |    4 +
 drivers/char/agp/intel-agp.h         |   11 +
 drivers/char/agp/intel-gtt.c         |   14 +
 drivers/gpu/drm/i915/i915_dma.c      |    2 +-
 drivers/gpu/drm/i915/i915_drv.c      |   37 ++
 drivers/gpu/drm/i915/i915_drv.h      |   17 +-
 drivers/gpu/drm/i915/i915_irq.c      |    6 +-
 drivers/gpu/drm/i915/i915_reg.h      |  194 +++++++++
 drivers/gpu/drm/i915/intel_display.c |  733 ++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_drv.h     |    1 +
 drivers/gpu/drm/i915/intel_hdmi.c    |   84 +++-
 11 files changed, 1064 insertions(+), 39 deletions(-)

-- 
1.7.9.5

[PATCH 01/41] drm/i915: transform HAS_PCH_SPLIT in a feature check

[Eugeni Dodonov]

The macro is becoming too complex and with VLV upon us it can lead to
confusion. So transforming this into a feature check instead.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c |    6 ++++++
 drivers/gpu/drm/i915/i915_drv.h |    3 ++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8e2c52e..9cf66e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -211,6 +211,7 @@ static const struct intel_device_info intel_ironlake_d_info = {
 	.gen = 5,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_bsd_ring = 1,
+	.has_pch_split = 1,
 };
 
 static const struct intel_device_info intel_ironlake_m_info = {
@@ -218,6 +219,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_fbc = 1,
 	.has_bsd_ring = 1,
+	.has_pch_split = 1,
 };
 
 static const struct intel_device_info intel_sandybridge_d_info = {
@@ -226,6 +228,7 @@ static const struct intel_device_info intel_sandybridge_d_info = {
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.has_llc = 1,
+	.has_pch_split = 1,
 };
 
 static const struct intel_device_info intel_sandybridge_m_info = {
@@ -235,6 +238,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.has_llc = 1,
+	.has_pch_split = 1,
 };
 
 static const struct intel_device_info intel_ivybridge_d_info = {
@@ -243,6 +247,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.has_llc = 1,
+	.has_pch_split = 1,
 };
 
 static const struct intel_device_info intel_ivybridge_m_info = {
@@ -252,6 +257,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.has_llc = 1,
+	.has_pch_split = 1,
 };
 
 static const struct pci_device_id pciidlist[] = {		/* aka */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f2f9dd9..0443f2d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -255,6 +255,7 @@ struct intel_device_info {
 	u8 is_broadwater:1;
 	u8 is_crestline:1;
 	u8 is_ivybridge:1;
+	u8 has_pch_split:1;
 	u8 has_fbc:1;
 	u8 has_pipe_cxsr:1;
 	u8 has_hotplug:1;
@@ -1048,7 +1049,7 @@ struct drm_i915_file_private {
 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
 
-#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+#define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split)
 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
 
 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
-- 
1.7.9.5

[PATCH 02/41] drm/i915: add Haswell devices and their PCI IDs

[Eugeni Dodonov]

This adds product definitions for desktop, mobile and server boards.

v2: split into a separate patch, add .has_pch_split feature.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/char/agp/intel-agp.h    |   11 +++++++++++
 drivers/char/agp/intel-gtt.c    |   14 ++++++++++++++
 drivers/gpu/drm/i915/i915_drv.c |   18 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h |    2 ++
 4 files changed, 45 insertions(+)

diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 5da67f1..46394c11 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -234,6 +234,17 @@
 #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG		0x0166
 #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB		0x0158  /* Server */
 #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG		0x015A
+#define PCI_DEVICE_ID_INTEL_HASWELL_HB				0x0400 /* Desktop */
+#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG		0x0402
+#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG		0x0412
+#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB			0x0404 /* Mobile */
+#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG		0x0406
+#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG		0x0416
+#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB			0x0408 /* Server */
+#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG		0x040a
+#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG		0x041a
+#define PCI_DEVICE_ID_INTEL_HASWELL_SDV		0x0c16 /* SDV */
+#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB			0x0c04
 
 int intel_gmch_probe(struct pci_dev *pdev,
 			       struct agp_bridge_data *bridge);
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 5cf47ac..f494556 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1459,6 +1459,20 @@ static const struct intel_gtt_driver_description {
 	    "Ivybridge", &sandybridge_gtt_driver },
 	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
 	    "Ivybridge", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
+	    "Haswell", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
+	    "Haswell", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
+	    "Haswell", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
+	    "Haswell", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
+	    "Haswell", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
+	    "Haswell", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV,
+	    "Haswell", &sandybridge_gtt_driver },
 	{ 0, NULL, NULL }
 };
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9cf66e1..6e4d90c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -260,6 +260,24 @@ static const struct intel_device_info intel_ivybridge_m_info = {
 	.has_pch_split = 1,
 };
 
+static const struct intel_device_info intel_haswell_d_info = {
+	.is_haswell = 1, .gen = 7,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.has_bsd_ring = 1,
+	.has_blt_ring = 1,
+	.has_llc = 1,
+	.has_pch_split = 1,
+};
+
+static const struct intel_device_info intel_haswell_m_info = {
+	.is_haswell = 1, .gen = 7, .is_mobile = 1,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.has_bsd_ring = 1,
+	.has_blt_ring = 1,
+	.has_llc = 1,
+	.has_pch_split = 1,
+};
+
 static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */
 	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0443f2d..90681d6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -256,6 +256,7 @@ struct intel_device_info {
 	u8 is_crestline:1;
 	u8 is_ivybridge:1;
 	u8 has_pch_split:1;
+	u8 is_haswell:1;
 	u8 has_fbc:1;
 	u8 has_pipe_cxsr:1;
 	u8 has_hotplug:1;
@@ -1006,6 +1007,7 @@ struct drm_i915_file_private {
 #define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
 #define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
 #define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
+#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
 
 /*
-- 
1.7.9.5

[PATCH 03/41] drm/i915: hook Haswell devices in place

[Eugeni Dodonov]

This patch enabled i915 driver to handle Haswell devices. It should go in
last, when things are working stable enough.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/char/agp/intel-agp.c    |    4 ++++
 drivers/gpu/drm/i915/i915_drv.c |    7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index 962e75d..0ad4933 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -907,6 +907,10 @@ static struct pci_device_id agp_intel_pci_table[] = {
 	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),
 	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),
 	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),
+	ID(PCI_DEVICE_ID_INTEL_HASWELL_HB),
+	ID(PCI_DEVICE_ID_INTEL_HASWELL_M_HB),
+	ID(PCI_DEVICE_ID_INTEL_HASWELL_S_HB),
+	ID(PCI_DEVICE_ID_INTEL_HASWELL_E_HB),
 	{ }
 };
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6e4d90c..8995165 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -322,6 +322,13 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
+	INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
+	INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
+	INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
+	INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
+	INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
+	INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
+	INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
 	{0, 0, 0}
 };
 
-- 
1.7.9.5

[PATCH 04/41] drm/i915: add support for LynxPoint PCH

[Eugeni Dodonov]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c |    4 ++++
 drivers/gpu/drm/i915/i915_drv.h |    2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8995165..e4b5571 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -340,6 +340,7 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE	0x3b00
 #define INTEL_PCH_CPT_DEVICE_ID_TYPE	0x1c00
 #define INTEL_PCH_PPT_DEVICE_ID_TYPE	0x1e00
+#define INTEL_PCH_LPT_DEVICE_ID_TYPE	0x8c00
 
 void intel_detect_pch(struct drm_device *dev)
 {
@@ -368,6 +369,9 @@ void intel_detect_pch(struct drm_device *dev)
 				/* PantherPoint is CPT compatible */
 				dev_priv->pch_type = PCH_CPT;
 				DRM_DEBUG_KMS("Found PatherPoint PCH\n");
+			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
+				dev_priv->pch_type = PCH_LPT;
+				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 			}
 		}
 		pci_dev_put(pch);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 90681d6..146778e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -293,6 +293,7 @@ enum no_fbc_reason {
 enum intel_pch {
 	PCH_IBX,	/* Ibexpeak PCH */
 	PCH_CPT,	/* Cougarpoint PCH */
+	PCH_LPT,	/* Lynxpoint PCH */
 };
 
 #define QUIRK_PIPEA_FORCE (1<<0)
@@ -1055,6 +1056,7 @@ struct drm_i915_file_private {
 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
 
 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
+#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
 
-- 
1.7.9.5

[PATCH 05/41] drm/i915: add support for power wells

[Eugeni Dodonov]

This defines the registers used by different power wells.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52a06be..b13ed38 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3850,4 +3850,17 @@
 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI		(0xf << 16)
 #define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
 
+/* HSW Power Wells */
+#define HSW_PWR_WELL_CTL1		0x45400		/* BIOS */
+#define HSW_PWR_WELL_CTL2		0x45404		/* Driver */
+#define HSW_PWR_WELL_CTL3		0x45408		/* KVMR */
+#define HSW_PWR_WELL_CTL4		0x4540C		/* Debug */
+#define   HSW_PWR_WELL_ENABLE				(1<<31)
+#define   HSW_PWR_WELL_STATE				(1<<30)
+#define HSW_PWR_WELL_CTL5		0x45410
+#define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1<<31)
+#define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1<<20)
+#define   HSW_PWR_WELL_FORCE_ON				(1<<19)
+#define HSW_PWR_WELL_CTL6		0x45414
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.5

[PATCH 06/41] drm/i915: add enumeration for DDI ports

[Eugeni Dodonov]

There are 5 DDI ports on Haswell. Port A is always enabled, and is the one
connected to eDP, and Port E is the one that can be connected to the PCH
using FDI protocol.  Ports B, C, D and E can be used for digital outputs.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |   10 ++++++++++
 drivers/gpu/drm/i915/i915_reg.h |    2 ++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 146778e..a30e88f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -63,6 +63,16 @@ enum plane {
 };
 #define plane_name(p) ((p) + 'A')
 
+enum port {
+	PORT_A = 0,
+	PORT_B,
+	PORT_C,
+	PORT_D,
+	PORT_E,
+	I915_MAX_PORTS
+};
+#define port_name(p) ((p) + 'A')
+
 #define I915_GEM_GPU_DOMAINS	(~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
 
 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b13ed38..cf7b397 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -27,6 +27,8 @@
 
 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
 
+#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
+
 /*
  * The Bridge device's PCI config space has information about the
  * fb aperture size and the amount of pre-reserved memory.
-- 
1.7.9.5

[PATCH 07/41] drm/i915: add DDI registers

[Eugeni Dodonov]

There is one set of such registers for each pipe (A/B/C/EDP).

v2: update to use DDI PORTS enum

v1 Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cf7b397..26c6929 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3865,4 +3865,30 @@
 #define   HSW_PWR_WELL_FORCE_ON				(1<<19)
 #define HSW_PWR_WELL_CTL6		0x45414
 
+/* Per-pipe DDI Function Control */
+#define PIPE_DDI_FUNC_CTL_A			0x60400
+#define PIPE_DDI_FUNC_CTL_B			0x61400
+#define PIPE_DDI_FUNC_CTL_C			0x62400
+#define PIPE_DDI_FUNC_CTL_EDP		0x6F400
+#define DDI_FUNC_CTL(pipe) _PIPE(pipe, \
+					PIPE_DDI_FUNC_CTL_A, \
+					PIPE_DDI_FUNC_CTL_B)
+#define  PIPE_DDI_FUNC_ENABLE		(1<<31)
+/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
+#define  PIPE_DDI_PORT_MASK				(0xf<<28)
+#define  PIPE_DDI_SELECT_PORT(x)		((x)<<28)
+#define  PIPE_DDI_MODE_SELECT_HDMI		(0<<24)
+#define  PIPE_DDI_MODE_SELECT_DVI		(1<<24)
+#define  PIPE_DDI_MODE_SELECT_DP_SST	(2<<24)
+#define  PIPE_DDI_MODE_SELECT_DP_MST	(3<<24)
+#define  PIPE_DDI_MODE_SELECT_FDI		(4<<24)
+#define  PIPE_DDI_BPC_8					(0<<20)
+#define  PIPE_DDI_BPC_10				(1<<20)
+#define  PIPE_DDI_BPC_6					(2<<20)
+#define  PIPE_DDI_BPC_12				(3<<20)
+#define  PIPE_DDI_BFI_ENABLE			(1<<4)
+#define  PIPE_DDI_PORT_WIDTH_X1			(0<<1)
+#define  PIPE_DDI_PORT_WIDTH_X2			(1<<1)
+#define  PIPE_DDI_PORT_WIDTH_X4			(3<<1)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.5

[PATCH 08/41] drm/i915: add DP_TP_CTL registers

[Eugeni Dodonov]

This is one set of those registers for each pipe.

v2: use port enum to access individual registers

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 26c6929..627e52d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3891,4 +3891,20 @@
 #define  PIPE_DDI_PORT_WIDTH_X2			(1<<1)
 #define  PIPE_DDI_PORT_WIDTH_X4			(3<<1)
 
+/* DisplayPort Transport Control */
+#define DP_TP_CTL_A			0x64040
+#define DP_TP_CTL_B			0x64140
+#define DP_TP_CTL(port) _PORT(port, \
+					DP_TP_CTL_A, \
+					DP_TP_CTL_B)
+#define  DP_TP_CTL_ENABLE		(1<<31)
+#define  DP_TP_CTL_MODE_SST	(0<<27)
+#define  DP_TP_CTL_MODE_MST	(1<<27)
+#define  DP_TP_CTL_ENHANCED_FRAME_ENABLE	(1<<18)
+#define  DP_TP_CTL_FDI_AUTOTRAIN	(1<<15)
+#define  DP_TP_CTL_LINK_TRAIN_MASK		(7<<8)
+#define  DP_TP_CTL_LINK_TRAIN_PAT1		(0<<8)
+#define  DP_TP_CTL_LINK_TRAIN_PAT2		(1<<8)
+#define  DP_TP_CTL_LINK_TRAIN_NORMAL	(3<<8)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.5

[PATCH 09/41] drm/i915: add DP_TP_STATUS registers

[Eugeni Dodonov]

There is one set of those registers for each port.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 627e52d..666e319 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3907,4 +3907,12 @@
 #define  DP_TP_CTL_LINK_TRAIN_PAT2		(1<<8)
 #define  DP_TP_CTL_LINK_TRAIN_NORMAL	(3<<8)
 
+/* DisplayPort Transport Status */
+#define DP_TP_STATUS_A			0x64044
+#define DP_TP_STATUS_B			0x64144
+#define DP_TP_STATUS(port) _PORT(port, \
+					DP_TP_STATUS_A, \
+					DP_TP_STATUS_B)
+#define  DP_TP_STATUS_AUTOTRAIN_DONE	(1<<12)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.5

[PATCH 10/41] drm/i915: add definitions for DDI_BUF_CTL registers

[Eugeni Dodonov]

There is one instance of those registers for each DDI port.

v2: access registers via the DDI_BUF_CTL() macro

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 666e319..ef99df3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3915,4 +3915,27 @@
 					DP_TP_STATUS_B)
 #define  DP_TP_STATUS_AUTOTRAIN_DONE	(1<<12)
 
+/* DDI Buffer Control */
+#define DDI_BUF_CTL_A				0x64000
+#define DDI_BUF_CTL_B				0x64100
+#define DDI_BUF_CTL(port) _PORT(port, \
+					DDI_BUF_CTL_A, \
+					DDI_BUF_CTL_B)
+#define  DDI_BUF_CTL_ENABLE				(1<<31)
+#define  DDI_BUF_EMP_400MV_0DB_HSW		(0<<24)   /* Sel0 */
+#define  DDI_BUF_EMP_400MV_3_5DB_HSW	(1<<24)   /* Sel1 */
+#define  DDI_BUF_EMP_400MV_6DB_HSW		(2<<24)   /* Sel2 */
+#define  DDI_BUF_EMP_400MV_9_5DB_HSW	(3<<24)   /* Sel3 */
+#define  DDI_BUF_EMP_600MV_0DB_HSW		(4<<24)   /* Sel4 */
+#define  DDI_BUF_EMP_600MV_3_5DB_HSW	(5<<24)   /* Sel5 */
+#define  DDI_BUF_EMP_600MV_6DB_HSW		(6<<24)   /* Sel6 */
+#define  DDI_BUF_EMP_800MV_0DB_HSW		(7<<24)   /* Sel7 */
+#define  DDI_BUF_EMP_800MV_3_5DB_HSW	(8<<24)   /* Sel8 */
+#define  DDI_BUF_EMP_MASK				(0xf<<24)
+#define  DDI_BUF_IS_IDLE				(1<<7)
+#define  DDI_PORT_WIDTH_X1				(0<<1)
+#define  DDI_PORT_WIDTH_X2				(1<<1)
+#define  DDI_PORT_WIDTH_X4				(3<<1)
+#define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.5

[PATCH 11/41] drm/i915: add definition of DDI buffer translations regs

[Eugeni Dodonov]

Those registers are used to train DDI buffer translations for each link
type.

v2: access each port registers through the DDI_BUF_TRANS macro

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ef99df3..880c4f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3938,4 +3938,11 @@
 #define  DDI_PORT_WIDTH_X4				(3<<1)
 #define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
 
+/* DDI Buffer Translations */
+#define DDI_BUF_TRANS_A				0x64E00
+#define DDI_BUF_TRANS_B				0x64E60
+#define DDI_BUF_TRANS(port) _PORT(port, \
+					DDI_BUF_TRANS_A, \
+					DDI_BUF_TRANS_B)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.5

[PATCH 12/41] drm/i915: add definition of LPT FDI port width registers

[Eugeni Dodonov]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 880c4f7..58fcfae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3475,6 +3475,9 @@
 #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2<<8)
 #define  FDI_LINK_TRAIN_NORMAL_CPT		(3<<8)
 #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3<<8)
+/* LPT */
+#define  LPT_FDI_PORT_WIDTH_1X          (0<<19)
+#define  LPT_FDI_PORT_WIDTH_2X          (1<<19)
 
 #define _FDI_RXA_MISC            0xf0010
 #define _FDI_RXB_MISC            0xf1010
-- 
1.7.9.5

Re: [PATCH 12/41] drm/i915: add definition of LPT FDI port width registers

[Daniel Vetter]

On Thu, Mar 29, 2012 at 12:32:28PM -0300, Eugeni Dodonov wrote:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 880c4f7..58fcfae 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3475,6 +3475,9 @@
>  #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2<<8)
>  #define  FDI_LINK_TRAIN_NORMAL_CPT		(3<<8)
>  #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3<<8)
> +/* LPT */
> +#define  LPT_FDI_PORT_WIDTH_1X          (0<<19)
> +#define  LPT_FDI_PORT_WIDTH_2X          (1<<19)

bikeshed: Surounding defines seem to use the _LTP postfix annotation. Also
please sort these in so that the bits are descending.
-Daniel

>  
>  #define _FDI_RXA_MISC            0xf0010
>  #define _FDI_RXB_MISC            0xf1010
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

[PATCH 13/41] drm/i915: add SBI registers

[Eugeni Dodonov]

Those are responsible for the Sideband Interface programming.

v2: rename SBI bits to better reflect their meaning

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 58fcfae..d6c0e36 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3948,4 +3948,16 @@
 					DDI_BUF_TRANS_A, \
 					DDI_BUF_TRANS_B)
 
+/* Sideband Interface (SBI) is programmed indirectly, via
+ * SBI_ADDR, which contains the register offset; and SBI_DATA,
+ * which contains the payload */
+#define SBI_ADDR				0xC6000
+#define SBI_DATA				0xC6004
+#define SBI_CTL_STAT			0xC6008
+#define  SBI_CTL_OP_CRRD		(0x6<<8)
+#define  SBI_CTL_OP_CRWR		(0x7<<8)
+#define  SBI_RESPONSE_FAIL		(0x1<<1)
+#define  SBI_RESPONSE_SUCCESS	(0x0<<1)
+#define  SBI_BUSY				(0x1<<0)
+#define  SBI_READY				(0x0<<0)
 #endif /* _I915_REG_H_ */
-- 
1.7.9.5

[PATCH 14/41] drm/i915: add support for SBI ops

[Eugeni Dodonov]

With Lynx Point, we need to use SBI to communicate with the display clock
control. This commit adds helper functions to access the registers via
SBI.

v2: de-inline the function and address changes in bits names

v1 Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   44 ++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a0e3166..8e5f5be 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1220,6 +1220,50 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	POSTING_READ(reg);
 }
 
+/* SBI access */
+static void
+intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
+{
+	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
+				10))
+		DRM_ERROR("timeout waiting for SBI to become ready\n");
+
+	I915_WRITE(SBI_ADDR,
+			(reg << 16));
+	I915_WRITE(SBI_DATA,
+			value);
+	I915_WRITE(SBI_CTL_STAT,
+			SBI_BUSY |
+			SBI_CTL_OP_CRWR);
+
+	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
+				10))
+		DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
+}
+
+static u32
+intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
+{
+	u32 value;
+	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
+				10))
+		DRM_ERROR("timeout waiting for SBI to become ready\n");
+
+	I915_WRITE(SBI_ADDR,
+			(reg << 16));
+	I915_WRITE(SBI_CTL_STAT,
+			SBI_BUSY |
+			SBI_CTL_OP_CRRD);
+
+	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
+				10))
+		DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
+
+	value = I915_READ(SBI_DATA);
+
+	return value;
+}
+
 /**
  * intel_enable_pch_pll - enable PCH PLL
  * @dev_priv: i915 private structure
-- 
1.7.9.5

Re: [PATCH 14/41] drm/i915: add support for SBI ops

[Daniel Vetter]

On Thu, Mar 29, 2012 at 12:32:30PM -0300, Eugeni Dodonov wrote:
> With Lynx Point, we need to use SBI to communicate with the display clock
> control. This commit adds helper functions to access the registers via
> SBI.
> 
> v2: de-inline the function and address changes in bits names
> 
> v1 Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

The corresponding stuff from vlv is protected by dpio_lock. I think just
for paranoia and consistency it would make sense to do the same in the sbi
read/write helpers. I think you could just reuse the dpio_lock (with
irqsafe spinlock variants).
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c |   44 ++++++++++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a0e3166..8e5f5be 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1220,6 +1220,50 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	POSTING_READ(reg);
>  }
>  
> +/* SBI access */
> +static void
> +intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
> +{
> +	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
> +				10))
> +		DRM_ERROR("timeout waiting for SBI to become ready\n");
> +
> +	I915_WRITE(SBI_ADDR,
> +			(reg << 16));
> +	I915_WRITE(SBI_DATA,
> +			value);
> +	I915_WRITE(SBI_CTL_STAT,
> +			SBI_BUSY |
> +			SBI_CTL_OP_CRWR);
> +
> +	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
> +				10))
> +		DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
> +}
> +
> +static u32
> +intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
> +{
> +	u32 value;
> +	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
> +				10))
> +		DRM_ERROR("timeout waiting for SBI to become ready\n");
> +
> +	I915_WRITE(SBI_ADDR,
> +			(reg << 16));
> +	I915_WRITE(SBI_CTL_STAT,
> +			SBI_BUSY |
> +			SBI_CTL_OP_CRRD);
> +
> +	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
> +				10))
> +		DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
> +
> +	value = I915_READ(SBI_DATA);
> +
> +	return value;
> +}
> +
>  /**
>   * intel_enable_pch_pll - enable PCH PLL
>   * @dev_priv: i915 private structure
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

[PATCH 15/41] drm/i915: add PIXCLK_GATE register

[Eugeni Dodonov]

Pixel clock gating control for Lynx point.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d6c0e36..48346ad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3960,4 +3960,10 @@
 #define  SBI_RESPONSE_SUCCESS	(0x0<<1)
 #define  SBI_BUSY				(0x1<<0)
 #define  SBI_READY				(0x0<<0)
+
+/* LPT PIXCLK_GATE */
+#define PIXCLK_GATE				0xC6020
+#define  PIXCLK_GATE_UNGATE		1<<0
+#define  PIXCLK_GATE_GATE		0<<0
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.5

[PATCH 16/41] drm/i915: add S PLL control

[Eugeni Dodonov]

This PLL control can drive DDI ports at desired frequencies for
DisplayPort and FDI connections.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 48346ad..db03446 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3966,4 +3966,12 @@
 #define  PIXCLK_GATE_UNGATE		1<<0
 #define  PIXCLK_GATE_GATE		0<<0
 
+/* SPLL */
+#define SPLL_CTL				0x46020
+#define  SPLL_PLL_ENABLE		(1<<31)
+#define  SPLL_PLL_SCC			(1<<28)
+#define  SPLL_PLL_NON_SCC		(2<<28)
+#define  SPLL_PLL_FREQ_810MHz	(0<<26)
+#define  SPLL_PLL_FREQ_1350MHz	(1<<26)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.5

[PATCH 17/41] drm/i915: add port clock selection support for HSW

[Eugeni Dodonov]

Multiple clocks can drive different outputs.

v2: use the port enums to access individual ports

v1 Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index db03446..81b076c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3974,4 +3974,27 @@
 #define  SPLL_PLL_FREQ_810MHz	(0<<26)
 #define  SPLL_PLL_FREQ_1350MHz	(1<<26)
 
+/* Port clock selection */
+#define PORT_CLK_SEL_A			0x46100
+#define PORT_CLK_SEL_B			0x46104
+#define PORT_CLK_SEL(port) _PORT(port, \
+					PORT_CLK_SEL_A, \
+					PORT_CLK_SEL_B)
+#define  PORT_CLK_SEL_LCPLL_2700	(0<<29)
+#define  PORT_CLK_SEL_LCPLL_1350	(1<<29)
+#define  PORT_CLK_SEL_LCPLL_810		(2<<29)
+#define  PORT_CLK_SEL_SPLL			(3<<29)
+#define  PORT_CLK_SEL_WRPLL1		(4<<29)
+#define  PORT_CLK_SEL_WRPLL2		(5<<29)
+
+/* Pipe clock selection */
+#define PIPE_CLK_SEL_A			0x46140
+#define PIPE_CLK_SEL_B			0x46144
+#define PIPE_CLK_SEL(pipe) _PIPE(pipe, \
+					PIPE_CLK_SEL_A, \
+					PIPE_CLK_SEL_B)
+/* For each pipe, we need to select the corresponding port clock */
+#define  PIPE_CLK_SEL_DISABLED	(0x0<<29)
+#define  PIPE_CLK_SEL_PORT(x)	((x+1)<<29)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.5

[PATCH 18/41] drm/i915: add SSC offsets for SBI access

[Eugeni Dodonov]

Different registers are identified by their target id and offset. To
simplify their programming, they are called as <RegisterName><TargetId>.
For example, SSCCTL register accessed through SBI at target id 6 and
offset 0c is called SBI_SSCCTL6.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 81b076c..b7eca0c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3961,6 +3961,21 @@
 #define  SBI_BUSY				(0x1<<0)
 #define  SBI_READY				(0x0<<0)
 
+/* SBI offsets */
+#define  SBI_SSCDIVINTPHASE6		0x0600
+#define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	((0x7f)<<1)
+#define   SBI_SSCDIVINTPHASE_DIVSEL(x)		((x)<<1)
+#define   SBI_SSCDIVINTPHASE_INCVAL_MASK	((0x7f)<<8)
+#define   SBI_SSCDIVINTPHASE_INCVAL(x)		((x)<<8)
+#define   SBI_SSCDIVINTPHASE_DIR(x)			((x)<<15)
+#define   SBI_SSCDIVINTPHASE_PROPAGATE		(1<<0)
+#define  SBI_SSCCTL					0x020c
+#define  SBI_SSCCTL6				0x060C
+#define   SBI_SSCCTL_DISABLE		(1<<0)
+#define  SBI_SSCAUXDIV6				0x0610
+#define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x)<<4)
+#define  SBI_DBUFF0					0x2a00
+
 /* LPT PIXCLK_GATE */
 #define PIXCLK_GATE				0xC6020
 #define  PIXCLK_GATE_UNGATE		1<<0
-- 
1.7.9.5

[PATCH 19/41] drm/i915: add LCPLL control registers

[Eugeni Dodonov]

Those are used to control the display core clock.

v2: change the enable bit setting, spotted by Rodrigo Vivi.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b7eca0c..fc24229 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4012,4 +4012,11 @@
 #define  PIPE_CLK_SEL_DISABLED	(0x0<<29)
 #define  PIPE_CLK_SEL_PORT(x)	((x+1)<<29)
 
+/* LCPLL Control */
+#define LCPLL_CTL				0x130040
+#define  LCPLL_PLL_DISABLE		(1<<31)
+#define  LCPLL_PLL_LOCK			(1<<30)
+#define  LCPLL_CD_CLOCK_DISABLE	(1<<25)
+#define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.5

[PATCH 20/41] drm/i915: add WRPLL clocks

[Eugeni Dodonov]

The WR PLL can drive the DDI ports at fixed frequencies for HDMI, DVI, DP
and FDI.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fc24229..7b6754d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3989,6 +3989,14 @@
 #define  SPLL_PLL_FREQ_810MHz	(0<<26)
 #define  SPLL_PLL_FREQ_1350MHz	(1<<26)
 
+/* WRPLL */
+#define WRPLL_CTL1				0x46040
+#define WRPLL_CTL2				0x46060
+#define  WRPLL_PLL_ENABLE				(1<<31)
+#define  WRPLL_PLL_SELECT_SSC			(0x01<<28)
+#define  WRPLL_PLL_SELECT_NON_SCC		(0x02<<28)
+#define  WRPLL_PLL_SELECT_LCPLL_2700	(0x03<<28)
+
 /* Port clock selection */
 #define PORT_CLK_SEL_A			0x46100
 #define PORT_CLK_SEL_B			0x46104
-- 
1.7.9.5

[PATCH 21/41] drm/i915: add WM_LINETIME registers

[Eugeni Dodonov]

Watermark line time registers for display low power watermark.

v2: improve bit names as suggested by Chris Wilson

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7b6754d..d9df228 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4027,4 +4027,14 @@
 #define  LCPLL_CD_CLOCK_DISABLE	(1<<25)
 #define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
 
+/* Pipe WM_LINETIME - watermark line time */
+#define PIPE_WM_LINETIME_A		0x45270
+#define PIPE_WM_LINETIME_B		0x45274
+#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, \
+					PIPE_WM_LINETIME_A, \
+					PIPE_WM_LINETIME_A)
+#define   PIPE_WM_LINETIME_MASK		(0x1ff)
+#define   PIPE_WM_LINETIME_TIME(x)			((x))
+#define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff<<16)
+#define   PIPE_WM_LINETIME_IPS_LINETIME(x)		((x)<<16)
 #endif /* _I915_REG_H_ */
-- 
1.7.9.5

[PATCH 22/41] drm/i915: add SFUSE_STRAP registers for digital port detection

[Eugeni Dodonov]

DDIA is detected via the DDI_BUF_CTL registers bit 0, but for DDIB, DDIC
and DDID we need to consult SFUSE_STRAP values.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d9df228..f300f5f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4037,4 +4037,11 @@
 #define   PIPE_WM_LINETIME_TIME(x)			((x))
 #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff<<16)
 #define   PIPE_WM_LINETIME_IPS_LINETIME(x)		((x)<<16)
+
+/* SFUSE_STRAP */
+#define SFUSE_STRAP				0xc2014
+#define  SFUSE_STRAP_DDIB_DETECTED	(1<<2)
+#define  SFUSE_STRAP_DDIC_DETECTED	(1<<1)
+#define  SFUSE_STRAP_DDID_DETECTED	(1<<0)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.5

Re: [PATCH 22/41] drm/i915: add SFUSE_STRAP registers for digital port detection

[Daniel Vetter]

On Thu, Mar 29, 2012 at 12:32:38PM -0300, Eugeni Dodonov wrote:
> DDIA is detected via the DDI_BUF_CTL registers bit 0, but for DDIB, DDIC
> and DDID we need to consult SFUSE_STRAP values.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d9df228..f300f5f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4037,4 +4037,11 @@
>  #define   PIPE_WM_LINETIME_TIME(x)			((x))
>  #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff<<16)
>  #define   PIPE_WM_LINETIME_IPS_LINETIME(x)		((x)<<16)
> +
> +/* SFUSE_STRAP */
> +#define SFUSE_STRAP				0xc2014
> +#define  SFUSE_STRAP_DDIB_DETECTED	(1<<2)
> +#define  SFUSE_STRAP_DDIC_DETECTED	(1<<1)
> +#define  SFUSE_STRAP_DDID_DETECTED	(1<<0)

I've noticed that we have another sfuse here indicating whether the vga
port is present. Do we not need this?
-Daniel
> +
>  #endif /* _I915_REG_H_ */
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

[PATCH 23/41] drm/i915: calculate same watermarks on Haswell as on Ivy Bridge

[Eugeni Dodonov]

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8e5f5be..5e226ad 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4679,7 +4679,7 @@ void sandybridge_update_wm(struct drm_device *dev)
 	}
 
 	/* IVB has 3 pipes */
-	if (IS_IVYBRIDGE(dev) &&
+	if ((IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) &&
 	    g4x_compute_wm0(dev, 2,
 			    &sandybridge_display_wm_info, latency,
 			    &sandybridge_cursor_wm_info, latency,
-- 
1.7.9.5

[PATCH 24/41] drm/i915: share forcewaking code between IVB and HSW

[Eugeni Dodonov]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5e226ad..1484195 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8924,7 +8924,7 @@ static void intel_init_display(struct drm_device *dev)
 		dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
 
 		/* IVB configs may use multi-threaded forcewake */
-		if (IS_IVYBRIDGE(dev)) {
+		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
 			u32	ecobus;
 
 			/* A small trick here - if the bios hasn't configured MT forcewake,
-- 
1.7.9.5

[PATCH 25/41] drm/i915: haswell has 3 pipes as well

[Eugeni Dodonov]

They work differently, but the count is the same.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index fdff009..1fb7beb 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -2089,7 +2089,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	spin_lock_init(&dev_priv->error_lock);
 	spin_lock_init(&dev_priv->rps_lock);
 
-	if (IS_IVYBRIDGE(dev))
+	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
 		dev_priv->num_pipe = 3;
 	else if (IS_MOBILE(dev) || !IS_GEN2(dev))
 		dev_priv->num_pipe = 2;
-- 
1.7.9.5

[PATCH 26/41] drm/i915: reuse Ivybridge interrupts code for Haswell

[Eugeni Dodonov]

v2: prevent possible conflicts with VLV.

v1 Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 998116e..16e9972 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1795,7 +1795,7 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
 
 	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
 	INIT_WORK(&dev_priv->error_work, i915_error_work_func);
-	if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+	if (IS_GEN6(dev) || IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
 		INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
 
 	I915_WRITE(HWSTAM, 0xeffe);
@@ -2121,7 +2121,7 @@ void intel_irq_init(struct drm_device *dev)
 {
 	dev->driver->get_vblank_counter = i915_get_vblank_counter;
 	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
-	if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
+	if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
 		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
 		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
 	}
@@ -2132,7 +2132,7 @@ void intel_irq_init(struct drm_device *dev)
 		dev->driver->get_vblank_timestamp = NULL;
 	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
 
-	if (IS_IVYBRIDGE(dev)) {
+	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
 		/* Share pre & uninstall handlers with ILK/SNB */
 		dev->driver->irq_handler = ivybridge_irq_handler;
 		dev->driver->irq_preinstall = ironlake_irq_preinstall;
-- 
1.7.9.5

[PATCH 27/41] drm/i915: share pipe count handling with Ivybridge

[Eugeni Dodonov]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1484195..ea103ca 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2330,7 +2330,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 	case 1:
 		break;
 	case 2:
-		if (IS_IVYBRIDGE(dev))
+		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
 			break;
 		/* fall through otherwise */
 	default:
-- 
1.7.9.5

[PATCH 28/41] drm/i915: share IVB cursor routine with Haswell

[Eugeni Dodonov]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ea103ca..7daad41 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6485,7 +6485,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
 	if (!visible && !intel_crtc->cursor_visible)
 		return;
 
-	if (IS_IVYBRIDGE(dev)) {
+	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
 		I915_WRITE(CURPOS_IVB(pipe), pos);
 		ivb_update_cursor(crtc, base);
 	} else {
-- 
1.7.9.5

[PATCH 29/41] drm/i915: show unknown sdvox registers on hdmi init

[Eugeni Dodonov]

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index cae3e5f..de54c01 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -542,6 +542,8 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 		intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
 		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
 		dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
+	} else {
+		DRM_DEBUG_DRIVER("Unknown sdvox register %x\n", sdvox_reg);
 	}
 
 	intel_hdmi->sdvox_reg = sdvox_reg;
-- 
1.7.9.5

[PATCH 30/41] drm/i915: enable power wells on haswell init

[Eugeni Dodonov]

This attempts to enable all the available power wells during the
initialization.

Those power wells can be enabled in parallel or on-demand, and disabled
when no longer needed, but this is out of scope of this initial
enablement. Proper tracking of who uses which power well will require
a considerable rework of our display handling, so we just leave them all
enabled when the driver is loaded for now.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7daad41..0e06a29 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9173,6 +9173,34 @@ static void i915_disable_vga(struct drm_device *dev)
 	POSTING_READ(vga_reg);
 }
 
+/* Starting with Haswell, we have different power wells for
+ * different parts of the GPU. This attempts to enable them all.
+ */
+static void intel_init_power_wells(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long power_wells[] = {
+		HSW_PWR_WELL_CTL1,
+		HSW_PWR_WELL_CTL2,
+		HSW_PWR_WELL_CTL4
+	};
+	int i;
+
+	mutex_lock(&dev->struct_mutex);
+
+	for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
+		int well = I915_READ(power_wells[i]);
+
+		if ((well & HSW_PWR_WELL_STATE) == 0) {
+			I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
+			if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20))
+				DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
+		}
+	}
+
+	mutex_unlock(&dev->struct_mutex);
+}
+
 void intel_modeset_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -9190,6 +9218,9 @@ void intel_modeset_init(struct drm_device *dev)
 
 	intel_init_quirks(dev);
 
+	if (IS_HASWELL(dev))
+		intel_init_power_wells(dev);
+
 	intel_init_display(dev);
 
 	if (IS_GEN2(dev)) {
-- 
1.7.9.5

[PATCH 31/41] drm/i915: disable rc6 on haswell for now

[Eugeni Dodonov]

This needs proper enablement to avoid machine hangs, so let's just avoid
it for now.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0e06a29..b2dc1eb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8293,6 +8293,10 @@ static bool intel_enable_rc6(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen == 5)
 		return 0;
 
+	/* Sorry Haswell, no RC6 for you for now. */
+	if (IS_HASWELL(dev))
+		return 0;
+
 	/*
 	 * Disable rc6 on Sandybridge
 	 */
-- 
1.7.9.5

[PATCH 32/41] drm/i915: program WM_LINETIME on Haswell

[Eugeni Dodonov]

The line time can be programmed according to the number of horizontal
pixels vs effective pixel rate ratio.

v2: improve comment as per Chris Wilson suggestion

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b2dc1eb..72f2211 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6103,6 +6103,19 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		   (adjusted_mode->crtc_vsync_start - 1) |
 		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
 
+	if (IS_HASWELL(dev)) {
+		temp = I915_READ(PIPE_WM_LINETIME(pipe));
+		temp &= ~PIPE_WM_LINETIME_MASK;
+
+		/* The WM are computed with base on how long it takes to fill a single
+		 * row at the given clock rate
+		 * */
+		temp |= PIPE_WM_LINETIME_TIME(
+				adjusted_mode->crtc_hdisplay /
+				(adjusted_mode->clock / 1000));
+		I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
+	}
+
 	/* pipesrc controls the size that is scaled from, which should
 	 * always be the user's requested size.
 	 */
-- 
1.7.9.5

[PATCH 33/41] drm/i915: initialize DDI buffer translations

[Eugeni Dodonov]

Buffer translations for DDI links must be initialized prior to enablement.
For FDI and DP, first 9 pairs of values are used to select the connection
parameters. HDMI uses the last pair of values and ignores the first 9
pairs. So we program HDMI values in both cases, which allows HDMI to work
over both FDI and DP-friendly buffers.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   84 +++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h     |    1 +
 2 files changed, 84 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 72f2211..1fdcd56 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2728,6 +2728,86 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
 	DRM_DEBUG_KMS("FDI train done.\n");
 }
 
+/* HDMI/DVI modes ignore everything but the last 2 items. So we share
+ * them for both DP and FDI transports, allowing those ports to
+ * automatically adapt to HDMI connections as well
+ */
+static const long hsw_ddi_translations_dp[] = {
+	0x00FFFFFF, 0x0006000E,
+	0x00D75FFF, 0x0005000A,
+	0x00C30FFF, 0x00040006,
+	0x80AAAFFF, 0x000B0000,
+	0x00FFFFFF, 0x0005000A,
+	0x00D75FFF, 0x000C0004,
+	0x80C30FFF, 0x000B0000,
+	0x00FFFFFF, 0x00040006,
+	0x80D75FFF, 0x000B0000,
+	0x00FFFFFF, 0x00040006
+};
+
+static const long hsw_ddi_translations_fdi[] = {
+	0x00FFFFFF, 0x0007000E,
+	0x00D75FFF, 0x000F000A,
+	0x00C30FFF, 0x00060006,
+	0x00AAAFFF, 0x001E0000,
+	0x00FFFFFF, 0x000F000A,
+	0x00D75FFF, 0x00160004,
+	0x00C30FFF, 0x001E0000,
+	0x00FFFFFF, 0x00060006,
+	0x00D75FFF, 0x001E0000,
+	0x00FFFFFF, 0x00040006
+};
+
+/* On Haswell, DDI port buffers must be programmed with correct values
+ * in advance. The buffer values are different for FDI and DP modes,
+ * but the HDMI/DVI fields are shared among those. So we program the DDI
+ * in either FDI or DP modes only, as HDMI connections will work with both
+ * of those
+ */
+void hsw_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool use_fdi_mode)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 reg;
+	int i, j;
+
+	DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
+			port_name(port),
+			use_fdi_mode ? "FDI" : "DP");
+
+	WARN((use_fdi_mode && (port != PORT_E)),
+		"Programming port %c in FDI mode, this probably will not work.\n",
+		port_name(port));
+
+	/* Those registers seem to be double-buffered, so write them twice */
+	for (j=0; j < 2; j++) {
+		for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
+			I915_WRITE(reg,
+					(use_fdi_mode) ?
+						hsw_ddi_translations_fdi[i] :
+						hsw_ddi_translations_dp[i]);
+			reg += 4;
+		}
+		udelay(20);
+	}
+}
+
+/* Program DDI buffers translations for DP. By default, program ports A-D in DP
+ * mode and port E for FDI.
+ */
+static void intel_hsw_prepare_ddi_buffers(struct drm_device *dev)
+{
+	int port;
+
+	for (port = PORT_A; port < PORT_E; port++)
+		hsw_prepare_ddi_buffers(dev, port, false);
+
+	/* DDI E is the suggested one to work in FDI mode, so program is as such by
+	 * default. It will have to be re-programmed in case a digital DP output
+	 * will be detected on it
+	 */
+	hsw_prepare_ddi_buffers(dev, PORT_E, true);
+}
+
 /* Manual link training for Ivy Bridge A0 parts */
 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
 {
@@ -9235,8 +9315,10 @@ void intel_modeset_init(struct drm_device *dev)
 
 	intel_init_quirks(dev);
 
-	if (IS_HASWELL(dev))
+	if (IS_HASWELL(dev)) {
 		intel_init_power_wells(dev);
+		intel_hsw_prepare_ddi_buffers(dev);
+	}
 
 	intel_init_display(dev);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9cec6c3..ef1d4ca 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -407,6 +407,7 @@ extern void intel_init_clock_gating(struct drm_device *dev);
 extern void intel_write_eld(struct drm_encoder *encoder,
 			    struct drm_display_mode *mode);
 extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
+extern void hsw_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool use_fdi_mode);
 
 /* For use by IVB LP watermark workaround in intel_sprite.c */
 extern void sandybridge_update_wm(struct drm_device *dev);
-- 
1.7.9.5

[PATCH 34/41] drm/i915: perform Haswell DDI link training in FDI mode

[Eugeni Dodonov]

This patch attempts at following the modeset sequence closely, retrying
with different voltages if the DP_TP_STATUS reports a failed training.

For training, we add a table of recommended settings for FDI, HDMI and DP
connections. For FDI and DP modes, we also add the HDMI buffer
translation as the last item. Those are ignored in such modes, so there is
no harm in having them set.

Initially, we use DDI E for FDI connectivity.  This is the suggested
configuration, and this seems to be what should work the best with FDI.

Note that we leave the DDI Function for corresponding pipe active when we
are done with the training. This ensures that we only need to enable pipe
afterwards to get a working modesetting, in a similar fashion as on
pre-HSW hardware. The modeset disabling sequence mentions a correct order
of disabling things, but this is out of scope of this patch and is being
done separately, for clearer distinction of what happens when.

v2: improve comments a bit, use PORT enums instead of hardcoded PORT_E
registers, split DDI buffers programming into a separate patch.

v1 Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  118 ++++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1fdcd56..09c18f8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2808,6 +2808,113 @@ static void intel_hsw_prepare_ddi_buffers(struct drm_device *dev)
 	hsw_prepare_ddi_buffers(dev, PORT_E, true);
 }
 
+static const long hsw_ddi_buf_ctl_values[] = {
+	DDI_BUF_EMP_400MV_0DB_HSW,
+	DDI_BUF_EMP_400MV_3_5DB_HSW,
+	DDI_BUF_EMP_400MV_6DB_HSW,
+	DDI_BUF_EMP_400MV_9_5DB_HSW,
+	DDI_BUF_EMP_600MV_0DB_HSW,
+	DDI_BUF_EMP_600MV_3_5DB_HSW,
+	DDI_BUF_EMP_600MV_6DB_HSW,
+	DDI_BUF_EMP_800MV_0DB_HSW,
+	DDI_BUF_EMP_800MV_3_5DB_HSW
+};
+
+
+/* Link training for HSW parts */
+static void hsw_fdi_link_train(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	u32 reg, temp, i;
+
+	/* Configure CPU PLL, wait for warmup */
+	I915_WRITE(SPLL_CTL,
+			SPLL_PLL_ENABLE |
+			SPLL_PLL_FREQ_1350MHz |
+			SPLL_PLL_SCC);
+
+	/* Use SPLL to drive the output when in FDI mode */
+	I915_WRITE(PORT_CLK_SEL(PORT_E),
+			PORT_CLK_SEL_SPLL);
+	I915_WRITE(PIPE_CLK_SEL(pipe),
+			PIPE_CLK_SEL_PORT(PORT_E));
+
+	udelay(20);
+
+	/* Start the training iterating through available voltages and emphasis */
+	for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) {
+		/* Configure DP_TP_CTL with auto-training */
+		I915_WRITE(DP_TP_CTL(PORT_E),
+					DP_TP_CTL_FDI_AUTOTRAIN |
+					DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+					DP_TP_CTL_LINK_TRAIN_PAT1 |
+					DP_TP_CTL_ENABLE);
+
+		/* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
+		temp = I915_READ(DDI_BUF_CTL(PORT_E));
+		temp = (temp & ~DDI_BUF_EMP_MASK);
+		I915_WRITE(DDI_BUF_CTL(PORT_E),
+				temp |
+				DDI_BUF_CTL_ENABLE |
+				DDI_PORT_WIDTH_X2 |
+				hsw_ddi_buf_ctl_values[i]);
+
+		udelay(600);
+
+		/* Enable CPU FDI Receiver with auto-training */
+		reg = FDI_RX_CTL(pipe);
+		I915_WRITE(reg,
+				I915_READ(reg) |
+					FDI_LINK_TRAIN_AUTO |
+					FDI_RX_ENABLE |
+					FDI_LINK_TRAIN_PATTERN_1_CPT |
+					FDI_RX_ENHANCE_FRAME_ENABLE |
+					LPT_FDI_PORT_WIDTH_2X |
+					FDI_RX_PLL_ENABLE);
+		POSTING_READ(reg);
+		udelay(100);
+
+		temp = I915_READ(DP_TP_STATUS(PORT_E));
+		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
+			DRM_INFO("BUF_CTL training done on %d step\n", i);
+
+			/* Enable normal pixel sending for FDI */
+			I915_WRITE(DP_TP_CTL(PORT_E),
+						DP_TP_CTL_FDI_AUTOTRAIN |
+						DP_TP_CTL_LINK_TRAIN_NORMAL |
+						DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+						DP_TP_CTL_ENABLE);
+
+			/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in FDI mode */
+			temp = I915_READ(DDI_FUNC_CTL(pipe));
+			temp &= ~PIPE_DDI_PORT_MASK;
+			temp |= PIPE_DDI_SELECT_PORT(PORT_E) |
+					PIPE_DDI_MODE_SELECT_FDI |
+					PIPE_DDI_FUNC_ENABLE |
+					PIPE_DDI_PORT_WIDTH_X2;
+			I915_WRITE(DDI_FUNC_CTL(pipe),
+					temp);
+			break;
+		} else {
+			DRM_ERROR("Error training BUF_CTL %d\n", i);
+
+			/* Disable DP_TP_CTL and FDI_RX_CTL) and retry */
+			I915_WRITE(DP_TP_CTL(PORT_E),
+					I915_READ(DP_TP_CTL(PORT_E)) &
+						~DP_TP_CTL_ENABLE);
+			I915_WRITE(FDI_RX_CTL(pipe),
+					I915_READ(FDI_RX_CTL(pipe)) &
+						~FDI_RX_PLL_ENABLE);
+			continue;
+		}
+	}
+
+	DRM_DEBUG_KMS("FDI train done.\n");
+}
+
 /* Manual link training for Ivy Bridge A0 parts */
 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
 {
@@ -9086,6 +9193,17 @@ static void intel_init_display(struct drm_device *dev)
 			}
 			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
 			dev_priv->display.write_eld = ironlake_write_eld;
+		} else if (IS_HASWELL(dev)) {
+			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
+			if (SNB_READ_WM0_LATENCY()) {
+				dev_priv->display.update_wm = sandybridge_update_wm;
+			} else {
+				DRM_DEBUG_KMS("Failed to read display plane latency. "
+					      "Disable CxSR\n");
+				dev_priv->display.update_wm = NULL;
+			}
+			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
+			dev_priv->display.write_eld = ironlake_write_eld;
 		} else
 			dev_priv->display.update_wm = NULL;
 	} else if (IS_PINEVIEW(dev)) {
-- 
1.7.9.5

[PATCH 35/41] drm/i915: disable pipe DDI function when disabling pipe

[Eugeni Dodonov]

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 09c18f8..0324250 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1475,6 +1475,16 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
 
 	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
 	intel_wait_for_pipe_off(dev_priv->dev, pipe);
+
+	/* On HSW, disable pipe DDI function the pipe */
+	if (IS_HASWELL(dev_priv->dev)) {
+		val = I915_READ(DDI_FUNC_CTL(pipe));
+		val &= ~PIPE_DDI_PORT_MASK;
+		val &= ~PIPE_DDI_FUNC_ENABLE;
+		I915_WRITE(DDI_FUNC_CTL(pipe),
+				val);
+	}
+
 }
 
 /*
-- 
1.7.9.5

[PATCH 36/41] drm/i915: do not use fdi_normal_train on haswell

[Eugeni Dodonov]

This should be already configured when FDI auto-negotiation is done.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0324250..dc207e7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3259,7 +3259,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
 	I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
 
-	intel_fdi_normal_train(crtc);
+	if (!IS_HASWELL(dev))
+		intel_fdi_normal_train(crtc);
 
 	/* For PCH DP, enable TRANS_DP_CTL */
 	if (HAS_PCH_CPT(dev) &&
-- 
1.7.9.5

[PATCH 37/41] drm/i915: program iCLKIP on Lynx Point

[Eugeni Dodonov]

The iCLKIP clock is used to drive the VGA pixel clock on the PCH. In order
to do so, it must be programmed to properly do the clock ticks according
to the divisor, phase direction, phase increments and a special auxiliary
divisor for 20MHz clock.

Those values can be programmed individually, by doing some math; or we
could use a pre-defined table of values for each modeset. For speed and
simplification, the idea was to just adopt the table of valid pixel clocks
and select the matching iCLKIP values from there.

As a possible idea for the future, it would be possible to add a fallback
and calculate those values manually in case no match is found. But I don't
think we'll encounter a mode not covered by those table, and VGA is pretty
much going away in the future anyway.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  309 ++++++++++++++++++++++++++++++++++
 1 file changed, 309 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dc207e7..5aaf592 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2830,6 +2830,312 @@ static const long hsw_ddi_buf_ctl_values[] = {
 	DDI_BUF_EMP_800MV_3_5DB_HSW
 };
 
+/* Available pixel clock values */
+struct iclk_vga_clock {
+	u32 clock;
+	u16 auxdiv;
+	u16 divsel;
+	u16 phasedir;
+	u16 phaseinc;
+};
+
+static const struct iclk_vga_clock iclk_vga_clock_table[] = {
+	{20000,	1,	0x41,	0,	0x20},	/* 20000 ppm=0 */
+	{21000,	0,	0x7E,	0,	0x25},	/* 20999 ppm=-53 */
+	{21912,	0,	0x79,	0,	0x0E},	/* 21912 ppm=12 */
+	{22000,	0,	0x78,	0,	0x2F},	/* 21999 ppm=-58 */
+	{23000,	0,	0x73,	0,	0x19},	/* 23000 ppm=6 */
+	{24000,	0,	0x6E,	0,	0x20},	/* 24000 ppm=0 */
+	{25000,	0,	0x6A,	0,	0x00},	/* 25000 ppm=0 */
+	{25175,	0,	0x69,	0,	0x10},	/* 25175 ppm=-7 */
+	{25200,	0,	0x69,	0,	0x09},	/* 25201 ppm=21 */
+	{26000,	0,	0x66,	1,	0x0A},	/* 26001 ppm=24 */
+	{27000,	0,	0x62,	0,	0x00},	/* 27000 ppm=0 */
+	{27027,	0,	0x62,	1,	0x06},	/* 27025 ppm=-62 */
+	{27500,	0,	0x60,	0,	0x0C},	/* 27498 ppm=-58 */
+	{28000,	0,	0x5E,	0,	0x1B},	/* 28002 ppm=70 */
+	{28320,	0,	0x5D,	0,	0x16},	/* 28319 ppm=-50 */
+	{28322,	0,	0x5D,	0,	0x15},	/* 28323 ppm=44 */
+	{29000,	0,	0x5B,	0,	0x07},	/* 28998 ppm=-64 */
+	{30000,	0,	0x58,	0,	0x00},	/* 30000 ppm=0 */
+	{31000,	0,	0x55,	0,	0x06},	/* 31001 ppm=35 */
+	{31500,	0,	0x54,	1,	0x12},	/* 31498 ppm=-53 */
+	{32000,	0,	0x52,	0,	0x18},	/* 32000 ppm=0 */
+	{32500,	0,	0x51,	0,	0x05},	/* 32500 ppm=-15 */
+	{33000,	0,	0x50,	1,	0x0C},	/* 33002 ppm=70 */
+	{34000,	0,	0x4D,	0,	0x1A},	/* 34002 ppm=70 */
+	{35000,	0,	0x4B,	0,	0x09},	/* 35001 ppm=29 */
+	{35500,	0,	0x4A,	0,	0x04},	/* 35497 ppm=-82 */
+	{36000,	0,	0x49,	0,	0x00},	/* 36000 ppm=0 */
+	{37000,	0,	0x47,	1,	0x02},	/* 37002 ppm=58 */
+	{38000,	0,	0x45,	0,	0x03},	/* 38003 ppm=82 */
+	{39000,	0,	0x43,	0,	0x0F},	/* 38998 ppm=-53 */
+	{40000,	0,	0x41,	0,	0x20},	/* 40000 ppm=0 */
+	{40500,	0,	0x41,	1,	0x15},	/* 40497 ppm=-79 */
+	{40541,	0,	0x41,	1,	0x1A},	/* 40544 ppm=95 */
+	{41000,	0,	0x40,	1,	0x09},	/* 40996 ppm=-87 */
+	{41540,	0,	0x3F,	0,	0x00},	/* 41538 ppm=-38 */
+	{42000,	0,	0x3E,	0,	0x12},	/* 42003 ppm=70 */
+	{43000,	0,	0x3D,	1,	0x0D},	/* 42996 ppm=-99 */
+	{43163,	0,	0x3D,	1,	0x1D},	/* 43168 ppm=108 */
+	{44000,	0,	0x3B,	0,	0x17},	/* 44003 ppm=70 */
+	{44900,	0,	0x3A,	0,	0x09},	/* 44895 ppm=-117 */
+	{45000,	0,	0x3A,	0,	0x00},	/* 45000 ppm=0 */
+	{46000,	0,	0x39,	1,	0x13},	/* 45994 ppm=-128 */
+	{47000,	0,	0x37,	0,	0x1D},	/* 46995 ppm=-110 */
+	{48000,	0,	0x36,	0,	0x10},	/* 48000 ppm=0 */
+	{49000,	0,	0x35,	0,	0x07},	/* 48993 ppm=-134 */
+	{49500,	0,	0x35,	1,	0x1D},	/* 49499 ppm=-27 */
+	{50000,	0,	0x34,	0,	0x00},	/* 50000 ppm=0 */
+	{51000,	0,	0x33,	1,	0x04},	/* 51004 ppm=70 */
+	{52000,	0,	0x32,	1,	0x05},	/* 52001 ppm=24 */
+	{52406,	0,	0x32,	1,	0x1F},	/* 52411 ppm=101 */
+	{53000,	0,	0x31,	1,	0x04},	/* 53006 ppm=116 */
+	{54000,	0,	0x30,	0,	0x00},	/* 54000 ppm=0 */
+	{54054,	0,	0x30,	1,	0x03},	/* 54051 ppm=-62 */
+	{55000,	0,	0x2F,	0,	0x06},	/* 54997 ppm=-58 */
+	{56000,	0,	0x2E,	0,	0x0E},	/* 55995 ppm=-93 */
+	{56250,	0,	0x2E,	0,	0x00},	/* 56250 ppm=0 */
+	{57000,	0,	0x2D,	0,	0x18},	/* 56992 ppm=-139 */
+	{58000,	0,	0x2D,	1,	0x1D},	/* 58006 ppm=105 */
+	{59000,	0,	0x2C,	1,	0x0F},	/* 58996 ppm=-64 */
+	{60000,	0,	0x2B,	0,	0x00},	/* 60000 ppm=0 */
+	{61000,	0,	0x2A,	0,	0x11},	/* 60995 ppm=-76 */
+	{62000,	0,	0x2A,	1,	0x1D},	/* 62002 ppm=35 */
+	{63000,	0,	0x29,	1,	0x09},	/* 62997 ppm=-53 */
+	{64000,	0,	0x28,	0,	0x0C},	/* 64000 ppm=0 */
+	{65000,	0,	0x28,	1,	0x1E},	/* 65011 ppm=174 */
+	{66000,	0,	0x27,	1,	0x06},	/* 66005 ppm=70 */
+	{66667,	0,	0x26,	0,	0x20},	/* 66667 ppm=-5 */
+	{67000,	0,	0x26,	0,	0x13},	/* 67003 ppm=41 */
+	{68000,	0,	0x26,	1,	0x13},	/* 68005 ppm=70 */
+	{68179,	0,	0x26,	1,	0x19},	/* 68166 ppm=-196 */
+	{69000,	0,	0x25,	0,	0x08},	/* 69010 ppm=139 */
+	{70000,	0,	0x25,	1,	0x1B},	/* 69988 ppm=-174 */
+	{71000,	0,	0x24,	0,	0x02},	/* 70994 ppm=-82 */
+	{72000,	0,	0x23,	0,	0x20},	/* 72000 ppm=0 */
+	{73000,	0,	0x23,	1,	0x01},	/* 73004 ppm=53 */
+	{74000,	0,	0x22,	0,	0x1F},	/* 74004 ppm=58 */
+	{74175,	0,	0x22,	0,	0x1A},	/* 74163 ppm=-161 */
+	{74250,	0,	0x22,	0,	0x17},	/* 74259 ppm=118 */
+	{74481,	0,	0x22,	0,	0x10},	/* 74483 ppm=24 */
+	{75000,	0,	0x22,	0,	0x00},	/* 75000 ppm=0 */
+	{76000,	0,	0x22,	1,	0x1E},	/* 75989 ppm=-139 */
+	{77000,	0,	0x21,	0,	0x04},	/* 77005 ppm=70 */
+	{78000,	0,	0x21,	1,	0x19},	/* 78014 ppm=174 */
+	{78750,	0,	0x20,	0,	0x12},	/* 78760 ppm=131 */
+	{79000,	0,	0x20,	0,	0x0B},	/* 79012 ppm=157 */
+	{80000,	0,	0x20,	1,	0x10},	/* 80000 ppm=0 */
+	{81000,	0,	0x1F,	0,	0x15},	/* 81013 ppm=157 */
+	{81081,	0,	0x1F,	0,	0x13},	/* 81089 ppm=95 */
+	{81624,	0,	0x1F,	0,	0x05},	/* 81625 ppm=12 */
+	{82000,	0,	0x1F,	1,	0x05},	/* 82012 ppm=151 */
+	{83000,	0,	0x1F,	1,	0x1E},	/* 82997 ppm=-35 */
+	{83950,	0,	0x1E,	0,	0x0A},	/* 83965 ppm=179 */
+	{84000,	0,	0x1E,	0,	0x09},	/* 84006 ppm=70 */
+	{85000,	0,	0x1E,	1,	0x0F},	/* 84998 ppm=-29 */
+	{86000,	0,	0x1D,	0,	0x19},	/* 86013 ppm=151 */
+	{87000,	0,	0x1D,	0,	0x02},	/* 87009 ppm=105 */
+	{88000,	0,	0x1D,	1,	0x14},	/* 87984 ppm=-186 */
+	{89000,	0,	0x1C,	0,	0x16},	/* 88980 ppm=-220 */
+	{90000,	0,	0x1C,	0,	0x00},	/* 90000 ppm=0 */
+	{91000,	0,	0x1C,	1,	0x15},	/* 90995 ppm=-53 */
+	{92000,	0,	0x1B,	0,	0x16},	/* 92013 ppm=139 */
+	{93000,	0,	0x1B,	0,	0x02},	/* 93003 ppm=35 */
+	{94000,	0,	0x1B,	1,	0x12},	/* 94015 ppm=163 */
+	{94500,	0,	0x1B,	1,	0x1B},	/* 94478 ppm=-235 */
+	{95000,	0,	0x1A,	0,	0x1B},	/* 94997 ppm=-29 */
+	{95654,	0,	0x1A,	0,	0x0F},	/* 95628 ppm=-271 */
+	{96000,	0,	0x1A,	0,	0x08},	/* 96000 ppm=0 */
+	{97000,	0,	0x1A,	1,	0x0B},	/* 97024 ppm=249 */
+	{98000,	0,	0x1A,	1,	0x1D},	/* 98015 ppm=151 */
+	{99000,	0,	0x19,	0,	0x11},	/* 99026 ppm=261 */
+	{100000,	0,	0x19,	0,	0x00},	/* 100000 ppm=0 */
+	{101000,	0,	0x19,	1,	0x11},	/* 100994 ppm=-64 */
+	{102000,	0,	0x18,	0,	0x1E},	/* 102007 ppm=70 */
+	{103000,	0,	0x18,	0,	0x0E},	/* 102980 ppm=-197 */
+	{104000,	0,	0x18,	1,	0x02},	/* 103971 ppm=-278 */
+	{105000,	0,	0x18,	1,	0x12},	/* 104982 ppm=-174 */
+	{106000,	0,	0x17,	0,	0x1E},	/* 106012 ppm=116 */
+	{107000,	0,	0x17,	0,	0x0F},	/* 106997 ppm=-29 */
+	{107214,	0,	0x17,	0,	0x0C},	/* 107196 ppm=-168 */
+	{108000,	0,	0x17,	0,	0x00},	/* 108000 ppm=0 */
+	{109000,	0,	0x17,	1,	0x0F},	/* 109022 ppm=203 */
+	{110000,	0,	0x17,	1,	0x1D},	/* 109994 ppm=-58 */
+	{110013,	0,	0x17,	1,	0x1D},	/* 109994 ppm=-177 */
+	{111000,	0,	0x16,	0,	0x15},	/* 110983 ppm=-157 */
+	{111263,	0,	0x16,	0,	0x11},	/* 111269 ppm=55 */
+	{111375,	0,	0x16,	0,	0x10},	/* 111340 ppm=-313 */
+	{112000,	0,	0x16,	0,	0x07},	/* 111990 ppm=-93 */
+	{113000,	0,	0x16,	1,	0x07},	/* 113015 ppm=134 */
+	{113309,	0,	0x16,	1,	0x0B},	/* 113311 ppm=22 */
+	{113100,	0,	0x16,	1,	0x08},	/* 113089 ppm=-98 */
+	{114000,	0,	0x16,	1,	0x14},	/* 113984 ppm=-139 */
+	{115000,	0,	0x15,	0,	0x1F},	/* 114970 ppm=-261 */
+	{116000,	0,	0x15,	0,	0x12},	/* 115973 ppm=-232 */
+	{117000,	0,	0x15,	0,	0x05},	/* 116994 ppm=-53 */
+	{118000,	0,	0x15,	1,	0x08},	/* 118033 ppm=278 */
+	{119000,	0,	0x15,	1,	0x14},	/* 119008 ppm=70 */
+	{119651,	0,	0x15,	1,	0x1C},	/* 119668 ppm=139 */
+	{120000,	0,	0x14,	0,	0x20},	/* 120000 ppm=0 */
+	{121000,	0,	0x14,	0,	0x14},	/* 121008 ppm=70 */
+	{122000,	0,	0x14,	0,	0x08},	/* 122034 ppm=278 */
+	{122614,	0,	0x14,	0,	0x01},	/* 122640 ppm=214 */
+	{123000,	0,	0x14,	1,	0x03},	/* 122989 ppm=-87 */
+	{123379,	0,	0x14,	1,	0x07},	/* 123340 ppm=-313 */
+	{124000,	0,	0x14,	1,	0x0E},	/* 123960 ppm=-324 */
+	{125000,	0,	0x14,	1,	0x1A},	/* 125036 ppm=290 */
+	{126000,	0,	0x13,	0,	0x1B},	/* 126039 ppm=313 */
+	{127000,	0,	0x13,	0,	0x11},	/* 126965 ppm=-272 */
+	{128000,	0,	0x13,	0,	0x06},	/* 128000 ppm=0 */
+	{129000,	0,	0x13,	1,	0x04},	/* 128955 ppm=-348 */
+	{129859,	0,	0x13,	1,	0x0D},	/* 129827 ppm=-245 */
+	{130000,	0,	0x13,	1,	0x0F},	/* 130023 ppm=174 */
+	{131000,	0,	0x13,	1,	0x19},	/* 131008 ppm=64 */
+	{131850,	0,	0x12,	0,	0x1F},	/* 131808 ppm=-321 */
+	{132000,	0,	0x12,	0,	0x1D},	/* 132009 ppm=70 */
+	{133000,	0,	0x12,	0,	0x13},	/* 133025 ppm=192 */
+	{133330,	0,	0x12,	0,	0x10},	/* 133333 ppm=26 */
+	{134000,	0,	0x12,	0,	0x0A},	/* 133953 ppm=-348 */
+	{135000,	0,	0x12,	0,	0x00},	/* 135000 ppm=0 */
+	{136000,	0,	0x12,	1,	0x09},	/* 135956 ppm=-324 */
+	{137000,	0,	0x12,	1,	0x13},	/* 137034 ppm=249 */
+	{138000,	0,	0x12,	1,	0x1C},	/* 138019 ppm=139 */
+	{139000,	0,	0x11,	0,	0x1B},	/* 139019 ppm=134 */
+	{139050,	0,	0x11,	0,	0x1B},	/* 139019 ppm=-227 */
+	{139054,	0,	0x11,	0,	0x1B},	/* 139019 ppm=-256 */
+	{140000,	0,	0x11,	0,	0x12},	/* 140032 ppm=232 */
+	{141000,	0,	0x11,	0,	0x0A},	/* 140946 ppm=-382 */
+	{142000,	0,	0x11,	0,	0x01},	/* 141988 ppm=-82 */
+	{143000,	0,	0x11,	1,	0x08},	/* 143046 ppm=325 */
+	{143472,	0,	0x11,	1,	0x0C},	/* 143522 ppm=346 */
+	{144000,	0,	0x11,	1,	0x10},	/* 144000 ppm=0 */
+	{145000,	0,	0x11,	1,	0x18},	/* 144966 ppm=-232 */
+	{146000,	0,	0x10,	0,	0x20},	/* 145946 ppm=-371 */
+	{147000,	0,	0x10,	0,	0x18},	/* 146939 ppm=-417 */
+	{147891,	0,	0x10,	0,	0x10},	/* 147945 ppm=367 */
+	{148000,	0,	0x10,	0,	0x10},	/* 147945 ppm=-371 */
+	{148350,	0,	0x10,	0,	0x0D},	/* 148326 ppm=-161 */
+	{148500,	0,	0x10,	0,	0x0C},	/* 148454 ppm=-313 */
+	{149000,	0,	0x10,	0,	0x08},	/* 148966 ppm=-232 */
+	{150000,	0,	0x10,	0,	0x00},	/* 150000 ppm=0 */
+	{151000,	0,	0x10,	1,	0x08},	/* 151049 ppm=325 */
+	{152000,	0,	0x10,	1,	0x0F},	/* 151979 ppm=-139 */
+	{152280,	0,	0x10,	1,	0x11},	/* 152247 ppm=-219 */
+	{153000,	0,	0x10,	1,	0x17},	/* 153056 ppm=365 */
+	{154000,	0,	0x10,	1,	0x1E},	/* 154011 ppm=70 */
+	{155000,	0,	0x0F,	0,	0x1B},	/* 154978 ppm=-145 */
+	{156000,	0,	0x0F,	0,	0x14},	/* 155957 ppm=-278 */
+	{157000,	0,	0x0F,	0,	0x0D},	/* 156948 ppm=-330 */
+	{157500,	0,	0x0F,	0,	0x09},	/* 157521 ppm=131 */
+	{158000,	0,	0x0F,	0,	0x06},	/* 157952 ppm=-301 */
+	{159000,	0,	0x0F,	1,	0x01},	/* 158970 ppm=-191 */
+	{160000,	0,	0x0F,	1,	0x08},	/* 160000 ppm=0 */
+	{161000,	0,	0x0F,	1,	0x0F},	/* 161044 ppm=273 */
+	{162000,	0,	0x0F,	1,	0x15},	/* 161949 ppm=-313 */
+	{163000,	0,	0x0F,	1,	0x1C},	/* 163019 ppm=116 */
+	{164000,	0,	0x0E,	0,	0x1E},	/* 163947 ppm=-324 */
+	{165000,	0,	0x0E,	0,	0x17},	/* 165043 ppm=261 */
+	{166000,	0,	0x0E,	0,	0x11},	/* 165994 ppm=-35 */
+	{167000,	0,	0x0E,	0,	0x0B},	/* 166957 ppm=-261 */
+	{168000,	0,	0x0E,	0,	0x05},	/* 167930 ppm=-417 */
+	{169000,	0,	0x0E,	1,	0x02},	/* 169080 ppm=475 */
+	{169128,	0,	0x0E,	1,	0x02},	/* 169080 ppm=-283 */
+	{170000,	0,	0x0E,	1,	0x08},	/* 170079 ppm=464 */
+	{171000,	0,	0x0E,	1,	0x0D},	/* 170920 ppm=-469 */
+	{172000,	0,	0x0E,	1,	0x13},	/* 171940 ppm=-348 */
+	{172800,	0,	0x0E,	1,	0x18},	/* 172800 ppm=0 */
+	{173000,	0,	0x0E,	1,	0x19},	/* 172973 ppm=-157 */
+	{174000,	0,	0x0E,	1,	0x1F},	/* 174018 ppm=105 */
+	{174787,	0,	0x0D,	0,	0x1D},	/* 174722 ppm=-373 */
+	{175000,	0,	0x0D,	0,	0x1B},	/* 175076 ppm=435 */
+	{175500,	0,	0x0D,	0,	0x19},	/* 175431 ppm=-391 */
+	{176000,	0,	0x0D,	0,	0x16},	/* 175967 ppm=-186 */
+	{177000,	0,	0x0D,	0,	0x10},	/* 177049 ppm=278 */
+	{178000,	0,	0x0D,	0,	0x0B},	/* 177961 ppm=-220 */
+	{179000,	0,	0x0D,	0,	0x05},	/* 179067 ppm=377 */
+	{180000,	0,	0x0D,	0,	0x00},	/* 180000 ppm=0 */
+};
+
+/* Program iCLKIP clock to the desired frequency */
+static void lpt_program_iclkip(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 auxdiv=0, divsel=0, phasedir=0, phaseinc=0, valid=0;
+	u32 temp, i;
+
+	/* Ungate pixel clock */
+	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
+
+	/* Disable SSCCTL */
+	intel_sbi_write(dev_priv, SBI_SSCCTL6,
+				intel_sbi_read(dev_priv, SBI_SSCCTL6) |
+					SBI_SSCCTL_DISABLE);
+
+	/* Calculating clock values for iCLKIP */
+	for (i=0; i < ARRAY_SIZE(iclk_vga_clock_table); i++) {
+		if (crtc->mode.clock == iclk_vga_clock_table[i].clock) {
+			DRM_INFO("Found clock settings for %dKHz refresh rate\n",
+					crtc->mode.clock);
+
+			auxdiv = iclk_vga_clock_table[i].auxdiv;
+			divsel = iclk_vga_clock_table[i].divsel;
+			phasedir = iclk_vga_clock_table[i].phasedir;
+			phaseinc = iclk_vga_clock_table[i].phaseinc;
+
+			valid = 1;
+
+			break;
+		}
+	}
+
+	if (!valid) {
+		DRM_ERROR("Unable to find iCLKIP clock settings for %dKHz refresh rate\n",
+				crtc->mode.clock);
+		return;
+	}
+
+	/* Program SSCDIVINTPHASE6 with values which HW team uses */
+	DRM_DEBUG("Programming SSCDIVINTPHASE for %dKHz: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
+			crtc->mode.clock,
+			auxdiv,
+			divsel,
+			phasedir,
+			phaseinc);
+
+	/* Program SSCDIVINTPHASE6 */
+	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
+	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
+	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
+	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
+	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
+	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
+	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
+
+	intel_sbi_write(dev_priv,
+			SBI_SSCDIVINTPHASE6,
+			temp);
+
+	/* Program SSCAUXDIV */
+	intel_sbi_write(dev_priv,
+			SBI_SSCAUXDIV6,
+				intel_sbi_read(dev_priv, SBI_SSCAUXDIV6) |
+					SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv));
+
+
+	/* Enable modulator and associated divider */
+	intel_sbi_write(dev_priv, SBI_SSCCTL6,
+				intel_sbi_read(dev_priv, SBI_SSCCTL6) &
+					~SBI_SSCCTL_DISABLE);
+
+	/* Wait for initialization time */
+	udelay(50);
+
+	/* Gate pixel clock */
+	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
+}
+
 
 /* Link training for HSW parts */
 static void hsw_fdi_link_train(struct drm_crtc *crtc)
@@ -3246,6 +3552,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 			temp |= (TRANSC_DPLL_ENABLE | transc_sel);
 		}
 		I915_WRITE(PCH_DPLL_SEL, temp);
+	} else if (HAS_PCH_LPT(dev)) {
+		/* Program iCLKIP */
+		lpt_program_iclkip(crtc);
 	}
 
 	/* set transcoder timing, panel must allow it */
-- 
1.7.9.5

[PATCH 38/41] drm/i915: detect digital outputs on Haswell

[Eugeni Dodonov]

Digital port detection on Haswell is indicated by the presence of a bit in
DDI_BUF_CTL for port A, and by a different register for ports B, C and D.
So we check for those bits during the initialization time and let the hdmi
function know about those.

Note that this bit does not indicates whether the output is DP or HDMI.
However, the DDI buffers can be programmed in a way that is shared between
DP/HDMI and FDI/HDMI except for PORT E.

So for now, we detect those digital outputs as being HDMI, but proper DP
support is still pending.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   50 +++++++++++++++++++++++-----------
 1 file changed, 34 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5aaf592..c457592 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8372,26 +8372,44 @@ static void intel_setup_outputs(struct drm_device *dev)
 	if (HAS_PCH_SPLIT(dev)) {
 		int found;
 
-		if (I915_READ(HDMIB) & PORT_DETECTED) {
-			/* PCH SDVOB multiplex with HDMIB */
-			found = intel_sdvo_init(dev, PCH_SDVOB);
-			if (!found)
-				intel_hdmi_init(dev, HDMIB);
-			if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
-				intel_dp_init(dev, PCH_DP_B);
-		}
+		if (IS_HASWELL(dev)) {
+			/* Haswell uses DDI functions to detect digital outputs */
+			found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
+			if (found)
+				intel_hdmi_init(dev, DDI_BUF_CTL_A);
+
+			/* DDI B, C and D detection is indicated by the SFUSE_STRAP
+			 * register */
+			found = I915_READ(SFUSE_STRAP);
+
+			if (found & SFUSE_STRAP_DDIB_DETECTED)
+				intel_hdmi_init(dev, DDI_BUF_CTL(PORT_B));
+			if (found & SFUSE_STRAP_DDIC_DETECTED)
+				intel_hdmi_init(dev, DDI_BUF_CTL(PORT_C));
+			if (found & SFUSE_STRAP_DDID_DETECTED)
+				intel_hdmi_init(dev, DDI_BUF_CTL(PORT_D));
+		} else {
+			if (I915_READ(HDMIB) & PORT_DETECTED) {
+				/* PCH SDVOB multiplex with HDMIB */
+				found = intel_sdvo_init(dev, PCH_SDVOB);
+				if (!found)
+					intel_hdmi_init(dev, HDMIB);
+				if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
+					intel_dp_init(dev, PCH_DP_B);
+			}
 
-		if (I915_READ(HDMIC) & PORT_DETECTED)
-			intel_hdmi_init(dev, HDMIC);
+			if (I915_READ(HDMIC) & PORT_DETECTED)
+				intel_hdmi_init(dev, HDMIC);
 
-		if (I915_READ(HDMID) & PORT_DETECTED)
-			intel_hdmi_init(dev, HDMID);
+			if (I915_READ(HDMID) & PORT_DETECTED)
+				intel_hdmi_init(dev, HDMID);
 
-		if (I915_READ(PCH_DP_C) & DP_DETECTED)
-			intel_dp_init(dev, PCH_DP_C);
+			if (I915_READ(PCH_DP_C) & DP_DETECTED)
+				intel_dp_init(dev, PCH_DP_C);
 
-		if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
-			intel_dp_init(dev, PCH_DP_D);
+			if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
+				intel_dp_init(dev, PCH_DP_D);
+		}
 
 	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
 		bool found = false;
-- 
1.7.9.5

[PATCH 39/41] drm/i915: add support for DDI-controlled digital outputs

[Eugeni Dodonov]

Those are driven by DDIs on Haswell architecture, so we need to keep track
of which DDI is being used on each output.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c |   19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index de54c01..6921756 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -41,6 +41,7 @@ struct intel_hdmi {
 	struct intel_encoder base;
 	u32 sdvox_reg;
 	int ddc_bus;
+	int ddi_port;
 	uint32_t color_range;
 	bool has_hdmi_sink;
 	bool has_audio;
@@ -542,6 +543,24 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 		intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
 		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
 		dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
+	} else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) {
+		DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
+		intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
+		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
+		intel_hdmi->ddi_port = PORT_B;
+		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
+	} else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) {
+		DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
+		intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
+		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
+		intel_hdmi->ddi_port = PORT_C;
+		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
+	} else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) {
+		DRM_DEBUG_DRIVER("LPT: detected output on DDI A\n");
+		intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
+		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
+		intel_hdmi->ddi_port = PORT_D;
+		dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
 	} else {
 		DRM_DEBUG_DRIVER("Unknown sdvox register %x\n", sdvox_reg);
 	}
-- 
1.7.9.5

[PATCH 40/41] drm/i915: prepare HDMI link for Haswell

[Eugeni Dodonov]

On Haswell, we need to properly train the DDI buffers prior to enabling
HDMI.

Note that we do enable the DDI Function for the corresponding pipe, in a
similar fashion as we do with FDI. This ensures that the pipe DDI
transport is left in a almost-ready state, and we only need to enable the
pipe afterwards to get a working modesetting.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c |   63 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 62 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 6921756..480f54b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -324,6 +324,67 @@ static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
 	return true;
 }
 
+static void intel_hdmi_prepare(struct drm_encoder *encoder)
+{
+	struct drm_device *dev = encoder->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc = encoder->crtc;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+	int port = intel_hdmi->ddi_port;
+	int pipe = intel_crtc->pipe;
+	u32 reg, temp;
+
+	/* On Haswell, we need to enable the clocks and prepare DDI function to
+	 * work in HDMI mode for this pipe.
+	 */
+	if (IS_HASWELL(encoder->dev)) {
+		DRM_DEBUG_KMS("Preparing HDMI DDI mode for Haswell on port %c, pipe %c\n", port_name(port), pipe_name(pipe));
+
+		/* Enable LCPLL if disabled */
+		reg = I915_READ(LCPLL_CTL);
+		if (reg & LCPLL_PLL_DISABLE)
+			I915_WRITE(LCPLL_CTL,
+					reg & ~LCPLL_PLL_DISABLE);
+
+		/* Configure CPU PLL, wait for warmup */
+		I915_WRITE(WRPLL_CTL1,
+				WRPLL_PLL_ENABLE |
+				WRPLL_PLL_SELECT_LCPLL_2700);
+
+		udelay(20);
+
+		/* Use WRPLL1 clock to drive the output to the port, and tell the pipe to use
+		 * this port for connection.
+		 */
+		I915_WRITE(PORT_CLK_SEL(port),
+				PORT_CLK_SEL_WRPLL1);
+		I915_WRITE(PIPE_CLK_SEL(pipe),
+				PIPE_CLK_SEL_PORT(port));
+
+		udelay(20);
+
+		/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
+		temp = I915_READ(DDI_FUNC_CTL(pipe));
+		temp &= ~PIPE_DDI_PORT_MASK;
+		temp |= PIPE_DDI_SELECT_PORT(port) |
+				PIPE_DDI_MODE_SELECT_HDMI |
+				PIPE_DDI_FUNC_ENABLE;
+		I915_WRITE(DDI_FUNC_CTL(pipe),
+					temp);
+
+		/* Enable DDI_BUF_CTL. In HDMI/DVI mode, the port width,
+		 * and swing/emphasis values are ignored so nothing special needs
+		 * to be done besides enabling the port.
+		 */
+		I915_WRITE(DDI_BUF_CTL(port),
+				I915_READ(DDI_BUF_CTL(port)) |
+					DDI_BUF_CTL_ENABLE);
+	}
+
+	return intel_encoder_prepare(encoder);
+}
+
 static enum drm_connector_status
 intel_hdmi_detect(struct drm_connector *connector, bool force)
 {
@@ -457,7 +518,7 @@ static void intel_hdmi_destroy(struct drm_connector *connector)
 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
 	.dpms = intel_hdmi_dpms,
 	.mode_fixup = intel_hdmi_mode_fixup,
-	.prepare = intel_encoder_prepare,
+	.prepare = intel_hdmi_prepare,
 	.mode_set = intel_hdmi_mode_set,
 	.commit = intel_encoder_commit,
 };
-- 
1.7.9.5

[PATCH 41/41] drm/i915: add debugging bits for haswell modesetting

[Eugeni Dodonov]

-- THIS PATCH IS NOT INTENDED FOR MERGING. IT IS MERELY HERE TO SIMPLIFY
THE DEBUGGING --

This patch is here for make debugging and log tracing easier, it should
go away in the future, when we'll stop hitting those code paths.

v2: cope with changes in bit names

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c      |    2 ++
 drivers/gpu/drm/i915/intel_display.c |   61 +++++++++++++++++++++++++++-------
 2 files changed, 51 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e4b5571..8ef2512 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1036,6 +1036,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 		val = read##y(dev_priv->regs + reg); \
 	} \
 	trace_i915_reg_rw(false, reg, val, sizeof(val)); \
+	DRM_DEBUG("I915_READ: 0x%x = 0x%x\n", reg, val); \
 	return val; \
 }
 
@@ -1048,6 +1049,7 @@ __i915_read(64, q)
 #define __i915_write(x, y) \
 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
 	u32 __fifo_ret = 0; \
+	DRM_DEBUG("I915_WRITE: 0x%x = 0x%x\n", reg, val); \
 	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
 	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c457592..82afc8a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -869,9 +869,16 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 	u32 val;
 	bool cur_state;
 
-	reg = FDI_TX_CTL(pipe);
-	val = I915_READ(reg);
-	cur_state = !!(val & FDI_TX_ENABLE);
+	if (IS_HASWELL(dev_priv->dev)) {
+		DRM_ERROR("Attempting to check FDI_TX_CTL on Haswell, using DDI instead\n");
+		reg = DDI_FUNC_CTL(pipe);
+		val = I915_READ(reg);
+		cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
+	} else {
+		reg = FDI_TX_CTL(pipe);
+		val = I915_READ(reg);
+		cur_state = !!(val & FDI_TX_ENABLE);
+	}
 	WARN(cur_state != state,
 	     "FDI TX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
@@ -886,9 +893,14 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 	u32 val;
 	bool cur_state;
 
-	reg = FDI_RX_CTL(pipe);
-	val = I915_READ(reg);
-	cur_state = !!(val & FDI_RX_ENABLE);
+	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+			DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
+			return;
+	} else {
+		reg = FDI_RX_CTL(pipe);
+		val = I915_READ(reg);
+		cur_state = !!(val & FDI_RX_ENABLE);
+	}
 	WARN(cur_state != state,
 	     "FDI RX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
@@ -906,6 +918,11 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 	if (dev_priv->info->gen == 5)
 		return;
 
+	if (IS_HASWELL(dev_priv->dev)) {
+		DRM_ERROR("Attempting to check FDI_TX_PLL on Haswell, aborting\n");
+		return;
+	}
+
 	reg = FDI_TX_CTL(pipe);
 	val = I915_READ(reg);
 	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
@@ -917,6 +934,10 @@ static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 	int reg;
 	u32 val;
 
+	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+		DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
+		return;
+	}
 	reg = FDI_RX_CTL(pipe);
 	val = I915_READ(reg);
 	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
@@ -1022,6 +1043,11 @@ static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 	u32 val;
 	bool enabled;
 
+	if (HAS_PCH_LPT(dev_priv->dev)) {
+		DRM_ERROR("LPT does not has PCH refclk, skipping check\n");
+		return;
+	}
+
 	val = I915_READ(PCH_DREF_CONTROL);
 	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 			    DREF_SUPERSPREAD_SOURCE_MASK));
@@ -1236,6 +1262,7 @@ intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
 			SBI_BUSY |
 			SBI_CTL_OP_CRWR);
 
+	DRM_DEBUG("SBI_WRITE: 0x%x = 0x%x\n", reg, value);
 	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
 				10))
 		DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
@@ -1261,6 +1288,7 @@ intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
 
 	value = I915_READ(SBI_DATA);
 
+	DRM_DEBUG("SBI_READ: 0x%x = 0x%x\n", reg, value); \
 	return value;
 }
 
@@ -1345,6 +1373,10 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
 	assert_fdi_tx_enabled(dev_priv, pipe);
 	assert_fdi_rx_enabled(dev_priv, pipe);
 
+	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+		DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
+		return;
+	}
 	reg = TRANSCONF(pipe);
 	val = I915_READ(reg);
 	pipeconf_val = I915_READ(PIPECONF(pipe));
@@ -3376,13 +3408,18 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
 	udelay(200);
 
 	/* Enable CPU FDI TX PLL, always on for Ironlake */
-	reg = FDI_TX_CTL(pipe);
-	temp = I915_READ(reg);
-	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
-		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
+	if (IS_HASWELL(dev)) {
+		DRM_ERROR("Skipping enablement of FDI_TX_PLL on Haswell\n");
+		return;
+	} else {
+		reg = FDI_TX_CTL(pipe);
+		temp = I915_READ(reg);
+		if ((temp & FDI_TX_PLL_ENABLE) == 0) {
+			I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
 
-		POSTING_READ(reg);
-		udelay(100);
+			POSTING_READ(reg);
+			udelay(100);
+		}
 	}
 }
 
-- 
1.7.9.5