* [PATCH 0/6] clk: sunxi: gates support
@ 2013-03-22 14:20 Emilio López
2013-03-22 14:20 ` [PATCH 1/6] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates Emilio López
` (6 more replies)
0 siblings, 7 replies; 37+ messages in thread
From: Emilio López @ 2013-03-22 14:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This patchset adds support for the main sunxi gates; namely, those found
on AXI, AHB, APB0 and APB1 clocks. The series depends on Maxime's UART
rework and on the basic sunxi clock driver by me.
Patches 1 and 2 implement the actual gate support, and patch 3 switches
the UARTs to use the correct gates now that they are available.
Patch 4 and 5 add clock support to our pinctrl driver, as we need to
keep the pio clock running for gpio to work.
Patch 6 drops the ignore flags; now that we have actual clock users that
will keep the important clocks running.
Thanks,
Emilio
Emilio L?pez (6):
clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
arm: sunxi: Add clock definitions for AXI, AHB, APB0, APB1 gates
arm: sunxi: use the right clock phandles for UARTs
pinctrl: sunxi: add clock support
arm: sunxi: Add clock to pinctrl node
clk: sunxi: drop CLK_IGNORE_UNUSED
Documentation/devicetree/bindings/clock/sunxi.txt | 108 +++++++++++++++++++++-
arch/arm/boot/dts/sun4i-a10.dtsi | 13 +--
arch/arm/boot/dts/sun5i-a13.dtsi | 1 +
arch/arm/boot/dts/sunxi.dtsi | 53 ++++++++++-
drivers/clk/sunxi/clk-sunxi.c | 98 +++++++++++++++++++-
drivers/pinctrl/pinctrl-sunxi.c | 8 ++
6 files changed, 267 insertions(+), 14 deletions(-)
--
1.8.2
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 1/6] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
2013-03-22 14:20 [PATCH 0/6] clk: sunxi: gates support Emilio López
@ 2013-03-22 14:20 ` Emilio López
2013-03-25 9:43 ` Maxime Ripard
2013-03-22 14:20 ` [PATCH 2/6] arm: sunxi: Add clock definitions for AXI, AHB, APB0, " Emilio López
` (5 subsequent siblings)
6 siblings, 1 reply; 37+ messages in thread
From: Emilio López @ 2013-03-22 14:20 UTC (permalink / raw)
To: linux-arm-kernel
This patchset adds DT support for all the AXI, AHB, APB0 and APB1
gates present on sunxi SoCs.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 108 +++++++++++++++++++++-
drivers/clk/sunxi/clk-sunxi.c | 90 +++++++++++++++++-
2 files changed, 196 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index b23cfbd..c5432c4 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -10,15 +10,23 @@ Required properties:
"allwinner,sunxi-pll1-clk" - for the main PLL clock
"allwinner,sunxi-cpu-clk" - for the CPU multiplexer clock
"allwinner,sunxi-axi-clk" - for the sunxi AXI clock
+ "allwinner,sunxi-axi-gates-clk" - for the AXI gates
"allwinner,sunxi-ahb-clk" - for the sunxi AHB clock
+ "allwinner,sunxi-ahb-gates-clk" - for the AHB gates
"allwinner,sunxi-apb0-clk" - for the sunxi APB0 clock
+ "allwinner,sunxi-apb0-gates-clk" - for the APB0 gates
"allwinner,sunxi-apb1-clk" - for the sunxi APB1 clock
"allwinner,sunxi-apb1-mux-clk" - for the sunxi APB1 clock muxing
+ "allwinner,sunxi-apb1-gates-clk" - for the APB1 gates
Required properties for all clocks:
- reg : shall be the control register address for the clock.
- clocks : shall be the input parent clock(s) phandle for the clock
-- #clock-cells : from common clock binding; shall be set to 0.
+- #clock-cells : from common clock binding; shall be set to 0 except for
+ "allwinner,sunxi-*-gates-clk" where it shall be set to 1
+
+Additionally, "allwinner,sunxi-*-gates-clk" clocks require:
+- clock-output-names : the corresponding gate names that the clock controls
For example:
@@ -42,3 +50,101 @@ cpu: cpu at 01c20054 {
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>;
};
+
+
+
+Gate clock outputs
+
+The "allwinner,sunxi-*-gates-clk" clocks provide several gatable outputs;
+their corresponding offsets are listed below:
+
+ * AXI gates ("allwinner,sunxi-axi-gates-clk")
+
+ DRAM 0
+
+ * AHB gates ("allwinner,sunxi-ahb-gates-clk")
+
+ USB0 0
+ EHCI0 1
+ OHCI0 2*
+ EHCI1 3
+ OHCI1 4*
+ SS 5
+ DMA 6
+ BIST 7
+ MMC0 8
+ MMC1 9
+ MMC2 10
+ MMC3 11
+ MS 12**
+ NAND 13
+ SDRAM 14
+
+ ACE 16
+ EMAC 17
+ TS 18
+
+ SPI0 20
+ SPI1 21
+ SPI2 22
+ SPI3 23
+ PATA 24
+ SATA 25**
+ GPS 26*
+
+ VE 32
+ TVD 33
+ TVE0 34
+ TVE1 35
+ LCD0 36
+ LCD1 37
+
+ CSI0 40
+ CSI1 41
+
+ HDMI 43
+ DE_BE0 44
+ DE_BE1 45
+ DE_FE0 46
+ DE_FE1 47
+
+ MP 50
+
+ MALI400 52
+
+ * APB0 gates ("allwinner,sunxi-apb0-gates-clk")
+
+ CODEC 0
+ SPDIF 1*
+ AC97 2
+ IIS 3
+
+ PIO 5
+ IR0 6
+ IR1 7
+
+ KEYPAD 10
+
+ * APB1 gates ("allwinner,sunxi-apb1-gates-clk")
+
+ TWI0 0
+ TWI1 1
+ TWI2 2
+
+ CAN 4
+ SCR 5
+ PS20 6
+ PS21 7
+
+ UART0 16
+ UART1 17
+ UART2 18
+ UART3 19
+ UART4 20
+ UART5 21
+ UART6 22
+ UART7 23
+
+Notation:
+ [*]: The datasheet didn't mention these, but they are present on AW code
+ [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index d4ad1c2..30d71f4 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -302,6 +302,82 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
}
+
+/**
+ * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
+ */
+
+#define SUNXI_GATES_MAX_SIZE 64
+
+struct gates_data {
+ DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
+};
+
+static const __initconst struct gates_data axi_gates_data = {
+ .mask = {1},
+};
+
+static const __initconst struct gates_data ahb_gates_data = {
+ .mask = {0x7F77FFF, 0x14FB3F},
+};
+
+static const __initconst struct gates_data apb0_gates_data = {
+ .mask = {0x4EF},
+};
+
+static const __initconst struct gates_data apb1_gates_data = {
+ .mask = {0xFF00F7},
+};
+
+static void __init sunxi_gates_clk_setup(struct device_node *node,
+ struct gates_data *data)
+{
+ struct clk_onecell_data *clk_data;
+ const char *clk_parent;
+ const char *clk_name;
+ void *reg;
+ int qty;
+ int i = 0;
+ int j = 0;
+ int ignore;
+
+ reg = of_iomap(node, 0);
+
+ clk_parent = of_clk_get_parent_name(node, 0);
+
+ /* Worst-case size approximation and memory allocation */
+ qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
+ clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+ if (!clk_data)
+ return;
+ clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
+ if (!clk_data->clks) {
+ kfree(clk_data);
+ return;
+ }
+
+ for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
+ of_property_read_string_index(node, "clock-output-names",
+ j, &clk_name);
+
+ /* No driver claims this clock, but it should remain gated */
+ ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
+
+ clk_data->clks[i] = clk_register_gate(NULL, clk_name,
+ clk_parent, ignore,
+ reg + 4 * (i/32), i % 32,
+ 0, &clk_lock);
+ WARN_ON(IS_ERR(clk_data->clks[i]));
+
+ j++;
+ }
+
+ /* Adjust to the real max */
+ clk_data->clk_num = i;
+
+ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
/* Matches for of_clk_init */
static const __initconst struct of_device_id clk_match[] = {
{.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
@@ -331,6 +407,15 @@ static const __initconst struct of_device_id clk_mux_match[] = {
{}
};
+/* Matches for gate clocks */
+static const __initconst struct of_device_id clk_gates_match[] = {
+ {.compatible = "allwinner,sunxi-axi-gates-clk", .data = &axi_gates_data,},
+ {.compatible = "allwinner,sunxi-ahb-gates-clk", .data = &ahb_gates_data,},
+ {.compatible = "allwinner,sunxi-apb0-gates-clk", .data = &apb0_gates_data,},
+ {.compatible = "allwinner,sunxi-apb1-gates-clk", .data = &apb1_gates_data,},
+ {}
+};
+
static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
void *function)
{
@@ -359,4 +444,7 @@ void __init sunxi_init_clocks(void)
/* Register mux clocks */
of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
+
+ /* Register gate clocks */
+ of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
}
--
1.8.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 2/6] arm: sunxi: Add clock definitions for AXI, AHB, APB0, APB1 gates
2013-03-22 14:20 [PATCH 0/6] clk: sunxi: gates support Emilio López
2013-03-22 14:20 ` [PATCH 1/6] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates Emilio López
@ 2013-03-22 14:20 ` Emilio López
2013-03-22 14:20 ` [PATCH 3/6] arm: sunxi: use the right clock phandles for UARTs Emilio López
` (4 subsequent siblings)
6 siblings, 0 replies; 37+ messages in thread
From: Emilio López @ 2013-03-22 14:20 UTC (permalink / raw)
To: linux-arm-kernel
This commit adds the corresponding DT bindings for all the AXI,
AHB, APB0 and APB1 gates.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
arch/arm/boot/dts/sunxi.dtsi | 49 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
index cafd393..22f0d9d 100644
--- a/arch/arm/boot/dts/sunxi.dtsi
+++ b/arch/arm/boot/dts/sunxi.dtsi
@@ -80,6 +80,14 @@
clocks = <&cpu>;
};
+ axi_gates: axi_gates at 01c2005c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sunxi-axi-gates-clk";
+ reg = <0x01c2005c 0x4>;
+ clocks = <&axi>;
+ clock-output-names = "axi_dram";
+ };
+
ahb: ahb at 01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-ahb-clk";
@@ -87,6 +95,24 @@
clocks = <&axi>;
};
+ ahb_gates: ahb_gates at 01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sunxi-ahb-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb>;
+ clock-output-names = "ahb_usb0", "ahb_ehci0",
+ "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
+ "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+ "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
+ "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
+ "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
+ "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
+ "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
+ "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+ "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+ "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+ };
+
apb0: apb0 at 01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-apb0-clk";
@@ -94,6 +120,16 @@
clocks = <&ahb>;
};
+ apb0_gates: apb0_gates at 01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sunxi-apb0-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_codec", "apb0_spdif",
+ "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
+ "apb0_ir1", "apb0_keypad";
+ };
+
/* dummy is pll62 */
apb1_mux: apb1_mux at 01c20058 {
#clock-cells = <0>;
@@ -108,6 +144,19 @@
reg = <0x01c20058 0x4>;
clocks = <&apb1_mux>;
};
+
+ apb1_gates: apb1_gates at 01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sunxi-apb1-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_twi0", "apb1_twi1",
+ "apb1_twi2", "apb1_can", "apb1_scr",
+ "apb1_ps20", "apb1_ps21", "apb1_uart0",
+ "apb1_uart1", "apb1_uart2", "apb1_uart3",
+ "apb1_uart4", "apb1_uart5", "apb1_uart6",
+ "apb1_uart7";
+ };
};
soc {
--
1.8.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 3/6] arm: sunxi: use the right clock phandles for UARTs
2013-03-22 14:20 [PATCH 0/6] clk: sunxi: gates support Emilio López
2013-03-22 14:20 ` [PATCH 1/6] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates Emilio López
2013-03-22 14:20 ` [PATCH 2/6] arm: sunxi: Add clock definitions for AXI, AHB, APB0, " Emilio López
@ 2013-03-22 14:20 ` Emilio López
2013-03-22 14:20 ` [PATCH 4/6] pinctrl: sunxi: add clock support Emilio López
` (3 subsequent siblings)
6 siblings, 0 replies; 37+ messages in thread
From: Emilio López @ 2013-03-22 14:20 UTC (permalink / raw)
To: linux-arm-kernel
All the UARTs are connected to clock gates; now that our clock driver
is able to handle them, make the switch.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 12 ++++++------
arch/arm/boot/dts/sunxi.dtsi | 4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 68a27fc..6b3a6b2 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -54,7 +54,7 @@
interrupts = <1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 16>;
status = "disabled";
};
@@ -64,7 +64,7 @@
interrupts = <3>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 18>;
status = "disabled";
};
@@ -74,7 +74,7 @@
interrupts = <17>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 20>;
status = "disabled";
};
@@ -84,7 +84,7 @@
interrupts = <18>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 21>;
status = "disabled";
};
@@ -94,7 +94,7 @@
interrupts = <19>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 22>;
status = "disabled";
};
@@ -104,7 +104,7 @@
interrupts = <20>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 23>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
index 22f0d9d..27a4fe2 100644
--- a/arch/arm/boot/dts/sunxi.dtsi
+++ b/arch/arm/boot/dts/sunxi.dtsi
@@ -191,7 +191,7 @@
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 17>;
status = "disabled";
};
@@ -201,7 +201,7 @@
interrupts = <4>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 19>;
status = "disabled";
};
};
--
1.8.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 4/6] pinctrl: sunxi: add clock support
2013-03-22 14:20 [PATCH 0/6] clk: sunxi: gates support Emilio López
` (2 preceding siblings ...)
2013-03-22 14:20 ` [PATCH 3/6] arm: sunxi: use the right clock phandles for UARTs Emilio López
@ 2013-03-22 14:20 ` Emilio López
2013-03-27 13:14 ` Linus Walleij
2013-03-22 14:20 ` [PATCH 5/6] arm: sunxi: Add clock to pinctrl node Emilio López
` (2 subsequent siblings)
6 siblings, 1 reply; 37+ messages in thread
From: Emilio López @ 2013-03-22 14:20 UTC (permalink / raw)
To: linux-arm-kernel
For the port controller to work, we need to enable the apb0_pio gate.
This commit adds the ability to enable one clock specified on the device
tree to the pinctrl driver.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
drivers/pinctrl/pinctrl-sunxi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 3e41cd1..a1e2af7 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -11,6 +11,7 @@
*/
#include <linux/io.h>
+#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -1917,6 +1918,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
struct pinctrl_pin_desc *pins;
struct sunxi_pinctrl *pctl;
int i, ret, last_pin;
+ struct clk *clk;
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
@@ -1987,6 +1989,12 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
goto gpiochip_error;
}
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk))
+ goto gpiochip_error;
+
+ clk_prepare_enable(clk);
+
dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
return 0;
--
1.8.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 5/6] arm: sunxi: Add clock to pinctrl node
2013-03-22 14:20 [PATCH 0/6] clk: sunxi: gates support Emilio López
` (3 preceding siblings ...)
2013-03-22 14:20 ` [PATCH 4/6] pinctrl: sunxi: add clock support Emilio López
@ 2013-03-22 14:20 ` Emilio López
2013-03-22 14:20 ` [PATCH 6/6] clk: sunxi: drop CLK_IGNORE_UNUSED Emilio López
2013-03-27 21:20 ` [PATCH v2 0/6] clk: sunxi: gates support Emilio López
6 siblings, 0 replies; 37+ messages in thread
From: Emilio López @ 2013-03-22 14:20 UTC (permalink / raw)
To: linux-arm-kernel
The port controller needs the apb0_pio clock enabled to be able to
work. This commit declares that on the device tree.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 1 +
arch/arm/boot/dts/sun5i-a13.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 6b3a6b2..f640520 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -21,6 +21,7 @@
pio: pinctrl at 01c20800 {
compatible = "allwinner,sun4i-a10-pinctrl";
reg = <0x01c20800 0x400>;
+ clocks = <&apb0_gates 5>;
gpio-controller;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 945bfac..10ee8ee 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -22,6 +22,7 @@
pio: pinctrl at 01c20800 {
compatible = "allwinner,sun5i-a13-pinctrl";
reg = <0x01c20800 0x400>;
+ clocks = <&apb0_gates 5>;
gpio-controller;
#address-cells = <1>;
#size-cells = <0>;
--
1.8.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 6/6] clk: sunxi: drop CLK_IGNORE_UNUSED
2013-03-22 14:20 [PATCH 0/6] clk: sunxi: gates support Emilio López
` (4 preceding siblings ...)
2013-03-22 14:20 ` [PATCH 5/6] arm: sunxi: Add clock to pinctrl node Emilio López
@ 2013-03-22 14:20 ` Emilio López
2013-03-27 21:20 ` [PATCH v2 0/6] clk: sunxi: gates support Emilio López
6 siblings, 0 replies; 37+ messages in thread
From: Emilio López @ 2013-03-22 14:20 UTC (permalink / raw)
To: linux-arm-kernel
This flag was in place to prevent important clocks from getting gated
while they had no users. Now that the UART driver supports clocks
properly, we can drop this.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
drivers/clk/sunxi/clk-sunxi.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 30d71f4..44c32fc 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -41,8 +41,8 @@ static void __init sunxi_osc_clk_setup(struct device_node *node)
parent = of_clk_get_parent_name(node, 0);
- clk = clk_register_gate(NULL, clk_name, parent, CLK_IGNORE_UNUSED,
- reg, SUNXI_OSC24M_GATE, 0, &clk_lock);
+ clk = clk_register_gate(NULL, clk_name, parent, 0, reg,
+ SUNXI_OSC24M_GATE, 0, &clk_lock);
if (clk) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
@@ -198,8 +198,8 @@ static void __init sunxi_factors_clk_setup(struct device_node *node,
parent = of_clk_get_parent_name(node, 0);
- clk = clk_register_factors(NULL, clk_name, parent, CLK_IGNORE_UNUSED,
- reg, data->table, data->getter, &clk_lock);
+ clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
+ data->table, data->getter, &clk_lock);
if (clk) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
--
1.8.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 1/6] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
2013-03-22 14:20 ` [PATCH 1/6] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates Emilio López
@ 2013-03-25 9:43 ` Maxime Ripard
2013-03-25 10:17 ` Emilio López
0 siblings, 1 reply; 37+ messages in thread
From: Maxime Ripard @ 2013-03-25 9:43 UTC (permalink / raw)
To: linux-arm-kernel
Hi Emilio,
I have a few comments below,
Le 22/03/2013 15:20, Emilio L?pez a ?crit :
> This patchset adds DT support for all the AXI, AHB, APB0 and APB1
> gates present on sunxi SoCs.
>
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
> ---
> Documentation/devicetree/bindings/clock/sunxi.txt | 108 +++++++++++++++++++++-
> drivers/clk/sunxi/clk-sunxi.c | 90 +++++++++++++++++-
> 2 files changed, 196 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index b23cfbd..c5432c4 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -10,15 +10,23 @@ Required properties:
> "allwinner,sunxi-pll1-clk" - for the main PLL clock
> "allwinner,sunxi-cpu-clk" - for the CPU multiplexer clock
> "allwinner,sunxi-axi-clk" - for the sunxi AXI clock
> + "allwinner,sunxi-axi-gates-clk" - for the AXI gates
> "allwinner,sunxi-ahb-clk" - for the sunxi AHB clock
> + "allwinner,sunxi-ahb-gates-clk" - for the AHB gates
> "allwinner,sunxi-apb0-clk" - for the sunxi APB0 clock
> + "allwinner,sunxi-apb0-gates-clk" - for the APB0 gates
> "allwinner,sunxi-apb1-clk" - for the sunxi APB1 clock
> "allwinner,sunxi-apb1-mux-clk" - for the sunxi APB1 clock muxing
> + "allwinner,sunxi-apb1-gates-clk" - for the APB1 gates
It has been pointed to me that the usual way of dealing with compatible
IPs in several generation of SoC in device tree is usually to use the
oldest SoC name to support it, and not some generic term like we use.
I'm currently struggling while doing some work on the A31, where some
IPs differ in a significant way from the A10/A13, and we can't just use
sunxi anymore.
I have a patchset that renames every other IP we have doing this, but
could you rename your compatible strings to allwinner,sun4i* as a first
patch for the already existing clocks, and use that prefix in the
following patches as well? Moreover, since it has been mostly tested on
an A10, if the IP came to differ to some aspect in the A13, it will make
our life easier as well.
>
> Required properties for all clocks:
> - reg : shall be the control register address for the clock.
> - clocks : shall be the input parent clock(s) phandle for the clock
> -- #clock-cells : from common clock binding; shall be set to 0.
> +- #clock-cells : from common clock binding; shall be set to 0 except for
> + "allwinner,sunxi-*-gates-clk" where it shall be set to 1
> +
> +Additionally, "allwinner,sunxi-*-gates-clk" clocks require:
> +- clock-output-names : the corresponding gate names that the clock controls
>
> For example:
>
> @@ -42,3 +50,101 @@ cpu: cpu at 01c20054 {
> reg = <0x01c20054 0x4>;
> clocks = <&osc32k>, <&osc24M>, <&pll1>;
> };
> +
> +
> +
> +Gate clock outputs
> +
> +The "allwinner,sunxi-*-gates-clk" clocks provide several gatable outputs;
> +their corresponding offsets are listed below:
> +
> + * AXI gates ("allwinner,sunxi-axi-gates-clk")
> +
> + DRAM 0
> +
> + * AHB gates ("allwinner,sunxi-ahb-gates-clk")
> +
> + USB0 0
> + EHCI0 1
> + OHCI0 2*
> + EHCI1 3
> + OHCI1 4*
> + SS 5
> + DMA 6
> + BIST 7
> + MMC0 8
> + MMC1 9
> + MMC2 10
> + MMC3 11
> + MS 12**
> + NAND 13
> + SDRAM 14
> +
> + ACE 16
> + EMAC 17
Hmmm, this makes me thinking that I used wemac in the pinctrl driver,
and that it's not really consistent with the datasheet, what you have
here, and what I did in the EMAC driver. I'll need to change that...
> + TS 18
> +
> + SPI0 20
> + SPI1 21
> + SPI2 22
> + SPI3 23
> + PATA 24
> + SATA 25**
> + GPS 26*
> +
> + VE 32
> + TVD 33
> + TVE0 34
> + TVE1 35
> + LCD0 36
> + LCD1 37
> +
> + CSI0 40
> + CSI1 41
> +
> + HDMI 43
> + DE_BE0 44
> + DE_BE1 45
> + DE_FE0 46
> + DE_FE1 47
> +
> + MP 50
> +
> + MALI400 52
> +
> + * APB0 gates ("allwinner,sunxi-apb0-gates-clk")
> +
> + CODEC 0
> + SPDIF 1*
> + AC97 2
> + IIS 3
> +
> + PIO 5
> + IR0 6
> + IR1 7
> +
> + KEYPAD 10
> +
> + * APB1 gates ("allwinner,sunxi-apb1-gates-clk")
> +
> + TWI0 0
> + TWI1 1
> + TWI2 2
I'd rather see here I2C. I know that it's called TWI in the datasheet,
but the term I2C is more commonly used in the kernel.
> + CAN 4
> + SCR 5
> + PS20 6
> + PS21 7
> +
> + UART0 16
> + UART1 17
> + UART2 18
> + UART3 19
> + UART4 20
> + UART5 21
> + UART6 22
> + UART7 23
> +
> +Notation:
> + [*]: The datasheet didn't mention these, but they are present on AW code
> + [**]: The datasheet had this marked as "NC" but they are used on AW code
I'm really happy with the general documentation, thanks for this.
However, all of this is true only for the A10, could you mention it
somewhere?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 1/6] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
2013-03-25 9:43 ` Maxime Ripard
@ 2013-03-25 10:17 ` Emilio López
2013-03-25 11:18 ` Maxime Ripard
0 siblings, 1 reply; 37+ messages in thread
From: Emilio López @ 2013-03-25 10:17 UTC (permalink / raw)
To: linux-arm-kernel
Hi Maxime,
El 25/03/13 06:43, Maxime Ripard escribi?:
> Hi Emilio,
>
> I have a few comments below,
>
> Le 22/03/2013 15:20, Emilio L?pez a ?crit :
>> This patchset adds DT support for all the AXI, AHB, APB0 and APB1
>> gates present on sunxi SoCs.
>>
>> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
>> ---
>> Documentation/devicetree/bindings/clock/sunxi.txt | 108 +++++++++++++++++++++-
>> drivers/clk/sunxi/clk-sunxi.c | 90 +++++++++++++++++-
>> 2 files changed, 196 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index b23cfbd..c5432c4 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -10,15 +10,23 @@ Required properties:
>> "allwinner,sunxi-pll1-clk" - for the main PLL clock
>> "allwinner,sunxi-cpu-clk" - for the CPU multiplexer clock
>> "allwinner,sunxi-axi-clk" - for the sunxi AXI clock
>> + "allwinner,sunxi-axi-gates-clk" - for the AXI gates
>> "allwinner,sunxi-ahb-clk" - for the sunxi AHB clock
>> + "allwinner,sunxi-ahb-gates-clk" - for the AHB gates
>> "allwinner,sunxi-apb0-clk" - for the sunxi APB0 clock
>> + "allwinner,sunxi-apb0-gates-clk" - for the APB0 gates
>> "allwinner,sunxi-apb1-clk" - for the sunxi APB1 clock
>> "allwinner,sunxi-apb1-mux-clk" - for the sunxi APB1 clock muxing
>> + "allwinner,sunxi-apb1-gates-clk" - for the APB1 gates
>
> It has been pointed to me that the usual way of dealing with compatible
> IPs in several generation of SoC in device tree is usually to use the
> oldest SoC name to support it, and not some generic term like we use.
>
> I'm currently struggling while doing some work on the A31, where some
> IPs differ in a significant way from the A10/A13, and we can't just use
> sunxi anymore.
>
> I have a patchset that renames every other IP we have doing this, but
> could you rename your compatible strings to allwinner,sun4i* as a first
> patch for the already existing clocks, and use that prefix in the
> following patches as well? Moreover, since it has been mostly tested on
> an A10, if the IP came to differ to some aspect in the A13, it will make
> our life easier as well.
Ok, I'll do so.
>
>>
>> Required properties for all clocks:
>> - reg : shall be the control register address for the clock.
>> - clocks : shall be the input parent clock(s) phandle for the clock
>> -- #clock-cells : from common clock binding; shall be set to 0.
>> +- #clock-cells : from common clock binding; shall be set to 0 except for
>> + "allwinner,sunxi-*-gates-clk" where it shall be set to 1
>> +
>> +Additionally, "allwinner,sunxi-*-gates-clk" clocks require:
>> +- clock-output-names : the corresponding gate names that the clock controls
>>
>> For example:
>>
>> @@ -42,3 +50,101 @@ cpu: cpu at 01c20054 {
>> reg = <0x01c20054 0x4>;
>> clocks = <&osc32k>, <&osc24M>, <&pll1>;
>> };
>> +
>> +
>> +
>> +Gate clock outputs
>> +
>> +The "allwinner,sunxi-*-gates-clk" clocks provide several gatable outputs;
>> +their corresponding offsets are listed below:
>> +
>> + * AXI gates ("allwinner,sunxi-axi-gates-clk")
>> +
>> + DRAM 0
>> +
>> + * AHB gates ("allwinner,sunxi-ahb-gates-clk")
>> +
>> + USB0 0
>> + EHCI0 1
>> + OHCI0 2*
>> + EHCI1 3
>> + OHCI1 4*
>> + SS 5
>> + DMA 6
>> + BIST 7
>> + MMC0 8
>> + MMC1 9
>> + MMC2 10
>> + MMC3 11
>> + MS 12**
>> + NAND 13
>> + SDRAM 14
>> +
>> + ACE 16
>> + EMAC 17
>
> Hmmm, this makes me thinking that I used wemac in the pinctrl driver,
> and that it's not really consistent with the datasheet, what you have
> here, and what I did in the EMAC driver. I'll need to change that...
>
>> + TS 18
>> +
>> + SPI0 20
>> + SPI1 21
>> + SPI2 22
>> + SPI3 23
>> + PATA 24
>> + SATA 25**
>> + GPS 26*
>> +
>> + VE 32
>> + TVD 33
>> + TVE0 34
>> + TVE1 35
>> + LCD0 36
>> + LCD1 37
>> +
>> + CSI0 40
>> + CSI1 41
>> +
>> + HDMI 43
>> + DE_BE0 44
>> + DE_BE1 45
>> + DE_FE0 46
>> + DE_FE1 47
>> +
>> + MP 50
>> +
>> + MALI400 52
>> +
>> + * APB0 gates ("allwinner,sunxi-apb0-gates-clk")
>> +
>> + CODEC 0
>> + SPDIF 1*
>> + AC97 2
>> + IIS 3
>> +
>> + PIO 5
>> + IR0 6
>> + IR1 7
>> +
>> + KEYPAD 10
>> +
>> + * APB1 gates ("allwinner,sunxi-apb1-gates-clk")
>> +
>> + TWI0 0
>> + TWI1 1
>> + TWI2 2
>
> I'd rather see here I2C. I know that it's called TWI in the datasheet,
> but the term I2C is more commonly used in the kernel.
Ok, I'll change it. Do you want me to rename the gate names on the DT
too to match? ("apb1_twi0" -> "apb1_i2c0")
>
>> + CAN 4
>> + SCR 5
>> + PS20 6
>> + PS21 7
>> +
>> + UART0 16
>> + UART1 17
>> + UART2 18
>> + UART3 19
>> + UART4 20
>> + UART5 21
>> + UART6 22
>> + UART7 23
>> +
>> +Notation:
>> + [*]: The datasheet didn't mention these, but they are present on AW code
>> + [**]: The datasheet had this marked as "NC" but they are used on AW code
>
> I'm really happy with the general documentation, thanks for this.
> However, all of this is true only for the A10, could you mention it
> somewhere?
I could add a note saying so. We could also rename this file to
sun4i.txt and then and add a sun5i.txt with the A13 gate descriptions
too; what would you prefer?
Thanks for the review,
Emilio
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 1/6] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
2013-03-25 10:17 ` Emilio López
@ 2013-03-25 11:18 ` Maxime Ripard
0 siblings, 0 replies; 37+ messages in thread
From: Maxime Ripard @ 2013-03-25 11:18 UTC (permalink / raw)
To: linux-arm-kernel
Le 25/03/2013 11:17, Emilio L?pez a ?crit :
> El 25/03/13 06:43, Maxime Ripard escribi?:
>>> + * APB1 gates ("allwinner,sunxi-apb1-gates-clk")
>>> +
>>> + TWI0 0
>>> + TWI1 1
>>> + TWI2 2
>>
>> I'd rather see here I2C. I know that it's called TWI in the datasheet,
>> but the term I2C is more commonly used in the kernel.
>
> Ok, I'll change it. Do you want me to rename the gate names on the DT
> too to match? ("apb1_twi0" -> "apb1_i2c0")
Yes, it would be nice.
>>> + CAN 4
>>> + SCR 5
>>> + PS20 6
>>> + PS21 7
>>> +
>>> + UART0 16
>>> + UART1 17
>>> + UART2 18
>>> + UART3 19
>>> + UART4 20
>>> + UART5 21
>>> + UART6 22
>>> + UART7 23
>>> +
>>> +Notation:
>>> + [*]: The datasheet didn't mention these, but they are present on AW code
>>> + [**]: The datasheet had this marked as "NC" but they are used on AW code
>>
>> I'm really happy with the general documentation, thanks for this.
>> However, all of this is true only for the A10, could you mention it
>> somewhere?
>
> I could add a note saying so. We could also rename this file to
> sun4i.txt and then and add a sun5i.txt with the A13 gate descriptions
> too; what would you prefer?
>From what we've seen so far, A10 and A13 will share a lot except the
gates in the documentation, so maybe you can keep this sunxi.txt file
with the generic comments, and add a note at the bottom saying to refer
to either sun4i.txt or sun5i.txt files for details.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 4/6] pinctrl: sunxi: add clock support
2013-03-22 14:20 ` [PATCH 4/6] pinctrl: sunxi: add clock support Emilio López
@ 2013-03-27 13:14 ` Linus Walleij
2013-03-27 20:03 ` Maxime Ripard
0 siblings, 1 reply; 37+ messages in thread
From: Linus Walleij @ 2013-03-27 13:14 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Mar 22, 2013 at 3:20 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> For the port controller to work, we need to enable the apb0_pio gate.
> This commit adds the ability to enable one clock specified on the device
> tree to the pinctrl driver.
>
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
I guess you'll want to merge these as one series to some platform-specific
tree, tell me if you want it merged in the pinctrl tree.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 4/6] pinctrl: sunxi: add clock support
2013-03-27 13:14 ` Linus Walleij
@ 2013-03-27 20:03 ` Maxime Ripard
2013-04-03 11:59 ` Linus Walleij
0 siblings, 1 reply; 37+ messages in thread
From: Maxime Ripard @ 2013-03-27 20:03 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
Le 27/03/2013 14:14, Linus Walleij a ?crit :
> On Fri, Mar 22, 2013 at 3:20 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
>
>> For the port controller to work, we need to enable the apb0_pio gate.
>> This commit adds the ability to enable one clock specified on the device
>> tree to the pinctrl driver.
>>
>> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> I guess you'll want to merge these as one series to some platform-specific
> tree, tell me if you want it merged in the pinctrl tree.
The easiest would probably be to merge this patch through your patch,
with Mike taking the clock driver patches and me taking the dt ones,
once we agree on the other patches.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v2 0/6] clk: sunxi: gates support
2013-03-22 14:20 [PATCH 0/6] clk: sunxi: gates support Emilio López
` (5 preceding siblings ...)
2013-03-22 14:20 ` [PATCH 6/6] clk: sunxi: drop CLK_IGNORE_UNUSED Emilio López
@ 2013-03-27 21:20 ` Emilio López
2013-03-27 21:20 ` [PATCH v2 1/7] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates Emilio López
` (8 more replies)
6 siblings, 9 replies; 37+ messages in thread
From: Emilio López @ 2013-03-27 21:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This patchset adds support for the main sunxi gates; namely, those found
on AXI, AHB, APB0 and APB1 clocks. The series depends on Maxime's UART
rework and on the basic sunxi clock driver by me.
Patches 1 and 2 implement the actual gate support, and patch 3 switches
the UARTs to use the correct gates now that they are available.
Patch 4 and 5 add clock support to our pinctrl driver, as we need to
keep the pio clock running for gpio to work.
Patch 6 drops the ignore flags; now that we have actual clock users that
will keep the important clocks running.
Patch 7 is an unrelated oneliner to remove an unnecesary kmalloc call.
The main changes from v1 are renamed compatible strings and a clarification
on the documentation, see each individual patch for more details.
Thanks,
Emilio
Emilio L?pez (7):
clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
arm: sunxi: Add clock definitions for AXI, AHB, APB0, APB1 gates
arm: sunxi: use the right clock phandles for UARTs
pinctrl: sunxi: add clock support
arm: sunxi: Add clock to pinctrl node
clk: sunxi: drop CLK_IGNORE_UNUSED
clk: sunxi: drop an unnecesary kmalloc
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v2 1/7] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
2013-03-27 21:20 ` [PATCH v2 0/6] clk: sunxi: gates support Emilio López
@ 2013-03-27 21:20 ` Emilio López
2013-04-03 21:48 ` Mike Turquette
2013-03-27 21:20 ` [PATCH v2 2/7] arm: sunxi: Add clock definitions for AXI, AHB, APB0, " Emilio López
` (7 subsequent siblings)
8 siblings, 1 reply; 37+ messages in thread
From: Emilio López @ 2013-03-27 21:20 UTC (permalink / raw)
To: linux-arm-kernel
This patchset adds DT support for all the AXI, AHB, APB0 and APB1
gates present on sunxi SoCs.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
Changes from v1:
- renamed compatibles to sun4i
- renamed TWI -> I2C
- added note about gate availability on sun5i
Documentation/devicetree/bindings/clock/sunxi.txt | 109 +++++++++++++++++++++-
drivers/clk/sunxi/clk-sunxi.c | 88 +++++++++++++++++
2 files changed, 196 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 20b8479..729f524 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -10,15 +10,23 @@ Required properties:
"allwinner,sun4i-pll1-clk" - for the main PLL clock
"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
"allwinner,sun4i-axi-clk" - for the AXI clock
+ "allwinner,sun4i-axi-gates-clk" - for the AXI gates
"allwinner,sun4i-ahb-clk" - for the AHB clock
+ "allwinner,sun4i-ahb-gates-clk" - for the AHB gates
"allwinner,sun4i-apb0-clk" - for the APB0 clock
+ "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
"allwinner,sun4i-apb1-clk" - for the APB1 clock
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
+ "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
Required properties for all clocks:
- reg : shall be the control register address for the clock.
- clocks : shall be the input parent clock(s) phandle for the clock
-- #clock-cells : from common clock binding; shall be set to 0.
+- #clock-cells : from common clock binding; shall be set to 0 except for
+ "allwinner,sun4i-*-gates-clk" where it shall be set to 1
+
+Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
+- clock-output-names : the corresponding gate names that the clock controls
For example:
@@ -42,3 +50,102 @@ cpu: cpu at 01c20054 {
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>;
};
+
+
+
+Gate clock outputs
+
+The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
+their corresponding offsets as present on sun4i are listed below. Note that
+some of these gates are not present on sun5i.
+
+ * AXI gates ("allwinner,sun4i-axi-gates-clk")
+
+ DRAM 0
+
+ * AHB gates ("allwinner,sun4i-ahb-gates-clk")
+
+ USB0 0
+ EHCI0 1
+ OHCI0 2*
+ EHCI1 3
+ OHCI1 4*
+ SS 5
+ DMA 6
+ BIST 7
+ MMC0 8
+ MMC1 9
+ MMC2 10
+ MMC3 11
+ MS 12**
+ NAND 13
+ SDRAM 14
+
+ ACE 16
+ EMAC 17
+ TS 18
+
+ SPI0 20
+ SPI1 21
+ SPI2 22
+ SPI3 23
+ PATA 24
+ SATA 25**
+ GPS 26*
+
+ VE 32
+ TVD 33
+ TVE0 34
+ TVE1 35
+ LCD0 36
+ LCD1 37
+
+ CSI0 40
+ CSI1 41
+
+ HDMI 43
+ DE_BE0 44
+ DE_BE1 45
+ DE_FE0 46
+ DE_FE1 47
+
+ MP 50
+
+ MALI400 52
+
+ * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
+
+ CODEC 0
+ SPDIF 1*
+ AC97 2
+ IIS 3
+
+ PIO 5
+ IR0 6
+ IR1 7
+
+ KEYPAD 10
+
+ * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
+
+ I2C0 0
+ I2C1 1
+ I2C2 2
+
+ CAN 4
+ SCR 5
+ PS20 6
+ PS21 7
+
+ UART0 16
+ UART1 17
+ UART2 18
+ UART3 19
+ UART4 20
+ UART5 21
+ UART6 22
+ UART7 23
+
+Notation:
+ [*]: The datasheet didn't mention these, but they are present on AW code
+ [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index d528a24..244de90 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -302,6 +302,82 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
}
+
+/**
+ * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
+ */
+
+#define SUNXI_GATES_MAX_SIZE 64
+
+struct gates_data {
+ DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
+};
+
+static const __initconst struct gates_data axi_gates_data = {
+ .mask = {1},
+};
+
+static const __initconst struct gates_data ahb_gates_data = {
+ .mask = {0x7F77FFF, 0x14FB3F},
+};
+
+static const __initconst struct gates_data apb0_gates_data = {
+ .mask = {0x4EF},
+};
+
+static const __initconst struct gates_data apb1_gates_data = {
+ .mask = {0xFF00F7},
+};
+
+static void __init sunxi_gates_clk_setup(struct device_node *node,
+ struct gates_data *data)
+{
+ struct clk_onecell_data *clk_data;
+ const char *clk_parent;
+ const char *clk_name;
+ void *reg;
+ int qty;
+ int i = 0;
+ int j = 0;
+ int ignore;
+
+ reg = of_iomap(node, 0);
+
+ clk_parent = of_clk_get_parent_name(node, 0);
+
+ /* Worst-case size approximation and memory allocation */
+ qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
+ clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+ if (!clk_data)
+ return;
+ clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
+ if (!clk_data->clks) {
+ kfree(clk_data);
+ return;
+ }
+
+ for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
+ of_property_read_string_index(node, "clock-output-names",
+ j, &clk_name);
+
+ /* No driver claims this clock, but it should remain gated */
+ ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
+
+ clk_data->clks[i] = clk_register_gate(NULL, clk_name,
+ clk_parent, ignore,
+ reg + 4 * (i/32), i % 32,
+ 0, &clk_lock);
+ WARN_ON(IS_ERR(clk_data->clks[i]));
+
+ j++;
+ }
+
+ /* Adjust to the real max */
+ clk_data->clk_num = i;
+
+ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
/* Matches for of_clk_init */
static const __initconst struct of_device_id clk_match[] = {
{.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
@@ -331,6 +407,15 @@ static const __initconst struct of_device_id clk_mux_match[] = {
{}
};
+/* Matches for gate clocks */
+static const __initconst struct of_device_id clk_gates_match[] = {
+ {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &axi_gates_data,},
+ {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &ahb_gates_data,},
+ {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &apb0_gates_data,},
+ {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &apb1_gates_data,},
+ {}
+};
+
static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
void *function)
{
@@ -359,4 +444,7 @@ void __init sunxi_init_clocks(void)
/* Register mux clocks */
of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
+
+ /* Register gate clocks */
+ of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
}
--
1.8.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v2 2/7] arm: sunxi: Add clock definitions for AXI, AHB, APB0, APB1 gates
2013-03-27 21:20 ` [PATCH v2 0/6] clk: sunxi: gates support Emilio López
2013-03-27 21:20 ` [PATCH v2 1/7] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates Emilio López
@ 2013-03-27 21:20 ` Emilio López
2013-03-27 21:20 ` [PATCH v2 3/7] arm: sunxi: use the right clock phandles for UARTs Emilio López
` (6 subsequent siblings)
8 siblings, 0 replies; 37+ messages in thread
From: Emilio López @ 2013-03-27 21:20 UTC (permalink / raw)
To: linux-arm-kernel
This commit adds the corresponding DT bindings for all the AXI,
AHB, APB0 and APB1 gates.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
Changes from v1:
- renamed compatible strings to sun4i
- rename twi gates to i2c
arch/arm/boot/dts/sunxi.dtsi | 49 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
index 40392de..87b2cce 100644
--- a/arch/arm/boot/dts/sunxi.dtsi
+++ b/arch/arm/boot/dts/sunxi.dtsi
@@ -80,6 +80,14 @@
clocks = <&cpu>;
};
+ axi_gates: axi_gates at 01c2005c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-axi-gates-clk";
+ reg = <0x01c2005c 0x4>;
+ clocks = <&axi>;
+ clock-output-names = "axi_dram";
+ };
+
ahb: ahb at 01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-ahb-clk";
@@ -87,6 +95,24 @@
clocks = <&axi>;
};
+ ahb_gates: ahb_gates at 01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-ahb-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb>;
+ clock-output-names = "ahb_usb0", "ahb_ehci0",
+ "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
+ "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+ "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
+ "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
+ "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
+ "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
+ "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
+ "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+ "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+ "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+ };
+
apb0: apb0 at 01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb0-clk";
@@ -94,6 +120,16 @@
clocks = <&ahb>;
};
+ apb0_gates: apb0_gates at 01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-apb0-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_codec", "apb0_spdif",
+ "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
+ "apb0_ir1", "apb0_keypad";
+ };
+
/* dummy is pll62 */
apb1_mux: apb1_mux at 01c20058 {
#clock-cells = <0>;
@@ -108,6 +144,19 @@
reg = <0x01c20058 0x4>;
clocks = <&apb1_mux>;
};
+
+ apb1_gates: apb1_gates at 01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-apb1-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_i2c0", "apb1_i2c1",
+ "apb1_i2c2", "apb1_can", "apb1_scr",
+ "apb1_ps20", "apb1_ps21", "apb1_uart0",
+ "apb1_uart1", "apb1_uart2", "apb1_uart3",
+ "apb1_uart4", "apb1_uart5", "apb1_uart6",
+ "apb1_uart7";
+ };
};
soc {
--
1.8.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v2 3/7] arm: sunxi: use the right clock phandles for UARTs
2013-03-27 21:20 ` [PATCH v2 0/6] clk: sunxi: gates support Emilio López
2013-03-27 21:20 ` [PATCH v2 1/7] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates Emilio López
2013-03-27 21:20 ` [PATCH v2 2/7] arm: sunxi: Add clock definitions for AXI, AHB, APB0, " Emilio López
@ 2013-03-27 21:20 ` Emilio López
2013-03-27 21:20 ` [PATCH v2 4/7] pinctrl: sunxi: add clock support Emilio López
` (5 subsequent siblings)
8 siblings, 0 replies; 37+ messages in thread
From: Emilio López @ 2013-03-27 21:20 UTC (permalink / raw)
To: linux-arm-kernel
All the UARTs are connected to clock gates; now that our clock driver
is able to handle them, make the switch.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
Changes from v1:
- no changes
arch/arm/boot/dts/sun4i-a10.dtsi | 12 ++++++------
arch/arm/boot/dts/sunxi.dtsi | 4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 68a27fc..6b3a6b2 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -54,7 +54,7 @@
interrupts = <1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 16>;
status = "disabled";
};
@@ -64,7 +64,7 @@
interrupts = <3>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 18>;
status = "disabled";
};
@@ -74,7 +74,7 @@
interrupts = <17>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 20>;
status = "disabled";
};
@@ -84,7 +84,7 @@
interrupts = <18>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 21>;
status = "disabled";
};
@@ -94,7 +94,7 @@
interrupts = <19>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 22>;
status = "disabled";
};
@@ -104,7 +104,7 @@
interrupts = <20>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 23>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
index 87b2cce..a8d47e2 100644
--- a/arch/arm/boot/dts/sunxi.dtsi
+++ b/arch/arm/boot/dts/sunxi.dtsi
@@ -191,7 +191,7 @@
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 17>;
status = "disabled";
};
@@ -201,7 +201,7 @@
interrupts = <4>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb1_gates 19>;
status = "disabled";
};
};
--
1.8.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v2 4/7] pinctrl: sunxi: add clock support
2013-03-27 21:20 ` [PATCH v2 0/6] clk: sunxi: gates support Emilio López
` (2 preceding siblings ...)
2013-03-27 21:20 ` [PATCH v2 3/7] arm: sunxi: use the right clock phandles for UARTs Emilio López
@ 2013-03-27 21:20 ` Emilio López
2013-03-27 21:20 ` [PATCH v2 5/7] arm: sunxi: Add clock to pinctrl node Emilio López
` (4 subsequent siblings)
8 siblings, 0 replies; 37+ messages in thread
From: Emilio López @ 2013-03-27 21:20 UTC (permalink / raw)
To: linux-arm-kernel
For the port controller to work, we need to enable the apb0_pio gate.
This commit adds the ability to enable one clock specified on the device
tree to the pinctrl driver.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
Changes from v1:
- no changes
drivers/pinctrl/pinctrl-sunxi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 3e41cd1..a1e2af7 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -11,6 +11,7 @@
*/
#include <linux/io.h>
+#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -1917,6 +1918,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
struct pinctrl_pin_desc *pins;
struct sunxi_pinctrl *pctl;
int i, ret, last_pin;
+ struct clk *clk;
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
@@ -1987,6 +1989,12 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
goto gpiochip_error;
}
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk))
+ goto gpiochip_error;
+
+ clk_prepare_enable(clk);
+
dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
return 0;
--
1.8.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v2 5/7] arm: sunxi: Add clock to pinctrl node
2013-03-27 21:20 ` [PATCH v2 0/6] clk: sunxi: gates support Emilio López
` (3 preceding siblings ...)
2013-03-27 21:20 ` [PATCH v2 4/7] pinctrl: sunxi: add clock support Emilio López
@ 2013-03-27 21:20 ` Emilio López
2013-03-27 21:20 ` [PATCH v2 6/7] clk: sunxi: drop CLK_IGNORE_UNUSED Emilio López
` (3 subsequent siblings)
8 siblings, 0 replies; 37+ messages in thread
From: Emilio López @ 2013-03-27 21:20 UTC (permalink / raw)
To: linux-arm-kernel
The port controller needs the apb0_pio clock enabled to be able to
work. This commit declares that on the device tree.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
Changes from v1:
- no changes
arch/arm/boot/dts/sun4i-a10.dtsi | 1 +
arch/arm/boot/dts/sun5i-a13.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 6b3a6b2..f640520 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -21,6 +21,7 @@
pio: pinctrl at 01c20800 {
compatible = "allwinner,sun4i-a10-pinctrl";
reg = <0x01c20800 0x400>;
+ clocks = <&apb0_gates 5>;
gpio-controller;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 945bfac..10ee8ee 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -22,6 +22,7 @@
pio: pinctrl at 01c20800 {
compatible = "allwinner,sun5i-a13-pinctrl";
reg = <0x01c20800 0x400>;
+ clocks = <&apb0_gates 5>;
gpio-controller;
#address-cells = <1>;
#size-cells = <0>;
--
1.8.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v2 6/7] clk: sunxi: drop CLK_IGNORE_UNUSED
2013-03-27 21:20 ` [PATCH v2 0/6] clk: sunxi: gates support Emilio López
` (4 preceding siblings ...)
2013-03-27 21:20 ` [PATCH v2 5/7] arm: sunxi: Add clock to pinctrl node Emilio López
@ 2013-03-27 21:20 ` Emilio López
2013-04-03 21:48 ` Mike Turquette
2013-03-27 21:20 ` [PATCH v2 7/7] clk: sunxi: drop an unnecesary kmalloc Emilio López
` (2 subsequent siblings)
8 siblings, 1 reply; 37+ messages in thread
From: Emilio López @ 2013-03-27 21:20 UTC (permalink / raw)
To: linux-arm-kernel
This flag was in place to prevent important clocks from getting gated
while they had no users. Now that the UART driver supports clocks
properly, we can drop this.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
Changes from v1:
- no changes
drivers/clk/sunxi/clk-sunxi.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 244de90..daa51ab 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -41,8 +41,8 @@ static void __init sunxi_osc_clk_setup(struct device_node *node)
parent = of_clk_get_parent_name(node, 0);
- clk = clk_register_gate(NULL, clk_name, parent, CLK_IGNORE_UNUSED,
- reg, SUNXI_OSC24M_GATE, 0, &clk_lock);
+ clk = clk_register_gate(NULL, clk_name, parent, 0, reg,
+ SUNXI_OSC24M_GATE, 0, &clk_lock);
if (clk) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
@@ -198,8 +198,8 @@ static void __init sunxi_factors_clk_setup(struct device_node *node,
parent = of_clk_get_parent_name(node, 0);
- clk = clk_register_factors(NULL, clk_name, parent, CLK_IGNORE_UNUSED,
- reg, data->table, data->getter, &clk_lock);
+ clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
+ data->table, data->getter, &clk_lock);
if (clk) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
--
1.8.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v2 7/7] clk: sunxi: drop an unnecesary kmalloc
2013-03-27 21:20 ` [PATCH v2 0/6] clk: sunxi: gates support Emilio López
` (5 preceding siblings ...)
2013-03-27 21:20 ` [PATCH v2 6/7] clk: sunxi: drop CLK_IGNORE_UNUSED Emilio López
@ 2013-03-27 21:20 ` Emilio López
2013-04-03 21:49 ` Mike Turquette
2013-04-03 21:45 ` [PATCH v2 0/6] clk: sunxi: gates support Mike Turquette
2013-04-04 22:01 ` Maxime Ripard
8 siblings, 1 reply; 37+ messages in thread
From: Emilio López @ 2013-03-27 21:20 UTC (permalink / raw)
To: linux-arm-kernel
clk_register will copy this information, so we can just use a normal
array and do one less dynamic allocation.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
Changes from v1:
- this patch was not present on v1
drivers/clk/sunxi/clk-sunxi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index daa51ab..0bb0eb4 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -232,7 +232,7 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
{
struct clk *clk;
const char *clk_name = node->name;
- const char **parents = kmalloc(sizeof(char *) * 5, GFP_KERNEL);
+ const char *parents[5];
void *reg;
int i = 0;
--
1.8.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 4/6] pinctrl: sunxi: add clock support
2013-03-27 20:03 ` Maxime Ripard
@ 2013-04-03 11:59 ` Linus Walleij
2013-04-03 21:20 ` Maxime Ripard
0 siblings, 1 reply; 37+ messages in thread
From: Linus Walleij @ 2013-04-03 11:59 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Mar 27, 2013 at 9:03 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi Linus,
> Le 27/03/2013 14:14, Linus Walleij a ?crit :
>> On Fri, Mar 22, 2013 at 3:20 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
>>
>>> For the port controller to work, we need to enable the apb0_pio gate.
>>> This commit adds the ability to enable one clock specified on the device
>>> tree to the pinctrl driver.
>>>
>>> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
>>
>> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>>
>> I guess you'll want to merge these as one series to some platform-specific
>> tree, tell me if you want it merged in the pinctrl tree.
>
> The easiest would probably be to merge this patch through your patch,
> with Mike taking the clock driver patches and me taking the dt ones,
> once we agree on the other patches.
OK then, patch applied to the pinctrl tree, thanks!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 4/6] pinctrl: sunxi: add clock support
2013-04-03 11:59 ` Linus Walleij
@ 2013-04-03 21:20 ` Maxime Ripard
2013-04-04 0:49 ` Mike Turquette
2013-04-04 11:37 ` Linus Walleij
0 siblings, 2 replies; 37+ messages in thread
From: Maxime Ripard @ 2013-04-03 21:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
Le 03/04/2013 13:59, Linus Walleij a ?crit :
> On Wed, Mar 27, 2013 at 9:03 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
>
>> Hi Linus,
>> Le 27/03/2013 14:14, Linus Walleij a ?crit :
>>> On Fri, Mar 22, 2013 at 3:20 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
>>>
>>>> For the port controller to work, we need to enable the apb0_pio gate.
>>>> This commit adds the ability to enable one clock specified on the device
>>>> tree to the pinctrl driver.
>>>>
>>>> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
>>>
>>> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>>>
>>> I guess you'll want to merge these as one series to some platform-specific
>>> tree, tell me if you want it merged in the pinctrl tree.
>>
>> The easiest would probably be to merge this patch through your patch,
>> with Mike taking the clock driver patches and me taking the dt ones,
>> once we agree on the other patches.
>
> OK then, patch applied to the pinctrl tree, thanks!
Ouch, the previous patches aren't applied yet by Mike, and we didn't
have some comments from him about these patches, so I can't really say
if the previous patches will get merge by 3.10 or not... So we will
maybe end up with a broken pinctrl stuff.
Mike, do you have some comments on Emilio's patches?
If you do, we can still fix things up later by applying a slightly
modified version of patches 5/6 with a clock that is already there, for
it to load properly.
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v2 0/6] clk: sunxi: gates support
2013-03-27 21:20 ` [PATCH v2 0/6] clk: sunxi: gates support Emilio López
` (6 preceding siblings ...)
2013-03-27 21:20 ` [PATCH v2 7/7] clk: sunxi: drop an unnecesary kmalloc Emilio López
@ 2013-04-03 21:45 ` Mike Turquette
2013-04-03 22:13 ` Emilio López
2013-04-04 5:52 ` Maxime Ripard
2013-04-04 22:01 ` Maxime Ripard
8 siblings, 2 replies; 37+ messages in thread
From: Mike Turquette @ 2013-04-03 21:45 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Emilio L?pez (2013-03-27 14:20:36)
> Hi,
>
> This patchset adds support for the main sunxi gates; namely, those found
> on AXI, AHB, APB0 and APB1 clocks. The series depends on Maxime's UART
> rework and on the basic sunxi clock driver by me.
>
> Patches 1 and 2 implement the actual gate support, and patch 3 switches
> the UARTs to use the correct gates now that they are available.
>
> Patch 4 and 5 add clock support to our pinctrl driver, as we need to
> keep the pio clock running for gpio to work.
>
> Patch 6 drops the ignore flags; now that we have actual clock users that
> will keep the important clocks running.
>
> Patch 7 is an unrelated oneliner to remove an unnecesary kmalloc call.
>
> The main changes from v1 are renamed compatible strings and a clarification
> on the documentation, see each individual patch for more details.
>
Hi Emilio,
Which tree(s) did you want these patches to go through?
Regards,
Mike
> Thanks,
>
> Emilio
>
> Emilio L?pez (7):
> clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
> arm: sunxi: Add clock definitions for AXI, AHB, APB0, APB1 gates
> arm: sunxi: use the right clock phandles for UARTs
> pinctrl: sunxi: add clock support
> arm: sunxi: Add clock to pinctrl node
> clk: sunxi: drop CLK_IGNORE_UNUSED
> clk: sunxi: drop an unnecesary kmalloc
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v2 1/7] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
2013-03-27 21:20 ` [PATCH v2 1/7] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates Emilio López
@ 2013-04-03 21:48 ` Mike Turquette
2013-04-04 1:19 ` Emilio López
0 siblings, 1 reply; 37+ messages in thread
From: Mike Turquette @ 2013-04-03 21:48 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Emilio L?pez (2013-03-27 14:20:37)
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index d528a24..244de90 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -302,6 +302,82 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
> }
>
>
> +
A lot of white space between these functions.
> +/**
> + * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
> + */
> +
> +#define SUNXI_GATES_MAX_SIZE 64
> +
> +struct gates_data {
> + DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
> +};
> +
> +static const __initconst struct gates_data axi_gates_data = {
> + .mask = {1},
> +};
> +
> +static const __initconst struct gates_data ahb_gates_data = {
> + .mask = {0x7F77FFF, 0x14FB3F},
> +};
> +
> +static const __initconst struct gates_data apb0_gates_data = {
> + .mask = {0x4EF},
> +};
> +
> +static const __initconst struct gates_data apb1_gates_data = {
> + .mask = {0xFF00F7},
> +};
> +
> +static void __init sunxi_gates_clk_setup(struct device_node *node,
> + struct gates_data *data)
> +{
> + struct clk_onecell_data *clk_data;
> + const char *clk_parent;
> + const char *clk_name;
> + void *reg;
> + int qty;
> + int i = 0;
> + int j = 0;
> + int ignore;
> +
> + reg = of_iomap(node, 0);
> +
> + clk_parent = of_clk_get_parent_name(node, 0);
> +
> + /* Worst-case size approximation and memory allocation */
> + qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
> + clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
> + if (!clk_data)
> + return;
> + clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
> + if (!clk_data->clks) {
> + kfree(clk_data);
> + return;
> + }
> +
> + for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
> + of_property_read_string_index(node, "clock-output-names",
> + j, &clk_name);
> +
> + /* No driver claims this clock, but it should remain gated */
Should the comment read, "ungated" instead of "gated"?
> + ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
> +
> + clk_data->clks[i] = clk_register_gate(NULL, clk_name,
> + clk_parent, ignore,
> + reg + 4 * (i/32), i % 32,
> + 0, &clk_lock);
> + WARN_ON(IS_ERR(clk_data->clks[i]));
> +
> + j++;
> + }
> +
> + /* Adjust to the real max */
> + clk_data->clk_num = i;
> +
> + of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> /* Matches for of_clk_init */
> static const __initconst struct of_device_id clk_match[] = {
> {.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
> @@ -331,6 +407,15 @@ static const __initconst struct of_device_id clk_mux_match[] = {
> {}
> };
>
> +/* Matches for gate clocks */
> +static const __initconst struct of_device_id clk_gates_match[] = {
> + {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &axi_gates_data,},
> + {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &ahb_gates_data,},
> + {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &apb0_gates_data,},
> + {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &apb1_gates_data,},
> + {}
> +};
> +
> static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
> void *function)
> {
> @@ -359,4 +444,7 @@ void __init sunxi_init_clocks(void)
>
> /* Register mux clocks */
> of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
> +
> + /* Register gate clocks */
> + of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
I'm still a device tree noob, so this may be a dumb question. Can the
above be converted to of_clk_init?
Regards,
Mike
> }
> --
> 1.8.2
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v2 6/7] clk: sunxi: drop CLK_IGNORE_UNUSED
2013-03-27 21:20 ` [PATCH v2 6/7] clk: sunxi: drop CLK_IGNORE_UNUSED Emilio López
@ 2013-04-03 21:48 ` Mike Turquette
0 siblings, 0 replies; 37+ messages in thread
From: Mike Turquette @ 2013-04-03 21:48 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Emilio L?pez (2013-03-27 14:20:42)
> This flag was in place to prevent important clocks from getting gated
> while they had no users. Now that the UART driver supports clocks
> properly, we can drop this.
>
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
This change looks good to me.
Regards,
Mike
> ---
>
> Changes from v1:
> - no changes
>
> drivers/clk/sunxi/clk-sunxi.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 244de90..daa51ab 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -41,8 +41,8 @@ static void __init sunxi_osc_clk_setup(struct device_node *node)
>
> parent = of_clk_get_parent_name(node, 0);
>
> - clk = clk_register_gate(NULL, clk_name, parent, CLK_IGNORE_UNUSED,
> - reg, SUNXI_OSC24M_GATE, 0, &clk_lock);
> + clk = clk_register_gate(NULL, clk_name, parent, 0, reg,
> + SUNXI_OSC24M_GATE, 0, &clk_lock);
>
> if (clk) {
> of_clk_add_provider(node, of_clk_src_simple_get, clk);
> @@ -198,8 +198,8 @@ static void __init sunxi_factors_clk_setup(struct device_node *node,
>
> parent = of_clk_get_parent_name(node, 0);
>
> - clk = clk_register_factors(NULL, clk_name, parent, CLK_IGNORE_UNUSED,
> - reg, data->table, data->getter, &clk_lock);
> + clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
> + data->table, data->getter, &clk_lock);
>
> if (clk) {
> of_clk_add_provider(node, of_clk_src_simple_get, clk);
> --
> 1.8.2
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v2 7/7] clk: sunxi: drop an unnecesary kmalloc
2013-03-27 21:20 ` [PATCH v2 7/7] clk: sunxi: drop an unnecesary kmalloc Emilio López
@ 2013-04-03 21:49 ` Mike Turquette
0 siblings, 0 replies; 37+ messages in thread
From: Mike Turquette @ 2013-04-03 21:49 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Emilio L?pez (2013-03-27 14:20:43)
> clk_register will copy this information, so we can just use a normal
> array and do one less dynamic allocation.
>
> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
Looks good to me.
Regards,
Mike
> ---
>
> Changes from v1:
> - this patch was not present on v1
>
> drivers/clk/sunxi/clk-sunxi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index daa51ab..0bb0eb4 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -232,7 +232,7 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
> {
> struct clk *clk;
> const char *clk_name = node->name;
> - const char **parents = kmalloc(sizeof(char *) * 5, GFP_KERNEL);
> + const char *parents[5];
> void *reg;
> int i = 0;
>
> --
> 1.8.2
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v2 0/6] clk: sunxi: gates support
2013-04-03 21:45 ` [PATCH v2 0/6] clk: sunxi: gates support Mike Turquette
@ 2013-04-03 22:13 ` Emilio López
2013-04-04 5:52 ` Maxime Ripard
1 sibling, 0 replies; 37+ messages in thread
From: Emilio López @ 2013-04-03 22:13 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mike,
El 03/04/13 18:45, Mike Turquette escribi?:
> Quoting Emilio L?pez (2013-03-27 14:20:36)
>> Hi,
>>
>> This patchset adds support for the main sunxi gates; namely, those found
>> on AXI, AHB, APB0 and APB1 clocks. The series depends on Maxime's UART
>> rework and on the basic sunxi clock driver by me.
>>
>> Patches 1 and 2 implement the actual gate support, and patch 3 switches
>> the UARTs to use the correct gates now that they are available.
>>
>> Patch 4 and 5 add clock support to our pinctrl driver, as we need to
>> keep the pio clock running for gpio to work.
>>
>> Patch 6 drops the ignore flags; now that we have actual clock users that
>> will keep the important clocks running.
>>
>> Patch 7 is an unrelated oneliner to remove an unnecesary kmalloc call.
>>
>> The main changes from v1 are renamed compatible strings and a clarification
>> on the documentation, see each individual patch for more details.
>>
>
> Hi Emilio,
>
> Which tree(s) did you want these patches to go through?
The rest of the clk driver is on your tree, so I think 1, 6 and 7 should
go through there too, unless Maxime has any objection.
Thanks,
Emilio
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 4/6] pinctrl: sunxi: add clock support
2013-04-03 21:20 ` Maxime Ripard
@ 2013-04-04 0:49 ` Mike Turquette
2013-04-04 11:37 ` Linus Walleij
1 sibling, 0 replies; 37+ messages in thread
From: Mike Turquette @ 2013-04-04 0:49 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Maxime Ripard (2013-04-03 14:20:37)
> Hi Linus,
>
> Le 03/04/2013 13:59, Linus Walleij a ?crit :
> > On Wed, Mar 27, 2013 at 9:03 PM, Maxime Ripard
> > <maxime.ripard@free-electrons.com> wrote:
> >
> >> Hi Linus,
> >> Le 27/03/2013 14:14, Linus Walleij a ?crit :
> >>> On Fri, Mar 22, 2013 at 3:20 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> >>>
> >>>> For the port controller to work, we need to enable the apb0_pio gate.
> >>>> This commit adds the ability to enable one clock specified on the device
> >>>> tree to the pinctrl driver.
> >>>>
> >>>> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
> >>>
> >>> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> >>>
> >>> I guess you'll want to merge these as one series to some platform-specific
> >>> tree, tell me if you want it merged in the pinctrl tree.
> >>
> >> The easiest would probably be to merge this patch through your patch,
> >> with Mike taking the clock driver patches and me taking the dt ones,
> >> once we agree on the other patches.
> >
> > OK then, patch applied to the pinctrl tree, thanks!
>
> Ouch, the previous patches aren't applied yet by Mike, and we didn't
> have some comments from him about these patches, so I can't really say
> if the previous patches will get merge by 3.10 or not... So we will
> maybe end up with a broken pinctrl stuff.
>
> Mike, do you have some comments on Emilio's patches?
>
> If you do, we can still fix things up later by applying a slightly
> modified version of patches 5/6 with a clock that is already there, for
> it to load properly.
>
Hi Maxime,
I did leave some comments a few hours ago. It would be better if the
fixes could be rolled in now, but if that is somehow impossible then I
don't mind taking them as-is with fixes at a later date. Just let me
know.
Regards,
Mike
> Thanks,
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v2 1/7] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
2013-04-03 21:48 ` Mike Turquette
@ 2013-04-04 1:19 ` Emilio López
2013-04-04 2:46 ` Mike Turquette
0 siblings, 1 reply; 37+ messages in thread
From: Emilio López @ 2013-04-04 1:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mike,
El 03/04/13 18:48, Mike Turquette escribi?:
> Quoting Emilio L?pez (2013-03-27 14:20:37)
>> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>> index d528a24..244de90 100644
>> --- a/drivers/clk/sunxi/clk-sunxi.c
>> +++ b/drivers/clk/sunxi/clk-sunxi.c
>> @@ -302,6 +302,82 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
>> }
>>
>>
>> +
>
> A lot of white space between these functions.
All of the function blocks are separated with three spaces on the file;
I thought it looked more readable that way, but I don't have any strong
opinion on separation. Is there any standard for this used on the kernel?
In any case, and to keep consistency, can we handle this on a follow-up
patch?
>> +/**
>> + * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
>> + */
>> +
>> +#define SUNXI_GATES_MAX_SIZE 64
>> +
>> +struct gates_data {
>> + DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
>> +};
>> +
>> +static const __initconst struct gates_data axi_gates_data = {
>> + .mask = {1},
>> +};
>> +
>> +static const __initconst struct gates_data ahb_gates_data = {
>> + .mask = {0x7F77FFF, 0x14FB3F},
>> +};
>> +
>> +static const __initconst struct gates_data apb0_gates_data = {
>> + .mask = {0x4EF},
>> +};
>> +
>> +static const __initconst struct gates_data apb1_gates_data = {
>> + .mask = {0xFF00F7},
>> +};
>> +
>> +static void __init sunxi_gates_clk_setup(struct device_node *node,
>> + struct gates_data *data)
>> +{
>> + struct clk_onecell_data *clk_data;
>> + const char *clk_parent;
>> + const char *clk_name;
>> + void *reg;
>> + int qty;
>> + int i = 0;
>> + int j = 0;
>> + int ignore;
>> +
>> + reg = of_iomap(node, 0);
>> +
>> + clk_parent = of_clk_get_parent_name(node, 0);
>> +
>> + /* Worst-case size approximation and memory allocation */
>> + qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
>> + clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
>> + if (!clk_data)
>> + return;
>> + clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
>> + if (!clk_data->clks) {
>> + kfree(clk_data);
>> + return;
>> + }
>> +
>> + for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
>> + of_property_read_string_index(node, "clock-output-names",
>> + j, &clk_name);
>> +
>> + /* No driver claims this clock, but it should remain gated */
>
> Should the comment read, "ungated" instead of "gated"?
Indeed, good catch. Do you want me to resend the series, or can you
amend this when picking the patches?
>> + ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
>> +
>> + clk_data->clks[i] = clk_register_gate(NULL, clk_name,
>> + clk_parent, ignore,
>> + reg + 4 * (i/32), i % 32,
>> + 0, &clk_lock);
>> + WARN_ON(IS_ERR(clk_data->clks[i]));
>> +
>> + j++;
>> + }
>> +
>> + /* Adjust to the real max */
>> + clk_data->clk_num = i;
>> +
>> + of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
>> +}
>> +
>> /* Matches for of_clk_init */
>> static const __initconst struct of_device_id clk_match[] = {
>> {.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
>> @@ -331,6 +407,15 @@ static const __initconst struct of_device_id clk_mux_match[] = {
>> {}
>> };
>>
>> +/* Matches for gate clocks */
>> +static const __initconst struct of_device_id clk_gates_match[] = {
>> + {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &axi_gates_data,},
>> + {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &ahb_gates_data,},
>> + {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &apb0_gates_data,},
>> + {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &apb1_gates_data,},
>> + {}
>> +};
>> +
>> static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
>> void *function)
>> {
>> @@ -359,4 +444,7 @@ void __init sunxi_init_clocks(void)
>>
>> /* Register mux clocks */
>> of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
>> +
>> + /* Register gate clocks */
>> + of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
>
> I'm still a device tree noob, so this may be a dumb question. Can the
> above be converted to of_clk_init?
As far as I know, you can't, because of_clk_init doesn't allow for
custom data to be passed to the functions. If we were to use of_clk_init
we would need one function per clock, and it would be mostly duplicated
code / wrappers. I've added Gregory on Cc, please correct me if this is
not the case.
Thanks for the review,
Emilio
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v2 1/7] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
2013-04-04 1:19 ` Emilio López
@ 2013-04-04 2:46 ` Mike Turquette
2013-04-04 20:45 ` Gregory CLEMENT
0 siblings, 1 reply; 37+ messages in thread
From: Mike Turquette @ 2013-04-04 2:46 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Emilio L?pez (2013-04-03 18:19:22)
> Hi Mike,
>
> El 03/04/13 18:48, Mike Turquette escribi?:
> > Quoting Emilio L?pez (2013-03-27 14:20:37)
> >> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> >> index d528a24..244de90 100644
> >> --- a/drivers/clk/sunxi/clk-sunxi.c
> >> +++ b/drivers/clk/sunxi/clk-sunxi.c
> >> @@ -302,6 +302,82 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
> >> }
> >>
> >>
> >> +
> >
> > A lot of white space between these functions.
>
> All of the function blocks are separated with three spaces on the file;
> I thought it looked more readable that way, but I don't have any strong
> opinion on separation. Is there any standard for this used on the kernel?
>
> In any case, and to keep consistency, can we handle this on a follow-up
> patch?
>
If it's consistent throughout the file then go ahead and keep it.
> >> +/**
> >> + * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
> >> + */
> >> +
> >> +#define SUNXI_GATES_MAX_SIZE 64
> >> +
> >> +struct gates_data {
> >> + DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
> >> +};
> >> +
> >> +static const __initconst struct gates_data axi_gates_data = {
> >> + .mask = {1},
> >> +};
> >> +
> >> +static const __initconst struct gates_data ahb_gates_data = {
> >> + .mask = {0x7F77FFF, 0x14FB3F},
> >> +};
> >> +
> >> +static const __initconst struct gates_data apb0_gates_data = {
> >> + .mask = {0x4EF},
> >> +};
> >> +
> >> +static const __initconst struct gates_data apb1_gates_data = {
> >> + .mask = {0xFF00F7},
> >> +};
> >> +
> >> +static void __init sunxi_gates_clk_setup(struct device_node *node,
> >> + struct gates_data *data)
> >> +{
> >> + struct clk_onecell_data *clk_data;
> >> + const char *clk_parent;
> >> + const char *clk_name;
> >> + void *reg;
> >> + int qty;
> >> + int i = 0;
> >> + int j = 0;
> >> + int ignore;
> >> +
> >> + reg = of_iomap(node, 0);
> >> +
> >> + clk_parent = of_clk_get_parent_name(node, 0);
> >> +
> >> + /* Worst-case size approximation and memory allocation */
> >> + qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
> >> + clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
> >> + if (!clk_data)
> >> + return;
> >> + clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
> >> + if (!clk_data->clks) {
> >> + kfree(clk_data);
> >> + return;
> >> + }
> >> +
> >> + for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
> >> + of_property_read_string_index(node, "clock-output-names",
> >> + j, &clk_name);
> >> +
> >> + /* No driver claims this clock, but it should remain gated */
> >
> > Should the comment read, "ungated" instead of "gated"?
>
> Indeed, good catch. Do you want me to resend the series, or can you
> amend this when picking the patches?
>
I can amend it, but I don't like to get into the habit of doing that too
often.
I'll wait on Gregory's response on the of_clk_init stuff before I do so.
Regards,
Mike
> >> + ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
> >> +
> >> + clk_data->clks[i] = clk_register_gate(NULL, clk_name,
> >> + clk_parent, ignore,
> >> + reg + 4 * (i/32), i % 32,
> >> + 0, &clk_lock);
> >> + WARN_ON(IS_ERR(clk_data->clks[i]));
> >> +
> >> + j++;
> >> + }
> >> +
> >> + /* Adjust to the real max */
> >> + clk_data->clk_num = i;
> >> +
> >> + of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> >> +}
> >> +
> >> /* Matches for of_clk_init */
> >> static const __initconst struct of_device_id clk_match[] = {
> >> {.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
> >> @@ -331,6 +407,15 @@ static const __initconst struct of_device_id clk_mux_match[] = {
> >> {}
> >> };
> >>
> >> +/* Matches for gate clocks */
> >> +static const __initconst struct of_device_id clk_gates_match[] = {
> >> + {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &axi_gates_data,},
> >> + {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &ahb_gates_data,},
> >> + {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &apb0_gates_data,},
> >> + {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &apb1_gates_data,},
> >> + {}
> >> +};
> >> +
> >> static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
> >> void *function)
> >> {
> >> @@ -359,4 +444,7 @@ void __init sunxi_init_clocks(void)
> >>
> >> /* Register mux clocks */
> >> of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
> >> +
> >> + /* Register gate clocks */
> >> + of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
> >
> > I'm still a device tree noob, so this may be a dumb question. Can the
> > above be converted to of_clk_init?
>
> As far as I know, you can't, because of_clk_init doesn't allow for
> custom data to be passed to the functions. If we were to use of_clk_init
> we would need one function per clock, and it would be mostly duplicated
> code / wrappers. I've added Gregory on Cc, please correct me if this is
> not the case.
>
> Thanks for the review,
>
> Emilio
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v2 0/6] clk: sunxi: gates support
2013-04-03 21:45 ` [PATCH v2 0/6] clk: sunxi: gates support Mike Turquette
2013-04-03 22:13 ` Emilio López
@ 2013-04-04 5:52 ` Maxime Ripard
1 sibling, 0 replies; 37+ messages in thread
From: Maxime Ripard @ 2013-04-04 5:52 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mike
Le 03/04/2013 23:45, Mike Turquette a ?crit :
> Quoting Emilio L?pez (2013-03-27 14:20:36)
>> Hi,
>>
>> This patchset adds support for the main sunxi gates; namely, those found
>> on AXI, AHB, APB0 and APB1 clocks. The series depends on Maxime's UART
>> rework and on the basic sunxi clock driver by me.
>>
>> Patches 1 and 2 implement the actual gate support, and patch 3 switches
>> the UARTs to use the correct gates now that they are available.
>>
>> Patch 4 and 5 add clock support to our pinctrl driver, as we need to
>> keep the pio clock running for gpio to work.
>>
>> Patch 6 drops the ignore flags; now that we have actual clock users that
>> will keep the important clocks running.
>>
>> Patch 7 is an unrelated oneliner to remove an unnecesary kmalloc call.
>>
>> The main changes from v1 are renamed compatible strings and a clarification
>> on the documentation, see each individual patch for more details.
>>
>
> Hi Emilio,
>
> Which tree(s) did you want these patches to go through?
1, 6 and 7 are changes on the clock driver in itself that depends on the
patches you have in your tree, so I guess you should take them through
your tree.
2,3 and 5 are dt patches, so I'll take them, and patch 4 has already
been applied by LinusW.
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 4/6] pinctrl: sunxi: add clock support
2013-04-03 21:20 ` Maxime Ripard
2013-04-04 0:49 ` Mike Turquette
@ 2013-04-04 11:37 ` Linus Walleij
2013-04-04 17:01 ` Mike Turquette
1 sibling, 1 reply; 37+ messages in thread
From: Linus Walleij @ 2013-04-04 11:37 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Apr 3, 2013 at 11:20 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Le 03/04/2013 13:59, Linus Walleij a ?crit :
>> On Wed, Mar 27, 2013 at 9:03 PM, Maxime Ripard
>> <maxime.ripard@free-electrons.com> wrote:
>>
>>> Hi Linus,
>>> Le 27/03/2013 14:14, Linus Walleij a ?crit :
>>>> On Fri, Mar 22, 2013 at 3:20 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
>>>>
>>>>> For the port controller to work, we need to enable the apb0_pio gate.
>>>>> This commit adds the ability to enable one clock specified on the device
>>>>> tree to the pinctrl driver.
>>>>>
>>>>> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
>>>>
>>>> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>>>>
>>>> I guess you'll want to merge these as one series to some platform-specific
>>>> tree, tell me if you want it merged in the pinctrl tree.
>>>
>>> The easiest would probably be to merge this patch through your patch,
>>> with Mike taking the clock driver patches and me taking the dt ones,
>>> once we agree on the other patches.
>>
>> OK then, patch applied to the pinctrl tree, thanks!
>
> Ouch, the previous patches aren't applied yet by Mike, and we didn't
> have some comments from him about these patches, so I can't really say
> if the previous patches will get merge by 3.10 or not... So we will
> maybe end up with a broken pinctrl stuff.
This is usually why we keep patches together and merge whole series
into one tree, such as ARM SoC.
Well, maybe I'll drop it then ...
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 4/6] pinctrl: sunxi: add clock support
2013-04-04 11:37 ` Linus Walleij
@ 2013-04-04 17:01 ` Mike Turquette
2013-04-05 7:45 ` Linus Walleij
0 siblings, 1 reply; 37+ messages in thread
From: Mike Turquette @ 2013-04-04 17:01 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Linus Walleij (2013-04-04 04:37:23)
> On Wed, Apr 3, 2013 at 11:20 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Le 03/04/2013 13:59, Linus Walleij a ?crit :
> >> On Wed, Mar 27, 2013 at 9:03 PM, Maxime Ripard
> >> <maxime.ripard@free-electrons.com> wrote:
> >>
> >>> Hi Linus,
> >>> Le 27/03/2013 14:14, Linus Walleij a ?crit :
> >>>> On Fri, Mar 22, 2013 at 3:20 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> >>>>
> >>>>> For the port controller to work, we need to enable the apb0_pio gate.
> >>>>> This commit adds the ability to enable one clock specified on the device
> >>>>> tree to the pinctrl driver.
> >>>>>
> >>>>> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
> >>>>
> >>>> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> >>>>
> >>>> I guess you'll want to merge these as one series to some platform-specific
> >>>> tree, tell me if you want it merged in the pinctrl tree.
> >>>
> >>> The easiest would probably be to merge this patch through your patch,
> >>> with Mike taking the clock driver patches and me taking the dt ones,
> >>> once we agree on the other patches.
> >>
> >> OK then, patch applied to the pinctrl tree, thanks!
> >
> > Ouch, the previous patches aren't applied yet by Mike, and we didn't
> > have some comments from him about these patches, so I can't really say
> > if the previous patches will get merge by 3.10 or not... So we will
> > maybe end up with a broken pinctrl stuff.
>
> This is usually why we keep patches together and merge whole series
> into one tree, such as ARM SoC.
>
> Well, maybe I'll drop it then ...
>
I plan on taking in the three clk patches after getting final comments
from Gregory. So maybe you do not need to drop the pinctrl patches?
Regards,
Mike
> Yours,
> Linus Walleij
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v2 1/7] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
2013-04-04 2:46 ` Mike Turquette
@ 2013-04-04 20:45 ` Gregory CLEMENT
2013-04-04 21:08 ` Mike Turquette
0 siblings, 1 reply; 37+ messages in thread
From: Gregory CLEMENT @ 2013-04-04 20:45 UTC (permalink / raw)
To: linux-arm-kernel
On 04/04/2013 04:46 AM, Mike Turquette wrote:
> Quoting Emilio L??pez (2013-04-03 18:19:22)
>> Hi Mike,
>>
>> El 03/04/13 18:48, Mike Turquette escribi??:
>>> Quoting Emilio L??pez (2013-03-27 14:20:37)
>>>> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>>>> index d528a24..244de90 100644
>>>> --- a/drivers/clk/sunxi/clk-sunxi.c
>>>> +++ b/drivers/clk/sunxi/clk-sunxi.c
>>>> @@ -302,6 +302,82 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
>>>> }
>>>>
>>>>
>>>> +
>>>
>>> A lot of white space between these functions.
>>
>> All of the function blocks are separated with three spaces on the file;
>> I thought it looked more readable that way, but I don't have any strong
>> opinion on separation. Is there any standard for this used on the kernel?
>>
>> In any case, and to keep consistency, can we handle this on a follow-up
>> patch?
>>
>
> If it's consistent throughout the file then go ahead and keep it.
>
>>>> +/**
>>>> + * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
>>>> + */
>>>> +
>>>> +#define SUNXI_GATES_MAX_SIZE 64
>>>> +
>>>> +struct gates_data {
>>>> + DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
>>>> +};
>>>> +
>>>> +static const __initconst struct gates_data axi_gates_data = {
>>>> + .mask = {1},
>>>> +};
>>>> +
>>>> +static const __initconst struct gates_data ahb_gates_data = {
>>>> + .mask = {0x7F77FFF, 0x14FB3F},
>>>> +};
>>>> +
>>>> +static const __initconst struct gates_data apb0_gates_data = {
>>>> + .mask = {0x4EF},
>>>> +};
>>>> +
>>>> +static const __initconst struct gates_data apb1_gates_data = {
>>>> + .mask = {0xFF00F7},
>>>> +};
>>>> +
>>>> +static void __init sunxi_gates_clk_setup(struct device_node *node,
>>>> + struct gates_data *data)
>>>> +{
>>>> + struct clk_onecell_data *clk_data;
>>>> + const char *clk_parent;
>>>> + const char *clk_name;
>>>> + void *reg;
>>>> + int qty;
>>>> + int i = 0;
>>>> + int j = 0;
>>>> + int ignore;
>>>> +
>>>> + reg = of_iomap(node, 0);
>>>> +
>>>> + clk_parent = of_clk_get_parent_name(node, 0);
>>>> +
>>>> + /* Worst-case size approximation and memory allocation */
>>>> + qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
>>>> + clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
>>>> + if (!clk_data)
>>>> + return;
>>>> + clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
>>>> + if (!clk_data->clks) {
>>>> + kfree(clk_data);
>>>> + return;
>>>> + }
>>>> +
>>>> + for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
>>>> + of_property_read_string_index(node, "clock-output-names",
>>>> + j, &clk_name);
>>>> +
>>>> + /* No driver claims this clock, but it should remain gated */
>>>
>>> Should the comment read, "ungated" instead of "gated"?
>>
>> Indeed, good catch. Do you want me to resend the series, or can you
>> amend this when picking the patches?
>>
>
> I can amend it, but I don't like to get into the habit of doing that too
> often.
>
> I'll wait on Gregory's response on the of_clk_init stuff before I do so.
>
> Regards,
> Mike
>
>>>> + ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
>>>> +
>>>> + clk_data->clks[i] = clk_register_gate(NULL, clk_name,
>>>> + clk_parent, ignore,
>>>> + reg + 4 * (i/32), i % 32,
>>>> + 0, &clk_lock);
>>>> + WARN_ON(IS_ERR(clk_data->clks[i]));
>>>> +
>>>> + j++;
>>>> + }
>>>> +
>>>> + /* Adjust to the real max */
>>>> + clk_data->clk_num = i;
>>>> +
>>>> + of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
>>>> +}
>>>> +
>>>> /* Matches for of_clk_init */
>>>> static const __initconst struct of_device_id clk_match[] = {
>>>> {.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
>>>> @@ -331,6 +407,15 @@ static const __initconst struct of_device_id clk_mux_match[] = {
>>>> {}
>>>> };
>>>>
>>>> +/* Matches for gate clocks */
>>>> +static const __initconst struct of_device_id clk_gates_match[] = {
>>>> + {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &axi_gates_data,},
>>>> + {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &ahb_gates_data,},
>>>> + {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &apb0_gates_data,},
>>>> + {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &apb1_gates_data,},
>>>> + {}
>>>> +};
>>>> +
>>>> static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
>>>> void *function)
>>>> {
>>>> @@ -359,4 +444,7 @@ void __init sunxi_init_clocks(void)
>>>>
>>>> /* Register mux clocks */
>>>> of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
>>>> +
>>>> + /* Register gate clocks */
>>>> + of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
>>>
>>> I'm still a device tree noob, so this may be a dumb question. Can the
>>> above be converted to of_clk_init?
>>
>> As far as I know, you can't, because of_clk_init doesn't allow for
>> custom data to be passed to the functions. If we were to use of_clk_init
>> we would need one function per clock, and it would be mostly duplicated
>> code / wrappers. I've added Gregory on Cc, please correct me if this is
>> not the case.
I confirm that the current implementation of of_clk_init only take setup
functions. That was also the reason why we didn't use it in mvebu/clk-core.c
for example.
Maybe it should be a good improvement to allow of_clk_init to receive
a function _and_ data for a given node. Something like that;
typedef void (*of_clk_init_cb_t)(struct device_node *, void *data);
struct clk_of_setup {
of_clk_init_cb_t clk_init_cb;
void* data;
}
void __init of_clk_init(const struct of_device_id *matches)
{
struct device_node *np;
if (!matches)
matches = __clk_of_table;
for_each_matching_node(np, matches) {
const struct of_device_id *match = of_match_node(matches, np);
match->clk_init_cb(np, match->data);
}
}
I have just writen this code in this email I didn't even try to compile this code.
This was just a rough idea which could be use as a base for future patch for 3.11.
With a good coccinelle script it should be not too complicated.
But about this current patch, I am fine with it, and you can add my
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>>
>> Thanks for the review,
>>
>> Emilio
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v2 1/7] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
2013-04-04 20:45 ` Gregory CLEMENT
@ 2013-04-04 21:08 ` Mike Turquette
0 siblings, 0 replies; 37+ messages in thread
From: Mike Turquette @ 2013-04-04 21:08 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Gregory CLEMENT (2013-04-04 13:45:24)
> On 04/04/2013 04:46 AM, Mike Turquette wrote:
> > Quoting Emilio L??pez (2013-04-03 18:19:22)
> >> Hi Mike,
> >>
> >> El 03/04/13 18:48, Mike Turquette escribi??:
> >>> Quoting Emilio L??pez (2013-03-27 14:20:37)
> >>>> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> >>>> index d528a24..244de90 100644
> >>>> --- a/drivers/clk/sunxi/clk-sunxi.c
> >>>> +++ b/drivers/clk/sunxi/clk-sunxi.c
> >>>> @@ -302,6 +302,82 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
> >>>> }
> >>>>
> >>>>
> >>>> +
> >>>
> >>> A lot of white space between these functions.
> >>
> >> All of the function blocks are separated with three spaces on the file;
> >> I thought it looked more readable that way, but I don't have any strong
> >> opinion on separation. Is there any standard for this used on the kernel?
> >>
> >> In any case, and to keep consistency, can we handle this on a follow-up
> >> patch?
> >>
> >
> > If it's consistent throughout the file then go ahead and keep it.
> >
> >>>> +/**
> >>>> + * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
> >>>> + */
> >>>> +
> >>>> +#define SUNXI_GATES_MAX_SIZE 64
> >>>> +
> >>>> +struct gates_data {
> >>>> + DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
> >>>> +};
> >>>> +
> >>>> +static const __initconst struct gates_data axi_gates_data = {
> >>>> + .mask = {1},
> >>>> +};
> >>>> +
> >>>> +static const __initconst struct gates_data ahb_gates_data = {
> >>>> + .mask = {0x7F77FFF, 0x14FB3F},
> >>>> +};
> >>>> +
> >>>> +static const __initconst struct gates_data apb0_gates_data = {
> >>>> + .mask = {0x4EF},
> >>>> +};
> >>>> +
> >>>> +static const __initconst struct gates_data apb1_gates_data = {
> >>>> + .mask = {0xFF00F7},
> >>>> +};
> >>>> +
> >>>> +static void __init sunxi_gates_clk_setup(struct device_node *node,
> >>>> + struct gates_data *data)
> >>>> +{
> >>>> + struct clk_onecell_data *clk_data;
> >>>> + const char *clk_parent;
> >>>> + const char *clk_name;
> >>>> + void *reg;
> >>>> + int qty;
> >>>> + int i = 0;
> >>>> + int j = 0;
> >>>> + int ignore;
> >>>> +
> >>>> + reg = of_iomap(node, 0);
> >>>> +
> >>>> + clk_parent = of_clk_get_parent_name(node, 0);
> >>>> +
> >>>> + /* Worst-case size approximation and memory allocation */
> >>>> + qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
> >>>> + clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
> >>>> + if (!clk_data)
> >>>> + return;
> >>>> + clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
> >>>> + if (!clk_data->clks) {
> >>>> + kfree(clk_data);
> >>>> + return;
> >>>> + }
> >>>> +
> >>>> + for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
> >>>> + of_property_read_string_index(node, "clock-output-names",
> >>>> + j, &clk_name);
> >>>> +
> >>>> + /* No driver claims this clock, but it should remain gated */
> >>>
> >>> Should the comment read, "ungated" instead of "gated"?
> >>
> >> Indeed, good catch. Do you want me to resend the series, or can you
> >> amend this when picking the patches?
> >>
> >
> > I can amend it, but I don't like to get into the habit of doing that too
> > often.
> >
> > I'll wait on Gregory's response on the of_clk_init stuff before I do so.
> >
> > Regards,
> > Mike
> >
> >>>> + ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
> >>>> +
> >>>> + clk_data->clks[i] = clk_register_gate(NULL, clk_name,
> >>>> + clk_parent, ignore,
> >>>> + reg + 4 * (i/32), i % 32,
> >>>> + 0, &clk_lock);
> >>>> + WARN_ON(IS_ERR(clk_data->clks[i]));
> >>>> +
> >>>> + j++;
> >>>> + }
> >>>> +
> >>>> + /* Adjust to the real max */
> >>>> + clk_data->clk_num = i;
> >>>> +
> >>>> + of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> >>>> +}
> >>>> +
> >>>> /* Matches for of_clk_init */
> >>>> static const __initconst struct of_device_id clk_match[] = {
> >>>> {.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
> >>>> @@ -331,6 +407,15 @@ static const __initconst struct of_device_id clk_mux_match[] = {
> >>>> {}
> >>>> };
> >>>>
> >>>> +/* Matches for gate clocks */
> >>>> +static const __initconst struct of_device_id clk_gates_match[] = {
> >>>> + {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &axi_gates_data,},
> >>>> + {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &ahb_gates_data,},
> >>>> + {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &apb0_gates_data,},
> >>>> + {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &apb1_gates_data,},
> >>>> + {}
> >>>> +};
> >>>> +
> >>>> static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
> >>>> void *function)
> >>>> {
> >>>> @@ -359,4 +444,7 @@ void __init sunxi_init_clocks(void)
> >>>>
> >>>> /* Register mux clocks */
> >>>> of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
> >>>> +
> >>>> + /* Register gate clocks */
> >>>> + of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
> >>>
> >>> I'm still a device tree noob, so this may be a dumb question. Can the
> >>> above be converted to of_clk_init?
> >>
> >> As far as I know, you can't, because of_clk_init doesn't allow for
> >> custom data to be passed to the functions. If we were to use of_clk_init
> >> we would need one function per clock, and it would be mostly duplicated
> >> code / wrappers. I've added Gregory on Cc, please correct me if this is
> >> not the case.
>
> I confirm that the current implementation of of_clk_init only take setup
> functions. That was also the reason why we didn't use it in mvebu/clk-core.c
> for example.
>
> Maybe it should be a good improvement to allow of_clk_init to receive
> a function _and_ data for a given node. Something like that;
>
> typedef void (*of_clk_init_cb_t)(struct device_node *, void *data);
> struct clk_of_setup {
> of_clk_init_cb_t clk_init_cb;
> void* data;
> }
>
> void __init of_clk_init(const struct of_device_id *matches)
> {
> struct device_node *np;
>
> if (!matches)
> matches = __clk_of_table;
>
> for_each_matching_node(np, matches) {
> const struct of_device_id *match = of_match_node(matches, np);
> match->clk_init_cb(np, match->data);
> }
> }
>
> I have just writen this code in this email I didn't even try to compile this code.
> This was just a rough idea which could be use as a base for future patch for 3.11.
> With a good coccinelle script it should be not too complicated.
>
Sure, maybe some solution can be found for 3.11.
>
> But about this current patch, I am fine with it, and you can add my
> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>
Thanks. The three clock patches have been pushed to clk-next.
Regards,
Mike
>
> >>
> >> Thanks for the review,
> >>
> >> Emilio
>
>
> --
> Gregory Clement, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v2 0/6] clk: sunxi: gates support
2013-03-27 21:20 ` [PATCH v2 0/6] clk: sunxi: gates support Emilio López
` (7 preceding siblings ...)
2013-04-03 21:45 ` [PATCH v2 0/6] clk: sunxi: gates support Mike Turquette
@ 2013-04-04 22:01 ` Maxime Ripard
8 siblings, 0 replies; 37+ messages in thread
From: Maxime Ripard @ 2013-04-04 22:01 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Le 27/03/2013 22:20, Emilio L?pez a ?crit :
> Hi,
>
> This patchset adds support for the main sunxi gates; namely, those found
> on AXI, AHB, APB0 and APB1 clocks. The series depends on Maxime's UART
> rework and on the basic sunxi clock driver by me.
>
> Patches 1 and 2 implement the actual gate support, and patch 3 switches
> the UARTs to use the correct gates now that they are available.
>
> Patch 4 and 5 add clock support to our pinctrl driver, as we need to
> keep the pio clock running for gpio to work.
>
> Patch 6 drops the ignore flags; now that we have actual clock users that
> will keep the important clocks running.
>
> Patch 7 is an unrelated oneliner to remove an unnecesary kmalloc call.
>
> The main changes from v1 are renamed compatible strings and a clarification
> on the documentation, see each individual patch for more details.
I merged the patches 2, 3 and 5 into my sunxi/dt-for-3.10 branch.
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 4/6] pinctrl: sunxi: add clock support
2013-04-04 17:01 ` Mike Turquette
@ 2013-04-05 7:45 ` Linus Walleij
0 siblings, 0 replies; 37+ messages in thread
From: Linus Walleij @ 2013-04-05 7:45 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Apr 4, 2013 at 7:01 PM, Mike Turquette <mturquette@linaro.org> wrote:
> Quoting Linus Walleij (2013-04-04 04:37:23)
>> On Wed, Apr 3, 2013 at 11:20 PM, Maxime Ripard
>> <maxime.ripard@free-electrons.com> wrote:
>> > Le 03/04/2013 13:59, Linus Walleij a ?crit :
>> >> On Wed, Mar 27, 2013 at 9:03 PM, Maxime Ripard
>> >> <maxime.ripard@free-electrons.com> wrote:
>> >>
>> >>> Hi Linus,
>> >>> Le 27/03/2013 14:14, Linus Walleij a ?crit :
>> >>>> On Fri, Mar 22, 2013 at 3:20 PM, Emilio L?pez <emilio@elopez.com.ar> wrote:
>> >>>>
>> >>>>> For the port controller to work, we need to enable the apb0_pio gate.
>> >>>>> This commit adds the ability to enable one clock specified on the device
>> >>>>> tree to the pinctrl driver.
>> >>>>>
>> >>>>> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
>> >>>>
>> >>>> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>> >>>>
>> >>>> I guess you'll want to merge these as one series to some platform-specific
>> >>>> tree, tell me if you want it merged in the pinctrl tree.
>> >>>
>> >>> The easiest would probably be to merge this patch through your patch,
>> >>> with Mike taking the clock driver patches and me taking the dt ones,
>> >>> once we agree on the other patches.
>> >>
>> >> OK then, patch applied to the pinctrl tree, thanks!
>> >
>> > Ouch, the previous patches aren't applied yet by Mike, and we didn't
>> > have some comments from him about these patches, so I can't really say
>> > if the previous patches will get merge by 3.10 or not... So we will
>> > maybe end up with a broken pinctrl stuff.
>>
>> This is usually why we keep patches together and merge whole series
>> into one tree, such as ARM SoC.
>>
>> Well, maybe I'll drop it then ...
>>
>
> I plan on taking in the three clk patches after getting final comments
> from Gregory. So maybe you do not need to drop the pinctrl patches?
No, I'm keeping it around, no problem.
Thanks Mike,
Linus Walleij
^ permalink raw reply [flat|nested] 37+ messages in thread
end of thread, other threads:[~2013-04-05 7:45 UTC | newest]
Thread overview: 37+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-03-22 14:20 [PATCH 0/6] clk: sunxi: gates support Emilio López
2013-03-22 14:20 ` [PATCH 1/6] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates Emilio López
2013-03-25 9:43 ` Maxime Ripard
2013-03-25 10:17 ` Emilio López
2013-03-25 11:18 ` Maxime Ripard
2013-03-22 14:20 ` [PATCH 2/6] arm: sunxi: Add clock definitions for AXI, AHB, APB0, " Emilio López
2013-03-22 14:20 ` [PATCH 3/6] arm: sunxi: use the right clock phandles for UARTs Emilio López
2013-03-22 14:20 ` [PATCH 4/6] pinctrl: sunxi: add clock support Emilio López
2013-03-27 13:14 ` Linus Walleij
2013-03-27 20:03 ` Maxime Ripard
2013-04-03 11:59 ` Linus Walleij
2013-04-03 21:20 ` Maxime Ripard
2013-04-04 0:49 ` Mike Turquette
2013-04-04 11:37 ` Linus Walleij
2013-04-04 17:01 ` Mike Turquette
2013-04-05 7:45 ` Linus Walleij
2013-03-22 14:20 ` [PATCH 5/6] arm: sunxi: Add clock to pinctrl node Emilio López
2013-03-22 14:20 ` [PATCH 6/6] clk: sunxi: drop CLK_IGNORE_UNUSED Emilio López
2013-03-27 21:20 ` [PATCH v2 0/6] clk: sunxi: gates support Emilio López
2013-03-27 21:20 ` [PATCH v2 1/7] clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates Emilio López
2013-04-03 21:48 ` Mike Turquette
2013-04-04 1:19 ` Emilio López
2013-04-04 2:46 ` Mike Turquette
2013-04-04 20:45 ` Gregory CLEMENT
2013-04-04 21:08 ` Mike Turquette
2013-03-27 21:20 ` [PATCH v2 2/7] arm: sunxi: Add clock definitions for AXI, AHB, APB0, " Emilio López
2013-03-27 21:20 ` [PATCH v2 3/7] arm: sunxi: use the right clock phandles for UARTs Emilio López
2013-03-27 21:20 ` [PATCH v2 4/7] pinctrl: sunxi: add clock support Emilio López
2013-03-27 21:20 ` [PATCH v2 5/7] arm: sunxi: Add clock to pinctrl node Emilio López
2013-03-27 21:20 ` [PATCH v2 6/7] clk: sunxi: drop CLK_IGNORE_UNUSED Emilio López
2013-04-03 21:48 ` Mike Turquette
2013-03-27 21:20 ` [PATCH v2 7/7] clk: sunxi: drop an unnecesary kmalloc Emilio López
2013-04-03 21:49 ` Mike Turquette
2013-04-03 21:45 ` [PATCH v2 0/6] clk: sunxi: gates support Mike Turquette
2013-04-03 22:13 ` Emilio López
2013-04-04 5:52 ` Maxime Ripard
2013-04-04 22:01 ` Maxime Ripard
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