[PATCHv4 00/33] ARM: OMAP: clock conversion to DT

[PATCHv4 00/33] ARM: OMAP: clock conversion to DT

[Tero Kristo]

Hi,

Changes compared to previous version:

- Clock init files moved from mach-omap2/ to drivers/clk/omap/
- AM33xx support added [patches 15-20]
- OMAP3 support added [patches 21-29]
- DRA7 APLL support added (thanks Keerthy) [patches 30-33]

Test branch on top of 3.11-rc1 available here:

git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
branch: mainline-3.11-rc1-omap-dt-clks

Testing done:

- boot + suspend tested on OMAP3 beagle C4 (omap3530)
- boot + suspend tested on OMAP4 panda ES (omap4460)
- boot tested on beagle bone (am335x)

A boot test was also executed for DRA7 and OMAP5 on a separate branch
(mainline does not have OMAP5 / DRA7 support so far.)

TODO:
- Add AM35xx support (OMAP3 derivative, AM35xx only clock nodes missing)

Overall diffstat added just for fun:

 arch/arm/boot/dts/am33xx-clocks.dtsi               |  663 ++++
 arch/arm/boot/dts/am33xx.dtsi                      |    7 +
 arch/arm/boot/dts/dra7xx-clocks.dtsi               | 2113 ++++++++++++
 arch/arm/boot/dts/omap3.dtsi                       |    7 +
 arch/arm/boot/dts/omap3430es1-clocks.dtsi          |  166 +
 arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi    |  240 ++
 arch/arm/boot/dts/omap34xx.dtsi                    |    9 +
 .../omap36xx-am35xx-omap3430es2plus-clocks.dtsi    |  214 ++
 arch/arm/boot/dts/omap36xx-clocks.dtsi             |   97 +
 .../boot/dts/omap36xx-omap3430es2plus-clocks.dtsi  |  185 +
 arch/arm/boot/dts/omap36xx.dtsi                    |   10 +
 arch/arm/boot/dts/omap3xxx-clocks.dtsi             | 1594 +++++++++
 arch/arm/boot/dts/omap443x-clocks.dtsi             |   17 +
 arch/arm/boot/dts/omap443x.dtsi                    |    8 +
 arch/arm/boot/dts/omap4460.dtsi                    |    8 +
 arch/arm/boot/dts/omap446x-clocks.dtsi             |   27 +
 arch/arm/boot/dts/omap44xx-clocks.dtsi             | 1654 +++++++++
 arch/arm/boot/dts/omap54xx-clocks.dtsi             | 1416 ++++++++
 arch/arm/mach-omap2/Makefile                       |    5 +-
 arch/arm/mach-omap2/cclock33xx_data.c              | 1059 ------
 arch/arm/mach-omap2/cclock3xxx_data.c              | 3641 --------------------
 arch/arm/mach-omap2/cclock44xx_data.c              | 1730 ----------
 arch/arm/mach-omap2/clock.c                        |    6 +
 arch/arm/mach-omap2/clock.h                        |  163 +-
 arch/arm/mach-omap2/clock3xxx.h                    |    7 +-
 arch/arm/mach-omap2/io.c                           |    7 +-
 arch/arm/mach-omap2/omap_hwmod.c                   |    5 +-
 drivers/clk/Makefile                               |    1 +
 drivers/clk/clk-divider.c                          |    6 +-
 drivers/clk/clk-fixed-factor.c                     |    6 +-
 drivers/clk/clk-gate.c                             |    8 +-
 drivers/clk/clk-mux.c                              |    6 +-
 drivers/clk/clkdev.c                               |   32 +
 drivers/clk/omap/Makefile                          |    4 +
 drivers/clk/omap/apll.c                            |  213 ++
 drivers/clk/omap/autoidle.c                        |  130 +
 drivers/clk/omap/clk-33xx.c                        |   85 +
 drivers/clk/omap/clk-3xxx.c                        |  171 +
 drivers/clk/omap/clk-44xx.c                        |  118 +
 drivers/clk/omap/clk-54xx.c                        |   58 +
 drivers/clk/omap/clk-7xx.c                         |   67 +
 drivers/clk/omap/clk.c                             |   84 +
 drivers/clk/omap/dpll.c                            |  387 +++
 drivers/clk/omap/gate.c                            |  166 +
 drivers/clk/omap/interface.c                       |  110 +
 include/linux/clk/omap.h                           |  223 ++
 46 files changed, 10327 insertions(+), 6606 deletions(-)

-Tero

[PATCHv4 00/33] ARM: OMAP: clock conversion to DT

[Tero Kristo]

Hi,

Changes compared to previous version:

- Clock init files moved from mach-omap2/ to drivers/clk/omap/
- AM33xx support added [patches 15-20]
- OMAP3 support added [patches 21-29]
- DRA7 APLL support added (thanks Keerthy) [patches 30-33]

Test branch on top of 3.11-rc1 available here:

git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
branch: mainline-3.11-rc1-omap-dt-clks

Testing done:

- boot + suspend tested on OMAP3 beagle C4 (omap3530)
- boot + suspend tested on OMAP4 panda ES (omap4460)
- boot tested on beagle bone (am335x)

A boot test was also executed for DRA7 and OMAP5 on a separate branch
(mainline does not have OMAP5 / DRA7 support so far.)

TODO:
- Add AM35xx support (OMAP3 derivative, AM35xx only clock nodes missing)

Overall diffstat added just for fun:

 arch/arm/boot/dts/am33xx-clocks.dtsi               |  663 ++++
 arch/arm/boot/dts/am33xx.dtsi                      |    7 +
 arch/arm/boot/dts/dra7xx-clocks.dtsi               | 2113 ++++++++++++
 arch/arm/boot/dts/omap3.dtsi                       |    7 +
 arch/arm/boot/dts/omap3430es1-clocks.dtsi          |  166 +
 arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi    |  240 ++
 arch/arm/boot/dts/omap34xx.dtsi                    |    9 +
 .../omap36xx-am35xx-omap3430es2plus-clocks.dtsi    |  214 ++
 arch/arm/boot/dts/omap36xx-clocks.dtsi             |   97 +
 .../boot/dts/omap36xx-omap3430es2plus-clocks.dtsi  |  185 +
 arch/arm/boot/dts/omap36xx.dtsi                    |   10 +
 arch/arm/boot/dts/omap3xxx-clocks.dtsi             | 1594 +++++++++
 arch/arm/boot/dts/omap443x-clocks.dtsi             |   17 +
 arch/arm/boot/dts/omap443x.dtsi                    |    8 +
 arch/arm/boot/dts/omap4460.dtsi                    |    8 +
 arch/arm/boot/dts/omap446x-clocks.dtsi             |   27 +
 arch/arm/boot/dts/omap44xx-clocks.dtsi             | 1654 +++++++++
 arch/arm/boot/dts/omap54xx-clocks.dtsi             | 1416 ++++++++
 arch/arm/mach-omap2/Makefile                       |    5 +-
 arch/arm/mach-omap2/cclock33xx_data.c              | 1059 ------
 arch/arm/mach-omap2/cclock3xxx_data.c              | 3641 --------------------
 arch/arm/mach-omap2/cclock44xx_data.c              | 1730 ----------
 arch/arm/mach-omap2/clock.c                        |    6 +
 arch/arm/mach-omap2/clock.h                        |  163 +-
 arch/arm/mach-omap2/clock3xxx.h                    |    7 +-
 arch/arm/mach-omap2/io.c                           |    7 +-
 arch/arm/mach-omap2/omap_hwmod.c                   |    5 +-
 drivers/clk/Makefile                               |    1 +
 drivers/clk/clk-divider.c                          |    6 +-
 drivers/clk/clk-fixed-factor.c                     |    6 +-
 drivers/clk/clk-gate.c                             |    8 +-
 drivers/clk/clk-mux.c                              |    6 +-
 drivers/clk/clkdev.c                               |   32 +
 drivers/clk/omap/Makefile                          |    4 +
 drivers/clk/omap/apll.c                            |  213 ++
 drivers/clk/omap/autoidle.c                        |  130 +
 drivers/clk/omap/clk-33xx.c                        |   85 +
 drivers/clk/omap/clk-3xxx.c                        |  171 +
 drivers/clk/omap/clk-44xx.c                        |  118 +
 drivers/clk/omap/clk-54xx.c                        |   58 +
 drivers/clk/omap/clk-7xx.c                         |   67 +
 drivers/clk/omap/clk.c                             |   84 +
 drivers/clk/omap/dpll.c                            |  387 +++
 drivers/clk/omap/gate.c                            |  166 +
 drivers/clk/omap/interface.c                       |  110 +
 include/linux/clk/omap.h                           |  223 ++
 46 files changed, 10327 insertions(+), 6606 deletions(-)

-Tero

[PATCHv4 01/33] CLK: clkdev: add support for looking up clocks from DT

[Tero Kristo]

clk_get_sys / clk_get can now find clocks from device-tree. If a DT clock
is found, an entry is added to the clk_lookup list also for subsequent
searches.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
---
 drivers/clk/clkdev.c |   32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 442a313..e39f082 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -93,6 +93,18 @@ struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
 EXPORT_SYMBOL(of_clk_get_by_name);
 #endif
 
+/**
+ * clkdev_add_nolock - add lookup entry for a clock
+ * @cl: pointer to new clock lookup entry
+ *
+ * Non-locking version, used internally by clk_find() to add DT based
+ * clock lookup entries.
+ */
+static void clkdev_add_nolock(struct clk_lookup *cl)
+{
+	list_add_tail(&cl->node, &clocks);
+}
+
 /*
  * Find the correct struct clk for the device and connection ID.
  * We do slightly fuzzy matching here:
@@ -106,6 +118,9 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
 {
 	struct clk_lookup *p, *cl = NULL;
 	int match, best_found = 0, best_possible = 0;
+	struct device_node *node;
+	struct clk *clk;
+	struct of_phandle_args clkspec;
 
 	if (dev_id)
 		best_possible += 2;
@@ -133,6 +148,23 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
 				break;
 		}
 	}
+
+	if (cl)
+		return cl;
+
+	/* If clock was not found, attempt to look-up from DT */
+	node = of_find_node_by_name(NULL, con_id);
+
+	clkspec.np = node;
+
+	clk = of_clk_get_from_provider(&clkspec);
+
+	if (!IS_ERR(clk)) {
+		/* We found a clock, add node to clkdev */
+		cl = clkdev_alloc(clk, con_id, dev_id);
+		clkdev_add_nolock(cl);
+	}
+
 	return cl;
 }
 
-- 
1.7.9.5

[PATCHv4 01/33] CLK: clkdev: add support for looking up clocks from DT

[Tero Kristo]

clk_get_sys / clk_get can now find clocks from device-tree. If a DT clock
is found, an entry is added to the clk_lookup list also for subsequent
searches.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
---
 drivers/clk/clkdev.c |   32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 442a313..e39f082 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -93,6 +93,18 @@ struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
 EXPORT_SYMBOL(of_clk_get_by_name);
 #endif
 
+/**
+ * clkdev_add_nolock - add lookup entry for a clock
+ * @cl: pointer to new clock lookup entry
+ *
+ * Non-locking version, used internally by clk_find() to add DT based
+ * clock lookup entries.
+ */
+static void clkdev_add_nolock(struct clk_lookup *cl)
+{
+	list_add_tail(&cl->node, &clocks);
+}
+
 /*
  * Find the correct struct clk for the device and connection ID.
  * We do slightly fuzzy matching here:
@@ -106,6 +118,9 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
 {
 	struct clk_lookup *p, *cl = NULL;
 	int match, best_found = 0, best_possible = 0;
+	struct device_node *node;
+	struct clk *clk;
+	struct of_phandle_args clkspec;
 
 	if (dev_id)
 		best_possible += 2;
@@ -133,6 +148,23 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
 				break;
 		}
 	}
+
+	if (cl)
+		return cl;
+
+	/* If clock was not found, attempt to look-up from DT */
+	node = of_find_node_by_name(NULL, con_id);
+
+	clkspec.np = node;
+
+	clk = of_clk_get_from_provider(&clkspec);
+
+	if (!IS_ERR(clk)) {
+		/* We found a clock, add node to clkdev */
+		cl = clkdev_alloc(clk, con_id, dev_id);
+		clkdev_add_nolock(cl);
+	}
+
 	return cl;
 }
 
-- 
1.7.9.5

Re: [PATCHv4 01/33] CLK: clkdev: add support for looking up clocks from DT

[Nishanth Menon]

On 07/23/2013 02:19 AM, Tero Kristo wrote:
> clk_get_sys / clk_get can now find clocks from device-tree. If a DT clock
> is found, an entry is added to the clk_lookup list also for subsequent
> searches.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> ---
>   drivers/clk/clkdev.c |   32 ++++++++++++++++++++++++++++++++
>   1 file changed, 32 insertions(+)
>
> diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
> index 442a313..e39f082 100644
> --- a/drivers/clk/clkdev.c
> +++ b/drivers/clk/clkdev.c
> @@ -93,6 +93,18 @@ struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
>   EXPORT_SYMBOL(of_clk_get_by_name);
>   #endif
>
> +/**
> + * clkdev_add_nolock - add lookup entry for a clock
> + * @cl: pointer to new clock lookup entry
> + *
> + * Non-locking version, used internally by clk_find() to add DT based
> + * clock lookup entries.
> + */
> +static void clkdev_add_nolock(struct clk_lookup *cl)
> +{
> +	list_add_tail(&cl->node, &clocks);
> +}
> +
>   /*
>    * Find the correct struct clk for the device and connection ID.
>    * We do slightly fuzzy matching here:
> @@ -106,6 +118,9 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
>   {
>   	struct clk_lookup *p, *cl = NULL;
>   	int match, best_found = 0, best_possible = 0;
> +	struct device_node *node;
> +	struct clk *clk;
> +	struct of_phandle_args clkspec;
>
>   	if (dev_id)
>   		best_possible += 2;
> @@ -133,6 +148,23 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
>   				break;
>   		}
>   	}
> +
> +	if (cl)
> +		return cl;
> +
> +	/* If clock was not found, attempt to look-up from DT */
> +	node = of_find_node_by_name(NULL, con_id);
> +
> +	clkspec.np = node;
> +
> +	clk = of_clk_get_from_provider(&clkspec);
> +
> +	if (!IS_ERR(clk)) {
> +		/* We found a clock, add node to clkdev */
> +		cl = clkdev_alloc(clk, con_id, dev_id);

clkdev_alloc may return NULL depending on vclkdev_alloc in which case 
clkdev_add_nolock will crash trying to dereference it.

> +		clkdev_add_nolock(cl);
> +	}
> +
>   	return cl;
>   }
>
>


-- 
Regards,
Nishanth Menon

[PATCHv4 01/33] CLK: clkdev: add support for looking up clocks from DT

[Nishanth Menon]

On 07/23/2013 02:19 AM, Tero Kristo wrote:
> clk_get_sys / clk_get can now find clocks from device-tree. If a DT clock
> is found, an entry is added to the clk_lookup list also for subsequent
> searches.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> ---
>   drivers/clk/clkdev.c |   32 ++++++++++++++++++++++++++++++++
>   1 file changed, 32 insertions(+)
>
> diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
> index 442a313..e39f082 100644
> --- a/drivers/clk/clkdev.c
> +++ b/drivers/clk/clkdev.c
> @@ -93,6 +93,18 @@ struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
>   EXPORT_SYMBOL(of_clk_get_by_name);
>   #endif
>
> +/**
> + * clkdev_add_nolock - add lookup entry for a clock
> + * @cl: pointer to new clock lookup entry
> + *
> + * Non-locking version, used internally by clk_find() to add DT based
> + * clock lookup entries.
> + */
> +static void clkdev_add_nolock(struct clk_lookup *cl)
> +{
> +	list_add_tail(&cl->node, &clocks);
> +}
> +
>   /*
>    * Find the correct struct clk for the device and connection ID.
>    * We do slightly fuzzy matching here:
> @@ -106,6 +118,9 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
>   {
>   	struct clk_lookup *p, *cl = NULL;
>   	int match, best_found = 0, best_possible = 0;
> +	struct device_node *node;
> +	struct clk *clk;
> +	struct of_phandle_args clkspec;
>
>   	if (dev_id)
>   		best_possible += 2;
> @@ -133,6 +148,23 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
>   				break;
>   		}
>   	}
> +
> +	if (cl)
> +		return cl;
> +
> +	/* If clock was not found, attempt to look-up from DT */
> +	node = of_find_node_by_name(NULL, con_id);
> +
> +	clkspec.np = node;
> +
> +	clk = of_clk_get_from_provider(&clkspec);
> +
> +	if (!IS_ERR(clk)) {
> +		/* We found a clock, add node to clkdev */
> +		cl = clkdev_alloc(clk, con_id, dev_id);

clkdev_alloc may return NULL depending on vclkdev_alloc in which case 
clkdev_add_nolock will crash trying to dereference it.

> +		clkdev_add_nolock(cl);
> +	}
> +
>   	return cl;
>   }
>
>


-- 
Regards,
Nishanth Menon

Re: [PATCHv4 01/33] CLK: clkdev: add support for looking up clocks from DT

[Tero Kristo]

On 07/30/2013 06:04 PM, Nishanth Menon wrote:
> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>> clk_get_sys / clk_get can now find clocks from device-tree. If a DT clock
>> is found, an entry is added to the clk_lookup list also for subsequent
>> searches.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> Cc: Russell King <linux@arm.linux.org.uk>
>> ---
>>   drivers/clk/clkdev.c |   32 ++++++++++++++++++++++++++++++++
>>   1 file changed, 32 insertions(+)
>>
>> diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
>> index 442a313..e39f082 100644
>> --- a/drivers/clk/clkdev.c
>> +++ b/drivers/clk/clkdev.c
>> @@ -93,6 +93,18 @@ struct clk *of_clk_get_by_name(struct device_node
>> *np, const char *name)
>>   EXPORT_SYMBOL(of_clk_get_by_name);
>>   #endif
>>
>> +/**
>> + * clkdev_add_nolock - add lookup entry for a clock
>> + * @cl: pointer to new clock lookup entry
>> + *
>> + * Non-locking version, used internally by clk_find() to add DT based
>> + * clock lookup entries.
>> + */
>> +static void clkdev_add_nolock(struct clk_lookup *cl)
>> +{
>> +    list_add_tail(&cl->node, &clocks);
>> +}
>> +
>>   /*
>>    * Find the correct struct clk for the device and connection ID.
>>    * We do slightly fuzzy matching here:
>> @@ -106,6 +118,9 @@ static struct clk_lookup *clk_find(const char
>> *dev_id, const char *con_id)
>>   {
>>       struct clk_lookup *p, *cl = NULL;
>>       int match, best_found = 0, best_possible = 0;
>> +    struct device_node *node;
>> +    struct clk *clk;
>> +    struct of_phandle_args clkspec;
>>
>>       if (dev_id)
>>           best_possible += 2;
>> @@ -133,6 +148,23 @@ static struct clk_lookup *clk_find(const char
>> *dev_id, const char *con_id)
>>                   break;
>>           }
>>       }
>> +
>> +    if (cl)
>> +        return cl;
>> +
>> +    /* If clock was not found, attempt to look-up from DT */
>> +    node = of_find_node_by_name(NULL, con_id);
>> +
>> +    clkspec.np = node;
>> +
>> +    clk = of_clk_get_from_provider(&clkspec);
>> +
>> +    if (!IS_ERR(clk)) {
>> +        /* We found a clock, add node to clkdev */
>> +        cl = clkdev_alloc(clk, con_id, dev_id);
>
> clkdev_alloc may return NULL depending on vclkdev_alloc in which case
> clkdev_add_nolock will crash trying to dereference it.

I'll add a check for that.

-Tero

>
>> +        clkdev_add_nolock(cl);
>> +    }
>> +
>>       return cl;
>>   }
>>
>>
>
>

[PATCHv4 01/33] CLK: clkdev: add support for looking up clocks from DT

[Tero Kristo]

On 07/30/2013 06:04 PM, Nishanth Menon wrote:
> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>> clk_get_sys / clk_get can now find clocks from device-tree. If a DT clock
>> is found, an entry is added to the clk_lookup list also for subsequent
>> searches.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> Cc: Russell King <linux@arm.linux.org.uk>
>> ---
>>   drivers/clk/clkdev.c |   32 ++++++++++++++++++++++++++++++++
>>   1 file changed, 32 insertions(+)
>>
>> diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
>> index 442a313..e39f082 100644
>> --- a/drivers/clk/clkdev.c
>> +++ b/drivers/clk/clkdev.c
>> @@ -93,6 +93,18 @@ struct clk *of_clk_get_by_name(struct device_node
>> *np, const char *name)
>>   EXPORT_SYMBOL(of_clk_get_by_name);
>>   #endif
>>
>> +/**
>> + * clkdev_add_nolock - add lookup entry for a clock
>> + * @cl: pointer to new clock lookup entry
>> + *
>> + * Non-locking version, used internally by clk_find() to add DT based
>> + * clock lookup entries.
>> + */
>> +static void clkdev_add_nolock(struct clk_lookup *cl)
>> +{
>> +    list_add_tail(&cl->node, &clocks);
>> +}
>> +
>>   /*
>>    * Find the correct struct clk for the device and connection ID.
>>    * We do slightly fuzzy matching here:
>> @@ -106,6 +118,9 @@ static struct clk_lookup *clk_find(const char
>> *dev_id, const char *con_id)
>>   {
>>       struct clk_lookup *p, *cl = NULL;
>>       int match, best_found = 0, best_possible = 0;
>> +    struct device_node *node;
>> +    struct clk *clk;
>> +    struct of_phandle_args clkspec;
>>
>>       if (dev_id)
>>           best_possible += 2;
>> @@ -133,6 +148,23 @@ static struct clk_lookup *clk_find(const char
>> *dev_id, const char *con_id)
>>                   break;
>>           }
>>       }
>> +
>> +    if (cl)
>> +        return cl;
>> +
>> +    /* If clock was not found, attempt to look-up from DT */
>> +    node = of_find_node_by_name(NULL, con_id);
>> +
>> +    clkspec.np = node;
>> +
>> +    clk = of_clk_get_from_provider(&clkspec);
>> +
>> +    if (!IS_ERR(clk)) {
>> +        /* We found a clock, add node to clkdev */
>> +        cl = clkdev_alloc(clk, con_id, dev_id);
>
> clkdev_alloc may return NULL depending on vclkdev_alloc in which case
> clkdev_add_nolock will crash trying to dereference it.

I'll add a check for that.

-Tero

>
>> +        clkdev_add_nolock(cl);
>> +    }
>> +
>>       return cl;
>>   }
>>
>>
>
>

[PATCHv4 02/33] clk: omap: introduce clock driver

[Tero Kristo]

Parses OMAP clock data from DT and registers those clocks with the clock
framework.  dt_omap_clk_init must be called early during boot for timer
initialization so it is exported and called from the existing clock code
instead of probing like a real driver. Based on initial work done by
Mike Turquette.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Mike Turquette <mturquette@linaro.org>
---
 drivers/clk/Makefile      |    1 +
 drivers/clk/omap/Makefile |    1 +
 drivers/clk/omap/clk.c    |   39 +++++++++++++++++++++++++++++++++++++++
 include/linux/clk/omap.h  |   24 ++++++++++++++++++++++++
 4 files changed, 65 insertions(+)
 create mode 100644 drivers/clk/omap/Makefile
 create mode 100644 drivers/clk/omap/clk.c
 create mode 100644 include/linux/clk/omap.h

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4038c2b..d3c3733 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500)	+= clk-vt8500.o
 obj-$(CONFIG_ARCH_ZYNQ)		+= zynq/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_PLAT_SAMSUNG)	+= samsung/
+obj-$(CONFIG_ARCH_OMAP)		+= omap/
 
 obj-$(CONFIG_X86)		+= x86/
 
diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
new file mode 100644
index 0000000..8195931
--- /dev/null
+++ b/drivers/clk/omap/Makefile
@@ -0,0 +1 @@
+obj-y					+= clk.o
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
new file mode 100644
index 0000000..4bf1929
--- /dev/null
+++ b/drivers/clk/omap/clk.c
@@ -0,0 +1,39 @@
+/*
+ * OMAP PRCM clock driver
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *     Tero Kristo <t-kristo@ti.com>
+ *     Mike Turquette <mturquette@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk/omap.h>
+#include <linux/kernel.h>
+#include <linux/of_device.h>
+
+/* FIXME - should the OMAP PRCM clock driver match generic types? */
+static const struct of_device_id clk_match[] = {
+	{.compatible = "fixed-clock", .data = of_fixed_clk_setup, },
+	{.compatible = "mux-clock", .data = of_mux_clk_setup, },
+	{.compatible = "fixed-factor-clock",
+		.data = of_fixed_factor_clk_setup, },
+	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
+	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
+	{},
+};
+
+/* FIXME - need to initialize early; skip real driver registration & probe */
+int __init dt_omap_clk_init(void)
+{
+	of_clk_init(clk_match);
+	return 0;
+}
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
new file mode 100644
index 0000000..647f02f
--- /dev/null
+++ b/include/linux/clk/omap.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_CLK_OMAP_H_
+#define __LINUX_CLK_OMAP_H_
+
+int __init dt_omap_clk_init(void);
+
+#endif
-- 
1.7.9.5

[PATCHv4 02/33] clk: omap: introduce clock driver

[Tero Kristo]

Parses OMAP clock data from DT and registers those clocks with the clock
framework.  dt_omap_clk_init must be called early during boot for timer
initialization so it is exported and called from the existing clock code
instead of probing like a real driver. Based on initial work done by
Mike Turquette.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Mike Turquette <mturquette@linaro.org>
---
 drivers/clk/Makefile      |    1 +
 drivers/clk/omap/Makefile |    1 +
 drivers/clk/omap/clk.c    |   39 +++++++++++++++++++++++++++++++++++++++
 include/linux/clk/omap.h  |   24 ++++++++++++++++++++++++
 4 files changed, 65 insertions(+)
 create mode 100644 drivers/clk/omap/Makefile
 create mode 100644 drivers/clk/omap/clk.c
 create mode 100644 include/linux/clk/omap.h

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4038c2b..d3c3733 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500)	+= clk-vt8500.o
 obj-$(CONFIG_ARCH_ZYNQ)		+= zynq/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_PLAT_SAMSUNG)	+= samsung/
+obj-$(CONFIG_ARCH_OMAP)		+= omap/
 
 obj-$(CONFIG_X86)		+= x86/
 
diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
new file mode 100644
index 0000000..8195931
--- /dev/null
+++ b/drivers/clk/omap/Makefile
@@ -0,0 +1 @@
+obj-y					+= clk.o
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
new file mode 100644
index 0000000..4bf1929
--- /dev/null
+++ b/drivers/clk/omap/clk.c
@@ -0,0 +1,39 @@
+/*
+ * OMAP PRCM clock driver
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *     Tero Kristo <t-kristo@ti.com>
+ *     Mike Turquette <mturquette@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk/omap.h>
+#include <linux/kernel.h>
+#include <linux/of_device.h>
+
+/* FIXME - should the OMAP PRCM clock driver match generic types? */
+static const struct of_device_id clk_match[] = {
+	{.compatible = "fixed-clock", .data = of_fixed_clk_setup, },
+	{.compatible = "mux-clock", .data = of_mux_clk_setup, },
+	{.compatible = "fixed-factor-clock",
+		.data = of_fixed_factor_clk_setup, },
+	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
+	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
+	{},
+};
+
+/* FIXME - need to initialize early; skip real driver registration & probe */
+int __init dt_omap_clk_init(void)
+{
+	of_clk_init(clk_match);
+	return 0;
+}
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
new file mode 100644
index 0000000..647f02f
--- /dev/null
+++ b/include/linux/clk/omap.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_CLK_OMAP_H_
+#define __LINUX_CLK_OMAP_H_
+
+int __init dt_omap_clk_init(void);
+
+#endif
-- 
1.7.9.5

Re: [PATCHv4 02/33] clk: omap: introduce clock driver

[Nishanth Menon]

On 07/23/2013 02:19 AM, Tero Kristo wrote:
> Parses OMAP clock data from DT and registers those clocks with the clock
> framework.  dt_omap_clk_init must be called early during boot for timer
> initialization so it is exported and called from the existing clock code
> instead of probing like a real driver. Based on initial work done by
> Mike Turquette.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Mike Turquette <mturquette@linaro.org>
> ---
>   drivers/clk/Makefile      |    1 +
>   drivers/clk/omap/Makefile |    1 +
>   drivers/clk/omap/clk.c    |   39 +++++++++++++++++++++++++++++++++++++++

Minor suggestion - should we just start drivers/clk/ti/ instead of clk/omap?

AM335x/DRA7 are not "strictly OMAP".. might also allow for some reuse 
for other TI platforms..

>   include/linux/clk/omap.h  |   24 ++++++++++++++++++++++++
>   4 files changed, 65 insertions(+)
>   create mode 100644 drivers/clk/omap/Makefile
>   create mode 100644 drivers/clk/omap/clk.c
>   create mode 100644 include/linux/clk/omap.h
>
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 4038c2b..d3c3733 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500)	+= clk-vt8500.o
>   obj-$(CONFIG_ARCH_ZYNQ)		+= zynq/
>   obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
>   obj-$(CONFIG_PLAT_SAMSUNG)	+= samsung/
> +obj-$(CONFIG_ARCH_OMAP)		+= omap/
>
>   obj-$(CONFIG_X86)		+= x86/
>
> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
> new file mode 100644
> index 0000000..8195931
> --- /dev/null
> +++ b/drivers/clk/omap/Makefile
> @@ -0,0 +1 @@
> +obj-y					+= clk.o
> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
> new file mode 100644
> index 0000000..4bf1929
> --- /dev/null
> +++ b/drivers/clk/omap/clk.c
> @@ -0,0 +1,39 @@
> +/*
> + * OMAP PRCM clock driver

maybe then prcm-clk.c ?

> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *     Tero Kristo <t-kristo@ti.com>
> + *     Mike Turquette <mturquette@linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clk/omap.h>
> +#include <linux/kernel.h>
> +#include <linux/of_device.h>
> +
> +/* FIXME - should the OMAP PRCM clock driver match generic types? */

should it? :)

> +static const struct of_device_id clk_match[] = {
> +	{.compatible = "fixed-clock", .data = of_fixed_clk_setup, },
drivers/clk/clk-fixed-rate.c seems to already do this with 
CLK_OF_DECLARE, or am I mistaken? and so on?
> +	{.compatible = "mux-clock", .data = of_mux_clk_setup, },
> +	{.compatible = "fixed-factor-clock",
> +		.data = of_fixed_factor_clk_setup, },
> +	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
> +	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
> +	{},
> +};
> +
> +/* FIXME - need to initialize early; skip real driver registration & probe */
> +int __init dt_omap_clk_init(void)

Might be good to have kernel doc to explain the init requirement as 
documented in commit message.

> +{
> +	of_clk_init(clk_match);

just doing of_clk_init(NULL); should do the job, no? that could even be 
a static inline OR introduced in board_generic without additional headers?

> +	return 0;
> +}
> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
> new file mode 100644
> index 0000000..647f02f
> --- /dev/null
> +++ b/include/linux/clk/omap.h
> @@ -0,0 +1,24 @@
> +/*
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.

would you like to match licensing to that of the C file?

> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> + */
> +
> +#ifndef __LINUX_CLK_OMAP_H_
> +#define __LINUX_CLK_OMAP_H_
> +
> +int __init dt_omap_clk_init(void);
> +
> +#endif
>


-- 
Regards,
Nishanth Menon

[PATCHv4 02/33] clk: omap: introduce clock driver

[Nishanth Menon]

On 07/23/2013 02:19 AM, Tero Kristo wrote:
> Parses OMAP clock data from DT and registers those clocks with the clock
> framework.  dt_omap_clk_init must be called early during boot for timer
> initialization so it is exported and called from the existing clock code
> instead of probing like a real driver. Based on initial work done by
> Mike Turquette.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Mike Turquette <mturquette@linaro.org>
> ---
>   drivers/clk/Makefile      |    1 +
>   drivers/clk/omap/Makefile |    1 +
>   drivers/clk/omap/clk.c    |   39 +++++++++++++++++++++++++++++++++++++++

Minor suggestion - should we just start drivers/clk/ti/ instead of clk/omap?

AM335x/DRA7 are not "strictly OMAP".. might also allow for some reuse 
for other TI platforms..

>   include/linux/clk/omap.h  |   24 ++++++++++++++++++++++++
>   4 files changed, 65 insertions(+)
>   create mode 100644 drivers/clk/omap/Makefile
>   create mode 100644 drivers/clk/omap/clk.c
>   create mode 100644 include/linux/clk/omap.h
>
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 4038c2b..d3c3733 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500)	+= clk-vt8500.o
>   obj-$(CONFIG_ARCH_ZYNQ)		+= zynq/
>   obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
>   obj-$(CONFIG_PLAT_SAMSUNG)	+= samsung/
> +obj-$(CONFIG_ARCH_OMAP)		+= omap/
>
>   obj-$(CONFIG_X86)		+= x86/
>
> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
> new file mode 100644
> index 0000000..8195931
> --- /dev/null
> +++ b/drivers/clk/omap/Makefile
> @@ -0,0 +1 @@
> +obj-y					+= clk.o
> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
> new file mode 100644
> index 0000000..4bf1929
> --- /dev/null
> +++ b/drivers/clk/omap/clk.c
> @@ -0,0 +1,39 @@
> +/*
> + * OMAP PRCM clock driver

maybe then prcm-clk.c ?

> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *     Tero Kristo <t-kristo@ti.com>
> + *     Mike Turquette <mturquette@linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clk/omap.h>
> +#include <linux/kernel.h>
> +#include <linux/of_device.h>
> +
> +/* FIXME - should the OMAP PRCM clock driver match generic types? */

should it? :)

> +static const struct of_device_id clk_match[] = {
> +	{.compatible = "fixed-clock", .data = of_fixed_clk_setup, },
drivers/clk/clk-fixed-rate.c seems to already do this with 
CLK_OF_DECLARE, or am I mistaken? and so on?
> +	{.compatible = "mux-clock", .data = of_mux_clk_setup, },
> +	{.compatible = "fixed-factor-clock",
> +		.data = of_fixed_factor_clk_setup, },
> +	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
> +	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
> +	{},
> +};
> +
> +/* FIXME - need to initialize early; skip real driver registration & probe */
> +int __init dt_omap_clk_init(void)

Might be good to have kernel doc to explain the init requirement as 
documented in commit message.

> +{
> +	of_clk_init(clk_match);

just doing of_clk_init(NULL); should do the job, no? that could even be 
a static inline OR introduced in board_generic without additional headers?

> +	return 0;
> +}
> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
> new file mode 100644
> index 0000000..647f02f
> --- /dev/null
> +++ b/include/linux/clk/omap.h
> @@ -0,0 +1,24 @@
> +/*
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.

would you like to match licensing to that of the C file?

> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> + */
> +
> +#ifndef __LINUX_CLK_OMAP_H_
> +#define __LINUX_CLK_OMAP_H_
> +
> +int __init dt_omap_clk_init(void);
> +
> +#endif
>


-- 
Regards,
Nishanth Menon

Re: [PATCHv4 02/33] clk: omap: introduce clock driver

[Tero Kristo]

On 07/30/2013 06:21 PM, Nishanth Menon wrote:
> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>> Parses OMAP clock data from DT and registers those clocks with the clock
>> framework.  dt_omap_clk_init must be called early during boot for timer
>> initialization so it is exported and called from the existing clock code
>> instead of probing like a real driver. Based on initial work done by
>> Mike Turquette.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> Cc: Mike Turquette <mturquette@linaro.org>
>> ---
>>   drivers/clk/Makefile      |    1 +
>>   drivers/clk/omap/Makefile |    1 +
>>   drivers/clk/omap/clk.c    |   39
>> +++++++++++++++++++++++++++++++++++++++
>
> Minor suggestion - should we just start drivers/clk/ti/ instead of
> clk/omap?
>
> AM335x/DRA7 are not "strictly OMAP".. might also allow for some reuse
> for other TI platforms..

Not sure, this idea has been bounced around a bit. samsung has its own 
directory under drivers/clk/ so maybe. I can change this if there is a 
strong wish for this.

>
>>   include/linux/clk/omap.h  |   24 ++++++++++++++++++++++++
>>   4 files changed, 65 insertions(+)
>>   create mode 100644 drivers/clk/omap/Makefile
>>   create mode 100644 drivers/clk/omap/clk.c
>>   create mode 100644 include/linux/clk/omap.h
>>
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index 4038c2b..d3c3733 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500)    += clk-vt8500.o
>>   obj-$(CONFIG_ARCH_ZYNQ)        += zynq/
>>   obj-$(CONFIG_ARCH_TEGRA)    += tegra/
>>   obj-$(CONFIG_PLAT_SAMSUNG)    += samsung/
>> +obj-$(CONFIG_ARCH_OMAP)        += omap/
>>
>>   obj-$(CONFIG_X86)        += x86/
>>
>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>> new file mode 100644
>> index 0000000..8195931
>> --- /dev/null
>> +++ b/drivers/clk/omap/Makefile
>> @@ -0,0 +1 @@
>> +obj-y                    += clk.o
>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>> new file mode 100644
>> index 0000000..4bf1929
>> --- /dev/null
>> +++ b/drivers/clk/omap/clk.c
>> @@ -0,0 +1,39 @@
>> +/*
>> + * OMAP PRCM clock driver
>
> maybe then prcm-clk.c ?

Maybe remove the PRCM part. We have some clocks behind i2c for example, 
and we might want to add support for them here.

>
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *     Tero Kristo <t-kristo@ti.com>
>> + *     Mike Turquette <mturquette@linaro.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/clk/omap.h>
>> +#include <linux/kernel.h>
>> +#include <linux/of_device.h>
>> +
>> +/* FIXME - should the OMAP PRCM clock driver match generic types? */
>
> should it? :)

Not 100% sure about the answer to this, the current implementation works 
though so we could potentially drop this comment. :)

>
>> +static const struct of_device_id clk_match[] = {
>> +    {.compatible = "fixed-clock", .data = of_fixed_clk_setup, },
> drivers/clk/clk-fixed-rate.c seems to already do this with
> CLK_OF_DECLARE, or am I mistaken? and so on?
>> +    {.compatible = "mux-clock", .data = of_mux_clk_setup, },
>> +    {.compatible = "fixed-factor-clock",
>> +        .data = of_fixed_factor_clk_setup, },
>> +    {.compatible = "divider-clock", .data = of_divider_clk_setup, },
>> +    {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>> +    {},
>> +};
>> +
>> +/* FIXME - need to initialize early; skip real driver registration &
>> probe */
>> +int __init dt_omap_clk_init(void)
>
> Might be good to have kernel doc to explain the init requirement as
> documented in commit message.

Yeah, I am lacking docs once again.

>
>> +{
>> +    of_clk_init(clk_match);
>
> just doing of_clk_init(NULL); should do the job, no? that could even be
> a static inline OR introduced in board_generic without additional headers?

I don't think that works, as we have special clock node types we want to 
support (the TI specific types, and we want to override the default 
behavior of some.)

>
>> +    return 0;
>> +}
>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>> new file mode 100644
>> index 0000000..647f02f
>> --- /dev/null
>> +++ b/include/linux/clk/omap.h
>> @@ -0,0 +1,24 @@
>> +/*
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>
> would you like to match licensing to that of the C file?

Ok, copy paste bug #2 for this. Initial version was worse than this though.

>
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
>> 02111-1307  USA
>> + */
>> +
>> +#ifndef __LINUX_CLK_OMAP_H_
>> +#define __LINUX_CLK_OMAP_H_
>> +
>> +int __init dt_omap_clk_init(void);
>> +
>> +#endif
>>
>
>

[PATCHv4 02/33] clk: omap: introduce clock driver

[Tero Kristo]

On 07/30/2013 06:21 PM, Nishanth Menon wrote:
> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>> Parses OMAP clock data from DT and registers those clocks with the clock
>> framework.  dt_omap_clk_init must be called early during boot for timer
>> initialization so it is exported and called from the existing clock code
>> instead of probing like a real driver. Based on initial work done by
>> Mike Turquette.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> Cc: Mike Turquette <mturquette@linaro.org>
>> ---
>>   drivers/clk/Makefile      |    1 +
>>   drivers/clk/omap/Makefile |    1 +
>>   drivers/clk/omap/clk.c    |   39
>> +++++++++++++++++++++++++++++++++++++++
>
> Minor suggestion - should we just start drivers/clk/ti/ instead of
> clk/omap?
>
> AM335x/DRA7 are not "strictly OMAP".. might also allow for some reuse
> for other TI platforms..

Not sure, this idea has been bounced around a bit. samsung has its own 
directory under drivers/clk/ so maybe. I can change this if there is a 
strong wish for this.

>
>>   include/linux/clk/omap.h  |   24 ++++++++++++++++++++++++
>>   4 files changed, 65 insertions(+)
>>   create mode 100644 drivers/clk/omap/Makefile
>>   create mode 100644 drivers/clk/omap/clk.c
>>   create mode 100644 include/linux/clk/omap.h
>>
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index 4038c2b..d3c3733 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500)    += clk-vt8500.o
>>   obj-$(CONFIG_ARCH_ZYNQ)        += zynq/
>>   obj-$(CONFIG_ARCH_TEGRA)    += tegra/
>>   obj-$(CONFIG_PLAT_SAMSUNG)    += samsung/
>> +obj-$(CONFIG_ARCH_OMAP)        += omap/
>>
>>   obj-$(CONFIG_X86)        += x86/
>>
>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>> new file mode 100644
>> index 0000000..8195931
>> --- /dev/null
>> +++ b/drivers/clk/omap/Makefile
>> @@ -0,0 +1 @@
>> +obj-y                    += clk.o
>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>> new file mode 100644
>> index 0000000..4bf1929
>> --- /dev/null
>> +++ b/drivers/clk/omap/clk.c
>> @@ -0,0 +1,39 @@
>> +/*
>> + * OMAP PRCM clock driver
>
> maybe then prcm-clk.c ?

Maybe remove the PRCM part. We have some clocks behind i2c for example, 
and we might want to add support for them here.

>
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *     Tero Kristo <t-kristo@ti.com>
>> + *     Mike Turquette <mturquette@linaro.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/clk/omap.h>
>> +#include <linux/kernel.h>
>> +#include <linux/of_device.h>
>> +
>> +/* FIXME - should the OMAP PRCM clock driver match generic types? */
>
> should it? :)

Not 100% sure about the answer to this, the current implementation works 
though so we could potentially drop this comment. :)

>
>> +static const struct of_device_id clk_match[] = {
>> +    {.compatible = "fixed-clock", .data = of_fixed_clk_setup, },
> drivers/clk/clk-fixed-rate.c seems to already do this with
> CLK_OF_DECLARE, or am I mistaken? and so on?
>> +    {.compatible = "mux-clock", .data = of_mux_clk_setup, },
>> +    {.compatible = "fixed-factor-clock",
>> +        .data = of_fixed_factor_clk_setup, },
>> +    {.compatible = "divider-clock", .data = of_divider_clk_setup, },
>> +    {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>> +    {},
>> +};
>> +
>> +/* FIXME - need to initialize early; skip real driver registration &
>> probe */
>> +int __init dt_omap_clk_init(void)
>
> Might be good to have kernel doc to explain the init requirement as
> documented in commit message.

Yeah, I am lacking docs once again.

>
>> +{
>> +    of_clk_init(clk_match);
>
> just doing of_clk_init(NULL); should do the job, no? that could even be
> a static inline OR introduced in board_generic without additional headers?

I don't think that works, as we have special clock node types we want to 
support (the TI specific types, and we want to override the default 
behavior of some.)

>
>> +    return 0;
>> +}
>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>> new file mode 100644
>> index 0000000..647f02f
>> --- /dev/null
>> +++ b/include/linux/clk/omap.h
>> @@ -0,0 +1,24 @@
>> +/*
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>
> would you like to match licensing to that of the C file?

Ok, copy paste bug #2 for this. Initial version was worse than this though.

>
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
>> 02111-1307  USA
>> + */
>> +
>> +#ifndef __LINUX_CLK_OMAP_H_
>> +#define __LINUX_CLK_OMAP_H_
>> +
>> +int __init dt_omap_clk_init(void);
>> +
>> +#endif
>>
>
>

Re: [PATCHv4 02/33] clk: omap: introduce clock driver

[Nishanth Menon]

On 07/31/2013 03:59 AM, Tero Kristo wrote:
> On 07/30/2013 06:21 PM, Nishanth Menon wrote:
>> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>>> Parses OMAP clock data from DT and registers those clocks with the clock
>>> framework.  dt_omap_clk_init must be called early during boot for timer
>>> initialization so it is exported and called from the existing clock code
>>> instead of probing like a real driver. Based on initial work done by
>>> Mike Turquette.
>>>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>> Cc: Mike Turquette <mturquette@linaro.org>
>>> ---
>>>   drivers/clk/Makefile      |    1 +
>>>   drivers/clk/omap/Makefile |    1 +
>>>   drivers/clk/omap/clk.c    |   39
>>> +++++++++++++++++++++++++++++++++++++++
>>
>> Minor suggestion - should we just start drivers/clk/ti/ instead of
>> clk/omap?
>>
>> AM335x/DRA7 are not "strictly OMAP".. might also allow for some reuse
>> for other TI platforms..
>
> Not sure, this idea has been bounced around a bit. samsung has its own
> directory under drivers/clk/ so maybe. I can change this if there is a
> strong wish for this.

just my 2 cents - if we use drivers/clk/ti, we can then move required 
stuff from arch/arm/mach-davinci or arch/arm/mach-keystone to a ti 
generic location allowing us to reuse things as needed.

>
>>
>>>   include/linux/clk/omap.h  |   24 ++++++++++++++++++++++++
>>>   4 files changed, 65 insertions(+)
>>>   create mode 100644 drivers/clk/omap/Makefile
>>>   create mode 100644 drivers/clk/omap/clk.c
>>>   create mode 100644 include/linux/clk/omap.h
>>>
>>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>>> index 4038c2b..d3c3733 100644
>>> --- a/drivers/clk/Makefile
>>> +++ b/drivers/clk/Makefile
>>> @@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500)    += clk-vt8500.o
>>>   obj-$(CONFIG_ARCH_ZYNQ)        += zynq/
>>>   obj-$(CONFIG_ARCH_TEGRA)    += tegra/
>>>   obj-$(CONFIG_PLAT_SAMSUNG)    += samsung/
>>> +obj-$(CONFIG_ARCH_OMAP)        += omap/
>>>
>>>   obj-$(CONFIG_X86)        += x86/
>>>
>>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>>> new file mode 100644
>>> index 0000000..8195931
>>> --- /dev/null
>>> +++ b/drivers/clk/omap/Makefile
>>> @@ -0,0 +1 @@
>>> +obj-y                    += clk.o
>>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>>> new file mode 100644
>>> index 0000000..4bf1929
>>> --- /dev/null
>>> +++ b/drivers/clk/omap/clk.c
>>> @@ -0,0 +1,39 @@
>>> +/*
>>> + * OMAP PRCM clock driver
>>
>> maybe then prcm-clk.c ?
>
> Maybe remove the PRCM part. We have some clocks behind i2c for example,
> and we might want to add support for them here.

I think we can actually drop this file in it's entirety if we stick with 
of_clk_init(NULL) and depend solely of CLK_OF_DECLARE from relevant drivers.

-- 
Regards,
Nishanth Menon

[PATCHv4 02/33] clk: omap: introduce clock driver

[Nishanth Menon]

On 07/31/2013 03:59 AM, Tero Kristo wrote:
> On 07/30/2013 06:21 PM, Nishanth Menon wrote:
>> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>>> Parses OMAP clock data from DT and registers those clocks with the clock
>>> framework.  dt_omap_clk_init must be called early during boot for timer
>>> initialization so it is exported and called from the existing clock code
>>> instead of probing like a real driver. Based on initial work done by
>>> Mike Turquette.
>>>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>> Cc: Mike Turquette <mturquette@linaro.org>
>>> ---
>>>   drivers/clk/Makefile      |    1 +
>>>   drivers/clk/omap/Makefile |    1 +
>>>   drivers/clk/omap/clk.c    |   39
>>> +++++++++++++++++++++++++++++++++++++++
>>
>> Minor suggestion - should we just start drivers/clk/ti/ instead of
>> clk/omap?
>>
>> AM335x/DRA7 are not "strictly OMAP".. might also allow for some reuse
>> for other TI platforms..
>
> Not sure, this idea has been bounced around a bit. samsung has its own
> directory under drivers/clk/ so maybe. I can change this if there is a
> strong wish for this.

just my 2 cents - if we use drivers/clk/ti, we can then move required 
stuff from arch/arm/mach-davinci or arch/arm/mach-keystone to a ti 
generic location allowing us to reuse things as needed.

>
>>
>>>   include/linux/clk/omap.h  |   24 ++++++++++++++++++++++++
>>>   4 files changed, 65 insertions(+)
>>>   create mode 100644 drivers/clk/omap/Makefile
>>>   create mode 100644 drivers/clk/omap/clk.c
>>>   create mode 100644 include/linux/clk/omap.h
>>>
>>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>>> index 4038c2b..d3c3733 100644
>>> --- a/drivers/clk/Makefile
>>> +++ b/drivers/clk/Makefile
>>> @@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500)    += clk-vt8500.o
>>>   obj-$(CONFIG_ARCH_ZYNQ)        += zynq/
>>>   obj-$(CONFIG_ARCH_TEGRA)    += tegra/
>>>   obj-$(CONFIG_PLAT_SAMSUNG)    += samsung/
>>> +obj-$(CONFIG_ARCH_OMAP)        += omap/
>>>
>>>   obj-$(CONFIG_X86)        += x86/
>>>
>>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>>> new file mode 100644
>>> index 0000000..8195931
>>> --- /dev/null
>>> +++ b/drivers/clk/omap/Makefile
>>> @@ -0,0 +1 @@
>>> +obj-y                    += clk.o
>>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>>> new file mode 100644
>>> index 0000000..4bf1929
>>> --- /dev/null
>>> +++ b/drivers/clk/omap/clk.c
>>> @@ -0,0 +1,39 @@
>>> +/*
>>> + * OMAP PRCM clock driver
>>
>> maybe then prcm-clk.c ?
>
> Maybe remove the PRCM part. We have some clocks behind i2c for example,
> and we might want to add support for them here.

I think we can actually drop this file in it's entirety if we stick with 
of_clk_init(NULL) and depend solely of CLK_OF_DECLARE from relevant drivers.

-- 
Regards,
Nishanth Menon

Re: [PATCHv4 02/33] clk: omap: introduce clock driver

[Tero Kristo]

On 08/01/2013 04:44 PM, Nishanth Menon wrote:
> On 07/31/2013 03:59 AM, Tero Kristo wrote:
>> On 07/30/2013 06:21 PM, Nishanth Menon wrote:
>>> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>>>> Parses OMAP clock data from DT and registers those clocks with the
>>>> clock
>>>> framework.  dt_omap_clk_init must be called early during boot for timer
>>>> initialization so it is exported and called from the existing clock
>>>> code
>>>> instead of probing like a real driver. Based on initial work done by
>>>> Mike Turquette.
>>>>
>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>> Cc: Mike Turquette <mturquette@linaro.org>
>>>> ---
>>>>   drivers/clk/Makefile      |    1 +
>>>>   drivers/clk/omap/Makefile |    1 +
>>>>   drivers/clk/omap/clk.c    |   39
>>>> +++++++++++++++++++++++++++++++++++++++
>>>
>>> Minor suggestion - should we just start drivers/clk/ti/ instead of
>>> clk/omap?
>>>
>>> AM335x/DRA7 are not "strictly OMAP".. might also allow for some reuse
>>> for other TI platforms..
>>
>> Not sure, this idea has been bounced around a bit. samsung has its own
>> directory under drivers/clk/ so maybe. I can change this if there is a
>> strong wish for this.
>
> just my 2 cents - if we use drivers/clk/ti, we can then move required
> stuff from arch/arm/mach-davinci or arch/arm/mach-keystone to a ti
> generic location allowing us to reuse things as needed.

Ok, I'll rename the dir.

>
>>
>>>
>>>>   include/linux/clk/omap.h  |   24 ++++++++++++++++++++++++
>>>>   4 files changed, 65 insertions(+)
>>>>   create mode 100644 drivers/clk/omap/Makefile
>>>>   create mode 100644 drivers/clk/omap/clk.c
>>>>   create mode 100644 include/linux/clk/omap.h
>>>>
>>>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>>>> index 4038c2b..d3c3733 100644
>>>> --- a/drivers/clk/Makefile
>>>> +++ b/drivers/clk/Makefile
>>>> @@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500)    += clk-vt8500.o
>>>>   obj-$(CONFIG_ARCH_ZYNQ)        += zynq/
>>>>   obj-$(CONFIG_ARCH_TEGRA)    += tegra/
>>>>   obj-$(CONFIG_PLAT_SAMSUNG)    += samsung/
>>>> +obj-$(CONFIG_ARCH_OMAP)        += omap/
>>>>
>>>>   obj-$(CONFIG_X86)        += x86/
>>>>
>>>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>>>> new file mode 100644
>>>> index 0000000..8195931
>>>> --- /dev/null
>>>> +++ b/drivers/clk/omap/Makefile
>>>> @@ -0,0 +1 @@
>>>> +obj-y                    += clk.o
>>>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>>>> new file mode 100644
>>>> index 0000000..4bf1929
>>>> --- /dev/null
>>>> +++ b/drivers/clk/omap/clk.c
>>>> @@ -0,0 +1,39 @@
>>>> +/*
>>>> + * OMAP PRCM clock driver
>>>
>>> maybe then prcm-clk.c ?
>>
>> Maybe remove the PRCM part. We have some clocks behind i2c for example,
>> and we might want to add support for them here.
>
> I think we can actually drop this file in it's entirety if we stick with
> of_clk_init(NULL) and depend solely of CLK_OF_DECLARE from relevant
> drivers.

Yeah, I'll do this and drop the file.

[PATCHv4 02/33] clk: omap: introduce clock driver

[Tero Kristo]

On 08/01/2013 04:44 PM, Nishanth Menon wrote:
> On 07/31/2013 03:59 AM, Tero Kristo wrote:
>> On 07/30/2013 06:21 PM, Nishanth Menon wrote:
>>> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>>>> Parses OMAP clock data from DT and registers those clocks with the
>>>> clock
>>>> framework.  dt_omap_clk_init must be called early during boot for timer
>>>> initialization so it is exported and called from the existing clock
>>>> code
>>>> instead of probing like a real driver. Based on initial work done by
>>>> Mike Turquette.
>>>>
>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>> Cc: Mike Turquette <mturquette@linaro.org>
>>>> ---
>>>>   drivers/clk/Makefile      |    1 +
>>>>   drivers/clk/omap/Makefile |    1 +
>>>>   drivers/clk/omap/clk.c    |   39
>>>> +++++++++++++++++++++++++++++++++++++++
>>>
>>> Minor suggestion - should we just start drivers/clk/ti/ instead of
>>> clk/omap?
>>>
>>> AM335x/DRA7 are not "strictly OMAP".. might also allow for some reuse
>>> for other TI platforms..
>>
>> Not sure, this idea has been bounced around a bit. samsung has its own
>> directory under drivers/clk/ so maybe. I can change this if there is a
>> strong wish for this.
>
> just my 2 cents - if we use drivers/clk/ti, we can then move required
> stuff from arch/arm/mach-davinci or arch/arm/mach-keystone to a ti
> generic location allowing us to reuse things as needed.

Ok, I'll rename the dir.

>
>>
>>>
>>>>   include/linux/clk/omap.h  |   24 ++++++++++++++++++++++++
>>>>   4 files changed, 65 insertions(+)
>>>>   create mode 100644 drivers/clk/omap/Makefile
>>>>   create mode 100644 drivers/clk/omap/clk.c
>>>>   create mode 100644 include/linux/clk/omap.h
>>>>
>>>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>>>> index 4038c2b..d3c3733 100644
>>>> --- a/drivers/clk/Makefile
>>>> +++ b/drivers/clk/Makefile
>>>> @@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_VT8500)    += clk-vt8500.o
>>>>   obj-$(CONFIG_ARCH_ZYNQ)        += zynq/
>>>>   obj-$(CONFIG_ARCH_TEGRA)    += tegra/
>>>>   obj-$(CONFIG_PLAT_SAMSUNG)    += samsung/
>>>> +obj-$(CONFIG_ARCH_OMAP)        += omap/
>>>>
>>>>   obj-$(CONFIG_X86)        += x86/
>>>>
>>>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>>>> new file mode 100644
>>>> index 0000000..8195931
>>>> --- /dev/null
>>>> +++ b/drivers/clk/omap/Makefile
>>>> @@ -0,0 +1 @@
>>>> +obj-y                    += clk.o
>>>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>>>> new file mode 100644
>>>> index 0000000..4bf1929
>>>> --- /dev/null
>>>> +++ b/drivers/clk/omap/clk.c
>>>> @@ -0,0 +1,39 @@
>>>> +/*
>>>> + * OMAP PRCM clock driver
>>>
>>> maybe then prcm-clk.c ?
>>
>> Maybe remove the PRCM part. We have some clocks behind i2c for example,
>> and we might want to add support for them here.
>
> I think we can actually drop this file in it's entirety if we stick with
> of_clk_init(NULL) and depend solely of CLK_OF_DECLARE from relevant
> drivers.

Yeah, I'll do this and drop the file.

[PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Tero Kristo]

The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/Makefile |    2 +-
 drivers/clk/omap/clk.c    |    1 +
 drivers/clk/omap/dpll.c   |  295 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 297 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/omap/dpll.c

diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index 8195931..4cad480 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1 +1 @@
-obj-y					+= clk.o
+obj-y					+= clk.o dpll.o
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index 4bf1929..1dafdaa 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -28,6 +28,7 @@ static const struct of_device_id clk_match[] = {
 		.data = of_fixed_factor_clk_setup, },
 	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
 	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
+	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
 	{},
 };
 
diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
new file mode 100644
index 0000000..66e82be
--- /dev/null
+++ b/drivers/clk/omap/dpll.c
@@ -0,0 +1,295 @@
+/*
+ * OMAP DPLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/omap.h>
+
+static const struct clk_ops dpll_m4xen_ck_ops = {
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.recalc_rate	= &omap4_dpll_regm4xen_recalc,
+	.round_rate	= &omap4_dpll_regm4xen_round_rate,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.get_parent	= &omap2_init_dpll_parent,
+};
+
+static const struct clk_ops dpll_core_ck_ops = {
+	.recalc_rate	= &omap3_dpll_recalc,
+	.get_parent	= &omap2_init_dpll_parent,
+};
+
+static const struct clk_ops dpll_ck_ops = {
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.round_rate	= &omap2_dpll_round_rate,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.get_parent	= &omap2_init_dpll_parent,
+	.init		= &omap2_init_clk_clkdm,
+};
+
+static const struct clk_ops dpll_x2_ck_ops = {
+	.recalc_rate	= &omap3_clkoutx2_recalc,
+};
+
+struct clk *omap_clk_register_dpll(struct device *dev, const char *name,
+		const char **parent_names, int num_parents, unsigned long flags,
+		struct dpll_data *dpll_data, const char *clkdm_name,
+		const struct clk_ops *ops)
+{
+	struct clk *clk;
+	struct clk_init_data init;
+	struct clk_hw_omap *clk_hw;
+
+	/* allocate the divider */
+	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk_hw->dpll_data = dpll_data;
+	clk_hw->ops = &clkhwops_omap3_dpll;
+	clk_hw->clkdm_name = clkdm_name;
+	clk_hw->hw.init = &init;
+
+	init.name = name;
+	init.ops = ops;
+	init.flags = flags;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+
+	/* register the clock */
+	clk = clk_register(dev, &clk_hw->hw);
+
+	if (IS_ERR(clk))
+		kfree(clk_hw);
+	else
+		omap2_init_clk_hw_omap_clocks(clk);
+
+	return clk;
+}
+
+struct clk *omap_clk_register_dpll_x2(struct device *dev, const char *name,
+		const char *parent_name, void __iomem *reg,
+		const struct clk_ops *ops)
+{
+	struct clk *clk;
+	struct clk_init_data init;
+	struct clk_hw_omap *clk_hw;
+
+	if (!parent_name) {
+		pr_err("%s: dpll_x2 must have parent\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk_hw->ops = &clkhwops_omap4_dpllmx;
+	clk_hw->clksel_reg = reg;
+	clk_hw->hw.init = &init;
+
+	init.name = name;
+	init.ops = ops;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	/* register the clock */
+	clk = clk_register(dev, &clk_hw->hw);
+
+	if (IS_ERR(clk))
+		kfree(clk_hw);
+	else
+		omap2_init_clk_hw_omap_clocks(clk);
+
+	return clk;
+}
+
+#ifdef CONFIG_OF
+
+/**
+ * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
+ */
+static void __init of_omap_dpll_setup(struct device_node *node,
+					const struct clk_ops *ops)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names;
+	const char *clkdm_name = NULL;
+	struct of_phandle_args clkspec;
+	u8 dpll_flags = 0;
+	struct dpll_data *dd;
+	u32 idlest_mask = 0x1;
+	u32 enable_mask = 0x7;
+	u32 autoidle_mask = 0x7;
+	u32 mult_mask = 0x7ff << 8;
+	u32 div1_mask = 0x7f;
+	u32 max_multiplier = 2047;
+	u32 max_divider = 128;
+	u32 min_divider = 1;
+	int i;
+
+	dd = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
+	if (!dd) {
+		pr_err("%s: could not allocate dpll_data\n", __func__);
+		return;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: omap dpll %s must have parent(s)\n",
+			__func__, node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	of_property_read_u32(node, "ti,idlest-mask", &idlest_mask);
+
+	of_property_read_u32(node, "ti,enable-mask", &enable_mask);
+
+	of_property_read_u32(node, "ti,autoidle-mask", &autoidle_mask);
+
+	clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
+	dd->clk_ref = of_clk_get_from_provider(&clkspec);
+	if (!dd->clk_ref) {
+		pr_err("%s: ti,clk-ref for %s not found\n", __func__,
+			clk_name);
+		goto cleanup;
+	}
+
+	clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
+	dd->clk_bypass = of_clk_get_from_provider(&clkspec);
+	if (!dd->clk_bypass) {
+		pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
+			clk_name);
+		goto cleanup;
+	}
+
+	of_property_read_string(node, "ti,clkdm-name", &clkdm_name);
+
+	dd->control_reg = of_iomap(node, 0);
+	dd->idlest_reg = of_iomap(node, 1);
+	dd->autoidle_reg = of_iomap(node, 2);
+	dd->mult_div1_reg = of_iomap(node, 3);
+
+	dd->idlest_mask = idlest_mask;
+	dd->enable_mask = enable_mask;
+	dd->autoidle_mask = autoidle_mask;
+
+	dd->modes = 0xa0;
+
+	if (of_property_read_bool(node, "ti,dpll-j-type")) {
+		dd->sddiv_mask = 0xff000000;
+		mult_mask = 0xfff << 8;
+		div1_mask = 0xff;
+		max_multiplier = 4095;
+		max_divider = 256;
+	}
+
+	if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
+		dd->m4xen_mask = 0x800;
+		dd->lpmode_mask = 1 << 10;
+	}
+
+	dd->mult_mask = mult_mask;
+	dd->div1_mask = div1_mask;
+	dd->max_multiplier = max_multiplier;
+	dd->max_divider = max_divider;
+	dd->min_divider = min_divider;
+
+	clk = omap_clk_register_dpll(NULL, clk_name, parent_names,
+				num_parents, dpll_flags, dd,
+				clkdm_name, ops);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	return;
+
+cleanup:
+	kfree(dd);
+	return;
+}
+
+static void __init of_omap_dpll_x2_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	void __iomem *reg;
+	const char *parent_name;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	parent_name = of_clk_get_parent_name(node, 0);
+
+	reg = of_iomap(node, 0);
+
+	clk = omap_clk_register_dpll_x2(NULL, clk_name, parent_name,
+				reg, &dpll_x2_ck_ops);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+
+__init void of_omap3_dpll_setup(struct device_node *node)
+{
+	/* XXX: to be done */
+}
+EXPORT_SYMBOL_GPL(of_omap3_dpll_setup);
+CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock", of_omap3_dpll_setup);
+
+__init void of_omap4_dpll_setup(struct device_node *node)
+{
+	const struct clk_ops *ops;
+
+	ops = &dpll_ck_ops;
+
+	if (of_property_read_bool(node, "ti,dpll-regm4xen"))
+		ops = &dpll_m4xen_ck_ops;
+
+	if (of_property_read_bool(node, "ti,dpll-core"))
+		ops = &dpll_core_ck_ops;
+
+	if (of_property_read_bool(node, "ti,dpll-clk-x2")) {
+		of_omap_dpll_x2_setup(node);
+		return;
+	}
+
+	of_omap_dpll_setup(node, ops);
+}
+EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
+CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock", of_omap4_dpll_setup);
+#endif
-- 
1.7.9.5

[PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Tero Kristo]

The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/Makefile |    2 +-
 drivers/clk/omap/clk.c    |    1 +
 drivers/clk/omap/dpll.c   |  295 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 297 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/omap/dpll.c

diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index 8195931..4cad480 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1 +1 @@
-obj-y					+= clk.o
+obj-y					+= clk.o dpll.o
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index 4bf1929..1dafdaa 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -28,6 +28,7 @@ static const struct of_device_id clk_match[] = {
 		.data = of_fixed_factor_clk_setup, },
 	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
 	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
+	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
 	{},
 };
 
diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
new file mode 100644
index 0000000..66e82be
--- /dev/null
+++ b/drivers/clk/omap/dpll.c
@@ -0,0 +1,295 @@
+/*
+ * OMAP DPLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/omap.h>
+
+static const struct clk_ops dpll_m4xen_ck_ops = {
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.recalc_rate	= &omap4_dpll_regm4xen_recalc,
+	.round_rate	= &omap4_dpll_regm4xen_round_rate,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.get_parent	= &omap2_init_dpll_parent,
+};
+
+static const struct clk_ops dpll_core_ck_ops = {
+	.recalc_rate	= &omap3_dpll_recalc,
+	.get_parent	= &omap2_init_dpll_parent,
+};
+
+static const struct clk_ops dpll_ck_ops = {
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.round_rate	= &omap2_dpll_round_rate,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.get_parent	= &omap2_init_dpll_parent,
+	.init		= &omap2_init_clk_clkdm,
+};
+
+static const struct clk_ops dpll_x2_ck_ops = {
+	.recalc_rate	= &omap3_clkoutx2_recalc,
+};
+
+struct clk *omap_clk_register_dpll(struct device *dev, const char *name,
+		const char **parent_names, int num_parents, unsigned long flags,
+		struct dpll_data *dpll_data, const char *clkdm_name,
+		const struct clk_ops *ops)
+{
+	struct clk *clk;
+	struct clk_init_data init;
+	struct clk_hw_omap *clk_hw;
+
+	/* allocate the divider */
+	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk_hw->dpll_data = dpll_data;
+	clk_hw->ops = &clkhwops_omap3_dpll;
+	clk_hw->clkdm_name = clkdm_name;
+	clk_hw->hw.init = &init;
+
+	init.name = name;
+	init.ops = ops;
+	init.flags = flags;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+
+	/* register the clock */
+	clk = clk_register(dev, &clk_hw->hw);
+
+	if (IS_ERR(clk))
+		kfree(clk_hw);
+	else
+		omap2_init_clk_hw_omap_clocks(clk);
+
+	return clk;
+}
+
+struct clk *omap_clk_register_dpll_x2(struct device *dev, const char *name,
+		const char *parent_name, void __iomem *reg,
+		const struct clk_ops *ops)
+{
+	struct clk *clk;
+	struct clk_init_data init;
+	struct clk_hw_omap *clk_hw;
+
+	if (!parent_name) {
+		pr_err("%s: dpll_x2 must have parent\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk_hw->ops = &clkhwops_omap4_dpllmx;
+	clk_hw->clksel_reg = reg;
+	clk_hw->hw.init = &init;
+
+	init.name = name;
+	init.ops = ops;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	/* register the clock */
+	clk = clk_register(dev, &clk_hw->hw);
+
+	if (IS_ERR(clk))
+		kfree(clk_hw);
+	else
+		omap2_init_clk_hw_omap_clocks(clk);
+
+	return clk;
+}
+
+#ifdef CONFIG_OF
+
+/**
+ * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
+ */
+static void __init of_omap_dpll_setup(struct device_node *node,
+					const struct clk_ops *ops)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names;
+	const char *clkdm_name = NULL;
+	struct of_phandle_args clkspec;
+	u8 dpll_flags = 0;
+	struct dpll_data *dd;
+	u32 idlest_mask = 0x1;
+	u32 enable_mask = 0x7;
+	u32 autoidle_mask = 0x7;
+	u32 mult_mask = 0x7ff << 8;
+	u32 div1_mask = 0x7f;
+	u32 max_multiplier = 2047;
+	u32 max_divider = 128;
+	u32 min_divider = 1;
+	int i;
+
+	dd = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
+	if (!dd) {
+		pr_err("%s: could not allocate dpll_data\n", __func__);
+		return;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: omap dpll %s must have parent(s)\n",
+			__func__, node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	of_property_read_u32(node, "ti,idlest-mask", &idlest_mask);
+
+	of_property_read_u32(node, "ti,enable-mask", &enable_mask);
+
+	of_property_read_u32(node, "ti,autoidle-mask", &autoidle_mask);
+
+	clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
+	dd->clk_ref = of_clk_get_from_provider(&clkspec);
+	if (!dd->clk_ref) {
+		pr_err("%s: ti,clk-ref for %s not found\n", __func__,
+			clk_name);
+		goto cleanup;
+	}
+
+	clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
+	dd->clk_bypass = of_clk_get_from_provider(&clkspec);
+	if (!dd->clk_bypass) {
+		pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
+			clk_name);
+		goto cleanup;
+	}
+
+	of_property_read_string(node, "ti,clkdm-name", &clkdm_name);
+
+	dd->control_reg = of_iomap(node, 0);
+	dd->idlest_reg = of_iomap(node, 1);
+	dd->autoidle_reg = of_iomap(node, 2);
+	dd->mult_div1_reg = of_iomap(node, 3);
+
+	dd->idlest_mask = idlest_mask;
+	dd->enable_mask = enable_mask;
+	dd->autoidle_mask = autoidle_mask;
+
+	dd->modes = 0xa0;
+
+	if (of_property_read_bool(node, "ti,dpll-j-type")) {
+		dd->sddiv_mask = 0xff000000;
+		mult_mask = 0xfff << 8;
+		div1_mask = 0xff;
+		max_multiplier = 4095;
+		max_divider = 256;
+	}
+
+	if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
+		dd->m4xen_mask = 0x800;
+		dd->lpmode_mask = 1 << 10;
+	}
+
+	dd->mult_mask = mult_mask;
+	dd->div1_mask = div1_mask;
+	dd->max_multiplier = max_multiplier;
+	dd->max_divider = max_divider;
+	dd->min_divider = min_divider;
+
+	clk = omap_clk_register_dpll(NULL, clk_name, parent_names,
+				num_parents, dpll_flags, dd,
+				clkdm_name, ops);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	return;
+
+cleanup:
+	kfree(dd);
+	return;
+}
+
+static void __init of_omap_dpll_x2_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	void __iomem *reg;
+	const char *parent_name;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	parent_name = of_clk_get_parent_name(node, 0);
+
+	reg = of_iomap(node, 0);
+
+	clk = omap_clk_register_dpll_x2(NULL, clk_name, parent_name,
+				reg, &dpll_x2_ck_ops);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+
+__init void of_omap3_dpll_setup(struct device_node *node)
+{
+	/* XXX: to be done */
+}
+EXPORT_SYMBOL_GPL(of_omap3_dpll_setup);
+CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock", of_omap3_dpll_setup);
+
+__init void of_omap4_dpll_setup(struct device_node *node)
+{
+	const struct clk_ops *ops;
+
+	ops = &dpll_ck_ops;
+
+	if (of_property_read_bool(node, "ti,dpll-regm4xen"))
+		ops = &dpll_m4xen_ck_ops;
+
+	if (of_property_read_bool(node, "ti,dpll-core"))
+		ops = &dpll_core_ck_ops;
+
+	if (of_property_read_bool(node, "ti,dpll-clk-x2")) {
+		of_omap_dpll_x2_setup(node);
+		return;
+	}
+
+	of_omap_dpll_setup(node, ops);
+}
+EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
+CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock", of_omap4_dpll_setup);
+#endif
-- 
1.7.9.5

Re: [PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Nishanth Menon]

This patch probably was submitted in the wrong sequence - fails build 
and few other issues below.

On 07/23/2013 02:19 AM, Tero Kristo wrote:
> The OMAP clock driver now supports DPLL clock type. This patch also
> adds support for DT DPLL nodes.

Then why is $subject specific to OMAP4? is that because of 
of_omap4_dpll_setup?

>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/Makefile |    2 +-
>   drivers/clk/omap/clk.c    |    1 +
>   drivers/clk/omap/dpll.c   |  295 +++++++++++++++++++++++++++++++++++++++++++++

Device Tree Binding documentation?

>   3 files changed, 297 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/clk/omap/dpll.c
>
> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
> index 8195931..4cad480 100644
> --- a/drivers/clk/omap/Makefile
> +++ b/drivers/clk/omap/Makefile
> @@ -1 +1 @@
> -obj-y					+= clk.o
> +obj-y					+= clk.o dpll.o
> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
> index 4bf1929..1dafdaa 100644
> --- a/drivers/clk/omap/clk.c
> +++ b/drivers/clk/omap/clk.c
> @@ -28,6 +28,7 @@ static const struct of_device_id clk_match[] = {
>   		.data = of_fixed_factor_clk_setup, },
>   	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
>   	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
> +	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
>   	{},
>   };
you would not need this if you did just of_clk_init(NULL); ?

Further, at this patch, build fails with:
drivers/clk/omap/clk.c:31:55: error: undefined identifier 
'of_omap4_dpll_setup'
drivers/clk/omap/clk.c:31:48: error: ‘of_omap4_dpll_setup’ undeclared 
here (not in a function)

which makes sense since we did not export the function.	
>
> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
> new file mode 100644
> index 0000000..66e82be
> --- /dev/null
> +++ b/drivers/clk/omap/dpll.c
> @@ -0,0 +1,295 @@
> +/*
> + * OMAP DPLL clock support
> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * Tero Kristo <t-kristo@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/string.h>
> +#include <linux/log2.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
after a quick check, are all these required?

> +#include <linux/clk/omap.h>

why?

> +
> +static const struct clk_ops dpll_m4xen_ck_ops = {
> +	.enable		= &omap3_noncore_dpll_enable,
> +	.disable	= &omap3_noncore_dpll_disable,
> +	.recalc_rate	= &omap4_dpll_regm4xen_recalc,
> +	.round_rate	= &omap4_dpll_regm4xen_round_rate,
> +	.set_rate	= &omap3_noncore_dpll_set_rate,
> +	.get_parent	= &omap2_init_dpll_parent,
> +};
> +
> +static const struct clk_ops dpll_core_ck_ops = {
> +	.recalc_rate	= &omap3_dpll_recalc,
> +	.get_parent	= &omap2_init_dpll_parent,
> +};
> +
> +static const struct clk_ops dpll_ck_ops = {
> +	.enable		= &omap3_noncore_dpll_enable,
> +	.disable	= &omap3_noncore_dpll_disable,
> +	.recalc_rate	= &omap3_dpll_recalc,
> +	.round_rate	= &omap2_dpll_round_rate,
> +	.set_rate	= &omap3_noncore_dpll_set_rate,
> +	.get_parent	= &omap2_init_dpll_parent,
> +	.init		= &omap2_init_clk_clkdm,
> +};
> +
> +static const struct clk_ops dpll_x2_ck_ops = {
> +	.recalc_rate	= &omap3_clkoutx2_recalc,
> +};

none of these are defined at this stage of the patch, generates a huge 
build error for dpll.c
http://pastebin.com/GJucv1A5
> +
> +struct clk *omap_clk_register_dpll(struct device *dev, const char *name,
> +		const char **parent_names, int num_parents, unsigned long flags,
> +		struct dpll_data *dpll_data, const char *clkdm_name,
> +		const struct clk_ops *ops)

why should this be public?

> +{
> +	struct clk *clk;
> +	struct clk_init_data init;

init = { 0 };  just to future proof?

> +	struct clk_hw_omap *clk_hw;

does not exist yet in generic header?

I am assuming you do not do parameter check as you expect clk_register 
to do the same?

> +
> +	/* allocate the divider */
> +	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
checkpatch complained:
CHECK: Prefer kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct 
clk_hw_omap)...)

or given we have dev, devm_kzalloc?
> +	if (!clk_hw) {
> +		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	clk_hw->dpll_data = dpll_data;
> +	clk_hw->ops = &clkhwops_omap3_dpll;
> +	clk_hw->clkdm_name = clkdm_name;
> +	clk_hw->hw.init = &init;
> +
> +	init.name = name;
> +	init.ops = ops;
> +	init.flags = flags;
> +	init.parent_names = parent_names;
> +	init.num_parents = num_parents;
> +
> +	/* register the clock */
> +	clk = clk_register(dev, &clk_hw->hw);
> +
> +	if (IS_ERR(clk))
> +		kfree(clk_hw);
> +	else
> +		omap2_init_clk_hw_omap_clocks(clk);
what if init fails? and it is in mach-omap2 at this point in time?

> +
> +	return clk;
> +}
> +
> +struct clk *omap_clk_register_dpll_x2(struct device *dev, const char *name,
> +		const char *parent_name, void __iomem *reg,
> +		const struct clk_ops *ops)

same question here as well

> +{
> +	struct clk *clk;
> +	struct clk_init_data init;
> +	struct clk_hw_omap *clk_hw;
> +
> +	if (!parent_name) {
> +		pr_err("%s: dpll_x2 must have parent\n", __func__);
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
checkpatch complained:
CHECK: Prefer kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct 
clk_hw_omap)...)

or devm_kzalloc?

> +	if (!clk_hw) {
> +		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	clk_hw->ops = &clkhwops_omap4_dpllmx;
> +	clk_hw->clksel_reg = reg;
> +	clk_hw->hw.init = &init;
> +
> +	init.name = name;
> +	init.ops = ops;
> +	init.parent_names = &parent_name;
> +	init.num_parents = 1;
> +
> +	/* register the clock */
> +	clk = clk_register(dev, &clk_hw->hw);
> +
> +	if (IS_ERR(clk))
> +		kfree(clk_hw);
> +	else
> +		omap2_init_clk_hw_omap_clocks(clk);
> +
> +	return clk;
> +}
this vaguely sounds like a replica of omap_clk_register_dpll with 
num_parents and clk_hw->ops different. why not merge the two?

> +
> +#ifdef CONFIG_OF

why not build the entire thing *iff* CONFIG_OF (Makefile/Kconfig dep)? 
that way, we can drop this #ifdef stuff from drivers that dont need to 
have dual support.

> +
> +/**
> + * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks

node and ops not documented.

> + */
> +static void __init of_omap_dpll_setup(struct device_node *node,
> +					const struct clk_ops *ops)
> +{
> +	struct clk *clk;
> +	const char *clk_name = node->name;
> +	int num_parents;
> +	const char **parent_names;
> +	const char *clkdm_name = NULL;
> +	struct of_phandle_args clkspec;
> +	u8 dpll_flags = 0;
> +	struct dpll_data *dd;
> +	u32 idlest_mask = 0x1;
> +	u32 enable_mask = 0x7;
> +	u32 autoidle_mask = 0x7;
> +	u32 mult_mask = 0x7ff << 8;
> +	u32 div1_mask = 0x7f;
> +	u32 max_multiplier = 2047;
> +	u32 max_divider = 128;
> +	u32 min_divider = 1;
> +	int i;
> +
> +	dd = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
kzalloc sizeof(*dd) ?

> +	if (!dd) {
> +		pr_err("%s: could not allocate dpll_data\n", __func__);
> +		return;
> +	}
> +
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +
> +	num_parents = of_clk_get_parent_count(node);
> +	if (num_parents < 1) {
> +		pr_err("%s: omap dpll %s must have parent(s)\n",
> +			__func__, node->name);

checkpatch complained:
CHECK: Alignment should match open parenthesis
#212: FILE: drivers/clk/omap/dpll.c:171:
After applying the patch, I think you should make __func__ aligned with 
" and not %

> +		goto cleanup;
> +	}
> +
> +	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
> +
> +	for (i = 0; i < num_parents; i++)
> +		parent_names[i] = of_clk_get_parent_name(node, i);
> +
> +	of_property_read_u32(node, "ti,idlest-mask", &idlest_mask);
> +
> +	of_property_read_u32(node, "ti,enable-mask", &enable_mask);
> +
> +	of_property_read_u32(node, "ti,autoidle-mask", &autoidle_mask);

are these going to be different? or can we catch with compatible flag?

> +
> +	clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
> +	dd->clk_ref = of_clk_get_from_provider(&clkspec);
> +	if (!dd->clk_ref) {
> +		pr_err("%s: ti,clk-ref for %s not found\n", __func__,
> +			clk_name);

CHECK: Alignment should match open parenthesis
#231: FILE: drivers/clk/omap/dpll.c:190:
similar issue here.

> +		goto cleanup;
> +	}
> +
> +	clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
> +	dd->clk_bypass = of_clk_get_from_provider(&clkspec);
> +	if (!dd->clk_bypass) {
> +		pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
> +			clk_name);

here as well

> +		goto cleanup;
> +	}
> +
> +	of_property_read_string(node, "ti,clkdm-name", &clkdm_name);
> +
> +	dd->control_reg = of_iomap(node, 0);
> +	dd->idlest_reg = of_iomap(node, 1);
> +	dd->autoidle_reg = of_iomap(node, 2);
> +	dd->mult_div1_reg = of_iomap(node, 3);

if dts has errors, should we not verify mandatory parameters?

> +
> +	dd->idlest_mask = idlest_mask;
> +	dd->enable_mask = enable_mask;
> +	dd->autoidle_mask = autoidle_mask;
> +
> +	dd->modes = 0xa0;

what is 0xa0?

> +
> +	if (of_property_read_bool(node, "ti,dpll-j-type")) {
> +		dd->sddiv_mask = 0xff000000;
> +		mult_mask = 0xfff << 8;
> +		div1_mask = 0xff;
> +		max_multiplier = 4095;
> +		max_divider = 256;
> +	}
> +
> +	if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
I think we need bindings to understand this better.

> +		dd->m4xen_mask = 0x800;
> +		dd->lpmode_mask = 1 << 10;
> +	}
> +
> +	dd->mult_mask = mult_mask;
> +	dd->div1_mask = div1_mask;
> +	dd->max_multiplier = max_multiplier;
> +	dd->max_divider = max_divider;
> +	dd->min_divider = min_divider;
> +
> +	clk = omap_clk_register_dpll(NULL, clk_name, parent_names,
> +				num_parents, dpll_flags, dd,
> +				clkdm_name, ops);
> +
> +	if (!IS_ERR(clk))
> +		of_clk_add_provider(node, of_clk_src_simple_get, clk);
error check?
> +	return;
> +
> +cleanup:

kfree(parent_names) ?

> +	kfree(dd);
> +	return;
> +}
> +
> +static void __init of_omap_dpll_x2_setup(struct device_node *node)
> +{
> +	struct clk *clk;
> +	const char *clk_name = node->name;
> +	void __iomem *reg;
> +	const char *parent_name;
> +
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +
> +	parent_name = of_clk_get_parent_name(node, 0);
> +
> +	reg = of_iomap(node, 0);

if dts has errors, should we not verify mandatory parameters?

> +
> +	clk = omap_clk_register_dpll_x2(NULL, clk_name, parent_name,
> +				reg, &dpll_x2_ck_ops);
> +
> +	if (!IS_ERR(clk))
> +		of_clk_add_provider(node, of_clk_src_simple_get, clk);
error check?

gentle request - in this setup function we dont see a return of error 
value (which makes sense), but more importantly - log saying that node 
was not setup

> +}
> +
> +__init void of_omap3_dpll_setup(struct device_node *node)

^^ void __init? further, you could make this static.

> +{
> +	/* XXX: to be done */
> +}
> +EXPORT_SYMBOL_GPL(of_omap3_dpll_setup);

you can drop the export if you use of_clk_init(NULL);

> +CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock", of_omap3_dpll_setup);
> +
> +__init void of_omap4_dpll_setup(struct device_node *node)

^^ void __init? further, you could make this static.

> +{
> +	const struct clk_ops *ops;
> +
> +	ops = &dpll_ck_ops;
> +
> +	if (of_property_read_bool(node, "ti,dpll-regm4xen"))
> +		ops = &dpll_m4xen_ck_ops;
> +
> +	if (of_property_read_bool(node, "ti,dpll-core"))
> +		ops = &dpll_core_ck_ops;
> +
> +	if (of_property_read_bool(node, "ti,dpll-clk-x2")) {
> +		of_omap_dpll_x2_setup(node);
> +		return;
> +	}
> +
> +	of_omap_dpll_setup(node, ops);
> +}
> +EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);

you can drop the export if you use of_clk_init(NULL);

> +CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock", of_omap4_dpll_setup);
> +#endif
>
-- 
Regards,
Nishanth Menon

[PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Nishanth Menon]

This patch probably was submitted in the wrong sequence - fails build 
and few other issues below.

On 07/23/2013 02:19 AM, Tero Kristo wrote:
> The OMAP clock driver now supports DPLL clock type. This patch also
> adds support for DT DPLL nodes.

Then why is $subject specific to OMAP4? is that because of 
of_omap4_dpll_setup?

>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/Makefile |    2 +-
>   drivers/clk/omap/clk.c    |    1 +
>   drivers/clk/omap/dpll.c   |  295 +++++++++++++++++++++++++++++++++++++++++++++

Device Tree Binding documentation?

>   3 files changed, 297 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/clk/omap/dpll.c
>
> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
> index 8195931..4cad480 100644
> --- a/drivers/clk/omap/Makefile
> +++ b/drivers/clk/omap/Makefile
> @@ -1 +1 @@
> -obj-y					+= clk.o
> +obj-y					+= clk.o dpll.o
> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
> index 4bf1929..1dafdaa 100644
> --- a/drivers/clk/omap/clk.c
> +++ b/drivers/clk/omap/clk.c
> @@ -28,6 +28,7 @@ static const struct of_device_id clk_match[] = {
>   		.data = of_fixed_factor_clk_setup, },
>   	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
>   	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
> +	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
>   	{},
>   };
you would not need this if you did just of_clk_init(NULL); ?

Further, at this patch, build fails with:
drivers/clk/omap/clk.c:31:55: error: undefined identifier 
'of_omap4_dpll_setup'
drivers/clk/omap/clk.c:31:48: error: ?of_omap4_dpll_setup? undeclared 
here (not in a function)

which makes sense since we did not export the function.	
>
> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
> new file mode 100644
> index 0000000..66e82be
> --- /dev/null
> +++ b/drivers/clk/omap/dpll.c
> @@ -0,0 +1,295 @@
> +/*
> + * OMAP DPLL clock support
> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * Tero Kristo <t-kristo@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/string.h>
> +#include <linux/log2.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
after a quick check, are all these required?

> +#include <linux/clk/omap.h>

why?

> +
> +static const struct clk_ops dpll_m4xen_ck_ops = {
> +	.enable		= &omap3_noncore_dpll_enable,
> +	.disable	= &omap3_noncore_dpll_disable,
> +	.recalc_rate	= &omap4_dpll_regm4xen_recalc,
> +	.round_rate	= &omap4_dpll_regm4xen_round_rate,
> +	.set_rate	= &omap3_noncore_dpll_set_rate,
> +	.get_parent	= &omap2_init_dpll_parent,
> +};
> +
> +static const struct clk_ops dpll_core_ck_ops = {
> +	.recalc_rate	= &omap3_dpll_recalc,
> +	.get_parent	= &omap2_init_dpll_parent,
> +};
> +
> +static const struct clk_ops dpll_ck_ops = {
> +	.enable		= &omap3_noncore_dpll_enable,
> +	.disable	= &omap3_noncore_dpll_disable,
> +	.recalc_rate	= &omap3_dpll_recalc,
> +	.round_rate	= &omap2_dpll_round_rate,
> +	.set_rate	= &omap3_noncore_dpll_set_rate,
> +	.get_parent	= &omap2_init_dpll_parent,
> +	.init		= &omap2_init_clk_clkdm,
> +};
> +
> +static const struct clk_ops dpll_x2_ck_ops = {
> +	.recalc_rate	= &omap3_clkoutx2_recalc,
> +};

none of these are defined at this stage of the patch, generates a huge 
build error for dpll.c
http://pastebin.com/GJucv1A5
> +
> +struct clk *omap_clk_register_dpll(struct device *dev, const char *name,
> +		const char **parent_names, int num_parents, unsigned long flags,
> +		struct dpll_data *dpll_data, const char *clkdm_name,
> +		const struct clk_ops *ops)

why should this be public?

> +{
> +	struct clk *clk;
> +	struct clk_init_data init;

init = { 0 };  just to future proof?

> +	struct clk_hw_omap *clk_hw;

does not exist yet in generic header?

I am assuming you do not do parameter check as you expect clk_register 
to do the same?

> +
> +	/* allocate the divider */
> +	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
checkpatch complained:
CHECK: Prefer kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct 
clk_hw_omap)...)

or given we have dev, devm_kzalloc?
> +	if (!clk_hw) {
> +		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	clk_hw->dpll_data = dpll_data;
> +	clk_hw->ops = &clkhwops_omap3_dpll;
> +	clk_hw->clkdm_name = clkdm_name;
> +	clk_hw->hw.init = &init;
> +
> +	init.name = name;
> +	init.ops = ops;
> +	init.flags = flags;
> +	init.parent_names = parent_names;
> +	init.num_parents = num_parents;
> +
> +	/* register the clock */
> +	clk = clk_register(dev, &clk_hw->hw);
> +
> +	if (IS_ERR(clk))
> +		kfree(clk_hw);
> +	else
> +		omap2_init_clk_hw_omap_clocks(clk);
what if init fails? and it is in mach-omap2 at this point in time?

> +
> +	return clk;
> +}
> +
> +struct clk *omap_clk_register_dpll_x2(struct device *dev, const char *name,
> +		const char *parent_name, void __iomem *reg,
> +		const struct clk_ops *ops)

same question here as well

> +{
> +	struct clk *clk;
> +	struct clk_init_data init;
> +	struct clk_hw_omap *clk_hw;
> +
> +	if (!parent_name) {
> +		pr_err("%s: dpll_x2 must have parent\n", __func__);
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
checkpatch complained:
CHECK: Prefer kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct 
clk_hw_omap)...)

or devm_kzalloc?

> +	if (!clk_hw) {
> +		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	clk_hw->ops = &clkhwops_omap4_dpllmx;
> +	clk_hw->clksel_reg = reg;
> +	clk_hw->hw.init = &init;
> +
> +	init.name = name;
> +	init.ops = ops;
> +	init.parent_names = &parent_name;
> +	init.num_parents = 1;
> +
> +	/* register the clock */
> +	clk = clk_register(dev, &clk_hw->hw);
> +
> +	if (IS_ERR(clk))
> +		kfree(clk_hw);
> +	else
> +		omap2_init_clk_hw_omap_clocks(clk);
> +
> +	return clk;
> +}
this vaguely sounds like a replica of omap_clk_register_dpll with 
num_parents and clk_hw->ops different. why not merge the two?

> +
> +#ifdef CONFIG_OF

why not build the entire thing *iff* CONFIG_OF (Makefile/Kconfig dep)? 
that way, we can drop this #ifdef stuff from drivers that dont need to 
have dual support.

> +
> +/**
> + * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks

node and ops not documented.

> + */
> +static void __init of_omap_dpll_setup(struct device_node *node,
> +					const struct clk_ops *ops)
> +{
> +	struct clk *clk;
> +	const char *clk_name = node->name;
> +	int num_parents;
> +	const char **parent_names;
> +	const char *clkdm_name = NULL;
> +	struct of_phandle_args clkspec;
> +	u8 dpll_flags = 0;
> +	struct dpll_data *dd;
> +	u32 idlest_mask = 0x1;
> +	u32 enable_mask = 0x7;
> +	u32 autoidle_mask = 0x7;
> +	u32 mult_mask = 0x7ff << 8;
> +	u32 div1_mask = 0x7f;
> +	u32 max_multiplier = 2047;
> +	u32 max_divider = 128;
> +	u32 min_divider = 1;
> +	int i;
> +
> +	dd = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
kzalloc sizeof(*dd) ?

> +	if (!dd) {
> +		pr_err("%s: could not allocate dpll_data\n", __func__);
> +		return;
> +	}
> +
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +
> +	num_parents = of_clk_get_parent_count(node);
> +	if (num_parents < 1) {
> +		pr_err("%s: omap dpll %s must have parent(s)\n",
> +			__func__, node->name);

checkpatch complained:
CHECK: Alignment should match open parenthesis
#212: FILE: drivers/clk/omap/dpll.c:171:
After applying the patch, I think you should make __func__ aligned with 
" and not %

> +		goto cleanup;
> +	}
> +
> +	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
> +
> +	for (i = 0; i < num_parents; i++)
> +		parent_names[i] = of_clk_get_parent_name(node, i);
> +
> +	of_property_read_u32(node, "ti,idlest-mask", &idlest_mask);
> +
> +	of_property_read_u32(node, "ti,enable-mask", &enable_mask);
> +
> +	of_property_read_u32(node, "ti,autoidle-mask", &autoidle_mask);

are these going to be different? or can we catch with compatible flag?

> +
> +	clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
> +	dd->clk_ref = of_clk_get_from_provider(&clkspec);
> +	if (!dd->clk_ref) {
> +		pr_err("%s: ti,clk-ref for %s not found\n", __func__,
> +			clk_name);

CHECK: Alignment should match open parenthesis
#231: FILE: drivers/clk/omap/dpll.c:190:
similar issue here.

> +		goto cleanup;
> +	}
> +
> +	clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
> +	dd->clk_bypass = of_clk_get_from_provider(&clkspec);
> +	if (!dd->clk_bypass) {
> +		pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
> +			clk_name);

here as well

> +		goto cleanup;
> +	}
> +
> +	of_property_read_string(node, "ti,clkdm-name", &clkdm_name);
> +
> +	dd->control_reg = of_iomap(node, 0);
> +	dd->idlest_reg = of_iomap(node, 1);
> +	dd->autoidle_reg = of_iomap(node, 2);
> +	dd->mult_div1_reg = of_iomap(node, 3);

if dts has errors, should we not verify mandatory parameters?

> +
> +	dd->idlest_mask = idlest_mask;
> +	dd->enable_mask = enable_mask;
> +	dd->autoidle_mask = autoidle_mask;
> +
> +	dd->modes = 0xa0;

what is 0xa0?

> +
> +	if (of_property_read_bool(node, "ti,dpll-j-type")) {
> +		dd->sddiv_mask = 0xff000000;
> +		mult_mask = 0xfff << 8;
> +		div1_mask = 0xff;
> +		max_multiplier = 4095;
> +		max_divider = 256;
> +	}
> +
> +	if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
I think we need bindings to understand this better.

> +		dd->m4xen_mask = 0x800;
> +		dd->lpmode_mask = 1 << 10;
> +	}
> +
> +	dd->mult_mask = mult_mask;
> +	dd->div1_mask = div1_mask;
> +	dd->max_multiplier = max_multiplier;
> +	dd->max_divider = max_divider;
> +	dd->min_divider = min_divider;
> +
> +	clk = omap_clk_register_dpll(NULL, clk_name, parent_names,
> +				num_parents, dpll_flags, dd,
> +				clkdm_name, ops);
> +
> +	if (!IS_ERR(clk))
> +		of_clk_add_provider(node, of_clk_src_simple_get, clk);
error check?
> +	return;
> +
> +cleanup:

kfree(parent_names) ?

> +	kfree(dd);
> +	return;
> +}
> +
> +static void __init of_omap_dpll_x2_setup(struct device_node *node)
> +{
> +	struct clk *clk;
> +	const char *clk_name = node->name;
> +	void __iomem *reg;
> +	const char *parent_name;
> +
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +
> +	parent_name = of_clk_get_parent_name(node, 0);
> +
> +	reg = of_iomap(node, 0);

if dts has errors, should we not verify mandatory parameters?

> +
> +	clk = omap_clk_register_dpll_x2(NULL, clk_name, parent_name,
> +				reg, &dpll_x2_ck_ops);
> +
> +	if (!IS_ERR(clk))
> +		of_clk_add_provider(node, of_clk_src_simple_get, clk);
error check?

gentle request - in this setup function we dont see a return of error 
value (which makes sense), but more importantly - log saying that node 
was not setup

> +}
> +
> +__init void of_omap3_dpll_setup(struct device_node *node)

^^ void __init? further, you could make this static.

> +{
> +	/* XXX: to be done */
> +}
> +EXPORT_SYMBOL_GPL(of_omap3_dpll_setup);

you can drop the export if you use of_clk_init(NULL);

> +CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock", of_omap3_dpll_setup);
> +
> +__init void of_omap4_dpll_setup(struct device_node *node)

^^ void __init? further, you could make this static.

> +{
> +	const struct clk_ops *ops;
> +
> +	ops = &dpll_ck_ops;
> +
> +	if (of_property_read_bool(node, "ti,dpll-regm4xen"))
> +		ops = &dpll_m4xen_ck_ops;
> +
> +	if (of_property_read_bool(node, "ti,dpll-core"))
> +		ops = &dpll_core_ck_ops;
> +
> +	if (of_property_read_bool(node, "ti,dpll-clk-x2")) {
> +		of_omap_dpll_x2_setup(node);
> +		return;
> +	}
> +
> +	of_omap_dpll_setup(node, ops);
> +}
> +EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);

you can drop the export if you use of_clk_init(NULL);

> +CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock", of_omap4_dpll_setup);
> +#endif
>
-- 
Regards,
Nishanth Menon

Re: [PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Tero Kristo]

On 07/30/2013 07:23 PM, Nishanth Menon wrote:
> This patch probably was submitted in the wrong sequence - fails build
> and few other issues below.

Yeah, I'll double check the build sequence for these.

>
> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>> The OMAP clock driver now supports DPLL clock type. This patch also
>> adds support for DT DPLL nodes.
>
> Then why is $subject specific to OMAP4? is that because of
> of_omap4_dpll_setup?

The driver only supports omap4 dpll type at this point, omap3 dplls 
require some modifications on top of this, and are provided later in the 
series.

>
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/Makefile |    2 +-
>>   drivers/clk/omap/clk.c    |    1 +
>>   drivers/clk/omap/dpll.c   |  295
>> +++++++++++++++++++++++++++++++++++++++++++++
>
> Device Tree Binding documentation?

Didn't bother writing those yet as I haven't received too much feedback 
whether this approach is acceptable or not.

>
>>   3 files changed, 297 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/clk/omap/dpll.c
>>
>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>> index 8195931..4cad480 100644
>> --- a/drivers/clk/omap/Makefile
>> +++ b/drivers/clk/omap/Makefile
>> @@ -1 +1 @@
>> -obj-y                    += clk.o
>> +obj-y                    += clk.o dpll.o
>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>> index 4bf1929..1dafdaa 100644
>> --- a/drivers/clk/omap/clk.c
>> +++ b/drivers/clk/omap/clk.c
>> @@ -28,6 +28,7 @@ static const struct of_device_id clk_match[] = {
>>           .data = of_fixed_factor_clk_setup, },
>>       {.compatible = "divider-clock", .data = of_divider_clk_setup, },
>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>> +    {.compatible = "ti,omap4-dpll-clock", .data =
>> of_omap4_dpll_setup, },
>>       {},
>>   };
> you would not need this if you did just of_clk_init(NULL); ?

Why not? And I think we still need to do this.

>
> Further, at this patch, build fails with:
> drivers/clk/omap/clk.c:31:55: error: undefined identifier
> 'of_omap4_dpll_setup'
> drivers/clk/omap/clk.c:31:48: error: ‘of_omap4_dpll_setup’ undeclared
> here (not in a function)
>
> which makes sense since we did not export the function.

Yea seems like wrong ordering of patches, sorry about that. >.<

>>
>> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
>> new file mode 100644
>> index 0000000..66e82be
>> --- /dev/null
>> +++ b/drivers/clk/omap/dpll.c
>> @@ -0,0 +1,295 @@
>> +/*
>> + * OMAP DPLL clock support
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * Tero Kristo <t-kristo@ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +#include <linux/string.h>
>> +#include <linux/log2.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
> after a quick check, are all these required?

Seems like some might not be needed, I'll double check this.

>
>> +#include <linux/clk/omap.h>
>
> why?

Need dpll_data definition for example.

>
>> +
>> +static const struct clk_ops dpll_m4xen_ck_ops = {
>> +    .enable        = &omap3_noncore_dpll_enable,
>> +    .disable    = &omap3_noncore_dpll_disable,
>> +    .recalc_rate    = &omap4_dpll_regm4xen_recalc,
>> +    .round_rate    = &omap4_dpll_regm4xen_round_rate,
>> +    .set_rate    = &omap3_noncore_dpll_set_rate,
>> +    .get_parent    = &omap2_init_dpll_parent,
>> +};
>> +
>> +static const struct clk_ops dpll_core_ck_ops = {
>> +    .recalc_rate    = &omap3_dpll_recalc,
>> +    .get_parent    = &omap2_init_dpll_parent,
>> +};
>> +
>> +static const struct clk_ops dpll_ck_ops = {
>> +    .enable        = &omap3_noncore_dpll_enable,
>> +    .disable    = &omap3_noncore_dpll_disable,
>> +    .recalc_rate    = &omap3_dpll_recalc,
>> +    .round_rate    = &omap2_dpll_round_rate,
>> +    .set_rate    = &omap3_noncore_dpll_set_rate,
>> +    .get_parent    = &omap2_init_dpll_parent,
>> +    .init        = &omap2_init_clk_clkdm,
>> +};
>> +
>> +static const struct clk_ops dpll_x2_ck_ops = {
>> +    .recalc_rate    = &omap3_clkoutx2_recalc,
>> +};
>
> none of these are defined at this stage of the patch, generates a huge
> build error for dpll.c
> http://pastebin.com/GJucv1A5

Yea, wrong ordering, linux/clk/omap.h is not up to date. I'll fix this 
and rest of the similar issues.

>> +
>> +struct clk *omap_clk_register_dpll(struct device *dev, const char *name,
>> +        const char **parent_names, int num_parents, unsigned long flags,
>> +        struct dpll_data *dpll_data, const char *clkdm_name,
>> +        const struct clk_ops *ops)
>
> why should this be public?

Currently does not need to be, but someone could in theory build up 
cclockXxxx_data.c file and use these calls from there. Kind of legacy 
support, see some of the basic clk types. I guess I can add static to 
this, and remove some of the params along.

>
>> +{
>> +    struct clk *clk;
>> +    struct clk_init_data init;
>
> init = { 0 };  just to future proof?

Good idea, i'll add this.

>
>> +    struct clk_hw_omap *clk_hw;
>
> does not exist yet in generic header?

Yea.

>
> I am assuming you do not do parameter check as you expect clk_register
> to do the same?

True, so I'll change the above function to static.

>
>> +
>> +    /* allocate the divider */
>> +    clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
> checkpatch complained:
> CHECK: Prefer kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct
> clk_hw_omap)...)

Hmm, I didn't get this with checkpatch. Some special option/version you 
use? I still see both types of sizeof used in the kernel.

>
> or given we have dev, devm_kzalloc?

Actually we don't have dev, check how this is called from below.

>> +    if (!clk_hw) {
>> +        pr_err("%s: could not allocate clk_hw_omap\n", __func__);
>> +        return ERR_PTR(-ENOMEM);
>> +    }
>> +
>> +    clk_hw->dpll_data = dpll_data;
>> +    clk_hw->ops = &clkhwops_omap3_dpll;
>> +    clk_hw->clkdm_name = clkdm_name;
>> +    clk_hw->hw.init = &init;
>> +
>> +    init.name = name;
>> +    init.ops = ops;
>> +    init.flags = flags;
>> +    init.parent_names = parent_names;
>> +    init.num_parents = num_parents;
>> +
>> +    /* register the clock */
>> +    clk = clk_register(dev, &clk_hw->hw);
>> +
>> +    if (IS_ERR(clk))
>> +        kfree(clk_hw);
>> +    else
>> +        omap2_init_clk_hw_omap_clocks(clk);
> what if init fails? and it is in mach-omap2 at this point in time?

Yea, this just calls the autoidle init part under mach-omap2.

>
>> +
>> +    return clk;
>> +}
>> +
>> +struct clk *omap_clk_register_dpll_x2(struct device *dev, const char
>> *name,
>> +        const char *parent_name, void __iomem *reg,
>> +        const struct clk_ops *ops)
>
> same question here as well

Yea, can change to static I think.

>
>> +{
>> +    struct clk *clk;
>> +    struct clk_init_data init;
>> +    struct clk_hw_omap *clk_hw;
>> +
>> +    if (!parent_name) {
>> +        pr_err("%s: dpll_x2 must have parent\n", __func__);
>> +        return ERR_PTR(-EINVAL);
>> +    }
>> +
>> +    clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
> checkpatch complained:
> CHECK: Prefer kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct
> clk_hw_omap)...)
>
> or devm_kzalloc?

Same as above.

>
>> +    if (!clk_hw) {
>> +        pr_err("%s: could not allocate clk_hw_omap\n", __func__);
>> +        return ERR_PTR(-ENOMEM);
>> +    }
>> +
>> +    clk_hw->ops = &clkhwops_omap4_dpllmx;
>> +    clk_hw->clksel_reg = reg;
>> +    clk_hw->hw.init = &init;
>> +
>> +    init.name = name;
>> +    init.ops = ops;
>> +    init.parent_names = &parent_name;
>> +    init.num_parents = 1;
>> +
>> +    /* register the clock */
>> +    clk = clk_register(dev, &clk_hw->hw);
>> +
>> +    if (IS_ERR(clk))
>> +        kfree(clk_hw);
>> +    else
>> +        omap2_init_clk_hw_omap_clocks(clk);
>> +
>> +    return clk;
>> +}
> this vaguely sounds like a replica of omap_clk_register_dpll with
> num_parents and clk_hw->ops different. why not merge the two?

Some of the params are different but yes, I'll see if I can merge the two.

>
>> +
>> +#ifdef CONFIG_OF
>
> why not build the entire thing *iff* CONFIG_OF (Makefile/Kconfig dep)?
> that way, we can drop this #ifdef stuff from drivers that dont need to
> have dual support.

Yea, I guess I can do this.

>
>> +
>> +/**
>> + * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
>
> node and ops not documented.

I'll add some beef here.

>
>> + */
>> +static void __init of_omap_dpll_setup(struct device_node *node,
>> +                    const struct clk_ops *ops)
>> +{
>> +    struct clk *clk;
>> +    const char *clk_name = node->name;
>> +    int num_parents;
>> +    const char **parent_names;
>> +    const char *clkdm_name = NULL;
>> +    struct of_phandle_args clkspec;
>> +    u8 dpll_flags = 0;
>> +    struct dpll_data *dd;
>> +    u32 idlest_mask = 0x1;
>> +    u32 enable_mask = 0x7;
>> +    u32 autoidle_mask = 0x7;
>> +    u32 mult_mask = 0x7ff << 8;
>> +    u32 div1_mask = 0x7f;
>> +    u32 max_multiplier = 2047;
>> +    u32 max_divider = 128;
>> +    u32 min_divider = 1;
>> +    int i;
>> +
>> +    dd = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
> kzalloc sizeof(*dd) ?

See above.

>
>> +    if (!dd) {
>> +        pr_err("%s: could not allocate dpll_data\n", __func__);
>> +        return;
>> +    }
>> +
>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>> +
>> +    num_parents = of_clk_get_parent_count(node);
>> +    if (num_parents < 1) {
>> +        pr_err("%s: omap dpll %s must have parent(s)\n",
>> +            __func__, node->name);
>
> checkpatch complained:
> CHECK: Alignment should match open parenthesis
> #212: FILE: drivers/clk/omap/dpll.c:171:
> After applying the patch, I think you should make __func__ aligned with
> " and not %

Again, what version of checkpatch you use? Or what flags?

>
>> +        goto cleanup;
>> +    }
>> +
>> +    parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
>> +
>> +    for (i = 0; i < num_parents; i++)
>> +        parent_names[i] = of_clk_get_parent_name(node, i);
>> +
>> +    of_property_read_u32(node, "ti,idlest-mask", &idlest_mask);
>> +
>> +    of_property_read_u32(node, "ti,enable-mask", &enable_mask);
>> +
>> +    of_property_read_u32(node, "ti,autoidle-mask", &autoidle_mask);
>
> are these going to be different? or can we catch with compatible flag?

For example, omap3 dpll4:

dpll4_ck: dpll4_ck@48004d00 {
         ti,autoidle-mask = <0x38>;
         ti,idlest-mask = <0x2>;
         ti,enable-mask = <0x70000>;
};

It seems that currently we can catch all cases with the 
ti,dpll-peripheral flag. I'll modify the code accordingly.


>
>> +
>> +    clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
>> +    dd->clk_ref = of_clk_get_from_provider(&clkspec);
>> +    if (!dd->clk_ref) {
>> +        pr_err("%s: ti,clk-ref for %s not found\n", __func__,
>> +            clk_name);
>
> CHECK: Alignment should match open parenthesis
> #231: FILE: drivers/clk/omap/dpll.c:190:
> similar issue here.
>
>> +        goto cleanup;
>> +    }
>> +
>> +    clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
>> +    dd->clk_bypass = of_clk_get_from_provider(&clkspec);
>> +    if (!dd->clk_bypass) {
>> +        pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
>> +            clk_name);
>
> here as well
>
>> +        goto cleanup;
>> +    }
>> +
>> +    of_property_read_string(node, "ti,clkdm-name", &clkdm_name);
>> +
>> +    dd->control_reg = of_iomap(node, 0);
>> +    dd->idlest_reg = of_iomap(node, 1);
>> +    dd->autoidle_reg = of_iomap(node, 2);
>> +    dd->mult_div1_reg = of_iomap(node, 3);
>
> if dts has errors, should we not verify mandatory parameters?
>
>> +
>> +    dd->idlest_mask = idlest_mask;
>> +    dd->enable_mask = enable_mask;
>> +    dd->autoidle_mask = autoidle_mask;
>> +
>> +    dd->modes = 0xa0;
>
> what is 0xa0?

Magic mode. :) I'll copy paste a macro for this.

>
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-j-type")) {
>> +        dd->sddiv_mask = 0xff000000;
>> +        mult_mask = 0xfff << 8;
>> +        div1_mask = 0xff;
>> +        max_multiplier = 4095;
>> +        max_divider = 256;
>> +    }
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
> I think we need bindings to understand this better.

Or documentation you mean?

>
>> +        dd->m4xen_mask = 0x800;
>> +        dd->lpmode_mask = 1 << 10;
>> +    }
>> +
>> +    dd->mult_mask = mult_mask;
>> +    dd->div1_mask = div1_mask;
>> +    dd->max_multiplier = max_multiplier;
>> +    dd->max_divider = max_divider;
>> +    dd->min_divider = min_divider;
>> +
>> +    clk = omap_clk_register_dpll(NULL, clk_name, parent_names,
>> +                num_parents, dpll_flags, dd,
>> +                clkdm_name, ops);
>> +
>> +    if (!IS_ERR(clk))
>> +        of_clk_add_provider(node, of_clk_src_simple_get, clk);
> error check?

This is not done with other drivers either. Would require clk_unregister 
use to cleanup the above register call which is currently unavailable. I 
could add an error trace for this though.

>> +    return;
>> +
>> +cleanup:
>
> kfree(parent_names) ?

Hmm yea.

>
>> +    kfree(dd);
>> +    return;
>> +}
>> +
>> +static void __init of_omap_dpll_x2_setup(struct device_node *node)
>> +{
>> +    struct clk *clk;
>> +    const char *clk_name = node->name;
>> +    void __iomem *reg;
>> +    const char *parent_name;
>> +
>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>> +
>> +    parent_name = of_clk_get_parent_name(node, 0);
>> +
>> +    reg = of_iomap(node, 0);
>
> if dts has errors, should we not verify mandatory parameters?

You mean checking the validity of this pointer? It seems of_iomap does 
something strange when it fails, e.g. when passed a 0x0 from DT. You can 
see what I do in a later patch for adding am335x support for DPLLs.

>
>> +
>> +    clk = omap_clk_register_dpll_x2(NULL, clk_name, parent_name,
>> +                reg, &dpll_x2_ck_ops);
>> +
>> +    if (!IS_ERR(clk))
>> +        of_clk_add_provider(node, of_clk_src_simple_get, clk);
> error check?
>
> gentle request - in this setup function we dont see a return of error
> value (which makes sense), but more importantly - log saying that node
> was not setup

Yea, I can add error prints.

>
>> +}
>> +
>> +__init void of_omap3_dpll_setup(struct device_node *node)
>
> ^^ void __init? further, you could make this static.

Ok.

>
>> +{
>> +    /* XXX: to be done */
>> +}
>> +EXPORT_SYMBOL_GPL(of_omap3_dpll_setup);
>
> you can drop the export if you use of_clk_init(NULL);

Same comment as earlier.

>
>> +CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock",
>> of_omap3_dpll_setup);
>> +
>> +__init void of_omap4_dpll_setup(struct device_node *node)
>
> ^^ void __init? further, you could make this static.

Ok.

>
>> +{
>> +    const struct clk_ops *ops;
>> +
>> +    ops = &dpll_ck_ops;
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-regm4xen"))
>> +        ops = &dpll_m4xen_ck_ops;
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-core"))
>> +        ops = &dpll_core_ck_ops;
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-clk-x2")) {
>> +        of_omap_dpll_x2_setup(node);
>> +        return;
>> +    }
>> +
>> +    of_omap_dpll_setup(node, ops);
>> +}
>> +EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>
> you can drop the export if you use of_clk_init(NULL);

Hmm no?

Actually dug this further, I think the init setup is slightly wrong at 
the moment, we should not do CLK_OF_DECLARE at all within the omap 
specific clock drivers, but instead just use the match table from clk.c. 
I'll change it like so.

>
>> +CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock",
>> of_omap4_dpll_setup);

So, for example this should be removed. We don't want to support this 
clock type on non-omap platforms just to avoid problems.

>> +#endif
>>

[PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Tero Kristo]

On 07/30/2013 07:23 PM, Nishanth Menon wrote:
> This patch probably was submitted in the wrong sequence - fails build
> and few other issues below.

Yeah, I'll double check the build sequence for these.

>
> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>> The OMAP clock driver now supports DPLL clock type. This patch also
>> adds support for DT DPLL nodes.
>
> Then why is $subject specific to OMAP4? is that because of
> of_omap4_dpll_setup?

The driver only supports omap4 dpll type at this point, omap3 dplls 
require some modifications on top of this, and are provided later in the 
series.

>
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/Makefile |    2 +-
>>   drivers/clk/omap/clk.c    |    1 +
>>   drivers/clk/omap/dpll.c   |  295
>> +++++++++++++++++++++++++++++++++++++++++++++
>
> Device Tree Binding documentation?

Didn't bother writing those yet as I haven't received too much feedback 
whether this approach is acceptable or not.

>
>>   3 files changed, 297 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/clk/omap/dpll.c
>>
>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>> index 8195931..4cad480 100644
>> --- a/drivers/clk/omap/Makefile
>> +++ b/drivers/clk/omap/Makefile
>> @@ -1 +1 @@
>> -obj-y                    += clk.o
>> +obj-y                    += clk.o dpll.o
>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>> index 4bf1929..1dafdaa 100644
>> --- a/drivers/clk/omap/clk.c
>> +++ b/drivers/clk/omap/clk.c
>> @@ -28,6 +28,7 @@ static const struct of_device_id clk_match[] = {
>>           .data = of_fixed_factor_clk_setup, },
>>       {.compatible = "divider-clock", .data = of_divider_clk_setup, },
>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>> +    {.compatible = "ti,omap4-dpll-clock", .data =
>> of_omap4_dpll_setup, },
>>       {},
>>   };
> you would not need this if you did just of_clk_init(NULL); ?

Why not? And I think we still need to do this.

>
> Further, at this patch, build fails with:
> drivers/clk/omap/clk.c:31:55: error: undefined identifier
> 'of_omap4_dpll_setup'
> drivers/clk/omap/clk.c:31:48: error: ?of_omap4_dpll_setup? undeclared
> here (not in a function)
>
> which makes sense since we did not export the function.

Yea seems like wrong ordering of patches, sorry about that. >.<

>>
>> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
>> new file mode 100644
>> index 0000000..66e82be
>> --- /dev/null
>> +++ b/drivers/clk/omap/dpll.c
>> @@ -0,0 +1,295 @@
>> +/*
>> + * OMAP DPLL clock support
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * Tero Kristo <t-kristo@ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +#include <linux/string.h>
>> +#include <linux/log2.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
> after a quick check, are all these required?

Seems like some might not be needed, I'll double check this.

>
>> +#include <linux/clk/omap.h>
>
> why?

Need dpll_data definition for example.

>
>> +
>> +static const struct clk_ops dpll_m4xen_ck_ops = {
>> +    .enable        = &omap3_noncore_dpll_enable,
>> +    .disable    = &omap3_noncore_dpll_disable,
>> +    .recalc_rate    = &omap4_dpll_regm4xen_recalc,
>> +    .round_rate    = &omap4_dpll_regm4xen_round_rate,
>> +    .set_rate    = &omap3_noncore_dpll_set_rate,
>> +    .get_parent    = &omap2_init_dpll_parent,
>> +};
>> +
>> +static const struct clk_ops dpll_core_ck_ops = {
>> +    .recalc_rate    = &omap3_dpll_recalc,
>> +    .get_parent    = &omap2_init_dpll_parent,
>> +};
>> +
>> +static const struct clk_ops dpll_ck_ops = {
>> +    .enable        = &omap3_noncore_dpll_enable,
>> +    .disable    = &omap3_noncore_dpll_disable,
>> +    .recalc_rate    = &omap3_dpll_recalc,
>> +    .round_rate    = &omap2_dpll_round_rate,
>> +    .set_rate    = &omap3_noncore_dpll_set_rate,
>> +    .get_parent    = &omap2_init_dpll_parent,
>> +    .init        = &omap2_init_clk_clkdm,
>> +};
>> +
>> +static const struct clk_ops dpll_x2_ck_ops = {
>> +    .recalc_rate    = &omap3_clkoutx2_recalc,
>> +};
>
> none of these are defined at this stage of the patch, generates a huge
> build error for dpll.c
> http://pastebin.com/GJucv1A5

Yea, wrong ordering, linux/clk/omap.h is not up to date. I'll fix this 
and rest of the similar issues.

>> +
>> +struct clk *omap_clk_register_dpll(struct device *dev, const char *name,
>> +        const char **parent_names, int num_parents, unsigned long flags,
>> +        struct dpll_data *dpll_data, const char *clkdm_name,
>> +        const struct clk_ops *ops)
>
> why should this be public?

Currently does not need to be, but someone could in theory build up 
cclockXxxx_data.c file and use these calls from there. Kind of legacy 
support, see some of the basic clk types. I guess I can add static to 
this, and remove some of the params along.

>
>> +{
>> +    struct clk *clk;
>> +    struct clk_init_data init;
>
> init = { 0 };  just to future proof?

Good idea, i'll add this.

>
>> +    struct clk_hw_omap *clk_hw;
>
> does not exist yet in generic header?

Yea.

>
> I am assuming you do not do parameter check as you expect clk_register
> to do the same?

True, so I'll change the above function to static.

>
>> +
>> +    /* allocate the divider */
>> +    clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
> checkpatch complained:
> CHECK: Prefer kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct
> clk_hw_omap)...)

Hmm, I didn't get this with checkpatch. Some special option/version you 
use? I still see both types of sizeof used in the kernel.

>
> or given we have dev, devm_kzalloc?

Actually we don't have dev, check how this is called from below.

>> +    if (!clk_hw) {
>> +        pr_err("%s: could not allocate clk_hw_omap\n", __func__);
>> +        return ERR_PTR(-ENOMEM);
>> +    }
>> +
>> +    clk_hw->dpll_data = dpll_data;
>> +    clk_hw->ops = &clkhwops_omap3_dpll;
>> +    clk_hw->clkdm_name = clkdm_name;
>> +    clk_hw->hw.init = &init;
>> +
>> +    init.name = name;
>> +    init.ops = ops;
>> +    init.flags = flags;
>> +    init.parent_names = parent_names;
>> +    init.num_parents = num_parents;
>> +
>> +    /* register the clock */
>> +    clk = clk_register(dev, &clk_hw->hw);
>> +
>> +    if (IS_ERR(clk))
>> +        kfree(clk_hw);
>> +    else
>> +        omap2_init_clk_hw_omap_clocks(clk);
> what if init fails? and it is in mach-omap2 at this point in time?

Yea, this just calls the autoidle init part under mach-omap2.

>
>> +
>> +    return clk;
>> +}
>> +
>> +struct clk *omap_clk_register_dpll_x2(struct device *dev, const char
>> *name,
>> +        const char *parent_name, void __iomem *reg,
>> +        const struct clk_ops *ops)
>
> same question here as well

Yea, can change to static I think.

>
>> +{
>> +    struct clk *clk;
>> +    struct clk_init_data init;
>> +    struct clk_hw_omap *clk_hw;
>> +
>> +    if (!parent_name) {
>> +        pr_err("%s: dpll_x2 must have parent\n", __func__);
>> +        return ERR_PTR(-EINVAL);
>> +    }
>> +
>> +    clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
> checkpatch complained:
> CHECK: Prefer kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct
> clk_hw_omap)...)
>
> or devm_kzalloc?

Same as above.

>
>> +    if (!clk_hw) {
>> +        pr_err("%s: could not allocate clk_hw_omap\n", __func__);
>> +        return ERR_PTR(-ENOMEM);
>> +    }
>> +
>> +    clk_hw->ops = &clkhwops_omap4_dpllmx;
>> +    clk_hw->clksel_reg = reg;
>> +    clk_hw->hw.init = &init;
>> +
>> +    init.name = name;
>> +    init.ops = ops;
>> +    init.parent_names = &parent_name;
>> +    init.num_parents = 1;
>> +
>> +    /* register the clock */
>> +    clk = clk_register(dev, &clk_hw->hw);
>> +
>> +    if (IS_ERR(clk))
>> +        kfree(clk_hw);
>> +    else
>> +        omap2_init_clk_hw_omap_clocks(clk);
>> +
>> +    return clk;
>> +}
> this vaguely sounds like a replica of omap_clk_register_dpll with
> num_parents and clk_hw->ops different. why not merge the two?

Some of the params are different but yes, I'll see if I can merge the two.

>
>> +
>> +#ifdef CONFIG_OF
>
> why not build the entire thing *iff* CONFIG_OF (Makefile/Kconfig dep)?
> that way, we can drop this #ifdef stuff from drivers that dont need to
> have dual support.

Yea, I guess I can do this.

>
>> +
>> +/**
>> + * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
>
> node and ops not documented.

I'll add some beef here.

>
>> + */
>> +static void __init of_omap_dpll_setup(struct device_node *node,
>> +                    const struct clk_ops *ops)
>> +{
>> +    struct clk *clk;
>> +    const char *clk_name = node->name;
>> +    int num_parents;
>> +    const char **parent_names;
>> +    const char *clkdm_name = NULL;
>> +    struct of_phandle_args clkspec;
>> +    u8 dpll_flags = 0;
>> +    struct dpll_data *dd;
>> +    u32 idlest_mask = 0x1;
>> +    u32 enable_mask = 0x7;
>> +    u32 autoidle_mask = 0x7;
>> +    u32 mult_mask = 0x7ff << 8;
>> +    u32 div1_mask = 0x7f;
>> +    u32 max_multiplier = 2047;
>> +    u32 max_divider = 128;
>> +    u32 min_divider = 1;
>> +    int i;
>> +
>> +    dd = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
> kzalloc sizeof(*dd) ?

See above.

>
>> +    if (!dd) {
>> +        pr_err("%s: could not allocate dpll_data\n", __func__);
>> +        return;
>> +    }
>> +
>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>> +
>> +    num_parents = of_clk_get_parent_count(node);
>> +    if (num_parents < 1) {
>> +        pr_err("%s: omap dpll %s must have parent(s)\n",
>> +            __func__, node->name);
>
> checkpatch complained:
> CHECK: Alignment should match open parenthesis
> #212: FILE: drivers/clk/omap/dpll.c:171:
> After applying the patch, I think you should make __func__ aligned with
> " and not %

Again, what version of checkpatch you use? Or what flags?

>
>> +        goto cleanup;
>> +    }
>> +
>> +    parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
>> +
>> +    for (i = 0; i < num_parents; i++)
>> +        parent_names[i] = of_clk_get_parent_name(node, i);
>> +
>> +    of_property_read_u32(node, "ti,idlest-mask", &idlest_mask);
>> +
>> +    of_property_read_u32(node, "ti,enable-mask", &enable_mask);
>> +
>> +    of_property_read_u32(node, "ti,autoidle-mask", &autoidle_mask);
>
> are these going to be different? or can we catch with compatible flag?

For example, omap3 dpll4:

dpll4_ck: dpll4_ck at 48004d00 {
         ti,autoidle-mask = <0x38>;
         ti,idlest-mask = <0x2>;
         ti,enable-mask = <0x70000>;
};

It seems that currently we can catch all cases with the 
ti,dpll-peripheral flag. I'll modify the code accordingly.


>
>> +
>> +    clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
>> +    dd->clk_ref = of_clk_get_from_provider(&clkspec);
>> +    if (!dd->clk_ref) {
>> +        pr_err("%s: ti,clk-ref for %s not found\n", __func__,
>> +            clk_name);
>
> CHECK: Alignment should match open parenthesis
> #231: FILE: drivers/clk/omap/dpll.c:190:
> similar issue here.
>
>> +        goto cleanup;
>> +    }
>> +
>> +    clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
>> +    dd->clk_bypass = of_clk_get_from_provider(&clkspec);
>> +    if (!dd->clk_bypass) {
>> +        pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
>> +            clk_name);
>
> here as well
>
>> +        goto cleanup;
>> +    }
>> +
>> +    of_property_read_string(node, "ti,clkdm-name", &clkdm_name);
>> +
>> +    dd->control_reg = of_iomap(node, 0);
>> +    dd->idlest_reg = of_iomap(node, 1);
>> +    dd->autoidle_reg = of_iomap(node, 2);
>> +    dd->mult_div1_reg = of_iomap(node, 3);
>
> if dts has errors, should we not verify mandatory parameters?
>
>> +
>> +    dd->idlest_mask = idlest_mask;
>> +    dd->enable_mask = enable_mask;
>> +    dd->autoidle_mask = autoidle_mask;
>> +
>> +    dd->modes = 0xa0;
>
> what is 0xa0?

Magic mode. :) I'll copy paste a macro for this.

>
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-j-type")) {
>> +        dd->sddiv_mask = 0xff000000;
>> +        mult_mask = 0xfff << 8;
>> +        div1_mask = 0xff;
>> +        max_multiplier = 4095;
>> +        max_divider = 256;
>> +    }
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
> I think we need bindings to understand this better.

Or documentation you mean?

>
>> +        dd->m4xen_mask = 0x800;
>> +        dd->lpmode_mask = 1 << 10;
>> +    }
>> +
>> +    dd->mult_mask = mult_mask;
>> +    dd->div1_mask = div1_mask;
>> +    dd->max_multiplier = max_multiplier;
>> +    dd->max_divider = max_divider;
>> +    dd->min_divider = min_divider;
>> +
>> +    clk = omap_clk_register_dpll(NULL, clk_name, parent_names,
>> +                num_parents, dpll_flags, dd,
>> +                clkdm_name, ops);
>> +
>> +    if (!IS_ERR(clk))
>> +        of_clk_add_provider(node, of_clk_src_simple_get, clk);
> error check?

This is not done with other drivers either. Would require clk_unregister 
use to cleanup the above register call which is currently unavailable. I 
could add an error trace for this though.

>> +    return;
>> +
>> +cleanup:
>
> kfree(parent_names) ?

Hmm yea.

>
>> +    kfree(dd);
>> +    return;
>> +}
>> +
>> +static void __init of_omap_dpll_x2_setup(struct device_node *node)
>> +{
>> +    struct clk *clk;
>> +    const char *clk_name = node->name;
>> +    void __iomem *reg;
>> +    const char *parent_name;
>> +
>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>> +
>> +    parent_name = of_clk_get_parent_name(node, 0);
>> +
>> +    reg = of_iomap(node, 0);
>
> if dts has errors, should we not verify mandatory parameters?

You mean checking the validity of this pointer? It seems of_iomap does 
something strange when it fails, e.g. when passed a 0x0 from DT. You can 
see what I do in a later patch for adding am335x support for DPLLs.

>
>> +
>> +    clk = omap_clk_register_dpll_x2(NULL, clk_name, parent_name,
>> +                reg, &dpll_x2_ck_ops);
>> +
>> +    if (!IS_ERR(clk))
>> +        of_clk_add_provider(node, of_clk_src_simple_get, clk);
> error check?
>
> gentle request - in this setup function we dont see a return of error
> value (which makes sense), but more importantly - log saying that node
> was not setup

Yea, I can add error prints.

>
>> +}
>> +
>> +__init void of_omap3_dpll_setup(struct device_node *node)
>
> ^^ void __init? further, you could make this static.

Ok.

>
>> +{
>> +    /* XXX: to be done */
>> +}
>> +EXPORT_SYMBOL_GPL(of_omap3_dpll_setup);
>
> you can drop the export if you use of_clk_init(NULL);

Same comment as earlier.

>
>> +CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock",
>> of_omap3_dpll_setup);
>> +
>> +__init void of_omap4_dpll_setup(struct device_node *node)
>
> ^^ void __init? further, you could make this static.

Ok.

>
>> +{
>> +    const struct clk_ops *ops;
>> +
>> +    ops = &dpll_ck_ops;
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-regm4xen"))
>> +        ops = &dpll_m4xen_ck_ops;
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-core"))
>> +        ops = &dpll_core_ck_ops;
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-clk-x2")) {
>> +        of_omap_dpll_x2_setup(node);
>> +        return;
>> +    }
>> +
>> +    of_omap_dpll_setup(node, ops);
>> +}
>> +EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>
> you can drop the export if you use of_clk_init(NULL);

Hmm no?

Actually dug this further, I think the init setup is slightly wrong at 
the moment, we should not do CLK_OF_DECLARE at all within the omap 
specific clock drivers, but instead just use the match table from clk.c. 
I'll change it like so.

>
>> +CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock",
>> of_omap4_dpll_setup);

So, for example this should be removed. We don't want to support this 
clock type on non-omap platforms just to avoid problems.

>> +#endif
>>

Re: [PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Nishanth Menon]

On 07/31/2013 04:46 AM, Tero Kristo wrote:
> On 07/30/2013 07:23 PM, Nishanth Menon wrote:
>> This patch probably was submitted in the wrong sequence - fails build
>> and few other issues below.
>
> Yeah, I'll double check the build sequence for these.
>
>>
>> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>>> The OMAP clock driver now supports DPLL clock type. This patch also
>>> adds support for DT DPLL nodes.
>>
>> Then why is $subject specific to OMAP4? is that because of
>> of_omap4_dpll_setup?
>
> The driver only supports omap4 dpll type at this point, omap3 dplls
> require some modifications on top of this, and are provided later in the
> series.

ok.

>
>>
>>>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>> ---
>>>   drivers/clk/omap/Makefile |    2 +-
>>>   drivers/clk/omap/clk.c    |    1 +
>>>   drivers/clk/omap/dpll.c   |  295
>>> +++++++++++++++++++++++++++++++++++++++++++++
>>
>> Device Tree Binding documentation?
>
> Didn't bother writing those yet as I haven't received too much feedback
> whether this approach is acceptable or not.

Documentation helps simplify the understanding of expected usage - this 
is useful to review approach as well :)

>>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>>> index 4bf1929..1dafdaa 100644
>>> --- a/drivers/clk/omap/clk.c
>>> +++ b/drivers/clk/omap/clk.c
>>> @@ -28,6 +28,7 @@ static const struct of_device_id clk_match[] = {
>>>           .data = of_fixed_factor_clk_setup, },
>>>       {.compatible = "divider-clock", .data = of_divider_clk_setup, },
>>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>>> +    {.compatible = "ti,omap4-dpll-clock", .data =
>>> of_omap4_dpll_setup, },
>>>       {},
>>>   };
>> you would not need this if you did just of_clk_init(NULL); ?
>
> Why not? And I think we still need to do this.

CLK_OF_DECLARE will take care of having all required clks registered 
of_clk_init(NULL); will pick up from that list.

that will remove all extra exports, and make clk.c redundant.
[...]

>
>>
>>> +#include <linux/clk/omap.h>
>>
>> why?
>
> Need dpll_data definition for example.
OK - without the ordering of patches, it was not obvious. structures aside,

We should move the functions to this file instead and empty out 
mach-omap2 gradually, omap_dpll.h should be exported and used by 
mach-omap2, rather than the other way around.

>>> +
>>> +struct clk *omap_clk_register_dpll(struct device *dev, const char
>>> *name,
>>> +        const char **parent_names, int num_parents, unsigned long
>>> flags,
>>> +        struct dpll_data *dpll_data, const char *clkdm_name,
>>> +        const struct clk_ops *ops)
>>
>> why should this be public?
>
> Currently does not need to be, but someone could in theory build up
> cclockXxxx_data.c file and use these calls from there. Kind of legacy
> support, see some of the basic clk types. I guess I can add static to
> this, and remove some of the params along.
>

thanks. we should keep unneeded stuff in static unless a specific 
provable need really arises.

>>
>> I am assuming you do not do parameter check as you expect clk_register
>> to do the same?
>
> True, so I'll change the above function to static.
>
>>
>>> +
>>> +    /* allocate the divider */
>>> +    clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
>> checkpatch complained:
>> CHECK: Prefer kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct
>> clk_hw_omap)...)
>
> Hmm, I didn't get this with checkpatch. Some special option/version you
> use? I still see both types of sizeof used in the kernel.
use checkpatch with --strict option

>
>>
>> or given we have dev, devm_kzalloc?
>
> Actually we don't have dev, check how this is called from below.

ok.

>
>>> +    if (!clk_hw) {
>>> +        pr_err("%s: could not allocate clk_hw_omap\n", __func__);
>>> +        return ERR_PTR(-ENOMEM);
>>> +    }
>>> +
>>> +    clk_hw->dpll_data = dpll_data;
>>> +    clk_hw->ops = &clkhwops_omap3_dpll;
>>> +    clk_hw->clkdm_name = clkdm_name;
>>> +    clk_hw->hw.init = &init;
>>> +
>>> +    init.name = name;
>>> +    init.ops = ops;
>>> +    init.flags = flags;
>>> +    init.parent_names = parent_names;
>>> +    init.num_parents = num_parents;
>>> +
>>> +    /* register the clock */
>>> +    clk = clk_register(dev, &clk_hw->hw);
>>> +
>>> +    if (IS_ERR(clk))
>>> +        kfree(clk_hw);
>>> +    else
>>> +        omap2_init_clk_hw_omap_clocks(clk);
>> what if init fails? and it is in mach-omap2 at this point in time?
>
> Yea, this just calls the autoidle init part under mach-omap2.

we should make this independent of mach-omap2. calls should be made to 
here if needed from mach-omap2 instead of the other way around. OR the 
required code should be moved over here.

>
>>
>>> +
>>> +    return clk;
>>> +}
>>
<snip>
>>
>>> +
>>> +    if (of_property_read_bool(node, "ti,dpll-j-type")) {
>>> +        dd->sddiv_mask = 0xff000000;
>>> +        mult_mask = 0xfff << 8;
>>> +        div1_mask = 0xff;
>>> +        max_multiplier = 4095;
>>> +        max_divider = 256;
>>> +    }
>>> +
>>> +    if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
>> I think we need bindings to understand this better.
>
> Or documentation you mean?

yes. Documentation/devicetree/bindings/....

>
>>
>>> +        dd->m4xen_mask = 0x800;
>>> +        dd->lpmode_mask = 1 << 10;
>>> +    }
>>> +
>>> +    dd->mult_mask = mult_mask;
>>> +    dd->div1_mask = div1_mask;
>>> +    dd->max_multiplier = max_multiplier;
>>> +    dd->max_divider = max_divider;
>>> +    dd->min_divider = min_divider;
>>> +
>>> +    clk = omap_clk_register_dpll(NULL, clk_name, parent_names,
>>> +                num_parents, dpll_flags, dd,
>>> +                clkdm_name, ops);
>>> +
>>> +    if (!IS_ERR(clk))
>>> +        of_clk_add_provider(node, of_clk_src_simple_get, clk);
>> error check?
>
> This is not done with other drivers either. Would require clk_unregister
> use to cleanup the above register call which is currently unavailable. I
> could add an error trace for this though.

you can definitely ensure this driver is clean :)

>>
>>> +    kfree(dd);
>>> +    return;
>>> +}
>>> +
>>> +static void __init of_omap_dpll_x2_setup(struct device_node *node)
>>> +{
>>> +    struct clk *clk;
>>> +    const char *clk_name = node->name;
>>> +    void __iomem *reg;
>>> +    const char *parent_name;
>>> +
>>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>>> +
>>> +    parent_name = of_clk_get_parent_name(node, 0);
>>> +
>>> +    reg = of_iomap(node, 0);
>>
>> if dts has errors, should we not verify mandatory parameters?
>
> You mean checking the validity of this pointer? It seems of_iomap does
> something strange when it fails, e.g. when passed a 0x0 from DT. You can
> see what I do in a later patch for adding am335x support for DPLLs.

in general, helping dts writers know of invalid/out of range parameters 
with a log message helps ensure those are fixed either on development or 
at some point - it aids debug instead of others having to scratch heads 
wondering what happened.

if mandatory parameters are verifable at setup and decided as bad, 
refusing to register is good idea especially with logs, they tend to get 
fixed rather faster - than an error that pops up when a specific DPLL is 
used at a later point in time.

just my 2 cents.
[..]

>>> +}
>>> +EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>>
>> you can drop the export if you use of_clk_init(NULL);
>
> Hmm no?
>
> Actually dug this further, I think the init setup is slightly wrong at
> the moment, we should not do CLK_OF_DECLARE at all within the omap
> specific clock drivers, but instead just use the match table from clk.c.
> I'll change it like so.
>
>>
>>> +CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock",
>>> of_omap4_dpll_setup);
>
> So, for example this should be removed. We don't want to support this
> clock type on non-omap platforms just to avoid problems.

As discussed offline, doing the other way around and doing what all 
other platforms do (which is CLK_OF_DECLARE) is a better idea to ensure 
standard APIs are carried forward and not spin off OMAP as a "special 
platform" - at least I dont seem to see any good reasoning for it yet.



-- 
Regards,
Nishanth Menon

[PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Nishanth Menon]

On 07/31/2013 04:46 AM, Tero Kristo wrote:
> On 07/30/2013 07:23 PM, Nishanth Menon wrote:
>> This patch probably was submitted in the wrong sequence - fails build
>> and few other issues below.
>
> Yeah, I'll double check the build sequence for these.
>
>>
>> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>>> The OMAP clock driver now supports DPLL clock type. This patch also
>>> adds support for DT DPLL nodes.
>>
>> Then why is $subject specific to OMAP4? is that because of
>> of_omap4_dpll_setup?
>
> The driver only supports omap4 dpll type at this point, omap3 dplls
> require some modifications on top of this, and are provided later in the
> series.

ok.

>
>>
>>>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>> ---
>>>   drivers/clk/omap/Makefile |    2 +-
>>>   drivers/clk/omap/clk.c    |    1 +
>>>   drivers/clk/omap/dpll.c   |  295
>>> +++++++++++++++++++++++++++++++++++++++++++++
>>
>> Device Tree Binding documentation?
>
> Didn't bother writing those yet as I haven't received too much feedback
> whether this approach is acceptable or not.

Documentation helps simplify the understanding of expected usage - this 
is useful to review approach as well :)

>>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>>> index 4bf1929..1dafdaa 100644
>>> --- a/drivers/clk/omap/clk.c
>>> +++ b/drivers/clk/omap/clk.c
>>> @@ -28,6 +28,7 @@ static const struct of_device_id clk_match[] = {
>>>           .data = of_fixed_factor_clk_setup, },
>>>       {.compatible = "divider-clock", .data = of_divider_clk_setup, },
>>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>>> +    {.compatible = "ti,omap4-dpll-clock", .data =
>>> of_omap4_dpll_setup, },
>>>       {},
>>>   };
>> you would not need this if you did just of_clk_init(NULL); ?
>
> Why not? And I think we still need to do this.

CLK_OF_DECLARE will take care of having all required clks registered 
of_clk_init(NULL); will pick up from that list.

that will remove all extra exports, and make clk.c redundant.
[...]

>
>>
>>> +#include <linux/clk/omap.h>
>>
>> why?
>
> Need dpll_data definition for example.
OK - without the ordering of patches, it was not obvious. structures aside,

We should move the functions to this file instead and empty out 
mach-omap2 gradually, omap_dpll.h should be exported and used by 
mach-omap2, rather than the other way around.

>>> +
>>> +struct clk *omap_clk_register_dpll(struct device *dev, const char
>>> *name,
>>> +        const char **parent_names, int num_parents, unsigned long
>>> flags,
>>> +        struct dpll_data *dpll_data, const char *clkdm_name,
>>> +        const struct clk_ops *ops)
>>
>> why should this be public?
>
> Currently does not need to be, but someone could in theory build up
> cclockXxxx_data.c file and use these calls from there. Kind of legacy
> support, see some of the basic clk types. I guess I can add static to
> this, and remove some of the params along.
>

thanks. we should keep unneeded stuff in static unless a specific 
provable need really arises.

>>
>> I am assuming you do not do parameter check as you expect clk_register
>> to do the same?
>
> True, so I'll change the above function to static.
>
>>
>>> +
>>> +    /* allocate the divider */
>>> +    clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
>> checkpatch complained:
>> CHECK: Prefer kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct
>> clk_hw_omap)...)
>
> Hmm, I didn't get this with checkpatch. Some special option/version you
> use? I still see both types of sizeof used in the kernel.
use checkpatch with --strict option

>
>>
>> or given we have dev, devm_kzalloc?
>
> Actually we don't have dev, check how this is called from below.

ok.

>
>>> +    if (!clk_hw) {
>>> +        pr_err("%s: could not allocate clk_hw_omap\n", __func__);
>>> +        return ERR_PTR(-ENOMEM);
>>> +    }
>>> +
>>> +    clk_hw->dpll_data = dpll_data;
>>> +    clk_hw->ops = &clkhwops_omap3_dpll;
>>> +    clk_hw->clkdm_name = clkdm_name;
>>> +    clk_hw->hw.init = &init;
>>> +
>>> +    init.name = name;
>>> +    init.ops = ops;
>>> +    init.flags = flags;
>>> +    init.parent_names = parent_names;
>>> +    init.num_parents = num_parents;
>>> +
>>> +    /* register the clock */
>>> +    clk = clk_register(dev, &clk_hw->hw);
>>> +
>>> +    if (IS_ERR(clk))
>>> +        kfree(clk_hw);
>>> +    else
>>> +        omap2_init_clk_hw_omap_clocks(clk);
>> what if init fails? and it is in mach-omap2 at this point in time?
>
> Yea, this just calls the autoidle init part under mach-omap2.

we should make this independent of mach-omap2. calls should be made to 
here if needed from mach-omap2 instead of the other way around. OR the 
required code should be moved over here.

>
>>
>>> +
>>> +    return clk;
>>> +}
>>
<snip>
>>
>>> +
>>> +    if (of_property_read_bool(node, "ti,dpll-j-type")) {
>>> +        dd->sddiv_mask = 0xff000000;
>>> +        mult_mask = 0xfff << 8;
>>> +        div1_mask = 0xff;
>>> +        max_multiplier = 4095;
>>> +        max_divider = 256;
>>> +    }
>>> +
>>> +    if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
>> I think we need bindings to understand this better.
>
> Or documentation you mean?

yes. Documentation/devicetree/bindings/....

>
>>
>>> +        dd->m4xen_mask = 0x800;
>>> +        dd->lpmode_mask = 1 << 10;
>>> +    }
>>> +
>>> +    dd->mult_mask = mult_mask;
>>> +    dd->div1_mask = div1_mask;
>>> +    dd->max_multiplier = max_multiplier;
>>> +    dd->max_divider = max_divider;
>>> +    dd->min_divider = min_divider;
>>> +
>>> +    clk = omap_clk_register_dpll(NULL, clk_name, parent_names,
>>> +                num_parents, dpll_flags, dd,
>>> +                clkdm_name, ops);
>>> +
>>> +    if (!IS_ERR(clk))
>>> +        of_clk_add_provider(node, of_clk_src_simple_get, clk);
>> error check?
>
> This is not done with other drivers either. Would require clk_unregister
> use to cleanup the above register call which is currently unavailable. I
> could add an error trace for this though.

you can definitely ensure this driver is clean :)

>>
>>> +    kfree(dd);
>>> +    return;
>>> +}
>>> +
>>> +static void __init of_omap_dpll_x2_setup(struct device_node *node)
>>> +{
>>> +    struct clk *clk;
>>> +    const char *clk_name = node->name;
>>> +    void __iomem *reg;
>>> +    const char *parent_name;
>>> +
>>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>>> +
>>> +    parent_name = of_clk_get_parent_name(node, 0);
>>> +
>>> +    reg = of_iomap(node, 0);
>>
>> if dts has errors, should we not verify mandatory parameters?
>
> You mean checking the validity of this pointer? It seems of_iomap does
> something strange when it fails, e.g. when passed a 0x0 from DT. You can
> see what I do in a later patch for adding am335x support for DPLLs.

in general, helping dts writers know of invalid/out of range parameters 
with a log message helps ensure those are fixed either on development or 
at some point - it aids debug instead of others having to scratch heads 
wondering what happened.

if mandatory parameters are verifable at setup and decided as bad, 
refusing to register is good idea especially with logs, they tend to get 
fixed rather faster - than an error that pops up when a specific DPLL is 
used at a later point in time.

just my 2 cents.
[..]

>>> +}
>>> +EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>>
>> you can drop the export if you use of_clk_init(NULL);
>
> Hmm no?
>
> Actually dug this further, I think the init setup is slightly wrong at
> the moment, we should not do CLK_OF_DECLARE at all within the omap
> specific clock drivers, but instead just use the match table from clk.c.
> I'll change it like so.
>
>>
>>> +CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock",
>>> of_omap4_dpll_setup);
>
> So, for example this should be removed. We don't want to support this
> clock type on non-omap platforms just to avoid problems.

As discussed offline, doing the other way around and doing what all 
other platforms do (which is CLK_OF_DECLARE) is a better idea to ensure 
standard APIs are carried forward and not spin off OMAP as a "special 
platform" - at least I dont seem to see any good reasoning for it yet.



-- 
Regards,
Nishanth Menon

Re: [PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Tero Kristo]

On 08/01/2013 05:00 PM, Nishanth Menon wrote:
> On 07/31/2013 04:46 AM, Tero Kristo wrote:
>> On 07/30/2013 07:23 PM, Nishanth Menon wrote:
>>> This patch probably was submitted in the wrong sequence - fails build
>>> and few other issues below.
>>
>> Yeah, I'll double check the build sequence for these.
>>
>>>
>>> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>>>> The OMAP clock driver now supports DPLL clock type. This patch also
>>>> adds support for DT DPLL nodes.
>>>
>>> Then why is $subject specific to OMAP4? is that because of
>>> of_omap4_dpll_setup?
>>
>> The driver only supports omap4 dpll type at this point, omap3 dplls
>> require some modifications on top of this, and are provided later in the
>> series.
>
> ok.
>
>>
>>>
>>>>
>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>> ---
>>>>   drivers/clk/omap/Makefile |    2 +-
>>>>   drivers/clk/omap/clk.c    |    1 +
>>>>   drivers/clk/omap/dpll.c   |  295
>>>> +++++++++++++++++++++++++++++++++++++++++++++
>>>
>>> Device Tree Binding documentation?
>>
>> Didn't bother writing those yet as I haven't received too much feedback
>> whether this approach is acceptable or not.
>
> Documentation helps simplify the understanding of expected usage - this
> is useful to review approach as well :)

True, I'll try adding docs for next rev.

>
>>>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>>>> index 4bf1929..1dafdaa 100644
>>>> --- a/drivers/clk/omap/clk.c
>>>> +++ b/drivers/clk/omap/clk.c
>>>> @@ -28,6 +28,7 @@ static const struct of_device_id clk_match[] = {
>>>>           .data = of_fixed_factor_clk_setup, },
>>>>       {.compatible = "divider-clock", .data = of_divider_clk_setup, },
>>>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>>>> +    {.compatible = "ti,omap4-dpll-clock", .data =
>>>> of_omap4_dpll_setup, },
>>>>       {},
>>>>   };
>>> you would not need this if you did just of_clk_init(NULL); ?
>>
>> Why not? And I think we still need to do this.
>
> CLK_OF_DECLARE will take care of having all required clks registered
> of_clk_init(NULL); will pick up from that list.
>
> that will remove all extra exports, and make clk.c redundant.
> [...]

Yep, as agreed on previous patch.

>
>>
>>>
>>>> +#include <linux/clk/omap.h>
>>>
>>> why?
>>
>> Need dpll_data definition for example.
> OK - without the ordering of patches, it was not obvious. structures aside,
>
> We should move the functions to this file instead and empty out
> mach-omap2 gradually, omap_dpll.h should be exported and used by
> mach-omap2, rather than the other way around.

Yeah, the clock stuff should evolve and move here. I just need to start 
from somewhere.

>
>>>> +
>>>> +struct clk *omap_clk_register_dpll(struct device *dev, const char
>>>> *name,
>>>> +        const char **parent_names, int num_parents, unsigned long
>>>> flags,
>>>> +        struct dpll_data *dpll_data, const char *clkdm_name,
>>>> +        const struct clk_ops *ops)
>>>
>>> why should this be public?
>>
>> Currently does not need to be, but someone could in theory build up
>> cclockXxxx_data.c file and use these calls from there. Kind of legacy
>> support, see some of the basic clk types. I guess I can add static to
>> this, and remove some of the params along.
>>
>
> thanks. we should keep unneeded stuff in static unless a specific
> provable need really arises.
>
>>>
>>> I am assuming you do not do parameter check as you expect clk_register
>>> to do the same?
>>
>> True, so I'll change the above function to static.
>>
>>>
>>>> +
>>>> +    /* allocate the divider */
>>>> +    clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
>>> checkpatch complained:
>>> CHECK: Prefer kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct
>>> clk_hw_omap)...)
>>
>> Hmm, I didn't get this with checkpatch. Some special option/version you
>> use? I still see both types of sizeof used in the kernel.
> use checkpatch with --strict option

Okay.

>
>>
>>>
>>> or given we have dev, devm_kzalloc?
>>
>> Actually we don't have dev, check how this is called from below.
>
> ok.
>
>>
>>>> +    if (!clk_hw) {
>>>> +        pr_err("%s: could not allocate clk_hw_omap\n", __func__);
>>>> +        return ERR_PTR(-ENOMEM);
>>>> +    }
>>>> +
>>>> +    clk_hw->dpll_data = dpll_data;
>>>> +    clk_hw->ops = &clkhwops_omap3_dpll;
>>>> +    clk_hw->clkdm_name = clkdm_name;
>>>> +    clk_hw->hw.init = &init;
>>>> +
>>>> +    init.name = name;
>>>> +    init.ops = ops;
>>>> +    init.flags = flags;
>>>> +    init.parent_names = parent_names;
>>>> +    init.num_parents = num_parents;
>>>> +
>>>> +    /* register the clock */
>>>> +    clk = clk_register(dev, &clk_hw->hw);
>>>> +
>>>> +    if (IS_ERR(clk))
>>>> +        kfree(clk_hw);
>>>> +    else
>>>> +        omap2_init_clk_hw_omap_clocks(clk);
>>> what if init fails? and it is in mach-omap2 at this point in time?
>>
>> Yea, this just calls the autoidle init part under mach-omap2.
>
> we should make this independent of mach-omap2. calls should be made to
> here if needed from mach-omap2 instead of the other way around. OR the
> required code should be moved over here.

Same comment as above, I did not want to move the allow / deny idle 
portion of every possible clock under drivers/clk/omap yet. This is on 
the evolution path for this driver.

>
>>
>>>
>>>> +
>>>> +    return clk;
>>>> +}
>>>
> <snip>
>>>
>>>> +
>>>> +    if (of_property_read_bool(node, "ti,dpll-j-type")) {
>>>> +        dd->sddiv_mask = 0xff000000;
>>>> +        mult_mask = 0xfff << 8;
>>>> +        div1_mask = 0xff;
>>>> +        max_multiplier = 4095;
>>>> +        max_divider = 256;
>>>> +    }
>>>> +
>>>> +    if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
>>> I think we need bindings to understand this better.
>>
>> Or documentation you mean?
>
> yes. Documentation/devicetree/bindings/....
>
>>
>>>
>>>> +        dd->m4xen_mask = 0x800;
>>>> +        dd->lpmode_mask = 1 << 10;
>>>> +    }
>>>> +
>>>> +    dd->mult_mask = mult_mask;
>>>> +    dd->div1_mask = div1_mask;
>>>> +    dd->max_multiplier = max_multiplier;
>>>> +    dd->max_divider = max_divider;
>>>> +    dd->min_divider = min_divider;
>>>> +
>>>> +    clk = omap_clk_register_dpll(NULL, clk_name, parent_names,
>>>> +                num_parents, dpll_flags, dd,
>>>> +                clkdm_name, ops);
>>>> +
>>>> +    if (!IS_ERR(clk))
>>>> +        of_clk_add_provider(node, of_clk_src_simple_get, clk);
>>> error check?
>>
>> This is not done with other drivers either. Would require clk_unregister
>> use to cleanup the above register call which is currently unavailable. I
>> could add an error trace for this though.
>
> you can definitely ensure this driver is clean :)

Not really, as the clk_unregister does not work, so the implementation 
for this can't be exactly clean yet. I don't know if we want to 
unregister any clocks anyway if this would fail...

>
>>>
>>>> +    kfree(dd);
>>>> +    return;
>>>> +}
>>>> +
>>>> +static void __init of_omap_dpll_x2_setup(struct device_node *node)
>>>> +{
>>>> +    struct clk *clk;
>>>> +    const char *clk_name = node->name;
>>>> +    void __iomem *reg;
>>>> +    const char *parent_name;
>>>> +
>>>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>>>> +
>>>> +    parent_name = of_clk_get_parent_name(node, 0);
>>>> +
>>>> +    reg = of_iomap(node, 0);
>>>
>>> if dts has errors, should we not verify mandatory parameters?
>>
>> You mean checking the validity of this pointer? It seems of_iomap does
>> something strange when it fails, e.g. when passed a 0x0 from DT. You can
>> see what I do in a later patch for adding am335x support for DPLLs.
>
> in general, helping dts writers know of invalid/out of range parameters
> with a log message helps ensure those are fixed either on development or
> at some point - it aids debug instead of others having to scratch heads
> wondering what happened.
>
> if mandatory parameters are verifable at setup and decided as bad,
> refusing to register is good idea especially with logs, they tend to get
> fixed rather faster - than an error that pops up when a specific DPLL is
> used at a later point in time.
>
> just my 2 cents.
> [..]

I'll add verification for the of_iomap calls.

>
>>>> +}
>>>> +EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>>>
>>> you can drop the export if you use of_clk_init(NULL);
>>
>> Hmm no?
>>
>> Actually dug this further, I think the init setup is slightly wrong at
>> the moment, we should not do CLK_OF_DECLARE at all within the omap
>> specific clock drivers, but instead just use the match table from clk.c.
>> I'll change it like so.
>>
>>>
>>>> +CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock",
>>>> of_omap4_dpll_setup);
>>
>> So, for example this should be removed. We don't want to support this
>> clock type on non-omap platforms just to avoid problems.
>
> As discussed offline, doing the other way around and doing what all
> other platforms do (which is CLK_OF_DECLARE) is a better idea to ensure
> standard APIs are carried forward and not spin off OMAP as a "special
> platform" - at least I dont seem to see any good reasoning for it yet.

Yea.

[PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Tero Kristo]

On 08/01/2013 05:00 PM, Nishanth Menon wrote:
> On 07/31/2013 04:46 AM, Tero Kristo wrote:
>> On 07/30/2013 07:23 PM, Nishanth Menon wrote:
>>> This patch probably was submitted in the wrong sequence - fails build
>>> and few other issues below.
>>
>> Yeah, I'll double check the build sequence for these.
>>
>>>
>>> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>>>> The OMAP clock driver now supports DPLL clock type. This patch also
>>>> adds support for DT DPLL nodes.
>>>
>>> Then why is $subject specific to OMAP4? is that because of
>>> of_omap4_dpll_setup?
>>
>> The driver only supports omap4 dpll type at this point, omap3 dplls
>> require some modifications on top of this, and are provided later in the
>> series.
>
> ok.
>
>>
>>>
>>>>
>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>> ---
>>>>   drivers/clk/omap/Makefile |    2 +-
>>>>   drivers/clk/omap/clk.c    |    1 +
>>>>   drivers/clk/omap/dpll.c   |  295
>>>> +++++++++++++++++++++++++++++++++++++++++++++
>>>
>>> Device Tree Binding documentation?
>>
>> Didn't bother writing those yet as I haven't received too much feedback
>> whether this approach is acceptable or not.
>
> Documentation helps simplify the understanding of expected usage - this
> is useful to review approach as well :)

True, I'll try adding docs for next rev.

>
>>>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>>>> index 4bf1929..1dafdaa 100644
>>>> --- a/drivers/clk/omap/clk.c
>>>> +++ b/drivers/clk/omap/clk.c
>>>> @@ -28,6 +28,7 @@ static const struct of_device_id clk_match[] = {
>>>>           .data = of_fixed_factor_clk_setup, },
>>>>       {.compatible = "divider-clock", .data = of_divider_clk_setup, },
>>>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>>>> +    {.compatible = "ti,omap4-dpll-clock", .data =
>>>> of_omap4_dpll_setup, },
>>>>       {},
>>>>   };
>>> you would not need this if you did just of_clk_init(NULL); ?
>>
>> Why not? And I think we still need to do this.
>
> CLK_OF_DECLARE will take care of having all required clks registered
> of_clk_init(NULL); will pick up from that list.
>
> that will remove all extra exports, and make clk.c redundant.
> [...]

Yep, as agreed on previous patch.

>
>>
>>>
>>>> +#include <linux/clk/omap.h>
>>>
>>> why?
>>
>> Need dpll_data definition for example.
> OK - without the ordering of patches, it was not obvious. structures aside,
>
> We should move the functions to this file instead and empty out
> mach-omap2 gradually, omap_dpll.h should be exported and used by
> mach-omap2, rather than the other way around.

Yeah, the clock stuff should evolve and move here. I just need to start 
from somewhere.

>
>>>> +
>>>> +struct clk *omap_clk_register_dpll(struct device *dev, const char
>>>> *name,
>>>> +        const char **parent_names, int num_parents, unsigned long
>>>> flags,
>>>> +        struct dpll_data *dpll_data, const char *clkdm_name,
>>>> +        const struct clk_ops *ops)
>>>
>>> why should this be public?
>>
>> Currently does not need to be, but someone could in theory build up
>> cclockXxxx_data.c file and use these calls from there. Kind of legacy
>> support, see some of the basic clk types. I guess I can add static to
>> this, and remove some of the params along.
>>
>
> thanks. we should keep unneeded stuff in static unless a specific
> provable need really arises.
>
>>>
>>> I am assuming you do not do parameter check as you expect clk_register
>>> to do the same?
>>
>> True, so I'll change the above function to static.
>>
>>>
>>>> +
>>>> +    /* allocate the divider */
>>>> +    clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
>>> checkpatch complained:
>>> CHECK: Prefer kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct
>>> clk_hw_omap)...)
>>
>> Hmm, I didn't get this with checkpatch. Some special option/version you
>> use? I still see both types of sizeof used in the kernel.
> use checkpatch with --strict option

Okay.

>
>>
>>>
>>> or given we have dev, devm_kzalloc?
>>
>> Actually we don't have dev, check how this is called from below.
>
> ok.
>
>>
>>>> +    if (!clk_hw) {
>>>> +        pr_err("%s: could not allocate clk_hw_omap\n", __func__);
>>>> +        return ERR_PTR(-ENOMEM);
>>>> +    }
>>>> +
>>>> +    clk_hw->dpll_data = dpll_data;
>>>> +    clk_hw->ops = &clkhwops_omap3_dpll;
>>>> +    clk_hw->clkdm_name = clkdm_name;
>>>> +    clk_hw->hw.init = &init;
>>>> +
>>>> +    init.name = name;
>>>> +    init.ops = ops;
>>>> +    init.flags = flags;
>>>> +    init.parent_names = parent_names;
>>>> +    init.num_parents = num_parents;
>>>> +
>>>> +    /* register the clock */
>>>> +    clk = clk_register(dev, &clk_hw->hw);
>>>> +
>>>> +    if (IS_ERR(clk))
>>>> +        kfree(clk_hw);
>>>> +    else
>>>> +        omap2_init_clk_hw_omap_clocks(clk);
>>> what if init fails? and it is in mach-omap2 at this point in time?
>>
>> Yea, this just calls the autoidle init part under mach-omap2.
>
> we should make this independent of mach-omap2. calls should be made to
> here if needed from mach-omap2 instead of the other way around. OR the
> required code should be moved over here.

Same comment as above, I did not want to move the allow / deny idle 
portion of every possible clock under drivers/clk/omap yet. This is on 
the evolution path for this driver.

>
>>
>>>
>>>> +
>>>> +    return clk;
>>>> +}
>>>
> <snip>
>>>
>>>> +
>>>> +    if (of_property_read_bool(node, "ti,dpll-j-type")) {
>>>> +        dd->sddiv_mask = 0xff000000;
>>>> +        mult_mask = 0xfff << 8;
>>>> +        div1_mask = 0xff;
>>>> +        max_multiplier = 4095;
>>>> +        max_divider = 256;
>>>> +    }
>>>> +
>>>> +    if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
>>> I think we need bindings to understand this better.
>>
>> Or documentation you mean?
>
> yes. Documentation/devicetree/bindings/....
>
>>
>>>
>>>> +        dd->m4xen_mask = 0x800;
>>>> +        dd->lpmode_mask = 1 << 10;
>>>> +    }
>>>> +
>>>> +    dd->mult_mask = mult_mask;
>>>> +    dd->div1_mask = div1_mask;
>>>> +    dd->max_multiplier = max_multiplier;
>>>> +    dd->max_divider = max_divider;
>>>> +    dd->min_divider = min_divider;
>>>> +
>>>> +    clk = omap_clk_register_dpll(NULL, clk_name, parent_names,
>>>> +                num_parents, dpll_flags, dd,
>>>> +                clkdm_name, ops);
>>>> +
>>>> +    if (!IS_ERR(clk))
>>>> +        of_clk_add_provider(node, of_clk_src_simple_get, clk);
>>> error check?
>>
>> This is not done with other drivers either. Would require clk_unregister
>> use to cleanup the above register call which is currently unavailable. I
>> could add an error trace for this though.
>
> you can definitely ensure this driver is clean :)

Not really, as the clk_unregister does not work, so the implementation 
for this can't be exactly clean yet. I don't know if we want to 
unregister any clocks anyway if this would fail...

>
>>>
>>>> +    kfree(dd);
>>>> +    return;
>>>> +}
>>>> +
>>>> +static void __init of_omap_dpll_x2_setup(struct device_node *node)
>>>> +{
>>>> +    struct clk *clk;
>>>> +    const char *clk_name = node->name;
>>>> +    void __iomem *reg;
>>>> +    const char *parent_name;
>>>> +
>>>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>>>> +
>>>> +    parent_name = of_clk_get_parent_name(node, 0);
>>>> +
>>>> +    reg = of_iomap(node, 0);
>>>
>>> if dts has errors, should we not verify mandatory parameters?
>>
>> You mean checking the validity of this pointer? It seems of_iomap does
>> something strange when it fails, e.g. when passed a 0x0 from DT. You can
>> see what I do in a later patch for adding am335x support for DPLLs.
>
> in general, helping dts writers know of invalid/out of range parameters
> with a log message helps ensure those are fixed either on development or
> at some point - it aids debug instead of others having to scratch heads
> wondering what happened.
>
> if mandatory parameters are verifable at setup and decided as bad,
> refusing to register is good idea especially with logs, they tend to get
> fixed rather faster - than an error that pops up when a specific DPLL is
> used at a later point in time.
>
> just my 2 cents.
> [..]

I'll add verification for the of_iomap calls.

>
>>>> +}
>>>> +EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>>>
>>> you can drop the export if you use of_clk_init(NULL);
>>
>> Hmm no?
>>
>> Actually dug this further, I think the init setup is slightly wrong at
>> the moment, we should not do CLK_OF_DECLARE at all within the omap
>> specific clock drivers, but instead just use the match table from clk.c.
>> I'll change it like so.
>>
>>>
>>>> +CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock",
>>>> of_omap4_dpll_setup);
>>
>> So, for example this should be removed. We don't want to support this
>> clock type on non-omap platforms just to avoid problems.
>
> As discussed offline, doing the other way around and doing what all
> other platforms do (which is CLK_OF_DECLARE) is a better idea to ensure
> standard APIs are carried forward and not spin off OMAP as a "special
> platform" - at least I dont seem to see any good reasoning for it yet.

Yea.

Re: [PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Nishanth Menon]

On Thu, Aug 1, 2013 at 10:08 AM, Tero Kristo <t-kristo@ti.com> wrote:
>> We should move the functions to this file instead and empty out
>> mach-omap2 gradually, omap_dpll.h should be exported and used by
>> mach-omap2, rather than the other way around.
>
>
> Yeah, the clock stuff should evolve and move here. I just need to start from
> somewhere.

yep, this step is good and as part of this step, moving the used
functions from mach-omap2 to dpll.c is indeed the right step for us to
do proper cleanup.

it is a question of what we bring into drivers/clk and ensuring what
we bring in is clean as well.

Regards,
Nishanth Menon

[PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Nishanth Menon]

On Thu, Aug 1, 2013 at 10:08 AM, Tero Kristo <t-kristo@ti.com> wrote:
>> We should move the functions to this file instead and empty out
>> mach-omap2 gradually, omap_dpll.h should be exported and used by
>> mach-omap2, rather than the other way around.
>
>
> Yeah, the clock stuff should evolve and move here. I just need to start from
> somewhere.

yep, this step is good and as part of this step, moving the used
functions from mach-omap2 to dpll.c is indeed the right step for us to
do proper cleanup.

it is a question of what we bring into drivers/clk and ensuring what
we bring in is clean as well.

Regards,
Nishanth Menon

Re: [PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Rajendra Nayak]

Tero,

On Tuesday 23 July 2013 12:49 PM, Tero Kristo wrote:
> +	dd->control_reg = of_iomap(node, 0);
> +	dd->idlest_reg = of_iomap(node, 1);
> +	dd->autoidle_reg = of_iomap(node, 2);
> +	dd->mult_div1_reg = of_iomap(node, 3);
> +
[]...
> +	reg = of_iomap(node, 0);

Doing an of_iomap() for every single clock register seems like an overkill
and might have performance penalties at boot.

regards,
Rajendra

[PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Rajendra Nayak]

Tero,

On Tuesday 23 July 2013 12:49 PM, Tero Kristo wrote:
> +	dd->control_reg = of_iomap(node, 0);
> +	dd->idlest_reg = of_iomap(node, 1);
> +	dd->autoidle_reg = of_iomap(node, 2);
> +	dd->mult_div1_reg = of_iomap(node, 3);
> +
[]...
> +	reg = of_iomap(node, 0);

Doing an of_iomap() for every single clock register seems like an overkill
and might have performance penalties at boot.

regards,
Rajendra

Re: [PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Nishanth Menon]

On 08/01/2013 03:29 AM, Rajendra Nayak wrote:
> Tero,
>
> On Tuesday 23 July 2013 12:49 PM, Tero Kristo wrote:
>> +	dd->control_reg = of_iomap(node, 0);
>> +	dd->idlest_reg = of_iomap(node, 1);
>> +	dd->autoidle_reg = of_iomap(node, 2);
>> +	dd->mult_div1_reg = of_iomap(node, 3);
>> +
> []...
>> +	reg = of_iomap(node, 0);
>
> Doing an of_iomap() for every single clock register seems like an overkill
> and might have performance penalties at boot.

the other option might be to use offset and a single allocation - but I 
think Tero should comment if this is possible or if registers on some 
SoCs are strewn all over the place

-- 
Regards,
Nishanth Menon

[PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Nishanth Menon]

On 08/01/2013 03:29 AM, Rajendra Nayak wrote:
> Tero,
>
> On Tuesday 23 July 2013 12:49 PM, Tero Kristo wrote:
>> +	dd->control_reg = of_iomap(node, 0);
>> +	dd->idlest_reg = of_iomap(node, 1);
>> +	dd->autoidle_reg = of_iomap(node, 2);
>> +	dd->mult_div1_reg = of_iomap(node, 3);
>> +
> []...
>> +	reg = of_iomap(node, 0);
>
> Doing an of_iomap() for every single clock register seems like an overkill
> and might have performance penalties at boot.

the other option might be to use offset and a single allocation - but I 
think Tero should comment if this is possible or if registers on some 
SoCs are strewn all over the place

-- 
Regards,
Nishanth Menon

Re: [PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Tero Kristo]

On 08/01/2013 06:10 PM, Nishanth Menon wrote:
> On 08/01/2013 03:29 AM, Rajendra Nayak wrote:
>> Tero,
>>
>> On Tuesday 23 July 2013 12:49 PM, Tero Kristo wrote:
>>> +    dd->control_reg = of_iomap(node, 0);
>>> +    dd->idlest_reg = of_iomap(node, 1);
>>> +    dd->autoidle_reg = of_iomap(node, 2);
>>> +    dd->mult_div1_reg = of_iomap(node, 3);
>>> +
>> []...
>>> +    reg = of_iomap(node, 0);
>>
>> Doing an of_iomap() for every single clock register seems like an
>> overkill
>> and might have performance penalties at boot.
>
> the other option might be to use offset and a single allocation - but I
> think Tero should comment if this is possible or if registers on some
> SoCs are strewn all over the place

Well, currently the basic clock nodes also do their individual 
of_iomaps, so doing a tweak only for the OMAP DPLLs is not going to 
change the figure much.

A generic solution is needed but I think this was commented elsewhere by 
Mike to remain as future optimization (can't find the reference to this 
with a quick search though.)

-Tero

[PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support

[Tero Kristo]

On 08/01/2013 06:10 PM, Nishanth Menon wrote:
> On 08/01/2013 03:29 AM, Rajendra Nayak wrote:
>> Tero,
>>
>> On Tuesday 23 July 2013 12:49 PM, Tero Kristo wrote:
>>> +    dd->control_reg = of_iomap(node, 0);
>>> +    dd->idlest_reg = of_iomap(node, 1);
>>> +    dd->autoidle_reg = of_iomap(node, 2);
>>> +    dd->mult_div1_reg = of_iomap(node, 3);
>>> +
>> []...
>>> +    reg = of_iomap(node, 0);
>>
>> Doing an of_iomap() for every single clock register seems like an
>> overkill
>> and might have performance penalties at boot.
>
> the other option might be to use offset and a single allocation - but I
> think Tero should comment if this is possible or if registers on some
> SoCs are strewn all over the place

Well, currently the basic clock nodes also do their individual 
of_iomaps, so doing a tweak only for the OMAP DPLLs is not going to 
change the figure much.

A generic solution is needed but I think this was commented elsewhere by 
Mike to remain as future optimization (can't find the reference to this 
with a quick search though.)

-Tero

[PATCHv4 04/33] CLK: omap: move part of the machine specific clock header contents to driver

[Tero Kristo]

Some of the clock.h contents are needed by the new OMAP clock driver,
including dpll_data and clk_hw_omap. Thus, move these to the generic
omap header file which can be accessed by the driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.h |  151 +----------------------------------------
 include/linux/clk/omap.h    |  157 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 157 insertions(+), 151 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 7aa32cd..d1a3125 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
 
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
+#include <linux/clk/omap.h>
 
 struct omap_clk {
 	u16				cpu;
@@ -178,83 +179,6 @@ struct clksel {
 	const struct clksel_rate *rates;
 };
 
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N bitfields
- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
- * @clk_bypass: struct clk pointer to the clock's bypass clock input
- * @clk_ref: struct clk pointer to the clock's reference clock input
- * @control_reg: register containing the DPLL mode bitfield
- * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
- * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
- * @last_rounded_m4xen: cache of the last M4X result of
- *			omap4_dpll_regm4xen_round_rate()
- * @last_rounded_lpmode: cache of the last lpmode result of
- *			 omap4_dpll_lpmode_recalc()
- * @max_multiplier: maximum valid non-bypass multiplier value (actual)
- * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
- * @min_divider: minimum valid non-bypass divider value (actual)
- * @max_divider: maximum valid non-bypass divider value (actual)
- * @modes: possible values of @enable_mask
- * @autoidle_reg: register containing the DPLL autoidle mode bitfield
- * @idlest_reg: register containing the DPLL idle status bitfield
- * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
- * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
- * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
- * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
- * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
- * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
- * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
- * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
- * @flags: DPLL type/features (see below)
- *
- * Possible values for @flags:
- * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- *
- * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
- *
- * XXX Some DPLLs have multiple bypass inputs, so it's not technically
- * correct to only have one @clk_bypass pointer.
- *
- * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
- * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a different structure, so that the runtime-fixed data
- * can be placed into read-only space.
- */
-struct dpll_data {
-	void __iomem		*mult_div1_reg;
-	u32			mult_mask;
-	u32			div1_mask;
-	struct clk		*clk_bypass;
-	struct clk		*clk_ref;
-	void __iomem		*control_reg;
-	u32			enable_mask;
-	unsigned long		last_rounded_rate;
-	u16			last_rounded_m;
-	u8			last_rounded_m4xen;
-	u8			last_rounded_lpmode;
-	u16			max_multiplier;
-	u8			last_rounded_n;
-	u8			min_divider;
-	u16			max_divider;
-	u8			modes;
-	void __iomem		*autoidle_reg;
-	void __iomem		*idlest_reg;
-	u32			autoidle_mask;
-	u32			freqsel_mask;
-	u32			idlest_mask;
-	u32			dco_mask;
-	u32			sddiv_mask;
-	u32			lpmode_mask;
-	u32			m4xen_mask;
-	u8			auto_recal_bit;
-	u8			recal_en_bit;
-	u8			recal_st_bit;
-	u8			flags;
-};
-
 /*
  * struct clk.flags possibilities
  *
@@ -274,56 +198,6 @@ struct dpll_data {
 #define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
 #define CLOCK_CLKOUTX2		(1 << 5)
 
-/**
- * struct clk_hw_omap - OMAP struct clk
- * @node: list_head connecting this clock into the full clock list
- * @enable_reg: register to write to enable the clock (see @enable_bit)
- * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
- * @flags: see "struct clk.flags possibilities" above
- * @clksel_reg: for clksel clks, register va containing src/divisor select
- * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
- * @clksel: for clksel clks, pointer to struct clksel for this clock
- * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
- * @clkdm_name: clockdomain name that this clock is contained in
- * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
- * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
- * @src_offset: bitshift for source selection bitfield (OMAP1 only)
- *
- * XXX @rate_offset, @src_offset should probably be removed and OMAP1
- * clock code converted to use clksel.
- *
- */
-
-struct clk_hw_omap_ops;
-
-struct clk_hw_omap {
-	struct clk_hw		hw;
-	struct list_head	node;
-	unsigned long		fixed_rate;
-	u8			fixed_div;
-	void __iomem		*enable_reg;
-	u8			enable_bit;
-	u8			flags;
-	void __iomem		*clksel_reg;
-	u32			clksel_mask;
-	const struct clksel	*clksel;
-	struct dpll_data	*dpll_data;
-	const char		*clkdm_name;
-	struct clockdomain	*clkdm;
-	const struct clk_hw_omap_ops	*ops;
-};
-
-struct clk_hw_omap_ops {
-	void			(*find_idlest)(struct clk_hw_omap *oclk,
-					void __iomem **idlest_reg,
-					u8 *idlest_bit, u8 *idlest_val);
-	void			(*find_companion)(struct clk_hw_omap *oclk,
-					void __iomem **other_reg,
-					u8 *other_bit);
-	void			(*allow_idle)(struct clk_hw_omap *oclk);
-	void			(*deny_idle)(struct clk_hw_omap *oclk);
-};
-
 unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
 					unsigned long parent_rate);
 
@@ -356,28 +230,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
 /* DPLL Type and DCO Selection Flags */
 #define DPLL_J_TYPE		0x1
 
-long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
-			unsigned long *parent_rate);
-unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
-int omap3_noncore_dpll_enable(struct clk_hw *hw);
-void omap3_noncore_dpll_disable(struct clk_hw *hw);
-int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
-				unsigned long parent_rate);
 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
 void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
 void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
-unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
-				    unsigned long parent_rate);
 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
-unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
-				unsigned long parent_rate);
-long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
-				    unsigned long target_rate,
-				    unsigned long *parent_rate);
 
-void omap2_init_clk_clkdm(struct clk_hw *clk);
 void __init omap2_clk_disable_clkdm_control(void);
 
 /* clkt_clksel.c public functions */
@@ -396,7 +255,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
 extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
 extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
 
-u8 omap2_init_dpll_parent(struct clk_hw *hw);
 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
 
 int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -408,9 +266,7 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 				void __iomem **idlest_reg,
 				u8 *idlest_bit, u8 *idlest_val);
-void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap2_clk_enable_autoidle_all(void);
-int omap2_clk_disable_autoidle_all(void);
 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
@@ -431,10 +287,8 @@ extern const struct clksel_rate gfx_l3_rates[];
 extern const struct clksel_rate dsp_ick_rates[];
 extern struct clk dummy_ck;
 
-extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
 extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 extern const struct clk_hw_omap_ops clkhwops_iclk;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
@@ -460,8 +314,5 @@ extern const struct clksel_rate div31_1to31_rates[];
 
 extern int am33xx_clk_init(void);
 
-extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
-extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
-
 extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
 #endif
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index 647f02f..cba892a 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -19,6 +19,161 @@
 #ifndef __LINUX_CLK_OMAP_H_
 #define __LINUX_CLK_OMAP_H_
 
-int __init dt_omap_clk_init(void);
+/**
+ * struct dpll_data - DPLL registers and integration data
+ * @mult_div1_reg: register containing the DPLL M and N bitfields
+ * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
+ * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
+ * @clk_bypass: struct clk pointer to the clock's bypass clock input
+ * @clk_ref: struct clk pointer to the clock's reference clock input
+ * @control_reg: register containing the DPLL mode bitfield
+ * @enable_mask: mask of the DPLL mode bitfield in @control_reg
+ * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
+ * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
+ * @last_rounded_m4xen: cache of the last M4X result of
+ *                     omap4_dpll_regm4xen_round_rate()
+ * @last_rounded_lpmode: cache of the last lpmode result of
+ *                      omap4_dpll_lpmode_recalc()
+ * @max_multiplier: maximum valid non-bypass multiplier value (actual)
+ * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
+ * @min_divider: minimum valid non-bypass divider value (actual)
+ * @max_divider: maximum valid non-bypass divider value (actual)
+ * @modes: possible values of @enable_mask
+ * @autoidle_reg: register containing the DPLL autoidle mode bitfield
+ * @idlest_reg: register containing the DPLL idle status bitfield
+ * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
+ * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
+ * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
+ * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
+ * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
+ * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
+ * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
+ * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
+ * @flags: DPLL type/features (see below)
+ *
+ * Possible values for @flags:
+ * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
+ *
+ * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
+ *
+ * XXX Some DPLLs have multiple bypass inputs, so it's not technically
+ * correct to only have one @clk_bypass pointer.
+ *
+ * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
+ * @last_rounded_n) should be separated from the runtime-fixed fields
+ * and placed into a different structure, so that the runtime-fixed data
+ * can be placed into read-only space.
+ */
+struct dpll_data {
+	void __iomem		*mult_div1_reg;
+	u32			mult_mask;
+	u32			div1_mask;
+	struct clk		*clk_bypass;
+	struct clk		*clk_ref;
+	void __iomem		*control_reg;
+	u32			enable_mask;
+	unsigned long		last_rounded_rate;
+	u16			last_rounded_m;
+	u8			last_rounded_m4xen;
+	u8			last_rounded_lpmode;
+	u16			max_multiplier;
+	u8			last_rounded_n;
+	u8			min_divider;
+	u16			max_divider;
+	u8			modes;
+	void __iomem		*autoidle_reg;
+	void __iomem		*idlest_reg;
+	u32			autoidle_mask;
+	u32			freqsel_mask;
+	u32			idlest_mask;
+	u32			dco_mask;
+	u32			sddiv_mask;
+	u32			lpmode_mask;
+	u32			m4xen_mask;
+	u8			auto_recal_bit;
+	u8			recal_en_bit;
+	u8			recal_st_bit;
+	u8			flags;
+};
+
+/**
+ * struct clk_hw_omap - OMAP struct clk
+ * @node: list_head connecting this clock into the full clock list
+ * @enable_reg: register to write to enable the clock (see @enable_bit)
+ * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
+ * @flags: see "struct clk.flags possibilities" above
+ * @clksel_reg: for clksel clks, register va containing src/divisor select
+ * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
+ * @clksel: for clksel clks, pointer to struct clksel for this clock
+ * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
+ * @clkdm_name: clockdomain name that this clock is contained in
+ * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
+ * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
+ * @src_offset: bitshift for source selection bitfield (OMAP1 only)
+ *
+ * XXX @rate_offset, @src_offset should probably be removed and OMAP1
+ * clock code converted to use clksel.
+ *
+ */
+
+struct clk_hw_omap_ops;
+
+struct clk_hw_omap {
+	struct clk_hw		hw;
+	struct list_head	node;
+	unsigned long		fixed_rate;
+	u8			fixed_div;
+	void __iomem		*enable_reg;
+	u8			enable_bit;
+	u8			flags;
+	void __iomem		*clksel_reg;
+	u32			clksel_mask;
+	const struct clksel	*clksel;
+	struct dpll_data	*dpll_data;
+	const char		*clkdm_name;
+	struct clockdomain	*clkdm;
+	const struct clk_hw_omap_ops	*ops;
+};
+
+struct clk_hw_omap_ops {
+	void			(*find_idlest)(struct clk_hw_omap *oclk,
+					void __iomem **idlest_reg,
+					u8 *idlest_bit, u8 *idlest_val);
+	void			(*find_companion)(struct clk_hw_omap *oclk,
+					void __iomem **other_reg,
+					u8 *other_bit);
+	void			(*allow_idle)(struct clk_hw_omap *oclk);
+	void			(*deny_idle)(struct clk_hw_omap *oclk);
+};
+
+void omap2_init_clk_hw_omap_clocks(struct clk *clk);
+int omap3_noncore_dpll_enable(struct clk_hw *hw);
+void omap3_noncore_dpll_disable(struct clk_hw *hw);
+int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long parent_rate);
+unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
+				unsigned long parent_rate);
+long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
+				    unsigned long target_rate,
+				    unsigned long *parent_rate);
+u8 omap2_init_dpll_parent(struct clk_hw *hw);
+unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
+long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
+			unsigned long *parent_rate);
+void omap2_init_clk_clkdm(struct clk_hw *clk);
+unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
+				    unsigned long parent_rate);
+
+int omap2_clkops_enable_clkdm(struct clk_hw *hw);
+void omap2_clkops_disable_clkdm(struct clk_hw *hw);
+
+int omap2_clk_disable_autoidle_all(void);
+
+extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
+extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+
+/* DT functions */
+int dt_omap_clk_init(void);
+void of_omap4_dpll_setup(struct device_node *node);
 
 #endif
-- 
1.7.9.5

[PATCHv4 04/33] CLK: omap: move part of the machine specific clock header contents to driver

[Tero Kristo]

Some of the clock.h contents are needed by the new OMAP clock driver,
including dpll_data and clk_hw_omap. Thus, move these to the generic
omap header file which can be accessed by the driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.h |  151 +----------------------------------------
 include/linux/clk/omap.h    |  157 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 157 insertions(+), 151 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 7aa32cd..d1a3125 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
 
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
+#include <linux/clk/omap.h>
 
 struct omap_clk {
 	u16				cpu;
@@ -178,83 +179,6 @@ struct clksel {
 	const struct clksel_rate *rates;
 };
 
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N bitfields
- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
- * @clk_bypass: struct clk pointer to the clock's bypass clock input
- * @clk_ref: struct clk pointer to the clock's reference clock input
- * @control_reg: register containing the DPLL mode bitfield
- * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
- * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
- * @last_rounded_m4xen: cache of the last M4X result of
- *			omap4_dpll_regm4xen_round_rate()
- * @last_rounded_lpmode: cache of the last lpmode result of
- *			 omap4_dpll_lpmode_recalc()
- * @max_multiplier: maximum valid non-bypass multiplier value (actual)
- * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
- * @min_divider: minimum valid non-bypass divider value (actual)
- * @max_divider: maximum valid non-bypass divider value (actual)
- * @modes: possible values of @enable_mask
- * @autoidle_reg: register containing the DPLL autoidle mode bitfield
- * @idlest_reg: register containing the DPLL idle status bitfield
- * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
- * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
- * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
- * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
- * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
- * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
- * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
- * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
- * @flags: DPLL type/features (see below)
- *
- * Possible values for @flags:
- * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- *
- * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
- *
- * XXX Some DPLLs have multiple bypass inputs, so it's not technically
- * correct to only have one @clk_bypass pointer.
- *
- * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
- * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a different structure, so that the runtime-fixed data
- * can be placed into read-only space.
- */
-struct dpll_data {
-	void __iomem		*mult_div1_reg;
-	u32			mult_mask;
-	u32			div1_mask;
-	struct clk		*clk_bypass;
-	struct clk		*clk_ref;
-	void __iomem		*control_reg;
-	u32			enable_mask;
-	unsigned long		last_rounded_rate;
-	u16			last_rounded_m;
-	u8			last_rounded_m4xen;
-	u8			last_rounded_lpmode;
-	u16			max_multiplier;
-	u8			last_rounded_n;
-	u8			min_divider;
-	u16			max_divider;
-	u8			modes;
-	void __iomem		*autoidle_reg;
-	void __iomem		*idlest_reg;
-	u32			autoidle_mask;
-	u32			freqsel_mask;
-	u32			idlest_mask;
-	u32			dco_mask;
-	u32			sddiv_mask;
-	u32			lpmode_mask;
-	u32			m4xen_mask;
-	u8			auto_recal_bit;
-	u8			recal_en_bit;
-	u8			recal_st_bit;
-	u8			flags;
-};
-
 /*
  * struct clk.flags possibilities
  *
@@ -274,56 +198,6 @@ struct dpll_data {
 #define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
 #define CLOCK_CLKOUTX2		(1 << 5)
 
-/**
- * struct clk_hw_omap - OMAP struct clk
- * @node: list_head connecting this clock into the full clock list
- * @enable_reg: register to write to enable the clock (see @enable_bit)
- * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
- * @flags: see "struct clk.flags possibilities" above
- * @clksel_reg: for clksel clks, register va containing src/divisor select
- * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
- * @clksel: for clksel clks, pointer to struct clksel for this clock
- * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
- * @clkdm_name: clockdomain name that this clock is contained in
- * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
- * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
- * @src_offset: bitshift for source selection bitfield (OMAP1 only)
- *
- * XXX @rate_offset, @src_offset should probably be removed and OMAP1
- * clock code converted to use clksel.
- *
- */
-
-struct clk_hw_omap_ops;
-
-struct clk_hw_omap {
-	struct clk_hw		hw;
-	struct list_head	node;
-	unsigned long		fixed_rate;
-	u8			fixed_div;
-	void __iomem		*enable_reg;
-	u8			enable_bit;
-	u8			flags;
-	void __iomem		*clksel_reg;
-	u32			clksel_mask;
-	const struct clksel	*clksel;
-	struct dpll_data	*dpll_data;
-	const char		*clkdm_name;
-	struct clockdomain	*clkdm;
-	const struct clk_hw_omap_ops	*ops;
-};
-
-struct clk_hw_omap_ops {
-	void			(*find_idlest)(struct clk_hw_omap *oclk,
-					void __iomem **idlest_reg,
-					u8 *idlest_bit, u8 *idlest_val);
-	void			(*find_companion)(struct clk_hw_omap *oclk,
-					void __iomem **other_reg,
-					u8 *other_bit);
-	void			(*allow_idle)(struct clk_hw_omap *oclk);
-	void			(*deny_idle)(struct clk_hw_omap *oclk);
-};
-
 unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
 					unsigned long parent_rate);
 
@@ -356,28 +230,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
 /* DPLL Type and DCO Selection Flags */
 #define DPLL_J_TYPE		0x1
 
-long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
-			unsigned long *parent_rate);
-unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
-int omap3_noncore_dpll_enable(struct clk_hw *hw);
-void omap3_noncore_dpll_disable(struct clk_hw *hw);
-int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
-				unsigned long parent_rate);
 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
 void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
 void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
-unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
-				    unsigned long parent_rate);
 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
-unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
-				unsigned long parent_rate);
-long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
-				    unsigned long target_rate,
-				    unsigned long *parent_rate);
 
-void omap2_init_clk_clkdm(struct clk_hw *clk);
 void __init omap2_clk_disable_clkdm_control(void);
 
 /* clkt_clksel.c public functions */
@@ -396,7 +255,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
 extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
 extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
 
-u8 omap2_init_dpll_parent(struct clk_hw *hw);
 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
 
 int omap2_dflt_clk_enable(struct clk_hw *hw);
@@ -408,9 +266,7 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 				void __iomem **idlest_reg,
 				u8 *idlest_bit, u8 *idlest_val);
-void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap2_clk_enable_autoidle_all(void);
-int omap2_clk_disable_autoidle_all(void);
 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
@@ -431,10 +287,8 @@ extern const struct clksel_rate gfx_l3_rates[];
 extern const struct clksel_rate dsp_ick_rates[];
 extern struct clk dummy_ck;
 
-extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
 extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 extern const struct clk_hw_omap_ops clkhwops_iclk;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
@@ -460,8 +314,5 @@ extern const struct clksel_rate div31_1to31_rates[];
 
 extern int am33xx_clk_init(void);
 
-extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
-extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
-
 extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
 #endif
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index 647f02f..cba892a 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -19,6 +19,161 @@
 #ifndef __LINUX_CLK_OMAP_H_
 #define __LINUX_CLK_OMAP_H_
 
-int __init dt_omap_clk_init(void);
+/**
+ * struct dpll_data - DPLL registers and integration data
+ * @mult_div1_reg: register containing the DPLL M and N bitfields
+ * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
+ * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
+ * @clk_bypass: struct clk pointer to the clock's bypass clock input
+ * @clk_ref: struct clk pointer to the clock's reference clock input
+ * @control_reg: register containing the DPLL mode bitfield
+ * @enable_mask: mask of the DPLL mode bitfield in @control_reg
+ * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
+ * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
+ * @last_rounded_m4xen: cache of the last M4X result of
+ *                     omap4_dpll_regm4xen_round_rate()
+ * @last_rounded_lpmode: cache of the last lpmode result of
+ *                      omap4_dpll_lpmode_recalc()
+ * @max_multiplier: maximum valid non-bypass multiplier value (actual)
+ * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
+ * @min_divider: minimum valid non-bypass divider value (actual)
+ * @max_divider: maximum valid non-bypass divider value (actual)
+ * @modes: possible values of @enable_mask
+ * @autoidle_reg: register containing the DPLL autoidle mode bitfield
+ * @idlest_reg: register containing the DPLL idle status bitfield
+ * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
+ * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
+ * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
+ * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
+ * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
+ * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
+ * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
+ * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
+ * @flags: DPLL type/features (see below)
+ *
+ * Possible values for @flags:
+ * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
+ *
+ * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
+ *
+ * XXX Some DPLLs have multiple bypass inputs, so it's not technically
+ * correct to only have one @clk_bypass pointer.
+ *
+ * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
+ * @last_rounded_n) should be separated from the runtime-fixed fields
+ * and placed into a different structure, so that the runtime-fixed data
+ * can be placed into read-only space.
+ */
+struct dpll_data {
+	void __iomem		*mult_div1_reg;
+	u32			mult_mask;
+	u32			div1_mask;
+	struct clk		*clk_bypass;
+	struct clk		*clk_ref;
+	void __iomem		*control_reg;
+	u32			enable_mask;
+	unsigned long		last_rounded_rate;
+	u16			last_rounded_m;
+	u8			last_rounded_m4xen;
+	u8			last_rounded_lpmode;
+	u16			max_multiplier;
+	u8			last_rounded_n;
+	u8			min_divider;
+	u16			max_divider;
+	u8			modes;
+	void __iomem		*autoidle_reg;
+	void __iomem		*idlest_reg;
+	u32			autoidle_mask;
+	u32			freqsel_mask;
+	u32			idlest_mask;
+	u32			dco_mask;
+	u32			sddiv_mask;
+	u32			lpmode_mask;
+	u32			m4xen_mask;
+	u8			auto_recal_bit;
+	u8			recal_en_bit;
+	u8			recal_st_bit;
+	u8			flags;
+};
+
+/**
+ * struct clk_hw_omap - OMAP struct clk
+ * @node: list_head connecting this clock into the full clock list
+ * @enable_reg: register to write to enable the clock (see @enable_bit)
+ * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
+ * @flags: see "struct clk.flags possibilities" above
+ * @clksel_reg: for clksel clks, register va containing src/divisor select
+ * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
+ * @clksel: for clksel clks, pointer to struct clksel for this clock
+ * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
+ * @clkdm_name: clockdomain name that this clock is contained in
+ * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name@runtime
+ * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
+ * @src_offset: bitshift for source selection bitfield (OMAP1 only)
+ *
+ * XXX @rate_offset, @src_offset should probably be removed and OMAP1
+ * clock code converted to use clksel.
+ *
+ */
+
+struct clk_hw_omap_ops;
+
+struct clk_hw_omap {
+	struct clk_hw		hw;
+	struct list_head	node;
+	unsigned long		fixed_rate;
+	u8			fixed_div;
+	void __iomem		*enable_reg;
+	u8			enable_bit;
+	u8			flags;
+	void __iomem		*clksel_reg;
+	u32			clksel_mask;
+	const struct clksel	*clksel;
+	struct dpll_data	*dpll_data;
+	const char		*clkdm_name;
+	struct clockdomain	*clkdm;
+	const struct clk_hw_omap_ops	*ops;
+};
+
+struct clk_hw_omap_ops {
+	void			(*find_idlest)(struct clk_hw_omap *oclk,
+					void __iomem **idlest_reg,
+					u8 *idlest_bit, u8 *idlest_val);
+	void			(*find_companion)(struct clk_hw_omap *oclk,
+					void __iomem **other_reg,
+					u8 *other_bit);
+	void			(*allow_idle)(struct clk_hw_omap *oclk);
+	void			(*deny_idle)(struct clk_hw_omap *oclk);
+};
+
+void omap2_init_clk_hw_omap_clocks(struct clk *clk);
+int omap3_noncore_dpll_enable(struct clk_hw *hw);
+void omap3_noncore_dpll_disable(struct clk_hw *hw);
+int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long parent_rate);
+unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
+				unsigned long parent_rate);
+long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
+				    unsigned long target_rate,
+				    unsigned long *parent_rate);
+u8 omap2_init_dpll_parent(struct clk_hw *hw);
+unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
+long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
+			unsigned long *parent_rate);
+void omap2_init_clk_clkdm(struct clk_hw *clk);
+unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
+				    unsigned long parent_rate);
+
+int omap2_clkops_enable_clkdm(struct clk_hw *hw);
+void omap2_clkops_disable_clkdm(struct clk_hw *hw);
+
+int omap2_clk_disable_autoidle_all(void);
+
+extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
+extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+
+/* DT functions */
+int dt_omap_clk_init(void);
+void of_omap4_dpll_setup(struct device_node *node);
 
 #endif
-- 
1.7.9.5

Re: [PATCHv4 04/33] CLK: omap: move part of the machine specific clock header contents to driver

[Nishanth Menon]

this patch should be 3/33 to allow dpll.c to build.

On 07/23/2013 02:19 AM, Tero Kristo wrote:
> Some of the clock.h contents are needed by the new OMAP clock driver,
> including dpll_data and clk_hw_omap. Thus, move these to the generic
> omap header file which can be accessed by the driver.
>
Looking at the change, I wonder what the rules are for the movement? 
commit message was not clear.

> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   arch/arm/mach-omap2/clock.h |  151 +----------------------------------------
>   include/linux/clk/omap.h    |  157 ++++++++++++++++++++++++++++++++++++++++++-
>   2 files changed, 157 insertions(+), 151 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
> index 7aa32cd..d1a3125 100644
> --- a/arch/arm/mach-omap2/clock.h
> +++ b/arch/arm/mach-omap2/clock.h
> @@ -21,6 +21,7 @@
>
>   #include <linux/clkdev.h>
>   #include <linux/clk-provider.h>
> +#include <linux/clk/omap.h>
>
>   struct omap_clk {
>   	u16				cpu;
> @@ -178,83 +179,6 @@ struct clksel {
>   	const struct clksel_rate *rates;
>   };
>
> -/**
> - * struct dpll_data - DPLL registers and integration data
> - * @mult_div1_reg: register containing the DPLL M and N bitfields
> - * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
> - * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
> - * @clk_bypass: struct clk pointer to the clock's bypass clock input
> - * @clk_ref: struct clk pointer to the clock's reference clock input
> - * @control_reg: register containing the DPLL mode bitfield
> - * @enable_mask: mask of the DPLL mode bitfield in @control_reg
> - * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
> - * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
> - * @last_rounded_m4xen: cache of the last M4X result of
> - *			omap4_dpll_regm4xen_round_rate()
> - * @last_rounded_lpmode: cache of the last lpmode result of
> - *			 omap4_dpll_lpmode_recalc()
> - * @max_multiplier: maximum valid non-bypass multiplier value (actual)
> - * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
> - * @min_divider: minimum valid non-bypass divider value (actual)
> - * @max_divider: maximum valid non-bypass divider value (actual)
> - * @modes: possible values of @enable_mask
> - * @autoidle_reg: register containing the DPLL autoidle mode bitfield
> - * @idlest_reg: register containing the DPLL idle status bitfield
> - * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
> - * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
> - * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
> - * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
> - * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
> - * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
> - * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
> - * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
> - * @flags: DPLL type/features (see below)
> - *
> - * Possible values for @flags:
> - * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
> - *
> - * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
> - *
> - * XXX Some DPLLs have multiple bypass inputs, so it's not technically
> - * correct to only have one @clk_bypass pointer.
> - *
> - * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
> - * @last_rounded_n) should be separated from the runtime-fixed fields
> - * and placed into a different structure, so that the runtime-fixed data
> - * can be placed into read-only space.
> - */
> -struct dpll_data {
> -	void __iomem		*mult_div1_reg;
> -	u32			mult_mask;
> -	u32			div1_mask;
> -	struct clk		*clk_bypass;
> -	struct clk		*clk_ref;
> -	void __iomem		*control_reg;
> -	u32			enable_mask;
> -	unsigned long		last_rounded_rate;
> -	u16			last_rounded_m;
> -	u8			last_rounded_m4xen;
> -	u8			last_rounded_lpmode;
> -	u16			max_multiplier;
> -	u8			last_rounded_n;
> -	u8			min_divider;
> -	u16			max_divider;
> -	u8			modes;
> -	void __iomem		*autoidle_reg;
> -	void __iomem		*idlest_reg;
> -	u32			autoidle_mask;
> -	u32			freqsel_mask;
> -	u32			idlest_mask;
> -	u32			dco_mask;
> -	u32			sddiv_mask;
> -	u32			lpmode_mask;
> -	u32			m4xen_mask;
> -	u8			auto_recal_bit;
> -	u8			recal_en_bit;
> -	u8			recal_st_bit;
> -	u8			flags;
> -};
> -
>   /*
>    * struct clk.flags possibilities
>    *
> @@ -274,56 +198,6 @@ struct dpll_data {
>   #define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
>   #define CLOCK_CLKOUTX2		(1 << 5)
>
> -/**
> - * struct clk_hw_omap - OMAP struct clk
> - * @node: list_head connecting this clock into the full clock list
> - * @enable_reg: register to write to enable the clock (see @enable_bit)
> - * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
> - * @flags: see "struct clk.flags possibilities" above
> - * @clksel_reg: for clksel clks, register va containing src/divisor select
> - * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
> - * @clksel: for clksel clks, pointer to struct clksel for this clock
> - * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
> - * @clkdm_name: clockdomain name that this clock is contained in
> - * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
> - * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
> - * @src_offset: bitshift for source selection bitfield (OMAP1 only)
> - *
> - * XXX @rate_offset, @src_offset should probably be removed and OMAP1
> - * clock code converted to use clksel.
> - *
> - */
> -
> -struct clk_hw_omap_ops;
> -
> -struct clk_hw_omap {
> -	struct clk_hw		hw;
> -	struct list_head	node;
> -	unsigned long		fixed_rate;
> -	u8			fixed_div;
> -	void __iomem		*enable_reg;
> -	u8			enable_bit;
> -	u8			flags;
> -	void __iomem		*clksel_reg;
> -	u32			clksel_mask;
> -	const struct clksel	*clksel;
> -	struct dpll_data	*dpll_data;
> -	const char		*clkdm_name;
> -	struct clockdomain	*clkdm;
> -	const struct clk_hw_omap_ops	*ops;
> -};
> -
> -struct clk_hw_omap_ops {
> -	void			(*find_idlest)(struct clk_hw_omap *oclk,
> -					void __iomem **idlest_reg,
> -					u8 *idlest_bit, u8 *idlest_val);
> -	void			(*find_companion)(struct clk_hw_omap *oclk,
> -					void __iomem **other_reg,
> -					u8 *other_bit);
> -	void			(*allow_idle)(struct clk_hw_omap *oclk);
> -	void			(*deny_idle)(struct clk_hw_omap *oclk);
> -};
> -
>   unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
>   					unsigned long parent_rate);
>
> @@ -356,28 +230,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
>   /* DPLL Type and DCO Selection Flags */
>   #define DPLL_J_TYPE		0x1
>
> -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
> -			unsigned long *parent_rate);
> -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
> -int omap3_noncore_dpll_enable(struct clk_hw *hw);
> -void omap3_noncore_dpll_disable(struct clk_hw *hw);
> -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
> -				unsigned long parent_rate);

Why are these being moved to generic?

>   u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
>   void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
>   void omap3_dpll_deny_idle(struct clk_hw_omap *clk);

> -unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
> -				    unsigned long parent_rate);
why move this?

>   int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
>   void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
>   void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
> -unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
> -				unsigned long parent_rate);
> -long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
> -				    unsigned long target_rate,
> -				    unsigned long *parent_rate);
same here.

>
> -void omap2_init_clk_clkdm(struct clk_hw *clk);
same question again.

>   void __init omap2_clk_disable_clkdm_control(void);
>
>   /* clkt_clksel.c public functions */
> @@ -396,7 +255,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
>   extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
>   extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
>
> -u8 omap2_init_dpll_parent(struct clk_hw *hw);
why move this?

>   unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
>
>   int omap2_dflt_clk_enable(struct clk_hw *hw);
> @@ -408,9 +266,7 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
>   void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
>   				void __iomem **idlest_reg,
>   				u8 *idlest_bit, u8 *idlest_val);
> -void omap2_init_clk_hw_omap_clocks(struct clk *clk);
why move this?

>   int omap2_clk_enable_autoidle_all(void);
> -int omap2_clk_disable_autoidle_all(void);
why move this?

>   void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
>   int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
>   void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
> @@ -431,10 +287,8 @@ extern const struct clksel_rate gfx_l3_rates[];
>   extern const struct clksel_rate dsp_ick_rates[];
>   extern struct clk dummy_ck;
>
> -extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
is this needed to be moved?

>   extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
>   extern const struct clk_hw_omap_ops clkhwops_wait;
> -extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
is this needed to be moved?

>   extern const struct clk_hw_omap_ops clkhwops_iclk;
>   extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
>   extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
> @@ -460,8 +314,5 @@ extern const struct clksel_rate div31_1to31_rates[];
>
>   extern int am33xx_clk_init(void);
>
> -extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
> -extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
> -


>   extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
>   #endif
> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
> index 647f02f..cba892a 100644
> --- a/include/linux/clk/omap.h
> +++ b/include/linux/clk/omap.h
> @@ -19,6 +19,161 @@
>   #ifndef __LINUX_CLK_OMAP_H_
>   #define __LINUX_CLK_OMAP_H_
>
> -int __init dt_omap_clk_init(void);
> +/**
> + * struct dpll_data - DPLL registers and integration data
> + * @mult_div1_reg: register containing the DPLL M and N bitfields
> + * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
> + * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
> + * @clk_bypass: struct clk pointer to the clock's bypass clock input
> + * @clk_ref: struct clk pointer to the clock's reference clock input
> + * @control_reg: register containing the DPLL mode bitfield
> + * @enable_mask: mask of the DPLL mode bitfield in @control_reg
> + * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
> + * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
> + * @last_rounded_m4xen: cache of the last M4X result of
> + *                     omap4_dpll_regm4xen_round_rate()
> + * @last_rounded_lpmode: cache of the last lpmode result of
> + *                      omap4_dpll_lpmode_recalc()
> + * @max_multiplier: maximum valid non-bypass multiplier value (actual)
> + * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
> + * @min_divider: minimum valid non-bypass divider value (actual)
> + * @max_divider: maximum valid non-bypass divider value (actual)
> + * @modes: possible values of @enable_mask
> + * @autoidle_reg: register containing the DPLL autoidle mode bitfield
> + * @idlest_reg: register containing the DPLL idle status bitfield
> + * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
> + * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
> + * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
> + * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
> + * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
> + * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
> + * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
> + * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
> + * @flags: DPLL type/features (see below)
> + *
> + * Possible values for @flags:
> + * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
but the flag is in arch/arm/mach-omap2/clock.h ?

> + *
> + * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
> + *
> + * XXX Some DPLLs have multiple bypass inputs, so it's not technically
> + * correct to only have one @clk_bypass pointer.
> + *
> + * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
> + * @last_rounded_n) should be separated from the runtime-fixed fields
> + * and placed into a different structure, so that the runtime-fixed data
> + * can be placed into read-only space.
> + */
> +struct dpll_data {

is it necessary to export this? usage is limited to dpll.c and could be 
made private to it alone, no?

> +	void __iomem		*mult_div1_reg;
> +	u32			mult_mask;
> +	u32			div1_mask;
> +	struct clk		*clk_bypass;
> +	struct clk		*clk_ref;
> +	void __iomem		*control_reg;
> +	u32			enable_mask;
> +	unsigned long		last_rounded_rate;
> +	u16			last_rounded_m;
> +	u8			last_rounded_m4xen;
> +	u8			last_rounded_lpmode;
> +	u16			max_multiplier;
> +	u8			last_rounded_n;
> +	u8			min_divider;
> +	u16			max_divider;
> +	u8			modes;
> +	void __iomem		*autoidle_reg;
> +	void __iomem		*idlest_reg;
> +	u32			autoidle_mask;
> +	u32			freqsel_mask;
> +	u32			idlest_mask;
> +	u32			dco_mask;

not part of kernel documentation above.

> +	u32			sddiv_mask;

not part of kernel documentation above.


> +	u32			lpmode_mask;
> +	u32			m4xen_mask;
> +	u8			auto_recal_bit;
> +	u8			recal_en_bit;
> +	u8			recal_st_bit;
> +	u8			flags;
> +};
> +
> +/**
> + * struct clk_hw_omap - OMAP struct clk
> + * @node: list_head connecting this clock into the full clock list
> + * @enable_reg: register to write to enable the clock (see @enable_bit)
> + * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
> + * @flags: see "struct clk.flags possibilities" above
> + * @clksel_reg: for clksel clks, register va containing src/divisor select
> + * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
> + * @clksel: for clksel clks, pointer to struct clksel for this clock
> + * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
> + * @clkdm_name: clockdomain name that this clock is contained in
> + * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
> + * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
> + * @src_offset: bitshift for source selection bitfield (OMAP1 only)
> + *
> + * XXX @rate_offset, @src_offset should probably be removed and OMAP1
> + * clock code converted to use clksel.
Do you need to carry these forward? they already disappeared from the 
struct below.

> + *
> + */
> +
> +struct clk_hw_omap_ops;
you need to keep the kernel documentation next to the struct which it is 
documenting, by introducing clk_hw_omap_ops forward declaration, we 
introduced the following kernel-doc error:

Error(include/linux/clk/omap.h:119): Cannot parse struct or union!

> +
> +struct clk_hw_omap {
> +	struct clk_hw		hw;
not documented.

> +	struct list_head	node;
> +	unsigned long		fixed_rate;
not documented.

> +	u8			fixed_div;
not documented.

> +	void __iomem		*enable_reg;
> +	u8			enable_bit;
> +	u8			flags;
> +	void __iomem		*clksel_reg;
> +	u32			clksel_mask;
> +	const struct clksel	*clksel;
> +	struct dpll_data	*dpll_data;
> +	const char		*clkdm_name;
> +	struct clockdomain	*clkdm;
> +	const struct clk_hw_omap_ops	*ops;
> +};
> +
> +struct clk_hw_omap_ops {
> +	void			(*find_idlest)(struct clk_hw_omap *oclk,
> +					void __iomem **idlest_reg,
> +					u8 *idlest_bit, u8 *idlest_val);
> +	void			(*find_companion)(struct clk_hw_omap *oclk,
> +					void __iomem **other_reg,
> +					u8 *other_bit);
> +	void			(*allow_idle)(struct clk_hw_omap *oclk);
> +	void			(*deny_idle)(struct clk_hw_omap *oclk);
> +};

will be nice to have kernel documentation for these.

> +
> +void omap2_init_clk_hw_omap_clocks(struct clk *clk);
> +int omap3_noncore_dpll_enable(struct clk_hw *hw);
> +void omap3_noncore_dpll_disable(struct clk_hw *hw);
> +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
> +				unsigned long parent_rate);
> +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
> +				unsigned long parent_rate);
> +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
> +				    unsigned long target_rate,
> +				    unsigned long *parent_rate);
> +u8 omap2_init_dpll_parent(struct clk_hw *hw);
> +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
> +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
> +			unsigned long *parent_rate);
> +void omap2_init_clk_clkdm(struct clk_hw *clk);
> +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
> +				    unsigned long parent_rate);
> +
> +int omap2_clkops_enable_clkdm(struct clk_hw *hw);
> +void omap2_clkops_disable_clkdm(struct clk_hw *hw);
> +
> +int omap2_clk_disable_autoidle_all(void);
^^ all the above, not clear why we are moving them out enmasse.

> +
> +extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
> +extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
why do we need to export these out?

> +
> +/* DT functions */
> +int dt_omap_clk_init(void);
in this change, we removed __init -> which should have been done in the 
patch that introduced it in the first place.

> +void of_omap4_dpll_setup(struct device_node *node);
we should not be needing this.

>
>   #endif
>

at this point, we have a dependency between drivers/clk/omap/dpll.c and 
arch/arm/mach-omap2/ -> a possible suggestion will be to move required 
data structures first and operations as required.

-- 
Regards,
Nishanth Menon

[PATCHv4 04/33] CLK: omap: move part of the machine specific clock header contents to driver

[Nishanth Menon]

this patch should be 3/33 to allow dpll.c to build.

On 07/23/2013 02:19 AM, Tero Kristo wrote:
> Some of the clock.h contents are needed by the new OMAP clock driver,
> including dpll_data and clk_hw_omap. Thus, move these to the generic
> omap header file which can be accessed by the driver.
>
Looking at the change, I wonder what the rules are for the movement? 
commit message was not clear.

> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   arch/arm/mach-omap2/clock.h |  151 +----------------------------------------
>   include/linux/clk/omap.h    |  157 ++++++++++++++++++++++++++++++++++++++++++-
>   2 files changed, 157 insertions(+), 151 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
> index 7aa32cd..d1a3125 100644
> --- a/arch/arm/mach-omap2/clock.h
> +++ b/arch/arm/mach-omap2/clock.h
> @@ -21,6 +21,7 @@
>
>   #include <linux/clkdev.h>
>   #include <linux/clk-provider.h>
> +#include <linux/clk/omap.h>
>
>   struct omap_clk {
>   	u16				cpu;
> @@ -178,83 +179,6 @@ struct clksel {
>   	const struct clksel_rate *rates;
>   };
>
> -/**
> - * struct dpll_data - DPLL registers and integration data
> - * @mult_div1_reg: register containing the DPLL M and N bitfields
> - * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
> - * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
> - * @clk_bypass: struct clk pointer to the clock's bypass clock input
> - * @clk_ref: struct clk pointer to the clock's reference clock input
> - * @control_reg: register containing the DPLL mode bitfield
> - * @enable_mask: mask of the DPLL mode bitfield in @control_reg
> - * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
> - * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
> - * @last_rounded_m4xen: cache of the last M4X result of
> - *			omap4_dpll_regm4xen_round_rate()
> - * @last_rounded_lpmode: cache of the last lpmode result of
> - *			 omap4_dpll_lpmode_recalc()
> - * @max_multiplier: maximum valid non-bypass multiplier value (actual)
> - * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
> - * @min_divider: minimum valid non-bypass divider value (actual)
> - * @max_divider: maximum valid non-bypass divider value (actual)
> - * @modes: possible values of @enable_mask
> - * @autoidle_reg: register containing the DPLL autoidle mode bitfield
> - * @idlest_reg: register containing the DPLL idle status bitfield
> - * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
> - * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
> - * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
> - * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
> - * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
> - * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
> - * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
> - * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
> - * @flags: DPLL type/features (see below)
> - *
> - * Possible values for @flags:
> - * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
> - *
> - * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
> - *
> - * XXX Some DPLLs have multiple bypass inputs, so it's not technically
> - * correct to only have one @clk_bypass pointer.
> - *
> - * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
> - * @last_rounded_n) should be separated from the runtime-fixed fields
> - * and placed into a different structure, so that the runtime-fixed data
> - * can be placed into read-only space.
> - */
> -struct dpll_data {
> -	void __iomem		*mult_div1_reg;
> -	u32			mult_mask;
> -	u32			div1_mask;
> -	struct clk		*clk_bypass;
> -	struct clk		*clk_ref;
> -	void __iomem		*control_reg;
> -	u32			enable_mask;
> -	unsigned long		last_rounded_rate;
> -	u16			last_rounded_m;
> -	u8			last_rounded_m4xen;
> -	u8			last_rounded_lpmode;
> -	u16			max_multiplier;
> -	u8			last_rounded_n;
> -	u8			min_divider;
> -	u16			max_divider;
> -	u8			modes;
> -	void __iomem		*autoidle_reg;
> -	void __iomem		*idlest_reg;
> -	u32			autoidle_mask;
> -	u32			freqsel_mask;
> -	u32			idlest_mask;
> -	u32			dco_mask;
> -	u32			sddiv_mask;
> -	u32			lpmode_mask;
> -	u32			m4xen_mask;
> -	u8			auto_recal_bit;
> -	u8			recal_en_bit;
> -	u8			recal_st_bit;
> -	u8			flags;
> -};
> -
>   /*
>    * struct clk.flags possibilities
>    *
> @@ -274,56 +198,6 @@ struct dpll_data {
>   #define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
>   #define CLOCK_CLKOUTX2		(1 << 5)
>
> -/**
> - * struct clk_hw_omap - OMAP struct clk
> - * @node: list_head connecting this clock into the full clock list
> - * @enable_reg: register to write to enable the clock (see @enable_bit)
> - * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
> - * @flags: see "struct clk.flags possibilities" above
> - * @clksel_reg: for clksel clks, register va containing src/divisor select
> - * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
> - * @clksel: for clksel clks, pointer to struct clksel for this clock
> - * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
> - * @clkdm_name: clockdomain name that this clock is contained in
> - * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
> - * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
> - * @src_offset: bitshift for source selection bitfield (OMAP1 only)
> - *
> - * XXX @rate_offset, @src_offset should probably be removed and OMAP1
> - * clock code converted to use clksel.
> - *
> - */
> -
> -struct clk_hw_omap_ops;
> -
> -struct clk_hw_omap {
> -	struct clk_hw		hw;
> -	struct list_head	node;
> -	unsigned long		fixed_rate;
> -	u8			fixed_div;
> -	void __iomem		*enable_reg;
> -	u8			enable_bit;
> -	u8			flags;
> -	void __iomem		*clksel_reg;
> -	u32			clksel_mask;
> -	const struct clksel	*clksel;
> -	struct dpll_data	*dpll_data;
> -	const char		*clkdm_name;
> -	struct clockdomain	*clkdm;
> -	const struct clk_hw_omap_ops	*ops;
> -};
> -
> -struct clk_hw_omap_ops {
> -	void			(*find_idlest)(struct clk_hw_omap *oclk,
> -					void __iomem **idlest_reg,
> -					u8 *idlest_bit, u8 *idlest_val);
> -	void			(*find_companion)(struct clk_hw_omap *oclk,
> -					void __iomem **other_reg,
> -					u8 *other_bit);
> -	void			(*allow_idle)(struct clk_hw_omap *oclk);
> -	void			(*deny_idle)(struct clk_hw_omap *oclk);
> -};
> -
>   unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
>   					unsigned long parent_rate);
>
> @@ -356,28 +230,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
>   /* DPLL Type and DCO Selection Flags */
>   #define DPLL_J_TYPE		0x1
>
> -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
> -			unsigned long *parent_rate);
> -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
> -int omap3_noncore_dpll_enable(struct clk_hw *hw);
> -void omap3_noncore_dpll_disable(struct clk_hw *hw);
> -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
> -				unsigned long parent_rate);

Why are these being moved to generic?

>   u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
>   void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
>   void omap3_dpll_deny_idle(struct clk_hw_omap *clk);

> -unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
> -				    unsigned long parent_rate);
why move this?

>   int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
>   void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
>   void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
> -unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
> -				unsigned long parent_rate);
> -long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
> -				    unsigned long target_rate,
> -				    unsigned long *parent_rate);
same here.

>
> -void omap2_init_clk_clkdm(struct clk_hw *clk);
same question again.

>   void __init omap2_clk_disable_clkdm_control(void);
>
>   /* clkt_clksel.c public functions */
> @@ -396,7 +255,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
>   extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
>   extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
>
> -u8 omap2_init_dpll_parent(struct clk_hw *hw);
why move this?

>   unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
>
>   int omap2_dflt_clk_enable(struct clk_hw *hw);
> @@ -408,9 +266,7 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
>   void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
>   				void __iomem **idlest_reg,
>   				u8 *idlest_bit, u8 *idlest_val);
> -void omap2_init_clk_hw_omap_clocks(struct clk *clk);
why move this?

>   int omap2_clk_enable_autoidle_all(void);
> -int omap2_clk_disable_autoidle_all(void);
why move this?

>   void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
>   int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
>   void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
> @@ -431,10 +287,8 @@ extern const struct clksel_rate gfx_l3_rates[];
>   extern const struct clksel_rate dsp_ick_rates[];
>   extern struct clk dummy_ck;
>
> -extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
is this needed to be moved?

>   extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
>   extern const struct clk_hw_omap_ops clkhwops_wait;
> -extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
is this needed to be moved?

>   extern const struct clk_hw_omap_ops clkhwops_iclk;
>   extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
>   extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
> @@ -460,8 +314,5 @@ extern const struct clksel_rate div31_1to31_rates[];
>
>   extern int am33xx_clk_init(void);
>
> -extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
> -extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
> -


>   extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
>   #endif
> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
> index 647f02f..cba892a 100644
> --- a/include/linux/clk/omap.h
> +++ b/include/linux/clk/omap.h
> @@ -19,6 +19,161 @@
>   #ifndef __LINUX_CLK_OMAP_H_
>   #define __LINUX_CLK_OMAP_H_
>
> -int __init dt_omap_clk_init(void);
> +/**
> + * struct dpll_data - DPLL registers and integration data
> + * @mult_div1_reg: register containing the DPLL M and N bitfields
> + * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
> + * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
> + * @clk_bypass: struct clk pointer to the clock's bypass clock input
> + * @clk_ref: struct clk pointer to the clock's reference clock input
> + * @control_reg: register containing the DPLL mode bitfield
> + * @enable_mask: mask of the DPLL mode bitfield in @control_reg
> + * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
> + * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
> + * @last_rounded_m4xen: cache of the last M4X result of
> + *                     omap4_dpll_regm4xen_round_rate()
> + * @last_rounded_lpmode: cache of the last lpmode result of
> + *                      omap4_dpll_lpmode_recalc()
> + * @max_multiplier: maximum valid non-bypass multiplier value (actual)
> + * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
> + * @min_divider: minimum valid non-bypass divider value (actual)
> + * @max_divider: maximum valid non-bypass divider value (actual)
> + * @modes: possible values of @enable_mask
> + * @autoidle_reg: register containing the DPLL autoidle mode bitfield
> + * @idlest_reg: register containing the DPLL idle status bitfield
> + * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
> + * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
> + * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
> + * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
> + * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
> + * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
> + * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
> + * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
> + * @flags: DPLL type/features (see below)
> + *
> + * Possible values for @flags:
> + * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
but the flag is in arch/arm/mach-omap2/clock.h ?

> + *
> + * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
> + *
> + * XXX Some DPLLs have multiple bypass inputs, so it's not technically
> + * correct to only have one @clk_bypass pointer.
> + *
> + * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
> + * @last_rounded_n) should be separated from the runtime-fixed fields
> + * and placed into a different structure, so that the runtime-fixed data
> + * can be placed into read-only space.
> + */
> +struct dpll_data {

is it necessary to export this? usage is limited to dpll.c and could be 
made private to it alone, no?

> +	void __iomem		*mult_div1_reg;
> +	u32			mult_mask;
> +	u32			div1_mask;
> +	struct clk		*clk_bypass;
> +	struct clk		*clk_ref;
> +	void __iomem		*control_reg;
> +	u32			enable_mask;
> +	unsigned long		last_rounded_rate;
> +	u16			last_rounded_m;
> +	u8			last_rounded_m4xen;
> +	u8			last_rounded_lpmode;
> +	u16			max_multiplier;
> +	u8			last_rounded_n;
> +	u8			min_divider;
> +	u16			max_divider;
> +	u8			modes;
> +	void __iomem		*autoidle_reg;
> +	void __iomem		*idlest_reg;
> +	u32			autoidle_mask;
> +	u32			freqsel_mask;
> +	u32			idlest_mask;
> +	u32			dco_mask;

not part of kernel documentation above.

> +	u32			sddiv_mask;

not part of kernel documentation above.


> +	u32			lpmode_mask;
> +	u32			m4xen_mask;
> +	u8			auto_recal_bit;
> +	u8			recal_en_bit;
> +	u8			recal_st_bit;
> +	u8			flags;
> +};
> +
> +/**
> + * struct clk_hw_omap - OMAP struct clk
> + * @node: list_head connecting this clock into the full clock list
> + * @enable_reg: register to write to enable the clock (see @enable_bit)
> + * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
> + * @flags: see "struct clk.flags possibilities" above
> + * @clksel_reg: for clksel clks, register va containing src/divisor select
> + * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
> + * @clksel: for clksel clks, pointer to struct clksel for this clock
> + * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
> + * @clkdm_name: clockdomain name that this clock is contained in
> + * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
> + * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
> + * @src_offset: bitshift for source selection bitfield (OMAP1 only)
> + *
> + * XXX @rate_offset, @src_offset should probably be removed and OMAP1
> + * clock code converted to use clksel.
Do you need to carry these forward? they already disappeared from the 
struct below.

> + *
> + */
> +
> +struct clk_hw_omap_ops;
you need to keep the kernel documentation next to the struct which it is 
documenting, by introducing clk_hw_omap_ops forward declaration, we 
introduced the following kernel-doc error:

Error(include/linux/clk/omap.h:119): Cannot parse struct or union!

> +
> +struct clk_hw_omap {
> +	struct clk_hw		hw;
not documented.

> +	struct list_head	node;
> +	unsigned long		fixed_rate;
not documented.

> +	u8			fixed_div;
not documented.

> +	void __iomem		*enable_reg;
> +	u8			enable_bit;
> +	u8			flags;
> +	void __iomem		*clksel_reg;
> +	u32			clksel_mask;
> +	const struct clksel	*clksel;
> +	struct dpll_data	*dpll_data;
> +	const char		*clkdm_name;
> +	struct clockdomain	*clkdm;
> +	const struct clk_hw_omap_ops	*ops;
> +};
> +
> +struct clk_hw_omap_ops {
> +	void			(*find_idlest)(struct clk_hw_omap *oclk,
> +					void __iomem **idlest_reg,
> +					u8 *idlest_bit, u8 *idlest_val);
> +	void			(*find_companion)(struct clk_hw_omap *oclk,
> +					void __iomem **other_reg,
> +					u8 *other_bit);
> +	void			(*allow_idle)(struct clk_hw_omap *oclk);
> +	void			(*deny_idle)(struct clk_hw_omap *oclk);
> +};

will be nice to have kernel documentation for these.

> +
> +void omap2_init_clk_hw_omap_clocks(struct clk *clk);
> +int omap3_noncore_dpll_enable(struct clk_hw *hw);
> +void omap3_noncore_dpll_disable(struct clk_hw *hw);
> +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
> +				unsigned long parent_rate);
> +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
> +				unsigned long parent_rate);
> +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
> +				    unsigned long target_rate,
> +				    unsigned long *parent_rate);
> +u8 omap2_init_dpll_parent(struct clk_hw *hw);
> +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
> +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
> +			unsigned long *parent_rate);
> +void omap2_init_clk_clkdm(struct clk_hw *clk);
> +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
> +				    unsigned long parent_rate);
> +
> +int omap2_clkops_enable_clkdm(struct clk_hw *hw);
> +void omap2_clkops_disable_clkdm(struct clk_hw *hw);
> +
> +int omap2_clk_disable_autoidle_all(void);
^^ all the above, not clear why we are moving them out enmasse.

> +
> +extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
> +extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
why do we need to export these out?

> +
> +/* DT functions */
> +int dt_omap_clk_init(void);
in this change, we removed __init -> which should have been done in the 
patch that introduced it in the first place.

> +void of_omap4_dpll_setup(struct device_node *node);
we should not be needing this.

>
>   #endif
>

at this point, we have a dependency between drivers/clk/omap/dpll.c and 
arch/arm/mach-omap2/ -> a possible suggestion will be to move required 
data structures first and operations as required.

-- 
Regards,
Nishanth Menon

Re: [PATCHv4 04/33] CLK: omap: move part of the machine specific clock header contents to driver

[Tero Kristo]

On 07/30/2013 09:22 PM, Nishanth Menon wrote:
> this patch should be 3/33 to allow dpll.c to build.
>
> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>> Some of the clock.h contents are needed by the new OMAP clock driver,
>> including dpll_data and clk_hw_omap. Thus, move these to the generic
>> omap header file which can be accessed by the driver.
>>
> Looking at the change, I wonder what the rules are for the movement?
> commit message was not clear.

This is kind of a merge of almost everything that is needed by clock 
drivers at some point. I can move the changes along to the patches that 
actually need the exports for clarity and to keep compilation clean.

>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   arch/arm/mach-omap2/clock.h |  151
>> +----------------------------------------
>>   include/linux/clk/omap.h    |  157
>> ++++++++++++++++++++++++++++++++++++++++++-
>>   2 files changed, 157 insertions(+), 151 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
>> index 7aa32cd..d1a3125 100644
>> --- a/arch/arm/mach-omap2/clock.h
>> +++ b/arch/arm/mach-omap2/clock.h
>> @@ -21,6 +21,7 @@
>>
>>   #include <linux/clkdev.h>
>>   #include <linux/clk-provider.h>
>> +#include <linux/clk/omap.h>
>>
>>   struct omap_clk {
>>       u16                cpu;
>> @@ -178,83 +179,6 @@ struct clksel {
>>       const struct clksel_rate *rates;
>>   };
>>
>> -/**
>> - * struct dpll_data - DPLL registers and integration data
>> - * @mult_div1_reg: register containing the DPLL M and N bitfields
>> - * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
>> - * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
>> - * @clk_bypass: struct clk pointer to the clock's bypass clock input
>> - * @clk_ref: struct clk pointer to the clock's reference clock input
>> - * @control_reg: register containing the DPLL mode bitfield
>> - * @enable_mask: mask of the DPLL mode bitfield in @control_reg
>> - * @last_rounded_rate: cache of the last rate result of
>> omap2_dpll_round_rate()
>> - * @last_rounded_m: cache of the last M result of
>> omap2_dpll_round_rate()
>> - * @last_rounded_m4xen: cache of the last M4X result of
>> - *            omap4_dpll_regm4xen_round_rate()
>> - * @last_rounded_lpmode: cache of the last lpmode result of
>> - *             omap4_dpll_lpmode_recalc()
>> - * @max_multiplier: maximum valid non-bypass multiplier value (actual)
>> - * @last_rounded_n: cache of the last N result of
>> omap2_dpll_round_rate()
>> - * @min_divider: minimum valid non-bypass divider value (actual)
>> - * @max_divider: maximum valid non-bypass divider value (actual)
>> - * @modes: possible values of @enable_mask
>> - * @autoidle_reg: register containing the DPLL autoidle mode bitfield
>> - * @idlest_reg: register containing the DPLL idle status bitfield
>> - * @autoidle_mask: mask of the DPLL autoidle mode bitfield in
>> @autoidle_reg
>> - * @freqsel_mask: mask of the DPLL jitter correction bitfield in
>> @control_reg
>> - * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
>> - * @lpmode_mask: mask of the DPLL low-power mode bitfield in
>> @control_reg
>> - * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
>> - * @auto_recal_bit: bitshift of the driftguard enable bit in
>> @control_reg
>> - * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for
>> recalibration IRQs
>> - * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for
>> recalibration IRQs
>> - * @flags: DPLL type/features (see below)
>> - *
>> - * Possible values for @flags:
>> - * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
>> - *
>> - * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
>> - *
>> - * XXX Some DPLLs have multiple bypass inputs, so it's not technically
>> - * correct to only have one @clk_bypass pointer.
>> - *
>> - * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
>> - * @last_rounded_n) should be separated from the runtime-fixed fields
>> - * and placed into a different structure, so that the runtime-fixed data
>> - * can be placed into read-only space.
>> - */
>> -struct dpll_data {
>> -    void __iomem        *mult_div1_reg;
>> -    u32            mult_mask;
>> -    u32            div1_mask;
>> -    struct clk        *clk_bypass;
>> -    struct clk        *clk_ref;
>> -    void __iomem        *control_reg;
>> -    u32            enable_mask;
>> -    unsigned long        last_rounded_rate;
>> -    u16            last_rounded_m;
>> -    u8            last_rounded_m4xen;
>> -    u8            last_rounded_lpmode;
>> -    u16            max_multiplier;
>> -    u8            last_rounded_n;
>> -    u8            min_divider;
>> -    u16            max_divider;
>> -    u8            modes;
>> -    void __iomem        *autoidle_reg;
>> -    void __iomem        *idlest_reg;
>> -    u32            autoidle_mask;
>> -    u32            freqsel_mask;
>> -    u32            idlest_mask;
>> -    u32            dco_mask;
>> -    u32            sddiv_mask;
>> -    u32            lpmode_mask;
>> -    u32            m4xen_mask;
>> -    u8            auto_recal_bit;
>> -    u8            recal_en_bit;
>> -    u8            recal_st_bit;
>> -    u8            flags;
>> -};
>> -
>>   /*
>>    * struct clk.flags possibilities
>>    *
>> @@ -274,56 +198,6 @@ struct dpll_data {
>>   #define INVERT_ENABLE        (1 << 4)    /* 0 enables, 1 disables */
>>   #define CLOCK_CLKOUTX2        (1 << 5)
>>
>> -/**
>> - * struct clk_hw_omap - OMAP struct clk
>> - * @node: list_head connecting this clock into the full clock list
>> - * @enable_reg: register to write to enable the clock (see @enable_bit)
>> - * @enable_bit: bitshift to write to enable/disable the clock (see
>> @enable_reg)
>> - * @flags: see "struct clk.flags possibilities" above
>> - * @clksel_reg: for clksel clks, register va containing src/divisor
>> select
>> - * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
>> - * @clksel: for clksel clks, pointer to struct clksel for this clock
>> - * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
>> - * @clkdm_name: clockdomain name that this clock is contained in
>> - * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name
>> at runtime
>> - * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
>> - * @src_offset: bitshift for source selection bitfield (OMAP1 only)
>> - *
>> - * XXX @rate_offset, @src_offset should probably be removed and OMAP1
>> - * clock code converted to use clksel.
>> - *
>> - */
>> -
>> -struct clk_hw_omap_ops;
>> -
>> -struct clk_hw_omap {
>> -    struct clk_hw        hw;
>> -    struct list_head    node;
>> -    unsigned long        fixed_rate;
>> -    u8            fixed_div;
>> -    void __iomem        *enable_reg;
>> -    u8            enable_bit;
>> -    u8            flags;
>> -    void __iomem        *clksel_reg;
>> -    u32            clksel_mask;
>> -    const struct clksel    *clksel;
>> -    struct dpll_data    *dpll_data;
>> -    const char        *clkdm_name;
>> -    struct clockdomain    *clkdm;
>> -    const struct clk_hw_omap_ops    *ops;
>> -};
>> -
>> -struct clk_hw_omap_ops {
>> -    void            (*find_idlest)(struct clk_hw_omap *oclk,
>> -                    void __iomem **idlest_reg,
>> -                    u8 *idlest_bit, u8 *idlest_val);
>> -    void            (*find_companion)(struct clk_hw_omap *oclk,
>> -                    void __iomem **other_reg,
>> -                    u8 *other_bit);
>> -    void            (*allow_idle)(struct clk_hw_omap *oclk);
>> -    void            (*deny_idle)(struct clk_hw_omap *oclk);
>> -};
>> -
>>   unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
>>                       unsigned long parent_rate);
>>
>> @@ -356,28 +230,13 @@ unsigned long omap_fixed_divisor_recalc(struct
>> clk_hw *hw,
>>   /* DPLL Type and DCO Selection Flags */
>>   #define DPLL_J_TYPE        0x1
>>
>> -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
>> -            unsigned long *parent_rate);
>> -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long
>> parent_rate);
>> -int omap3_noncore_dpll_enable(struct clk_hw *hw);
>> -void omap3_noncore_dpll_disable(struct clk_hw *hw);
>> -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
>> -                unsigned long parent_rate);
>
> Why are these being moved to generic?

These are used from the dpll.c by the ops.

>
>>   u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
>>   void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
>>   void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
>
>> -unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
>> -                    unsigned long parent_rate);
> why move this?

Same, anyway, I'll cover the rest of similar comments by moving them 
along with the patch that actually needs the export.


>
>>   int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
>>   void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
>>   void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
>> -unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
>> -                unsigned long parent_rate);
>> -long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
>> -                    unsigned long target_rate,
>> -                    unsigned long *parent_rate);
> same here.
>
>>
>> -void omap2_init_clk_clkdm(struct clk_hw *clk);
> same question again.
>
>>   void __init omap2_clk_disable_clkdm_control(void);
>>
>>   /* clkt_clksel.c public functions */
>> @@ -396,7 +255,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8
>> field_val);
>>   extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
>>   extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
>>
>> -u8 omap2_init_dpll_parent(struct clk_hw *hw);
> why move this?
>
>>   unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
>>
>>   int omap2_dflt_clk_enable(struct clk_hw *hw);
>> @@ -408,9 +266,7 @@ void omap2_clk_dflt_find_companion(struct
>> clk_hw_omap *clk,
>>   void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
>>                   void __iomem **idlest_reg,
>>                   u8 *idlest_bit, u8 *idlest_val);
>> -void omap2_init_clk_hw_omap_clocks(struct clk *clk);
> why move this?
>
>>   int omap2_clk_enable_autoidle_all(void);
>> -int omap2_clk_disable_autoidle_all(void);
> why move this?
>
>>   void omap2_clk_enable_init_clocks(const char **clk_names, u8
>> num_clocks);
>>   int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
>>   void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
>> @@ -431,10 +287,8 @@ extern const struct clksel_rate gfx_l3_rates[];
>>   extern const struct clksel_rate dsp_ick_rates[];
>>   extern struct clk dummy_ck;
>>
>> -extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
> is this needed to be moved?
>
>>   extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
>>   extern const struct clk_hw_omap_ops clkhwops_wait;
>> -extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
> is this needed to be moved?
>
>>   extern const struct clk_hw_omap_ops clkhwops_iclk;
>>   extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
>>   extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
>> @@ -460,8 +314,5 @@ extern const struct clksel_rate div31_1to31_rates[];
>>
>>   extern int am33xx_clk_init(void);
>>
>> -extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
>> -extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
>> -
>
>
>>   extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
>>   #endif
>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>> index 647f02f..cba892a 100644
>> --- a/include/linux/clk/omap.h
>> +++ b/include/linux/clk/omap.h
>> @@ -19,6 +19,161 @@
>>   #ifndef __LINUX_CLK_OMAP_H_
>>   #define __LINUX_CLK_OMAP_H_
>>
>> -int __init dt_omap_clk_init(void);
>> +/**
>> + * struct dpll_data - DPLL registers and integration data
>> + * @mult_div1_reg: register containing the DPLL M and N bitfields
>> + * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
>> + * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
>> + * @clk_bypass: struct clk pointer to the clock's bypass clock input
>> + * @clk_ref: struct clk pointer to the clock's reference clock input
>> + * @control_reg: register containing the DPLL mode bitfield
>> + * @enable_mask: mask of the DPLL mode bitfield in @control_reg
>> + * @last_rounded_rate: cache of the last rate result of
>> omap2_dpll_round_rate()
>> + * @last_rounded_m: cache of the last M result of
>> omap2_dpll_round_rate()
>> + * @last_rounded_m4xen: cache of the last M4X result of
>> + *                     omap4_dpll_regm4xen_round_rate()
>> + * @last_rounded_lpmode: cache of the last lpmode result of
>> + *                      omap4_dpll_lpmode_recalc()
>> + * @max_multiplier: maximum valid non-bypass multiplier value (actual)
>> + * @last_rounded_n: cache of the last N result of
>> omap2_dpll_round_rate()
>> + * @min_divider: minimum valid non-bypass divider value (actual)
>> + * @max_divider: maximum valid non-bypass divider value (actual)
>> + * @modes: possible values of @enable_mask
>> + * @autoidle_reg: register containing the DPLL autoidle mode bitfield
>> + * @idlest_reg: register containing the DPLL idle status bitfield
>> + * @autoidle_mask: mask of the DPLL autoidle mode bitfield in
>> @autoidle_reg
>> + * @freqsel_mask: mask of the DPLL jitter correction bitfield in
>> @control_reg
>> + * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
>> + * @lpmode_mask: mask of the DPLL low-power mode bitfield in
>> @control_reg
>> + * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
>> + * @auto_recal_bit: bitshift of the driftguard enable bit in
>> @control_reg
>> + * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for
>> recalibration IRQs
>> + * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for
>> recalibration IRQs
>> + * @flags: DPLL type/features (see below)
>> + *
>> + * Possible values for @flags:
>> + * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
> but the flag is in arch/arm/mach-omap2/clock.h ?

I'll look at this and probably move the flag also.

>
>> + *
>> + * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
>> + *
>> + * XXX Some DPLLs have multiple bypass inputs, so it's not technically
>> + * correct to only have one @clk_bypass pointer.
>> + *
>> + * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
>> + * @last_rounded_n) should be separated from the runtime-fixed fields
>> + * and placed into a different structure, so that the runtime-fixed data
>> + * can be placed into read-only space.
>> + */
>> +struct dpll_data {
>
> is it necessary to export this? usage is limited to dpll.c and could be
> made private to it alone, no?

No, unfortunately dpll_data is used both by the dpll.c and the support 
code under mach-omap2. This is some sort of intermediate solution, so 
get DT clocks working first, then move the support code also under 
drivers/clk/omap.

>
>> +    void __iomem        *mult_div1_reg;
>> +    u32            mult_mask;
>> +    u32            div1_mask;
>> +    struct clk        *clk_bypass;
>> +    struct clk        *clk_ref;
>> +    void __iomem        *control_reg;
>> +    u32            enable_mask;
>> +    unsigned long        last_rounded_rate;
>> +    u16            last_rounded_m;
>> +    u8            last_rounded_m4xen;
>> +    u8            last_rounded_lpmode;
>> +    u16            max_multiplier;
>> +    u8            last_rounded_n;
>> +    u8            min_divider;
>> +    u16            max_divider;
>> +    u8            modes;
>> +    void __iomem        *autoidle_reg;
>> +    void __iomem        *idlest_reg;
>> +    u32            autoidle_mask;
>> +    u32            freqsel_mask;
>> +    u32            idlest_mask;
>> +    u32            dco_mask;
>
> not part of kernel documentation above.
>
>> +    u32            sddiv_mask;
>
> not part of kernel documentation above.

Copy paste from the corresponding mach-omap2 file, I need to double 
check what these parameters actually do.

>
>
>> +    u32            lpmode_mask;
>> +    u32            m4xen_mask;
>> +    u8            auto_recal_bit;
>> +    u8            recal_en_bit;
>> +    u8            recal_st_bit;
>> +    u8            flags;
>> +};
>> +
>> +/**
>> + * struct clk_hw_omap - OMAP struct clk
>> + * @node: list_head connecting this clock into the full clock list
>> + * @enable_reg: register to write to enable the clock (see @enable_bit)
>> + * @enable_bit: bitshift to write to enable/disable the clock (see
>> @enable_reg)
>> + * @flags: see "struct clk.flags possibilities" above
>> + * @clksel_reg: for clksel clks, register va containing src/divisor
>> select
>> + * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
>> + * @clksel: for clksel clks, pointer to struct clksel for this clock
>> + * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
>> + * @clkdm_name: clockdomain name that this clock is contained in
>> + * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name
>> at runtime
>> + * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
>> + * @src_offset: bitshift for source selection bitfield (OMAP1 only)
>> + *
>> + * XXX @rate_offset, @src_offset should probably be removed and OMAP1
>> + * clock code converted to use clksel.
> Do you need to carry these forward? they already disappeared from the
> struct below.

Hmm, I'll check this.

>
>> + *
>> + */
>> +
>> +struct clk_hw_omap_ops;
> you need to keep the kernel documentation next to the struct which it is
> documenting, by introducing clk_hw_omap_ops forward declaration, we
> introduced the following kernel-doc error:
>
> Error(include/linux/clk/omap.h:119): Cannot parse struct or union!

Copy pasted problem it seems, I'll fix it.

>
>> +
>> +struct clk_hw_omap {
>> +    struct clk_hw        hw;
> not documented.
>
>> +    struct list_head    node;
>> +    unsigned long        fixed_rate;
> not documented.
>
>> +    u8            fixed_div;
> not documented.

I'll fix these.

>
>> +    void __iomem        *enable_reg;
>> +    u8            enable_bit;
>> +    u8            flags;
>> +    void __iomem        *clksel_reg;
>> +    u32            clksel_mask;
>> +    const struct clksel    *clksel;
>> +    struct dpll_data    *dpll_data;
>> +    const char        *clkdm_name;
>> +    struct clockdomain    *clkdm;
>> +    const struct clk_hw_omap_ops    *ops;
>> +};
>> +
>> +struct clk_hw_omap_ops {
>> +    void            (*find_idlest)(struct clk_hw_omap *oclk,
>> +                    void __iomem **idlest_reg,
>> +                    u8 *idlest_bit, u8 *idlest_val);
>> +    void            (*find_companion)(struct clk_hw_omap *oclk,
>> +                    void __iomem **other_reg,
>> +                    u8 *other_bit);
>> +    void            (*allow_idle)(struct clk_hw_omap *oclk);
>> +    void            (*deny_idle)(struct clk_hw_omap *oclk);
>> +};
>
> will be nice to have kernel documentation for these.

Okay.

>
>> +
>> +void omap2_init_clk_hw_omap_clocks(struct clk *clk);
>> +int omap3_noncore_dpll_enable(struct clk_hw *hw);
>> +void omap3_noncore_dpll_disable(struct clk_hw *hw);
>> +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
>> +                unsigned long parent_rate);
>> +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
>> +                unsigned long parent_rate);
>> +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
>> +                    unsigned long target_rate,
>> +                    unsigned long *parent_rate);
>> +u8 omap2_init_dpll_parent(struct clk_hw *hw);
>> +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long
>> parent_rate);
>> +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
>> +            unsigned long *parent_rate);
>> +void omap2_init_clk_clkdm(struct clk_hw *clk);
>> +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
>> +                    unsigned long parent_rate);
>> +
>> +int omap2_clkops_enable_clkdm(struct clk_hw *hw);
>> +void omap2_clkops_disable_clkdm(struct clk_hw *hw);
>> +
>> +int omap2_clk_disable_autoidle_all(void);
> ^^ all the above, not clear why we are moving them out enmasse.

Will split out the moves.


>
>> +
>> +extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
>> +extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
> why do we need to export these out?

Ditto. But these are used by the dpll.c code.

>
>> +
>> +/* DT functions */
>> +int dt_omap_clk_init(void);
> in this change, we removed __init -> which should have been done in the
> patch that introduced it in the first place.
>
>> +void of_omap4_dpll_setup(struct device_node *node);
> we should not be needing this.

I think we do.

>
>>
>>   #endif
>>
>
> at this point, we have a dependency between drivers/clk/omap/dpll.c and
> arch/arm/mach-omap2/ -> a possible suggestion will be to move required
> data structures first and operations as required.

My plan is to move the data structs + code later once the initial 
support is in. Otherwise this excercise is going to take much more time 
to get anything up and running.

Also, you can't even move some of the support code / structs, as they 
are still needed by the code under mach-omap2 (clock data for other 
platforms for example.)

-Tero

[PATCHv4 04/33] CLK: omap: move part of the machine specific clock header contents to driver

[Tero Kristo]

On 07/30/2013 09:22 PM, Nishanth Menon wrote:
> this patch should be 3/33 to allow dpll.c to build.
>
> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>> Some of the clock.h contents are needed by the new OMAP clock driver,
>> including dpll_data and clk_hw_omap. Thus, move these to the generic
>> omap header file which can be accessed by the driver.
>>
> Looking at the change, I wonder what the rules are for the movement?
> commit message was not clear.

This is kind of a merge of almost everything that is needed by clock 
drivers at some point. I can move the changes along to the patches that 
actually need the exports for clarity and to keep compilation clean.

>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   arch/arm/mach-omap2/clock.h |  151
>> +----------------------------------------
>>   include/linux/clk/omap.h    |  157
>> ++++++++++++++++++++++++++++++++++++++++++-
>>   2 files changed, 157 insertions(+), 151 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
>> index 7aa32cd..d1a3125 100644
>> --- a/arch/arm/mach-omap2/clock.h
>> +++ b/arch/arm/mach-omap2/clock.h
>> @@ -21,6 +21,7 @@
>>
>>   #include <linux/clkdev.h>
>>   #include <linux/clk-provider.h>
>> +#include <linux/clk/omap.h>
>>
>>   struct omap_clk {
>>       u16                cpu;
>> @@ -178,83 +179,6 @@ struct clksel {
>>       const struct clksel_rate *rates;
>>   };
>>
>> -/**
>> - * struct dpll_data - DPLL registers and integration data
>> - * @mult_div1_reg: register containing the DPLL M and N bitfields
>> - * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
>> - * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
>> - * @clk_bypass: struct clk pointer to the clock's bypass clock input
>> - * @clk_ref: struct clk pointer to the clock's reference clock input
>> - * @control_reg: register containing the DPLL mode bitfield
>> - * @enable_mask: mask of the DPLL mode bitfield in @control_reg
>> - * @last_rounded_rate: cache of the last rate result of
>> omap2_dpll_round_rate()
>> - * @last_rounded_m: cache of the last M result of
>> omap2_dpll_round_rate()
>> - * @last_rounded_m4xen: cache of the last M4X result of
>> - *            omap4_dpll_regm4xen_round_rate()
>> - * @last_rounded_lpmode: cache of the last lpmode result of
>> - *             omap4_dpll_lpmode_recalc()
>> - * @max_multiplier: maximum valid non-bypass multiplier value (actual)
>> - * @last_rounded_n: cache of the last N result of
>> omap2_dpll_round_rate()
>> - * @min_divider: minimum valid non-bypass divider value (actual)
>> - * @max_divider: maximum valid non-bypass divider value (actual)
>> - * @modes: possible values of @enable_mask
>> - * @autoidle_reg: register containing the DPLL autoidle mode bitfield
>> - * @idlest_reg: register containing the DPLL idle status bitfield
>> - * @autoidle_mask: mask of the DPLL autoidle mode bitfield in
>> @autoidle_reg
>> - * @freqsel_mask: mask of the DPLL jitter correction bitfield in
>> @control_reg
>> - * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
>> - * @lpmode_mask: mask of the DPLL low-power mode bitfield in
>> @control_reg
>> - * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
>> - * @auto_recal_bit: bitshift of the driftguard enable bit in
>> @control_reg
>> - * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for
>> recalibration IRQs
>> - * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for
>> recalibration IRQs
>> - * @flags: DPLL type/features (see below)
>> - *
>> - * Possible values for @flags:
>> - * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
>> - *
>> - * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
>> - *
>> - * XXX Some DPLLs have multiple bypass inputs, so it's not technically
>> - * correct to only have one @clk_bypass pointer.
>> - *
>> - * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
>> - * @last_rounded_n) should be separated from the runtime-fixed fields
>> - * and placed into a different structure, so that the runtime-fixed data
>> - * can be placed into read-only space.
>> - */
>> -struct dpll_data {
>> -    void __iomem        *mult_div1_reg;
>> -    u32            mult_mask;
>> -    u32            div1_mask;
>> -    struct clk        *clk_bypass;
>> -    struct clk        *clk_ref;
>> -    void __iomem        *control_reg;
>> -    u32            enable_mask;
>> -    unsigned long        last_rounded_rate;
>> -    u16            last_rounded_m;
>> -    u8            last_rounded_m4xen;
>> -    u8            last_rounded_lpmode;
>> -    u16            max_multiplier;
>> -    u8            last_rounded_n;
>> -    u8            min_divider;
>> -    u16            max_divider;
>> -    u8            modes;
>> -    void __iomem        *autoidle_reg;
>> -    void __iomem        *idlest_reg;
>> -    u32            autoidle_mask;
>> -    u32            freqsel_mask;
>> -    u32            idlest_mask;
>> -    u32            dco_mask;
>> -    u32            sddiv_mask;
>> -    u32            lpmode_mask;
>> -    u32            m4xen_mask;
>> -    u8            auto_recal_bit;
>> -    u8            recal_en_bit;
>> -    u8            recal_st_bit;
>> -    u8            flags;
>> -};
>> -
>>   /*
>>    * struct clk.flags possibilities
>>    *
>> @@ -274,56 +198,6 @@ struct dpll_data {
>>   #define INVERT_ENABLE        (1 << 4)    /* 0 enables, 1 disables */
>>   #define CLOCK_CLKOUTX2        (1 << 5)
>>
>> -/**
>> - * struct clk_hw_omap - OMAP struct clk
>> - * @node: list_head connecting this clock into the full clock list
>> - * @enable_reg: register to write to enable the clock (see @enable_bit)
>> - * @enable_bit: bitshift to write to enable/disable the clock (see
>> @enable_reg)
>> - * @flags: see "struct clk.flags possibilities" above
>> - * @clksel_reg: for clksel clks, register va containing src/divisor
>> select
>> - * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
>> - * @clksel: for clksel clks, pointer to struct clksel for this clock
>> - * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
>> - * @clkdm_name: clockdomain name that this clock is contained in
>> - * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name
>> at runtime
>> - * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
>> - * @src_offset: bitshift for source selection bitfield (OMAP1 only)
>> - *
>> - * XXX @rate_offset, @src_offset should probably be removed and OMAP1
>> - * clock code converted to use clksel.
>> - *
>> - */
>> -
>> -struct clk_hw_omap_ops;
>> -
>> -struct clk_hw_omap {
>> -    struct clk_hw        hw;
>> -    struct list_head    node;
>> -    unsigned long        fixed_rate;
>> -    u8            fixed_div;
>> -    void __iomem        *enable_reg;
>> -    u8            enable_bit;
>> -    u8            flags;
>> -    void __iomem        *clksel_reg;
>> -    u32            clksel_mask;
>> -    const struct clksel    *clksel;
>> -    struct dpll_data    *dpll_data;
>> -    const char        *clkdm_name;
>> -    struct clockdomain    *clkdm;
>> -    const struct clk_hw_omap_ops    *ops;
>> -};
>> -
>> -struct clk_hw_omap_ops {
>> -    void            (*find_idlest)(struct clk_hw_omap *oclk,
>> -                    void __iomem **idlest_reg,
>> -                    u8 *idlest_bit, u8 *idlest_val);
>> -    void            (*find_companion)(struct clk_hw_omap *oclk,
>> -                    void __iomem **other_reg,
>> -                    u8 *other_bit);
>> -    void            (*allow_idle)(struct clk_hw_omap *oclk);
>> -    void            (*deny_idle)(struct clk_hw_omap *oclk);
>> -};
>> -
>>   unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
>>                       unsigned long parent_rate);
>>
>> @@ -356,28 +230,13 @@ unsigned long omap_fixed_divisor_recalc(struct
>> clk_hw *hw,
>>   /* DPLL Type and DCO Selection Flags */
>>   #define DPLL_J_TYPE        0x1
>>
>> -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
>> -            unsigned long *parent_rate);
>> -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long
>> parent_rate);
>> -int omap3_noncore_dpll_enable(struct clk_hw *hw);
>> -void omap3_noncore_dpll_disable(struct clk_hw *hw);
>> -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
>> -                unsigned long parent_rate);
>
> Why are these being moved to generic?

These are used from the dpll.c by the ops.

>
>>   u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
>>   void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
>>   void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
>
>> -unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
>> -                    unsigned long parent_rate);
> why move this?

Same, anyway, I'll cover the rest of similar comments by moving them 
along with the patch that actually needs the export.


>
>>   int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
>>   void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
>>   void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
>> -unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
>> -                unsigned long parent_rate);
>> -long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
>> -                    unsigned long target_rate,
>> -                    unsigned long *parent_rate);
> same here.
>
>>
>> -void omap2_init_clk_clkdm(struct clk_hw *clk);
> same question again.
>
>>   void __init omap2_clk_disable_clkdm_control(void);
>>
>>   /* clkt_clksel.c public functions */
>> @@ -396,7 +255,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8
>> field_val);
>>   extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
>>   extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
>>
>> -u8 omap2_init_dpll_parent(struct clk_hw *hw);
> why move this?
>
>>   unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
>>
>>   int omap2_dflt_clk_enable(struct clk_hw *hw);
>> @@ -408,9 +266,7 @@ void omap2_clk_dflt_find_companion(struct
>> clk_hw_omap *clk,
>>   void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
>>                   void __iomem **idlest_reg,
>>                   u8 *idlest_bit, u8 *idlest_val);
>> -void omap2_init_clk_hw_omap_clocks(struct clk *clk);
> why move this?
>
>>   int omap2_clk_enable_autoidle_all(void);
>> -int omap2_clk_disable_autoidle_all(void);
> why move this?
>
>>   void omap2_clk_enable_init_clocks(const char **clk_names, u8
>> num_clocks);
>>   int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
>>   void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
>> @@ -431,10 +287,8 @@ extern const struct clksel_rate gfx_l3_rates[];
>>   extern const struct clksel_rate dsp_ick_rates[];
>>   extern struct clk dummy_ck;
>>
>> -extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
> is this needed to be moved?
>
>>   extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
>>   extern const struct clk_hw_omap_ops clkhwops_wait;
>> -extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
> is this needed to be moved?
>
>>   extern const struct clk_hw_omap_ops clkhwops_iclk;
>>   extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
>>   extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
>> @@ -460,8 +314,5 @@ extern const struct clksel_rate div31_1to31_rates[];
>>
>>   extern int am33xx_clk_init(void);
>>
>> -extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
>> -extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
>> -
>
>
>>   extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
>>   #endif
>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>> index 647f02f..cba892a 100644
>> --- a/include/linux/clk/omap.h
>> +++ b/include/linux/clk/omap.h
>> @@ -19,6 +19,161 @@
>>   #ifndef __LINUX_CLK_OMAP_H_
>>   #define __LINUX_CLK_OMAP_H_
>>
>> -int __init dt_omap_clk_init(void);
>> +/**
>> + * struct dpll_data - DPLL registers and integration data
>> + * @mult_div1_reg: register containing the DPLL M and N bitfields
>> + * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
>> + * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
>> + * @clk_bypass: struct clk pointer to the clock's bypass clock input
>> + * @clk_ref: struct clk pointer to the clock's reference clock input
>> + * @control_reg: register containing the DPLL mode bitfield
>> + * @enable_mask: mask of the DPLL mode bitfield in @control_reg
>> + * @last_rounded_rate: cache of the last rate result of
>> omap2_dpll_round_rate()
>> + * @last_rounded_m: cache of the last M result of
>> omap2_dpll_round_rate()
>> + * @last_rounded_m4xen: cache of the last M4X result of
>> + *                     omap4_dpll_regm4xen_round_rate()
>> + * @last_rounded_lpmode: cache of the last lpmode result of
>> + *                      omap4_dpll_lpmode_recalc()
>> + * @max_multiplier: maximum valid non-bypass multiplier value (actual)
>> + * @last_rounded_n: cache of the last N result of
>> omap2_dpll_round_rate()
>> + * @min_divider: minimum valid non-bypass divider value (actual)
>> + * @max_divider: maximum valid non-bypass divider value (actual)
>> + * @modes: possible values of @enable_mask
>> + * @autoidle_reg: register containing the DPLL autoidle mode bitfield
>> + * @idlest_reg: register containing the DPLL idle status bitfield
>> + * @autoidle_mask: mask of the DPLL autoidle mode bitfield in
>> @autoidle_reg
>> + * @freqsel_mask: mask of the DPLL jitter correction bitfield in
>> @control_reg
>> + * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
>> + * @lpmode_mask: mask of the DPLL low-power mode bitfield in
>> @control_reg
>> + * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
>> + * @auto_recal_bit: bitshift of the driftguard enable bit in
>> @control_reg
>> + * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for
>> recalibration IRQs
>> + * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for
>> recalibration IRQs
>> + * @flags: DPLL type/features (see below)
>> + *
>> + * Possible values for @flags:
>> + * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
> but the flag is in arch/arm/mach-omap2/clock.h ?

I'll look at this and probably move the flag also.

>
>> + *
>> + * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
>> + *
>> + * XXX Some DPLLs have multiple bypass inputs, so it's not technically
>> + * correct to only have one @clk_bypass pointer.
>> + *
>> + * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
>> + * @last_rounded_n) should be separated from the runtime-fixed fields
>> + * and placed into a different structure, so that the runtime-fixed data
>> + * can be placed into read-only space.
>> + */
>> +struct dpll_data {
>
> is it necessary to export this? usage is limited to dpll.c and could be
> made private to it alone, no?

No, unfortunately dpll_data is used both by the dpll.c and the support 
code under mach-omap2. This is some sort of intermediate solution, so 
get DT clocks working first, then move the support code also under 
drivers/clk/omap.

>
>> +    void __iomem        *mult_div1_reg;
>> +    u32            mult_mask;
>> +    u32            div1_mask;
>> +    struct clk        *clk_bypass;
>> +    struct clk        *clk_ref;
>> +    void __iomem        *control_reg;
>> +    u32            enable_mask;
>> +    unsigned long        last_rounded_rate;
>> +    u16            last_rounded_m;
>> +    u8            last_rounded_m4xen;
>> +    u8            last_rounded_lpmode;
>> +    u16            max_multiplier;
>> +    u8            last_rounded_n;
>> +    u8            min_divider;
>> +    u16            max_divider;
>> +    u8            modes;
>> +    void __iomem        *autoidle_reg;
>> +    void __iomem        *idlest_reg;
>> +    u32            autoidle_mask;
>> +    u32            freqsel_mask;
>> +    u32            idlest_mask;
>> +    u32            dco_mask;
>
> not part of kernel documentation above.
>
>> +    u32            sddiv_mask;
>
> not part of kernel documentation above.

Copy paste from the corresponding mach-omap2 file, I need to double 
check what these parameters actually do.

>
>
>> +    u32            lpmode_mask;
>> +    u32            m4xen_mask;
>> +    u8            auto_recal_bit;
>> +    u8            recal_en_bit;
>> +    u8            recal_st_bit;
>> +    u8            flags;
>> +};
>> +
>> +/**
>> + * struct clk_hw_omap - OMAP struct clk
>> + * @node: list_head connecting this clock into the full clock list
>> + * @enable_reg: register to write to enable the clock (see @enable_bit)
>> + * @enable_bit: bitshift to write to enable/disable the clock (see
>> @enable_reg)
>> + * @flags: see "struct clk.flags possibilities" above
>> + * @clksel_reg: for clksel clks, register va containing src/divisor
>> select
>> + * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
>> + * @clksel: for clksel clks, pointer to struct clksel for this clock
>> + * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
>> + * @clkdm_name: clockdomain name that this clock is contained in
>> + * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name
>> at runtime
>> + * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
>> + * @src_offset: bitshift for source selection bitfield (OMAP1 only)
>> + *
>> + * XXX @rate_offset, @src_offset should probably be removed and OMAP1
>> + * clock code converted to use clksel.
> Do you need to carry these forward? they already disappeared from the
> struct below.

Hmm, I'll check this.

>
>> + *
>> + */
>> +
>> +struct clk_hw_omap_ops;
> you need to keep the kernel documentation next to the struct which it is
> documenting, by introducing clk_hw_omap_ops forward declaration, we
> introduced the following kernel-doc error:
>
> Error(include/linux/clk/omap.h:119): Cannot parse struct or union!

Copy pasted problem it seems, I'll fix it.

>
>> +
>> +struct clk_hw_omap {
>> +    struct clk_hw        hw;
> not documented.
>
>> +    struct list_head    node;
>> +    unsigned long        fixed_rate;
> not documented.
>
>> +    u8            fixed_div;
> not documented.

I'll fix these.

>
>> +    void __iomem        *enable_reg;
>> +    u8            enable_bit;
>> +    u8            flags;
>> +    void __iomem        *clksel_reg;
>> +    u32            clksel_mask;
>> +    const struct clksel    *clksel;
>> +    struct dpll_data    *dpll_data;
>> +    const char        *clkdm_name;
>> +    struct clockdomain    *clkdm;
>> +    const struct clk_hw_omap_ops    *ops;
>> +};
>> +
>> +struct clk_hw_omap_ops {
>> +    void            (*find_idlest)(struct clk_hw_omap *oclk,
>> +                    void __iomem **idlest_reg,
>> +                    u8 *idlest_bit, u8 *idlest_val);
>> +    void            (*find_companion)(struct clk_hw_omap *oclk,
>> +                    void __iomem **other_reg,
>> +                    u8 *other_bit);
>> +    void            (*allow_idle)(struct clk_hw_omap *oclk);
>> +    void            (*deny_idle)(struct clk_hw_omap *oclk);
>> +};
>
> will be nice to have kernel documentation for these.

Okay.

>
>> +
>> +void omap2_init_clk_hw_omap_clocks(struct clk *clk);
>> +int omap3_noncore_dpll_enable(struct clk_hw *hw);
>> +void omap3_noncore_dpll_disable(struct clk_hw *hw);
>> +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
>> +                unsigned long parent_rate);
>> +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
>> +                unsigned long parent_rate);
>> +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
>> +                    unsigned long target_rate,
>> +                    unsigned long *parent_rate);
>> +u8 omap2_init_dpll_parent(struct clk_hw *hw);
>> +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long
>> parent_rate);
>> +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
>> +            unsigned long *parent_rate);
>> +void omap2_init_clk_clkdm(struct clk_hw *clk);
>> +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
>> +                    unsigned long parent_rate);
>> +
>> +int omap2_clkops_enable_clkdm(struct clk_hw *hw);
>> +void omap2_clkops_disable_clkdm(struct clk_hw *hw);
>> +
>> +int omap2_clk_disable_autoidle_all(void);
> ^^ all the above, not clear why we are moving them out enmasse.

Will split out the moves.


>
>> +
>> +extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
>> +extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
> why do we need to export these out?

Ditto. But these are used by the dpll.c code.

>
>> +
>> +/* DT functions */
>> +int dt_omap_clk_init(void);
> in this change, we removed __init -> which should have been done in the
> patch that introduced it in the first place.
>
>> +void of_omap4_dpll_setup(struct device_node *node);
> we should not be needing this.

I think we do.

>
>>
>>   #endif
>>
>
> at this point, we have a dependency between drivers/clk/omap/dpll.c and
> arch/arm/mach-omap2/ -> a possible suggestion will be to move required
> data structures first and operations as required.

My plan is to move the data structs + code later once the initial 
support is in. Otherwise this excercise is going to take much more time 
to get anything up and running.

Also, you can't even move some of the support code / structs, as they 
are still needed by the code under mach-omap2 (clock data for other 
platforms for example.)

-Tero

Re: [PATCHv4 04/33] CLK: omap: move part of the machine specific clock header contents to driver

[Nishanth Menon]

On 07/31/2013 04:59 AM, Tero Kristo wrote:
> On 07/30/2013 09:22 PM, Nishanth Menon wrote:
>> this patch should be 3/33 to allow dpll.c to build.
>>
>> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>>> Some of the clock.h contents are needed by the new OMAP clock driver,
>>> including dpll_data and clk_hw_omap. Thus, move these to the generic
>>> omap header file which can be accessed by the driver.
>>>
>> Looking at the change, I wonder what the rules are for the movement?
>> commit message was not clear.
>
> This is kind of a merge of almost everything that is needed by clock
> drivers at some point. I can move the changes along to the patches that
> actually need the exports for clarity and to keep compilation clean.

I think it is better to do in stages (while ensuring compilation is 
clean) - it is a bit hard to understand need and context of movement 
when a singular movement is done :(
[..]
>>> @@ -356,28 +230,13 @@ unsigned long omap_fixed_divisor_recalc(struct
>>> clk_hw *hw,
>>>   /* DPLL Type and DCO Selection Flags */
>>>   #define DPLL_J_TYPE        0x1
>>>
>>> -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long
>>> target_rate,
>>> -            unsigned long *parent_rate);
>>> -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long
>>> parent_rate);
>>> -int omap3_noncore_dpll_enable(struct clk_hw *hw);
>>> -void omap3_noncore_dpll_disable(struct clk_hw *hw);
>>> -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
>>> -                unsigned long parent_rate);
>>
>> Why are these being moved to generic?
>
> These are used from the dpll.c by the ops.

The ops should probably move as well from mach-omap2. No reason to keep 
it around in mach-omap2 then.
[...]

>>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>>> index 647f02f..cba892a 100644
>>> --- a/include/linux/clk/omap.h
>>> +++ b/include/linux/clk/omap.h
>>> @@ -19,6 +19,161 @@
>>>   #ifndef __LINUX_CLK_OMAP_H_
>>>   #define __LINUX_CLK_OMAP_H_
>>>
>>> -int __init dt_omap_clk_init(void);
>>> +/**
>>> + * struct dpll_data - DPLL registers and integration data
>>> + * @mult_div1_reg: register containing the DPLL M and N bitfields
>>> + * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
>>> + * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
>>> + * @clk_bypass: struct clk pointer to the clock's bypass clock input
>>> + * @clk_ref: struct clk pointer to the clock's reference clock input
>>> + * @control_reg: register containing the DPLL mode bitfield
>>> + * @enable_mask: mask of the DPLL mode bitfield in @control_reg
>>> + * @last_rounded_rate: cache of the last rate result of
>>> omap2_dpll_round_rate()
>>> + * @last_rounded_m: cache of the last M result of
>>> omap2_dpll_round_rate()
>>> + * @last_rounded_m4xen: cache of the last M4X result of
>>> + *                     omap4_dpll_regm4xen_round_rate()
>>> + * @last_rounded_lpmode: cache of the last lpmode result of
>>> + *                      omap4_dpll_lpmode_recalc()
>>> + * @max_multiplier: maximum valid non-bypass multiplier value (actual)
>>> + * @last_rounded_n: cache of the last N result of
>>> omap2_dpll_round_rate()
>>> + * @min_divider: minimum valid non-bypass divider value (actual)
>>> + * @max_divider: maximum valid non-bypass divider value (actual)
>>> + * @modes: possible values of @enable_mask
>>> + * @autoidle_reg: register containing the DPLL autoidle mode bitfield
>>> + * @idlest_reg: register containing the DPLL idle status bitfield
>>> + * @autoidle_mask: mask of the DPLL autoidle mode bitfield in
>>> @autoidle_reg
>>> + * @freqsel_mask: mask of the DPLL jitter correction bitfield in
>>> @control_reg
>>> + * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
>>> + * @lpmode_mask: mask of the DPLL low-power mode bitfield in
>>> @control_reg
>>> + * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in
>>> @control_reg
>>> + * @auto_recal_bit: bitshift of the driftguard enable bit in
>>> @control_reg
>>> + * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for
>>> recalibration IRQs
>>> + * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for
>>> recalibration IRQs
>>> + * @flags: DPLL type/features (see below)
>>> + *
>>> + * Possible values for @flags:
>>> + * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
>> but the flag is in arch/arm/mach-omap2/clock.h ?
>
> I'll look at this and probably move the flag also.
>
>>
>>> + *
>>> + * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
>>> + *
>>> + * XXX Some DPLLs have multiple bypass inputs, so it's not technically
>>> + * correct to only have one @clk_bypass pointer.
>>> + *
>>> + * XXX The runtime-variable fields (@last_rounded_rate,
>>> @last_rounded_m,
>>> + * @last_rounded_n) should be separated from the runtime-fixed fields
>>> + * and placed into a different structure, so that the runtime-fixed
>>> data
>>> + * can be placed into read-only space.
>>> + */
>>> +struct dpll_data {
>>
>> is it necessary to export this? usage is limited to dpll.c and could be
>> made private to it alone, no?
>
> No, unfortunately dpll_data is used both by the dpll.c and the support
> code under mach-omap2. This is some sort of intermediate solution, so
> get DT clocks working first, then move the support code also under
> drivers/clk/omap.

looks like a case for omap_dpll.h instead of a single mega header with 
everything in it?


[...]

-- 
Regards,
Nishanth Menon

[PATCHv4 04/33] CLK: omap: move part of the machine specific clock header contents to driver

[Nishanth Menon]

On 07/31/2013 04:59 AM, Tero Kristo wrote:
> On 07/30/2013 09:22 PM, Nishanth Menon wrote:
>> this patch should be 3/33 to allow dpll.c to build.
>>
>> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>>> Some of the clock.h contents are needed by the new OMAP clock driver,
>>> including dpll_data and clk_hw_omap. Thus, move these to the generic
>>> omap header file which can be accessed by the driver.
>>>
>> Looking at the change, I wonder what the rules are for the movement?
>> commit message was not clear.
>
> This is kind of a merge of almost everything that is needed by clock
> drivers at some point. I can move the changes along to the patches that
> actually need the exports for clarity and to keep compilation clean.

I think it is better to do in stages (while ensuring compilation is 
clean) - it is a bit hard to understand need and context of movement 
when a singular movement is done :(
[..]
>>> @@ -356,28 +230,13 @@ unsigned long omap_fixed_divisor_recalc(struct
>>> clk_hw *hw,
>>>   /* DPLL Type and DCO Selection Flags */
>>>   #define DPLL_J_TYPE        0x1
>>>
>>> -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long
>>> target_rate,
>>> -            unsigned long *parent_rate);
>>> -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long
>>> parent_rate);
>>> -int omap3_noncore_dpll_enable(struct clk_hw *hw);
>>> -void omap3_noncore_dpll_disable(struct clk_hw *hw);
>>> -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
>>> -                unsigned long parent_rate);
>>
>> Why are these being moved to generic?
>
> These are used from the dpll.c by the ops.

The ops should probably move as well from mach-omap2. No reason to keep 
it around in mach-omap2 then.
[...]

>>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>>> index 647f02f..cba892a 100644
>>> --- a/include/linux/clk/omap.h
>>> +++ b/include/linux/clk/omap.h
>>> @@ -19,6 +19,161 @@
>>>   #ifndef __LINUX_CLK_OMAP_H_
>>>   #define __LINUX_CLK_OMAP_H_
>>>
>>> -int __init dt_omap_clk_init(void);
>>> +/**
>>> + * struct dpll_data - DPLL registers and integration data
>>> + * @mult_div1_reg: register containing the DPLL M and N bitfields
>>> + * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
>>> + * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
>>> + * @clk_bypass: struct clk pointer to the clock's bypass clock input
>>> + * @clk_ref: struct clk pointer to the clock's reference clock input
>>> + * @control_reg: register containing the DPLL mode bitfield
>>> + * @enable_mask: mask of the DPLL mode bitfield in @control_reg
>>> + * @last_rounded_rate: cache of the last rate result of
>>> omap2_dpll_round_rate()
>>> + * @last_rounded_m: cache of the last M result of
>>> omap2_dpll_round_rate()
>>> + * @last_rounded_m4xen: cache of the last M4X result of
>>> + *                     omap4_dpll_regm4xen_round_rate()
>>> + * @last_rounded_lpmode: cache of the last lpmode result of
>>> + *                      omap4_dpll_lpmode_recalc()
>>> + * @max_multiplier: maximum valid non-bypass multiplier value (actual)
>>> + * @last_rounded_n: cache of the last N result of
>>> omap2_dpll_round_rate()
>>> + * @min_divider: minimum valid non-bypass divider value (actual)
>>> + * @max_divider: maximum valid non-bypass divider value (actual)
>>> + * @modes: possible values of @enable_mask
>>> + * @autoidle_reg: register containing the DPLL autoidle mode bitfield
>>> + * @idlest_reg: register containing the DPLL idle status bitfield
>>> + * @autoidle_mask: mask of the DPLL autoidle mode bitfield in
>>> @autoidle_reg
>>> + * @freqsel_mask: mask of the DPLL jitter correction bitfield in
>>> @control_reg
>>> + * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
>>> + * @lpmode_mask: mask of the DPLL low-power mode bitfield in
>>> @control_reg
>>> + * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in
>>> @control_reg
>>> + * @auto_recal_bit: bitshift of the driftguard enable bit in
>>> @control_reg
>>> + * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for
>>> recalibration IRQs
>>> + * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for
>>> recalibration IRQs
>>> + * @flags: DPLL type/features (see below)
>>> + *
>>> + * Possible values for @flags:
>>> + * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
>> but the flag is in arch/arm/mach-omap2/clock.h ?
>
> I'll look at this and probably move the flag also.
>
>>
>>> + *
>>> + * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
>>> + *
>>> + * XXX Some DPLLs have multiple bypass inputs, so it's not technically
>>> + * correct to only have one @clk_bypass pointer.
>>> + *
>>> + * XXX The runtime-variable fields (@last_rounded_rate,
>>> @last_rounded_m,
>>> + * @last_rounded_n) should be separated from the runtime-fixed fields
>>> + * and placed into a different structure, so that the runtime-fixed
>>> data
>>> + * can be placed into read-only space.
>>> + */
>>> +struct dpll_data {
>>
>> is it necessary to export this? usage is limited to dpll.c and could be
>> made private to it alone, no?
>
> No, unfortunately dpll_data is used both by the dpll.c and the support
> code under mach-omap2. This is some sort of intermediate solution, so
> get DT clocks working first, then move the support code also under
> drivers/clk/omap.

looks like a case for omap_dpll.h instead of a single mega header with 
everything in it?


[...]

-- 
Regards,
Nishanth Menon

Re: [PATCHv4 04/33] CLK: omap: move part of the machine specific clock header contents to driver

[Tero Kristo]

On 08/01/2013 05:04 PM, Nishanth Menon wrote:
> On 07/31/2013 04:59 AM, Tero Kristo wrote:
>> On 07/30/2013 09:22 PM, Nishanth Menon wrote:
>>> this patch should be 3/33 to allow dpll.c to build.
>>>
>>> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>>>> Some of the clock.h contents are needed by the new OMAP clock driver,
>>>> including dpll_data and clk_hw_omap. Thus, move these to the generic
>>>> omap header file which can be accessed by the driver.
>>>>
>>> Looking at the change, I wonder what the rules are for the movement?
>>> commit message was not clear.
>>
>> This is kind of a merge of almost everything that is needed by clock
>> drivers at some point. I can move the changes along to the patches that
>> actually need the exports for clarity and to keep compilation clean.
>
> I think it is better to do in stages (while ensuring compilation is
> clean) - it is a bit hard to understand need and context of movement
> when a singular movement is done :(

Yep, will do the change for this.

> [..]
>>>> @@ -356,28 +230,13 @@ unsigned long omap_fixed_divisor_recalc(struct
>>>> clk_hw *hw,
>>>>   /* DPLL Type and DCO Selection Flags */
>>>>   #define DPLL_J_TYPE        0x1
>>>>
>>>> -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long
>>>> target_rate,
>>>> -            unsigned long *parent_rate);
>>>> -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long
>>>> parent_rate);
>>>> -int omap3_noncore_dpll_enable(struct clk_hw *hw);
>>>> -void omap3_noncore_dpll_disable(struct clk_hw *hw);
>>>> -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
>>>> -                unsigned long parent_rate);
>>>
>>> Why are these being moved to generic?
>>
>> These are used from the dpll.c by the ops.
>
> The ops should probably move as well from mach-omap2. No reason to keep
> it around in mach-omap2 then.

There is reason.... I don't want to move _everything_ from mach-omap2 in 
the first phase. But after initial support is in, yes, they can be moved.

> [...]
>
>>>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>>>> index 647f02f..cba892a 100644
>>>> --- a/include/linux/clk/omap.h
>>>> +++ b/include/linux/clk/omap.h
>>>> @@ -19,6 +19,161 @@
>>>>   #ifndef __LINUX_CLK_OMAP_H_
>>>>   #define __LINUX_CLK_OMAP_H_
>>>>
>>>> -int __init dt_omap_clk_init(void);
>>>> +/**
>>>> + * struct dpll_data - DPLL registers and integration data
>>>> + * @mult_div1_reg: register containing the DPLL M and N bitfields
>>>> + * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
>>>> + * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
>>>> + * @clk_bypass: struct clk pointer to the clock's bypass clock input
>>>> + * @clk_ref: struct clk pointer to the clock's reference clock input
>>>> + * @control_reg: register containing the DPLL mode bitfield
>>>> + * @enable_mask: mask of the DPLL mode bitfield in @control_reg
>>>> + * @last_rounded_rate: cache of the last rate result of
>>>> omap2_dpll_round_rate()
>>>> + * @last_rounded_m: cache of the last M result of
>>>> omap2_dpll_round_rate()
>>>> + * @last_rounded_m4xen: cache of the last M4X result of
>>>> + *                     omap4_dpll_regm4xen_round_rate()
>>>> + * @last_rounded_lpmode: cache of the last lpmode result of
>>>> + *                      omap4_dpll_lpmode_recalc()
>>>> + * @max_multiplier: maximum valid non-bypass multiplier value (actual)
>>>> + * @last_rounded_n: cache of the last N result of
>>>> omap2_dpll_round_rate()
>>>> + * @min_divider: minimum valid non-bypass divider value (actual)
>>>> + * @max_divider: maximum valid non-bypass divider value (actual)
>>>> + * @modes: possible values of @enable_mask
>>>> + * @autoidle_reg: register containing the DPLL autoidle mode bitfield
>>>> + * @idlest_reg: register containing the DPLL idle status bitfield
>>>> + * @autoidle_mask: mask of the DPLL autoidle mode bitfield in
>>>> @autoidle_reg
>>>> + * @freqsel_mask: mask of the DPLL jitter correction bitfield in
>>>> @control_reg
>>>> + * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
>>>> + * @lpmode_mask: mask of the DPLL low-power mode bitfield in
>>>> @control_reg
>>>> + * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in
>>>> @control_reg
>>>> + * @auto_recal_bit: bitshift of the driftguard enable bit in
>>>> @control_reg
>>>> + * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for
>>>> recalibration IRQs
>>>> + * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for
>>>> recalibration IRQs
>>>> + * @flags: DPLL type/features (see below)
>>>> + *
>>>> + * Possible values for @flags:
>>>> + * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
>>> but the flag is in arch/arm/mach-omap2/clock.h ?
>>
>> I'll look at this and probably move the flag also.
>>
>>>
>>>> + *
>>>> + * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
>>>> + *
>>>> + * XXX Some DPLLs have multiple bypass inputs, so it's not technically
>>>> + * correct to only have one @clk_bypass pointer.
>>>> + *
>>>> + * XXX The runtime-variable fields (@last_rounded_rate,
>>>> @last_rounded_m,
>>>> + * @last_rounded_n) should be separated from the runtime-fixed fields
>>>> + * and placed into a different structure, so that the runtime-fixed
>>>> data
>>>> + * can be placed into read-only space.
>>>> + */
>>>> +struct dpll_data {
>>>
>>> is it necessary to export this? usage is limited to dpll.c and could be
>>> made private to it alone, no?
>>
>> No, unfortunately dpll_data is used both by the dpll.c and the support
>> code under mach-omap2. This is some sort of intermediate solution, so
>> get DT clocks working first, then move the support code also under
>> drivers/clk/omap.
>
> looks like a case for omap_dpll.h instead of a single mega header with
> everything in it?

Well, I am not sure we want to do that, as some stuff will be in 
clk/omap.h and it will be removed once these are moved inside the clk 
driver. The end result should be a header with minimal contents, but it 
is going to be rather large during the intermediate evolution phase.

-Tero

[PATCHv4 04/33] CLK: omap: move part of the machine specific clock header contents to driver

[Tero Kristo]

On 08/01/2013 05:04 PM, Nishanth Menon wrote:
> On 07/31/2013 04:59 AM, Tero Kristo wrote:
>> On 07/30/2013 09:22 PM, Nishanth Menon wrote:
>>> this patch should be 3/33 to allow dpll.c to build.
>>>
>>> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>>>> Some of the clock.h contents are needed by the new OMAP clock driver,
>>>> including dpll_data and clk_hw_omap. Thus, move these to the generic
>>>> omap header file which can be accessed by the driver.
>>>>
>>> Looking at the change, I wonder what the rules are for the movement?
>>> commit message was not clear.
>>
>> This is kind of a merge of almost everything that is needed by clock
>> drivers at some point. I can move the changes along to the patches that
>> actually need the exports for clarity and to keep compilation clean.
>
> I think it is better to do in stages (while ensuring compilation is
> clean) - it is a bit hard to understand need and context of movement
> when a singular movement is done :(

Yep, will do the change for this.

> [..]
>>>> @@ -356,28 +230,13 @@ unsigned long omap_fixed_divisor_recalc(struct
>>>> clk_hw *hw,
>>>>   /* DPLL Type and DCO Selection Flags */
>>>>   #define DPLL_J_TYPE        0x1
>>>>
>>>> -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long
>>>> target_rate,
>>>> -            unsigned long *parent_rate);
>>>> -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long
>>>> parent_rate);
>>>> -int omap3_noncore_dpll_enable(struct clk_hw *hw);
>>>> -void omap3_noncore_dpll_disable(struct clk_hw *hw);
>>>> -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
>>>> -                unsigned long parent_rate);
>>>
>>> Why are these being moved to generic?
>>
>> These are used from the dpll.c by the ops.
>
> The ops should probably move as well from mach-omap2. No reason to keep
> it around in mach-omap2 then.

There is reason.... I don't want to move _everything_ from mach-omap2 in 
the first phase. But after initial support is in, yes, they can be moved.

> [...]
>
>>>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>>>> index 647f02f..cba892a 100644
>>>> --- a/include/linux/clk/omap.h
>>>> +++ b/include/linux/clk/omap.h
>>>> @@ -19,6 +19,161 @@
>>>>   #ifndef __LINUX_CLK_OMAP_H_
>>>>   #define __LINUX_CLK_OMAP_H_
>>>>
>>>> -int __init dt_omap_clk_init(void);
>>>> +/**
>>>> + * struct dpll_data - DPLL registers and integration data
>>>> + * @mult_div1_reg: register containing the DPLL M and N bitfields
>>>> + * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
>>>> + * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
>>>> + * @clk_bypass: struct clk pointer to the clock's bypass clock input
>>>> + * @clk_ref: struct clk pointer to the clock's reference clock input
>>>> + * @control_reg: register containing the DPLL mode bitfield
>>>> + * @enable_mask: mask of the DPLL mode bitfield in @control_reg
>>>> + * @last_rounded_rate: cache of the last rate result of
>>>> omap2_dpll_round_rate()
>>>> + * @last_rounded_m: cache of the last M result of
>>>> omap2_dpll_round_rate()
>>>> + * @last_rounded_m4xen: cache of the last M4X result of
>>>> + *                     omap4_dpll_regm4xen_round_rate()
>>>> + * @last_rounded_lpmode: cache of the last lpmode result of
>>>> + *                      omap4_dpll_lpmode_recalc()
>>>> + * @max_multiplier: maximum valid non-bypass multiplier value (actual)
>>>> + * @last_rounded_n: cache of the last N result of
>>>> omap2_dpll_round_rate()
>>>> + * @min_divider: minimum valid non-bypass divider value (actual)
>>>> + * @max_divider: maximum valid non-bypass divider value (actual)
>>>> + * @modes: possible values of @enable_mask
>>>> + * @autoidle_reg: register containing the DPLL autoidle mode bitfield
>>>> + * @idlest_reg: register containing the DPLL idle status bitfield
>>>> + * @autoidle_mask: mask of the DPLL autoidle mode bitfield in
>>>> @autoidle_reg
>>>> + * @freqsel_mask: mask of the DPLL jitter correction bitfield in
>>>> @control_reg
>>>> + * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
>>>> + * @lpmode_mask: mask of the DPLL low-power mode bitfield in
>>>> @control_reg
>>>> + * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in
>>>> @control_reg
>>>> + * @auto_recal_bit: bitshift of the driftguard enable bit in
>>>> @control_reg
>>>> + * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for
>>>> recalibration IRQs
>>>> + * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for
>>>> recalibration IRQs
>>>> + * @flags: DPLL type/features (see below)
>>>> + *
>>>> + * Possible values for @flags:
>>>> + * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
>>> but the flag is in arch/arm/mach-omap2/clock.h ?
>>
>> I'll look at this and probably move the flag also.
>>
>>>
>>>> + *
>>>> + * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
>>>> + *
>>>> + * XXX Some DPLLs have multiple bypass inputs, so it's not technically
>>>> + * correct to only have one @clk_bypass pointer.
>>>> + *
>>>> + * XXX The runtime-variable fields (@last_rounded_rate,
>>>> @last_rounded_m,
>>>> + * @last_rounded_n) should be separated from the runtime-fixed fields
>>>> + * and placed into a different structure, so that the runtime-fixed
>>>> data
>>>> + * can be placed into read-only space.
>>>> + */
>>>> +struct dpll_data {
>>>
>>> is it necessary to export this? usage is limited to dpll.c and could be
>>> made private to it alone, no?
>>
>> No, unfortunately dpll_data is used both by the dpll.c and the support
>> code under mach-omap2. This is some sort of intermediate solution, so
>> get DT clocks working first, then move the support code also under
>> drivers/clk/omap.
>
> looks like a case for omap_dpll.h instead of a single mega header with
> everything in it?

Well, I am not sure we want to do that, as some stuff will be in 
clk/omap.h and it will be removed once these are moved inside the clk 
driver. The end result should be a header with minimal contents, but it 
is going to be rather large during the intermediate evolution phase.

-Tero

Re: [PATCHv4 04/33] CLK: omap: move part of the machine specific clock header contents to driver

[Nishanth Menon]

On 08/01/2013 10:12 AM, Tero Kristo wrote:
> On 08/01/2013 05:04 PM, Nishanth Menon wrote:
>> On 07/31/2013 04:59 AM, Tero Kristo wrote:
>>> On 07/30/2013 09:22 PM, Nishanth Menon wrote:
>>>> this patch should be 3/33 to allow dpll.c to build.
>>>>
>>>> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>>>>> Some of the clock.h contents are needed by the new OMAP clock driver,
>>>>> including dpll_data and clk_hw_omap. Thus, move these to the generic
>>>>> omap header file which can be accessed by the driver.
>>>>>
>>>> Looking at the change, I wonder what the rules are for the movement?
>>>> commit message was not clear.
>>>
>>> This is kind of a merge of almost everything that is needed by clock
>>> drivers at some point. I can move the changes along to the patches that
>>> actually need the exports for clarity and to keep compilation clean.
>>
>> I think it is better to do in stages (while ensuring compilation is
>> clean) - it is a bit hard to understand need and context of movement
>> when a singular movement is done :(
>
> Yep, will do the change for this.
>
>> [..]
>>>>> @@ -356,28 +230,13 @@ unsigned long omap_fixed_divisor_recalc(struct
>>>>> clk_hw *hw,
>>>>>   /* DPLL Type and DCO Selection Flags */
>>>>>   #define DPLL_J_TYPE        0x1
>>>>>
>>>>> -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long
>>>>> target_rate,
>>>>> -            unsigned long *parent_rate);
>>>>> -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long
>>>>> parent_rate);
>>>>> -int omap3_noncore_dpll_enable(struct clk_hw *hw);
>>>>> -void omap3_noncore_dpll_disable(struct clk_hw *hw);
>>>>> -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long
>>>>> rate,
>>>>> -                unsigned long parent_rate);
>>>>
>>>> Why are these being moved to generic?
>>>
>>> These are used from the dpll.c by the ops.
>>
>> The ops should probably move as well from mach-omap2. No reason to keep
>> it around in mach-omap2 then.
>
> There is reason.... I don't want to move _everything_ from mach-omap2 in
> the first phase. But after initial support is in, yes, they can be moved.

I will re-iterate my suggestion again - DPLL enable/disable stuff is 
going to be a series of steps, which would not change if we do DT or 
non-DT. currently those steps reside inside mach-omap2. having a driver 
call into mach-omap2 is counter-intutive, at least to me. if we want to 
have a cleanup in the future, mach-omap2 should depend on drivers/clk 
rather than the other way around. This is the reason of requesting files 
in drivers/clk to be as isolated as possible - dpll operations (the 
actual steps) of doing dpll configuration does sound isolated enough to 
move into drivers/clk and not have reverse dependencies.

Any reverse dependencies should be clearly mentioned with reasoning why 
it cannot be moved in the respective patches, it was a little hard for 
me to indicate precisely which functions make absolutely no sense and 
which not.

I am not saying this is an easy step to do, but for our future cleanups, 
it does sound reasonable to expect from this series.

-- 
Regards,
Nishanth Menon

[PATCHv4 04/33] CLK: omap: move part of the machine specific clock header contents to driver

[Nishanth Menon]

On 08/01/2013 10:12 AM, Tero Kristo wrote:
> On 08/01/2013 05:04 PM, Nishanth Menon wrote:
>> On 07/31/2013 04:59 AM, Tero Kristo wrote:
>>> On 07/30/2013 09:22 PM, Nishanth Menon wrote:
>>>> this patch should be 3/33 to allow dpll.c to build.
>>>>
>>>> On 07/23/2013 02:19 AM, Tero Kristo wrote:
>>>>> Some of the clock.h contents are needed by the new OMAP clock driver,
>>>>> including dpll_data and clk_hw_omap. Thus, move these to the generic
>>>>> omap header file which can be accessed by the driver.
>>>>>
>>>> Looking at the change, I wonder what the rules are for the movement?
>>>> commit message was not clear.
>>>
>>> This is kind of a merge of almost everything that is needed by clock
>>> drivers at some point. I can move the changes along to the patches that
>>> actually need the exports for clarity and to keep compilation clean.
>>
>> I think it is better to do in stages (while ensuring compilation is
>> clean) - it is a bit hard to understand need and context of movement
>> when a singular movement is done :(
>
> Yep, will do the change for this.
>
>> [..]
>>>>> @@ -356,28 +230,13 @@ unsigned long omap_fixed_divisor_recalc(struct
>>>>> clk_hw *hw,
>>>>>   /* DPLL Type and DCO Selection Flags */
>>>>>   #define DPLL_J_TYPE        0x1
>>>>>
>>>>> -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long
>>>>> target_rate,
>>>>> -            unsigned long *parent_rate);
>>>>> -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long
>>>>> parent_rate);
>>>>> -int omap3_noncore_dpll_enable(struct clk_hw *hw);
>>>>> -void omap3_noncore_dpll_disable(struct clk_hw *hw);
>>>>> -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long
>>>>> rate,
>>>>> -                unsigned long parent_rate);
>>>>
>>>> Why are these being moved to generic?
>>>
>>> These are used from the dpll.c by the ops.
>>
>> The ops should probably move as well from mach-omap2. No reason to keep
>> it around in mach-omap2 then.
>
> There is reason.... I don't want to move _everything_ from mach-omap2 in
> the first phase. But after initial support is in, yes, they can be moved.

I will re-iterate my suggestion again - DPLL enable/disable stuff is 
going to be a series of steps, which would not change if we do DT or 
non-DT. currently those steps reside inside mach-omap2. having a driver 
call into mach-omap2 is counter-intutive, at least to me. if we want to 
have a cleanup in the future, mach-omap2 should depend on drivers/clk 
rather than the other way around. This is the reason of requesting files 
in drivers/clk to be as isolated as possible - dpll operations (the 
actual steps) of doing dpll configuration does sound isolated enough to 
move into drivers/clk and not have reverse dependencies.

Any reverse dependencies should be clearly mentioned with reasoning why 
it cannot be moved in the respective patches, it was a little hard for 
me to indicate precisely which functions make absolutely no sense and 
which not.

I am not saying this is an easy step to do, but for our future cleanups, 
it does sound reasonable to expect from this series.

-- 
Regards,
Nishanth Menon

[PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Tero Kristo]

Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name, or alternatively through the device node of
the consumer. With drivers, that don't support DT fully yet, add
mechanism to register specific clock names.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/clk.c   |   39 +++++++++++++++++++++++++++++++++++++++
 include/linux/clk/omap.h |   17 +++++++++++++++++
 2 files changed, 56 insertions(+)

diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index 1dafdaa..cd31a81 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -32,6 +32,45 @@ static const struct of_device_id clk_match[] = {
 	{},
 };
 
+ /**
+ * omap_dt_clocks_register - register DT duplicate clocks during boot
+ * @oclks: list of clocks to register
+ * @cnt: number of clocks
+ *
+ * Register duplicate or non-standard DT clock entries during boot. By
+ * default, DT clocks are found based on their node name. If any
+ * additional con-id / dev-id -> clock mapping is required, use this
+ * function to list these.
+ */
+void __init omap_dt_clocks_register(struct omap_dt_clk oclks[], int cnt)
+{
+	struct omap_dt_clk *c;
+	struct device_node *n;
+	struct clk *clk;
+	struct of_phandle_args clkspec;
+
+	for (c = oclks; c < oclks + cnt; c++) {
+		n = of_find_node_by_name(NULL, c->node_name);
+
+		if (!n) {
+			pr_err("%s: %s not found!\n", __func__, c->node_name);
+			continue;
+		}
+
+		clkspec.np = n;
+
+		clk = of_clk_get_from_provider(&clkspec);
+
+		if (!clk) {
+			pr_err("%s: %s has no clock!\n", __func__,
+				c->node_name);
+			continue;
+		}
+		c->lk.clk = clk;
+		clkdev_add(&c->lk);
+	}
+}
+
 /* FIXME - need to initialize early; skip real driver registration & probe */
 int __init dt_omap_clk_init(void)
 {
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index cba892a..c39e775 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -19,6 +19,8 @@
 #ifndef __LINUX_CLK_OMAP_H_
 #define __LINUX_CLK_OMAP_H_
 
+#include <linux/clkdev.h>
+
 /**
  * struct dpll_data - DPLL registers and integration data
  * @mult_div1_reg: register containing the DPLL M and N bitfields
@@ -146,6 +148,20 @@ struct clk_hw_omap_ops {
 	void			(*deny_idle)(struct clk_hw_omap *oclk);
 };
 
+struct omap_dt_clk {
+	struct clk_lookup		lk;
+	const char			*node_name;
+};
+
+#define DT_CLK(dev, con, name)		\
+	{				\
+		.lk = {			\
+			.dev_id = dev,	\
+			.con_id = con,	\
+		},			\
+		.node_name = name,	\
+	}
+
 void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap3_noncore_dpll_enable(struct clk_hw *hw);
 void omap3_noncore_dpll_disable(struct clk_hw *hw);
@@ -174,6 +190,7 @@ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 
 /* DT functions */
 int dt_omap_clk_init(void);
+extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
 void of_omap4_dpll_setup(struct device_node *node);
 
 #endif
-- 
1.7.9.5

[PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Tero Kristo]

Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name, or alternatively through the device node of
the consumer. With drivers, that don't support DT fully yet, add
mechanism to register specific clock names.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/clk.c   |   39 +++++++++++++++++++++++++++++++++++++++
 include/linux/clk/omap.h |   17 +++++++++++++++++
 2 files changed, 56 insertions(+)

diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index 1dafdaa..cd31a81 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -32,6 +32,45 @@ static const struct of_device_id clk_match[] = {
 	{},
 };
 
+ /**
+ * omap_dt_clocks_register - register DT duplicate clocks during boot
+ * @oclks: list of clocks to register
+ * @cnt: number of clocks
+ *
+ * Register duplicate or non-standard DT clock entries during boot. By
+ * default, DT clocks are found based on their node name. If any
+ * additional con-id / dev-id -> clock mapping is required, use this
+ * function to list these.
+ */
+void __init omap_dt_clocks_register(struct omap_dt_clk oclks[], int cnt)
+{
+	struct omap_dt_clk *c;
+	struct device_node *n;
+	struct clk *clk;
+	struct of_phandle_args clkspec;
+
+	for (c = oclks; c < oclks + cnt; c++) {
+		n = of_find_node_by_name(NULL, c->node_name);
+
+		if (!n) {
+			pr_err("%s: %s not found!\n", __func__, c->node_name);
+			continue;
+		}
+
+		clkspec.np = n;
+
+		clk = of_clk_get_from_provider(&clkspec);
+
+		if (!clk) {
+			pr_err("%s: %s has no clock!\n", __func__,
+				c->node_name);
+			continue;
+		}
+		c->lk.clk = clk;
+		clkdev_add(&c->lk);
+	}
+}
+
 /* FIXME - need to initialize early; skip real driver registration & probe */
 int __init dt_omap_clk_init(void)
 {
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index cba892a..c39e775 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -19,6 +19,8 @@
 #ifndef __LINUX_CLK_OMAP_H_
 #define __LINUX_CLK_OMAP_H_
 
+#include <linux/clkdev.h>
+
 /**
  * struct dpll_data - DPLL registers and integration data
  * @mult_div1_reg: register containing the DPLL M and N bitfields
@@ -146,6 +148,20 @@ struct clk_hw_omap_ops {
 	void			(*deny_idle)(struct clk_hw_omap *oclk);
 };
 
+struct omap_dt_clk {
+	struct clk_lookup		lk;
+	const char			*node_name;
+};
+
+#define DT_CLK(dev, con, name)		\
+	{				\
+		.lk = {			\
+			.dev_id = dev,	\
+			.con_id = con,	\
+		},			\
+		.node_name = name,	\
+	}
+
 void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap3_noncore_dpll_enable(struct clk_hw *hw);
 void omap3_noncore_dpll_disable(struct clk_hw *hw);
@@ -174,6 +190,7 @@ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 
 /* DT functions */
 int dt_omap_clk_init(void);
+extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
 void of_omap4_dpll_setup(struct device_node *node);
 
 #endif
-- 
1.7.9.5

Re: [PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> Some devices require their clocks to be available with a specific
> dev-id con-id mapping. With DT, the clocks can be found by default
> only with their name, or alternatively through the device node of
> the consumer. With drivers, that don't support DT fully yet, add
> mechanism to register specific clock names.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>

with this, should it not be enough to add clocks=<&phandle>

I am not sure I understand what specific drivers should need to carry 
this "old hack" forward. More importantly, why is it preferable to carry 
the hack forward rather than fixing the drivers.


> ---
>   drivers/clk/omap/clk.c   |   39 +++++++++++++++++++++++++++++++++++++++
>   include/linux/clk/omap.h |   17 +++++++++++++++++
>   2 files changed, 56 insertions(+)
>
> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
> index 1dafdaa..cd31a81 100644
> --- a/drivers/clk/omap/clk.c
> +++ b/drivers/clk/omap/clk.c
> @@ -32,6 +32,45 @@ static const struct of_device_id clk_match[] = {
>   	{},
>   };
>
> + /**
> + * omap_dt_clocks_register - register DT duplicate clocks during boot
> + * @oclks: list of clocks to register
> + * @cnt: number of clocks
> + *
> + * Register duplicate or non-standard DT clock entries during boot. By
> + * default, DT clocks are found based on their node name. If any
> + * additional con-id / dev-id -> clock mapping is required, use this
> + * function to list these.
> + */
> +void __init omap_dt_clocks_register(struct omap_dt_clk oclks[], int cnt)

Cant we use a NULL terminated array? then we dont need to pass cnt.

> +{
> +	struct omap_dt_clk *c;
> +	struct device_node *n;
> +	struct clk *clk;
> +	struct of_phandle_args clkspec;
> +
> +	for (c = oclks; c < oclks + cnt; c++) {
> +		n = of_find_node_by_name(NULL, c->node_name);
> +
> +		if (!n) {
> +			pr_err("%s: %s not found!\n", __func__, c->node_name);
> +			continue;
> +		}
> +
> +		clkspec.np = n;
> +
> +		clk = of_clk_get_from_provider(&clkspec);
> +
> +		if (!clk) {
> +			pr_err("%s: %s has no clock!\n", __func__,
> +				c->node_name);
> +			continue;
> +		}
> +		c->lk.clk = clk;
> +		clkdev_add(&c->lk);

why not clk_add_alias ?

> +	}
> +}
> +
>   /* FIXME - need to initialize early; skip real driver registration & probe */
>   int __init dt_omap_clk_init(void)
>   {
> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
> index cba892a..c39e775 100644
> --- a/include/linux/clk/omap.h
> +++ b/include/linux/clk/omap.h
> @@ -19,6 +19,8 @@
>   #ifndef __LINUX_CLK_OMAP_H_
>   #define __LINUX_CLK_OMAP_H_
>
> +#include <linux/clkdev.h>
> +
>   /**
>    * struct dpll_data - DPLL registers and integration data
>    * @mult_div1_reg: register containing the DPLL M and N bitfields
> @@ -146,6 +148,20 @@ struct clk_hw_omap_ops {
>   	void			(*deny_idle)(struct clk_hw_omap *oclk);
>   };
>
> +struct omap_dt_clk {
> +	struct clk_lookup		lk;
> +	const char			*node_name;
> +};
> +

documentation missing.

> +#define DT_CLK(dev, con, name)		\
> +	{				\
> +		.lk = {			\
> +			.dev_id = dev,	\
> +			.con_id = con,	\
> +		},			\
> +		.node_name = name,	\
> +	}
> +
>   void omap2_init_clk_hw_omap_clocks(struct clk *clk);
>   int omap3_noncore_dpll_enable(struct clk_hw *hw);
>   void omap3_noncore_dpll_disable(struct clk_hw *hw);
> @@ -174,6 +190,7 @@ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
>
>   /* DT functions */
>   int dt_omap_clk_init(void);
> +extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);

do you need the extern?

>   void of_omap4_dpll_setup(struct device_node *node);
>
>   #endif
>


-- 
Regards,
Nishanth Menon

[PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> Some devices require their clocks to be available with a specific
> dev-id con-id mapping. With DT, the clocks can be found by default
> only with their name, or alternatively through the device node of
> the consumer. With drivers, that don't support DT fully yet, add
> mechanism to register specific clock names.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>

with this, should it not be enough to add clocks=<&phandle>

I am not sure I understand what specific drivers should need to carry 
this "old hack" forward. More importantly, why is it preferable to carry 
the hack forward rather than fixing the drivers.


> ---
>   drivers/clk/omap/clk.c   |   39 +++++++++++++++++++++++++++++++++++++++
>   include/linux/clk/omap.h |   17 +++++++++++++++++
>   2 files changed, 56 insertions(+)
>
> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
> index 1dafdaa..cd31a81 100644
> --- a/drivers/clk/omap/clk.c
> +++ b/drivers/clk/omap/clk.c
> @@ -32,6 +32,45 @@ static const struct of_device_id clk_match[] = {
>   	{},
>   };
>
> + /**
> + * omap_dt_clocks_register - register DT duplicate clocks during boot
> + * @oclks: list of clocks to register
> + * @cnt: number of clocks
> + *
> + * Register duplicate or non-standard DT clock entries during boot. By
> + * default, DT clocks are found based on their node name. If any
> + * additional con-id / dev-id -> clock mapping is required, use this
> + * function to list these.
> + */
> +void __init omap_dt_clocks_register(struct omap_dt_clk oclks[], int cnt)

Cant we use a NULL terminated array? then we dont need to pass cnt.

> +{
> +	struct omap_dt_clk *c;
> +	struct device_node *n;
> +	struct clk *clk;
> +	struct of_phandle_args clkspec;
> +
> +	for (c = oclks; c < oclks + cnt; c++) {
> +		n = of_find_node_by_name(NULL, c->node_name);
> +
> +		if (!n) {
> +			pr_err("%s: %s not found!\n", __func__, c->node_name);
> +			continue;
> +		}
> +
> +		clkspec.np = n;
> +
> +		clk = of_clk_get_from_provider(&clkspec);
> +
> +		if (!clk) {
> +			pr_err("%s: %s has no clock!\n", __func__,
> +				c->node_name);
> +			continue;
> +		}
> +		c->lk.clk = clk;
> +		clkdev_add(&c->lk);

why not clk_add_alias ?

> +	}
> +}
> +
>   /* FIXME - need to initialize early; skip real driver registration & probe */
>   int __init dt_omap_clk_init(void)
>   {
> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
> index cba892a..c39e775 100644
> --- a/include/linux/clk/omap.h
> +++ b/include/linux/clk/omap.h
> @@ -19,6 +19,8 @@
>   #ifndef __LINUX_CLK_OMAP_H_
>   #define __LINUX_CLK_OMAP_H_
>
> +#include <linux/clkdev.h>
> +
>   /**
>    * struct dpll_data - DPLL registers and integration data
>    * @mult_div1_reg: register containing the DPLL M and N bitfields
> @@ -146,6 +148,20 @@ struct clk_hw_omap_ops {
>   	void			(*deny_idle)(struct clk_hw_omap *oclk);
>   };
>
> +struct omap_dt_clk {
> +	struct clk_lookup		lk;
> +	const char			*node_name;
> +};
> +

documentation missing.

> +#define DT_CLK(dev, con, name)		\
> +	{				\
> +		.lk = {			\
> +			.dev_id = dev,	\
> +			.con_id = con,	\
> +		},			\
> +		.node_name = name,	\
> +	}
> +
>   void omap2_init_clk_hw_omap_clocks(struct clk *clk);
>   int omap3_noncore_dpll_enable(struct clk_hw *hw);
>   void omap3_noncore_dpll_disable(struct clk_hw *hw);
> @@ -174,6 +190,7 @@ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
>
>   /* DT functions */
>   int dt_omap_clk_init(void);
> +extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);

do you need the extern?

>   void of_omap4_dpll_setup(struct device_node *node);
>
>   #endif
>


-- 
Regards,
Nishanth Menon

Re: [PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Tero Kristo]

On 07/30/2013 09:40 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> Some devices require their clocks to be available with a specific
>> dev-id con-id mapping. With DT, the clocks can be found by default
>> only with their name, or alternatively through the device node of
>> the consumer. With drivers, that don't support DT fully yet, add
>> mechanism to register specific clock names.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>
> with this, should it not be enough to add clocks=<&phandle>

Don't know, I am not an expert on DT. :)

>
> I am not sure I understand what specific drivers should need to carry
> this "old hack" forward. More importantly, why is it preferable to carry
> the hack forward rather than fixing the drivers.

At least the GP timer seems to need this, and I don't want to touch / 
verify all the potential drivers touched by this so it is easier to 
provide a (semi) temporary tweak.

>
>
>> ---
>>   drivers/clk/omap/clk.c   |   39 +++++++++++++++++++++++++++++++++++++++
>>   include/linux/clk/omap.h |   17 +++++++++++++++++
>>   2 files changed, 56 insertions(+)
>>
>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>> index 1dafdaa..cd31a81 100644
>> --- a/drivers/clk/omap/clk.c
>> +++ b/drivers/clk/omap/clk.c
>> @@ -32,6 +32,45 @@ static const struct of_device_id clk_match[] = {
>>       {},
>>   };
>>
>> + /**
>> + * omap_dt_clocks_register - register DT duplicate clocks during boot
>> + * @oclks: list of clocks to register
>> + * @cnt: number of clocks
>> + *
>> + * Register duplicate or non-standard DT clock entries during boot. By
>> + * default, DT clocks are found based on their node name. If any
>> + * additional con-id / dev-id -> clock mapping is required, use this
>> + * function to list these.
>> + */
>> +void __init omap_dt_clocks_register(struct omap_dt_clk oclks[], int cnt)
>
> Cant we use a NULL terminated array? then we dont need to pass cnt.

Yea can.

>
>> +{
>> +    struct omap_dt_clk *c;
>> +    struct device_node *n;
>> +    struct clk *clk;
>> +    struct of_phandle_args clkspec;
>> +
>> +    for (c = oclks; c < oclks + cnt; c++) {
>> +        n = of_find_node_by_name(NULL, c->node_name);
>> +
>> +        if (!n) {
>> +            pr_err("%s: %s not found!\n", __func__, c->node_name);
>> +            continue;
>> +        }
>> +
>> +        clkspec.np = n;
>> +
>> +        clk = of_clk_get_from_provider(&clkspec);
>> +
>> +        if (!clk) {
>> +            pr_err("%s: %s has no clock!\n", __func__,
>> +                c->node_name);
>> +            continue;
>> +        }
>> +        c->lk.clk = clk;
>> +        clkdev_add(&c->lk);
>
> why not clk_add_alias ?

Hmm yea, that might work also now that I made patch #1.

>
>> +    }
>> +}
>> +
>>   /* FIXME - need to initialize early; skip real driver registration &
>> probe */
>>   int __init dt_omap_clk_init(void)
>>   {
>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>> index cba892a..c39e775 100644
>> --- a/include/linux/clk/omap.h
>> +++ b/include/linux/clk/omap.h
>> @@ -19,6 +19,8 @@
>>   #ifndef __LINUX_CLK_OMAP_H_
>>   #define __LINUX_CLK_OMAP_H_
>>
>> +#include <linux/clkdev.h>
>> +
>>   /**
>>    * struct dpll_data - DPLL registers and integration data
>>    * @mult_div1_reg: register containing the DPLL M and N bitfields
>> @@ -146,6 +148,20 @@ struct clk_hw_omap_ops {
>>       void            (*deny_idle)(struct clk_hw_omap *oclk);
>>   };
>>
>> +struct omap_dt_clk {
>> +    struct clk_lookup        lk;
>> +    const char            *node_name;
>> +};
>> +
>
> documentation missing.

Yea, will add.

>
>> +#define DT_CLK(dev, con, name)        \
>> +    {                \
>> +        .lk = {            \
>> +            .dev_id = dev,    \
>> +            .con_id = con,    \
>> +        },            \
>> +        .node_name = name,    \
>> +    }
>> +
>>   void omap2_init_clk_hw_omap_clocks(struct clk *clk);
>>   int omap3_noncore_dpll_enable(struct clk_hw *hw);
>>   void omap3_noncore_dpll_disable(struct clk_hw *hw);
>> @@ -174,6 +190,7 @@ extern const struct clk_hw_omap_ops
>> clkhwops_omap4_dpllmx;
>>
>>   /* DT functions */
>>   int dt_omap_clk_init(void);
>> +extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
>
> do you need the extern?

I guess not.

>
>>   void of_omap4_dpll_setup(struct device_node *node);
>>
>>   #endif
>>
>
>

[PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Tero Kristo]

On 07/30/2013 09:40 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> Some devices require their clocks to be available with a specific
>> dev-id con-id mapping. With DT, the clocks can be found by default
>> only with their name, or alternatively through the device node of
>> the consumer. With drivers, that don't support DT fully yet, add
>> mechanism to register specific clock names.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>
> with this, should it not be enough to add clocks=<&phandle>

Don't know, I am not an expert on DT. :)

>
> I am not sure I understand what specific drivers should need to carry
> this "old hack" forward. More importantly, why is it preferable to carry
> the hack forward rather than fixing the drivers.

At least the GP timer seems to need this, and I don't want to touch / 
verify all the potential drivers touched by this so it is easier to 
provide a (semi) temporary tweak.

>
>
>> ---
>>   drivers/clk/omap/clk.c   |   39 +++++++++++++++++++++++++++++++++++++++
>>   include/linux/clk/omap.h |   17 +++++++++++++++++
>>   2 files changed, 56 insertions(+)
>>
>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>> index 1dafdaa..cd31a81 100644
>> --- a/drivers/clk/omap/clk.c
>> +++ b/drivers/clk/omap/clk.c
>> @@ -32,6 +32,45 @@ static const struct of_device_id clk_match[] = {
>>       {},
>>   };
>>
>> + /**
>> + * omap_dt_clocks_register - register DT duplicate clocks during boot
>> + * @oclks: list of clocks to register
>> + * @cnt: number of clocks
>> + *
>> + * Register duplicate or non-standard DT clock entries during boot. By
>> + * default, DT clocks are found based on their node name. If any
>> + * additional con-id / dev-id -> clock mapping is required, use this
>> + * function to list these.
>> + */
>> +void __init omap_dt_clocks_register(struct omap_dt_clk oclks[], int cnt)
>
> Cant we use a NULL terminated array? then we dont need to pass cnt.

Yea can.

>
>> +{
>> +    struct omap_dt_clk *c;
>> +    struct device_node *n;
>> +    struct clk *clk;
>> +    struct of_phandle_args clkspec;
>> +
>> +    for (c = oclks; c < oclks + cnt; c++) {
>> +        n = of_find_node_by_name(NULL, c->node_name);
>> +
>> +        if (!n) {
>> +            pr_err("%s: %s not found!\n", __func__, c->node_name);
>> +            continue;
>> +        }
>> +
>> +        clkspec.np = n;
>> +
>> +        clk = of_clk_get_from_provider(&clkspec);
>> +
>> +        if (!clk) {
>> +            pr_err("%s: %s has no clock!\n", __func__,
>> +                c->node_name);
>> +            continue;
>> +        }
>> +        c->lk.clk = clk;
>> +        clkdev_add(&c->lk);
>
> why not clk_add_alias ?

Hmm yea, that might work also now that I made patch #1.

>
>> +    }
>> +}
>> +
>>   /* FIXME - need to initialize early; skip real driver registration &
>> probe */
>>   int __init dt_omap_clk_init(void)
>>   {
>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>> index cba892a..c39e775 100644
>> --- a/include/linux/clk/omap.h
>> +++ b/include/linux/clk/omap.h
>> @@ -19,6 +19,8 @@
>>   #ifndef __LINUX_CLK_OMAP_H_
>>   #define __LINUX_CLK_OMAP_H_
>>
>> +#include <linux/clkdev.h>
>> +
>>   /**
>>    * struct dpll_data - DPLL registers and integration data
>>    * @mult_div1_reg: register containing the DPLL M and N bitfields
>> @@ -146,6 +148,20 @@ struct clk_hw_omap_ops {
>>       void            (*deny_idle)(struct clk_hw_omap *oclk);
>>   };
>>
>> +struct omap_dt_clk {
>> +    struct clk_lookup        lk;
>> +    const char            *node_name;
>> +};
>> +
>
> documentation missing.

Yea, will add.

>
>> +#define DT_CLK(dev, con, name)        \
>> +    {                \
>> +        .lk = {            \
>> +            .dev_id = dev,    \
>> +            .con_id = con,    \
>> +        },            \
>> +        .node_name = name,    \
>> +    }
>> +
>>   void omap2_init_clk_hw_omap_clocks(struct clk *clk);
>>   int omap3_noncore_dpll_enable(struct clk_hw *hw);
>>   void omap3_noncore_dpll_disable(struct clk_hw *hw);
>> @@ -174,6 +190,7 @@ extern const struct clk_hw_omap_ops
>> clkhwops_omap4_dpllmx;
>>
>>   /* DT functions */
>>   int dt_omap_clk_init(void);
>> +extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
>
> do you need the extern?

I guess not.

>
>>   void of_omap4_dpll_setup(struct device_node *node);
>>
>>   #endif
>>
>
>

Re: [PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Nishanth Menon]

On 07/31/2013 05:07 AM, Tero Kristo wrote:
> On 07/30/2013 09:40 PM, Nishanth Menon wrote:
>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>> Some devices require their clocks to be available with a specific
>>> dev-id con-id mapping. With DT, the clocks can be found by default
>>> only with their name, or alternatively through the device node of
>>> the consumer. With drivers, that don't support DT fully yet, add
>>> mechanism to register specific clock names.
>>>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>
>> with this, should it not be enough to add clocks=<&phandle>
>
> Don't know, I am not an expert on DT. :)

That is the usage - 
Documentation/devicetree/bindings/clock/clock-bindings.txt

>
>>
>> I am not sure I understand what specific drivers should need to carry
>> this "old hack" forward. More importantly, why is it preferable to carry
>> the hack forward rather than fixing the drivers.
>
> At least the GP timer seems to need this, and I don't want to touch /
> verify all the potential drivers touched by this so it is easier to
> provide a (semi) temporary tweak.

I see that GP timer nodes seem to be already device tree converted, at 
least I see the nodes in SoC.dtsi

Do we know what is going on for these that need these temporary devices? 
can we do a special node property for these?

I think the entire problem is coz of
timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); in case of 
even of_populated.

if we can get rid of usage of omap_hwmod_get_main_clk by catching them 
with [1], then we can force the drivers to pick up based on device node 
clocks= property.

It might be easier to fix 1 driver - timer, rather than introduce am33x, 
omap4, omap5 dra7 specific "SoC clk driver".

with that this entire patch becomes redundant.


[1]
diff --git a/arch/arm/mach-omap2/omap_hwmod.c 
b/arch/arm/mach-omap2/omap_hwmod.c
index da26659..2e90ab4 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -4153,5 +4153,10 @@ const char *omap_hwmod_get_main_clk(struct 
omap_hwmod *oh)
  	if (!oh)
  		return NULL;

+	if (!of_have_populated_dt()) {
+		WARN(1, "%s hwmod clk node read with OF?:FIXME!\n",
+		     oh->name);
+	}
+
  	return oh->main_clk;
  }
-- 
Regards,
Nishanth Menon

[PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Nishanth Menon]

On 07/31/2013 05:07 AM, Tero Kristo wrote:
> On 07/30/2013 09:40 PM, Nishanth Menon wrote:
>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>> Some devices require their clocks to be available with a specific
>>> dev-id con-id mapping. With DT, the clocks can be found by default
>>> only with their name, or alternatively through the device node of
>>> the consumer. With drivers, that don't support DT fully yet, add
>>> mechanism to register specific clock names.
>>>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>
>> with this, should it not be enough to add clocks=<&phandle>
>
> Don't know, I am not an expert on DT. :)

That is the usage - 
Documentation/devicetree/bindings/clock/clock-bindings.txt

>
>>
>> I am not sure I understand what specific drivers should need to carry
>> this "old hack" forward. More importantly, why is it preferable to carry
>> the hack forward rather than fixing the drivers.
>
> At least the GP timer seems to need this, and I don't want to touch /
> verify all the potential drivers touched by this so it is easier to
> provide a (semi) temporary tweak.

I see that GP timer nodes seem to be already device tree converted, at 
least I see the nodes in SoC.dtsi

Do we know what is going on for these that need these temporary devices? 
can we do a special node property for these?

I think the entire problem is coz of
timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); in case of 
even of_populated.

if we can get rid of usage of omap_hwmod_get_main_clk by catching them 
with [1], then we can force the drivers to pick up based on device node 
clocks= property.

It might be easier to fix 1 driver - timer, rather than introduce am33x, 
omap4, omap5 dra7 specific "SoC clk driver".

with that this entire patch becomes redundant.


[1]
diff --git a/arch/arm/mach-omap2/omap_hwmod.c 
b/arch/arm/mach-omap2/omap_hwmod.c
index da26659..2e90ab4 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -4153,5 +4153,10 @@ const char *omap_hwmod_get_main_clk(struct 
omap_hwmod *oh)
  	if (!oh)
  		return NULL;

+	if (!of_have_populated_dt()) {
+		WARN(1, "%s hwmod clk node read with OF?:FIXME!\n",
+		     oh->name);
+	}
+
  	return oh->main_clk;
  }
-- 
Regards,
Nishanth Menon

Re: [PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Tero Kristo]

On 08/01/2013 05:25 PM, Nishanth Menon wrote:
> On 07/31/2013 05:07 AM, Tero Kristo wrote:
>> On 07/30/2013 09:40 PM, Nishanth Menon wrote:
>>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>>> Some devices require their clocks to be available with a specific
>>>> dev-id con-id mapping. With DT, the clocks can be found by default
>>>> only with their name, or alternatively through the device node of
>>>> the consumer. With drivers, that don't support DT fully yet, add
>>>> mechanism to register specific clock names.
>>>>
>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>
>>> with this, should it not be enough to add clocks=<&phandle>
>>
>> Don't know, I am not an expert on DT. :)
>
> That is the usage -
> Documentation/devicetree/bindings/clock/clock-bindings.txt
>
>>
>>>
>>> I am not sure I understand what specific drivers should need to carry
>>> this "old hack" forward. More importantly, why is it preferable to carry
>>> the hack forward rather than fixing the drivers.
>>
>> At least the GP timer seems to need this, and I don't want to touch /
>> verify all the potential drivers touched by this so it is easier to
>> provide a (semi) temporary tweak.
>
> I see that GP timer nodes seem to be already device tree converted, at
> least I see the nodes in SoC.dtsi

Even if those exist, they don't seem to work. The kernel crashes without 
the alias nodes as of now.

>
> Do we know what is going on for these that need these temporary devices?
> can we do a special node property for these?
>
> I think the entire problem is coz of
> timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); in case of
> even of_populated.

I guess so, clk_get tries to look for improper clk which does not exist. 
Might be a bug with hwmod data.

>
> if we can get rid of usage of omap_hwmod_get_main_clk by catching them
> with [1], then we can force the drivers to pick up based on device node
> clocks= property.
>
> It might be easier to fix 1 driver - timer, rather than introduce am33x,
> omap4, omap5 dra7 specific "SoC clk driver".
>
> with that this entire patch becomes redundant.

It is not that simple. Looking at the architectures this set supports, I 
see clock alias nodes at least for following drivers:

- GPT timer
- USB
- DCAN
- EMAC
- VPFE
- UART
- SSI
- DSS
- security
- MMC
- MCBSP
- MCSPI

I am _not_ going to fix all of these during the initial phase. :P

But yes, eventually these should go away.

>
>
> [1]
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c
> b/arch/arm/mach-omap2/omap_hwmod.c
> index da26659..2e90ab4 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -4153,5 +4153,10 @@ const char *omap_hwmod_get_main_clk(struct
> omap_hwmod *oh)
>       if (!oh)
>           return NULL;
>
> +    if (!of_have_populated_dt()) {
> +        WARN(1, "%s hwmod clk node read with OF?:FIXME!\n",
> +             oh->name);
> +    }
> +
>       return oh->main_clk;
>   }

[PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Tero Kristo]

On 08/01/2013 05:25 PM, Nishanth Menon wrote:
> On 07/31/2013 05:07 AM, Tero Kristo wrote:
>> On 07/30/2013 09:40 PM, Nishanth Menon wrote:
>>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>>> Some devices require their clocks to be available with a specific
>>>> dev-id con-id mapping. With DT, the clocks can be found by default
>>>> only with their name, or alternatively through the device node of
>>>> the consumer. With drivers, that don't support DT fully yet, add
>>>> mechanism to register specific clock names.
>>>>
>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>
>>> with this, should it not be enough to add clocks=<&phandle>
>>
>> Don't know, I am not an expert on DT. :)
>
> That is the usage -
> Documentation/devicetree/bindings/clock/clock-bindings.txt
>
>>
>>>
>>> I am not sure I understand what specific drivers should need to carry
>>> this "old hack" forward. More importantly, why is it preferable to carry
>>> the hack forward rather than fixing the drivers.
>>
>> At least the GP timer seems to need this, and I don't want to touch /
>> verify all the potential drivers touched by this so it is easier to
>> provide a (semi) temporary tweak.
>
> I see that GP timer nodes seem to be already device tree converted, at
> least I see the nodes in SoC.dtsi

Even if those exist, they don't seem to work. The kernel crashes without 
the alias nodes as of now.

>
> Do we know what is going on for these that need these temporary devices?
> can we do a special node property for these?
>
> I think the entire problem is coz of
> timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); in case of
> even of_populated.

I guess so, clk_get tries to look for improper clk which does not exist. 
Might be a bug with hwmod data.

>
> if we can get rid of usage of omap_hwmod_get_main_clk by catching them
> with [1], then we can force the drivers to pick up based on device node
> clocks= property.
>
> It might be easier to fix 1 driver - timer, rather than introduce am33x,
> omap4, omap5 dra7 specific "SoC clk driver".
>
> with that this entire patch becomes redundant.

It is not that simple. Looking at the architectures this set supports, I 
see clock alias nodes at least for following drivers:

- GPT timer
- USB
- DCAN
- EMAC
- VPFE
- UART
- SSI
- DSS
- security
- MMC
- MCBSP
- MCSPI

I am _not_ going to fix all of these during the initial phase. :P

But yes, eventually these should go away.

>
>
> [1]
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c
> b/arch/arm/mach-omap2/omap_hwmod.c
> index da26659..2e90ab4 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -4153,5 +4153,10 @@ const char *omap_hwmod_get_main_clk(struct
> omap_hwmod *oh)
>       if (!oh)
>           return NULL;
>
> +    if (!of_have_populated_dt()) {
> +        WARN(1, "%s hwmod clk node read with OF?:FIXME!\n",
> +             oh->name);
> +    }
> +
>       return oh->main_clk;
>   }

Re: [PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Nishanth Menon]

On 08/01/2013 10:18 AM, Tero Kristo wrote:
> On 08/01/2013 05:25 PM, Nishanth Menon wrote:
>> On 07/31/2013 05:07 AM, Tero Kristo wrote:
>>> On 07/30/2013 09:40 PM, Nishanth Menon wrote:
>>>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
[..]
>> if we can get rid of usage of omap_hwmod_get_main_clk by catching them
>> with [1], then we can force the drivers to pick up based on device node
>> clocks= property.
>>
>> It might be easier to fix 1 driver - timer, rather than introduce am33x,
>> omap4, omap5 dra7 specific "SoC clk driver".
>>
>> with that this entire patch becomes redundant.
>
> It is not that simple. Looking at the architectures this set supports, I
> see clock alias nodes at least for following drivers:
>
> - GPT timer
> - USB
> - DCAN
> - EMAC
> - VPFE
> - UART
> - SSI
> - DSS
> - security
> - MMC
> - MCBSP
> - MCSPI
>
> I am _not_ going to fix all of these during the initial phase. :P
>
> But yes, eventually these should go away.

How many of these are needed to boot? what functionality do we expect 
with the series -> we can constraint saying that remaining drivers 
should fix themselves the right way, else dont have the feature - 
example cpufreq- fix it the right way, or wont see the feature enabled.

introducing a "way out" for all of these just invites more guys to screw 
around claiming "it was done before - see here"..

lets just fix the darned basic ones, refuse to provide "way out" and let 
the others fix themselves.

-- 
Regards,
Nishanth Menon

[PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Nishanth Menon]

On 08/01/2013 10:18 AM, Tero Kristo wrote:
> On 08/01/2013 05:25 PM, Nishanth Menon wrote:
>> On 07/31/2013 05:07 AM, Tero Kristo wrote:
>>> On 07/30/2013 09:40 PM, Nishanth Menon wrote:
>>>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
[..]
>> if we can get rid of usage of omap_hwmod_get_main_clk by catching them
>> with [1], then we can force the drivers to pick up based on device node
>> clocks= property.
>>
>> It might be easier to fix 1 driver - timer, rather than introduce am33x,
>> omap4, omap5 dra7 specific "SoC clk driver".
>>
>> with that this entire patch becomes redundant.
>
> It is not that simple. Looking at the architectures this set supports, I
> see clock alias nodes at least for following drivers:
>
> - GPT timer
> - USB
> - DCAN
> - EMAC
> - VPFE
> - UART
> - SSI
> - DSS
> - security
> - MMC
> - MCBSP
> - MCSPI
>
> I am _not_ going to fix all of these during the initial phase. :P
>
> But yes, eventually these should go away.

How many of these are needed to boot? what functionality do we expect 
with the series -> we can constraint saying that remaining drivers 
should fix themselves the right way, else dont have the feature - 
example cpufreq- fix it the right way, or wont see the feature enabled.

introducing a "way out" for all of these just invites more guys to screw 
around claiming "it was done before - see here"..

lets just fix the darned basic ones, refuse to provide "way out" and let 
the others fix themselves.

-- 
Regards,
Nishanth Menon

Re: [PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Tero Kristo]

On 08/01/2013 06:24 PM, Nishanth Menon wrote:
> On 08/01/2013 10:18 AM, Tero Kristo wrote:
>> On 08/01/2013 05:25 PM, Nishanth Menon wrote:
>>> On 07/31/2013 05:07 AM, Tero Kristo wrote:
>>>> On 07/30/2013 09:40 PM, Nishanth Menon wrote:
>>>>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
> [..]
>>> if we can get rid of usage of omap_hwmod_get_main_clk by catching them
>>> with [1], then we can force the drivers to pick up based on device node
>>> clocks= property.
>>>
>>> It might be easier to fix 1 driver - timer, rather than introduce am33x,
>>> omap4, omap5 dra7 specific "SoC clk driver".
>>>
>>> with that this entire patch becomes redundant.
>>
>> It is not that simple. Looking at the architectures this set supports, I
>> see clock alias nodes at least for following drivers:
>>
>> - GPT timer
>> - USB
>> - DCAN
>> - EMAC
>> - VPFE
>> - UART
>> - SSI
>> - DSS
>> - security
>> - MMC
>> - MCBSP
>> - MCSPI
>>
>> I am _not_ going to fix all of these during the initial phase. :P
>>
>> But yes, eventually these should go away.
>
> How many of these are needed to boot? what functionality do we expect
> with the series -> we can constraint saying that remaining drivers
> should fix themselves the right way, else dont have the feature -
> example cpufreq- fix it the right way, or wont see the feature enabled.
>
> introducing a "way out" for all of these just invites more guys to screw
> around claiming "it was done before - see here"..
>
> lets just fix the darned basic ones, refuse to provide "way out" and let
> the others fix themselves.
>

Yea, that would be one way. I guess someone like Tony should comment on 
this.

[PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Tero Kristo]

On 08/01/2013 06:24 PM, Nishanth Menon wrote:
> On 08/01/2013 10:18 AM, Tero Kristo wrote:
>> On 08/01/2013 05:25 PM, Nishanth Menon wrote:
>>> On 07/31/2013 05:07 AM, Tero Kristo wrote:
>>>> On 07/30/2013 09:40 PM, Nishanth Menon wrote:
>>>>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
> [..]
>>> if we can get rid of usage of omap_hwmod_get_main_clk by catching them
>>> with [1], then we can force the drivers to pick up based on device node
>>> clocks= property.
>>>
>>> It might be easier to fix 1 driver - timer, rather than introduce am33x,
>>> omap4, omap5 dra7 specific "SoC clk driver".
>>>
>>> with that this entire patch becomes redundant.
>>
>> It is not that simple. Looking at the architectures this set supports, I
>> see clock alias nodes at least for following drivers:
>>
>> - GPT timer
>> - USB
>> - DCAN
>> - EMAC
>> - VPFE
>> - UART
>> - SSI
>> - DSS
>> - security
>> - MMC
>> - MCBSP
>> - MCSPI
>>
>> I am _not_ going to fix all of these during the initial phase. :P
>>
>> But yes, eventually these should go away.
>
> How many of these are needed to boot? what functionality do we expect
> with the series -> we can constraint saying that remaining drivers
> should fix themselves the right way, else dont have the feature -
> example cpufreq- fix it the right way, or wont see the feature enabled.
>
> introducing a "way out" for all of these just invites more guys to screw
> around claiming "it was done before - see here"..
>
> lets just fix the darned basic ones, refuse to provide "way out" and let
> the others fix themselves.
>

Yea, that would be one way. I guess someone like Tony should comment on 
this.

Re: [PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [130801 08:37]:
> On 08/01/2013 06:24 PM, Nishanth Menon wrote:
> >On 08/01/2013 10:18 AM, Tero Kristo wrote:
> >>On 08/01/2013 05:25 PM, Nishanth Menon wrote:
> >>>On 07/31/2013 05:07 AM, Tero Kristo wrote:
> >>>>On 07/30/2013 09:40 PM, Nishanth Menon wrote:
> >>>>>On 07/23/2013 02:20 AM, Tero Kristo wrote:
> >[..]
> >>>if we can get rid of usage of omap_hwmod_get_main_clk by catching them
> >>>with [1], then we can force the drivers to pick up based on device node
> >>>clocks= property.
> >>>
> >>>It might be easier to fix 1 driver - timer, rather than introduce am33x,
> >>>omap4, omap5 dra7 specific "SoC clk driver".
> >>>
> >>>with that this entire patch becomes redundant.
> >>
> >>It is not that simple. Looking at the architectures this set supports, I
> >>see clock alias nodes at least for following drivers:
> >>
> >>- GPT timer
> >>- USB
> >>- DCAN
> >>- EMAC
> >>- VPFE
> >>- UART
> >>- SSI
> >>- DSS
> >>- security
> >>- MMC
> >>- MCBSP
> >>- MCSPI
> >>
> >>I am _not_ going to fix all of these during the initial phase. :P
> >>
> >>But yes, eventually these should go away.
> >
> >How many of these are needed to boot? what functionality do we expect
> >with the series -> we can constraint saying that remaining drivers
> >should fix themselves the right way, else dont have the feature -
> >example cpufreq- fix it the right way, or wont see the feature enabled.
> >
> >introducing a "way out" for all of these just invites more guys to screw
> >around claiming "it was done before - see here"..
> >
> >lets just fix the darned basic ones, refuse to provide "way out" and let
> >the others fix themselves.
> >
> 
> Yea, that would be one way. I guess someone like Tony should comment
> on this.

Well how about add some dev_warns so we can keep things working and
know which ones to fix? Otherwise it seems that things will not work
properly for many devices.

Regards,

Tony

[PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [130801 08:37]:
> On 08/01/2013 06:24 PM, Nishanth Menon wrote:
> >On 08/01/2013 10:18 AM, Tero Kristo wrote:
> >>On 08/01/2013 05:25 PM, Nishanth Menon wrote:
> >>>On 07/31/2013 05:07 AM, Tero Kristo wrote:
> >>>>On 07/30/2013 09:40 PM, Nishanth Menon wrote:
> >>>>>On 07/23/2013 02:20 AM, Tero Kristo wrote:
> >[..]
> >>>if we can get rid of usage of omap_hwmod_get_main_clk by catching them
> >>>with [1], then we can force the drivers to pick up based on device node
> >>>clocks= property.
> >>>
> >>>It might be easier to fix 1 driver - timer, rather than introduce am33x,
> >>>omap4, omap5 dra7 specific "SoC clk driver".
> >>>
> >>>with that this entire patch becomes redundant.
> >>
> >>It is not that simple. Looking at the architectures this set supports, I
> >>see clock alias nodes at least for following drivers:
> >>
> >>- GPT timer
> >>- USB
> >>- DCAN
> >>- EMAC
> >>- VPFE
> >>- UART
> >>- SSI
> >>- DSS
> >>- security
> >>- MMC
> >>- MCBSP
> >>- MCSPI
> >>
> >>I am _not_ going to fix all of these during the initial phase. :P
> >>
> >>But yes, eventually these should go away.
> >
> >How many of these are needed to boot? what functionality do we expect
> >with the series -> we can constraint saying that remaining drivers
> >should fix themselves the right way, else dont have the feature -
> >example cpufreq- fix it the right way, or wont see the feature enabled.
> >
> >introducing a "way out" for all of these just invites more guys to screw
> >around claiming "it was done before - see here"..
> >
> >lets just fix the darned basic ones, refuse to provide "way out" and let
> >the others fix themselves.
> >
> 
> Yea, that would be one way. I guess someone like Tony should comment
> on this.

Well how about add some dev_warns so we can keep things working and
know which ones to fix? Otherwise it seems that things will not work
properly for many devices.

Regards,

Tony

[PATCHv4 06/33] CLK: omap: add autoidle support

[Tero Kristo]

OMAP clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.c |    6 ++
 drivers/clk/omap/Makefile   |    2 +-
 drivers/clk/omap/autoidle.c |  130 +++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/omap/clk.c      |    4 +-
 include/linux/clk/omap.h    |    4 ++
 5 files changed, 143 insertions(+), 3 deletions(-)
 create mode 100644 drivers/clk/omap/autoidle.c

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 0c38ca9..669d4c4 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
 	list_for_each_entry(c, &clk_hw_omap_clocks, node)
 		if (c->ops && c->ops->allow_idle)
 			c->ops->allow_idle(c);
+
+	of_omap_clk_allow_autoidle_all();
+
 	return 0;
 }
 
@@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
 	list_for_each_entry(c, &clk_hw_omap_clocks, node)
 		if (c->ops && c->ops->deny_idle)
 			c->ops->deny_idle(c);
+
+	of_omap_clk_deny_autoidle_all();
+
 	return 0;
 }
 
diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index 4cad480..ca56700 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1 +1 @@
-obj-y					+= clk.o dpll.o
+obj-y					+= clk.o dpll.o autoidle.o
diff --git a/drivers/clk/omap/autoidle.c b/drivers/clk/omap/autoidle.c
new file mode 100644
index 0000000..6424cb2
--- /dev/null
+++ b/drivers/clk/omap/autoidle.c
@@ -0,0 +1,130 @@
+/*
+ * OMAP clock autoidle support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#ifdef CONFIG_OF
+struct clk_omap_autoidle {
+	void __iomem		*reg;
+	u8			shift;
+	u8			flags;
+	const char		*name;
+	struct list_head	node;
+};
+
+#define AUTOIDLE_LOW		0x1
+
+static LIST_HEAD(autoidle_clks);
+
+static void omap_allow_autoidle(struct clk_omap_autoidle *clk)
+{
+	u32 val;
+
+	val = readl(clk->reg);
+
+	if (clk->flags & AUTOIDLE_LOW)
+		val &= ~(1 << clk->shift);
+	else
+		val |= (1 << clk->shift);
+
+	writel(val, clk->reg);
+}
+
+static void omap_deny_autoidle(struct clk_omap_autoidle *clk)
+{
+	u32 val;
+
+	val = readl(clk->reg);
+
+	if (clk->flags & AUTOIDLE_LOW)
+		val |= (1 << clk->shift);
+	else
+		val &= ~(1 << clk->shift);
+
+	writel(val, clk->reg);
+}
+
+void of_omap_clk_allow_autoidle_all(void)
+{
+	struct clk_omap_autoidle *c;
+
+	list_for_each_entry(c, &autoidle_clks, node)
+		omap_allow_autoidle(c);
+}
+
+void of_omap_clk_deny_autoidle_all(void)
+{
+	struct clk_omap_autoidle *c;
+
+	list_for_each_entry(c, &autoidle_clks, node)
+		omap_deny_autoidle(c);
+}
+
+static __init void of_omap_autoidle_setup(struct device_node *node)
+{
+	u32 shift;
+	void __iomem *reg;
+	struct clk_omap_autoidle *clk;
+
+	if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
+		return;
+
+	reg = of_iomap(node, 0);
+
+	clk = kzalloc(sizeof(struct clk_omap_autoidle), GFP_KERNEL);
+
+	if (!clk) {
+		pr_err("%s: kzalloc failed\n", __func__);
+		return;
+	}
+
+	clk->shift = shift;
+	clk->name = node->name;
+	clk->reg = reg;
+
+	if (of_property_read_bool(node, "ti,autoidle-low"))
+		clk->flags |= AUTOIDLE_LOW;
+
+	list_add(&clk->node, &autoidle_clks);
+}
+
+void __init of_omap_divider_setup(struct device_node *node)
+{
+	of_divider_clk_setup(node);
+	of_omap_autoidle_setup(node);
+}
+EXPORT_SYMBOL_GPL(of_omap_divider_setup);
+CLK_OF_DECLARE(omap_autoidle_clock, "divider-clock", of_omap_divider_setup);
+
+void __init of_omap_fixed_factor_setup(struct device_node *node)
+{
+	of_fixed_factor_clk_setup(node);
+	of_omap_autoidle_setup(node);
+}
+EXPORT_SYMBOL_GPL(of_omap_fixed_factor_setup);
+CLK_OF_DECLARE(omap_fixed_factor_clock, "fixed-factor-clock",
+	of_omap_fixed_factor_setup);
+
+#endif
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index cd31a81..c149097 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -25,8 +25,8 @@ static const struct of_device_id clk_match[] = {
 	{.compatible = "fixed-clock", .data = of_fixed_clk_setup, },
 	{.compatible = "mux-clock", .data = of_mux_clk_setup, },
 	{.compatible = "fixed-factor-clock",
-		.data = of_fixed_factor_clk_setup, },
-	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
+		.data = of_omap_fixed_factor_setup, },
+	{.compatible = "divider-clock", .data = of_omap_divider_setup, },
 	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
 	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
 	{},
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index c39e775..904bdad 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -192,5 +192,9 @@ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 int dt_omap_clk_init(void);
 extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
 void of_omap4_dpll_setup(struct device_node *node);
+void of_omap_fixed_factor_setup(struct device_node *node);
+void of_omap_divider_setup(struct device_node *node);
+void of_omap_clk_allow_autoidle_all(void);
+void of_omap_clk_deny_autoidle_all(void);
 
 #endif
-- 
1.7.9.5

[PATCHv4 06/33] CLK: omap: add autoidle support

[Tero Kristo]

OMAP clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.c |    6 ++
 drivers/clk/omap/Makefile   |    2 +-
 drivers/clk/omap/autoidle.c |  130 +++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/omap/clk.c      |    4 +-
 include/linux/clk/omap.h    |    4 ++
 5 files changed, 143 insertions(+), 3 deletions(-)
 create mode 100644 drivers/clk/omap/autoidle.c

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 0c38ca9..669d4c4 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
 	list_for_each_entry(c, &clk_hw_omap_clocks, node)
 		if (c->ops && c->ops->allow_idle)
 			c->ops->allow_idle(c);
+
+	of_omap_clk_allow_autoidle_all();
+
 	return 0;
 }
 
@@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
 	list_for_each_entry(c, &clk_hw_omap_clocks, node)
 		if (c->ops && c->ops->deny_idle)
 			c->ops->deny_idle(c);
+
+	of_omap_clk_deny_autoidle_all();
+
 	return 0;
 }
 
diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index 4cad480..ca56700 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1 +1 @@
-obj-y					+= clk.o dpll.o
+obj-y					+= clk.o dpll.o autoidle.o
diff --git a/drivers/clk/omap/autoidle.c b/drivers/clk/omap/autoidle.c
new file mode 100644
index 0000000..6424cb2
--- /dev/null
+++ b/drivers/clk/omap/autoidle.c
@@ -0,0 +1,130 @@
+/*
+ * OMAP clock autoidle support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#ifdef CONFIG_OF
+struct clk_omap_autoidle {
+	void __iomem		*reg;
+	u8			shift;
+	u8			flags;
+	const char		*name;
+	struct list_head	node;
+};
+
+#define AUTOIDLE_LOW		0x1
+
+static LIST_HEAD(autoidle_clks);
+
+static void omap_allow_autoidle(struct clk_omap_autoidle *clk)
+{
+	u32 val;
+
+	val = readl(clk->reg);
+
+	if (clk->flags & AUTOIDLE_LOW)
+		val &= ~(1 << clk->shift);
+	else
+		val |= (1 << clk->shift);
+
+	writel(val, clk->reg);
+}
+
+static void omap_deny_autoidle(struct clk_omap_autoidle *clk)
+{
+	u32 val;
+
+	val = readl(clk->reg);
+
+	if (clk->flags & AUTOIDLE_LOW)
+		val |= (1 << clk->shift);
+	else
+		val &= ~(1 << clk->shift);
+
+	writel(val, clk->reg);
+}
+
+void of_omap_clk_allow_autoidle_all(void)
+{
+	struct clk_omap_autoidle *c;
+
+	list_for_each_entry(c, &autoidle_clks, node)
+		omap_allow_autoidle(c);
+}
+
+void of_omap_clk_deny_autoidle_all(void)
+{
+	struct clk_omap_autoidle *c;
+
+	list_for_each_entry(c, &autoidle_clks, node)
+		omap_deny_autoidle(c);
+}
+
+static __init void of_omap_autoidle_setup(struct device_node *node)
+{
+	u32 shift;
+	void __iomem *reg;
+	struct clk_omap_autoidle *clk;
+
+	if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
+		return;
+
+	reg = of_iomap(node, 0);
+
+	clk = kzalloc(sizeof(struct clk_omap_autoidle), GFP_KERNEL);
+
+	if (!clk) {
+		pr_err("%s: kzalloc failed\n", __func__);
+		return;
+	}
+
+	clk->shift = shift;
+	clk->name = node->name;
+	clk->reg = reg;
+
+	if (of_property_read_bool(node, "ti,autoidle-low"))
+		clk->flags |= AUTOIDLE_LOW;
+
+	list_add(&clk->node, &autoidle_clks);
+}
+
+void __init of_omap_divider_setup(struct device_node *node)
+{
+	of_divider_clk_setup(node);
+	of_omap_autoidle_setup(node);
+}
+EXPORT_SYMBOL_GPL(of_omap_divider_setup);
+CLK_OF_DECLARE(omap_autoidle_clock, "divider-clock", of_omap_divider_setup);
+
+void __init of_omap_fixed_factor_setup(struct device_node *node)
+{
+	of_fixed_factor_clk_setup(node);
+	of_omap_autoidle_setup(node);
+}
+EXPORT_SYMBOL_GPL(of_omap_fixed_factor_setup);
+CLK_OF_DECLARE(omap_fixed_factor_clock, "fixed-factor-clock",
+	of_omap_fixed_factor_setup);
+
+#endif
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index cd31a81..c149097 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -25,8 +25,8 @@ static const struct of_device_id clk_match[] = {
 	{.compatible = "fixed-clock", .data = of_fixed_clk_setup, },
 	{.compatible = "mux-clock", .data = of_mux_clk_setup, },
 	{.compatible = "fixed-factor-clock",
-		.data = of_fixed_factor_clk_setup, },
-	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
+		.data = of_omap_fixed_factor_setup, },
+	{.compatible = "divider-clock", .data = of_omap_divider_setup, },
 	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
 	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
 	{},
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index c39e775..904bdad 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -192,5 +192,9 @@ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 int dt_omap_clk_init(void);
 extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
 void of_omap4_dpll_setup(struct device_node *node);
+void of_omap_fixed_factor_setup(struct device_node *node);
+void of_omap_divider_setup(struct device_node *node);
+void of_omap_clk_allow_autoidle_all(void);
+void of_omap_clk_deny_autoidle_all(void);
 
 #endif
-- 
1.7.9.5

Re: [PATCHv4 06/33] CLK: omap: add autoidle support

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> OMAP clk driver now routes some of the basic clocks through own
> registration routine to allow autoidle support. This routine just
> checks a couple of device node properties and adds autoidle support
> if required, and just passes the registration forward to basic clocks.

why not extend standard framework to support autoidle capable clocks OR 
introduce our own clk node which depends on basic clocks?
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   arch/arm/mach-omap2/clock.c |    6 ++
>   drivers/clk/omap/Makefile   |    2 +-
>   drivers/clk/omap/autoidle.c |  130 +++++++++++++++++++++++++++++++++++++++++++
>   drivers/clk/omap/clk.c      |    4 +-
>   include/linux/clk/omap.h    |    4 ++
>   5 files changed, 143 insertions(+), 3 deletions(-)
>   create mode 100644 drivers/clk/omap/autoidle.c

I know it is getting a little stale, but anyways, device tree binding 
missing.

>
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index 0c38ca9..669d4c4 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
Not sure why, at this point in time we are going to calling drivers/clk 
code.

> @@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
>   	list_for_each_entry(c, &clk_hw_omap_clocks, node)
>   		if (c->ops && c->ops->allow_idle)
>   			c->ops->allow_idle(c);
> +
> +	of_omap_clk_allow_autoidle_all();
> +
>   	return 0;
>   }
>
> @@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
>   	list_for_each_entry(c, &clk_hw_omap_clocks, node)
>   		if (c->ops && c->ops->deny_idle)
>   			c->ops->deny_idle(c);
> +
> +	of_omap_clk_deny_autoidle_all();
> +

these are defined for CONFIG_OF.. anyways, without dt nodes (OMAP3 is 
supposed to support non-DT boot even now), this would not work, would it?


>   	return 0;
>   }
>
> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
> index 4cad480..ca56700 100644
> --- a/drivers/clk/omap/Makefile
> +++ b/drivers/clk/omap/Makefile
> @@ -1 +1 @@
> -obj-y					+= clk.o dpll.o
> +obj-y					+= clk.o dpll.o autoidle.o
> diff --git a/drivers/clk/omap/autoidle.c b/drivers/clk/omap/autoidle.c
> new file mode 100644
> index 0000000..6424cb2
> --- /dev/null
> +++ b/drivers/clk/omap/autoidle.c
> @@ -0,0 +1,130 @@
> +/*
> + * OMAP clock autoidle support
> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * Tero Kristo <t-kristo@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/string.h>
> +#include <linux/log2.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
at all of these required?

> +
> +#ifdef CONFIG_OF
> +struct clk_omap_autoidle {
> +	void __iomem		*reg;
> +	u8			shift;
> +	u8			flags;
> +	const char		*name;
> +	struct list_head	node;
> +};
> +
> +#define AUTOIDLE_LOW		0x1
> +
> +static LIST_HEAD(autoidle_clks);
> +
> +static void omap_allow_autoidle(struct clk_omap_autoidle *clk)
> +{
> +	u32 val;
> +
> +	val = readl(clk->reg);
> +
> +	if (clk->flags & AUTOIDLE_LOW)
> +		val &= ~(1 << clk->shift);
> +	else
> +		val |= (1 << clk->shift);
> +
> +	writel(val, clk->reg);
> +}
> +
> +static void omap_deny_autoidle(struct clk_omap_autoidle *clk)
> +{
> +	u32 val;
> +
> +	val = readl(clk->reg);
> +
> +	if (clk->flags & AUTOIDLE_LOW)
> +		val |= (1 << clk->shift);
> +	else
> +		val &= ~(1 << clk->shift);
> +
> +	writel(val, clk->reg);
> +}
> +
> +void of_omap_clk_allow_autoidle_all(void)
> +{
> +	struct clk_omap_autoidle *c;
> +
> +	list_for_each_entry(c, &autoidle_clks, node)
> +		omap_allow_autoidle(c);
> +}
> +
> +void of_omap_clk_deny_autoidle_all(void)
> +{
> +	struct clk_omap_autoidle *c;
> +
> +	list_for_each_entry(c, &autoidle_clks, node)
> +		omap_deny_autoidle(c);
> +}
> +
> +static __init void of_omap_autoidle_setup(struct device_node *node)
> +{
> +	u32 shift;
> +	void __iomem *reg;
> +	struct clk_omap_autoidle *clk;
> +
> +	if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
> +		return;
> +
> +	reg = of_iomap(node, 0);
> +
> +	clk = kzalloc(sizeof(struct clk_omap_autoidle), GFP_KERNEL);
> +
> +	if (!clk) {
> +		pr_err("%s: kzalloc failed\n", __func__);
> +		return;
> +	}
> +
> +	clk->shift = shift;
> +	clk->name = node->name;
> +	clk->reg = reg;
> +
> +	if (of_property_read_bool(node, "ti,autoidle-low"))
> +		clk->flags |= AUTOIDLE_LOW;
> +
> +	list_add(&clk->node, &autoidle_clks);
> +}
> +
> +void __init of_omap_divider_setup(struct device_node *node)
> +{
> +	of_divider_clk_setup(node);
> +	of_omap_autoidle_setup(node);
> +}
> +EXPORT_SYMBOL_GPL(of_omap_divider_setup);
> +CLK_OF_DECLARE(omap_autoidle_clock, "divider-clock", of_omap_divider_setup);

This is overriding drivers/clk/clk-divider.c ?
> +
> +void __init of_omap_fixed_factor_setup(struct device_node *node)
> +{
> +	of_fixed_factor_clk_setup(node);
> +	of_omap_autoidle_setup(node);
> +}
> +EXPORT_SYMBOL_GPL(of_omap_fixed_factor_setup);
> +CLK_OF_DECLARE(omap_fixed_factor_clock, "fixed-factor-clock",
> +	of_omap_fixed_factor_setup);

This is overriding drivers/clk/clk-fixed-factor.c ?
> +
> +#endif
> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
> index cd31a81..c149097 100644
> --- a/drivers/clk/omap/clk.c
> +++ b/drivers/clk/omap/clk.c
> @@ -25,8 +25,8 @@ static const struct of_device_id clk_match[] = {
>   	{.compatible = "fixed-clock", .data = of_fixed_clk_setup, },
>   	{.compatible = "mux-clock", .data = of_mux_clk_setup, },
>   	{.compatible = "fixed-factor-clock",
> -		.data = of_fixed_factor_clk_setup, },
> -	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
> +		.data = of_omap_fixed_factor_setup, },
> +	{.compatible = "divider-clock", .data = of_omap_divider_setup, },
>   	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
>   	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
>   	{},
> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
> index c39e775..904bdad 100644
> --- a/include/linux/clk/omap.h
> +++ b/include/linux/clk/omap.h
> @@ -192,5 +192,9 @@ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
>   int dt_omap_clk_init(void);
>   extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
>   void of_omap4_dpll_setup(struct device_node *node);
> +void of_omap_fixed_factor_setup(struct device_node *node);
> +void of_omap_divider_setup(struct device_node *node);
> +void of_omap_clk_allow_autoidle_all(void);
> +void of_omap_clk_deny_autoidle_all(void);
>
>   #endif
>

I personally dont prefer the fact that divider-clock and 
fixed-rate-clock now has double meaning - building a multi-arch kernel 
for example, this can wreak havoc. standard definitions should not be 
monkeyed around with thus if avoidable, and in this case, very much 
avoidable.

just my 2 cents.
-- 
Regards,
Nishanth Menon

[PATCHv4 06/33] CLK: omap: add autoidle support

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> OMAP clk driver now routes some of the basic clocks through own
> registration routine to allow autoidle support. This routine just
> checks a couple of device node properties and adds autoidle support
> if required, and just passes the registration forward to basic clocks.

why not extend standard framework to support autoidle capable clocks OR 
introduce our own clk node which depends on basic clocks?
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   arch/arm/mach-omap2/clock.c |    6 ++
>   drivers/clk/omap/Makefile   |    2 +-
>   drivers/clk/omap/autoidle.c |  130 +++++++++++++++++++++++++++++++++++++++++++
>   drivers/clk/omap/clk.c      |    4 +-
>   include/linux/clk/omap.h    |    4 ++
>   5 files changed, 143 insertions(+), 3 deletions(-)
>   create mode 100644 drivers/clk/omap/autoidle.c

I know it is getting a little stale, but anyways, device tree binding 
missing.

>
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index 0c38ca9..669d4c4 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
Not sure why, at this point in time we are going to calling drivers/clk 
code.

> @@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
>   	list_for_each_entry(c, &clk_hw_omap_clocks, node)
>   		if (c->ops && c->ops->allow_idle)
>   			c->ops->allow_idle(c);
> +
> +	of_omap_clk_allow_autoidle_all();
> +
>   	return 0;
>   }
>
> @@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
>   	list_for_each_entry(c, &clk_hw_omap_clocks, node)
>   		if (c->ops && c->ops->deny_idle)
>   			c->ops->deny_idle(c);
> +
> +	of_omap_clk_deny_autoidle_all();
> +

these are defined for CONFIG_OF.. anyways, without dt nodes (OMAP3 is 
supposed to support non-DT boot even now), this would not work, would it?


>   	return 0;
>   }
>
> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
> index 4cad480..ca56700 100644
> --- a/drivers/clk/omap/Makefile
> +++ b/drivers/clk/omap/Makefile
> @@ -1 +1 @@
> -obj-y					+= clk.o dpll.o
> +obj-y					+= clk.o dpll.o autoidle.o
> diff --git a/drivers/clk/omap/autoidle.c b/drivers/clk/omap/autoidle.c
> new file mode 100644
> index 0000000..6424cb2
> --- /dev/null
> +++ b/drivers/clk/omap/autoidle.c
> @@ -0,0 +1,130 @@
> +/*
> + * OMAP clock autoidle support
> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * Tero Kristo <t-kristo@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/string.h>
> +#include <linux/log2.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
at all of these required?

> +
> +#ifdef CONFIG_OF
> +struct clk_omap_autoidle {
> +	void __iomem		*reg;
> +	u8			shift;
> +	u8			flags;
> +	const char		*name;
> +	struct list_head	node;
> +};
> +
> +#define AUTOIDLE_LOW		0x1
> +
> +static LIST_HEAD(autoidle_clks);
> +
> +static void omap_allow_autoidle(struct clk_omap_autoidle *clk)
> +{
> +	u32 val;
> +
> +	val = readl(clk->reg);
> +
> +	if (clk->flags & AUTOIDLE_LOW)
> +		val &= ~(1 << clk->shift);
> +	else
> +		val |= (1 << clk->shift);
> +
> +	writel(val, clk->reg);
> +}
> +
> +static void omap_deny_autoidle(struct clk_omap_autoidle *clk)
> +{
> +	u32 val;
> +
> +	val = readl(clk->reg);
> +
> +	if (clk->flags & AUTOIDLE_LOW)
> +		val |= (1 << clk->shift);
> +	else
> +		val &= ~(1 << clk->shift);
> +
> +	writel(val, clk->reg);
> +}
> +
> +void of_omap_clk_allow_autoidle_all(void)
> +{
> +	struct clk_omap_autoidle *c;
> +
> +	list_for_each_entry(c, &autoidle_clks, node)
> +		omap_allow_autoidle(c);
> +}
> +
> +void of_omap_clk_deny_autoidle_all(void)
> +{
> +	struct clk_omap_autoidle *c;
> +
> +	list_for_each_entry(c, &autoidle_clks, node)
> +		omap_deny_autoidle(c);
> +}
> +
> +static __init void of_omap_autoidle_setup(struct device_node *node)
> +{
> +	u32 shift;
> +	void __iomem *reg;
> +	struct clk_omap_autoidle *clk;
> +
> +	if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
> +		return;
> +
> +	reg = of_iomap(node, 0);
> +
> +	clk = kzalloc(sizeof(struct clk_omap_autoidle), GFP_KERNEL);
> +
> +	if (!clk) {
> +		pr_err("%s: kzalloc failed\n", __func__);
> +		return;
> +	}
> +
> +	clk->shift = shift;
> +	clk->name = node->name;
> +	clk->reg = reg;
> +
> +	if (of_property_read_bool(node, "ti,autoidle-low"))
> +		clk->flags |= AUTOIDLE_LOW;
> +
> +	list_add(&clk->node, &autoidle_clks);
> +}
> +
> +void __init of_omap_divider_setup(struct device_node *node)
> +{
> +	of_divider_clk_setup(node);
> +	of_omap_autoidle_setup(node);
> +}
> +EXPORT_SYMBOL_GPL(of_omap_divider_setup);
> +CLK_OF_DECLARE(omap_autoidle_clock, "divider-clock", of_omap_divider_setup);

This is overriding drivers/clk/clk-divider.c ?
> +
> +void __init of_omap_fixed_factor_setup(struct device_node *node)
> +{
> +	of_fixed_factor_clk_setup(node);
> +	of_omap_autoidle_setup(node);
> +}
> +EXPORT_SYMBOL_GPL(of_omap_fixed_factor_setup);
> +CLK_OF_DECLARE(omap_fixed_factor_clock, "fixed-factor-clock",
> +	of_omap_fixed_factor_setup);

This is overriding drivers/clk/clk-fixed-factor.c ?
> +
> +#endif
> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
> index cd31a81..c149097 100644
> --- a/drivers/clk/omap/clk.c
> +++ b/drivers/clk/omap/clk.c
> @@ -25,8 +25,8 @@ static const struct of_device_id clk_match[] = {
>   	{.compatible = "fixed-clock", .data = of_fixed_clk_setup, },
>   	{.compatible = "mux-clock", .data = of_mux_clk_setup, },
>   	{.compatible = "fixed-factor-clock",
> -		.data = of_fixed_factor_clk_setup, },
> -	{.compatible = "divider-clock", .data = of_divider_clk_setup, },
> +		.data = of_omap_fixed_factor_setup, },
> +	{.compatible = "divider-clock", .data = of_omap_divider_setup, },
>   	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
>   	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
>   	{},
> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
> index c39e775..904bdad 100644
> --- a/include/linux/clk/omap.h
> +++ b/include/linux/clk/omap.h
> @@ -192,5 +192,9 @@ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
>   int dt_omap_clk_init(void);
>   extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
>   void of_omap4_dpll_setup(struct device_node *node);
> +void of_omap_fixed_factor_setup(struct device_node *node);
> +void of_omap_divider_setup(struct device_node *node);
> +void of_omap_clk_allow_autoidle_all(void);
> +void of_omap_clk_deny_autoidle_all(void);
>
>   #endif
>

I personally dont prefer the fact that divider-clock and 
fixed-rate-clock now has double meaning - building a multi-arch kernel 
for example, this can wreak havoc. standard definitions should not be 
monkeyed around with thus if avoidable, and in this case, very much 
avoidable.

just my 2 cents.
-- 
Regards,
Nishanth Menon

Re: [PATCHv4 06/33] CLK: omap: add autoidle support

[Tero Kristo]

On 07/30/2013 09:56 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> OMAP clk driver now routes some of the basic clocks through own
>> registration routine to allow autoidle support. This routine just
>> checks a couple of device node properties and adds autoidle support
>> if required, and just passes the registration forward to basic clocks.
>
> why not extend standard framework to support autoidle capable clocks OR
> introduce our own clk node which depends on basic clocks?

Was kind of easier this way.

>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   arch/arm/mach-omap2/clock.c |    6 ++
>>   drivers/clk/omap/Makefile   |    2 +-
>>   drivers/clk/omap/autoidle.c |  130
>> +++++++++++++++++++++++++++++++++++++++++++
>>   drivers/clk/omap/clk.c      |    4 +-
>>   include/linux/clk/omap.h    |    4 ++
>>   5 files changed, 143 insertions(+), 3 deletions(-)
>>   create mode 100644 drivers/clk/omap/autoidle.c
>
> I know it is getting a little stale, but anyways, device tree binding
> missing.
>
>>
>> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
>> index 0c38ca9..669d4c4 100644
>> --- a/arch/arm/mach-omap2/clock.c
>> +++ b/arch/arm/mach-omap2/clock.c
> Not sure why, at this point in time we are going to calling drivers/clk
> code.
>
>> @@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
>>       list_for_each_entry(c, &clk_hw_omap_clocks, node)
>>           if (c->ops && c->ops->allow_idle)
>>               c->ops->allow_idle(c);
>> +
>> +    of_omap_clk_allow_autoidle_all();
>> +
>>       return 0;
>>   }
>>
>> @@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
>>       list_for_each_entry(c, &clk_hw_omap_clocks, node)
>>           if (c->ops && c->ops->deny_idle)
>>               c->ops->deny_idle(c);
>> +
>> +    of_omap_clk_deny_autoidle_all();
>> +
>
> these are defined for CONFIG_OF.. anyways, without dt nodes (OMAP3 is
> supposed to support non-DT boot even now), this would not work, would it?

The lists are empty so the funcs do nothing. However, dropping CONFIG_OF 
would break these of course. Will figure out a fix for this.

The calls are needed for the transition phase until we can move more clk 
stuff from mach-omap2 to drivers.

>
>
>>       return 0;
>>   }
>>
>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>> index 4cad480..ca56700 100644
>> --- a/drivers/clk/omap/Makefile
>> +++ b/drivers/clk/omap/Makefile
>> @@ -1 +1 @@
>> -obj-y                    += clk.o dpll.o
>> +obj-y                    += clk.o dpll.o autoidle.o
>> diff --git a/drivers/clk/omap/autoidle.c b/drivers/clk/omap/autoidle.c
>> new file mode 100644
>> index 0000000..6424cb2
>> --- /dev/null
>> +++ b/drivers/clk/omap/autoidle.c
>> @@ -0,0 +1,130 @@
>> +/*
>> + * OMAP clock autoidle support
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * Tero Kristo <t-kristo@ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +#include <linux/string.h>
>> +#include <linux/log2.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
> at all of these required?

I'll double check.

>
>> +
>> +#ifdef CONFIG_OF
>> +struct clk_omap_autoidle {
>> +    void __iomem        *reg;
>> +    u8            shift;
>> +    u8            flags;
>> +    const char        *name;
>> +    struct list_head    node;
>> +};
>> +
>> +#define AUTOIDLE_LOW        0x1
>> +
>> +static LIST_HEAD(autoidle_clks);
>> +
>> +static void omap_allow_autoidle(struct clk_omap_autoidle *clk)
>> +{
>> +    u32 val;
>> +
>> +    val = readl(clk->reg);
>> +
>> +    if (clk->flags & AUTOIDLE_LOW)
>> +        val &= ~(1 << clk->shift);
>> +    else
>> +        val |= (1 << clk->shift);
>> +
>> +    writel(val, clk->reg);
>> +}
>> +
>> +static void omap_deny_autoidle(struct clk_omap_autoidle *clk)
>> +{
>> +    u32 val;
>> +
>> +    val = readl(clk->reg);
>> +
>> +    if (clk->flags & AUTOIDLE_LOW)
>> +        val |= (1 << clk->shift);
>> +    else
>> +        val &= ~(1 << clk->shift);
>> +
>> +    writel(val, clk->reg);
>> +}
>> +
>> +void of_omap_clk_allow_autoidle_all(void)
>> +{
>> +    struct clk_omap_autoidle *c;
>> +
>> +    list_for_each_entry(c, &autoidle_clks, node)
>> +        omap_allow_autoidle(c);
>> +}
>> +
>> +void of_omap_clk_deny_autoidle_all(void)
>> +{
>> +    struct clk_omap_autoidle *c;
>> +
>> +    list_for_each_entry(c, &autoidle_clks, node)
>> +        omap_deny_autoidle(c);
>> +}
>> +
>> +static __init void of_omap_autoidle_setup(struct device_node *node)
>> +{
>> +    u32 shift;
>> +    void __iomem *reg;
>> +    struct clk_omap_autoidle *clk;
>> +
>> +    if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
>> +        return;
>> +
>> +    reg = of_iomap(node, 0);
>> +
>> +    clk = kzalloc(sizeof(struct clk_omap_autoidle), GFP_KERNEL);
>> +
>> +    if (!clk) {
>> +        pr_err("%s: kzalloc failed\n", __func__);
>> +        return;
>> +    }
>> +
>> +    clk->shift = shift;
>> +    clk->name = node->name;
>> +    clk->reg = reg;
>> +
>> +    if (of_property_read_bool(node, "ti,autoidle-low"))
>> +        clk->flags |= AUTOIDLE_LOW;
>> +
>> +    list_add(&clk->node, &autoidle_clks);
>> +}
>> +
>> +void __init of_omap_divider_setup(struct device_node *node)
>> +{
>> +    of_divider_clk_setup(node);
>> +    of_omap_autoidle_setup(node);
>> +}
>> +EXPORT_SYMBOL_GPL(of_omap_divider_setup);
>> +CLK_OF_DECLARE(omap_autoidle_clock, "divider-clock",
>> of_omap_divider_setup);
>
> This is overriding drivers/clk/clk-divider.c ?

Yea, this declaration here should be removed.

>> +
>> +void __init of_omap_fixed_factor_setup(struct device_node *node)
>> +{
>> +    of_fixed_factor_clk_setup(node);
>> +    of_omap_autoidle_setup(node);
>> +}
>> +EXPORT_SYMBOL_GPL(of_omap_fixed_factor_setup);
>> +CLK_OF_DECLARE(omap_fixed_factor_clock, "fixed-factor-clock",
>> +    of_omap_fixed_factor_setup);
>
> This is overriding drivers/clk/clk-fixed-factor.c ?

Ditto.

>> +
>> +#endif
>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>> index cd31a81..c149097 100644
>> --- a/drivers/clk/omap/clk.c
>> +++ b/drivers/clk/omap/clk.c
>> @@ -25,8 +25,8 @@ static const struct of_device_id clk_match[] = {
>>       {.compatible = "fixed-clock", .data = of_fixed_clk_setup, },
>>       {.compatible = "mux-clock", .data = of_mux_clk_setup, },
>>       {.compatible = "fixed-factor-clock",
>> -        .data = of_fixed_factor_clk_setup, },
>> -    {.compatible = "divider-clock", .data = of_divider_clk_setup, },
>> +        .data = of_omap_fixed_factor_setup, },
>> +    {.compatible = "divider-clock", .data = of_omap_divider_setup, },

These should be enough for registration.

>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>>       {.compatible = "ti,omap4-dpll-clock", .data =
>> of_omap4_dpll_setup, },
>>       {},
>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>> index c39e775..904bdad 100644
>> --- a/include/linux/clk/omap.h
>> +++ b/include/linux/clk/omap.h
>> @@ -192,5 +192,9 @@ extern const struct clk_hw_omap_ops
>> clkhwops_omap4_dpllmx;
>>   int dt_omap_clk_init(void);
>>   extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int
>> cnt);
>>   void of_omap4_dpll_setup(struct device_node *node);
>> +void of_omap_fixed_factor_setup(struct device_node *node);
>> +void of_omap_divider_setup(struct device_node *node);
>> +void of_omap_clk_allow_autoidle_all(void);
>> +void of_omap_clk_deny_autoidle_all(void);
>>
>>   #endif
>>
>
> I personally dont prefer the fact that divider-clock and
> fixed-rate-clock now has double meaning - building a multi-arch kernel
> for example, this can wreak havoc. standard definitions should not be
> monkeyed around with thus if avoidable, and in this case, very much
> avoidable.
>
> just my 2 cents.

Yea, as described before, I'll change the code not to make a global 
override, instead, just make omap specific override which parses the 
extra params. That sound better or still see some issues with that?

-Tero

[PATCHv4 06/33] CLK: omap: add autoidle support

[Tero Kristo]

On 07/30/2013 09:56 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> OMAP clk driver now routes some of the basic clocks through own
>> registration routine to allow autoidle support. This routine just
>> checks a couple of device node properties and adds autoidle support
>> if required, and just passes the registration forward to basic clocks.
>
> why not extend standard framework to support autoidle capable clocks OR
> introduce our own clk node which depends on basic clocks?

Was kind of easier this way.

>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   arch/arm/mach-omap2/clock.c |    6 ++
>>   drivers/clk/omap/Makefile   |    2 +-
>>   drivers/clk/omap/autoidle.c |  130
>> +++++++++++++++++++++++++++++++++++++++++++
>>   drivers/clk/omap/clk.c      |    4 +-
>>   include/linux/clk/omap.h    |    4 ++
>>   5 files changed, 143 insertions(+), 3 deletions(-)
>>   create mode 100644 drivers/clk/omap/autoidle.c
>
> I know it is getting a little stale, but anyways, device tree binding
> missing.
>
>>
>> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
>> index 0c38ca9..669d4c4 100644
>> --- a/arch/arm/mach-omap2/clock.c
>> +++ b/arch/arm/mach-omap2/clock.c
> Not sure why, at this point in time we are going to calling drivers/clk
> code.
>
>> @@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
>>       list_for_each_entry(c, &clk_hw_omap_clocks, node)
>>           if (c->ops && c->ops->allow_idle)
>>               c->ops->allow_idle(c);
>> +
>> +    of_omap_clk_allow_autoidle_all();
>> +
>>       return 0;
>>   }
>>
>> @@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
>>       list_for_each_entry(c, &clk_hw_omap_clocks, node)
>>           if (c->ops && c->ops->deny_idle)
>>               c->ops->deny_idle(c);
>> +
>> +    of_omap_clk_deny_autoidle_all();
>> +
>
> these are defined for CONFIG_OF.. anyways, without dt nodes (OMAP3 is
> supposed to support non-DT boot even now), this would not work, would it?

The lists are empty so the funcs do nothing. However, dropping CONFIG_OF 
would break these of course. Will figure out a fix for this.

The calls are needed for the transition phase until we can move more clk 
stuff from mach-omap2 to drivers.

>
>
>>       return 0;
>>   }
>>
>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>> index 4cad480..ca56700 100644
>> --- a/drivers/clk/omap/Makefile
>> +++ b/drivers/clk/omap/Makefile
>> @@ -1 +1 @@
>> -obj-y                    += clk.o dpll.o
>> +obj-y                    += clk.o dpll.o autoidle.o
>> diff --git a/drivers/clk/omap/autoidle.c b/drivers/clk/omap/autoidle.c
>> new file mode 100644
>> index 0000000..6424cb2
>> --- /dev/null
>> +++ b/drivers/clk/omap/autoidle.c
>> @@ -0,0 +1,130 @@
>> +/*
>> + * OMAP clock autoidle support
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * Tero Kristo <t-kristo@ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +#include <linux/string.h>
>> +#include <linux/log2.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
> at all of these required?

I'll double check.

>
>> +
>> +#ifdef CONFIG_OF
>> +struct clk_omap_autoidle {
>> +    void __iomem        *reg;
>> +    u8            shift;
>> +    u8            flags;
>> +    const char        *name;
>> +    struct list_head    node;
>> +};
>> +
>> +#define AUTOIDLE_LOW        0x1
>> +
>> +static LIST_HEAD(autoidle_clks);
>> +
>> +static void omap_allow_autoidle(struct clk_omap_autoidle *clk)
>> +{
>> +    u32 val;
>> +
>> +    val = readl(clk->reg);
>> +
>> +    if (clk->flags & AUTOIDLE_LOW)
>> +        val &= ~(1 << clk->shift);
>> +    else
>> +        val |= (1 << clk->shift);
>> +
>> +    writel(val, clk->reg);
>> +}
>> +
>> +static void omap_deny_autoidle(struct clk_omap_autoidle *clk)
>> +{
>> +    u32 val;
>> +
>> +    val = readl(clk->reg);
>> +
>> +    if (clk->flags & AUTOIDLE_LOW)
>> +        val |= (1 << clk->shift);
>> +    else
>> +        val &= ~(1 << clk->shift);
>> +
>> +    writel(val, clk->reg);
>> +}
>> +
>> +void of_omap_clk_allow_autoidle_all(void)
>> +{
>> +    struct clk_omap_autoidle *c;
>> +
>> +    list_for_each_entry(c, &autoidle_clks, node)
>> +        omap_allow_autoidle(c);
>> +}
>> +
>> +void of_omap_clk_deny_autoidle_all(void)
>> +{
>> +    struct clk_omap_autoidle *c;
>> +
>> +    list_for_each_entry(c, &autoidle_clks, node)
>> +        omap_deny_autoidle(c);
>> +}
>> +
>> +static __init void of_omap_autoidle_setup(struct device_node *node)
>> +{
>> +    u32 shift;
>> +    void __iomem *reg;
>> +    struct clk_omap_autoidle *clk;
>> +
>> +    if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
>> +        return;
>> +
>> +    reg = of_iomap(node, 0);
>> +
>> +    clk = kzalloc(sizeof(struct clk_omap_autoidle), GFP_KERNEL);
>> +
>> +    if (!clk) {
>> +        pr_err("%s: kzalloc failed\n", __func__);
>> +        return;
>> +    }
>> +
>> +    clk->shift = shift;
>> +    clk->name = node->name;
>> +    clk->reg = reg;
>> +
>> +    if (of_property_read_bool(node, "ti,autoidle-low"))
>> +        clk->flags |= AUTOIDLE_LOW;
>> +
>> +    list_add(&clk->node, &autoidle_clks);
>> +}
>> +
>> +void __init of_omap_divider_setup(struct device_node *node)
>> +{
>> +    of_divider_clk_setup(node);
>> +    of_omap_autoidle_setup(node);
>> +}
>> +EXPORT_SYMBOL_GPL(of_omap_divider_setup);
>> +CLK_OF_DECLARE(omap_autoidle_clock, "divider-clock",
>> of_omap_divider_setup);
>
> This is overriding drivers/clk/clk-divider.c ?

Yea, this declaration here should be removed.

>> +
>> +void __init of_omap_fixed_factor_setup(struct device_node *node)
>> +{
>> +    of_fixed_factor_clk_setup(node);
>> +    of_omap_autoidle_setup(node);
>> +}
>> +EXPORT_SYMBOL_GPL(of_omap_fixed_factor_setup);
>> +CLK_OF_DECLARE(omap_fixed_factor_clock, "fixed-factor-clock",
>> +    of_omap_fixed_factor_setup);
>
> This is overriding drivers/clk/clk-fixed-factor.c ?

Ditto.

>> +
>> +#endif
>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>> index cd31a81..c149097 100644
>> --- a/drivers/clk/omap/clk.c
>> +++ b/drivers/clk/omap/clk.c
>> @@ -25,8 +25,8 @@ static const struct of_device_id clk_match[] = {
>>       {.compatible = "fixed-clock", .data = of_fixed_clk_setup, },
>>       {.compatible = "mux-clock", .data = of_mux_clk_setup, },
>>       {.compatible = "fixed-factor-clock",
>> -        .data = of_fixed_factor_clk_setup, },
>> -    {.compatible = "divider-clock", .data = of_divider_clk_setup, },
>> +        .data = of_omap_fixed_factor_setup, },
>> +    {.compatible = "divider-clock", .data = of_omap_divider_setup, },

These should be enough for registration.

>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>>       {.compatible = "ti,omap4-dpll-clock", .data =
>> of_omap4_dpll_setup, },
>>       {},
>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>> index c39e775..904bdad 100644
>> --- a/include/linux/clk/omap.h
>> +++ b/include/linux/clk/omap.h
>> @@ -192,5 +192,9 @@ extern const struct clk_hw_omap_ops
>> clkhwops_omap4_dpllmx;
>>   int dt_omap_clk_init(void);
>>   extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int
>> cnt);
>>   void of_omap4_dpll_setup(struct device_node *node);
>> +void of_omap_fixed_factor_setup(struct device_node *node);
>> +void of_omap_divider_setup(struct device_node *node);
>> +void of_omap_clk_allow_autoidle_all(void);
>> +void of_omap_clk_deny_autoidle_all(void);
>>
>>   #endif
>>
>
> I personally dont prefer the fact that divider-clock and
> fixed-rate-clock now has double meaning - building a multi-arch kernel
> for example, this can wreak havoc. standard definitions should not be
> monkeyed around with thus if avoidable, and in this case, very much
> avoidable.
>
> just my 2 cents.

Yea, as described before, I'll change the code not to make a global 
override, instead, just make omap specific override which parses the 
extra params. That sound better or still see some issues with that?

-Tero

Re: [PATCHv4 06/33] CLK: omap: add autoidle support

[Nishanth Menon]

On 07/31/2013 05:13 AM, Tero Kristo wrote:
> On 07/30/2013 09:56 PM, Nishanth Menon wrote:
>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>> OMAP clk driver now routes some of the basic clocks through own
>>> registration routine to allow autoidle support. This routine just
>>> checks a couple of device node properties and adds autoidle support
>>> if required, and just passes the registration forward to basic clocks.
>>
>> why not extend standard framework to support autoidle capable clocks OR
>> introduce our own clk node which depends on basic clocks?
>
> Was kind of easier this way.

We never liked taking the easy road :) if we can extend standard 
drivers, that will be the first preference - else we will need to 
explain precisely why it cant be extended.

>>> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
>>> index 0c38ca9..669d4c4 100644
>>> --- a/arch/arm/mach-omap2/clock.c
>>> +++ b/arch/arm/mach-omap2/clock.c
>> Not sure why, at this point in time we are going to calling drivers/clk
>> code.
>>
>>> @@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
>>>       list_for_each_entry(c, &clk_hw_omap_clocks, node)
>>>           if (c->ops && c->ops->allow_idle)
>>>               c->ops->allow_idle(c);
>>> +
>>> +    of_omap_clk_allow_autoidle_all();
>>> +
>>>       return 0;
>>>   }
>>>
>>> @@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
>>>       list_for_each_entry(c, &clk_hw_omap_clocks, node)
>>>           if (c->ops && c->ops->deny_idle)
>>>               c->ops->deny_idle(c);
>>> +
>>> +    of_omap_clk_deny_autoidle_all();
>>> +
>>
>> these are defined for CONFIG_OF.. anyways, without dt nodes (OMAP3 is
>> supposed to support non-DT boot even now), this would not work, would it?
>
> The lists are empty so the funcs do nothing. However, dropping CONFIG_OF
> would break these of course. Will figure out a fix for this.
>
> The calls are needed for the transition phase until we can move more clk
> stuff from mach-omap2 to drivers.

yes please. for ones like these, we can try to maintain a rule of 
mach-omap2 calling drivers/clk rather than drivers/clk -> mach-omap2. 
This will allow us to move out of mach-omap2 eventually by just deleting 
call points in mach-omap2.

[...]
>>>
>>>   #endif
>>>
>>
>> I personally dont prefer the fact that divider-clock and
>> fixed-rate-clock now has double meaning - building a multi-arch kernel
>> for example, this can wreak havoc. standard definitions should not be
>> monkeyed around with thus if avoidable, and in this case, very much
>> avoidable.
>>
>> just my 2 cents.
>
> Yea, as described before, I'll change the code not to make a global
> override, instead, just make omap specific override which parses the
> extra params. That sound better or still see some issues with that?

I think described above - if we can introduce these into standard 
drivers, it is the best, else introduce it with ti, prefix to indicate a 
TI variant. keeps everyone happy.


-- 
Regards,
Nishanth Menon

[PATCHv4 06/33] CLK: omap: add autoidle support

[Nishanth Menon]

On 07/31/2013 05:13 AM, Tero Kristo wrote:
> On 07/30/2013 09:56 PM, Nishanth Menon wrote:
>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>> OMAP clk driver now routes some of the basic clocks through own
>>> registration routine to allow autoidle support. This routine just
>>> checks a couple of device node properties and adds autoidle support
>>> if required, and just passes the registration forward to basic clocks.
>>
>> why not extend standard framework to support autoidle capable clocks OR
>> introduce our own clk node which depends on basic clocks?
>
> Was kind of easier this way.

We never liked taking the easy road :) if we can extend standard 
drivers, that will be the first preference - else we will need to 
explain precisely why it cant be extended.

>>> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
>>> index 0c38ca9..669d4c4 100644
>>> --- a/arch/arm/mach-omap2/clock.c
>>> +++ b/arch/arm/mach-omap2/clock.c
>> Not sure why, at this point in time we are going to calling drivers/clk
>> code.
>>
>>> @@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
>>>       list_for_each_entry(c, &clk_hw_omap_clocks, node)
>>>           if (c->ops && c->ops->allow_idle)
>>>               c->ops->allow_idle(c);
>>> +
>>> +    of_omap_clk_allow_autoidle_all();
>>> +
>>>       return 0;
>>>   }
>>>
>>> @@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
>>>       list_for_each_entry(c, &clk_hw_omap_clocks, node)
>>>           if (c->ops && c->ops->deny_idle)
>>>               c->ops->deny_idle(c);
>>> +
>>> +    of_omap_clk_deny_autoidle_all();
>>> +
>>
>> these are defined for CONFIG_OF.. anyways, without dt nodes (OMAP3 is
>> supposed to support non-DT boot even now), this would not work, would it?
>
> The lists are empty so the funcs do nothing. However, dropping CONFIG_OF
> would break these of course. Will figure out a fix for this.
>
> The calls are needed for the transition phase until we can move more clk
> stuff from mach-omap2 to drivers.

yes please. for ones like these, we can try to maintain a rule of 
mach-omap2 calling drivers/clk rather than drivers/clk -> mach-omap2. 
This will allow us to move out of mach-omap2 eventually by just deleting 
call points in mach-omap2.

[...]
>>>
>>>   #endif
>>>
>>
>> I personally dont prefer the fact that divider-clock and
>> fixed-rate-clock now has double meaning - building a multi-arch kernel
>> for example, this can wreak havoc. standard definitions should not be
>> monkeyed around with thus if avoidable, and in this case, very much
>> avoidable.
>>
>> just my 2 cents.
>
> Yea, as described before, I'll change the code not to make a global
> override, instead, just make omap specific override which parses the
> extra params. That sound better or still see some issues with that?

I think described above - if we can introduce these into standard 
drivers, it is the best, else introduce it with ti, prefix to indicate a 
TI variant. keeps everyone happy.


-- 
Regards,
Nishanth Menon

Re: [PATCHv4 06/33] CLK: omap: add autoidle support

[Tero Kristo]

On 08/01/2013 05:11 PM, Nishanth Menon wrote:
> On 07/31/2013 05:13 AM, Tero Kristo wrote:
>> On 07/30/2013 09:56 PM, Nishanth Menon wrote:
>>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>>> OMAP clk driver now routes some of the basic clocks through own
>>>> registration routine to allow autoidle support. This routine just
>>>> checks a couple of device node properties and adds autoidle support
>>>> if required, and just passes the registration forward to basic clocks.
>>>
>>> why not extend standard framework to support autoidle capable clocks OR
>>> introduce our own clk node which depends on basic clocks?
>>
>> Was kind of easier this way.
>
> We never liked taking the easy road :) if we can extend standard
> drivers, that will be the first preference - else we will need to
> explain precisely why it cant be extended.
>
>>>> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
>>>> index 0c38ca9..669d4c4 100644
>>>> --- a/arch/arm/mach-omap2/clock.c
>>>> +++ b/arch/arm/mach-omap2/clock.c
>>> Not sure why, at this point in time we are going to calling drivers/clk
>>> code.
>>>
>>>> @@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
>>>>       list_for_each_entry(c, &clk_hw_omap_clocks, node)
>>>>           if (c->ops && c->ops->allow_idle)
>>>>               c->ops->allow_idle(c);
>>>> +
>>>> +    of_omap_clk_allow_autoidle_all();
>>>> +
>>>>       return 0;
>>>>   }
>>>>
>>>> @@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
>>>>       list_for_each_entry(c, &clk_hw_omap_clocks, node)
>>>>           if (c->ops && c->ops->deny_idle)
>>>>               c->ops->deny_idle(c);
>>>> +
>>>> +    of_omap_clk_deny_autoidle_all();
>>>> +
>>>
>>> these are defined for CONFIG_OF.. anyways, without dt nodes (OMAP3 is
>>> supposed to support non-DT boot even now), this would not work, would
>>> it?
>>
>> The lists are empty so the funcs do nothing. However, dropping CONFIG_OF
>> would break these of course. Will figure out a fix for this.
>>
>> The calls are needed for the transition phase until we can move more clk
>> stuff from mach-omap2 to drivers.
>
> yes please. for ones like these, we can try to maintain a rule of
> mach-omap2 calling drivers/clk rather than drivers/clk -> mach-omap2.
> This will allow us to move out of mach-omap2 eventually by just deleting
> call points in mach-omap2.
>
> [...]
>>>>
>>>>   #endif
>>>>
>>>
>>> I personally dont prefer the fact that divider-clock and
>>> fixed-rate-clock now has double meaning - building a multi-arch kernel
>>> for example, this can wreak havoc. standard definitions should not be
>>> monkeyed around with thus if avoidable, and in this case, very much
>>> avoidable.
>>>
>>> just my 2 cents.
>>
>> Yea, as described before, I'll change the code not to make a global
>> override, instead, just make omap specific override which parses the
>> extra params. That sound better or still see some issues with that?
>
> I think described above - if we can introduce these into standard
> drivers, it is the best, else introduce it with ti, prefix to indicate a
> TI variant. keeps everyone happy.

Going with TI variant for now, I don't think other architectures have 
exactly similar need right now.

-Tero

[PATCHv4 06/33] CLK: omap: add autoidle support

[Tero Kristo]

On 08/01/2013 05:11 PM, Nishanth Menon wrote:
> On 07/31/2013 05:13 AM, Tero Kristo wrote:
>> On 07/30/2013 09:56 PM, Nishanth Menon wrote:
>>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>>> OMAP clk driver now routes some of the basic clocks through own
>>>> registration routine to allow autoidle support. This routine just
>>>> checks a couple of device node properties and adds autoidle support
>>>> if required, and just passes the registration forward to basic clocks.
>>>
>>> why not extend standard framework to support autoidle capable clocks OR
>>> introduce our own clk node which depends on basic clocks?
>>
>> Was kind of easier this way.
>
> We never liked taking the easy road :) if we can extend standard
> drivers, that will be the first preference - else we will need to
> explain precisely why it cant be extended.
>
>>>> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
>>>> index 0c38ca9..669d4c4 100644
>>>> --- a/arch/arm/mach-omap2/clock.c
>>>> +++ b/arch/arm/mach-omap2/clock.c
>>> Not sure why, at this point in time we are going to calling drivers/clk
>>> code.
>>>
>>>> @@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void)
>>>>       list_for_each_entry(c, &clk_hw_omap_clocks, node)
>>>>           if (c->ops && c->ops->allow_idle)
>>>>               c->ops->allow_idle(c);
>>>> +
>>>> +    of_omap_clk_allow_autoidle_all();
>>>> +
>>>>       return 0;
>>>>   }
>>>>
>>>> @@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void)
>>>>       list_for_each_entry(c, &clk_hw_omap_clocks, node)
>>>>           if (c->ops && c->ops->deny_idle)
>>>>               c->ops->deny_idle(c);
>>>> +
>>>> +    of_omap_clk_deny_autoidle_all();
>>>> +
>>>
>>> these are defined for CONFIG_OF.. anyways, without dt nodes (OMAP3 is
>>> supposed to support non-DT boot even now), this would not work, would
>>> it?
>>
>> The lists are empty so the funcs do nothing. However, dropping CONFIG_OF
>> would break these of course. Will figure out a fix for this.
>>
>> The calls are needed for the transition phase until we can move more clk
>> stuff from mach-omap2 to drivers.
>
> yes please. for ones like these, we can try to maintain a rule of
> mach-omap2 calling drivers/clk rather than drivers/clk -> mach-omap2.
> This will allow us to move out of mach-omap2 eventually by just deleting
> call points in mach-omap2.
>
> [...]
>>>>
>>>>   #endif
>>>>
>>>
>>> I personally dont prefer the fact that divider-clock and
>>> fixed-rate-clock now has double meaning - building a multi-arch kernel
>>> for example, this can wreak havoc. standard definitions should not be
>>> monkeyed around with thus if avoidable, and in this case, very much
>>> avoidable.
>>>
>>> just my 2 cents.
>>
>> Yea, as described before, I'll change the code not to make a global
>> override, instead, just make omap specific override which parses the
>> extra params. That sound better or still see some issues with that?
>
> I think described above - if we can introduce these into standard
> drivers, it is the best, else introduce it with ti, prefix to indicate a
> TI variant. keeps everyone happy.

Going with TI variant for now, I don't think other architectures have 
exactly similar need right now.

-Tero

[PATCHv4 07/33] CLK: omap: add support for OMAP gate clock

[Tero Kristo]

This node adds support for a clock node which allows control to the
clockdomain enable / disable.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/Makefile |    2 +-
 drivers/clk/omap/clk.c    |    1 +
 drivers/clk/omap/gate.c   |   88 +++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/omap.h  |    1 +
 4 files changed, 91 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/omap/gate.c

diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index ca56700..3d3ca30f 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1 +1 @@
-obj-y					+= clk.o dpll.o autoidle.o
+obj-y					+= clk.o dpll.o autoidle.o gate.o
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index c149097..8c89714 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -29,6 +29,7 @@ static const struct of_device_id clk_match[] = {
 	{.compatible = "divider-clock", .data = of_omap_divider_setup, },
 	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
 	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
+	{.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
 	{},
 };
 
diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
new file mode 100644
index 0000000..7186bb2
--- /dev/null
+++ b/drivers/clk/omap/gate.c
@@ -0,0 +1,88 @@
+/*
+ * OMAP gate clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/omap.h>
+
+#ifdef CONFIG_OF
+
+static const struct clk_ops omap_gate_clk_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_clkops_enable_clkdm,
+	.disable	= &omap2_clkops_disable_clkdm,
+};
+
+void __init of_omap_gate_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	struct clk_init_data init;
+	struct clk_hw_omap *clk_hw;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names;
+	int i;
+
+	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return;
+	}
+
+	clk_hw->hw.init = &init;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
+
+	init.name = clk_name;
+	init.ops = &omap_gate_clk_ops;
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: omap trace_clk %s must have parent(s)\n",
+			__func__, node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	init.num_parents = num_parents;
+	init.parent_names = parent_names;
+
+	clk = clk_register(NULL, &clk_hw->hw);
+
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		return;
+	}
+
+cleanup:
+	kfree(clk_hw);
+}
+EXPORT_SYMBOL(of_omap_gate_clk_setup);
+CLK_OF_DECLARE(omap_gate_clk, "ti,omap-gate-clock", of_omap_gate_clk_setup);
+#endif
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index 904bdad..58ebb80 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -194,6 +194,7 @@ extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
 void of_omap4_dpll_setup(struct device_node *node);
 void of_omap_fixed_factor_setup(struct device_node *node);
 void of_omap_divider_setup(struct device_node *node);
+void of_omap_gate_clk_setup(struct device_node *node);
 void of_omap_clk_allow_autoidle_all(void);
 void of_omap_clk_deny_autoidle_all(void);
 
-- 
1.7.9.5

[PATCHv4 07/33] CLK: omap: add support for OMAP gate clock

[Tero Kristo]

This node adds support for a clock node which allows control to the
clockdomain enable / disable.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/Makefile |    2 +-
 drivers/clk/omap/clk.c    |    1 +
 drivers/clk/omap/gate.c   |   88 +++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/omap.h  |    1 +
 4 files changed, 91 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/omap/gate.c

diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index ca56700..3d3ca30f 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1 +1 @@
-obj-y					+= clk.o dpll.o autoidle.o
+obj-y					+= clk.o dpll.o autoidle.o gate.o
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index c149097..8c89714 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -29,6 +29,7 @@ static const struct of_device_id clk_match[] = {
 	{.compatible = "divider-clock", .data = of_omap_divider_setup, },
 	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
 	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
+	{.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
 	{},
 };
 
diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
new file mode 100644
index 0000000..7186bb2
--- /dev/null
+++ b/drivers/clk/omap/gate.c
@@ -0,0 +1,88 @@
+/*
+ * OMAP gate clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/omap.h>
+
+#ifdef CONFIG_OF
+
+static const struct clk_ops omap_gate_clk_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_clkops_enable_clkdm,
+	.disable	= &omap2_clkops_disable_clkdm,
+};
+
+void __init of_omap_gate_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	struct clk_init_data init;
+	struct clk_hw_omap *clk_hw;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names;
+	int i;
+
+	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return;
+	}
+
+	clk_hw->hw.init = &init;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
+
+	init.name = clk_name;
+	init.ops = &omap_gate_clk_ops;
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: omap trace_clk %s must have parent(s)\n",
+			__func__, node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	init.num_parents = num_parents;
+	init.parent_names = parent_names;
+
+	clk = clk_register(NULL, &clk_hw->hw);
+
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		return;
+	}
+
+cleanup:
+	kfree(clk_hw);
+}
+EXPORT_SYMBOL(of_omap_gate_clk_setup);
+CLK_OF_DECLARE(omap_gate_clk, "ti,omap-gate-clock", of_omap_gate_clk_setup);
+#endif
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index 904bdad..58ebb80 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -194,6 +194,7 @@ extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
 void of_omap4_dpll_setup(struct device_node *node);
 void of_omap_fixed_factor_setup(struct device_node *node);
 void of_omap_divider_setup(struct device_node *node);
+void of_omap_gate_clk_setup(struct device_node *node);
 void of_omap_clk_allow_autoidle_all(void);
 void of_omap_clk_deny_autoidle_all(void);
 
-- 
1.7.9.5

Re: [PATCHv4 07/33] CLK: omap: add support for OMAP gate clock

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> This node adds support for a clock node which allows control to the
> clockdomain enable / disable.

Dont we have clkdm_enable/disable for the same? should we model 
clockdomain as a clock node?

>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/Makefile |    2 +-
>   drivers/clk/omap/clk.c    |    1 +
>   drivers/clk/omap/gate.c   |   88 +++++++++++++++++++++++++++++++++++++++++++++
>   include/linux/clk/omap.h  |    1 +
>   4 files changed, 91 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/clk/omap/gate.c
>

my usual crib: device tree binding documentation is missing

> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
> index ca56700..3d3ca30f 100644
> --- a/drivers/clk/omap/Makefile
> +++ b/drivers/clk/omap/Makefile
> @@ -1 +1 @@
> -obj-y					+= clk.o dpll.o autoidle.o
> +obj-y					+= clk.o dpll.o autoidle.o gate.o
> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
> index c149097..8c89714 100644
> --- a/drivers/clk/omap/clk.c
> +++ b/drivers/clk/omap/clk.c
> @@ -29,6 +29,7 @@ static const struct of_device_id clk_match[] = {
>   	{.compatible = "divider-clock", .data = of_omap_divider_setup, },
>   	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
>   	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
> +	{.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },

I am a little lost - is there any SoC dts that actually uses this? at 
least this series does not seem to introduce any node that uses this 
compatibility as per git grep :(

might as well drop the patch?

>   	{},
>   };
>
> diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
> new file mode 100644
> index 0000000..7186bb2
> --- /dev/null
> +++ b/drivers/clk/omap/gate.c
> @@ -0,0 +1,88 @@
> +/*
> + * OMAP gate clock support
> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * Tero Kristo <t-kristo@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/string.h>
> +#include <linux/log2.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk/omap.h>
> +
> +#ifdef CONFIG_OF
> +
> +static const struct clk_ops omap_gate_clk_ops = {
> +	.init		= &omap2_init_clk_clkdm,
> +	.enable		= &omap2_clkops_enable_clkdm,
> +	.disable	= &omap2_clkops_disable_clkdm,
> +};
> +
> +void __init of_omap_gate_clk_setup(struct device_node *node)
> +{
> +	struct clk *clk;
> +	struct clk_init_data init;
init = { 0 };
> +	struct clk_hw_omap *clk_hw;
> +	const char *clk_name = node->name;
> +	int num_parents;
> +	const char **parent_names;
> +	int i;
> +
> +	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct clk_hw_omap)...)

> +	if (!clk_hw) {
> +		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
> +		return;
> +	}
> +
> +	clk_hw->hw.init = &init;
> +
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
> +
> +	init.name = clk_name;
> +	init.ops = &omap_gate_clk_ops;
> +
> +	num_parents = of_clk_get_parent_count(node);
> +	if (num_parents < 1) {
> +		pr_err("%s: omap trace_clk %s must have parent(s)\n",
> +			__func__, node->name);
CHECK: Alignment should match open parenthesis

> +		goto cleanup;
> +	}
> +
> +	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
> +
> +	for (i = 0; i < num_parents; i++)
> +		parent_names[i] = of_clk_get_parent_name(node, i);
> +
> +	init.num_parents = num_parents;
> +	init.parent_names = parent_names;
> +
> +	clk = clk_register(NULL, &clk_hw->hw);
> +
> +	if (!IS_ERR(clk)) {
> +		of_clk_add_provider(node, of_clk_src_simple_get, clk);
> +		return;
> +	}
> +
> +cleanup:
kfree(parent_names)?
> +	kfree(clk_hw);
> +}
> +EXPORT_SYMBOL(of_omap_gate_clk_setup);
> +CLK_OF_DECLARE(omap_gate_clk, "ti,omap-gate-clock", of_omap_gate_clk_setup);
> +#endif
> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
> index 904bdad..58ebb80 100644
> --- a/include/linux/clk/omap.h
> +++ b/include/linux/clk/omap.h
> @@ -194,6 +194,7 @@ extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
>   void of_omap4_dpll_setup(struct device_node *node);
>   void of_omap_fixed_factor_setup(struct device_node *node);
>   void of_omap_divider_setup(struct device_node *node);
> +void of_omap_gate_clk_setup(struct device_node *node);
dont need to export I think if we use strategy mentioned previously.

>   void of_omap_clk_allow_autoidle_all(void);
>   void of_omap_clk_deny_autoidle_all(void);
>
>


-- 
Regards,
Nishanth Menon

[PATCHv4 07/33] CLK: omap: add support for OMAP gate clock

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> This node adds support for a clock node which allows control to the
> clockdomain enable / disable.

Dont we have clkdm_enable/disable for the same? should we model 
clockdomain as a clock node?

>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/Makefile |    2 +-
>   drivers/clk/omap/clk.c    |    1 +
>   drivers/clk/omap/gate.c   |   88 +++++++++++++++++++++++++++++++++++++++++++++
>   include/linux/clk/omap.h  |    1 +
>   4 files changed, 91 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/clk/omap/gate.c
>

my usual crib: device tree binding documentation is missing

> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
> index ca56700..3d3ca30f 100644
> --- a/drivers/clk/omap/Makefile
> +++ b/drivers/clk/omap/Makefile
> @@ -1 +1 @@
> -obj-y					+= clk.o dpll.o autoidle.o
> +obj-y					+= clk.o dpll.o autoidle.o gate.o
> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
> index c149097..8c89714 100644
> --- a/drivers/clk/omap/clk.c
> +++ b/drivers/clk/omap/clk.c
> @@ -29,6 +29,7 @@ static const struct of_device_id clk_match[] = {
>   	{.compatible = "divider-clock", .data = of_omap_divider_setup, },
>   	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
>   	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
> +	{.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },

I am a little lost - is there any SoC dts that actually uses this? at 
least this series does not seem to introduce any node that uses this 
compatibility as per git grep :(

might as well drop the patch?

>   	{},
>   };
>
> diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
> new file mode 100644
> index 0000000..7186bb2
> --- /dev/null
> +++ b/drivers/clk/omap/gate.c
> @@ -0,0 +1,88 @@
> +/*
> + * OMAP gate clock support
> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * Tero Kristo <t-kristo@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/string.h>
> +#include <linux/log2.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk/omap.h>
> +
> +#ifdef CONFIG_OF
> +
> +static const struct clk_ops omap_gate_clk_ops = {
> +	.init		= &omap2_init_clk_clkdm,
> +	.enable		= &omap2_clkops_enable_clkdm,
> +	.disable	= &omap2_clkops_disable_clkdm,
> +};
> +
> +void __init of_omap_gate_clk_setup(struct device_node *node)
> +{
> +	struct clk *clk;
> +	struct clk_init_data init;
init = { 0 };
> +	struct clk_hw_omap *clk_hw;
> +	const char *clk_name = node->name;
> +	int num_parents;
> +	const char **parent_names;
> +	int i;
> +
> +	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct clk_hw_omap)...)

> +	if (!clk_hw) {
> +		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
> +		return;
> +	}
> +
> +	clk_hw->hw.init = &init;
> +
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
> +
> +	init.name = clk_name;
> +	init.ops = &omap_gate_clk_ops;
> +
> +	num_parents = of_clk_get_parent_count(node);
> +	if (num_parents < 1) {
> +		pr_err("%s: omap trace_clk %s must have parent(s)\n",
> +			__func__, node->name);
CHECK: Alignment should match open parenthesis

> +		goto cleanup;
> +	}
> +
> +	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
> +
> +	for (i = 0; i < num_parents; i++)
> +		parent_names[i] = of_clk_get_parent_name(node, i);
> +
> +	init.num_parents = num_parents;
> +	init.parent_names = parent_names;
> +
> +	clk = clk_register(NULL, &clk_hw->hw);
> +
> +	if (!IS_ERR(clk)) {
> +		of_clk_add_provider(node, of_clk_src_simple_get, clk);
> +		return;
> +	}
> +
> +cleanup:
kfree(parent_names)?
> +	kfree(clk_hw);
> +}
> +EXPORT_SYMBOL(of_omap_gate_clk_setup);
> +CLK_OF_DECLARE(omap_gate_clk, "ti,omap-gate-clock", of_omap_gate_clk_setup);
> +#endif
> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
> index 904bdad..58ebb80 100644
> --- a/include/linux/clk/omap.h
> +++ b/include/linux/clk/omap.h
> @@ -194,6 +194,7 @@ extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
>   void of_omap4_dpll_setup(struct device_node *node);
>   void of_omap_fixed_factor_setup(struct device_node *node);
>   void of_omap_divider_setup(struct device_node *node);
> +void of_omap_gate_clk_setup(struct device_node *node);
dont need to export I think if we use strategy mentioned previously.

>   void of_omap_clk_allow_autoidle_all(void);
>   void of_omap_clk_deny_autoidle_all(void);
>
>


-- 
Regards,
Nishanth Menon

Re: [PATCHv4 07/33] CLK: omap: add support for OMAP gate clock

[Tero Kristo]

On 07/30/2013 10:17 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> This node adds support for a clock node which allows control to the
>> clockdomain enable / disable.
>
> Dont we have clkdm_enable/disable for the same? should we model
> clockdomain as a clock node?

There was some discussion about having clockdomain code under 
drivers/clk while back, but Mike turned this idea down.

>
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/Makefile |    2 +-
>>   drivers/clk/omap/clk.c    |    1 +
>>   drivers/clk/omap/gate.c   |   88
>> +++++++++++++++++++++++++++++++++++++++++++++
>>   include/linux/clk/omap.h  |    1 +
>>   4 files changed, 91 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/clk/omap/gate.c
>>
>
> my usual crib: device tree binding documentation is missing
>
>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>> index ca56700..3d3ca30f 100644
>> --- a/drivers/clk/omap/Makefile
>> +++ b/drivers/clk/omap/Makefile
>> @@ -1 +1 @@
>> -obj-y                    += clk.o dpll.o autoidle.o
>> +obj-y                    += clk.o dpll.o autoidle.o gate.o
>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>> index c149097..8c89714 100644
>> --- a/drivers/clk/omap/clk.c
>> +++ b/drivers/clk/omap/clk.c
>> @@ -29,6 +29,7 @@ static const struct of_device_id clk_match[] = {
>>       {.compatible = "divider-clock", .data = of_omap_divider_setup, },
>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>>       {.compatible = "ti,omap4-dpll-clock", .data =
>> of_omap4_dpll_setup, },
>> +    {.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
>
> I am a little lost - is there any SoC dts that actually uses this? at
> least this series does not seem to introduce any node that uses this
> compatibility as per git grep :(

There is, see patch 08/33 or 28/33.

>
> might as well drop the patch?
>
>>       {},
>>   };
>>
>> diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
>> new file mode 100644
>> index 0000000..7186bb2
>> --- /dev/null
>> +++ b/drivers/clk/omap/gate.c
>> @@ -0,0 +1,88 @@
>> +/*
>> + * OMAP gate clock support
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * Tero Kristo <t-kristo@ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +#include <linux/string.h>
>> +#include <linux/log2.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk/omap.h>
>> +
>> +#ifdef CONFIG_OF
>> +
>> +static const struct clk_ops omap_gate_clk_ops = {
>> +    .init        = &omap2_init_clk_clkdm,
>> +    .enable        = &omap2_clkops_enable_clkdm,
>> +    .disable    = &omap2_clkops_disable_clkdm,
>> +};
>> +
>> +void __init of_omap_gate_clk_setup(struct device_node *node)
>> +{
>> +    struct clk *clk;
>> +    struct clk_init_data init;
> init = { 0 };

Will add.

>> +    struct clk_hw_omap *clk_hw;
>> +    const char *clk_name = node->name;
>> +    int num_parents;
>> +    const char **parent_names;
>> +    int i;
>> +
>> +    clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
> kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct clk_hw_omap)...)
>
>> +    if (!clk_hw) {
>> +        pr_err("%s: could not allocate clk_hw_omap\n", __func__);
>> +        return;
>> +    }
>> +
>> +    clk_hw->hw.init = &init;
>> +
>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>> +    of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
>> +
>> +    init.name = clk_name;
>> +    init.ops = &omap_gate_clk_ops;
>> +
>> +    num_parents = of_clk_get_parent_count(node);
>> +    if (num_parents < 1) {
>> +        pr_err("%s: omap trace_clk %s must have parent(s)\n",
>> +            __func__, node->name);
> CHECK: Alignment should match open parenthesis

I still wonder which version of checkpatch you are using.

>
>> +        goto cleanup;
>> +    }
>> +
>> +    parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
>> +
>> +    for (i = 0; i < num_parents; i++)
>> +        parent_names[i] = of_clk_get_parent_name(node, i);
>> +
>> +    init.num_parents = num_parents;
>> +    init.parent_names = parent_names;
>> +
>> +    clk = clk_register(NULL, &clk_hw->hw);
>> +
>> +    if (!IS_ERR(clk)) {
>> +        of_clk_add_provider(node, of_clk_src_simple_get, clk);
>> +        return;
>> +    }
>> +
>> +cleanup:
> kfree(parent_names)?

Yea, will add.

>> +    kfree(clk_hw);
>> +}
>> +EXPORT_SYMBOL(of_omap_gate_clk_setup);
>> +CLK_OF_DECLARE(omap_gate_clk, "ti,omap-gate-clock",
>> of_omap_gate_clk_setup);
>> +#endif
>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>> index 904bdad..58ebb80 100644
>> --- a/include/linux/clk/omap.h
>> +++ b/include/linux/clk/omap.h
>> @@ -194,6 +194,7 @@ extern void omap_dt_clocks_register(struct
>> omap_dt_clk *oclks, int cnt);
>>   void of_omap4_dpll_setup(struct device_node *node);
>>   void of_omap_fixed_factor_setup(struct device_node *node);
>>   void of_omap_divider_setup(struct device_node *node);
>> +void of_omap_gate_clk_setup(struct device_node *node);
> dont need to export I think if we use strategy mentioned previously.

So, we actually had an offline chat with Nishanth, and I will modify the 
init setup like previously suggested by him.

>
>>   void of_omap_clk_allow_autoidle_all(void);
>>   void of_omap_clk_deny_autoidle_all(void);
>>
>>
>
>

[PATCHv4 07/33] CLK: omap: add support for OMAP gate clock

[Tero Kristo]

On 07/30/2013 10:17 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> This node adds support for a clock node which allows control to the
>> clockdomain enable / disable.
>
> Dont we have clkdm_enable/disable for the same? should we model
> clockdomain as a clock node?

There was some discussion about having clockdomain code under 
drivers/clk while back, but Mike turned this idea down.

>
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/Makefile |    2 +-
>>   drivers/clk/omap/clk.c    |    1 +
>>   drivers/clk/omap/gate.c   |   88
>> +++++++++++++++++++++++++++++++++++++++++++++
>>   include/linux/clk/omap.h  |    1 +
>>   4 files changed, 91 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/clk/omap/gate.c
>>
>
> my usual crib: device tree binding documentation is missing
>
>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>> index ca56700..3d3ca30f 100644
>> --- a/drivers/clk/omap/Makefile
>> +++ b/drivers/clk/omap/Makefile
>> @@ -1 +1 @@
>> -obj-y                    += clk.o dpll.o autoidle.o
>> +obj-y                    += clk.o dpll.o autoidle.o gate.o
>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>> index c149097..8c89714 100644
>> --- a/drivers/clk/omap/clk.c
>> +++ b/drivers/clk/omap/clk.c
>> @@ -29,6 +29,7 @@ static const struct of_device_id clk_match[] = {
>>       {.compatible = "divider-clock", .data = of_omap_divider_setup, },
>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>>       {.compatible = "ti,omap4-dpll-clock", .data =
>> of_omap4_dpll_setup, },
>> +    {.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
>
> I am a little lost - is there any SoC dts that actually uses this? at
> least this series does not seem to introduce any node that uses this
> compatibility as per git grep :(

There is, see patch 08/33 or 28/33.

>
> might as well drop the patch?
>
>>       {},
>>   };
>>
>> diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
>> new file mode 100644
>> index 0000000..7186bb2
>> --- /dev/null
>> +++ b/drivers/clk/omap/gate.c
>> @@ -0,0 +1,88 @@
>> +/*
>> + * OMAP gate clock support
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * Tero Kristo <t-kristo@ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +#include <linux/string.h>
>> +#include <linux/log2.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk/omap.h>
>> +
>> +#ifdef CONFIG_OF
>> +
>> +static const struct clk_ops omap_gate_clk_ops = {
>> +    .init        = &omap2_init_clk_clkdm,
>> +    .enable        = &omap2_clkops_enable_clkdm,
>> +    .disable    = &omap2_clkops_disable_clkdm,
>> +};
>> +
>> +void __init of_omap_gate_clk_setup(struct device_node *node)
>> +{
>> +    struct clk *clk;
>> +    struct clk_init_data init;
> init = { 0 };

Will add.

>> +    struct clk_hw_omap *clk_hw;
>> +    const char *clk_name = node->name;
>> +    int num_parents;
>> +    const char **parent_names;
>> +    int i;
>> +
>> +    clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
> kzalloc(sizeof(*clk_hw)...) over kzalloc(sizeof(struct clk_hw_omap)...)
>
>> +    if (!clk_hw) {
>> +        pr_err("%s: could not allocate clk_hw_omap\n", __func__);
>> +        return;
>> +    }
>> +
>> +    clk_hw->hw.init = &init;
>> +
>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>> +    of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
>> +
>> +    init.name = clk_name;
>> +    init.ops = &omap_gate_clk_ops;
>> +
>> +    num_parents = of_clk_get_parent_count(node);
>> +    if (num_parents < 1) {
>> +        pr_err("%s: omap trace_clk %s must have parent(s)\n",
>> +            __func__, node->name);
> CHECK: Alignment should match open parenthesis

I still wonder which version of checkpatch you are using.

>
>> +        goto cleanup;
>> +    }
>> +
>> +    parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
>> +
>> +    for (i = 0; i < num_parents; i++)
>> +        parent_names[i] = of_clk_get_parent_name(node, i);
>> +
>> +    init.num_parents = num_parents;
>> +    init.parent_names = parent_names;
>> +
>> +    clk = clk_register(NULL, &clk_hw->hw);
>> +
>> +    if (!IS_ERR(clk)) {
>> +        of_clk_add_provider(node, of_clk_src_simple_get, clk);
>> +        return;
>> +    }
>> +
>> +cleanup:
> kfree(parent_names)?

Yea, will add.

>> +    kfree(clk_hw);
>> +}
>> +EXPORT_SYMBOL(of_omap_gate_clk_setup);
>> +CLK_OF_DECLARE(omap_gate_clk, "ti,omap-gate-clock",
>> of_omap_gate_clk_setup);
>> +#endif
>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>> index 904bdad..58ebb80 100644
>> --- a/include/linux/clk/omap.h
>> +++ b/include/linux/clk/omap.h
>> @@ -194,6 +194,7 @@ extern void omap_dt_clocks_register(struct
>> omap_dt_clk *oclks, int cnt);
>>   void of_omap4_dpll_setup(struct device_node *node);
>>   void of_omap_fixed_factor_setup(struct device_node *node);
>>   void of_omap_divider_setup(struct device_node *node);
>> +void of_omap_gate_clk_setup(struct device_node *node);
> dont need to export I think if we use strategy mentioned previously.

So, we actually had an offline chat with Nishanth, and I will modify the 
init setup like previously suggested by him.

>
>>   void of_omap_clk_allow_autoidle_all(void);
>>   void of_omap_clk_deny_autoidle_all(void);
>>
>>
>
>

Re: [PATCHv4 07/33] CLK: omap: add support for OMAP gate clock

[Nishanth Menon]

On 07/31/2013 09:45 AM, Tero Kristo wrote:
> On 07/30/2013 10:17 PM, Nishanth Menon wrote:
>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>> This node adds support for a clock node which allows control to the
>>> clockdomain enable / disable.
>>
>> Dont we have clkdm_enable/disable for the same? should we model
>> clockdomain as a clock node?
>
> There was some discussion about having clockdomain code under
> drivers/clk while back, but Mike turned this idea down.

then why are we doing this?

 >>> +    .init        = &omap2_init_clk_clkdm,
 >>> +    .enable        = &omap2_clkops_enable_clkdm,
 >>> +    .disable    = &omap2_clkops_disable_clkdm,

is practically doing this in a round about way, no? If Mike no likey 
clkdm going in here, introducing a "pseudo" clk node has no chance of 
going in either.. dont you think so? should we not just try to have our 
clocks first available before we try low power scenarios as next stage?


>
>>
>>>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>> ---
>>>   drivers/clk/omap/Makefile |    2 +-
>>>   drivers/clk/omap/clk.c    |    1 +
>>>   drivers/clk/omap/gate.c   |   88
>>> +++++++++++++++++++++++++++++++++++++++++++++
>>>   include/linux/clk/omap.h  |    1 +
>>>   4 files changed, 91 insertions(+), 1 deletion(-)
>>>   create mode 100644 drivers/clk/omap/gate.c
>>>
>>
>> my usual crib: device tree binding documentation is missing
>>
>>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>>> index ca56700..3d3ca30f 100644
>>> --- a/drivers/clk/omap/Makefile
>>> +++ b/drivers/clk/omap/Makefile
>>> @@ -1 +1 @@
>>> -obj-y                    += clk.o dpll.o autoidle.o
>>> +obj-y                    += clk.o dpll.o autoidle.o gate.o
>>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>>> index c149097..8c89714 100644
>>> --- a/drivers/clk/omap/clk.c
>>> +++ b/drivers/clk/omap/clk.c
>>> @@ -29,6 +29,7 @@ static const struct of_device_id clk_match[] = {
>>>       {.compatible = "divider-clock", .data = of_omap_divider_setup, },
>>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>>>       {.compatible = "ti,omap4-dpll-clock", .data =
>>> of_omap4_dpll_setup, },
>>> +    {.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
>>
>> I am a little lost - is there any SoC dts that actually uses this? at
>> least this series does not seem to introduce any node that uses this
>> compatibility as per git grep :(
>
> There is, see patch 08/33 or 28/33.

yes indeed, my bad, looks like my eyesight is no longer what it used to 
be :P.. time for those binocular glasses and a hammer on top of my head 
to remind myself :D


>>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>>> +    of_property_read_string(node, "ti,clkdm-name",
>>> &clk_hw->clkdm_name);
>>> +
>>> +    init.name = clk_name;
>>> +    init.ops = &omap_gate_clk_ops;
>>> +
>>> +    num_parents = of_clk_get_parent_count(node);
>>> +    if (num_parents < 1) {
>>> +        pr_err("%s: omap trace_clk %s must have parent(s)\n",
>>> +            __func__, node->name);
>> CHECK: Alignment should match open parenthesis
>
> I still wonder which version of checkpatch you are using.

hehe, makes me look hawkeyed :P.. no magic here obviously ;)

./scripts/checkpatch.pl --strict

revision: git describe
v3.11-rc3-47-g72195e0
(with all the patches applied).

[...]
>>> +    kfree(clk_hw);
>>> +}
>>> +EXPORT_SYMBOL(of_omap_gate_clk_setup);
>>> +CLK_OF_DECLARE(omap_gate_clk, "ti,omap-gate-clock",
>>> of_omap_gate_clk_setup);
>>> +#endif
>>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>>> index 904bdad..58ebb80 100644
>>> --- a/include/linux/clk/omap.h
>>> +++ b/include/linux/clk/omap.h
>>> @@ -194,6 +194,7 @@ extern void omap_dt_clocks_register(struct
>>> omap_dt_clk *oclks, int cnt);
>>>   void of_omap4_dpll_setup(struct device_node *node);
>>>   void of_omap_fixed_factor_setup(struct device_node *node);
>>>   void of_omap_divider_setup(struct device_node *node);
>>> +void of_omap_gate_clk_setup(struct device_node *node);
>> dont need to export I think if we use strategy mentioned previously.
>
> So, we actually had an offline chat with Nishanth, and I will modify the
> init setup like previously suggested by him.
>
yes, thanks.


-- 
Regards,
Nishanth Menon

[PATCHv4 07/33] CLK: omap: add support for OMAP gate clock

[Nishanth Menon]

On 07/31/2013 09:45 AM, Tero Kristo wrote:
> On 07/30/2013 10:17 PM, Nishanth Menon wrote:
>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>> This node adds support for a clock node which allows control to the
>>> clockdomain enable / disable.
>>
>> Dont we have clkdm_enable/disable for the same? should we model
>> clockdomain as a clock node?
>
> There was some discussion about having clockdomain code under
> drivers/clk while back, but Mike turned this idea down.

then why are we doing this?

 >>> +    .init        = &omap2_init_clk_clkdm,
 >>> +    .enable        = &omap2_clkops_enable_clkdm,
 >>> +    .disable    = &omap2_clkops_disable_clkdm,

is practically doing this in a round about way, no? If Mike no likey 
clkdm going in here, introducing a "pseudo" clk node has no chance of 
going in either.. dont you think so? should we not just try to have our 
clocks first available before we try low power scenarios as next stage?


>
>>
>>>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>> ---
>>>   drivers/clk/omap/Makefile |    2 +-
>>>   drivers/clk/omap/clk.c    |    1 +
>>>   drivers/clk/omap/gate.c   |   88
>>> +++++++++++++++++++++++++++++++++++++++++++++
>>>   include/linux/clk/omap.h  |    1 +
>>>   4 files changed, 91 insertions(+), 1 deletion(-)
>>>   create mode 100644 drivers/clk/omap/gate.c
>>>
>>
>> my usual crib: device tree binding documentation is missing
>>
>>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>>> index ca56700..3d3ca30f 100644
>>> --- a/drivers/clk/omap/Makefile
>>> +++ b/drivers/clk/omap/Makefile
>>> @@ -1 +1 @@
>>> -obj-y                    += clk.o dpll.o autoidle.o
>>> +obj-y                    += clk.o dpll.o autoidle.o gate.o
>>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>>> index c149097..8c89714 100644
>>> --- a/drivers/clk/omap/clk.c
>>> +++ b/drivers/clk/omap/clk.c
>>> @@ -29,6 +29,7 @@ static const struct of_device_id clk_match[] = {
>>>       {.compatible = "divider-clock", .data = of_omap_divider_setup, },
>>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>>>       {.compatible = "ti,omap4-dpll-clock", .data =
>>> of_omap4_dpll_setup, },
>>> +    {.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
>>
>> I am a little lost - is there any SoC dts that actually uses this? at
>> least this series does not seem to introduce any node that uses this
>> compatibility as per git grep :(
>
> There is, see patch 08/33 or 28/33.

yes indeed, my bad, looks like my eyesight is no longer what it used to 
be :P.. time for those binocular glasses and a hammer on top of my head 
to remind myself :D


>>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>>> +    of_property_read_string(node, "ti,clkdm-name",
>>> &clk_hw->clkdm_name);
>>> +
>>> +    init.name = clk_name;
>>> +    init.ops = &omap_gate_clk_ops;
>>> +
>>> +    num_parents = of_clk_get_parent_count(node);
>>> +    if (num_parents < 1) {
>>> +        pr_err("%s: omap trace_clk %s must have parent(s)\n",
>>> +            __func__, node->name);
>> CHECK: Alignment should match open parenthesis
>
> I still wonder which version of checkpatch you are using.

hehe, makes me look hawkeyed :P.. no magic here obviously ;)

./scripts/checkpatch.pl --strict

revision: git describe
v3.11-rc3-47-g72195e0
(with all the patches applied).

[...]
>>> +    kfree(clk_hw);
>>> +}
>>> +EXPORT_SYMBOL(of_omap_gate_clk_setup);
>>> +CLK_OF_DECLARE(omap_gate_clk, "ti,omap-gate-clock",
>>> of_omap_gate_clk_setup);
>>> +#endif
>>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>>> index 904bdad..58ebb80 100644
>>> --- a/include/linux/clk/omap.h
>>> +++ b/include/linux/clk/omap.h
>>> @@ -194,6 +194,7 @@ extern void omap_dt_clocks_register(struct
>>> omap_dt_clk *oclks, int cnt);
>>>   void of_omap4_dpll_setup(struct device_node *node);
>>>   void of_omap_fixed_factor_setup(struct device_node *node);
>>>   void of_omap_divider_setup(struct device_node *node);
>>> +void of_omap_gate_clk_setup(struct device_node *node);
>> dont need to export I think if we use strategy mentioned previously.
>
> So, we actually had an offline chat with Nishanth, and I will modify the
> init setup like previously suggested by him.
>
yes, thanks.


-- 
Regards,
Nishanth Menon

Re: [PATCHv4 07/33] CLK: omap: add support for OMAP gate clock

[Tero Kristo]

On 08/01/2013 05:33 PM, Nishanth Menon wrote:
> On 07/31/2013 09:45 AM, Tero Kristo wrote:
>> On 07/30/2013 10:17 PM, Nishanth Menon wrote:
>>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>>> This node adds support for a clock node which allows control to the
>>>> clockdomain enable / disable.
>>>
>>> Dont we have clkdm_enable/disable for the same? should we model
>>> clockdomain as a clock node?
>>
>> There was some discussion about having clockdomain code under
>> drivers/clk while back, but Mike turned this idea down.
>
> then why are we doing this?
>
>  >>> +    .init        = &omap2_init_clk_clkdm,
>  >>> +    .enable        = &omap2_clkops_enable_clkdm,
>  >>> +    .disable    = &omap2_clkops_disable_clkdm,
>
> is practically doing this in a round about way, no? If Mike no likey
> clkdm going in here, introducing a "pseudo" clk node has no chance of
> going in either.. dont you think so? should we not just try to have our
> clocks first available before we try low power scenarios as next stage?

This is actually for a single hwmod I believe, the emu one. It doesn't 
have proper functional clock control, but instead relies on clkdm being 
up/down. The conversion for this exists as it is part of the 
cclock44xx_data.c at the moment. We could maybe argue removing the hwmod 
for this to get rid of the need for this clock node.

>
>
>>
>>>
>>>>
>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>> ---
>>>>   drivers/clk/omap/Makefile |    2 +-
>>>>   drivers/clk/omap/clk.c    |    1 +
>>>>   drivers/clk/omap/gate.c   |   88
>>>> +++++++++++++++++++++++++++++++++++++++++++++
>>>>   include/linux/clk/omap.h  |    1 +
>>>>   4 files changed, 91 insertions(+), 1 deletion(-)
>>>>   create mode 100644 drivers/clk/omap/gate.c
>>>>
>>>
>>> my usual crib: device tree binding documentation is missing
>>>
>>>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>>>> index ca56700..3d3ca30f 100644
>>>> --- a/drivers/clk/omap/Makefile
>>>> +++ b/drivers/clk/omap/Makefile
>>>> @@ -1 +1 @@
>>>> -obj-y                    += clk.o dpll.o autoidle.o
>>>> +obj-y                    += clk.o dpll.o autoidle.o gate.o
>>>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>>>> index c149097..8c89714 100644
>>>> --- a/drivers/clk/omap/clk.c
>>>> +++ b/drivers/clk/omap/clk.c
>>>> @@ -29,6 +29,7 @@ static const struct of_device_id clk_match[] = {
>>>>       {.compatible = "divider-clock", .data = of_omap_divider_setup, },
>>>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>>>>       {.compatible = "ti,omap4-dpll-clock", .data =
>>>> of_omap4_dpll_setup, },
>>>> +    {.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
>>>
>>> I am a little lost - is there any SoC dts that actually uses this? at
>>> least this series does not seem to introduce any node that uses this
>>> compatibility as per git grep :(
>>
>> There is, see patch 08/33 or 28/33.
>
> yes indeed, my bad, looks like my eyesight is no longer what it used to
> be :P.. time for those binocular glasses and a hammer on top of my head
> to remind myself :D
>
>
>>>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>>>> +    of_property_read_string(node, "ti,clkdm-name",
>>>> &clk_hw->clkdm_name);
>>>> +
>>>> +    init.name = clk_name;
>>>> +    init.ops = &omap_gate_clk_ops;
>>>> +
>>>> +    num_parents = of_clk_get_parent_count(node);
>>>> +    if (num_parents < 1) {
>>>> +        pr_err("%s: omap trace_clk %s must have parent(s)\n",
>>>> +            __func__, node->name);
>>> CHECK: Alignment should match open parenthesis
>>
>> I still wonder which version of checkpatch you are using.
>
> hehe, makes me look hawkeyed :P.. no magic here obviously ;)
>
> ./scripts/checkpatch.pl --strict
>
> revision: git describe
> v3.11-rc3-47-g72195e0
> (with all the patches applied).
>
> [...]
>>>> +    kfree(clk_hw);
>>>> +}
>>>> +EXPORT_SYMBOL(of_omap_gate_clk_setup);
>>>> +CLK_OF_DECLARE(omap_gate_clk, "ti,omap-gate-clock",
>>>> of_omap_gate_clk_setup);
>>>> +#endif
>>>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>>>> index 904bdad..58ebb80 100644
>>>> --- a/include/linux/clk/omap.h
>>>> +++ b/include/linux/clk/omap.h
>>>> @@ -194,6 +194,7 @@ extern void omap_dt_clocks_register(struct
>>>> omap_dt_clk *oclks, int cnt);
>>>>   void of_omap4_dpll_setup(struct device_node *node);
>>>>   void of_omap_fixed_factor_setup(struct device_node *node);
>>>>   void of_omap_divider_setup(struct device_node *node);
>>>> +void of_omap_gate_clk_setup(struct device_node *node);
>>> dont need to export I think if we use strategy mentioned previously.
>>
>> So, we actually had an offline chat with Nishanth, and I will modify the
>> init setup like previously suggested by him.
>>
> yes, thanks.
>
>

[PATCHv4 07/33] CLK: omap: add support for OMAP gate clock

[Tero Kristo]

On 08/01/2013 05:33 PM, Nishanth Menon wrote:
> On 07/31/2013 09:45 AM, Tero Kristo wrote:
>> On 07/30/2013 10:17 PM, Nishanth Menon wrote:
>>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>>> This node adds support for a clock node which allows control to the
>>>> clockdomain enable / disable.
>>>
>>> Dont we have clkdm_enable/disable for the same? should we model
>>> clockdomain as a clock node?
>>
>> There was some discussion about having clockdomain code under
>> drivers/clk while back, but Mike turned this idea down.
>
> then why are we doing this?
>
>  >>> +    .init        = &omap2_init_clk_clkdm,
>  >>> +    .enable        = &omap2_clkops_enable_clkdm,
>  >>> +    .disable    = &omap2_clkops_disable_clkdm,
>
> is practically doing this in a round about way, no? If Mike no likey
> clkdm going in here, introducing a "pseudo" clk node has no chance of
> going in either.. dont you think so? should we not just try to have our
> clocks first available before we try low power scenarios as next stage?

This is actually for a single hwmod I believe, the emu one. It doesn't 
have proper functional clock control, but instead relies on clkdm being 
up/down. The conversion for this exists as it is part of the 
cclock44xx_data.c at the moment. We could maybe argue removing the hwmod 
for this to get rid of the need for this clock node.

>
>
>>
>>>
>>>>
>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>> ---
>>>>   drivers/clk/omap/Makefile |    2 +-
>>>>   drivers/clk/omap/clk.c    |    1 +
>>>>   drivers/clk/omap/gate.c   |   88
>>>> +++++++++++++++++++++++++++++++++++++++++++++
>>>>   include/linux/clk/omap.h  |    1 +
>>>>   4 files changed, 91 insertions(+), 1 deletion(-)
>>>>   create mode 100644 drivers/clk/omap/gate.c
>>>>
>>>
>>> my usual crib: device tree binding documentation is missing
>>>
>>>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>>>> index ca56700..3d3ca30f 100644
>>>> --- a/drivers/clk/omap/Makefile
>>>> +++ b/drivers/clk/omap/Makefile
>>>> @@ -1 +1 @@
>>>> -obj-y                    += clk.o dpll.o autoidle.o
>>>> +obj-y                    += clk.o dpll.o autoidle.o gate.o
>>>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>>>> index c149097..8c89714 100644
>>>> --- a/drivers/clk/omap/clk.c
>>>> +++ b/drivers/clk/omap/clk.c
>>>> @@ -29,6 +29,7 @@ static const struct of_device_id clk_match[] = {
>>>>       {.compatible = "divider-clock", .data = of_omap_divider_setup, },
>>>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>>>>       {.compatible = "ti,omap4-dpll-clock", .data =
>>>> of_omap4_dpll_setup, },
>>>> +    {.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
>>>
>>> I am a little lost - is there any SoC dts that actually uses this? at
>>> least this series does not seem to introduce any node that uses this
>>> compatibility as per git grep :(
>>
>> There is, see patch 08/33 or 28/33.
>
> yes indeed, my bad, looks like my eyesight is no longer what it used to
> be :P.. time for those binocular glasses and a hammer on top of my head
> to remind myself :D
>
>
>>>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>>>> +    of_property_read_string(node, "ti,clkdm-name",
>>>> &clk_hw->clkdm_name);
>>>> +
>>>> +    init.name = clk_name;
>>>> +    init.ops = &omap_gate_clk_ops;
>>>> +
>>>> +    num_parents = of_clk_get_parent_count(node);
>>>> +    if (num_parents < 1) {
>>>> +        pr_err("%s: omap trace_clk %s must have parent(s)\n",
>>>> +            __func__, node->name);
>>> CHECK: Alignment should match open parenthesis
>>
>> I still wonder which version of checkpatch you are using.
>
> hehe, makes me look hawkeyed :P.. no magic here obviously ;)
>
> ./scripts/checkpatch.pl --strict
>
> revision: git describe
> v3.11-rc3-47-g72195e0
> (with all the patches applied).
>
> [...]
>>>> +    kfree(clk_hw);
>>>> +}
>>>> +EXPORT_SYMBOL(of_omap_gate_clk_setup);
>>>> +CLK_OF_DECLARE(omap_gate_clk, "ti,omap-gate-clock",
>>>> of_omap_gate_clk_setup);
>>>> +#endif
>>>> diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
>>>> index 904bdad..58ebb80 100644
>>>> --- a/include/linux/clk/omap.h
>>>> +++ b/include/linux/clk/omap.h
>>>> @@ -194,6 +194,7 @@ extern void omap_dt_clocks_register(struct
>>>> omap_dt_clk *oclks, int cnt);
>>>>   void of_omap4_dpll_setup(struct device_node *node);
>>>>   void of_omap_fixed_factor_setup(struct device_node *node);
>>>>   void of_omap_divider_setup(struct device_node *node);
>>>> +void of_omap_gate_clk_setup(struct device_node *node);
>>> dont need to export I think if we use strategy mentioned previously.
>>
>> So, we actually had an offline chat with Nishanth, and I will modify the
>> init setup like previously suggested by him.
>>
> yes, thanks.
>
>

[PATCHv4 08/33] ARM: dts: omap4 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap443x-clocks.dtsi |   17 +
 arch/arm/boot/dts/omap443x.dtsi        |    8 +
 arch/arm/boot/dts/omap4460.dtsi        |    8 +
 arch/arm/boot/dts/omap446x-clocks.dtsi |   27 +
 arch/arm/boot/dts/omap44xx-clocks.dtsi | 1654 ++++++++++++++++++++++++++++++++
 5 files changed, 1714 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 0000000..2bd82b2
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Device Tree Source for OMAP443x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+bandgap_fclk: bandgap_fclk@4a307888 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a307888 0x4>;
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index bcf455e..dfd648c 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -30,4 +30,12 @@
 		       0x4a00232C 0x4>;
 		compatible = "ti,omap4430-bandgap";
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap44xx-clocks.dtsi"
+		/include/ "omap443x-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index c2f0f39..d9d00b2 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -38,4 +38,12 @@
 		interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
 		gpios = <&gpio3 22 0>; /* tshut */
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap44xx-clocks.dtsi"
+		/include/ "omap446x-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi
new file mode 100644
index 0000000..86d0805
--- /dev/null
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for OMAP446x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+div_ts_ck: div_ts_ck@4a307888 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	bit-shift = <24>;
+	reg = <0x4a307888 0x4>;
+	table = < 8 0 >, < 16 1 >, < 32 2 >;
+	bit-mask = <0x3>;
+};
+
+bandgap_ts_fclk: bandgap_ts_fclk@4a307888 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&div_ts_ck>;
+	bit-shift = <8>;
+	reg = <0x4a307888 0x4>;
+};
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
new file mode 100644
index 0000000..ed6bc9b
--- /dev/null
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -0,0 +1,1654 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+extalt_clkin_ck: extalt_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <59000000>;
+};
+
+pad_clks_src_ck: pad_clks_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+pad_clks_ck: pad_clks_ck@4a004108 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&pad_clks_src_ck>;
+	bit-shift = <8>;
+	reg = <0x4a004108 0x4>;
+};
+
+pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+slimbus_src_clk: slimbus_src_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+slimbus_clk: slimbus_clk@4a004108 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&slimbus_src_clk>;
+	bit-shift = <10>;
+	reg = <0x4a004108 0x4>;
+};
+
+sys_32k_ck: sys_32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <38400000>;
+};
+
+sys_clkin_ck: sys_clkin_ck@4a306110 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+	reg = <0x4a306110 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+tie_low_clock_ck: tie_low_clock_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+utmi_phy_clkout_ck: utmi_phy_clkout_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60mhsp1_ck: xclk60mhsp1_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60mhsp2_ck: xclk60mhsp2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60motg_ck: xclk60motg_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a306108 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@4a30610c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	reg = <0x4a30610c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_abe_ck: dpll_abe_ck@4a0041e0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
+	reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
+	ti,clk-ref = <&abe_dpll_refclk_mux_ck>;
+	ti,clk-bypass = <&abe_dpll_bypass_clk_mux_ck>;
+	ti,dpll-regm4xen;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck@4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_abe_ck>;
+	reg = <0x4a0041f0 0x4>;
+	ti,dpll-clk-x2;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+abe_clk: abe_clk@4a004108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4a004108 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+aess_fclk: aess_fclk@4a004528 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&abe_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004528 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0041f4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041f4 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@4a00412c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
+	bit-shift = <23>;
+	reg = <0x4a00412c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_core_ck: dpll_core_ck@4a004120 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
+	reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&core_hsd_byp_clk_mux_ck>;
+	ti,dpll-core;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_core_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_core_m6x2_ck: dpll_core_m6x2_ck@4a004140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004140 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dbgclk_mux_ck: dbgclk_mux_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck@4a004130 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004130 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+ddrphy_ck: ddrphy_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_core_m5x2_ck: dpll_core_m5x2_ck@4a00413c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00413c 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+div_core_ck: div_core_ck@4a004100 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	reg = <0x4a004100 0x4>;
+	bit-mask = <0x1>;
+};
+
+div_iva_hs_clk: div_iva_hs_clk@4a0041dc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	reg = <0x4a0041dc 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+div_mpu_hs_clk: div_mpu_hs_clk@4a00419c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	reg = <0x4a00419c 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+dpll_core_m4x2_ck: dpll_core_m4x2_ck@4a004138 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004138 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dll_clk_div_ck: dll_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_abe_m2_ck: dpll_abe_m2_ck@4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_ck>;
+	reg = <0x4a0041f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@4a004134 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	reg = <0x4a004134 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck@4a004134 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_core_m3x2_div_ck>;
+	bit-shift = <8>;
+	reg = <0x4a004134 0x4>;
+};
+
+dpll_core_m7x2_ck: dpll_core_m7x2_ck@4a004144 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004144 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@4a0041ac {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
+	bit-shift = <23>;
+	reg = <0x4a0041ac 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_iva_ck: dpll_iva_ck@4a0041a0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
+	reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&iva_hsd_byp_clk_mux_ck>;
+};
+
+dpll_iva_x2_ck: dpll_iva_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_iva_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@4a0041b8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041b8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@4a0041bc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041bc 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_mpu_ck: dpll_mpu_ck@4a004160 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
+	reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&div_mpu_hs_clk>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a004170 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004170 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+per_hs_clk_div_ck: per_hs_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@4a00814c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
+	bit-shift = <23>;
+	reg = <0x4a00814c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_per_ck: dpll_per_ck@4a008140 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
+	reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&per_hsd_byp_clk_mux_ck>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck@4a008150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_ck>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck@4a008150 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_per_ck>;
+	reg = <0x4a008150 0x4>;
+	ti,dpll-clk-x2;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@4a008154 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	reg = <0x4a008154 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_per_m3x2_ck: dpll_per_m3x2_ck@4a008154 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m3x2_div_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008154 0x4>;
+};
+
+dpll_per_m4x2_ck: dpll_per_m4x2_ck@4a008158 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008158 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m5x2_ck: dpll_per_m5x2_ck@4a00815c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00815c 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m6x2_ck: dpll_per_m6x2_ck@4a008160 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008160 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m7x2_ck: dpll_per_m7x2_ck@4a008164 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008164 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+usb_hs_clk_div_ck: usb_hs_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck@4a008180 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
+	ti,clk-bypass = <&usb_hs_clk_div_ck>;
+	reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clkdm-name = "l3_init_clkdm";
+	ti,dpll-j-type;
+};
+
+dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@4a0081b4 {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,autoidle-shift = <8>;
+	clock-div = <1>;
+	reg = <0x4a0081b4 0x4>;
+	clock-mult = <1>;
+	ti,autoidle-low;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008190 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+ducati_clk_mux_ck: ducati_clk_mux_ck@4a008100 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
+	reg = <0x4a008100 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_12m_fclk: func_12m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_24mc_fclk: func_24mc_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+func_48m_fclk: func_48m_fclk@4a008108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	reg = <0x4a008108 0x4>;
+	table = < 4 0 >, < 8 1 >;
+	bit-mask = <0x1>;
+};
+
+func_48mc_fclk: func_48mc_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_64m_fclk: func_64m_fclk@4a008108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	reg = <0x4a008108 0x4>;
+	table = < 2 0 >, < 4 1 >;
+	bit-mask = <0x1>;
+};
+
+func_96m_fclk: func_96m_fclk@4a008108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	reg = <0x4a008108 0x4>;
+	table = < 2 0 >, < 4 1 >;
+	bit-mask = <0x1>;
+};
+
+init_60m_fclk: init_60m_fclk@4a008104 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	reg = <0x4a008104 0x4>;
+	table = < 1 0 >, < 8 1 >;
+	bit-mask = <0x1>;
+};
+
+l3_div_ck: l3_div_ck@4a004100 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&div_core_ck>;
+	bit-shift = <4>;
+	reg = <0x4a004100 0x4>;
+	bit-mask = <0x1>;
+};
+
+l4_div_ck: l4_div_ck@4a004100 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <8>;
+	reg = <0x4a004100 0x4>;
+	bit-mask = <0x1>;
+};
+
+lp_clk_div_ck: lp_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@4a306108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
+	reg = <0x4a306108 0x4>;
+	bit-mask = <0x1>;
+};
+
+mpu_periphclk: mpu_periphclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_mpu_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+ocp_abe_iclk: ocp_abe_iclk@4a004528 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&aess_fclk>;
+	bit-shift = <24>;
+	reg = <0x4a004528 0x4>;
+	table = < 2 0 >, < 1 1 >;
+	bit-mask = <0x1>;
+};
+
+per_abe_24m_fclk: per_abe_24m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+per_abe_nc_fclk: per_abe_nc_fclk@4a008108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	reg = <0x4a008108 0x4>;
+	bit-mask = <0x1>;
+};
+
+syc_clk_div_ck: syc_clk_div_ck@4a306100 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x4a306100 0x4>;
+	bit-mask = <0x1>;
+};
+
+aes1_fck: aes1_fck@4a0095a0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <1>;
+	reg = <0x4a0095a0 0x4>;
+};
+
+aes2_fck: aes2_fck@4a0095a8 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <1>;
+	reg = <0x4a0095a8 0x4>;
+};
+
+dmic_sync_mux_ck: dmic_sync_mux_ck@4a004538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004538 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_dmic_abe_gfclk: func_dmic_abe_gfclk@4a004538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004538 0x4>;
+	bit-mask = <0x3>;
+};
+
+dss_sys_clk: dss_sys_clk@4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&syc_clk_div_ck>;
+	bit-shift = <10>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_tv_clk: dss_tv_clk@4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&extalt_clkin_ck>;
+	bit-shift = <11>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk@4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m5x2_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk@4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48mc_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_fck: dss_fck@4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <1>;
+	reg = <0x4a009120 0x4>;
+};
+
+fdif_fck: fdif_fck@4a009028 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009028 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+gpio1_dbclk: gpio1_dbclk@4a307838 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a307838 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk@4a009460 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009460 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk@4a009468 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009468 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk@4a009470 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009470 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk@4a009478 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009478 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk@4a009480 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009480 0x4>;
+};
+
+sgx_clk_mux: sgx_clk_mux@4a009220 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009220 0x4>;
+	bit-mask = <0x1>;
+};
+
+hsi_fck: hsi_fck@4a009338 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009338 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+iss_ctrlclk: iss_ctrlclk@4a009020 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_96m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009020 0x4>;
+};
+
+mcasp_sync_mux_ck: mcasp_sync_mux_ck@4a004540 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004540 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@4a004540 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004540 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@4a004548 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004548 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_mcbsp1_gfclk: func_mcbsp1_gfclk@4a004548 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004548 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@4a004550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004550 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_mcbsp2_gfclk: func_mcbsp2_gfclk@4a004550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004550 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@4a004558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004558 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_mcbsp3_gfclk: func_mcbsp3_gfclk@4a004558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004558 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@4a0094e0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
+	bit-shift = <25>;
+	reg = <0x4a0094e0 0x4>;
+	bit-mask = <0x1>;
+};
+
+per_mcbsp4_gfclk: per_mcbsp4_gfclk@4a0094e0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0094e0 0x4>;
+	bit-mask = <0x1>;
+};
+
+hsmmc1_fclk: hsmmc1_fclk@4a009328 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+	bit-shift = <24>;
+	reg = <0x4a009328 0x4>;
+	bit-mask = <0x1>;
+};
+
+hsmmc2_fclk: hsmmc2_fclk@4a009330 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+	bit-shift = <24>;
+	reg = <0x4a009330 0x4>;
+	bit-mask = <0x1>;
+};
+
+ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@4a0093e0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a0093e0 0x4>;
+};
+
+sha2md5_fck: sha2md5_fck@4a0095c8 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <1>;
+	reg = <0x4a0095c8 0x4>;
+};
+
+slimbus1_fclk_1: slimbus1_fclk_1@4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_24m_clk>;
+	bit-shift = <9>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus1_fclk_0: slimbus1_fclk_0@4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&abe_24m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus1_fclk_2: slimbus1_fclk_2@4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&pad_clks_ck>;
+	bit-shift = <10>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus1_slimbus_clk: slimbus1_slimbus_clk@4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&slimbus_clk>;
+	bit-shift = <11>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus2_fclk_1: slimbus2_fclk_1@4a009538 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_abe_24m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009538 0x4>;
+};
+
+slimbus2_fclk_0: slimbus2_fclk_0@4a009538 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_24mc_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009538 0x4>;
+};
+
+slimbus2_slimbus_clk: slimbus2_slimbus_clk@4a009538 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&pad_slimbus_core_clks_ck>;
+	bit-shift = <10>;
+	reg = <0x4a009538 0x4>;
+};
+
+smartreflex_core_fck: smartreflex_core_fck@4a008638 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	bit-shift = <1>;
+	reg = <0x4a008638 0x4>;
+};
+
+smartreflex_iva_fck: smartreflex_iva_fck@4a008630 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	bit-shift = <1>;
+	reg = <0x4a008630 0x4>;
+};
+
+smartreflex_mpu_fck: smartreflex_mpu_fck@4a008628 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	bit-shift = <1>;
+	reg = <0x4a008628 0x4>;
+};
+
+dmt1_clk_mux: dmt1_clk_mux@4a307840 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a307840 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm10_mux: cm2_dm10_mux@4a009428 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009428 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm11_mux: cm2_dm11_mux@4a009430 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009430 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm2_mux: cm2_dm2_mux@4a009438 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009438 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm3_mux: cm2_dm3_mux@4a009440 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009440 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm4_mux: cm2_dm4_mux@4a009448 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009448 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer5_sync_mux: timer5_sync_mux@4a004568 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004568 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer6_sync_mux: timer6_sync_mux@4a004570 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004570 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer7_sync_mux: timer7_sync_mux@4a004578 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004578 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer8_sync_mux: timer8_sync_mux@4a004580 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004580 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm9_mux: cm2_dm9_mux@4a009450 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009450 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_fs_fck: usb_host_fs_fck@4a0093d0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48mc_fclk>;
+	reg = <0x4a0093d0 0x4>;
+	bit-shift = <1>;
+};
+
+utmi_p1_gfclk: utmi_p1_gfclk@4a009358 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009358 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&utmi_p1_gfclk>;
+	bit-shift = <8>;
+	reg = <0x4a009358 0x4>;
+};
+
+utmi_p2_gfclk: utmi_p2_gfclk@4a009358 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
+	bit-shift = <25>;
+	reg = <0x4a009358 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&utmi_p2_gfclk>;
+	bit-shift = <9>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <10>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <13>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <11>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <12>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <14>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_func48mclk: usb_host_hs_func48mclk@4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48mc_fclk>;
+	bit-shift = <15>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_fck: usb_host_hs_fck@4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <1>;
+	reg = <0x4a009358 0x4>;
+};
+
+otg_60m_gfclk: otg_60m_gfclk@4a009360 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009360 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_otg_hs_xclk: usb_otg_hs_xclk@4a009360 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&otg_60m_gfclk>;
+	bit-shift = <8>;
+	reg = <0x4a009360 0x4>;
+};
+
+usb_otg_hs_ick: usb_otg_hs_ick@4a009360 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <0>;
+	reg = <0x4a009360 0x4>;
+};
+
+usb_phy_cm_clk32k: usb_phy_cm_clk32k@4a008640 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008640 0x4>;
+};
+
+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@4a009368 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <10>;
+	reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@4a009368 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@4a009368 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_ick: usb_tll_hs_ick@4a009368 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l4_div_ck>;
+	bit-shift = <0>;
+	reg = <0x4a009368 0x4>;
+};
+
+usim_ck: usim_ck@4a307858 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a307858 0x4>;
+	table = < 14 0 >, < 18 1 >;
+	bit-mask = <0x1>;
+};
+
+usim_fclk: usim_fclk@4a307858 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&usim_ck>;
+	bit-shift = <8>;
+	reg = <0x4a307858 0x4>;
+};
+
+pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@4a307a20 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+	bit-shift = <20>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x3>;
+};
+
+pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@4a307a20 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+	bit-shift = <22>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x3>;
+};
+
+stm_clk_div_ck: stm_clk_div_ck@4a307a20 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&pmd_stm_clock_mux_ck>;
+	bit-shift = <27>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+trace_clk_div_div_ck: trace_clk_div_div_ck@4a307a20 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	bit-shift = <24>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+trace_clk_div_ck: trace_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&trace_clk_div_div_ck>;
+	ti,clkdm-name = "emu_sys_clkdm";
+};
+
+auxclk0_src_mux_ck: auxclk0_src_mux_ck@4a30a310 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a310 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk0_src_ck: auxclk0_src_ck@4a30a310 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk0_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a310 0x4>;
+};
+
+auxclk0_ck: auxclk0_ck@4a30a310 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk0_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a310 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk1_src_mux_ck: auxclk1_src_mux_ck@4a30a314 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a314 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk1_src_ck: auxclk1_src_ck@4a30a314 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk1_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a314 0x4>;
+};
+
+auxclk1_ck: auxclk1_ck@4a30a314 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk1_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a314 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk2_src_mux_ck: auxclk2_src_mux_ck@4a30a318 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a318 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk2_src_ck: auxclk2_src_ck@4a30a318 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk2_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a318 0x4>;
+};
+
+auxclk2_ck: auxclk2_ck@4a30a318 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk2_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a318 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk3_src_mux_ck: auxclk3_src_mux_ck@4a30a31c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a31c 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk3_src_ck: auxclk3_src_ck@4a30a31c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk3_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a31c 0x4>;
+};
+
+auxclk3_ck: auxclk3_ck@4a30a31c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk3_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a31c 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk4_src_mux_ck: auxclk4_src_mux_ck@4a30a320 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a320 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk4_src_ck: auxclk4_src_ck@4a30a320 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk4_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a320 0x4>;
+};
+
+auxclk4_ck: auxclk4_ck@4a30a320 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk4_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a320 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk5_src_mux_ck: auxclk5_src_mux_ck@4a30a324 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a324 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk5_src_ck: auxclk5_src_ck@4a30a324 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk5_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a324 0x4>;
+};
+
+auxclk5_ck: auxclk5_ck@4a30a324 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk5_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a324 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclkreq0_ck: auxclkreq0_ck@4a30a210 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a210 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq1_ck: auxclkreq1_ck@4a30a214 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a214 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq2_ck: auxclkreq2_ck@4a30a218 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a218 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq3_ck: auxclkreq3_ck@4a30a21c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a21c 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq4_ck: auxclkreq4_ck@4a30a220 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a220 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq5_ck: auxclkreq5_ck@4a30a224 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a224 0x4>;
+	bit-mask = <0x7>;
+};
-- 
1.7.9.5

[PATCHv4 08/33] ARM: dts: omap4 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap443x-clocks.dtsi |   17 +
 arch/arm/boot/dts/omap443x.dtsi        |    8 +
 arch/arm/boot/dts/omap4460.dtsi        |    8 +
 arch/arm/boot/dts/omap446x-clocks.dtsi |   27 +
 arch/arm/boot/dts/omap44xx-clocks.dtsi | 1654 ++++++++++++++++++++++++++++++++
 5 files changed, 1714 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 0000000..2bd82b2
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Device Tree Source for OMAP443x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+bandgap_fclk: bandgap_fclk at 4a307888 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a307888 0x4>;
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index bcf455e..dfd648c 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -30,4 +30,12 @@
 		       0x4a00232C 0x4>;
 		compatible = "ti,omap4430-bandgap";
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap44xx-clocks.dtsi"
+		/include/ "omap443x-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index c2f0f39..d9d00b2 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -38,4 +38,12 @@
 		interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
 		gpios = <&gpio3 22 0>; /* tshut */
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap44xx-clocks.dtsi"
+		/include/ "omap446x-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi
new file mode 100644
index 0000000..86d0805
--- /dev/null
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for OMAP446x clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+div_ts_ck: div_ts_ck at 4a307888 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	bit-shift = <24>;
+	reg = <0x4a307888 0x4>;
+	table = < 8 0 >, < 16 1 >, < 32 2 >;
+	bit-mask = <0x3>;
+};
+
+bandgap_ts_fclk: bandgap_ts_fclk at 4a307888 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&div_ts_ck>;
+	bit-shift = <8>;
+	reg = <0x4a307888 0x4>;
+};
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
new file mode 100644
index 0000000..ed6bc9b
--- /dev/null
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -0,0 +1,1654 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+extalt_clkin_ck: extalt_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <59000000>;
+};
+
+pad_clks_src_ck: pad_clks_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+pad_clks_ck: pad_clks_ck at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&pad_clks_src_ck>;
+	bit-shift = <8>;
+	reg = <0x4a004108 0x4>;
+};
+
+pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+slimbus_src_clk: slimbus_src_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+slimbus_clk: slimbus_clk at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&slimbus_src_clk>;
+	bit-shift = <10>;
+	reg = <0x4a004108 0x4>;
+};
+
+sys_32k_ck: sys_32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <38400000>;
+};
+
+sys_clkin_ck: sys_clkin_ck at 4a306110 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+	reg = <0x4a306110 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+tie_low_clock_ck: tie_low_clock_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+utmi_phy_clkout_ck: utmi_phy_clkout_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60mhsp1_ck: xclk60mhsp1_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60mhsp2_ck: xclk60mhsp2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60motg_ck: xclk60motg_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck at 4a306108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a306108 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck at 4a30610c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	reg = <0x4a30610c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_abe_ck: dpll_abe_ck at 4a0041e0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
+	reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
+	ti,clk-ref = <&abe_dpll_refclk_mux_ck>;
+	ti,clk-bypass = <&abe_dpll_bypass_clk_mux_ck>;
+	ti,dpll-regm4xen;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck at 4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_abe_ck>;
+	reg = <0x4a0041f0 0x4>;
+	ti,dpll-clk-x2;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+abe_clk: abe_clk at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4a004108 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+aess_fclk: aess_fclk at 4a004528 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&abe_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004528 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 4a0041f4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041f4 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck at 4a00412c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
+	bit-shift = <23>;
+	reg = <0x4a00412c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_core_ck: dpll_core_ck at 4a004120 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
+	reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&core_hsd_byp_clk_mux_ck>;
+	ti,dpll-core;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_core_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_core_m6x2_ck: dpll_core_m6x2_ck at 4a004140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004140 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dbgclk_mux_ck: dbgclk_mux_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck at 4a004130 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004130 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+ddrphy_ck: ddrphy_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_core_m5x2_ck: dpll_core_m5x2_ck at 4a00413c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00413c 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+div_core_ck: div_core_ck at 4a004100 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	reg = <0x4a004100 0x4>;
+	bit-mask = <0x1>;
+};
+
+div_iva_hs_clk: div_iva_hs_clk at 4a0041dc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	reg = <0x4a0041dc 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+div_mpu_hs_clk: div_mpu_hs_clk at 4a00419c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_m5x2_ck>;
+	reg = <0x4a00419c 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+dpll_core_m4x2_ck: dpll_core_m4x2_ck at 4a004138 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004138 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dll_clk_div_ck: dll_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_abe_m2_ck: dpll_abe_m2_ck at 4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_ck>;
+	reg = <0x4a0041f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck at 4a004134 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	reg = <0x4a004134 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck at 4a004134 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_core_m3x2_div_ck>;
+	bit-shift = <8>;
+	reg = <0x4a004134 0x4>;
+};
+
+dpll_core_m7x2_ck: dpll_core_m7x2_ck at 4a004144 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004144 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck at 4a0041ac {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
+	bit-shift = <23>;
+	reg = <0x4a0041ac 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_iva_ck: dpll_iva_ck at 4a0041a0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
+	reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&iva_hsd_byp_clk_mux_ck>;
+};
+
+dpll_iva_x2_ck: dpll_iva_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_iva_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_iva_m4x2_ck: dpll_iva_m4x2_ck at 4a0041b8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041b8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_iva_m5x2_ck: dpll_iva_m5x2_ck at 4a0041bc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041bc 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 4a004160 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
+	reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&div_mpu_hs_clk>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 4a004170 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004170 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+per_hs_clk_div_ck: per_hs_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck at 4a00814c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
+	bit-shift = <23>;
+	reg = <0x4a00814c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_per_ck: dpll_per_ck at 4a008140 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
+	reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&per_hsd_byp_clk_mux_ck>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_ck>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_per_ck>;
+	reg = <0x4a008150 0x4>;
+	ti,dpll-clk-x2;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck at 4a008154 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	reg = <0x4a008154 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_per_m3x2_ck: dpll_per_m3x2_ck at 4a008154 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m3x2_div_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008154 0x4>;
+};
+
+dpll_per_m4x2_ck: dpll_per_m4x2_ck at 4a008158 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008158 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m5x2_ck: dpll_per_m5x2_ck at 4a00815c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00815c 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m6x2_ck: dpll_per_m6x2_ck at 4a008160 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008160 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m7x2_ck: dpll_per_m7x2_ck at 4a008164 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008164 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+usb_hs_clk_div_ck: usb_hs_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck at 4a008180 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
+	ti,clk-bypass = <&usb_hs_clk_div_ck>;
+	reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clkdm-name = "l3_init_clkdm";
+	ti,dpll-j-type;
+};
+
+dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck at 4a0081b4 {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,autoidle-shift = <8>;
+	clock-div = <1>;
+	reg = <0x4a0081b4 0x4>;
+	clock-mult = <1>;
+	ti,autoidle-low;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008190 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+ducati_clk_mux_ck: ducati_clk_mux_ck at 4a008100 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
+	reg = <0x4a008100 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_12m_fclk: func_12m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_24mc_fclk: func_24mc_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+func_48m_fclk: func_48m_fclk at 4a008108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	reg = <0x4a008108 0x4>;
+	table = < 4 0 >, < 8 1 >;
+	bit-mask = <0x1>;
+};
+
+func_48mc_fclk: func_48mc_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_64m_fclk: func_64m_fclk at 4a008108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	reg = <0x4a008108 0x4>;
+	table = < 2 0 >, < 4 1 >;
+	bit-mask = <0x1>;
+};
+
+func_96m_fclk: func_96m_fclk at 4a008108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	reg = <0x4a008108 0x4>;
+	table = < 2 0 >, < 4 1 >;
+	bit-mask = <0x1>;
+};
+
+init_60m_fclk: init_60m_fclk at 4a008104 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	reg = <0x4a008104 0x4>;
+	table = < 1 0 >, < 8 1 >;
+	bit-mask = <0x1>;
+};
+
+l3_div_ck: l3_div_ck at 4a004100 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&div_core_ck>;
+	bit-shift = <4>;
+	reg = <0x4a004100 0x4>;
+	bit-mask = <0x1>;
+};
+
+l4_div_ck: l4_div_ck at 4a004100 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <8>;
+	reg = <0x4a004100 0x4>;
+	bit-mask = <0x1>;
+};
+
+lp_clk_div_ck: lp_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck at 4a306108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
+	reg = <0x4a306108 0x4>;
+	bit-mask = <0x1>;
+};
+
+mpu_periphclk: mpu_periphclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_mpu_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+ocp_abe_iclk: ocp_abe_iclk at 4a004528 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&aess_fclk>;
+	bit-shift = <24>;
+	reg = <0x4a004528 0x4>;
+	table = < 2 0 >, < 1 1 >;
+	bit-mask = <0x1>;
+};
+
+per_abe_24m_fclk: per_abe_24m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+per_abe_nc_fclk: per_abe_nc_fclk at 4a008108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	reg = <0x4a008108 0x4>;
+	bit-mask = <0x1>;
+};
+
+syc_clk_div_ck: syc_clk_div_ck at 4a306100 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x4a306100 0x4>;
+	bit-mask = <0x1>;
+};
+
+aes1_fck: aes1_fck at 4a0095a0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <1>;
+	reg = <0x4a0095a0 0x4>;
+};
+
+aes2_fck: aes2_fck at 4a0095a8 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <1>;
+	reg = <0x4a0095a8 0x4>;
+};
+
+dmic_sync_mux_ck: dmic_sync_mux_ck at 4a004538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004538 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_dmic_abe_gfclk: func_dmic_abe_gfclk at 4a004538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004538 0x4>;
+	bit-mask = <0x3>;
+};
+
+dss_sys_clk: dss_sys_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&syc_clk_div_ck>;
+	bit-shift = <10>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_tv_clk: dss_tv_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&extalt_clkin_ck>;
+	bit-shift = <11>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m5x2_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48mc_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_fck: dss_fck at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <1>;
+	reg = <0x4a009120 0x4>;
+};
+
+fdif_fck: fdif_fck at 4a009028 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009028 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+gpio1_dbclk: gpio1_dbclk at 4a307838 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a307838 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 4a009460 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009460 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 4a009468 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009468 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk at 4a009470 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009470 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk at 4a009478 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009478 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk at 4a009480 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009480 0x4>;
+};
+
+sgx_clk_mux: sgx_clk_mux at 4a009220 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009220 0x4>;
+	bit-mask = <0x1>;
+};
+
+hsi_fck: hsi_fck at 4a009338 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009338 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+iss_ctrlclk: iss_ctrlclk at 4a009020 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_96m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009020 0x4>;
+};
+
+mcasp_sync_mux_ck: mcasp_sync_mux_ck at 4a004540 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004540 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_mcasp_abe_gfclk: func_mcasp_abe_gfclk at 4a004540 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004540 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck at 4a004548 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004548 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_mcbsp1_gfclk: func_mcbsp1_gfclk at 4a004548 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004548 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck at 4a004550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004550 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_mcbsp2_gfclk: func_mcbsp2_gfclk at 4a004550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004550 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck at 4a004558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+	bit-shift = <25>;
+	reg = <0x4a004558 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_mcbsp3_gfclk: func_mcbsp3_gfclk at 4a004558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004558 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck at 4a0094e0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
+	bit-shift = <25>;
+	reg = <0x4a0094e0 0x4>;
+	bit-mask = <0x1>;
+};
+
+per_mcbsp4_gfclk: per_mcbsp4_gfclk at 4a0094e0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0094e0 0x4>;
+	bit-mask = <0x1>;
+};
+
+hsmmc1_fclk: hsmmc1_fclk at 4a009328 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+	bit-shift = <24>;
+	reg = <0x4a009328 0x4>;
+	bit-mask = <0x1>;
+};
+
+hsmmc2_fclk: hsmmc2_fclk at 4a009330 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+	bit-shift = <24>;
+	reg = <0x4a009330 0x4>;
+	bit-mask = <0x1>;
+};
+
+ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m at 4a0093e0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a0093e0 0x4>;
+};
+
+sha2md5_fck: sha2md5_fck at 4a0095c8 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <1>;
+	reg = <0x4a0095c8 0x4>;
+};
+
+slimbus1_fclk_1: slimbus1_fclk_1 at 4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_24m_clk>;
+	bit-shift = <9>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus1_fclk_0: slimbus1_fclk_0 at 4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&abe_24m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus1_fclk_2: slimbus1_fclk_2 at 4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&pad_clks_ck>;
+	bit-shift = <10>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus1_slimbus_clk: slimbus1_slimbus_clk at 4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&slimbus_clk>;
+	bit-shift = <11>;
+	reg = <0x4a004560 0x4>;
+};
+
+slimbus2_fclk_1: slimbus2_fclk_1 at 4a009538 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_abe_24m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009538 0x4>;
+};
+
+slimbus2_fclk_0: slimbus2_fclk_0 at 4a009538 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_24mc_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009538 0x4>;
+};
+
+slimbus2_slimbus_clk: slimbus2_slimbus_clk at 4a009538 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&pad_slimbus_core_clks_ck>;
+	bit-shift = <10>;
+	reg = <0x4a009538 0x4>;
+};
+
+smartreflex_core_fck: smartreflex_core_fck at 4a008638 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	bit-shift = <1>;
+	reg = <0x4a008638 0x4>;
+};
+
+smartreflex_iva_fck: smartreflex_iva_fck at 4a008630 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	bit-shift = <1>;
+	reg = <0x4a008630 0x4>;
+};
+
+smartreflex_mpu_fck: smartreflex_mpu_fck at 4a008628 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l4_wkup_clk_mux_ck>;
+	bit-shift = <1>;
+	reg = <0x4a008628 0x4>;
+};
+
+dmt1_clk_mux: dmt1_clk_mux at 4a307840 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a307840 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm10_mux: cm2_dm10_mux at 4a009428 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009428 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm11_mux: cm2_dm11_mux at 4a009430 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009430 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm2_mux: cm2_dm2_mux at 4a009438 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009438 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm3_mux: cm2_dm3_mux at 4a009440 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009440 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm4_mux: cm2_dm4_mux at 4a009448 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009448 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer5_sync_mux: timer5_sync_mux at 4a004568 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004568 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer6_sync_mux: timer6_sync_mux at 4a004570 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004570 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer7_sync_mux: timer7_sync_mux at 4a004578 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004578 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer8_sync_mux: timer8_sync_mux at 4a004580 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004580 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm2_dm9_mux: cm2_dm9_mux at 4a009450 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009450 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_fs_fck: usb_host_fs_fck at 4a0093d0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48mc_fclk>;
+	reg = <0x4a0093d0 0x4>;
+	bit-shift = <1>;
+};
+
+utmi_p1_gfclk: utmi_p1_gfclk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009358 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&utmi_p1_gfclk>;
+	bit-shift = <8>;
+	reg = <0x4a009358 0x4>;
+};
+
+utmi_p2_gfclk: utmi_p2_gfclk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
+	bit-shift = <25>;
+	reg = <0x4a009358 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&utmi_p2_gfclk>;
+	bit-shift = <9>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <10>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <13>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <11>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <12>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <14>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_func48mclk: usb_host_hs_func48mclk at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48mc_fclk>;
+	bit-shift = <15>;
+	reg = <0x4a009358 0x4>;
+};
+
+usb_host_hs_fck: usb_host_hs_fck at 4a009358 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <1>;
+	reg = <0x4a009358 0x4>;
+};
+
+otg_60m_gfclk: otg_60m_gfclk at 4a009360 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009360 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_otg_hs_xclk: usb_otg_hs_xclk at 4a009360 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&otg_60m_gfclk>;
+	bit-shift = <8>;
+	reg = <0x4a009360 0x4>;
+};
+
+usb_otg_hs_ick: usb_otg_hs_ick at 4a009360 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3_div_ck>;
+	bit-shift = <0>;
+	reg = <0x4a009360 0x4>;
+};
+
+usb_phy_cm_clk32k: usb_phy_cm_clk32k at 4a008640 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008640 0x4>;
+};
+
+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk at 4a009368 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <10>;
+	reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk at 4a009368 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk at 4a009368 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&init_60m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009368 0x4>;
+};
+
+usb_tll_hs_ick: usb_tll_hs_ick at 4a009368 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l4_div_ck>;
+	bit-shift = <0>;
+	reg = <0x4a009368 0x4>;
+};
+
+usim_ck: usim_ck at 4a307858 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m4x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a307858 0x4>;
+	table = < 14 0 >, < 18 1 >;
+	bit-mask = <0x1>;
+};
+
+usim_fclk: usim_fclk at 4a307858 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&usim_ck>;
+	bit-shift = <8>;
+	reg = <0x4a307858 0x4>;
+};
+
+pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck at 4a307a20 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+	bit-shift = <20>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x3>;
+};
+
+pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck at 4a307a20 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+	bit-shift = <22>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x3>;
+};
+
+stm_clk_div_ck: stm_clk_div_ck at 4a307a20 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&pmd_stm_clock_mux_ck>;
+	bit-shift = <27>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+trace_clk_div_div_ck: trace_clk_div_div_ck at 4a307a20 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	bit-shift = <24>;
+	reg = <0x4a307a20 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+trace_clk_div_ck: trace_clk_div_ck {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&trace_clk_div_div_ck>;
+	ti,clkdm-name = "emu_sys_clkdm";
+};
+
+auxclk0_src_mux_ck: auxclk0_src_mux_ck at 4a30a310 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a310 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk0_src_ck: auxclk0_src_ck at 4a30a310 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk0_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a310 0x4>;
+};
+
+auxclk0_ck: auxclk0_ck at 4a30a310 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk0_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a310 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk1_src_mux_ck: auxclk1_src_mux_ck at 4a30a314 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a314 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk1_src_ck: auxclk1_src_ck at 4a30a314 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk1_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a314 0x4>;
+};
+
+auxclk1_ck: auxclk1_ck at 4a30a314 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk1_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a314 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk2_src_mux_ck: auxclk2_src_mux_ck at 4a30a318 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a318 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk2_src_ck: auxclk2_src_ck at 4a30a318 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk2_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a318 0x4>;
+};
+
+auxclk2_ck: auxclk2_ck at 4a30a318 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk2_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a318 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk3_src_mux_ck: auxclk3_src_mux_ck at 4a30a31c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a31c 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk3_src_ck: auxclk3_src_ck at 4a30a31c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk3_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a31c 0x4>;
+};
+
+auxclk3_ck: auxclk3_ck at 4a30a31c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk3_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a31c 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk4_src_mux_ck: auxclk4_src_mux_ck at 4a30a320 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a320 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk4_src_ck: auxclk4_src_ck at 4a30a320 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk4_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a320 0x4>;
+};
+
+auxclk4_ck: auxclk4_ck at 4a30a320 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk4_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a320 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk5_src_mux_ck: auxclk5_src_mux_ck at 4a30a324 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4a30a324 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk5_src_ck: auxclk5_src_ck at 4a30a324 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk5_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4a30a324 0x4>;
+};
+
+auxclk5_ck: auxclk5_ck at 4a30a324 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk5_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4a30a324 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclkreq0_ck: auxclkreq0_ck at 4a30a210 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a210 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq1_ck: auxclkreq1_ck at 4a30a214 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a214 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq2_ck: auxclkreq2_ck at 4a30a218 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a218 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq3_ck: auxclkreq3_ck at 4a30a21c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a21c 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq4_ck: auxclkreq4_ck at 4a30a220 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a220 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq5_ck: auxclkreq5_ck at 4a30a224 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+	bit-shift = <2>;
+	reg = <0x4a30a224 0x4>;
+	bit-mask = <0x7>;
+};
-- 
1.7.9.5

Re: [PATCHv4 08/33] ARM: dts: omap4 clock data

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> This patch creates a unique node for each clock in the OMAP4 power,
> reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
> different clock tree which is taken into account in the data.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   arch/arm/boot/dts/omap443x-clocks.dtsi |   17 +
>   arch/arm/boot/dts/omap443x.dtsi        |    8 +
>   arch/arm/boot/dts/omap4460.dtsi        |    8 +
>   arch/arm/boot/dts/omap446x-clocks.dtsi |   27 +
>   arch/arm/boot/dts/omap44xx-clocks.dtsi | 1654 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/omap44xx-common-clocks.dtsi ?
>   5 files changed, 1714 insertions(+)
>   create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
>   create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
>   create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi
>
> diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
> new file mode 100644
> index 0000000..2bd82b2
> --- /dev/null
> +++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
> @@ -0,0 +1,17 @@
> +/*
> + * Device Tree Source for OMAP443x clock data
> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
Doing
/include/ "omap44xx-clocks.dtsi" might avoid including that header in 
corresponding SoC dtsi,
OR:
> +bandgap_fclk: bandgap_fclk@4a307888 {
> +	#clock-cells = <0>;
> +	compatible = "gate-clock";
> +	clocks = <&sys_32k_ck>;
> +	bit-shift = <8>;
> +	reg = <0x4a307888 0x4>;
> +};

Since we already have omap443x.dtsi and omap446x.dtsi, do we need 
clock.dtsi containing just a few entries?
instead we could define the delta clocks in the clocks section, and save 
on two additional files, no?

[...]

> diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
> new file mode 100644
> index 0000000..ed6bc9b
> --- /dev/null
> +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
[...]

> +dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 {
> +	#clock-cells = <0>;
> +	compatible = "divider-clock";
> +	clocks = <&dpll_abe_x2_ck>;
> +	ti,autoidle-shift = <8>;
> +	reg = <0x4a0041f0 0x4>;
> +	bit-mask = <0x1f>;
> +	index-starts-at-one;
> +	ti,autoidle-low;
> +};
> +
> +abe_24m_fclk: abe_24m_fclk {
> +	#clock-cells = <0>;
> +	compatible = "fixed-factor-clock";
> +	clocks = <&dpll_abe_m2x2_ck>;
> +	clock-mult = <1>;
> +	clock-div = <8>;
> +};
> +
> +abe_clk: abe_clk@4a004108 {
> +	#clock-cells = <0>;
> +	compatible = "divider-clock";
> +	clocks = <&dpll_abe_m2x2_ck>;
> +	reg = <0x4a004108 0x4>;
> +	bit-mask = <0x3>;
> +	index-power-of-two;
> +};
> +
> +aess_fclk: aess_fclk@4a004528 {
is there a naming convention used here? abe_clk, fclk etc?

> +	#clock-cells = <0>;
> +	compatible = "divider-clock";
> +	clocks = <&abe_clk>;
> +	bit-shift = <24>;
> +	reg = <0x4a004528 0x4>;
> +	bit-mask = <0x1>;
> +};

[...]

> +
> +ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@4a0093e0 {
_ck?

[...]


-- 
Regards,
Nishanth Menon

[PATCHv4 08/33] ARM: dts: omap4 clock data

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> This patch creates a unique node for each clock in the OMAP4 power,
> reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
> different clock tree which is taken into account in the data.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   arch/arm/boot/dts/omap443x-clocks.dtsi |   17 +
>   arch/arm/boot/dts/omap443x.dtsi        |    8 +
>   arch/arm/boot/dts/omap4460.dtsi        |    8 +
>   arch/arm/boot/dts/omap446x-clocks.dtsi |   27 +
>   arch/arm/boot/dts/omap44xx-clocks.dtsi | 1654 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/omap44xx-common-clocks.dtsi ?
>   5 files changed, 1714 insertions(+)
>   create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
>   create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
>   create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi
>
> diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
> new file mode 100644
> index 0000000..2bd82b2
> --- /dev/null
> +++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
> @@ -0,0 +1,17 @@
> +/*
> + * Device Tree Source for OMAP443x clock data
> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
Doing
/include/ "omap44xx-clocks.dtsi" might avoid including that header in 
corresponding SoC dtsi,
OR:
> +bandgap_fclk: bandgap_fclk at 4a307888 {
> +	#clock-cells = <0>;
> +	compatible = "gate-clock";
> +	clocks = <&sys_32k_ck>;
> +	bit-shift = <8>;
> +	reg = <0x4a307888 0x4>;
> +};

Since we already have omap443x.dtsi and omap446x.dtsi, do we need 
clock.dtsi containing just a few entries?
instead we could define the delta clocks in the clocks section, and save 
on two additional files, no?

[...]

> diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
> new file mode 100644
> index 0000000..ed6bc9b
> --- /dev/null
> +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
[...]

> +dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0041f0 {
> +	#clock-cells = <0>;
> +	compatible = "divider-clock";
> +	clocks = <&dpll_abe_x2_ck>;
> +	ti,autoidle-shift = <8>;
> +	reg = <0x4a0041f0 0x4>;
> +	bit-mask = <0x1f>;
> +	index-starts-at-one;
> +	ti,autoidle-low;
> +};
> +
> +abe_24m_fclk: abe_24m_fclk {
> +	#clock-cells = <0>;
> +	compatible = "fixed-factor-clock";
> +	clocks = <&dpll_abe_m2x2_ck>;
> +	clock-mult = <1>;
> +	clock-div = <8>;
> +};
> +
> +abe_clk: abe_clk at 4a004108 {
> +	#clock-cells = <0>;
> +	compatible = "divider-clock";
> +	clocks = <&dpll_abe_m2x2_ck>;
> +	reg = <0x4a004108 0x4>;
> +	bit-mask = <0x3>;
> +	index-power-of-two;
> +};
> +
> +aess_fclk: aess_fclk at 4a004528 {
is there a naming convention used here? abe_clk, fclk etc?

> +	#clock-cells = <0>;
> +	compatible = "divider-clock";
> +	clocks = <&abe_clk>;
> +	bit-shift = <24>;
> +	reg = <0x4a004528 0x4>;
> +	bit-mask = <0x1>;
> +};

[...]

> +
> +ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m at 4a0093e0 {
_ck?

[...]


-- 
Regards,
Nishanth Menon

Re: [PATCHv4 08/33] ARM: dts: omap4 clock data

[Tero Kristo]

On 07/30/2013 10:27 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> This patch creates a unique node for each clock in the OMAP4 power,
>> reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
>> different clock tree which is taken into account in the data.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   arch/arm/boot/dts/omap443x-clocks.dtsi |   17 +
>>   arch/arm/boot/dts/omap443x.dtsi        |    8 +
>>   arch/arm/boot/dts/omap4460.dtsi        |    8 +
>>   arch/arm/boot/dts/omap446x-clocks.dtsi |   27 +
>>   arch/arm/boot/dts/omap44xx-clocks.dtsi | 1654
>> ++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/omap44xx-common-clocks.dtsi ?
>>   5 files changed, 1714 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
>>   create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
>>   create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi
>>
>> diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi
>> b/arch/arm/boot/dts/omap443x-clocks.dtsi
>> new file mode 100644
>> index 0000000..2bd82b2
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
>> @@ -0,0 +1,17 @@
>> +/*
>> + * Device Tree Source for OMAP443x clock data
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
> Doing
> /include/ "omap44xx-clocks.dtsi" might avoid including that header in
> corresponding SoC dtsi,
> OR:
>> +bandgap_fclk: bandgap_fclk@4a307888 {
>> +    #clock-cells = <0>;
>> +    compatible = "gate-clock";
>> +    clocks = <&sys_32k_ck>;
>> +    bit-shift = <8>;
>> +    reg = <0x4a307888 0x4>;
>> +};
>
> Since we already have omap443x.dtsi and omap446x.dtsi, do we need
> clock.dtsi containing just a few entries?
> instead we could define the delta clocks in the clocks section, and save
> on two additional files, no?

Yea, thats also possible. I didn't want to put clock nodes there though, 
just for clarity. I think this is for whoever is maintaining the DTS 
files to answer.

>
> [...]
>
>> diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi
>> b/arch/arm/boot/dts/omap44xx-clocks.dtsi
>> new file mode 100644
>> index 0000000..ed6bc9b
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
> [...]
>
>> +dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 {
>> +    #clock-cells = <0>;
>> +    compatible = "divider-clock";
>> +    clocks = <&dpll_abe_x2_ck>;
>> +    ti,autoidle-shift = <8>;
>> +    reg = <0x4a0041f0 0x4>;
>> +    bit-mask = <0x1f>;
>> +    index-starts-at-one;
>> +    ti,autoidle-low;
>> +};
>> +
>> +abe_24m_fclk: abe_24m_fclk {
>> +    #clock-cells = <0>;
>> +    compatible = "fixed-factor-clock";
>> +    clocks = <&dpll_abe_m2x2_ck>;
>> +    clock-mult = <1>;
>> +    clock-div = <8>;
>> +};
>> +
>> +abe_clk: abe_clk@4a004108 {
>> +    #clock-cells = <0>;
>> +    compatible = "divider-clock";
>> +    clocks = <&dpll_abe_m2x2_ck>;
>> +    reg = <0x4a004108 0x4>;
>> +    bit-mask = <0x3>;
>> +    index-power-of-two;
>> +};
>> +
>> +aess_fclk: aess_fclk@4a004528 {
> is there a naming convention used here? abe_clk, fclk etc?

The clock names are directly converted from existing data, so whatever 
currently is there, will be in the DT also.

>
>> +    #clock-cells = <0>;
>> +    compatible = "divider-clock";
>> +    clocks = <&abe_clk>;
>> +    bit-shift = <24>;
>> +    reg = <0x4a004528 0x4>;
>> +    bit-mask = <0x1>;
>> +};
>
> [...]
>
>> +
>> +ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@4a0093e0 {
> _ck?
>
> [...]
>
>

[PATCHv4 08/33] ARM: dts: omap4 clock data

[Tero Kristo]

On 07/30/2013 10:27 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> This patch creates a unique node for each clock in the OMAP4 power,
>> reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
>> different clock tree which is taken into account in the data.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   arch/arm/boot/dts/omap443x-clocks.dtsi |   17 +
>>   arch/arm/boot/dts/omap443x.dtsi        |    8 +
>>   arch/arm/boot/dts/omap4460.dtsi        |    8 +
>>   arch/arm/boot/dts/omap446x-clocks.dtsi |   27 +
>>   arch/arm/boot/dts/omap44xx-clocks.dtsi | 1654
>> ++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/omap44xx-common-clocks.dtsi ?
>>   5 files changed, 1714 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi
>>   create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi
>>   create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi
>>
>> diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi
>> b/arch/arm/boot/dts/omap443x-clocks.dtsi
>> new file mode 100644
>> index 0000000..2bd82b2
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
>> @@ -0,0 +1,17 @@
>> +/*
>> + * Device Tree Source for OMAP443x clock data
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
> Doing
> /include/ "omap44xx-clocks.dtsi" might avoid including that header in
> corresponding SoC dtsi,
> OR:
>> +bandgap_fclk: bandgap_fclk at 4a307888 {
>> +    #clock-cells = <0>;
>> +    compatible = "gate-clock";
>> +    clocks = <&sys_32k_ck>;
>> +    bit-shift = <8>;
>> +    reg = <0x4a307888 0x4>;
>> +};
>
> Since we already have omap443x.dtsi and omap446x.dtsi, do we need
> clock.dtsi containing just a few entries?
> instead we could define the delta clocks in the clocks section, and save
> on two additional files, no?

Yea, thats also possible. I didn't want to put clock nodes there though, 
just for clarity. I think this is for whoever is maintaining the DTS 
files to answer.

>
> [...]
>
>> diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi
>> b/arch/arm/boot/dts/omap44xx-clocks.dtsi
>> new file mode 100644
>> index 0000000..ed6bc9b
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
> [...]
>
>> +dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0041f0 {
>> +    #clock-cells = <0>;
>> +    compatible = "divider-clock";
>> +    clocks = <&dpll_abe_x2_ck>;
>> +    ti,autoidle-shift = <8>;
>> +    reg = <0x4a0041f0 0x4>;
>> +    bit-mask = <0x1f>;
>> +    index-starts-at-one;
>> +    ti,autoidle-low;
>> +};
>> +
>> +abe_24m_fclk: abe_24m_fclk {
>> +    #clock-cells = <0>;
>> +    compatible = "fixed-factor-clock";
>> +    clocks = <&dpll_abe_m2x2_ck>;
>> +    clock-mult = <1>;
>> +    clock-div = <8>;
>> +};
>> +
>> +abe_clk: abe_clk at 4a004108 {
>> +    #clock-cells = <0>;
>> +    compatible = "divider-clock";
>> +    clocks = <&dpll_abe_m2x2_ck>;
>> +    reg = <0x4a004108 0x4>;
>> +    bit-mask = <0x3>;
>> +    index-power-of-two;
>> +};
>> +
>> +aess_fclk: aess_fclk at 4a004528 {
> is there a naming convention used here? abe_clk, fclk etc?

The clock names are directly converted from existing data, so whatever 
currently is there, will be in the DT also.

>
>> +    #clock-cells = <0>;
>> +    compatible = "divider-clock";
>> +    clocks = <&abe_clk>;
>> +    bit-shift = <24>;
>> +    reg = <0x4a004528 0x4>;
>> +    bit-mask = <0x1>;
>> +};
>
> [...]
>
>> +
>> +ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m at 4a0093e0 {
> _ck?
>
> [...]
>
>

[PATCHv4 09/33] CLK: omap: add omap4 clock init file

[Tero Kristo]

clk-44xx.c now contains the clock init functionality for omap4, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/clk-44xx.c |  118 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)
 create mode 100644 drivers/clk/omap/clk-44xx.c

diff --git a/drivers/clk/omap/clk-44xx.c b/drivers/clk/omap/clk-44xx.c
new file mode 100644
index 0000000..cc12134
--- /dev/null
+++ b/drivers/clk/omap/clk-44xx.c
@@ -0,0 +1,118 @@
+/*
+ * OMAP4 Clock data
+ *
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Mike Turquette (mturquette@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
+ *
+ * XXX All of the remaining MODULEMODE clock nodes should be removed
+ * once the drivers are updated to use pm_runtime or to use the appropriate
+ * upstream clock node for rate/parent selection.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk/omap.h>
+
+/*
+ * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
+ * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
+ * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
+ * half of this value.
+ */
+#define OMAP4_DPLL_ABE_DEFFREQ				98304000
+
+/*
+ * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
+ * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
+ * locked frequency for the USB DPLL is 960MHz.
+ */
+#define OMAP4_DPLL_USB_DEFFREQ				960000000
+
+static struct omap_dt_clk omap44xx_clks[] = {
+	DT_CLK("smp_twd",	NULL,			"mpu_periphclk"),
+	DT_CLK("omapdss_dss", "ick", "dss_fck"),
+	DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
+	DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
+	DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
+	DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
+	DT_CLK(NULL,	"timer_32k_ck",	"sys_32k_ck"),
+	/* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
+	DT_CLK("omap_timer.1",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.2",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.3",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.4",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.9",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.10",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.11",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.5",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("omap_timer.6",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("omap_timer.7",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("omap_timer.8",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4a318000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48032000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48034000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48036000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("4803e000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48086000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48088000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("40138000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4013a000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4013c000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4013e000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK(NULL,	"cpufreq_ck",	"dpll_mpu_ck"),
+};
+
+int __init omap4xxx_clk_init(void)
+{
+	int rc;
+	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
+
+	/* FIXME register clocks from DT first */
+	dt_omap_clk_init();
+
+	omap_dt_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
+
+	omap2_clk_disable_autoidle_all();
+
+	/*
+	 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
+	 * state when turning the ABE clock domain. Workaround this by
+	 * locking the ABE DPLL on boot.
+	 * Lock the ABE DPLL in any case to avoid issues with audio.
+	 */
+	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
+	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+	if (!rc)
+		rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+	/*
+	 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
+	 * domain can transition to retention state when not in use.
+	 */
+	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+	rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+	return 0;
+}
-- 
1.7.9.5

[PATCHv4 09/33] CLK: omap: add omap4 clock init file

[Tero Kristo]

clk-44xx.c now contains the clock init functionality for omap4, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/clk-44xx.c |  118 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)
 create mode 100644 drivers/clk/omap/clk-44xx.c

diff --git a/drivers/clk/omap/clk-44xx.c b/drivers/clk/omap/clk-44xx.c
new file mode 100644
index 0000000..cc12134
--- /dev/null
+++ b/drivers/clk/omap/clk-44xx.c
@@ -0,0 +1,118 @@
+/*
+ * OMAP4 Clock data
+ *
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul at pwsan.com)
+ * Rajendra Nayak (rnayak at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ * Mike Turquette (mturquette at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
+ *
+ * XXX All of the remaining MODULEMODE clock nodes should be removed
+ * once the drivers are updated to use pm_runtime or to use the appropriate
+ * upstream clock node for rate/parent selection.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk/omap.h>
+
+/*
+ * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
+ * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
+ * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
+ * half of this value.
+ */
+#define OMAP4_DPLL_ABE_DEFFREQ				98304000
+
+/*
+ * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
+ * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
+ * locked frequency for the USB DPLL is 960MHz.
+ */
+#define OMAP4_DPLL_USB_DEFFREQ				960000000
+
+static struct omap_dt_clk omap44xx_clks[] = {
+	DT_CLK("smp_twd",	NULL,			"mpu_periphclk"),
+	DT_CLK("omapdss_dss", "ick", "dss_fck"),
+	DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
+	DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
+	DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
+	DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
+	DT_CLK(NULL,	"timer_32k_ck",	"sys_32k_ck"),
+	/* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
+	DT_CLK("omap_timer.1",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.2",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.3",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.4",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.9",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.10",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.11",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("omap_timer.5",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("omap_timer.6",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("omap_timer.7",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("omap_timer.8",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4a318000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48032000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48034000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48036000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("4803e000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48086000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("48088000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
+	DT_CLK("40138000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4013a000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4013c000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK("4013e000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
+	DT_CLK(NULL,	"cpufreq_ck",	"dpll_mpu_ck"),
+};
+
+int __init omap4xxx_clk_init(void)
+{
+	int rc;
+	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
+
+	/* FIXME register clocks from DT first */
+	dt_omap_clk_init();
+
+	omap_dt_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
+
+	omap2_clk_disable_autoidle_all();
+
+	/*
+	 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
+	 * state when turning the ABE clock domain. Workaround this by
+	 * locking the ABE DPLL on boot.
+	 * Lock the ABE DPLL in any case to avoid issues with audio.
+	 */
+	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
+	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+	if (!rc)
+		rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+	/*
+	 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
+	 * domain can transition to retention state when not in use.
+	 */
+	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+	rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+	return 0;
+}
-- 
1.7.9.5

Re: [PATCHv4 09/33] CLK: omap: add omap4 clock init file

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> clk-44xx.c now contains the clock init functionality for omap4, including
> DT clock registration and adding of static clkdev entries.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/clk-44xx.c |  118 +++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 118 insertions(+)
>   create mode 100644 drivers/clk/omap/clk-44xx.c
>
> diff --git a/drivers/clk/omap/clk-44xx.c b/drivers/clk/omap/clk-44xx.c
> new file mode 100644
> index 0000000..cc12134
> --- /dev/null
> +++ b/drivers/clk/omap/clk-44xx.c
> @@ -0,0 +1,118 @@
> +/*
> + * OMAP4 Clock data
> + *
> + * Copyright (C) 2009-2012 Texas Instruments, Inc.
> + * Copyright (C) 2009-2010 Nokia Corporation
> + *
> + * Paul Walmsley (paul@pwsan.com)
> + * Rajendra Nayak (rnayak@ti.com)
> + * Benoit Cousson (b-cousson@ti.com)
> + * Mike Turquette (mturquette@ti.com)
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * XXX Some of the ES1 clocks have been removed/changed; once support
> + * is added for discriminating clocks by ES level, these should be added back
> + * in.
> + *
> + * XXX All of the remaining MODULEMODE clock nodes should be removed
> + * once the drivers are updated to use pm_runtime or to use the appropriate
> + * upstream clock node for rate/parent selection.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/clk-private.h>
> +#include <linux/clkdev.h>
> +#include <linux/io.h>
> +#include <linux/clk/omap.h>
> +
> +/*
> + * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
> + * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
> + * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
> + * half of this value.
> + */
> +#define OMAP4_DPLL_ABE_DEFFREQ				98304000
> +
> +/*
> + * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
> + * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
> + * locked frequency for the USB DPLL is 960MHz.
> + */
> +#define OMAP4_DPLL_USB_DEFFREQ				960000000
> +
> +static struct omap_dt_clk omap44xx_clks[] = {
> +	DT_CLK("smp_twd",	NULL,			"mpu_periphclk"),
> +	DT_CLK("omapdss_dss", "ick", "dss_fck"),
> +	DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
> +	DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
> +	DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
> +	DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
> +	DT_CLK(NULL,	"timer_32k_ck",	"sys_32k_ck"),
> +	/* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
> +	DT_CLK("omap_timer.1",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("omap_timer.2",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("omap_timer.3",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("omap_timer.4",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("omap_timer.9",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("omap_timer.10",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("omap_timer.11",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("omap_timer.5",	"timer_sys_ck",	"syc_clk_div_ck"),
> +	DT_CLK("omap_timer.6",	"timer_sys_ck",	"syc_clk_div_ck"),
> +	DT_CLK("omap_timer.7",	"timer_sys_ck",	"syc_clk_div_ck"),
> +	DT_CLK("omap_timer.8",	"timer_sys_ck",	"syc_clk_div_ck"),
> +	DT_CLK("4a318000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("48032000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("48034000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("48036000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("4803e000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("48086000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("48088000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("40138000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
> +	DT_CLK("4013a000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
> +	DT_CLK("4013c000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
> +	DT_CLK("4013e000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),

> +	DT_CLK(NULL,	"cpufreq_ck",	"dpll_mpu_ck"),
please remove cpufreq.

> +};
> +
> +int __init omap4xxx_clk_init(void)
> +{
> +	int rc;
> +	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
> +
> +	/* FIXME register clocks from DT first */
> +	dt_omap_clk_init();
> +
> +	omap_dt_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
> +
> +	omap2_clk_disable_autoidle_all();
> +
> +	/*
> +	 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
> +	 * state when turning the ABE clock domain. Workaround this by
> +	 * locking the ABE DPLL on boot.
> +	 * Lock the ABE DPLL in any case to avoid issues with audio.
> +	 */

But this code will be called for 4430 and 4460. if the requirement is 
only for 4460, then we are not adhering to the spec?

> +	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
> +	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
> +	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
> +	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
> +	if (!rc)
> +		rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
> +	if (rc)
> +		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
> +
> +	/*
> +	 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
> +	 * domain can transition to retention state when not in use.
> +	 */
> +	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
> +	rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
> +	if (rc)
> +		pr_err("%s: failed to configure USB DPLL!\n", __func__);

^^^^ why cant we have a generic property that does this "automagically" 
from dts property to the node?
a) be able to select a parent
b) be able to set a frequency.
c) how do we ensure that CLK_SET_RATE_PARENT are setup for the clock 
nodes defined by dt?

> +
> +	return 0;
> +}
>


-- 
Regards,
Nishanth Menon

[PATCHv4 09/33] CLK: omap: add omap4 clock init file

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> clk-44xx.c now contains the clock init functionality for omap4, including
> DT clock registration and adding of static clkdev entries.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/clk-44xx.c |  118 +++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 118 insertions(+)
>   create mode 100644 drivers/clk/omap/clk-44xx.c
>
> diff --git a/drivers/clk/omap/clk-44xx.c b/drivers/clk/omap/clk-44xx.c
> new file mode 100644
> index 0000000..cc12134
> --- /dev/null
> +++ b/drivers/clk/omap/clk-44xx.c
> @@ -0,0 +1,118 @@
> +/*
> + * OMAP4 Clock data
> + *
> + * Copyright (C) 2009-2012 Texas Instruments, Inc.
> + * Copyright (C) 2009-2010 Nokia Corporation
> + *
> + * Paul Walmsley (paul at pwsan.com)
> + * Rajendra Nayak (rnayak at ti.com)
> + * Benoit Cousson (b-cousson at ti.com)
> + * Mike Turquette (mturquette at ti.com)
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * XXX Some of the ES1 clocks have been removed/changed; once support
> + * is added for discriminating clocks by ES level, these should be added back
> + * in.
> + *
> + * XXX All of the remaining MODULEMODE clock nodes should be removed
> + * once the drivers are updated to use pm_runtime or to use the appropriate
> + * upstream clock node for rate/parent selection.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/clk-private.h>
> +#include <linux/clkdev.h>
> +#include <linux/io.h>
> +#include <linux/clk/omap.h>
> +
> +/*
> + * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
> + * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
> + * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
> + * half of this value.
> + */
> +#define OMAP4_DPLL_ABE_DEFFREQ				98304000
> +
> +/*
> + * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
> + * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
> + * locked frequency for the USB DPLL is 960MHz.
> + */
> +#define OMAP4_DPLL_USB_DEFFREQ				960000000
> +
> +static struct omap_dt_clk omap44xx_clks[] = {
> +	DT_CLK("smp_twd",	NULL,			"mpu_periphclk"),
> +	DT_CLK("omapdss_dss", "ick", "dss_fck"),
> +	DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
> +	DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
> +	DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
> +	DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
> +	DT_CLK(NULL,	"timer_32k_ck",	"sys_32k_ck"),
> +	/* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
> +	DT_CLK("omap_timer.1",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("omap_timer.2",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("omap_timer.3",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("omap_timer.4",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("omap_timer.9",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("omap_timer.10",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("omap_timer.11",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("omap_timer.5",	"timer_sys_ck",	"syc_clk_div_ck"),
> +	DT_CLK("omap_timer.6",	"timer_sys_ck",	"syc_clk_div_ck"),
> +	DT_CLK("omap_timer.7",	"timer_sys_ck",	"syc_clk_div_ck"),
> +	DT_CLK("omap_timer.8",	"timer_sys_ck",	"syc_clk_div_ck"),
> +	DT_CLK("4a318000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("48032000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("48034000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("48036000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("4803e000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("48086000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("48088000.timer",	"timer_sys_ck",	"sys_clkin_ck"),
> +	DT_CLK("40138000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
> +	DT_CLK("4013a000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
> +	DT_CLK("4013c000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),
> +	DT_CLK("4013e000.timer",	"timer_sys_ck",	"syc_clk_div_ck"),

> +	DT_CLK(NULL,	"cpufreq_ck",	"dpll_mpu_ck"),
please remove cpufreq.

> +};
> +
> +int __init omap4xxx_clk_init(void)
> +{
> +	int rc;
> +	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
> +
> +	/* FIXME register clocks from DT first */
> +	dt_omap_clk_init();
> +
> +	omap_dt_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
> +
> +	omap2_clk_disable_autoidle_all();
> +
> +	/*
> +	 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
> +	 * state when turning the ABE clock domain. Workaround this by
> +	 * locking the ABE DPLL on boot.
> +	 * Lock the ABE DPLL in any case to avoid issues with audio.
> +	 */

But this code will be called for 4430 and 4460. if the requirement is 
only for 4460, then we are not adhering to the spec?

> +	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
> +	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
> +	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
> +	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
> +	if (!rc)
> +		rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
> +	if (rc)
> +		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
> +
> +	/*
> +	 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
> +	 * domain can transition to retention state when not in use.
> +	 */
> +	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
> +	rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
> +	if (rc)
> +		pr_err("%s: failed to configure USB DPLL!\n", __func__);

^^^^ why cant we have a generic property that does this "automagically" 
from dts property to the node?
a) be able to select a parent
b) be able to set a frequency.
c) how do we ensure that CLK_SET_RATE_PARENT are setup for the clock 
nodes defined by dt?

> +
> +	return 0;
> +}
>


-- 
Regards,
Nishanth Menon

Re: [PATCHv4 09/33] CLK: omap: add omap4 clock init file

[Tero Kristo]

On 07/30/2013 10:33 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> clk-44xx.c now contains the clock init functionality for omap4, including
>> DT clock registration and adding of static clkdev entries.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/clk-44xx.c |  118
>> +++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 118 insertions(+)
>>   create mode 100644 drivers/clk/omap/clk-44xx.c
>>
>> diff --git a/drivers/clk/omap/clk-44xx.c b/drivers/clk/omap/clk-44xx.c
>> new file mode 100644
>> index 0000000..cc12134
>> --- /dev/null
>> +++ b/drivers/clk/omap/clk-44xx.c
>> @@ -0,0 +1,118 @@
>> +/*
>> + * OMAP4 Clock data
>> + *
>> + * Copyright (C) 2009-2012 Texas Instruments, Inc.
>> + * Copyright (C) 2009-2010 Nokia Corporation
>> + *
>> + * Paul Walmsley (paul@pwsan.com)
>> + * Rajendra Nayak (rnayak@ti.com)
>> + * Benoit Cousson (b-cousson@ti.com)
>> + * Mike Turquette (mturquette@ti.com)
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * XXX Some of the ES1 clocks have been removed/changed; once support
>> + * is added for discriminating clocks by ES level, these should be
>> added back
>> + * in.
>> + *
>> + * XXX All of the remaining MODULEMODE clock nodes should be removed
>> + * once the drivers are updated to use pm_runtime or to use the
>> appropriate
>> + * upstream clock node for rate/parent selection.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/list.h>
>> +#include <linux/clk-private.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/io.h>
>> +#include <linux/clk/omap.h>
>> +
>> +/*
>> + * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
>> + * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
>> + * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
>> + * half of this value.
>> + */
>> +#define OMAP4_DPLL_ABE_DEFFREQ                98304000
>> +
>> +/*
>> + * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
>> + * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
>> + * locked frequency for the USB DPLL is 960MHz.
>> + */
>> +#define OMAP4_DPLL_USB_DEFFREQ                960000000
>> +
>> +static struct omap_dt_clk omap44xx_clks[] = {
>> +    DT_CLK("smp_twd",    NULL,            "mpu_periphclk"),
>> +    DT_CLK("omapdss_dss", "ick", "dss_fck"),
>> +    DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
>> +    DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
>> +    DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
>> +    DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
>> +    DT_CLK(NULL,    "timer_32k_ck",    "sys_32k_ck"),
>> +    /* TODO: Remove "omap_timer.X" aliases once DT migration is
>> complete */
>> +    DT_CLK("omap_timer.1",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("omap_timer.2",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("omap_timer.3",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("omap_timer.4",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("omap_timer.9",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("omap_timer.10",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("omap_timer.11",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("omap_timer.5",    "timer_sys_ck",    "syc_clk_div_ck"),
>> +    DT_CLK("omap_timer.6",    "timer_sys_ck",    "syc_clk_div_ck"),
>> +    DT_CLK("omap_timer.7",    "timer_sys_ck",    "syc_clk_div_ck"),
>> +    DT_CLK("omap_timer.8",    "timer_sys_ck",    "syc_clk_div_ck"),
>> +    DT_CLK("4a318000.timer",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("48032000.timer",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("48034000.timer",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("48036000.timer",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("4803e000.timer",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("48086000.timer",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("48088000.timer",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("40138000.timer",    "timer_sys_ck",    "syc_clk_div_ck"),
>> +    DT_CLK("4013a000.timer",    "timer_sys_ck",    "syc_clk_div_ck"),
>> +    DT_CLK("4013c000.timer",    "timer_sys_ck",    "syc_clk_div_ck"),
>> +    DT_CLK("4013e000.timer",    "timer_sys_ck",    "syc_clk_div_ck"),
>
>> +    DT_CLK(NULL,    "cpufreq_ck",    "dpll_mpu_ck"),
> please remove cpufreq.

Hmm why?

Because cpufreq is completely broken now and your current work on it? :)

>
>> +};
>> +
>> +int __init omap4xxx_clk_init(void)
>> +{
>> +    int rc;
>> +    struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
>> +
>> +    /* FIXME register clocks from DT first */
>> +    dt_omap_clk_init();
>> +
>> +    omap_dt_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
>> +
>> +    omap2_clk_disable_autoidle_all();
>> +
>> +    /*
>> +     * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
>> +     * state when turning the ABE clock domain. Workaround this by
>> +     * locking the ABE DPLL on boot.
>> +     * Lock the ABE DPLL in any case to avoid issues with audio.
>> +     */
>
> But this code will be called for 4430 and 4460. if the requirement is
> only for 4460, then we are not adhering to the spec?

This is copy pasted from existing cclock44xx_data.c file init function.

>
>> +    abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
>> +    sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
>> +    rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
>> +    abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
>> +    if (!rc)
>> +        rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
>> +    if (rc)
>> +        pr_err("%s: failed to configure ABE DPLL!\n", __func__);
>> +
>> +    /*
>> +     * Lock USB DPLL on OMAP4 devices so that the L3INIT power
>> +     * domain can transition to retention state when not in use.
>> +     */
>> +    usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
>> +    rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
>> +    if (rc)
>> +        pr_err("%s: failed to configure USB DPLL!\n", __func__);
>
> ^^^^ why cant we have a generic property that does this "automagically"
> from dts property to the node?
> a) be able to select a parent
> b) be able to set a frequency.
> c) how do we ensure that CLK_SET_RATE_PARENT are setup for the clock
> nodes defined by dt?

This is probably for Mike to answer, currently such mechanism does not 
exist.

>
>> +
>> +    return 0;
>> +}
>>
>
>

[PATCHv4 09/33] CLK: omap: add omap4 clock init file

[Tero Kristo]

On 07/30/2013 10:33 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> clk-44xx.c now contains the clock init functionality for omap4, including
>> DT clock registration and adding of static clkdev entries.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/clk-44xx.c |  118
>> +++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 118 insertions(+)
>>   create mode 100644 drivers/clk/omap/clk-44xx.c
>>
>> diff --git a/drivers/clk/omap/clk-44xx.c b/drivers/clk/omap/clk-44xx.c
>> new file mode 100644
>> index 0000000..cc12134
>> --- /dev/null
>> +++ b/drivers/clk/omap/clk-44xx.c
>> @@ -0,0 +1,118 @@
>> +/*
>> + * OMAP4 Clock data
>> + *
>> + * Copyright (C) 2009-2012 Texas Instruments, Inc.
>> + * Copyright (C) 2009-2010 Nokia Corporation
>> + *
>> + * Paul Walmsley (paul at pwsan.com)
>> + * Rajendra Nayak (rnayak at ti.com)
>> + * Benoit Cousson (b-cousson at ti.com)
>> + * Mike Turquette (mturquette at ti.com)
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * XXX Some of the ES1 clocks have been removed/changed; once support
>> + * is added for discriminating clocks by ES level, these should be
>> added back
>> + * in.
>> + *
>> + * XXX All of the remaining MODULEMODE clock nodes should be removed
>> + * once the drivers are updated to use pm_runtime or to use the
>> appropriate
>> + * upstream clock node for rate/parent selection.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/list.h>
>> +#include <linux/clk-private.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/io.h>
>> +#include <linux/clk/omap.h>
>> +
>> +/*
>> + * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
>> + * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
>> + * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
>> + * half of this value.
>> + */
>> +#define OMAP4_DPLL_ABE_DEFFREQ                98304000
>> +
>> +/*
>> + * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
>> + * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
>> + * locked frequency for the USB DPLL is 960MHz.
>> + */
>> +#define OMAP4_DPLL_USB_DEFFREQ                960000000
>> +
>> +static struct omap_dt_clk omap44xx_clks[] = {
>> +    DT_CLK("smp_twd",    NULL,            "mpu_periphclk"),
>> +    DT_CLK("omapdss_dss", "ick", "dss_fck"),
>> +    DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
>> +    DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
>> +    DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
>> +    DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
>> +    DT_CLK(NULL,    "timer_32k_ck",    "sys_32k_ck"),
>> +    /* TODO: Remove "omap_timer.X" aliases once DT migration is
>> complete */
>> +    DT_CLK("omap_timer.1",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("omap_timer.2",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("omap_timer.3",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("omap_timer.4",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("omap_timer.9",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("omap_timer.10",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("omap_timer.11",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("omap_timer.5",    "timer_sys_ck",    "syc_clk_div_ck"),
>> +    DT_CLK("omap_timer.6",    "timer_sys_ck",    "syc_clk_div_ck"),
>> +    DT_CLK("omap_timer.7",    "timer_sys_ck",    "syc_clk_div_ck"),
>> +    DT_CLK("omap_timer.8",    "timer_sys_ck",    "syc_clk_div_ck"),
>> +    DT_CLK("4a318000.timer",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("48032000.timer",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("48034000.timer",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("48036000.timer",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("4803e000.timer",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("48086000.timer",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("48088000.timer",    "timer_sys_ck",    "sys_clkin_ck"),
>> +    DT_CLK("40138000.timer",    "timer_sys_ck",    "syc_clk_div_ck"),
>> +    DT_CLK("4013a000.timer",    "timer_sys_ck",    "syc_clk_div_ck"),
>> +    DT_CLK("4013c000.timer",    "timer_sys_ck",    "syc_clk_div_ck"),
>> +    DT_CLK("4013e000.timer",    "timer_sys_ck",    "syc_clk_div_ck"),
>
>> +    DT_CLK(NULL,    "cpufreq_ck",    "dpll_mpu_ck"),
> please remove cpufreq.

Hmm why?

Because cpufreq is completely broken now and your current work on it? :)

>
>> +};
>> +
>> +int __init omap4xxx_clk_init(void)
>> +{
>> +    int rc;
>> +    struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
>> +
>> +    /* FIXME register clocks from DT first */
>> +    dt_omap_clk_init();
>> +
>> +    omap_dt_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
>> +
>> +    omap2_clk_disable_autoidle_all();
>> +
>> +    /*
>> +     * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
>> +     * state when turning the ABE clock domain. Workaround this by
>> +     * locking the ABE DPLL on boot.
>> +     * Lock the ABE DPLL in any case to avoid issues with audio.
>> +     */
>
> But this code will be called for 4430 and 4460. if the requirement is
> only for 4460, then we are not adhering to the spec?

This is copy pasted from existing cclock44xx_data.c file init function.

>
>> +    abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
>> +    sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
>> +    rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
>> +    abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
>> +    if (!rc)
>> +        rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
>> +    if (rc)
>> +        pr_err("%s: failed to configure ABE DPLL!\n", __func__);
>> +
>> +    /*
>> +     * Lock USB DPLL on OMAP4 devices so that the L3INIT power
>> +     * domain can transition to retention state when not in use.
>> +     */
>> +    usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
>> +    rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
>> +    if (rc)
>> +        pr_err("%s: failed to configure USB DPLL!\n", __func__);
>
> ^^^^ why cant we have a generic property that does this "automagically"
> from dts property to the node?
> a) be able to select a parent
> b) be able to set a frequency.
> c) how do we ensure that CLK_SET_RATE_PARENT are setup for the clock
> nodes defined by dt?

This is probably for Mike to answer, currently such mechanism does not 
exist.

>
>> +
>> +    return 0;
>> +}
>>
>
>

Re: [PATCHv4 09/33] CLK: omap: add omap4 clock init file

[Nishanth Menon]

On 07/31/2013 09:52 AM, Tero Kristo wrote:
> On 07/30/2013 10:33 PM, Nishanth Menon wrote:
[...]

>>
>>> +    DT_CLK(NULL,    "cpufreq_ck",    "dpll_mpu_ck"),
>> please remove cpufreq.
>
> Hmm why?
>
> Because cpufreq is completely broken now and your current work on it? :)

cpufreq fixing can be done separately and has abillity to pick up clock 
nodes by describing clocks=<&dpll_mpu_ck> in cpu0 node. absolutely no 
need to carry on this hack - See my comment on [1]

yes, I know I will have to redo my cpufreq series, but thanks to your 
work, it is a 10 min job to enable them back online :) dont worry about 
the broken cpufreq, we will fix it properly and it is not even needed 
for basic boot to shell (example omap2plus_defconfig does not even 
enable CONFIG_CPU_FREQ).


>>
>>> +    abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
>>> +    sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
>>> +    rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
>>> +    abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
>>> +    if (!rc)
>>> +        rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
>>> +    if (rc)
>>> +        pr_err("%s: failed to configure ABE DPLL!\n", __func__);
>>> +
>>> +    /*
>>> +     * Lock USB DPLL on OMAP4 devices so that the L3INIT power
>>> +     * domain can transition to retention state when not in use.
>>> +     */
>>> +    usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
>>> +    rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
>>> +    if (rc)
>>> +        pr_err("%s: failed to configure USB DPLL!\n", __func__);
>>
>> ^^^^ why cant we have a generic property that does this "automagically"
>> from dts property to the node?
>> a) be able to select a parent
>> b) be able to set a frequency.
>> c) how do we ensure that CLK_SET_RATE_PARENT are setup for the clock
>> nodes defined by dt?
>
> This is probably for Mike to answer, currently such mechanism does not
> exist.

I think you already dealt with (c). in the same vein, we can do (a) and 
(b). Dont think anyone else has gone about this to the extent we are 
attempting to do till date, so as pioneers, we might as well suggest 
with a patch :D ?

[1] http://marc.info/?l=linux-omap&m=137536714605620&w=2
-- 
Regards,
Nishanth Menon

[PATCHv4 09/33] CLK: omap: add omap4 clock init file

[Nishanth Menon]

On 07/31/2013 09:52 AM, Tero Kristo wrote:
> On 07/30/2013 10:33 PM, Nishanth Menon wrote:
[...]

>>
>>> +    DT_CLK(NULL,    "cpufreq_ck",    "dpll_mpu_ck"),
>> please remove cpufreq.
>
> Hmm why?
>
> Because cpufreq is completely broken now and your current work on it? :)

cpufreq fixing can be done separately and has abillity to pick up clock 
nodes by describing clocks=<&dpll_mpu_ck> in cpu0 node. absolutely no 
need to carry on this hack - See my comment on [1]

yes, I know I will have to redo my cpufreq series, but thanks to your 
work, it is a 10 min job to enable them back online :) dont worry about 
the broken cpufreq, we will fix it properly and it is not even needed 
for basic boot to shell (example omap2plus_defconfig does not even 
enable CONFIG_CPU_FREQ).


>>
>>> +    abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
>>> +    sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
>>> +    rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
>>> +    abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
>>> +    if (!rc)
>>> +        rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
>>> +    if (rc)
>>> +        pr_err("%s: failed to configure ABE DPLL!\n", __func__);
>>> +
>>> +    /*
>>> +     * Lock USB DPLL on OMAP4 devices so that the L3INIT power
>>> +     * domain can transition to retention state when not in use.
>>> +     */
>>> +    usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
>>> +    rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
>>> +    if (rc)
>>> +        pr_err("%s: failed to configure USB DPLL!\n", __func__);
>>
>> ^^^^ why cant we have a generic property that does this "automagically"
>> from dts property to the node?
>> a) be able to select a parent
>> b) be able to set a frequency.
>> c) how do we ensure that CLK_SET_RATE_PARENT are setup for the clock
>> nodes defined by dt?
>
> This is probably for Mike to answer, currently such mechanism does not
> exist.

I think you already dealt with (c). in the same vein, we can do (a) and 
(b). Dont think anyone else has gone about this to the extent we are 
attempting to do till date, so as pioneers, we might as well suggest 
with a patch :D ?

[1] http://marc.info/?l=linux-omap&m=137536714605620&w=2
-- 
Regards,
Nishanth Menon

Re: [PATCHv4 09/33] CLK: omap: add omap4 clock init file

[Tero Kristo]

On 08/01/2013 05:40 PM, Nishanth Menon wrote:
> On 07/31/2013 09:52 AM, Tero Kristo wrote:
>> On 07/30/2013 10:33 PM, Nishanth Menon wrote:
> [...]
>
>>>
>>>> +    DT_CLK(NULL,    "cpufreq_ck",    "dpll_mpu_ck"),
>>> please remove cpufreq.
>>
>> Hmm why?
>>
>> Because cpufreq is completely broken now and your current work on it? :)
>
> cpufreq fixing can be done separately and has abillity to pick up clock
> nodes by describing clocks=<&dpll_mpu_ck> in cpu0 node. absolutely no
> need to carry on this hack - See my comment on [1]
>
> yes, I know I will have to redo my cpufreq series, but thanks to your
> work, it is a 10 min job to enable them back online :) dont worry about
> the broken cpufreq, we will fix it properly and it is not even needed
> for basic boot to shell (example omap2plus_defconfig does not even
> enable CONFIG_CPU_FREQ).

Ok, I'll drop the cpufreq one out at least. :)

>
>
>>>
>>>> +    abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
>>>> +    sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
>>>> +    rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
>>>> +    abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
>>>> +    if (!rc)
>>>> +        rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
>>>> +    if (rc)
>>>> +        pr_err("%s: failed to configure ABE DPLL!\n", __func__);
>>>> +
>>>> +    /*
>>>> +     * Lock USB DPLL on OMAP4 devices so that the L3INIT power
>>>> +     * domain can transition to retention state when not in use.
>>>> +     */
>>>> +    usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
>>>> +    rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
>>>> +    if (rc)
>>>> +        pr_err("%s: failed to configure USB DPLL!\n", __func__);
>>>
>>> ^^^^ why cant we have a generic property that does this "automagically"
>>> from dts property to the node?
>>> a) be able to select a parent
>>> b) be able to set a frequency.
>>> c) how do we ensure that CLK_SET_RATE_PARENT are setup for the clock
>>> nodes defined by dt?
>>
>> This is probably for Mike to answer, currently such mechanism does not
>> exist.
>
> I think you already dealt with (c). in the same vein, we can do (a) and
> (b). Dont think anyone else has gone about this to the extent we are
> attempting to do till date, so as pioneers, we might as well suggest
> with a patch :D ?

Yea, for c I have a patch as that is clearly required. For a/b, we can 
currently workaround. Again, I don't want to implement everything in 
this set at once, as the result would be a huge behemoth (this is 
complicated enough as is imo.)

>
> [1] http://marc.info/?l=linux-omap&m=137536714605620&w=2

[PATCHv4 09/33] CLK: omap: add omap4 clock init file

[Tero Kristo]

On 08/01/2013 05:40 PM, Nishanth Menon wrote:
> On 07/31/2013 09:52 AM, Tero Kristo wrote:
>> On 07/30/2013 10:33 PM, Nishanth Menon wrote:
> [...]
>
>>>
>>>> +    DT_CLK(NULL,    "cpufreq_ck",    "dpll_mpu_ck"),
>>> please remove cpufreq.
>>
>> Hmm why?
>>
>> Because cpufreq is completely broken now and your current work on it? :)
>
> cpufreq fixing can be done separately and has abillity to pick up clock
> nodes by describing clocks=<&dpll_mpu_ck> in cpu0 node. absolutely no
> need to carry on this hack - See my comment on [1]
>
> yes, I know I will have to redo my cpufreq series, but thanks to your
> work, it is a 10 min job to enable them back online :) dont worry about
> the broken cpufreq, we will fix it properly and it is not even needed
> for basic boot to shell (example omap2plus_defconfig does not even
> enable CONFIG_CPU_FREQ).

Ok, I'll drop the cpufreq one out at least. :)

>
>
>>>
>>>> +    abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
>>>> +    sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
>>>> +    rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
>>>> +    abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
>>>> +    if (!rc)
>>>> +        rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
>>>> +    if (rc)
>>>> +        pr_err("%s: failed to configure ABE DPLL!\n", __func__);
>>>> +
>>>> +    /*
>>>> +     * Lock USB DPLL on OMAP4 devices so that the L3INIT power
>>>> +     * domain can transition to retention state when not in use.
>>>> +     */
>>>> +    usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
>>>> +    rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
>>>> +    if (rc)
>>>> +        pr_err("%s: failed to configure USB DPLL!\n", __func__);
>>>
>>> ^^^^ why cant we have a generic property that does this "automagically"
>>> from dts property to the node?
>>> a) be able to select a parent
>>> b) be able to set a frequency.
>>> c) how do we ensure that CLK_SET_RATE_PARENT are setup for the clock
>>> nodes defined by dt?
>>
>> This is probably for Mike to answer, currently such mechanism does not
>> exist.
>
> I think you already dealt with (c). in the same vein, we can do (a) and
> (b). Dont think anyone else has gone about this to the extent we are
> attempting to do till date, so as pioneers, we might as well suggest
> with a patch :D ?

Yea, for c I have a patch as that is clearly required. For a/b, we can 
currently workaround. Again, I don't want to implement everything in 
this set at once, as the result would be a huge behemoth (this is 
complicated enough as is imo.)

>
> [1] http://marc.info/?l=linux-omap&m=137536714605620&w=2

Re: [PATCHv4 09/33] CLK: omap: add omap4 clock init file

[Nishanth Menon]

On Thu, Aug 1, 2013 at 10:34 AM, Tero Kristo <t-kristo@ti.com> wrote:
>>
>> I think you already dealt with (c). in the same vein, we can do (a) and
>> (b). Dont think anyone else has gone about this to the extent we are
>> attempting to do till date, so as pioneers, we might as well suggest
>> with a patch :D ?
>
>
> Yea, for c I have a patch as that is clearly required. For a/b, we can
> currently workaround. Again, I don't want to implement everything in this
> set at once, as the result would be a huge behemoth (this is complicated
> enough as is imo.)
this series will be smaller if you do it, not larger. you would just
need to introduce those parameters and not have to deal with SoC
specific "hacky drivers".
Regards,
NM

[PATCHv4 09/33] CLK: omap: add omap4 clock init file

[Nishanth Menon]

On Thu, Aug 1, 2013 at 10:34 AM, Tero Kristo <t-kristo@ti.com> wrote:
>>
>> I think you already dealt with (c). in the same vein, we can do (a) and
>> (b). Dont think anyone else has gone about this to the extent we are
>> attempting to do till date, so as pioneers, we might as well suggest
>> with a patch :D ?
>
>
> Yea, for c I have a patch as that is clearly required. For a/b, we can
> currently workaround. Again, I don't want to implement everything in this
> set at once, as the result would be a huge behemoth (this is complicated
> enough as is imo.)
this series will be smaller if you do it, not larger. you would just
need to introduce those parameters and not have to deal with SoC
specific "hacky drivers".
Regards,
NM

[PATCHv4 10/33] ARM: OMAP4: remove old clock data and link in new clock init code

[Tero Kristo]

OMAP4 clocks have now been moved to DT, thus remove the old data file
and use the new init code under drivers/clk/omap/clk-44xx.c.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/Makefile          |    2 +-
 arch/arm/mach-omap2/cclock44xx_data.c | 1730 ---------------------------------
 drivers/clk/omap/Makefile             |    3 +-
 3 files changed, 3 insertions(+), 1732 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/cclock44xx_data.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d4f6715..9f8d3ed 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -175,7 +175,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clock34xx.o clkt34xx_dpll3m2.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clock3517.o clock36xx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= dpll3xxx.o cclock3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clkt_iclk.o
-obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common) cclock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o dpll44xx.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clock-common) dpll3xxx.o
 obj-$(CONFIG_SOC_AM33XX)		+= cclock33xx_data.o
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
deleted file mode 100644
index 88e37a4..0000000
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ /dev/null
@@ -1,1730 +0,0 @@
-/*
- * OMAP4 Clock data
- *
- * Copyright (C) 2009-2012 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley (paul@pwsan.com)
- * Rajendra Nayak (rnayak@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- * Mike Turquette (mturquette@ti.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * XXX Some of the ES1 clocks have been removed/changed; once support
- * is added for discriminating clocks by ES level, these should be added back
- * in.
- *
- * XXX All of the remaining MODULEMODE clock nodes should be removed
- * once the drivers are updated to use pm_runtime or to use the appropriate
- * upstream clock node for rate/parent selection.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "clock44xx.h"
-#include "cm1_44xx.h"
-#include "cm2_44xx.h"
-#include "cm-regbits-44xx.h"
-#include "prm44xx.h"
-#include "prm-regbits-44xx.h"
-#include "control.h"
-#include "scrm44xx.h"
-
-/* OMAP4 modulemode control */
-#define OMAP4430_MODULEMODE_HWCTRL_SHIFT		0
-#define OMAP4430_MODULEMODE_SWCTRL_SHIFT		1
-
-/*
- * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
- * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
- * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
- * half of this value.
- */
-#define OMAP4_DPLL_ABE_DEFFREQ				98304000
-
-/*
- * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
- * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
- * locked frequency for the USB DPLL is 960MHz.
- */
-#define OMAP4_DPLL_USB_DEFFREQ				960000000
-
-/* Root clocks */
-
-DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
-		OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
-		OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
-
-static const char *sys_clkin_ck_parents[] = {
-	"virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
-	"virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
-	"virt_38400000_ck",
-};
-
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
-	       OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
-
-DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
-
-DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
-	       NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
-	       OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-/* DPLL_ABE */
-static struct dpll_data dpll_abe_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_ABE,
-	.clk_bypass	= &abe_dpll_bypass_clk_mux_ck,
-	.clk_ref	= &abe_dpll_refclk_mux_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_ABE,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_ABE,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_ABE,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.m4xen_mask	= OMAP4430_DPLL_REGM4XEN_MASK,
-	.lpmode_mask	= OMAP4430_DPLL_LPMODE_EN_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-
-static const char *dpll_abe_ck_parents[] = {
-	"abe_dpll_refclk_mux_ck",
-};
-
-static struct clk dpll_abe_ck;
-
-static const struct clk_ops dpll_abe_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap4_dpll_regm4xen_recalc,
-	.round_rate	= &omap4_dpll_regm4xen_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_abe_ck_hw = {
-	.hw = {
-		.clk = &dpll_abe_ck,
-	},
-	.dpll_data	= &dpll_abe_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
-
-static const char *dpll_abe_x2_ck_parents[] = {
-	"dpll_abe_ck",
-};
-
-static struct clk dpll_abe_x2_ck;
-
-static const struct clk_ops dpll_abe_x2_ck_ops = {
-	.recalc_rate	= &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_abe_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_abe_x2_ck,
-	},
-	.flags		= CLOCK_CLKOUTX2,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-static const struct clk_ops omap_hsdivider_ops = {
-	.set_rate	= &omap2_clksel_set_rate,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-};
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
-			0x0, 1, 8);
-
-DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
-		   OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
-		   OMAP4430_CM1_ABE_AESS_CLKCTRL,
-		   OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
-		   OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
-			  OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
-
-static const char *core_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "dpll_abe_m3x2_ck",
-};
-
-DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
-	       OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
-	       0x0, NULL);
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_CORE,
-	.clk_bypass	= &core_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_CORE,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_CORE,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_CORE,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-
-static const char *dpll_core_ck_parents[] = {
-	"sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
-	.recalc_rate	= &omap3_dpll_recalc,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
-	.hw = {
-		.clk = &dpll_core_ck,
-	},
-	.dpll_data	= &dpll_core_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-	"dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_core_x2_ck,
-	},
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_CORE,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
-			2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
-		   OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
-		   0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
-		   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
-		   0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
-		   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
-			0x0, 1, 2);
-
-DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
-		   OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
-		   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const struct clk_ops dpll_hsd_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static const struct clk_ops func_dmic_abe_gfclk_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-};
-
-static const char *dpll_core_m3x2_ck_parents[] = {
-	"dpll_core_x2_ck",
-};
-
-static const struct clksel dpll_core_m3x2_div[] = {
-	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
-			 OMAP4430_CM_DIV_M3_DPLL_CORE,
-			 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-			 OMAP4430_CM_DIV_M3_DPLL_CORE,
-			 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-			 dpll_core_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "div_iva_hs_clk",
-};
-
-DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
-	       OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_IVA */
-static struct dpll_data dpll_iva_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_IVA,
-	.clk_bypass	= &iva_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_IVA,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_IVA,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_IVA,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_iva_ck_parents[] = {
-	"sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_iva_ck;
-
-static const struct clk_ops dpll_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_iva_ck_hw = {
-	.hw = {
-		.clk = &dpll_iva_ck,
-	},
-	.dpll_data	= &dpll_iva_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
-
-static const char *dpll_iva_x2_ck_parents[] = {
-	"dpll_iva_ck",
-};
-
-static struct clk dpll_iva_x2_ck;
-
-static struct clk_hw_omap dpll_iva_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_iva_x2_ck,
-	},
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_MPU,
-	.clk_bypass	= &div_mpu_hs_clk,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_MPU,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_MPU,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_MPU,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_mpu_ck_parents[] = {
-	"sys_clkin_ck", "div_mpu_hs_clk"
-};
-
-static struct clk dpll_mpu_ck;
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
-	.hw = {
-		.clk = &dpll_mpu_ck,
-	},
-	.dpll_data	= &dpll_mpu_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_MPU,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
-			&dpll_abe_m3x2_ck, 0x0, 1, 2);
-
-static const char *per_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "per_hs_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
-	       OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_PER,
-	.clk_bypass	= &per_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_PER,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_PER,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_PER,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_per_ck_parents[] = {
-	"sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
-	.hw = {
-		.clk = &dpll_per_ck,
-	},
-	.dpll_data	= &dpll_per_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
-		   OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
-		   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const char *dpll_per_x2_ck_parents[] = {
-	"dpll_per_ck",
-};
-
-static struct clk dpll_per_x2_ck;
-
-static struct clk_hw_omap dpll_per_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_per_x2_ck,
-	},
-	.flags		= CLOCK_CLKOUTX2,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-static const char *dpll_per_m3x2_ck_parents[] = {
-	"dpll_per_x2_ck",
-};
-
-static const struct clksel dpll_per_m3x2_div[] = {
-	{ .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
-			 OMAP4430_CM_DIV_M3_DPLL_PER,
-			 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-			 OMAP4430_CM_DIV_M3_DPLL_PER,
-			 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-			 dpll_per_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
-			&dpll_abe_m3x2_ck, 0x0, 1, 3);
-
-/* DPLL_USB */
-static struct dpll_data dpll_usb_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_USB,
-	.clk_bypass	= &usb_hs_clk_div_ck,
-	.flags		= DPLL_J_TYPE,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_USB,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_USB,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_USB,
-	.mult_mask	= OMAP4430_DPLL_MULT_USB_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_0_7_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.sddiv_mask	= OMAP4430_DPLL_SD_DIV_MASK,
-	.max_multiplier	= 4095,
-	.max_divider	= 256,
-	.min_divider	= 1,
-};
-
-static const char *dpll_usb_ck_parents[] = {
-	"sys_clkin_ck", "usb_hs_clk_div_ck"
-};
-
-static struct clk dpll_usb_ck;
-
-static const struct clk_ops dpll_usb_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap dpll_usb_ck_hw = {
-	.hw = {
-		.clk = &dpll_usb_ck,
-	},
-	.dpll_data	= &dpll_usb_dd,
-	.clkdm_name	= "l3_init_clkdm",
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
-
-static const char *dpll_usb_clkdcoldo_ck_parents[] = {
-	"dpll_usb_ck",
-};
-
-static struct clk dpll_usb_clkdcoldo_ck;
-
-static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
-};
-
-static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
-	.hw = {
-		.clk = &dpll_usb_clkdcoldo_ck,
-	},
-	.clksel_reg	= OMAP4430_CM_CLKDCOLDO_DPLL_USB,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
-		  dpll_usb_clkdcoldo_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_USB,
-			  OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
-
-static const char *ducati_clk_mux_ck_parents[] = {
-	"div_core_ck", "dpll_per_m6x2_ck",
-};
-
-DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 16);
-
-DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
-			1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 8);
-
-static const struct clk_div_table func_48m_fclk_rates[] = {
-	{ .div = 4, .val = 0 },
-	{ .div = 8, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
-			 NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk,	"dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 4);
-
-static const struct clk_div_table func_64m_fclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 4, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
-			 NULL);
-
-static const struct clk_div_table func_96m_fclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 4, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
-			 NULL);
-
-static const struct clk_div_table init_60m_fclk_rates[] = {
-	{ .div = 1, .val = 0 },
-	{ .div = 8, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
-			 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
-			 OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
-			 0x0, init_60m_fclk_rates, NULL);
-
-DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
-		   OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
-		   OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
-			0x0, 1, 16);
-
-static const char *l4_wkup_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "lp_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const struct clk_div_table ocp_abe_iclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 1, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
-			 OMAP4430_CM1_ABE_AESS_CLKCTRL,
-			 OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
-			 OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
-			 0x0, ocp_abe_iclk_rates, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
-			0x0, 1, 4);
-
-DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
-		   OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-		   OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-		   OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-		   OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const char *dbgclk_mux_ck_parents[] = {
-	"sys_clkin_ck"
-};
-
-static struct clk dbgclk_mux_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
-DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
-		  dpll_usb_clkdcoldo_ck_ops);
-
-/* Leaf clocks controlled by modules */
-
-DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_AES1_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_AES2_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-		OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table div_ts_ck_rates[] = {
-	{ .div = 8, .val = 0 },
-	{ .div = 16, .val = 1 },
-	{ .div = 32, .val = 2 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-			 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-			 OMAP4430_CLKSEL_24_25_SHIFT,
-			 OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
-			 NULL);
-
-DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
-		OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-		OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
-		0x0, NULL);
-
-static const char *dmic_sync_mux_ck_parents[] = {
-	"abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
-};
-
-DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_dmic_abe_gfclk_sel[] = {
-	{ .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_dmic_abe_gfclk_parents[] = {
-	"dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
-		    OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-		    func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
-		   OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
-		   OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-		OMAP4430_OPTFCLKEN_DBCLK_SHIFT,	0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-		OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-static const struct clksel sgx_clk_mux_sel[] = {
-	{ .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *sgx_clk_mux_parents[] = {
-	"dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
-		    OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
-		    sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
-		   OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
-		   OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
-		OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcasp_abe_gfclk_sel[] = {
-	{ .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcasp_abe_gfclk_parents[] = {
-	"mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-		    func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp1_gfclk_sel[] = {
-	{ .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp1_gfclk_parents[] = {
-	"mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp2_gfclk_sel[] = {
-	{ .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp2_gfclk_parents[] = {
-	"mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp3_gfclk_sel[] = {
-	{ .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp3_gfclk_parents[] = {
-	"mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const char *mcbsp4_sync_mux_ck_parents[] = {
-	"func_96m_fclk", "per_abe_nc_fclk",
-};
-
-DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel per_mcbsp4_gfclk_sel[] = {
-	{ .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *per_mcbsp4_gfclk_parents[] = {
-	"mcbsp4_sync_mux_ck", "pad_clks_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
-		    OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const struct clksel hsmmc1_fclk_sel[] = {
-	{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
-	{ .parent = &func_96m_fclk, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *hsmmc1_fclk_parents[] = {
-	"func_64m_fclk", "func_96m_fclk",
-};
-
-DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-		    OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-		    OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
-		&pad_slimbus_core_clks_ck, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clksel dmt1_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const struct clksel timer5_sync_mux_sel[] = {
-	{ .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *timer5_sync_mux_parents[] = {
-	"syc_clk_div_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static struct clk usb_host_fs_fck;
-
-static const char *usb_host_fs_fck_parent_names[] = {
-	"func_48mc_fclk",
-};
-
-static const struct clk_ops usb_host_fs_fck_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-};
-
-static struct clk_hw_omap usb_host_fs_fck_hw = {
-	.hw = {
-		.clk = &usb_host_fs_fck,
-	},
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-};
-
-DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
-		  usb_host_fs_fck_ops);
-
-static const char *utmi_p1_gfclk_parents[] = {
-	"init_60m_fclk", "xclk60mhsp1_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	       OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
-
-static const char *utmi_p2_gfclk_parents[] = {
-	"init_60m_fclk", "xclk60mhsp2_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	       OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
-		&dpll_usb_m2_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
-		&init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
-		&init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
-		&dpll_usb_m2_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const char *otg_60m_gfclk_parents[] = {
-	"utmi_phy_clkout_ck", "xclk60motg_ck",
-};
-
-DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
-	       OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-		OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-		OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
-		OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table usim_ck_rates[] = {
-	{ .div = 14, .val = 0 },
-	{ .div = 18, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
-			 OMAP4430_CM_WKUP_USIM_CLKCTRL,
-			 OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
-			 0x0, usim_ck_rates, NULL);
-
-DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
-		OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
-		0x0, NULL);
-
-/* Remaining optional clocks */
-static const char *pmd_stm_clock_mux_ck_parents[] = {
-	"sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
-};
-
-DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
-	       OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	       OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
-	       OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
-		   &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-		   OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
-		   OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-static const char *trace_clk_div_ck_parents[] = {
-	"pmd_trace_clk_mux_ck",
-};
-
-static const struct clksel trace_clk_div_div[] = {
-	{ .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
-
-static struct clk trace_clk_div_ck;
-
-static const struct clk_ops trace_clk_div_ck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.set_rate	= &omap2_clksel_set_rate,
-	.round_rate	= &omap2_clksel_round_rate,
-	.init		= &omap2_init_clk_clkdm,
-	.enable		= &omap2_clkops_enable_clkdm,
-	.disable	= &omap2_clkops_disable_clkdm,
-};
-
-static struct clk_hw_omap trace_clk_div_ck_hw = {
-	.hw = {
-		.clk = &trace_clk_div_ck,
-	},
-	.clkdm_name	= "emu_sys_clkdm",
-	.clksel		= trace_clk_div_div,
-	.clksel_reg	= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
-		  trace_clk_div_ck_ops);
-
-/* SCRM aux clk nodes */
-
-static const struct clksel auxclk_src_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
-	{ .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *auxclk_src_ck_parents[] = {
-	"sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
-};
-
-static const struct clk_ops auxclk_src_ck_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-static const char *auxclkreq_ck_parents[] = {
-	"auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
-	"auxclk5_ck",
-};
-
-DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-/*
- * clocks specific to omap4460
- */
-static struct omap_clk omap446x_clks[] = {
-	CLK(NULL,	"div_ts_ck",			&div_ts_ck),
-	CLK(NULL,	"bandgap_ts_fclk",		&bandgap_ts_fclk),
-};
-
-/*
- * clocks specific to omap4430
- */
-static struct omap_clk omap443x_clks[] = {
-	CLK(NULL,	"bandgap_fclk",			&bandgap_fclk),
-};
-
-/*
- * clocks common to omap44xx
- */
-static struct omap_clk omap44xx_clks[] = {
-	CLK(NULL,	"extalt_clkin_ck",		&extalt_clkin_ck),
-	CLK(NULL,	"pad_clks_src_ck",		&pad_clks_src_ck),
-	CLK(NULL,	"pad_clks_ck",			&pad_clks_ck),
-	CLK(NULL,	"pad_slimbus_core_clks_ck",	&pad_slimbus_core_clks_ck),
-	CLK(NULL,	"secure_32k_clk_src_ck",	&secure_32k_clk_src_ck),
-	CLK(NULL,	"slimbus_src_clk",		&slimbus_src_clk),
-	CLK(NULL,	"slimbus_clk",			&slimbus_clk),
-	CLK(NULL,	"sys_32k_ck",			&sys_32k_ck),
-	CLK(NULL,	"virt_12000000_ck",		&virt_12000000_ck),
-	CLK(NULL,	"virt_13000000_ck",		&virt_13000000_ck),
-	CLK(NULL,	"virt_16800000_ck",		&virt_16800000_ck),
-	CLK(NULL,	"virt_19200000_ck",		&virt_19200000_ck),
-	CLK(NULL,	"virt_26000000_ck",		&virt_26000000_ck),
-	CLK(NULL,	"virt_27000000_ck",		&virt_27000000_ck),
-	CLK(NULL,	"virt_38400000_ck",		&virt_38400000_ck),
-	CLK(NULL,	"sys_clkin_ck",			&sys_clkin_ck),
-	CLK(NULL,	"tie_low_clock_ck",		&tie_low_clock_ck),
-	CLK(NULL,	"utmi_phy_clkout_ck",		&utmi_phy_clkout_ck),
-	CLK(NULL,	"xclk60mhsp1_ck",		&xclk60mhsp1_ck),
-	CLK(NULL,	"xclk60mhsp2_ck",		&xclk60mhsp2_ck),
-	CLK(NULL,	"xclk60motg_ck",		&xclk60motg_ck),
-	CLK(NULL,	"abe_dpll_bypass_clk_mux_ck",	&abe_dpll_bypass_clk_mux_ck),
-	CLK(NULL,	"abe_dpll_refclk_mux_ck",	&abe_dpll_refclk_mux_ck),
-	CLK(NULL,	"dpll_abe_ck",			&dpll_abe_ck),
-	CLK(NULL,	"dpll_abe_x2_ck",		&dpll_abe_x2_ck),
-	CLK(NULL,	"dpll_abe_m2x2_ck",		&dpll_abe_m2x2_ck),
-	CLK(NULL,	"abe_24m_fclk",			&abe_24m_fclk),
-	CLK(NULL,	"abe_clk",			&abe_clk),
-	CLK(NULL,	"aess_fclk",			&aess_fclk),
-	CLK(NULL,	"dpll_abe_m3x2_ck",		&dpll_abe_m3x2_ck),
-	CLK(NULL,	"core_hsd_byp_clk_mux_ck",	&core_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_core_ck",			&dpll_core_ck),
-	CLK(NULL,	"dpll_core_x2_ck",		&dpll_core_x2_ck),
-	CLK(NULL,	"dpll_core_m6x2_ck",		&dpll_core_m6x2_ck),
-	CLK(NULL,	"dbgclk_mux_ck",		&dbgclk_mux_ck),
-	CLK(NULL,	"dpll_core_m2_ck",		&dpll_core_m2_ck),
-	CLK(NULL,	"ddrphy_ck",			&ddrphy_ck),
-	CLK(NULL,	"dpll_core_m5x2_ck",		&dpll_core_m5x2_ck),
-	CLK(NULL,	"div_core_ck",			&div_core_ck),
-	CLK(NULL,	"div_iva_hs_clk",		&div_iva_hs_clk),
-	CLK(NULL,	"div_mpu_hs_clk",		&div_mpu_hs_clk),
-	CLK(NULL,	"dpll_core_m4x2_ck",		&dpll_core_m4x2_ck),
-	CLK(NULL,	"dll_clk_div_ck",		&dll_clk_div_ck),
-	CLK(NULL,	"dpll_abe_m2_ck",		&dpll_abe_m2_ck),
-	CLK(NULL,	"dpll_core_m3x2_ck",		&dpll_core_m3x2_ck),
-	CLK(NULL,	"dpll_core_m7x2_ck",		&dpll_core_m7x2_ck),
-	CLK(NULL,	"iva_hsd_byp_clk_mux_ck",	&iva_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_iva_ck",			&dpll_iva_ck),
-	CLK(NULL,	"dpll_iva_x2_ck",		&dpll_iva_x2_ck),
-	CLK(NULL,	"dpll_iva_m4x2_ck",		&dpll_iva_m4x2_ck),
-	CLK(NULL,	"dpll_iva_m5x2_ck",		&dpll_iva_m5x2_ck),
-	CLK(NULL,	"dpll_mpu_ck",			&dpll_mpu_ck),
-	CLK(NULL,	"dpll_mpu_m2_ck",		&dpll_mpu_m2_ck),
-	CLK(NULL,	"per_hs_clk_div_ck",		&per_hs_clk_div_ck),
-	CLK(NULL,	"per_hsd_byp_clk_mux_ck",	&per_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_per_ck",			&dpll_per_ck),
-	CLK(NULL,	"dpll_per_m2_ck",		&dpll_per_m2_ck),
-	CLK(NULL,	"dpll_per_x2_ck",		&dpll_per_x2_ck),
-	CLK(NULL,	"dpll_per_m2x2_ck",		&dpll_per_m2x2_ck),
-	CLK(NULL,	"dpll_per_m3x2_ck",		&dpll_per_m3x2_ck),
-	CLK(NULL,	"dpll_per_m4x2_ck",		&dpll_per_m4x2_ck),
-	CLK(NULL,	"dpll_per_m5x2_ck",		&dpll_per_m5x2_ck),
-	CLK(NULL,	"dpll_per_m6x2_ck",		&dpll_per_m6x2_ck),
-	CLK(NULL,	"dpll_per_m7x2_ck",		&dpll_per_m7x2_ck),
-	CLK(NULL,	"usb_hs_clk_div_ck",		&usb_hs_clk_div_ck),
-	CLK(NULL,	"dpll_usb_ck",			&dpll_usb_ck),
-	CLK(NULL,	"dpll_usb_clkdcoldo_ck",	&dpll_usb_clkdcoldo_ck),
-	CLK(NULL,	"dpll_usb_m2_ck",		&dpll_usb_m2_ck),
-	CLK(NULL,	"ducati_clk_mux_ck",		&ducati_clk_mux_ck),
-	CLK(NULL,	"func_12m_fclk",		&func_12m_fclk),
-	CLK(NULL,	"func_24m_clk",			&func_24m_clk),
-	CLK(NULL,	"func_24mc_fclk",		&func_24mc_fclk),
-	CLK(NULL,	"func_48m_fclk",		&func_48m_fclk),
-	CLK(NULL,	"func_48mc_fclk",		&func_48mc_fclk),
-	CLK(NULL,	"func_64m_fclk",		&func_64m_fclk),
-	CLK(NULL,	"func_96m_fclk",		&func_96m_fclk),
-	CLK(NULL,	"init_60m_fclk",		&init_60m_fclk),
-	CLK(NULL,	"l3_div_ck",			&l3_div_ck),
-	CLK(NULL,	"l4_div_ck",			&l4_div_ck),
-	CLK(NULL,	"lp_clk_div_ck",		&lp_clk_div_ck),
-	CLK(NULL,	"l4_wkup_clk_mux_ck",		&l4_wkup_clk_mux_ck),
-	CLK("smp_twd",	NULL,				&mpu_periphclk),
-	CLK(NULL,	"ocp_abe_iclk",			&ocp_abe_iclk),
-	CLK(NULL,	"per_abe_24m_fclk",		&per_abe_24m_fclk),
-	CLK(NULL,	"per_abe_nc_fclk",		&per_abe_nc_fclk),
-	CLK(NULL,	"syc_clk_div_ck",		&syc_clk_div_ck),
-	CLK(NULL,	"aes1_fck",			&aes1_fck),
-	CLK(NULL,	"aes2_fck",			&aes2_fck),
-	CLK(NULL,	"dmic_sync_mux_ck",		&dmic_sync_mux_ck),
-	CLK(NULL,	"func_dmic_abe_gfclk",		&func_dmic_abe_gfclk),
-	CLK(NULL,	"dss_sys_clk",			&dss_sys_clk),
-	CLK(NULL,	"dss_tv_clk",			&dss_tv_clk),
-	CLK(NULL,	"dss_dss_clk",			&dss_dss_clk),
-	CLK(NULL,	"dss_48mhz_clk",		&dss_48mhz_clk),
-	CLK(NULL,	"dss_fck",			&dss_fck),
-	CLK("omapdss_dss",	"ick",			&dss_fck),
-	CLK(NULL,	"fdif_fck",			&fdif_fck),
-	CLK(NULL,	"gpio1_dbclk",			&gpio1_dbclk),
-	CLK(NULL,	"gpio2_dbclk",			&gpio2_dbclk),
-	CLK(NULL,	"gpio3_dbclk",			&gpio3_dbclk),
-	CLK(NULL,	"gpio4_dbclk",			&gpio4_dbclk),
-	CLK(NULL,	"gpio5_dbclk",			&gpio5_dbclk),
-	CLK(NULL,	"gpio6_dbclk",			&gpio6_dbclk),
-	CLK(NULL,	"sgx_clk_mux",			&sgx_clk_mux),
-	CLK(NULL,	"hsi_fck",			&hsi_fck),
-	CLK(NULL,	"iss_ctrlclk",			&iss_ctrlclk),
-	CLK(NULL,	"mcasp_sync_mux_ck",		&mcasp_sync_mux_ck),
-	CLK(NULL,	"func_mcasp_abe_gfclk",		&func_mcasp_abe_gfclk),
-	CLK(NULL,	"mcbsp1_sync_mux_ck",		&mcbsp1_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp1_gfclk",		&func_mcbsp1_gfclk),
-	CLK(NULL,	"mcbsp2_sync_mux_ck",		&mcbsp2_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp2_gfclk",		&func_mcbsp2_gfclk),
-	CLK(NULL,	"mcbsp3_sync_mux_ck",		&mcbsp3_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp3_gfclk",		&func_mcbsp3_gfclk),
-	CLK(NULL,	"mcbsp4_sync_mux_ck",		&mcbsp4_sync_mux_ck),
-	CLK(NULL,	"per_mcbsp4_gfclk",		&per_mcbsp4_gfclk),
-	CLK(NULL,	"hsmmc1_fclk",			&hsmmc1_fclk),
-	CLK(NULL,	"hsmmc2_fclk",			&hsmmc2_fclk),
-	CLK(NULL,	"ocp2scp_usb_phy_phy_48m",	&ocp2scp_usb_phy_phy_48m),
-	CLK(NULL,	"sha2md5_fck",			&sha2md5_fck),
-	CLK(NULL,	"slimbus1_fclk_1",		&slimbus1_fclk_1),
-	CLK(NULL,	"slimbus1_fclk_0",		&slimbus1_fclk_0),
-	CLK(NULL,	"slimbus1_fclk_2",		&slimbus1_fclk_2),
-	CLK(NULL,	"slimbus1_slimbus_clk",		&slimbus1_slimbus_clk),
-	CLK(NULL,	"slimbus2_fclk_1",		&slimbus2_fclk_1),
-	CLK(NULL,	"slimbus2_fclk_0",		&slimbus2_fclk_0),
-	CLK(NULL,	"slimbus2_slimbus_clk",		&slimbus2_slimbus_clk),
-	CLK(NULL,	"smartreflex_core_fck",		&smartreflex_core_fck),
-	CLK(NULL,	"smartreflex_iva_fck",		&smartreflex_iva_fck),
-	CLK(NULL,	"smartreflex_mpu_fck",		&smartreflex_mpu_fck),
-	CLK(NULL,	"dmt1_clk_mux",			&dmt1_clk_mux),
-	CLK(NULL,	"cm2_dm10_mux",			&cm2_dm10_mux),
-	CLK(NULL,	"cm2_dm11_mux",			&cm2_dm11_mux),
-	CLK(NULL,	"cm2_dm2_mux",			&cm2_dm2_mux),
-	CLK(NULL,	"cm2_dm3_mux",			&cm2_dm3_mux),
-	CLK(NULL,	"cm2_dm4_mux",			&cm2_dm4_mux),
-	CLK(NULL,	"timer5_sync_mux",		&timer5_sync_mux),
-	CLK(NULL,	"timer6_sync_mux",		&timer6_sync_mux),
-	CLK(NULL,	"timer7_sync_mux",		&timer7_sync_mux),
-	CLK(NULL,	"timer8_sync_mux",		&timer8_sync_mux),
-	CLK(NULL,	"cm2_dm9_mux",			&cm2_dm9_mux),
-	CLK(NULL,	"usb_host_fs_fck",		&usb_host_fs_fck),
-	CLK("usbhs_omap",	"fs_fck",		&usb_host_fs_fck),
-	CLK(NULL,	"utmi_p1_gfclk",		&utmi_p1_gfclk),
-	CLK(NULL,	"usb_host_hs_utmi_p1_clk",	&usb_host_hs_utmi_p1_clk),
-	CLK(NULL,	"utmi_p2_gfclk",		&utmi_p2_gfclk),
-	CLK(NULL,	"usb_host_hs_utmi_p2_clk",	&usb_host_hs_utmi_p2_clk),
-	CLK(NULL,	"usb_host_hs_utmi_p3_clk",	&usb_host_hs_utmi_p3_clk),
-	CLK(NULL,	"usb_host_hs_hsic480m_p1_clk",	&usb_host_hs_hsic480m_p1_clk),
-	CLK(NULL,	"usb_host_hs_hsic60m_p1_clk",	&usb_host_hs_hsic60m_p1_clk),
-	CLK(NULL,	"usb_host_hs_hsic60m_p2_clk",	&usb_host_hs_hsic60m_p2_clk),
-	CLK(NULL,	"usb_host_hs_hsic480m_p2_clk",	&usb_host_hs_hsic480m_p2_clk),
-	CLK(NULL,	"usb_host_hs_func48mclk",	&usb_host_hs_func48mclk),
-	CLK(NULL,	"usb_host_hs_fck",		&usb_host_hs_fck),
-	CLK("usbhs_omap",	"hs_fck",		&usb_host_hs_fck),
-	CLK(NULL,	"otg_60m_gfclk",		&otg_60m_gfclk),
-	CLK(NULL,	"usb_otg_hs_xclk",		&usb_otg_hs_xclk),
-	CLK(NULL,	"usb_otg_hs_ick",		&usb_otg_hs_ick),
-	CLK("musb-omap2430",	"ick",			&usb_otg_hs_ick),
-	CLK(NULL,	"usb_phy_cm_clk32k",		&usb_phy_cm_clk32k),
-	CLK(NULL,	"usb_tll_hs_usb_ch2_clk",	&usb_tll_hs_usb_ch2_clk),
-	CLK(NULL,	"usb_tll_hs_usb_ch0_clk",	&usb_tll_hs_usb_ch0_clk),
-	CLK(NULL,	"usb_tll_hs_usb_ch1_clk",	&usb_tll_hs_usb_ch1_clk),
-	CLK(NULL,	"usb_tll_hs_ick",		&usb_tll_hs_ick),
-	CLK("usbhs_omap",	"usbtll_ick",		&usb_tll_hs_ick),
-	CLK("usbhs_tll",	"usbtll_ick",		&usb_tll_hs_ick),
-	CLK(NULL,	"usim_ck",			&usim_ck),
-	CLK(NULL,	"usim_fclk",			&usim_fclk),
-	CLK(NULL,	"pmd_stm_clock_mux_ck",		&pmd_stm_clock_mux_ck),
-	CLK(NULL,	"pmd_trace_clk_mux_ck",		&pmd_trace_clk_mux_ck),
-	CLK(NULL,	"stm_clk_div_ck",		&stm_clk_div_ck),
-	CLK(NULL,	"trace_clk_div_ck",		&trace_clk_div_ck),
-	CLK(NULL,	"auxclk0_src_ck",		&auxclk0_src_ck),
-	CLK(NULL,	"auxclk0_ck",			&auxclk0_ck),
-	CLK(NULL,	"auxclkreq0_ck",		&auxclkreq0_ck),
-	CLK(NULL,	"auxclk1_src_ck",		&auxclk1_src_ck),
-	CLK(NULL,	"auxclk1_ck",			&auxclk1_ck),
-	CLK(NULL,	"auxclkreq1_ck",		&auxclkreq1_ck),
-	CLK(NULL,	"auxclk2_src_ck",		&auxclk2_src_ck),
-	CLK(NULL,	"auxclk2_ck",			&auxclk2_ck),
-	CLK(NULL,	"auxclkreq2_ck",		&auxclkreq2_ck),
-	CLK(NULL,	"auxclk3_src_ck",		&auxclk3_src_ck),
-	CLK(NULL,	"auxclk3_ck",			&auxclk3_ck),
-	CLK(NULL,	"auxclkreq3_ck",		&auxclkreq3_ck),
-	CLK(NULL,	"auxclk4_src_ck",		&auxclk4_src_ck),
-	CLK(NULL,	"auxclk4_ck",			&auxclk4_ck),
-	CLK(NULL,	"auxclkreq4_ck",		&auxclkreq4_ck),
-	CLK(NULL,	"auxclk5_src_ck",		&auxclk5_src_ck),
-	CLK(NULL,	"auxclk5_ck",			&auxclk5_ck),
-	CLK(NULL,	"auxclkreq5_ck",		&auxclkreq5_ck),
-	CLK("omap-gpmc",	"fck",			&dummy_ck),
-	CLK("omap_i2c.1",	"ick",			&dummy_ck),
-	CLK("omap_i2c.2",	"ick",			&dummy_ck),
-	CLK("omap_i2c.3",	"ick",			&dummy_ck),
-	CLK("omap_i2c.4",	"ick",			&dummy_ck),
-	CLK(NULL,	"mailboxes_ick",		&dummy_ck),
-	CLK("omap_hsmmc.0",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.1",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.2",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.3",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.4",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.1",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.2",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.3",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.4",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.1",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.2",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.3",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.4",	"ick",			&dummy_ck),
-	CLK(NULL,	"uart1_ick",			&dummy_ck),
-	CLK(NULL,	"uart2_ick",			&dummy_ck),
-	CLK(NULL,	"uart3_ick",			&dummy_ck),
-	CLK(NULL,	"uart4_ick",			&dummy_ck),
-	CLK("usbhs_omap",	"usbhost_ick",		&dummy_ck),
-	CLK("usbhs_omap",	"usbtll_fck",		&dummy_ck),
-	CLK("usbhs_tll",	"usbtll_fck",		&dummy_ck),
-	CLK("omap_wdt",	"ick",				&dummy_ck),
-	CLK(NULL,	"timer_32k_ck",	&sys_32k_ck),
-	/* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
-	CLK("omap_timer.1",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.2",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.3",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.4",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.9",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.10",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.11",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.5",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.6",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.7",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.8",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4a318000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48032000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48034000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48036000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("4803e000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48086000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48088000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("40138000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013a000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013c000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013e000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK(NULL,	"cpufreq_ck",	&dpll_mpu_ck),
-};
-
-int __init omap4xxx_clk_init(void)
-{
-	int rc;
-
-	if (cpu_is_omap443x()) {
-		cpu_mask = RATE_IN_4430;
-		omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
-	} else if (cpu_is_omap446x() || cpu_is_omap447x()) {
-		cpu_mask = RATE_IN_4460 | RATE_IN_4430;
-		omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
-		if (cpu_is_omap447x())
-			pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
-	} else {
-		return 0;
-	}
-
-	omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
-
-	omap2_clk_disable_autoidle_all();
-
-	/*
-	 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
-	 * state when turning the ABE clock domain. Workaround this by
-	 * locking the ABE DPLL on boot.
-	 * Lock the ABE DPLL in any case to avoid issues with audio.
-	 */
-	rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
-	if (!rc)
-		rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
-	if (rc)
-		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
-
-	/*
-	 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
-	 * domain can transition to retention state when not in use.
-	 */
-	rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
-	if (rc)
-		pr_err("%s: failed to configure USB DPLL!\n", __func__);
-
-	return 0;
-}
diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index 3d3ca30f..9ad10be 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1 +1,2 @@
-obj-y					+= clk.o dpll.o autoidle.o gate.o
+obj-y					+= clk.o dpll.o autoidle.o gate.o \
+					   clk-44xx.o
-- 
1.7.9.5

[PATCHv4 10/33] ARM: OMAP4: remove old clock data and link in new clock init code

[Tero Kristo]

OMAP4 clocks have now been moved to DT, thus remove the old data file
and use the new init code under drivers/clk/omap/clk-44xx.c.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/Makefile          |    2 +-
 arch/arm/mach-omap2/cclock44xx_data.c | 1730 ---------------------------------
 drivers/clk/omap/Makefile             |    3 +-
 3 files changed, 3 insertions(+), 1732 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/cclock44xx_data.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d4f6715..9f8d3ed 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -175,7 +175,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clock34xx.o clkt34xx_dpll3m2.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clock3517.o clock36xx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= dpll3xxx.o cclock3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clkt_iclk.o
-obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common) cclock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o dpll44xx.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clock-common) dpll3xxx.o
 obj-$(CONFIG_SOC_AM33XX)		+= cclock33xx_data.o
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
deleted file mode 100644
index 88e37a4..0000000
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ /dev/null
@@ -1,1730 +0,0 @@
-/*
- * OMAP4 Clock data
- *
- * Copyright (C) 2009-2012 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley (paul at pwsan.com)
- * Rajendra Nayak (rnayak at ti.com)
- * Benoit Cousson (b-cousson at ti.com)
- * Mike Turquette (mturquette at ti.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * XXX Some of the ES1 clocks have been removed/changed; once support
- * is added for discriminating clocks by ES level, these should be added back
- * in.
- *
- * XXX All of the remaining MODULEMODE clock nodes should be removed
- * once the drivers are updated to use pm_runtime or to use the appropriate
- * upstream clock node for rate/parent selection.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "clock44xx.h"
-#include "cm1_44xx.h"
-#include "cm2_44xx.h"
-#include "cm-regbits-44xx.h"
-#include "prm44xx.h"
-#include "prm-regbits-44xx.h"
-#include "control.h"
-#include "scrm44xx.h"
-
-/* OMAP4 modulemode control */
-#define OMAP4430_MODULEMODE_HWCTRL_SHIFT		0
-#define OMAP4430_MODULEMODE_SWCTRL_SHIFT		1
-
-/*
- * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
- * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
- * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
- * half of this value.
- */
-#define OMAP4_DPLL_ABE_DEFFREQ				98304000
-
-/*
- * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
- * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
- * locked frequency for the USB DPLL is 960MHz.
- */
-#define OMAP4_DPLL_USB_DEFFREQ				960000000
-
-/* Root clocks */
-
-DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
-		OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
-		OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
-
-static const char *sys_clkin_ck_parents[] = {
-	"virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
-	"virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
-	"virt_38400000_ck",
-};
-
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
-	       OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
-
-DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
-
-DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
-	       NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
-	       OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-/* DPLL_ABE */
-static struct dpll_data dpll_abe_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_ABE,
-	.clk_bypass	= &abe_dpll_bypass_clk_mux_ck,
-	.clk_ref	= &abe_dpll_refclk_mux_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_ABE,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_ABE,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_ABE,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.m4xen_mask	= OMAP4430_DPLL_REGM4XEN_MASK,
-	.lpmode_mask	= OMAP4430_DPLL_LPMODE_EN_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-
-static const char *dpll_abe_ck_parents[] = {
-	"abe_dpll_refclk_mux_ck",
-};
-
-static struct clk dpll_abe_ck;
-
-static const struct clk_ops dpll_abe_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap4_dpll_regm4xen_recalc,
-	.round_rate	= &omap4_dpll_regm4xen_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_abe_ck_hw = {
-	.hw = {
-		.clk = &dpll_abe_ck,
-	},
-	.dpll_data	= &dpll_abe_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
-
-static const char *dpll_abe_x2_ck_parents[] = {
-	"dpll_abe_ck",
-};
-
-static struct clk dpll_abe_x2_ck;
-
-static const struct clk_ops dpll_abe_x2_ck_ops = {
-	.recalc_rate	= &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_abe_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_abe_x2_ck,
-	},
-	.flags		= CLOCK_CLKOUTX2,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-static const struct clk_ops omap_hsdivider_ops = {
-	.set_rate	= &omap2_clksel_set_rate,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-};
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
-			0x0, 1, 8);
-
-DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
-		   OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
-		   OMAP4430_CM1_ABE_AESS_CLKCTRL,
-		   OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
-		   OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
-			  OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
-
-static const char *core_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "dpll_abe_m3x2_ck",
-};
-
-DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
-	       OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
-	       0x0, NULL);
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_CORE,
-	.clk_bypass	= &core_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_CORE,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_CORE,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_CORE,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-
-static const char *dpll_core_ck_parents[] = {
-	"sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
-	.recalc_rate	= &omap3_dpll_recalc,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
-	.hw = {
-		.clk = &dpll_core_ck,
-	},
-	.dpll_data	= &dpll_core_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-	"dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_core_x2_ck,
-	},
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_CORE,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
-			2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
-		   OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
-		   0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
-		   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
-		   0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
-		   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
-			0x0, 1, 2);
-
-DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
-		   OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
-		   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const struct clk_ops dpll_hsd_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static const struct clk_ops func_dmic_abe_gfclk_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-};
-
-static const char *dpll_core_m3x2_ck_parents[] = {
-	"dpll_core_x2_ck",
-};
-
-static const struct clksel dpll_core_m3x2_div[] = {
-	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
-			 OMAP4430_CM_DIV_M3_DPLL_CORE,
-			 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-			 OMAP4430_CM_DIV_M3_DPLL_CORE,
-			 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-			 dpll_core_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
-			  &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
-			  OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "div_iva_hs_clk",
-};
-
-DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
-	       OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_IVA */
-static struct dpll_data dpll_iva_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_IVA,
-	.clk_bypass	= &iva_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_IVA,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_IVA,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_IVA,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_iva_ck_parents[] = {
-	"sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_iva_ck;
-
-static const struct clk_ops dpll_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_iva_ck_hw = {
-	.hw = {
-		.clk = &dpll_iva_ck,
-	},
-	.dpll_data	= &dpll_iva_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
-
-static const char *dpll_iva_x2_ck_parents[] = {
-	"dpll_iva_ck",
-};
-
-static struct clk dpll_iva_x2_ck;
-
-static struct clk_hw_omap dpll_iva_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_iva_x2_ck,
-	},
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_MPU,
-	.clk_bypass	= &div_mpu_hs_clk,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_MPU,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_MPU,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_MPU,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_mpu_ck_parents[] = {
-	"sys_clkin_ck", "div_mpu_hs_clk"
-};
-
-static struct clk dpll_mpu_ck;
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
-	.hw = {
-		.clk = &dpll_mpu_ck,
-	},
-	.dpll_data	= &dpll_mpu_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_MPU,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
-			&dpll_abe_m3x2_ck, 0x0, 1, 2);
-
-static const char *per_hsd_byp_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "per_hs_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
-	       OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_PER,
-	.clk_bypass	= &per_hsd_byp_clk_mux_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_PER,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_PER,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_PER,
-	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-static const char *dpll_per_ck_parents[] = {
-	"sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
-	.hw = {
-		.clk = &dpll_per_ck,
-	},
-	.dpll_data	= &dpll_per_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
-		   OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
-		   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const char *dpll_per_x2_ck_parents[] = {
-	"dpll_per_ck",
-};
-
-static struct clk dpll_per_x2_ck;
-
-static struct clk_hw_omap dpll_per_x2_ck_hw = {
-	.hw = {
-		.clk = &dpll_per_x2_ck,
-	},
-	.flags		= CLOCK_CLKOUTX2,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
-			  OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-static const char *dpll_per_m3x2_ck_parents[] = {
-	"dpll_per_x2_ck",
-};
-
-static const struct clksel dpll_per_m3x2_div[] = {
-	{ .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
-			 OMAP4430_CM_DIV_M3_DPLL_PER,
-			 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-			 OMAP4430_CM_DIV_M3_DPLL_PER,
-			 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-			 dpll_per_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-			  0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
-			  OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
-			&dpll_abe_m3x2_ck, 0x0, 1, 3);
-
-/* DPLL_USB */
-static struct dpll_data dpll_usb_dd = {
-	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_USB,
-	.clk_bypass	= &usb_hs_clk_div_ck,
-	.flags		= DPLL_J_TYPE,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_USB,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_USB,
-	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_USB,
-	.mult_mask	= OMAP4430_DPLL_MULT_USB_MASK,
-	.div1_mask	= OMAP4430_DPLL_DIV_0_7_MASK,
-	.enable_mask	= OMAP4430_DPLL_EN_MASK,
-	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
-	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
-	.sddiv_mask	= OMAP4430_DPLL_SD_DIV_MASK,
-	.max_multiplier	= 4095,
-	.max_divider	= 256,
-	.min_divider	= 1,
-};
-
-static const char *dpll_usb_ck_parents[] = {
-	"sys_clkin_ck", "usb_hs_clk_div_ck"
-};
-
-static struct clk dpll_usb_ck;
-
-static const struct clk_ops dpll_usb_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap dpll_usb_ck_hw = {
-	.hw = {
-		.clk = &dpll_usb_ck,
-	},
-	.dpll_data	= &dpll_usb_dd,
-	.clkdm_name	= "l3_init_clkdm",
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
-
-static const char *dpll_usb_clkdcoldo_ck_parents[] = {
-	"dpll_usb_ck",
-};
-
-static struct clk dpll_usb_clkdcoldo_ck;
-
-static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
-};
-
-static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
-	.hw = {
-		.clk = &dpll_usb_clkdcoldo_ck,
-	},
-	.clksel_reg	= OMAP4430_CM_CLKDCOLDO_DPLL_USB,
-	.ops		= &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
-		  dpll_usb_clkdcoldo_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
-			  OMAP4430_CM_DIV_M2_DPLL_USB,
-			  OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
-
-static const char *ducati_clk_mux_ck_parents[] = {
-	"div_core_ck", "dpll_per_m6x2_ck",
-};
-
-DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 16);
-
-DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
-			1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 8);
-
-static const struct clk_div_table func_48m_fclk_rates[] = {
-	{ .div = 4, .val = 0 },
-	{ .div = 8, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
-			 NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk,	"dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			0x0, 1, 4);
-
-static const struct clk_div_table func_64m_fclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 4, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
-			 NULL);
-
-static const struct clk_div_table func_96m_fclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 4, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-			 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-			 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
-			 NULL);
-
-static const struct clk_div_table init_60m_fclk_rates[] = {
-	{ .div = 1, .val = 0 },
-	{ .div = 8, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
-			 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
-			 OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
-			 0x0, init_60m_fclk_rates, NULL);
-
-DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
-		   OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
-		   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
-		   OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
-			0x0, 1, 16);
-
-static const char *l4_wkup_clk_mux_ck_parents[] = {
-	"sys_clkin_ck", "lp_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-	       OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const struct clk_div_table ocp_abe_iclk_rates[] = {
-	{ .div = 2, .val = 0 },
-	{ .div = 1, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
-			 OMAP4430_CM1_ABE_AESS_CLKCTRL,
-			 OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
-			 OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
-			 0x0, ocp_abe_iclk_rates, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
-			0x0, 1, 4);
-
-DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
-		   OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-		   OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-		   OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-		   OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const char *dbgclk_mux_ck_parents[] = {
-	"sys_clkin_ck"
-};
-
-static struct clk dbgclk_mux_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
-DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
-		  dpll_usb_clkdcoldo_ck_ops);
-
-/* Leaf clocks controlled by modules */
-
-DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_AES1_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_AES2_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-		OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table div_ts_ck_rates[] = {
-	{ .div = 8, .val = 0 },
-	{ .div = 16, .val = 1 },
-	{ .div = 32, .val = 2 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-			 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-			 OMAP4430_CLKSEL_24_25_SHIFT,
-			 OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
-			 NULL);
-
-DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
-		OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-		OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
-		0x0, NULL);
-
-static const char *dmic_sync_mux_ck_parents[] = {
-	"abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
-};
-
-DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
-	       0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_dmic_abe_gfclk_sel[] = {
-	{ .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_dmic_abe_gfclk_parents[] = {
-	"dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
-		    OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-		    func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
-		   OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
-		   OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-		OMAP4430_OPTFCLKEN_DBCLK_SHIFT,	0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-		OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-		0x0, NULL);
-
-static const struct clksel sgx_clk_mux_sel[] = {
-	{ .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *sgx_clk_mux_parents[] = {
-	"dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
-		    OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
-		    sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
-		   OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
-		   OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
-		OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcasp_abe_gfclk_sel[] = {
-	{ .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcasp_abe_gfclk_parents[] = {
-	"mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-		    func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp1_gfclk_sel[] = {
-	{ .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp1_gfclk_parents[] = {
-	"mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp2_gfclk_sel[] = {
-	{ .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp2_gfclk_parents[] = {
-	"mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp3_gfclk_sel[] = {
-	{ .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *func_mcbsp3_gfclk_parents[] = {
-	"mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
-		    OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const char *mcbsp4_sync_mux_ck_parents[] = {
-	"func_96m_fclk", "per_abe_nc_fclk",
-};
-
-DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-	       OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel per_mcbsp4_gfclk_sel[] = {
-	{ .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *per_mcbsp4_gfclk_parents[] = {
-	"mcbsp4_sync_mux_ck", "pad_clks_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
-		    OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-		    OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const struct clksel hsmmc1_fclk_sel[] = {
-	{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
-	{ .parent = &func_96m_fclk, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *hsmmc1_fclk_parents[] = {
-	"func_64m_fclk", "func_96m_fclk",
-};
-
-DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-		    OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-		    OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
-		OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
-		&pad_slimbus_core_clks_ck, 0x0,
-		OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-		OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-		0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clksel dmt1_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static const struct clksel timer5_sync_mux_sel[] = {
-	{ .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *timer5_sync_mux_parents[] = {
-	"syc_clk_div_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-		    OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-		    OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
-		    abe_dpll_bypass_clk_mux_ck_parents,
-		    func_dmic_abe_gfclk_ops);
-
-static struct clk usb_host_fs_fck;
-
-static const char *usb_host_fs_fck_parent_names[] = {
-	"func_48mc_fclk",
-};
-
-static const struct clk_ops usb_host_fs_fck_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-};
-
-static struct clk_hw_omap usb_host_fs_fck_hw = {
-	.hw = {
-		.clk = &usb_host_fs_fck,
-	},
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-};
-
-DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
-		  usb_host_fs_fck_ops);
-
-static const char *utmi_p1_gfclk_parents[] = {
-	"init_60m_fclk", "xclk60mhsp1_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	       OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
-
-static const char *utmi_p2_gfclk_parents[] = {
-	"init_60m_fclk", "xclk60mhsp2_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	       OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
-		&dpll_usb_m2_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
-		&init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
-		&init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
-		&dpll_usb_m2_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-		OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const char *otg_60m_gfclk_parents[] = {
-	"utmi_phy_clkout_ck", "xclk60motg_ck",
-};
-
-DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
-	       OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
-	       OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-		OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-		OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
-		OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
-		OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
-		OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-		OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table usim_ck_rates[] = {
-	{ .div = 14, .val = 0 },
-	{ .div = 18, .val = 1 },
-	{ .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
-			 OMAP4430_CM_WKUP_USIM_CLKCTRL,
-			 OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
-			 0x0, usim_ck_rates, NULL);
-
-DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
-		OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
-		0x0, NULL);
-
-/* Remaining optional clocks */
-static const char *pmd_stm_clock_mux_ck_parents[] = {
-	"sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
-};
-
-DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
-	       OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
-	       OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	       OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
-	       OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
-		   &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-		   OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
-		   OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-static const char *trace_clk_div_ck_parents[] = {
-	"pmd_trace_clk_mux_ck",
-};
-
-static const struct clksel trace_clk_div_div[] = {
-	{ .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
-
-static struct clk trace_clk_div_ck;
-
-static const struct clk_ops trace_clk_div_ck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.set_rate	= &omap2_clksel_set_rate,
-	.round_rate	= &omap2_clksel_round_rate,
-	.init		= &omap2_init_clk_clkdm,
-	.enable		= &omap2_clkops_enable_clkdm,
-	.disable	= &omap2_clkops_disable_clkdm,
-};
-
-static struct clk_hw_omap trace_clk_div_ck_hw = {
-	.hw = {
-		.clk = &trace_clk_div_ck,
-	},
-	.clkdm_name	= "emu_sys_clkdm",
-	.clksel		= trace_clk_div_div,
-	.clksel_reg	= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
-		  trace_clk_div_ck_ops);
-
-/* SCRM aux clk nodes */
-
-static const struct clksel auxclk_src_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
-	{ .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *auxclk_src_ck_parents[] = {
-	"sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
-};
-
-static const struct clk_ops auxclk_src_ck_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-	.is_enabled	= &omap2_dflt_clk_is_enabled,
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
-			 OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
-			 OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
-			 auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
-		   OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-		   0x0, NULL);
-
-static const char *auxclkreq_ck_parents[] = {
-	"auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
-	"auxclk5_ck",
-};
-
-DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
-	       OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-	       0x0, NULL);
-
-/*
- * clocks specific to omap4460
- */
-static struct omap_clk omap446x_clks[] = {
-	CLK(NULL,	"div_ts_ck",			&div_ts_ck),
-	CLK(NULL,	"bandgap_ts_fclk",		&bandgap_ts_fclk),
-};
-
-/*
- * clocks specific to omap4430
- */
-static struct omap_clk omap443x_clks[] = {
-	CLK(NULL,	"bandgap_fclk",			&bandgap_fclk),
-};
-
-/*
- * clocks common to omap44xx
- */
-static struct omap_clk omap44xx_clks[] = {
-	CLK(NULL,	"extalt_clkin_ck",		&extalt_clkin_ck),
-	CLK(NULL,	"pad_clks_src_ck",		&pad_clks_src_ck),
-	CLK(NULL,	"pad_clks_ck",			&pad_clks_ck),
-	CLK(NULL,	"pad_slimbus_core_clks_ck",	&pad_slimbus_core_clks_ck),
-	CLK(NULL,	"secure_32k_clk_src_ck",	&secure_32k_clk_src_ck),
-	CLK(NULL,	"slimbus_src_clk",		&slimbus_src_clk),
-	CLK(NULL,	"slimbus_clk",			&slimbus_clk),
-	CLK(NULL,	"sys_32k_ck",			&sys_32k_ck),
-	CLK(NULL,	"virt_12000000_ck",		&virt_12000000_ck),
-	CLK(NULL,	"virt_13000000_ck",		&virt_13000000_ck),
-	CLK(NULL,	"virt_16800000_ck",		&virt_16800000_ck),
-	CLK(NULL,	"virt_19200000_ck",		&virt_19200000_ck),
-	CLK(NULL,	"virt_26000000_ck",		&virt_26000000_ck),
-	CLK(NULL,	"virt_27000000_ck",		&virt_27000000_ck),
-	CLK(NULL,	"virt_38400000_ck",		&virt_38400000_ck),
-	CLK(NULL,	"sys_clkin_ck",			&sys_clkin_ck),
-	CLK(NULL,	"tie_low_clock_ck",		&tie_low_clock_ck),
-	CLK(NULL,	"utmi_phy_clkout_ck",		&utmi_phy_clkout_ck),
-	CLK(NULL,	"xclk60mhsp1_ck",		&xclk60mhsp1_ck),
-	CLK(NULL,	"xclk60mhsp2_ck",		&xclk60mhsp2_ck),
-	CLK(NULL,	"xclk60motg_ck",		&xclk60motg_ck),
-	CLK(NULL,	"abe_dpll_bypass_clk_mux_ck",	&abe_dpll_bypass_clk_mux_ck),
-	CLK(NULL,	"abe_dpll_refclk_mux_ck",	&abe_dpll_refclk_mux_ck),
-	CLK(NULL,	"dpll_abe_ck",			&dpll_abe_ck),
-	CLK(NULL,	"dpll_abe_x2_ck",		&dpll_abe_x2_ck),
-	CLK(NULL,	"dpll_abe_m2x2_ck",		&dpll_abe_m2x2_ck),
-	CLK(NULL,	"abe_24m_fclk",			&abe_24m_fclk),
-	CLK(NULL,	"abe_clk",			&abe_clk),
-	CLK(NULL,	"aess_fclk",			&aess_fclk),
-	CLK(NULL,	"dpll_abe_m3x2_ck",		&dpll_abe_m3x2_ck),
-	CLK(NULL,	"core_hsd_byp_clk_mux_ck",	&core_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_core_ck",			&dpll_core_ck),
-	CLK(NULL,	"dpll_core_x2_ck",		&dpll_core_x2_ck),
-	CLK(NULL,	"dpll_core_m6x2_ck",		&dpll_core_m6x2_ck),
-	CLK(NULL,	"dbgclk_mux_ck",		&dbgclk_mux_ck),
-	CLK(NULL,	"dpll_core_m2_ck",		&dpll_core_m2_ck),
-	CLK(NULL,	"ddrphy_ck",			&ddrphy_ck),
-	CLK(NULL,	"dpll_core_m5x2_ck",		&dpll_core_m5x2_ck),
-	CLK(NULL,	"div_core_ck",			&div_core_ck),
-	CLK(NULL,	"div_iva_hs_clk",		&div_iva_hs_clk),
-	CLK(NULL,	"div_mpu_hs_clk",		&div_mpu_hs_clk),
-	CLK(NULL,	"dpll_core_m4x2_ck",		&dpll_core_m4x2_ck),
-	CLK(NULL,	"dll_clk_div_ck",		&dll_clk_div_ck),
-	CLK(NULL,	"dpll_abe_m2_ck",		&dpll_abe_m2_ck),
-	CLK(NULL,	"dpll_core_m3x2_ck",		&dpll_core_m3x2_ck),
-	CLK(NULL,	"dpll_core_m7x2_ck",		&dpll_core_m7x2_ck),
-	CLK(NULL,	"iva_hsd_byp_clk_mux_ck",	&iva_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_iva_ck",			&dpll_iva_ck),
-	CLK(NULL,	"dpll_iva_x2_ck",		&dpll_iva_x2_ck),
-	CLK(NULL,	"dpll_iva_m4x2_ck",		&dpll_iva_m4x2_ck),
-	CLK(NULL,	"dpll_iva_m5x2_ck",		&dpll_iva_m5x2_ck),
-	CLK(NULL,	"dpll_mpu_ck",			&dpll_mpu_ck),
-	CLK(NULL,	"dpll_mpu_m2_ck",		&dpll_mpu_m2_ck),
-	CLK(NULL,	"per_hs_clk_div_ck",		&per_hs_clk_div_ck),
-	CLK(NULL,	"per_hsd_byp_clk_mux_ck",	&per_hsd_byp_clk_mux_ck),
-	CLK(NULL,	"dpll_per_ck",			&dpll_per_ck),
-	CLK(NULL,	"dpll_per_m2_ck",		&dpll_per_m2_ck),
-	CLK(NULL,	"dpll_per_x2_ck",		&dpll_per_x2_ck),
-	CLK(NULL,	"dpll_per_m2x2_ck",		&dpll_per_m2x2_ck),
-	CLK(NULL,	"dpll_per_m3x2_ck",		&dpll_per_m3x2_ck),
-	CLK(NULL,	"dpll_per_m4x2_ck",		&dpll_per_m4x2_ck),
-	CLK(NULL,	"dpll_per_m5x2_ck",		&dpll_per_m5x2_ck),
-	CLK(NULL,	"dpll_per_m6x2_ck",		&dpll_per_m6x2_ck),
-	CLK(NULL,	"dpll_per_m7x2_ck",		&dpll_per_m7x2_ck),
-	CLK(NULL,	"usb_hs_clk_div_ck",		&usb_hs_clk_div_ck),
-	CLK(NULL,	"dpll_usb_ck",			&dpll_usb_ck),
-	CLK(NULL,	"dpll_usb_clkdcoldo_ck",	&dpll_usb_clkdcoldo_ck),
-	CLK(NULL,	"dpll_usb_m2_ck",		&dpll_usb_m2_ck),
-	CLK(NULL,	"ducati_clk_mux_ck",		&ducati_clk_mux_ck),
-	CLK(NULL,	"func_12m_fclk",		&func_12m_fclk),
-	CLK(NULL,	"func_24m_clk",			&func_24m_clk),
-	CLK(NULL,	"func_24mc_fclk",		&func_24mc_fclk),
-	CLK(NULL,	"func_48m_fclk",		&func_48m_fclk),
-	CLK(NULL,	"func_48mc_fclk",		&func_48mc_fclk),
-	CLK(NULL,	"func_64m_fclk",		&func_64m_fclk),
-	CLK(NULL,	"func_96m_fclk",		&func_96m_fclk),
-	CLK(NULL,	"init_60m_fclk",		&init_60m_fclk),
-	CLK(NULL,	"l3_div_ck",			&l3_div_ck),
-	CLK(NULL,	"l4_div_ck",			&l4_div_ck),
-	CLK(NULL,	"lp_clk_div_ck",		&lp_clk_div_ck),
-	CLK(NULL,	"l4_wkup_clk_mux_ck",		&l4_wkup_clk_mux_ck),
-	CLK("smp_twd",	NULL,				&mpu_periphclk),
-	CLK(NULL,	"ocp_abe_iclk",			&ocp_abe_iclk),
-	CLK(NULL,	"per_abe_24m_fclk",		&per_abe_24m_fclk),
-	CLK(NULL,	"per_abe_nc_fclk",		&per_abe_nc_fclk),
-	CLK(NULL,	"syc_clk_div_ck",		&syc_clk_div_ck),
-	CLK(NULL,	"aes1_fck",			&aes1_fck),
-	CLK(NULL,	"aes2_fck",			&aes2_fck),
-	CLK(NULL,	"dmic_sync_mux_ck",		&dmic_sync_mux_ck),
-	CLK(NULL,	"func_dmic_abe_gfclk",		&func_dmic_abe_gfclk),
-	CLK(NULL,	"dss_sys_clk",			&dss_sys_clk),
-	CLK(NULL,	"dss_tv_clk",			&dss_tv_clk),
-	CLK(NULL,	"dss_dss_clk",			&dss_dss_clk),
-	CLK(NULL,	"dss_48mhz_clk",		&dss_48mhz_clk),
-	CLK(NULL,	"dss_fck",			&dss_fck),
-	CLK("omapdss_dss",	"ick",			&dss_fck),
-	CLK(NULL,	"fdif_fck",			&fdif_fck),
-	CLK(NULL,	"gpio1_dbclk",			&gpio1_dbclk),
-	CLK(NULL,	"gpio2_dbclk",			&gpio2_dbclk),
-	CLK(NULL,	"gpio3_dbclk",			&gpio3_dbclk),
-	CLK(NULL,	"gpio4_dbclk",			&gpio4_dbclk),
-	CLK(NULL,	"gpio5_dbclk",			&gpio5_dbclk),
-	CLK(NULL,	"gpio6_dbclk",			&gpio6_dbclk),
-	CLK(NULL,	"sgx_clk_mux",			&sgx_clk_mux),
-	CLK(NULL,	"hsi_fck",			&hsi_fck),
-	CLK(NULL,	"iss_ctrlclk",			&iss_ctrlclk),
-	CLK(NULL,	"mcasp_sync_mux_ck",		&mcasp_sync_mux_ck),
-	CLK(NULL,	"func_mcasp_abe_gfclk",		&func_mcasp_abe_gfclk),
-	CLK(NULL,	"mcbsp1_sync_mux_ck",		&mcbsp1_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp1_gfclk",		&func_mcbsp1_gfclk),
-	CLK(NULL,	"mcbsp2_sync_mux_ck",		&mcbsp2_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp2_gfclk",		&func_mcbsp2_gfclk),
-	CLK(NULL,	"mcbsp3_sync_mux_ck",		&mcbsp3_sync_mux_ck),
-	CLK(NULL,	"func_mcbsp3_gfclk",		&func_mcbsp3_gfclk),
-	CLK(NULL,	"mcbsp4_sync_mux_ck",		&mcbsp4_sync_mux_ck),
-	CLK(NULL,	"per_mcbsp4_gfclk",		&per_mcbsp4_gfclk),
-	CLK(NULL,	"hsmmc1_fclk",			&hsmmc1_fclk),
-	CLK(NULL,	"hsmmc2_fclk",			&hsmmc2_fclk),
-	CLK(NULL,	"ocp2scp_usb_phy_phy_48m",	&ocp2scp_usb_phy_phy_48m),
-	CLK(NULL,	"sha2md5_fck",			&sha2md5_fck),
-	CLK(NULL,	"slimbus1_fclk_1",		&slimbus1_fclk_1),
-	CLK(NULL,	"slimbus1_fclk_0",		&slimbus1_fclk_0),
-	CLK(NULL,	"slimbus1_fclk_2",		&slimbus1_fclk_2),
-	CLK(NULL,	"slimbus1_slimbus_clk",		&slimbus1_slimbus_clk),
-	CLK(NULL,	"slimbus2_fclk_1",		&slimbus2_fclk_1),
-	CLK(NULL,	"slimbus2_fclk_0",		&slimbus2_fclk_0),
-	CLK(NULL,	"slimbus2_slimbus_clk",		&slimbus2_slimbus_clk),
-	CLK(NULL,	"smartreflex_core_fck",		&smartreflex_core_fck),
-	CLK(NULL,	"smartreflex_iva_fck",		&smartreflex_iva_fck),
-	CLK(NULL,	"smartreflex_mpu_fck",		&smartreflex_mpu_fck),
-	CLK(NULL,	"dmt1_clk_mux",			&dmt1_clk_mux),
-	CLK(NULL,	"cm2_dm10_mux",			&cm2_dm10_mux),
-	CLK(NULL,	"cm2_dm11_mux",			&cm2_dm11_mux),
-	CLK(NULL,	"cm2_dm2_mux",			&cm2_dm2_mux),
-	CLK(NULL,	"cm2_dm3_mux",			&cm2_dm3_mux),
-	CLK(NULL,	"cm2_dm4_mux",			&cm2_dm4_mux),
-	CLK(NULL,	"timer5_sync_mux",		&timer5_sync_mux),
-	CLK(NULL,	"timer6_sync_mux",		&timer6_sync_mux),
-	CLK(NULL,	"timer7_sync_mux",		&timer7_sync_mux),
-	CLK(NULL,	"timer8_sync_mux",		&timer8_sync_mux),
-	CLK(NULL,	"cm2_dm9_mux",			&cm2_dm9_mux),
-	CLK(NULL,	"usb_host_fs_fck",		&usb_host_fs_fck),
-	CLK("usbhs_omap",	"fs_fck",		&usb_host_fs_fck),
-	CLK(NULL,	"utmi_p1_gfclk",		&utmi_p1_gfclk),
-	CLK(NULL,	"usb_host_hs_utmi_p1_clk",	&usb_host_hs_utmi_p1_clk),
-	CLK(NULL,	"utmi_p2_gfclk",		&utmi_p2_gfclk),
-	CLK(NULL,	"usb_host_hs_utmi_p2_clk",	&usb_host_hs_utmi_p2_clk),
-	CLK(NULL,	"usb_host_hs_utmi_p3_clk",	&usb_host_hs_utmi_p3_clk),
-	CLK(NULL,	"usb_host_hs_hsic480m_p1_clk",	&usb_host_hs_hsic480m_p1_clk),
-	CLK(NULL,	"usb_host_hs_hsic60m_p1_clk",	&usb_host_hs_hsic60m_p1_clk),
-	CLK(NULL,	"usb_host_hs_hsic60m_p2_clk",	&usb_host_hs_hsic60m_p2_clk),
-	CLK(NULL,	"usb_host_hs_hsic480m_p2_clk",	&usb_host_hs_hsic480m_p2_clk),
-	CLK(NULL,	"usb_host_hs_func48mclk",	&usb_host_hs_func48mclk),
-	CLK(NULL,	"usb_host_hs_fck",		&usb_host_hs_fck),
-	CLK("usbhs_omap",	"hs_fck",		&usb_host_hs_fck),
-	CLK(NULL,	"otg_60m_gfclk",		&otg_60m_gfclk),
-	CLK(NULL,	"usb_otg_hs_xclk",		&usb_otg_hs_xclk),
-	CLK(NULL,	"usb_otg_hs_ick",		&usb_otg_hs_ick),
-	CLK("musb-omap2430",	"ick",			&usb_otg_hs_ick),
-	CLK(NULL,	"usb_phy_cm_clk32k",		&usb_phy_cm_clk32k),
-	CLK(NULL,	"usb_tll_hs_usb_ch2_clk",	&usb_tll_hs_usb_ch2_clk),
-	CLK(NULL,	"usb_tll_hs_usb_ch0_clk",	&usb_tll_hs_usb_ch0_clk),
-	CLK(NULL,	"usb_tll_hs_usb_ch1_clk",	&usb_tll_hs_usb_ch1_clk),
-	CLK(NULL,	"usb_tll_hs_ick",		&usb_tll_hs_ick),
-	CLK("usbhs_omap",	"usbtll_ick",		&usb_tll_hs_ick),
-	CLK("usbhs_tll",	"usbtll_ick",		&usb_tll_hs_ick),
-	CLK(NULL,	"usim_ck",			&usim_ck),
-	CLK(NULL,	"usim_fclk",			&usim_fclk),
-	CLK(NULL,	"pmd_stm_clock_mux_ck",		&pmd_stm_clock_mux_ck),
-	CLK(NULL,	"pmd_trace_clk_mux_ck",		&pmd_trace_clk_mux_ck),
-	CLK(NULL,	"stm_clk_div_ck",		&stm_clk_div_ck),
-	CLK(NULL,	"trace_clk_div_ck",		&trace_clk_div_ck),
-	CLK(NULL,	"auxclk0_src_ck",		&auxclk0_src_ck),
-	CLK(NULL,	"auxclk0_ck",			&auxclk0_ck),
-	CLK(NULL,	"auxclkreq0_ck",		&auxclkreq0_ck),
-	CLK(NULL,	"auxclk1_src_ck",		&auxclk1_src_ck),
-	CLK(NULL,	"auxclk1_ck",			&auxclk1_ck),
-	CLK(NULL,	"auxclkreq1_ck",		&auxclkreq1_ck),
-	CLK(NULL,	"auxclk2_src_ck",		&auxclk2_src_ck),
-	CLK(NULL,	"auxclk2_ck",			&auxclk2_ck),
-	CLK(NULL,	"auxclkreq2_ck",		&auxclkreq2_ck),
-	CLK(NULL,	"auxclk3_src_ck",		&auxclk3_src_ck),
-	CLK(NULL,	"auxclk3_ck",			&auxclk3_ck),
-	CLK(NULL,	"auxclkreq3_ck",		&auxclkreq3_ck),
-	CLK(NULL,	"auxclk4_src_ck",		&auxclk4_src_ck),
-	CLK(NULL,	"auxclk4_ck",			&auxclk4_ck),
-	CLK(NULL,	"auxclkreq4_ck",		&auxclkreq4_ck),
-	CLK(NULL,	"auxclk5_src_ck",		&auxclk5_src_ck),
-	CLK(NULL,	"auxclk5_ck",			&auxclk5_ck),
-	CLK(NULL,	"auxclkreq5_ck",		&auxclkreq5_ck),
-	CLK("omap-gpmc",	"fck",			&dummy_ck),
-	CLK("omap_i2c.1",	"ick",			&dummy_ck),
-	CLK("omap_i2c.2",	"ick",			&dummy_ck),
-	CLK("omap_i2c.3",	"ick",			&dummy_ck),
-	CLK("omap_i2c.4",	"ick",			&dummy_ck),
-	CLK(NULL,	"mailboxes_ick",		&dummy_ck),
-	CLK("omap_hsmmc.0",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.1",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.2",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.3",	"ick",			&dummy_ck),
-	CLK("omap_hsmmc.4",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.1",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.2",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.3",	"ick",			&dummy_ck),
-	CLK("omap-mcbsp.4",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.1",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.2",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.3",	"ick",			&dummy_ck),
-	CLK("omap2_mcspi.4",	"ick",			&dummy_ck),
-	CLK(NULL,	"uart1_ick",			&dummy_ck),
-	CLK(NULL,	"uart2_ick",			&dummy_ck),
-	CLK(NULL,	"uart3_ick",			&dummy_ck),
-	CLK(NULL,	"uart4_ick",			&dummy_ck),
-	CLK("usbhs_omap",	"usbhost_ick",		&dummy_ck),
-	CLK("usbhs_omap",	"usbtll_fck",		&dummy_ck),
-	CLK("usbhs_tll",	"usbtll_fck",		&dummy_ck),
-	CLK("omap_wdt",	"ick",				&dummy_ck),
-	CLK(NULL,	"timer_32k_ck",	&sys_32k_ck),
-	/* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
-	CLK("omap_timer.1",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.2",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.3",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.4",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.9",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.10",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.11",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("omap_timer.5",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.6",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.7",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("omap_timer.8",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4a318000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48032000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48034000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48036000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("4803e000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48086000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("48088000.timer",	"timer_sys_ck",	&sys_clkin_ck),
-	CLK("40138000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013a000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013c000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK("4013e000.timer",	"timer_sys_ck",	&syc_clk_div_ck),
-	CLK(NULL,	"cpufreq_ck",	&dpll_mpu_ck),
-};
-
-int __init omap4xxx_clk_init(void)
-{
-	int rc;
-
-	if (cpu_is_omap443x()) {
-		cpu_mask = RATE_IN_4430;
-		omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
-	} else if (cpu_is_omap446x() || cpu_is_omap447x()) {
-		cpu_mask = RATE_IN_4460 | RATE_IN_4430;
-		omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
-		if (cpu_is_omap447x())
-			pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
-	} else {
-		return 0;
-	}
-
-	omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
-
-	omap2_clk_disable_autoidle_all();
-
-	/*
-	 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
-	 * state when turning the ABE clock domain. Workaround this by
-	 * locking the ABE DPLL on boot.
-	 * Lock the ABE DPLL in any case to avoid issues with audio.
-	 */
-	rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
-	if (!rc)
-		rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
-	if (rc)
-		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
-
-	/*
-	 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
-	 * domain can transition to retention state when not in use.
-	 */
-	rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
-	if (rc)
-		pr_err("%s: failed to configure USB DPLL!\n", __func__);
-
-	return 0;
-}
diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index 3d3ca30f..9ad10be 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1 +1,2 @@
-obj-y					+= clk.o dpll.o autoidle.o gate.o
+obj-y					+= clk.o dpll.o autoidle.o gate.o \
+					   clk-44xx.o
-- 
1.7.9.5

Re: [PATCHv4 10/33] ARM: OMAP4: remove old clock data and link in new clock init code

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:

> diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
> deleted file mode 100644
> index 88e37a4..0000000
> --- a/arch/arm/mach-omap2/cclock44xx_data.c
> +++ /dev/null
[...]
> -
> -int __init omap4xxx_clk_init(void)
> -{
arch/arm/mach-omap2/clock44xx.h:int omap4xxx_clk_init(void);
arch/arm/mach-omap2/io.c:       omap_clk_init = omap4xxx_clk_init;
code in drivers/clk/omap/clk-44xx.c

Seems goofy to me a little.
entire purpose of having a clk-44xx.c is:
a) doing a clk alias for device nodes
b) set_parent, rate
both of these seem to be an old style carry forward and should instead 
be fixes with generic properties IMHO voiding the need for SoC specific 
inits.

instead all we should be doing is call of_clk_init(NULL); at appropriate 
init sequence.

-- 
Regards,
Nishanth Menon

[PATCHv4 10/33] ARM: OMAP4: remove old clock data and link in new clock init code

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:

> diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
> deleted file mode 100644
> index 88e37a4..0000000
> --- a/arch/arm/mach-omap2/cclock44xx_data.c
> +++ /dev/null
[...]
> -
> -int __init omap4xxx_clk_init(void)
> -{
arch/arm/mach-omap2/clock44xx.h:int omap4xxx_clk_init(void);
arch/arm/mach-omap2/io.c:       omap_clk_init = omap4xxx_clk_init;
code in drivers/clk/omap/clk-44xx.c

Seems goofy to me a little.
entire purpose of having a clk-44xx.c is:
a) doing a clk alias for device nodes
b) set_parent, rate
both of these seem to be an old style carry forward and should instead 
be fixes with generic properties IMHO voiding the need for SoC specific 
inits.

instead all we should be doing is call of_clk_init(NULL); at appropriate 
init sequence.

-- 
Regards,
Nishanth Menon

Re: [PATCHv4 10/33] ARM: OMAP4: remove old clock data and link in new clock init code

[Tero Kristo]

On 07/30/2013 10:42 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>
>> diff --git a/arch/arm/mach-omap2/cclock44xx_data.c
>> b/arch/arm/mach-omap2/cclock44xx_data.c
>> deleted file mode 100644
>> index 88e37a4..0000000
>> --- a/arch/arm/mach-omap2/cclock44xx_data.c
>> +++ /dev/null
> [...]
>> -
>> -int __init omap4xxx_clk_init(void)
>> -{
> arch/arm/mach-omap2/clock44xx.h:int omap4xxx_clk_init(void);
> arch/arm/mach-omap2/io.c:       omap_clk_init = omap4xxx_clk_init;
> code in drivers/clk/omap/clk-44xx.c
>
> Seems goofy to me a little.
> entire purpose of having a clk-44xx.c is:
> a) doing a clk alias for device nodes

I am not quite sure we have mechanisms for doing this (yet).

> b) set_parent, rate

I think this is maybe an idea for future dev and Mike to consider if he 
wants generic clock nodes to have such properties.


> both of these seem to be an old style carry forward and should instead
> be fixes with generic properties IMHO voiding the need for SoC specific
> inits.
>
> instead all we should be doing is call of_clk_init(NULL); at appropriate
> init sequence.

[PATCHv4 10/33] ARM: OMAP4: remove old clock data and link in new clock init code

[Tero Kristo]

On 07/30/2013 10:42 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>
>> diff --git a/arch/arm/mach-omap2/cclock44xx_data.c
>> b/arch/arm/mach-omap2/cclock44xx_data.c
>> deleted file mode 100644
>> index 88e37a4..0000000
>> --- a/arch/arm/mach-omap2/cclock44xx_data.c
>> +++ /dev/null
> [...]
>> -
>> -int __init omap4xxx_clk_init(void)
>> -{
> arch/arm/mach-omap2/clock44xx.h:int omap4xxx_clk_init(void);
> arch/arm/mach-omap2/io.c:       omap_clk_init = omap4xxx_clk_init;
> code in drivers/clk/omap/clk-44xx.c
>
> Seems goofy to me a little.
> entire purpose of having a clk-44xx.c is:
> a) doing a clk alias for device nodes

I am not quite sure we have mechanisms for doing this (yet).

> b) set_parent, rate

I think this is maybe an idea for future dev and Mike to consider if he 
wants generic clock nodes to have such properties.


> both of these seem to be an old style carry forward and should instead
> be fixes with generic properties IMHO voiding the need for SoC specific
> inits.
>
> instead all we should be doing is call of_clk_init(NULL); at appropriate
> init sequence.

[PATCHv4 11/33] ARM: dts: omap5 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP5 power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap54xx-clocks.dtsi | 1416 ++++++++++++++++++++++++++++++++
 1 file changed, 1416 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap54xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
new file mode 100644
index 0000000..391edee
--- /dev/null
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -0,0 +1,1416 @@
+/*
+ * Device Tree Source for OMAP5 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+pad_clks_src_ck: pad_clks_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+pad_clks_ck: pad_clks_ck@4a004108 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&pad_clks_src_ck>;
+	bit-shift = <8>;
+	reg = <0x4a004108 0x4>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+slimbus_src_clk: slimbus_src_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+slimbus_clk: slimbus_clk@4a004108 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&slimbus_src_clk>;
+	bit-shift = <10>;
+	reg = <0x4a004108 0x4>;
+};
+
+sys_32k_ck: sys_32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <38400000>;
+};
+
+sys_clkin: sys_clkin@4ae06110 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+	reg = <0x4ae06110 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+xclk60mhsp1_ck: xclk60mhsp1_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60mhsp2_ck: xclk60mhsp2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@4ae06108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	reg = <0x4ae06108 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_dpll_clk_mux: abe_dpll_clk_mux@4ae0610c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	reg = <0x4ae0610c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_abe_ck: dpll_abe_ck@4a0041e0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+	reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
+	ti,clk-ref = <&abe_dpll_clk_mux>;
+	ti,clk-bypass = <&abe_dpll_bypass_clk_mux>;
+	ti,dpll-regm4xen;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_abe_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+abe_clk: abe_clk@4a004108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4a004108 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+abe_iclk: abe_iclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&abe_clk>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+abe_lp_clk_div: abe_lp_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0041f4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041f4 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_ck: dpll_core_ck@4a004120 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+	ti,dpll-core;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_core_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_core_h21x2_ck: dpll_core_h21x2_ck@4a004150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004150 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+c2c_fclk: c2c_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h21x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+c2c_iclk: c2c_iclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&c2c_fclk>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_core_h11x2_ck: dpll_core_h11x2_ck@4a004138 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004138 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h12x2_ck: dpll_core_h12x2_ck@4a00413c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00413c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h13x2_ck: dpll_core_h13x2_ck@4a004140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004140 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h14x2_ck: dpll_core_h14x2_ck@4a004144 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004144 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h22x2_ck: dpll_core_h22x2_ck@4a004154 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004154 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h23x2_ck: dpll_core_h23x2_ck@4a004158 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004158 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h24x2_ck: dpll_core_h24x2_ck@4a00415c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00415c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck@4a004130 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004130 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck@4a004134 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004134 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_iva_ck: dpll_iva_ck@4a0041a0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
+	reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&iva_dpll_hs_clk_div>;
+};
+
+dpll_iva_x2_ck: dpll_iva_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_iva_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@4a0041b8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041b8 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@4a0041bc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041bc 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_mpu_ck: dpll_mpu_ck@4a004160 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
+	reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&mpu_dpll_hs_clk_div>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a004170 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004170 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_per_ck: dpll_per_ck@4a008140 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
+	reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&per_dpll_hs_clk_div>;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_per_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_per_h11x2_ck: dpll_per_h11x2_ck@4a008158 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008158 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h12x2_ck: dpll_per_h12x2_ck@4a00815c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00815c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h14x2_ck: dpll_per_h14x2_ck@4a008164 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008164 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck@4a008150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m3x2_ck: dpll_per_m3x2_ck@4a008154 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008154 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_unipro1_ck: dpll_unipro1_ck@4a008200 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>;
+	reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&sys_clkin>;
+};
+
+dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_unipro1_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@4a008210 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_unipro1_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008210 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_unipro2_ck: dpll_unipro2_ck@4a0081c0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>;
+	reg = <0x4a0081c0 0x4>, <0x4a0081c4 0x4>, <0x4a0081c8 0x4>, <0x4a0081cc 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&sys_clkin>;
+};
+
+dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_unipro2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@4a0081d0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_unipro2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0081d0 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck@4a008180 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
+	ti,clk-bypass = <&usb_dpll_hs_clk_div>;
+	reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clkdm-name = "l3init_clkdm";
+	ti,dpll-j-type;
+};
+
+dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_usb_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008190 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dss_syc_gfclk_div: dss_syc_gfclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+func_128m_clk: func_128m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_h11x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+func_12m_fclk: func_12m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_48m_fclk: func_48m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_96m_fclk: func_96m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+l3_iclk_div: l3_iclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gpu_l3_iclk: gpu_l3_iclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_iclk_div>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3init_60m_fclk: l3init_60m_fclk@4a008104 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	reg = <0x4a008104 0x4>;
+	table = < 1 0 >, < 8 1 >;
+	bit-mask = <0x1>;
+};
+
+wkupaon_iclk_mux: wkupaon_iclk_mux@4ae06108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&abe_lp_clk_div>;
+	reg = <0x4ae06108 0x4>;
+	bit-mask = <0x1>;
+};
+
+l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&wkupaon_iclk_mux>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l4_root_clk_div: l4_root_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_iclk_div>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dss_32khz_clk: dss_32khz_clk@4a009420 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <11>;
+	reg = <0x4a009420 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk@4a009420 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009420 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk@4a009420 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_h12x2_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009420 0x4>;
+};
+
+dss_sys_clk: dss_sys_clk@4a009420 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dss_syc_gfclk_div>;
+	bit-shift = <10>;
+	reg = <0x4a009420 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk@4ae07938 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae07938 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk@4a009060 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009060 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk@4a009068 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009068 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk@4a009070 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009070 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk@4a009078 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009078 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk@4a009080 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009080 0x4>;
+};
+
+gpio7_dbclk: gpio7_dbclk@4a009110 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009110 0x4>;
+};
+
+gpio8_dbclk: gpio8_dbclk@4a009118 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009118 0x4>;
+};
+
+iss_ctrlclk: iss_ctrlclk@4a009320 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_96m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009320 0x4>;
+};
+
+lli_txphy_clk: lli_txphy_clk@4a008f20 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_unipro1_clkdcoldo>;
+	bit-shift = <8>;
+	reg = <0x4a008f20 0x4>;
+};
+
+lli_txphy_ls_clk: lli_txphy_ls_clk@4a008f20 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_unipro1_m2_ck>;
+	bit-shift = <9>;
+	reg = <0x4a008f20 0x4>;
+};
+
+mmc1_32khz_clk: mmc1_32khz_clk@4a009628 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009628 0x4>;
+};
+
+sata_ref_clk: sata_ref_clk@4a009688 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_clkin>;
+	bit-shift = <8>;
+	reg = <0x4a009688 0x4>;
+};
+
+slimbus1_slimbus_clk: slimbus1_slimbus_clk@4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&slimbus_clk>;
+	bit-shift = <11>;
+	reg = <0x4a004560 0x4>;
+};
+
+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <13>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <14>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <7>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <11>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <12>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <6>;
+	reg = <0x4a009658 0x4>;
+};
+
+utmi_p1_gfclk: utmi_p1_gfclk@4a009658 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009658 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&utmi_p1_gfclk>;
+	bit-shift = <8>;
+	reg = <0x4a009658 0x4>;
+};
+
+utmi_p2_gfclk: utmi_p2_gfclk@4a009658 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
+	bit-shift = <25>;
+	reg = <0x4a009658 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&utmi_p2_gfclk>;
+	bit-shift = <9>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <10>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@4a0096f0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_clkdcoldo>;
+	bit-shift = <8>;
+	reg = <0x4a0096f0 0x4>;
+};
+
+usb_phy_cm_clk32k: usb_phy_cm_clk32k@4a008640 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008640 0x4>;
+};
+
+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@4a009668 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009668 0x4>;
+};
+
+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@4a009668 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009668 0x4>;
+};
+
+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@4a009668 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <10>;
+	reg = <0x4a009668 0x4>;
+};
+
+aess_fclk: aess_fclk@4a004528 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&abe_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004528 0x4>;
+	bit-mask = <0x1>;
+};
+
+dmic_sync_mux_ck: dmic_sync_mux_ck@4a004538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004538 0x4>;
+	bit-mask = <0x3>;
+};
+
+dmic_gfclk: dmic_gfclk@4a004538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004538 0x4>;
+	bit-mask = <0x3>;
+};
+
+fdif_fclk: fdif_fclk@4a009328 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_h11x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009328 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpu_core_gclk_mux: gpu_core_gclk_mux@4a009520 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009520 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@4a009520 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+	bit-shift = <25>;
+	reg = <0x4a009520 0x4>;
+	bit-mask = <0x1>;
+};
+
+hsi_fclk: hsi_fclk@4a009638 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009638 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcasp_sync_mux_ck: mcasp_sync_mux_ck@4a004540 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004540 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp_gfclk: mcasp_gfclk@4a004540 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004540 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@4a004548 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004548 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp1_gfclk: mcbsp1_gfclk@4a004548 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004548 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@4a004550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004550 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp2_gfclk: mcbsp2_gfclk@4a004550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004550 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@4a004558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004558 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp3_gfclk: mcbsp3_gfclk@4a004558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004558 0x4>;
+	bit-mask = <0x3>;
+};
+
+mmc1_fclk_mux: mmc1_fclk_mux@4a009628 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009628 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc1_fclk: mmc1_fclk@4a009628 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc1_fclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009628 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc2_fclk_mux: mmc2_fclk_mux@4a009630 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009630 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc2_fclk: mmc2_fclk@4a009630 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc2_fclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009630 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer10_gfclk_mux: timer10_gfclk_mux@4a009028 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009028 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer11_gfclk_mux: timer11_gfclk_mux@4a009030 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009030 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer1_gfclk_mux: timer1_gfclk_mux@4ae07940 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4ae07940 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer2_gfclk_mux: timer2_gfclk_mux@4a009038 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009038 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer3_gfclk_mux: timer3_gfclk_mux@4a009040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009040 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer4_gfclk_mux: timer4_gfclk_mux@4a009048 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009048 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer5_gfclk_mux: timer5_gfclk_mux@4a004568 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004568 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer6_gfclk_mux: timer6_gfclk_mux@4a004570 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004570 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer7_gfclk_mux: timer7_gfclk_mux@4a004578 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004578 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer8_gfclk_mux: timer8_gfclk_mux@4a004580 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004580 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer9_gfclk_mux: timer9_gfclk_mux@4a009050 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009050 0x4>;
+	bit-mask = <0x1>;
+};
+
+auxclk0_src_mux_ck: auxclk0_src_mux_ck@4ae0a310 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a310 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk0_src_ck: auxclk0_src_ck@4ae0a310 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk0_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a310 0x4>;
+};
+
+auxclk0_ck: auxclk0_ck@4ae0a310 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk0_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a310 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk1_src_mux_ck: auxclk1_src_mux_ck@4ae0a314 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a314 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk1_src_ck: auxclk1_src_ck@4ae0a314 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk1_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a314 0x4>;
+};
+
+auxclk1_ck: auxclk1_ck@4ae0a314 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk1_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a314 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk2_src_mux_ck: auxclk2_src_mux_ck@4ae0a318 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a318 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk2_src_ck: auxclk2_src_ck@4ae0a318 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk2_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a318 0x4>;
+};
+
+auxclk2_ck: auxclk2_ck@4ae0a318 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk2_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a318 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk3_src_mux_ck: auxclk3_src_mux_ck@4ae0a31c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a31c 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk3_src_ck: auxclk3_src_ck@4ae0a31c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk3_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a31c 0x4>;
+};
+
+auxclk3_ck: auxclk3_ck@4ae0a31c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk3_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a31c 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk4_src_mux_ck: auxclk4_src_mux_ck@4ae0a320 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a320 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk4_src_ck: auxclk4_src_ck@4ae0a320 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk4_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a320 0x4>;
+};
+
+auxclk4_ck: auxclk4_ck@4ae0a320 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk4_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a320 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclkreq0_ck: auxclkreq0_ck@4ae0a210 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+	bit-shift = <2>;
+	reg = <0x4ae0a210 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq1_ck: auxclkreq1_ck@4ae0a214 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+	bit-shift = <2>;
+	reg = <0x4ae0a214 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq2_ck: auxclkreq2_ck@4ae0a218 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+	bit-shift = <2>;
+	reg = <0x4ae0a218 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq3_ck: auxclkreq3_ck@4ae0a21c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+	bit-shift = <2>;
+	reg = <0x4ae0a21c 0x4>;
+	bit-mask = <0x7>;
+};
-- 
1.7.9.5

[PATCHv4 11/33] ARM: dts: omap5 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP5 power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap54xx-clocks.dtsi | 1416 ++++++++++++++++++++++++++++++++
 1 file changed, 1416 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap54xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
new file mode 100644
index 0000000..391edee
--- /dev/null
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -0,0 +1,1416 @@
+/*
+ * Device Tree Source for OMAP5 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+pad_clks_src_ck: pad_clks_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+pad_clks_ck: pad_clks_ck at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&pad_clks_src_ck>;
+	bit-shift = <8>;
+	reg = <0x4a004108 0x4>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+slimbus_src_clk: slimbus_src_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+slimbus_clk: slimbus_clk at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&slimbus_src_clk>;
+	bit-shift = <10>;
+	reg = <0x4a004108 0x4>;
+};
+
+sys_32k_ck: sys_32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <38400000>;
+};
+
+sys_clkin: sys_clkin at 4ae06110 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+	reg = <0x4ae06110 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+xclk60mhsp1_ck: xclk60mhsp1_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+xclk60mhsp2_ck: xclk60mhsp2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <60000000>;
+};
+
+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux at 4ae06108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	reg = <0x4ae06108 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_dpll_clk_mux: abe_dpll_clk_mux at 4ae0610c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	reg = <0x4ae0610c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_abe_ck: dpll_abe_ck at 4a0041e0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+	reg = <0x4a0041e0 0x4>, <0x4a0041e4 0x4>, <0x4a0041e8 0x4>, <0x4a0041ec 0x4>;
+	ti,clk-ref = <&abe_dpll_clk_mux>;
+	ti,clk-bypass = <&abe_dpll_bypass_clk_mux>;
+	ti,dpll-regm4xen;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_abe_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0041f0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+abe_clk: abe_clk at 4a004108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4a004108 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+abe_iclk: abe_iclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&abe_clk>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+abe_lp_clk_div: abe_lp_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 4a0041f4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041f4 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_ck: dpll_core_ck at 4a004120 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a004120 0x4>, <0x4a004124 0x4>, <0x4a004128 0x4>, <0x4a00412c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+	ti,dpll-core;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_core_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_core_h21x2_ck: dpll_core_h21x2_ck at 4a004150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004150 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+c2c_fclk: c2c_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h21x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+c2c_iclk: c2c_iclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&c2c_fclk>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_core_h11x2_ck: dpll_core_h11x2_ck at 4a004138 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004138 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h12x2_ck: dpll_core_h12x2_ck at 4a00413c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00413c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h13x2_ck: dpll_core_h13x2_ck at 4a004140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004140 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h14x2_ck: dpll_core_h14x2_ck at 4a004144 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004144 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h22x2_ck: dpll_core_h22x2_ck at 4a004154 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004154 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h23x2_ck: dpll_core_h23x2_ck at 4a004158 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004158 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h24x2_ck: dpll_core_h24x2_ck at 4a00415c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00415c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck at 4a004130 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004130 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_m3x2_ck: dpll_core_m3x2_ck at 4a004134 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004134 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_iva_ck: dpll_iva_ck at 4a0041a0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
+	reg = <0x4a0041a0 0x4>, <0x4a0041a4 0x4>, <0x4a0041a8 0x4>, <0x4a0041ac 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&iva_dpll_hs_clk_div>;
+};
+
+dpll_iva_x2_ck: dpll_iva_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_iva_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_iva_h11x2_ck: dpll_iva_h11x2_ck at 4a0041b8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041b8 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_iva_h12x2_ck: dpll_iva_h12x2_ck at 4a0041bc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_iva_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0041bc 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 4a004160 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
+	reg = <0x4a004160 0x4>, <0x4a004164 0x4>, <0x4a004168 0x4>, <0x4a00416c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&mpu_dpll_hs_clk_div>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 4a004170 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a004170 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_per_ck: dpll_per_ck at 4a008140 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
+	reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&per_dpll_hs_clk_div>;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_per_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_per_h11x2_ck: dpll_per_h11x2_ck at 4a008158 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008158 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h12x2_ck: dpll_per_h12x2_ck at 4a00815c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00815c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h14x2_ck: dpll_per_h14x2_ck at 4a008164 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008164 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m3x2_ck: dpll_per_m3x2_ck at 4a008154 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008154 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_unipro1_ck: dpll_unipro1_ck at 4a008200 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>;
+	reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&sys_clkin>;
+};
+
+dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_unipro1_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_unipro1_m2_ck: dpll_unipro1_m2_ck at 4a008210 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_unipro1_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008210 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_unipro2_ck: dpll_unipro2_ck at 4a0081c0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>;
+	reg = <0x4a0081c0 0x4>, <0x4a0081c4 0x4>, <0x4a0081c8 0x4>, <0x4a0081cc 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clk-bypass = <&sys_clkin>;
+};
+
+dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_unipro2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_unipro2_m2_ck: dpll_unipro2_m2_ck at 4a0081d0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_unipro2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0081d0 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck at 4a008180 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
+	ti,clk-bypass = <&usb_dpll_hs_clk_div>;
+	reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+	ti,clk-ref = <&sys_clkin>;
+	ti,clkdm-name = "l3init_clkdm";
+	ti,dpll-j-type;
+};
+
+dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_usb_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008190 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dss_syc_gfclk_div: dss_syc_gfclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+func_128m_clk: func_128m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_h11x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+func_12m_fclk: func_12m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_48m_fclk: func_48m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_96m_fclk: func_96m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+l3_iclk_div: l3_iclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gpu_l3_iclk: gpu_l3_iclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_iclk_div>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3init_60m_fclk: l3init_60m_fclk at 4a008104 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	reg = <0x4a008104 0x4>;
+	table = < 1 0 >, < 8 1 >;
+	bit-mask = <0x1>;
+};
+
+wkupaon_iclk_mux: wkupaon_iclk_mux at 4ae06108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&abe_lp_clk_div>;
+	reg = <0x4ae06108 0x4>;
+	bit-mask = <0x1>;
+};
+
+l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&wkupaon_iclk_mux>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l4_root_clk_div: l4_root_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_iclk_div>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dss_32khz_clk: dss_32khz_clk at 4a009420 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <11>;
+	reg = <0x4a009420 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk at 4a009420 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009420 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk at 4a009420 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_h12x2_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009420 0x4>;
+};
+
+dss_sys_clk: dss_sys_clk at 4a009420 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dss_syc_gfclk_div>;
+	bit-shift = <10>;
+	reg = <0x4a009420 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk at 4ae07938 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae07938 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 4a009060 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009060 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 4a009068 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009068 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk at 4a009070 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009070 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk at 4a009078 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009078 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk at 4a009080 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009080 0x4>;
+};
+
+gpio7_dbclk: gpio7_dbclk at 4a009110 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009110 0x4>;
+};
+
+gpio8_dbclk: gpio8_dbclk at 4a009118 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009118 0x4>;
+};
+
+iss_ctrlclk: iss_ctrlclk at 4a009320 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_96m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009320 0x4>;
+};
+
+lli_txphy_clk: lli_txphy_clk at 4a008f20 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_unipro1_clkdcoldo>;
+	bit-shift = <8>;
+	reg = <0x4a008f20 0x4>;
+};
+
+lli_txphy_ls_clk: lli_txphy_ls_clk at 4a008f20 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_unipro1_m2_ck>;
+	bit-shift = <9>;
+	reg = <0x4a008f20 0x4>;
+};
+
+mmc1_32khz_clk: mmc1_32khz_clk at 4a009628 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009628 0x4>;
+};
+
+sata_ref_clk: sata_ref_clk at 4a009688 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_clkin>;
+	bit-shift = <8>;
+	reg = <0x4a009688 0x4>;
+};
+
+slimbus1_slimbus_clk: slimbus1_slimbus_clk at 4a004560 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&slimbus_clk>;
+	bit-shift = <11>;
+	reg = <0x4a004560 0x4>;
+};
+
+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <13>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <14>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	bit-shift = <7>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <11>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <12>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <6>;
+	reg = <0x4a009658 0x4>;
+};
+
+utmi_p1_gfclk: utmi_p1_gfclk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009658 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&utmi_p1_gfclk>;
+	bit-shift = <8>;
+	reg = <0x4a009658 0x4>;
+};
+
+utmi_p2_gfclk: utmi_p2_gfclk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
+	bit-shift = <25>;
+	reg = <0x4a009658 0x4>;
+	bit-mask = <0x1>;
+};
+
+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&utmi_p2_gfclk>;
+	bit-shift = <9>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk at 4a009658 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <10>;
+	reg = <0x4a009658 0x4>;
+};
+
+usb_otg_ss_refclk960m: usb_otg_ss_refclk960m at 4a0096f0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_clkdcoldo>;
+	bit-shift = <8>;
+	reg = <0x4a0096f0 0x4>;
+};
+
+usb_phy_cm_clk32k: usb_phy_cm_clk32k at 4a008640 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008640 0x4>;
+};
+
+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk at 4a009668 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <8>;
+	reg = <0x4a009668 0x4>;
+};
+
+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk at 4a009668 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009668 0x4>;
+};
+
+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk at 4a009668 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&l3init_60m_fclk>;
+	bit-shift = <10>;
+	reg = <0x4a009668 0x4>;
+};
+
+aess_fclk: aess_fclk at 4a004528 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&abe_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004528 0x4>;
+	bit-mask = <0x1>;
+};
+
+dmic_sync_mux_ck: dmic_sync_mux_ck at 4a004538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004538 0x4>;
+	bit-mask = <0x3>;
+};
+
+dmic_gfclk: dmic_gfclk at 4a004538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004538 0x4>;
+	bit-mask = <0x3>;
+};
+
+fdif_fclk: fdif_fclk at 4a009328 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_h11x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009328 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpu_core_gclk_mux: gpu_core_gclk_mux at 4a009520 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009520 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux at 4a009520 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+	bit-shift = <25>;
+	reg = <0x4a009520 0x4>;
+	bit-mask = <0x1>;
+};
+
+hsi_fclk: hsi_fclk at 4a009638 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009638 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcasp_sync_mux_ck: mcasp_sync_mux_ck at 4a004540 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004540 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp_gfclk: mcasp_gfclk at 4a004540 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004540 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck at 4a004548 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004548 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp1_gfclk: mcbsp1_gfclk at 4a004548 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004548 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck at 4a004550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004550 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp2_gfclk: mcbsp2_gfclk at 4a004550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004550 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck at 4a004558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+	bit-shift = <26>;
+	reg = <0x4a004558 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcbsp3_gfclk: mcbsp3_gfclk at 4a004558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+	bit-shift = <24>;
+	reg = <0x4a004558 0x4>;
+	bit-mask = <0x3>;
+};
+
+mmc1_fclk_mux: mmc1_fclk_mux at 4a009628 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009628 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc1_fclk: mmc1_fclk at 4a009628 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc1_fclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009628 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc2_fclk_mux: mmc2_fclk_mux at 4a009630 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009630 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc2_fclk: mmc2_fclk at 4a009630 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc2_fclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009630 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer10_gfclk_mux: timer10_gfclk_mux at 4a009028 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009028 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer11_gfclk_mux: timer11_gfclk_mux at 4a009030 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009030 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer1_gfclk_mux: timer1_gfclk_mux at 4ae07940 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4ae07940 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer2_gfclk_mux: timer2_gfclk_mux at 4a009038 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009038 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer3_gfclk_mux: timer3_gfclk_mux at 4a009040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009040 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer4_gfclk_mux: timer4_gfclk_mux at 4a009048 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009048 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer5_gfclk_mux: timer5_gfclk_mux at 4a004568 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004568 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer6_gfclk_mux: timer6_gfclk_mux at 4a004570 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004570 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer7_gfclk_mux: timer7_gfclk_mux at 4a004578 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004578 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer8_gfclk_mux: timer8_gfclk_mux at 4a004580 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a004580 0x4>;
+	bit-mask = <0x1>;
+};
+
+timer9_gfclk_mux: timer9_gfclk_mux at 4a009050 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&sys_32k_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009050 0x4>;
+	bit-mask = <0x1>;
+};
+
+auxclk0_src_mux_ck: auxclk0_src_mux_ck at 4ae0a310 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a310 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk0_src_ck: auxclk0_src_ck at 4ae0a310 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk0_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a310 0x4>;
+};
+
+auxclk0_ck: auxclk0_ck at 4ae0a310 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk0_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a310 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk1_src_mux_ck: auxclk1_src_mux_ck at 4ae0a314 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a314 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk1_src_ck: auxclk1_src_ck at 4ae0a314 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk1_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a314 0x4>;
+};
+
+auxclk1_ck: auxclk1_ck at 4ae0a314 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk1_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a314 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk2_src_mux_ck: auxclk2_src_mux_ck at 4ae0a318 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a318 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk2_src_ck: auxclk2_src_ck at 4ae0a318 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk2_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a318 0x4>;
+};
+
+auxclk2_ck: auxclk2_ck at 4ae0a318 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk2_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a318 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk3_src_mux_ck: auxclk3_src_mux_ck at 4ae0a31c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a31c 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk3_src_ck: auxclk3_src_ck at 4ae0a31c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk3_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a31c 0x4>;
+};
+
+auxclk3_ck: auxclk3_ck at 4ae0a31c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk3_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a31c 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclk4_src_mux_ck: auxclk4_src_mux_ck at 4ae0a320 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+	bit-shift = <1>;
+	reg = <0x4ae0a320 0x4>;
+	bit-mask = <0x3>;
+};
+
+auxclk4_src_ck: auxclk4_src_ck at 4ae0a320 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&auxclk4_src_mux_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae0a320 0x4>;
+};
+
+auxclk4_ck: auxclk4_ck at 4ae0a320 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&auxclk4_src_ck>;
+	bit-shift = <16>;
+	reg = <0x4ae0a320 0x4>;
+	bit-mask = <0xf>;
+};
+
+auxclkreq0_ck: auxclkreq0_ck at 4ae0a210 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+	bit-shift = <2>;
+	reg = <0x4ae0a210 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq1_ck: auxclkreq1_ck at 4ae0a214 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+	bit-shift = <2>;
+	reg = <0x4ae0a214 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq2_ck: auxclkreq2_ck at 4ae0a218 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+	bit-shift = <2>;
+	reg = <0x4ae0a218 0x4>;
+	bit-mask = <0x7>;
+};
+
+auxclkreq3_ck: auxclkreq3_ck at 4ae0a21c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+	bit-shift = <2>;
+	reg = <0x4ae0a21c 0x4>;
+	bit-mask = <0x7>;
+};
-- 
1.7.9.5

[PATCHv4 12/33] CLK: omap: add omap5 clock init file

[Tero Kristo]

clk-54xx.c now contains the clock init functionality for omap5, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/Makefile   |    2 +-
 drivers/clk/omap/clk-54xx.c |   58 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/omap/clk-54xx.c

diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index 9ad10be..74385f2 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1,2 +1,2 @@
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
-					   clk-44xx.o
+					   clk-44xx.o clk-54xx.o
diff --git a/drivers/clk/omap/clk-54xx.c b/drivers/clk/omap/clk-54xx.c
new file mode 100644
index 0000000..ade0481
--- /dev/null
+++ b/drivers/clk/omap/clk-54xx.c
@@ -0,0 +1,58 @@
+/*
+ * OMAP5 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk/omap.h>
+
+#define OMAP5_DPLL_ABE_DEFFREQ				98304000
+
+static struct omap_dt_clk omap54xx_clks[] = {
+	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+	DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.2", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.3", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.4", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.9", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.10", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.11", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.5", "sys_ck", "dss_syc_gfclk_div"),
+	DT_CLK("omap_timer.6", "sys_ck", "dss_syc_gfclk_div"),
+	DT_CLK("omap_timer.7", "sys_ck", "dss_syc_gfclk_div"),
+	DT_CLK("omap_timer.8", "sys_ck", "dss_syc_gfclk_div"),
+};
+
+int __init omap5xxx_clk_init(void)
+{
+	int rc;
+	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+
+	dt_omap_clk_init();
+
+	omap_dt_clocks_register(omap54xx_clks, ARRAY_SIZE(omap54xx_clks));
+
+	omap2_clk_disable_autoidle_all();
+
+	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
+	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+	if (!rc)
+		rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+	return 0;
+}
-- 
1.7.9.5

[PATCHv4 12/33] CLK: omap: add omap5 clock init file

[Tero Kristo]

clk-54xx.c now contains the clock init functionality for omap5, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/Makefile   |    2 +-
 drivers/clk/omap/clk-54xx.c |   58 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/omap/clk-54xx.c

diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index 9ad10be..74385f2 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1,2 +1,2 @@
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
-					   clk-44xx.o
+					   clk-44xx.o clk-54xx.o
diff --git a/drivers/clk/omap/clk-54xx.c b/drivers/clk/omap/clk-54xx.c
new file mode 100644
index 0000000..ade0481
--- /dev/null
+++ b/drivers/clk/omap/clk-54xx.c
@@ -0,0 +1,58 @@
+/*
+ * OMAP5 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk/omap.h>
+
+#define OMAP5_DPLL_ABE_DEFFREQ				98304000
+
+static struct omap_dt_clk omap54xx_clks[] = {
+	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+	DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.2", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.3", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.4", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.9", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.10", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.11", "sys_ck", "sys_clkin"),
+	DT_CLK("omap_timer.5", "sys_ck", "dss_syc_gfclk_div"),
+	DT_CLK("omap_timer.6", "sys_ck", "dss_syc_gfclk_div"),
+	DT_CLK("omap_timer.7", "sys_ck", "dss_syc_gfclk_div"),
+	DT_CLK("omap_timer.8", "sys_ck", "dss_syc_gfclk_div"),
+};
+
+int __init omap5xxx_clk_init(void)
+{
+	int rc;
+	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+
+	dt_omap_clk_init();
+
+	omap_dt_clocks_register(omap54xx_clks, ARRAY_SIZE(omap54xx_clks));
+
+	omap2_clk_disable_autoidle_all();
+
+	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
+	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
+	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
+	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
+	if (!rc)
+		rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+	return 0;
+}
-- 
1.7.9.5

[PATCHv4 13/33] ARM: dts: dra7 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).

TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 2081 ++++++++++++++++++++++++++++++++++
 1 file changed, 2081 insertions(+)
 create mode 100644 arch/arm/boot/dts/dra7xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
new file mode 100644
index 0000000..8477ff9
--- /dev/null
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -0,0 +1,2081 @@
+/*
+ * Device Tree Source for DRA7xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+atl_clkin0_ck: atl_clkin0_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+atl_clkin1_ck: atl_clkin1_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+atl_clkin2_ck: atl_clkin2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+atlclkin3_ck: atlclkin3_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+hdmi_clkin_ck: hdmi_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+mlb_clkin_ck: mlb_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+mlbp_clkin_ck: mlbp_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <100000000>;
+};
+
+ref_clkin0_ck: ref_clkin0_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+ref_clkin1_ck: ref_clkin1_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+ref_clkin2_ck: ref_clkin2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+ref_clkin3_ck: ref_clkin3_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+rmii_clk_ck: rmii_clk_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+sdvenc_clkin_ck: sdvenc_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+sys_32k_ck: sys_32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_20000000_ck: virt_20000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <20000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <38400000>;
+};
+
+sys_clkin1: sys_clkin1@4ae06110 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+	reg = <0x4ae06110 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+sys_clkin2: sys_clkin2 {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <22579200>;
+};
+
+usb_otg_clkin_ck: usb_otg_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+video1_clkin_ck: video1_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+video1_m2_clkin_ck: video1_m2_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+video2_clkin_ck: video2_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+video2_m2_clkin_ck: video2_m2_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@4ae06118 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	reg = <0x4ae06118 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@4ae06114 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+	reg = <0x4ae06114 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_dpll_clk_mux: abe_dpll_clk_mux@4ae0610c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+	reg = <0x4ae0610c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_abe_ck: dpll_abe_ck@4a0051e0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+	reg = <0x4a0051e0 0x4>, <0x4a0051e4 0x4>, <0x4a0051e8 0x4>, <0x4a0051ec 0x4>;
+	ti,clk-ref = <&abe_dpll_clk_mux>;
+	ti,clk-bypass = <&abe_dpll_bypass_clk_mux>;
+	ti,dpll-regm4xen;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_abe_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0051f0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0051f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk@4ae0611c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4ae0611c 0x4>;
+	table = < 8 0 >, < 16 1 >;
+	bit-mask = <0x1>;
+};
+
+abe_clk: abe_clk@4a005108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4a005108 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+aess_fclk: aess_fclk@4ae06178 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&abe_clk>;
+	reg = <0x4ae06178 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_giclk_div: abe_giclk_div@4ae06174 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&aess_fclk>;
+	reg = <0x4ae06174 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_lp_clk_div: abe_lp_clk_div@4ae061d8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4ae061d8 0x4>;
+	table = < 16 0 >, < 32 1 >;
+	bit-mask = <0x1>;
+};
+
+abe_sys_clk_div: abe_sys_clk_div@4ae06120 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae06120 0x4>;
+	bit-mask = <0x1>;
+};
+
+adc_gfclk_mux: adc_gfclk_mux@4ae061dc {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
+	reg = <0x4ae061dc 0x4>;
+	bit-mask = <0x7>;
+};
+
+dpll_pcie_ref_ck: dpll_pcie_ref_ck@4a008200 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&sys_clkin1>;
+};
+
+dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@4a008210 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_pcie_ref_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008210 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+apll_pcie_ck: apll_pcie_ck@4a008200 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_pcie_ref_ck>;
+	reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+	ti,clk-ref = <&dpll_pcie_ref_ck>;
+	ti,clk-bypass = <&dpll_pcie_ref_ck>;
+};
+
+apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&apll_pcie_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&apll_pcie_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+apll_pcie_m2_ck: apll_pcie_m2_ck@4a008224 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&apll_pcie_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008224 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+sys_clk1_dclk_div: sys_clk1_dclk_div@4ae061c8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae061c8 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+sys_clk2_dclk_div: sys_clk2_dclk_div@4ae061cc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin2>;
+	reg = <0x4ae061cc 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_abe_m2_ck: dpll_abe_m2_ck@4a0051f0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0051f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+per_abe_x1_dclk_div: per_abe_x1_dclk_div@4ae061bc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	reg = <0x4ae061bc 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0051f4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0051f4 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_ck: dpll_core_ck@4a005120 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a005120 0x4>, <0x4a005124 0x4>, <0x4a005128 0x4>, <0x4a00512c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+	ti,dpll-core;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_core_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_core_h12x2_ck: dpll_core_h12x2_ck@4a00513c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00513c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_mpu_ck: dpll_mpu_ck@4a005160 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
+	reg = <0x4a005160 0x4>, <0x4a005164 0x4>, <0x4a005168 0x4>, <0x4a00516c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&mpu_dpll_hs_clk_div>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a005170 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005170 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+mpu_dclk_div: mpu_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_mpu_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_dsp_ck: dpll_dsp_ck@4a005234 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+	reg = <0x4a005234 0x4>, <0x4a005238 0x4>, <0x4a00523c 0x4>, <0x4a005240 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dsp_dpll_hs_clk_div>;
+};
+
+dpll_dsp_m2_ck: dpll_dsp_m2_ck@4a005244 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_dsp_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005244 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dsp_gclk_div: dsp_gclk_div@4ae0618c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_dsp_m2_ck>;
+	reg = <0x4ae0618c 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_iva_ck: dpll_iva_ck@4a0051a0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+	reg = <0x4a0051a0 0x4>, <0x4a0051a4 0x4>, <0x4a0051a8 0x4>, <0x4a0051ac 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&iva_dpll_hs_clk_div>;
+};
+
+dpll_iva_m2_ck: dpll_iva_m2_ck@4a0051b0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_iva_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0051b0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+iva_dclk: iva_dclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_iva_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_gpu_ck: dpll_gpu_ck@4a0052d8 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a0052d8 0x4>, <0x4a0052dc 0x4>, <0x4a0052e0 0x4>, <0x4a0052e4 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+};
+
+dpll_gpu_m2_ck: dpll_gpu_m2_ck@4a0052e8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gpu_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052e8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+gpu_dclk: gpu_dclk@4ae061a0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gpu_m2_ck>;
+	reg = <0x4ae061a0 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck@4a005130 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005130 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_ddr_ck: dpll_ddr_ck@4a005210 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a005210 0x4>, <0x4a005214 0x4>, <0x4a005218 0x4>, <0x4a00521c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a005220 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_ddr_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005220 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+emif_phy_dclk_div: emif_phy_dclk_div@4ae06190 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_ddr_m2_ck>;
+	reg = <0x4ae06190 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_gmac_ck: dpll_gmac_ck@4a0052a8 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a0052a8 0x4>, <0x4a0052ac 0x4>, <0x4a0052b0 0x4>, <0x4a0052b4 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+};
+
+dpll_gmac_m2_ck: dpll_gmac_m2_ck@4a0052b8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052b8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+gmac_250m_dclk_div: gmac_250m_dclk_div@4ae0619c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_m2_ck>;
+	reg = <0x4ae0619c 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+video2_dclk_div: video2_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video2_m2_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video1_dclk_div: video1_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video1_m2_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+hdmi_dclk_div: hdmi_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&hdmi_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_per_ck: dpll_per_ck@4a008140 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+	reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&per_dpll_hs_clk_div>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck@4a008150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck@4a008180 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+	ti,clk-bypass = <&usb_dpll_hs_clk_div>;
+	reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clkdm-name = "coreaon_clkdm";
+	ti,dpll-j-type;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008190 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+l3init_480m_dclk_div: l3init_480m_dclk_div@4ae061ac {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	reg = <0x4ae061ac 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+usb_otg_dclk_div: usb_otg_dclk_div@4ae06184 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&usb_otg_clkin_ck>;
+	reg = <0x4ae06184 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+sata_dclk_div: sata_dclk_div@4ae061c0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae061c0 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@4a008210 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_pcie_ref_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008210 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+pcie2_dclk_div: pcie2_dclk_div@4ae061b8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_pcie_ref_m2_ck>;
+	reg = <0x4ae061b8 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+pcie_dclk_div: pcie_dclk_div@4ae061b4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&apll_pcie_m2_ck>;
+	reg = <0x4ae061b4 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+emu_dclk_div: emu_dclk_div@4ae06194 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae06194 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+secure_32k_dclk_div: secure_32k_dclk_div@4ae061c4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&secure_32k_clk_src_ck>;
+	reg = <0x4ae061c4 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_eve_ck: dpll_eve_ck@4a005284 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+	reg = <0x4a005284 0x4>, <0x4a005288 0x4>, <0x4a00528c 0x4>, <0x4a005290 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&eve_dpll_hs_clk_div>;
+};
+
+dpll_eve_m2_ck: dpll_eve_m2_ck@4a005294 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_eve_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005294 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+eve_dclk_div: eve_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_eve_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+clkoutmux0_clk_mux: clkoutmux0_clk_mux@4ae06158 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+	reg = <0x4ae06158 0x4>;
+	bit-mask = <0x1f>;
+};
+
+clkoutmux1_clk_mux: clkoutmux1_clk_mux@4ae0615c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+	reg = <0x4ae0615c 0x4>;
+	bit-mask = <0x1f>;
+};
+
+clkoutmux2_clk_mux: clkoutmux2_clk_mux@4ae06160 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+	reg = <0x4ae06160 0x4>;
+	bit-mask = <0x1f>;
+};
+
+custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin1>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_core_h13x2_ck: dpll_core_h13x2_ck@4a005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005140 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h14x2_ck: dpll_core_h14x2_ck@4a005144 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005144 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h22x2_ck: dpll_core_h22x2_ck@4a005154 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005154 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h23x2_ck: dpll_core_h23x2_ck@4a005158 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005158 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h24x2_ck: dpll_core_h24x2_ck@4a00515c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00515c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_ddr_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@4a005228 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_ddr_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005228 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_dsp_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@4a005248 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_dsp_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005248 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_gmac_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@4a0052c0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052c0 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@4a0052c4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052c4 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@4a0052c8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052c8 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@4a0052bc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052bc 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_per_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_per_h11x2_ck: dpll_per_h11x2_ck@4a008158 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008158 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h12x2_ck: dpll_per_h12x2_ck@4a00815c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00815c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h13x2_ck: dpll_per_h13x2_ck@4a008160 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008160 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h14x2_ck: dpll_per_h14x2_ck@4a008164 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008164 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_usb_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+eve_clk: eve_clk@4ae06180 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
+	reg = <0x4ae06180 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_128m_clk: func_128m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_h11x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+func_12m_fclk: func_12m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_48m_fclk: func_48m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_96m_fclk: func_96m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+gmii_m_clk_div: gmii_m_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_gmac_h11x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+hdmi_clk2_div: hdmi_clk2_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&hdmi_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+hdmi_div_clk: hdmi_div_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&hdmi_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@4ae061a4 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	reg = <0x4ae061a4 0x4>;
+	bit-mask = <0x7>;
+};
+
+l3_iclk_div: l3_iclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3init_60m_fclk: l3init_60m_fclk@4a008104 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	reg = <0x4a008104 0x4>;
+	table = < 1 0 >, < 8 1 >;
+	bit-mask = <0x1>;
+};
+
+l4_root_clk_div: l4_root_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_iclk_div>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mlb_clk: mlb_clk@4ae06134 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mlb_clkin_ck>;
+	reg = <0x4ae06134 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+mlbp_clk: mlbp_clk@4ae06130 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mlbp_clkin_ck>;
+	reg = <0x4ae06130 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@4ae06138 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	reg = <0x4ae06138 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+timer_sys_clk_div: timer_sys_clk_div@4ae06144 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae06144 0x4>;
+	bit-mask = <0x1>;
+};
+
+video1_clk2_div: video1_clk2_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video1_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video1_div_clk: video1_div_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video1_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video1_dpll_clk_mux: video1_dpll_clk_mux@4ae061d0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	reg = <0x4ae061d0 0x4>;
+	bit-mask = <0x7>;
+};
+
+video2_clk2_div: video2_clk2_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video2_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video2_div_clk: video2_div_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video2_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video2_dpll_clk_mux: video2_dpll_clk_mux@4ae061d4 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	reg = <0x4ae061d4 0x4>;
+	bit-mask = <0x7>;
+};
+
+wkupaon_iclk_mux: wkupaon_iclk_mux@4ae06108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
+	reg = <0x4ae06108 0x4>;
+	bit-mask = <0x1>;
+};
+
+dss_32khz_clk: dss_32khz_clk@4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <11>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk@4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk@4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_h12x2_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_hdmi_clk: dss_hdmi_clk@4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&hdmi_dpll_clk_mux>;
+	bit-shift = <10>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_video1_clk: dss_video1_clk@4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&video1_dpll_clk_mux>;
+	bit-shift = <12>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_video2_clk: dss_video2_clk@4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&video2_dpll_clk_mux>;
+	bit-shift = <13>;
+	reg = <0x4a009120 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk@4ae07838 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae07838 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk@4a009760 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009760 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk@4a009768 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009768 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk@4a009770 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009770 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk@4a009778 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009778 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk@4a009780 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009780 0x4>;
+};
+
+gpio7_dbclk: gpio7_dbclk@4a009810 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009810 0x4>;
+};
+
+gpio8_dbclk: gpio8_dbclk@4a009818 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009818 0x4>;
+};
+
+mmc1_clk32k: mmc1_clk32k@4a009328 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009328 0x4>;
+};
+
+mmc2_clk32k: mmc2_clk32k@4a009330 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009330 0x4>;
+};
+
+mmc3_clk32k: mmc3_clk32k@4a009820 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009820 0x4>;
+};
+
+mmc4_clk32k: mmc4_clk32k@4a009828 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009828 0x4>;
+};
+
+sata_ref_clk: sata_ref_clk@4a009388 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_clkin1>;
+	bit-shift = <8>;
+	reg = <0x4a009388 0x4>;
+};
+
+usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@4a0093f0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_clkdcoldo>;
+	bit-shift = <8>;
+	reg = <0x4a0093f0 0x4>;
+};
+
+usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@4a009340 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_clkdcoldo>;
+	bit-shift = <8>;
+	reg = <0x4a009340 0x4>;
+};
+
+usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@4a008640 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008640 0x4>;
+};
+
+usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@4a008688 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008688 0x4>;
+};
+
+usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@4a008698 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008698 0x4>;
+};
+
+atl_dpll_clk_mux: atl_dpll_clk_mux@4a008c00 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
+	bit-shift = <24>;
+	reg = <0x4a008c00 0x4>;
+	bit-mask = <0x3>;
+};
+
+atl_gfclk_mux: atl_gfclk_mux@4a008c00 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
+	bit-shift = <26>;
+	reg = <0x4a008c00 0x4>;
+	bit-mask = <0x3>;
+};
+
+dcan1_sys_clk_mux: dcan1_sys_clk_mux@4ae07888 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	bit-shift = <24>;
+	reg = <0x4ae07888 0x4>;
+	bit-mask = <0x1>;
+};
+
+gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@4a0093d0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_m2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0093d0 0x4>;
+	table = < 2 0 >;
+	bit-mask = <0x1>;
+};
+
+gmac_rft_clk_mux: gmac_rft_clk_mux@4a0093d0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
+	bit-shift = <25>;
+	reg = <0x4a0093d0 0x4>;
+	bit-mask = <0x7>;
+};
+
+gpu_core_gclk_mux: gpu_core_gclk_mux@4a009220 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009220 0x4>;
+	bit-mask = <0x3>;
+};
+
+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@4a009220 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+	bit-shift = <26>;
+	reg = <0x4a009220 0x4>;
+	bit-mask = <0x3>;
+};
+
+ipu1_gfclk_mux: ipu1_gfclk_mux@4a005520 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a005520 0x4>;
+	bit-mask = <0x1>;
+};
+
+l3instr_ts_gclk_div: l3instr_ts_gclk_div@4a008e50 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&wkupaon_iclk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a008e50 0x4>;
+	table = < 8 0 >, < 16 1 >, < 32 2 >;
+	bit-mask = <0x3>;
+};
+
+mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@4a005550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <28>;
+	reg = <0x4a005550 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@4a005550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a005550 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@4a005550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a005550 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@4a009860 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <28>;
+	reg = <0x4a009860 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@4a009860 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <28>;
+	reg = <0x4a009860 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@4a009860 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009860 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@4a009868 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009868 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@4a009868 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009868 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@4a009898 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009898 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@4a009898 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009898 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@4a009878 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009878 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@4a009878 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009878 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@4a009904 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009904 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@4a009904 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009904 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@4a009908 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009908 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@4a009908 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009908 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp8_ahclk_mux: mcasp8_ahclk_mux@4a009890 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <22>;
+	reg = <0x4a009890 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@4a009890 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <24>;
+	reg = <0x4a009890 0x4>;
+	bit-mask = <0xf>;
+};
+
+mmc1_fclk_mux: mmc1_fclk_mux@4a009328 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009328 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc1_fclk_div: mmc1_fclk_div@4a009328 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc1_fclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009328 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+mmc2_fclk_mux: mmc2_fclk_mux@4a009330 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009330 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc2_fclk_div: mmc2_fclk_div@4a009330 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc2_fclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009330 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+mmc3_gfclk_mux: mmc3_gfclk_mux@4a009820 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009820 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc3_gfclk_div: mmc3_gfclk_div@4a009820 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc3_gfclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009820 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+mmc4_gfclk_mux: mmc4_gfclk_mux@4a009828 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009828 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc4_gfclk_div: mmc4_gfclk_div@4a009828 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc4_gfclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009828 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+qspi_gfclk_mux: qspi_gfclk_mux@4a009838 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009838 0x4>;
+	bit-mask = <0x1>;
+};
+
+qspi_gfclk_div: qspi_gfclk_div@4a009838 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&qspi_gfclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009838 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+timer10_gfclk_mux: timer10_gfclk_mux@4a009728 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009728 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer11_gfclk_mux: timer11_gfclk_mux@4a009730 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009730 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer13_gfclk_mux: timer13_gfclk_mux@4a0097c8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a0097c8 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer14_gfclk_mux: timer14_gfclk_mux@4a0097d0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a0097d0 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer15_gfclk_mux: timer15_gfclk_mux@4a0097d8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a0097d8 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer16_gfclk_mux: timer16_gfclk_mux@4a009830 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009830 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer1_gfclk_mux: timer1_gfclk_mux@4ae07840 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4ae07840 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer2_gfclk_mux: timer2_gfclk_mux@4a009738 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009738 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer3_gfclk_mux: timer3_gfclk_mux@4a009740 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009740 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer4_gfclk_mux: timer4_gfclk_mux@4a009748 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009748 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer5_gfclk_mux: timer5_gfclk_mux@4a005558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a005558 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer6_gfclk_mux: timer6_gfclk_mux@4a005560 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a005560 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer7_gfclk_mux: timer7_gfclk_mux@4a005568 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a005568 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer8_gfclk_mux: timer8_gfclk_mux@4a005570 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a005570 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer9_gfclk_mux: timer9_gfclk_mux@4a009750 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009750 0x4>;
+	bit-mask = <0xf>;
+};
+
+uart10_gfclk_mux: uart10_gfclk_mux@4ae07880 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4ae07880 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart1_gfclk_mux: uart1_gfclk_mux@4a009840 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009840 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart2_gfclk_mux: uart2_gfclk_mux@4a009848 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009848 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart3_gfclk_mux: uart3_gfclk_mux@4a009850 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009850 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart4_gfclk_mux: uart4_gfclk_mux@4a009858 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009858 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart5_gfclk_mux: uart5_gfclk_mux@4a009870 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009870 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart6_gfclk_mux: uart6_gfclk_mux@4a005580 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a005580 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart7_gfclk_mux: uart7_gfclk_mux@4a0098d0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0098d0 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart8_gfclk_mux: uart8_gfclk_mux@4a0098e0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0098e0 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart9_gfclk_mux: uart9_gfclk_mux@4a0098e8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0098e8 0x4>;
+	bit-mask = <0x1>;
+};
+
+vip1_gclk_mux: vip1_gclk_mux@4a009020 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009020 0x4>;
+	bit-mask = <0x1>;
+};
+
+vip2_gclk_mux: vip2_gclk_mux@4a009028 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009028 0x4>;
+	bit-mask = <0x1>;
+};
+
+vip3_gclk_mux: vip3_gclk_mux@4a009030 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009030 0x4>;
+	bit-mask = <0x1>;
+};
-- 
1.7.9.5

[PATCHv4 13/33] ARM: dts: dra7 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).

TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 2081 ++++++++++++++++++++++++++++++++++
 1 file changed, 2081 insertions(+)
 create mode 100644 arch/arm/boot/dts/dra7xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
new file mode 100644
index 0000000..8477ff9
--- /dev/null
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -0,0 +1,2081 @@
+/*
+ * Device Tree Source for DRA7xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+atl_clkin0_ck: atl_clkin0_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+atl_clkin1_ck: atl_clkin1_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+atl_clkin2_ck: atl_clkin2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+atlclkin3_ck: atlclkin3_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+hdmi_clkin_ck: hdmi_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+mlb_clkin_ck: mlb_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+mlbp_clkin_ck: mlbp_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <100000000>;
+};
+
+ref_clkin0_ck: ref_clkin0_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+ref_clkin1_ck: ref_clkin1_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+ref_clkin2_ck: ref_clkin2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+ref_clkin3_ck: ref_clkin3_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+rmii_clk_ck: rmii_clk_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+sdvenc_clkin_ck: sdvenc_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+sys_32k_ck: sys_32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_12000000_ck: virt_12000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+virt_13000000_ck: virt_13000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <13000000>;
+};
+
+virt_16800000_ck: virt_16800000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <16800000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_20000000_ck: virt_20000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <20000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+virt_27000000_ck: virt_27000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <27000000>;
+};
+
+virt_38400000_ck: virt_38400000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <38400000>;
+};
+
+sys_clkin1: sys_clkin1 at 4ae06110 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+	reg = <0x4ae06110 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+sys_clkin2: sys_clkin2 {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <22579200>;
+};
+
+usb_otg_clkin_ck: usb_otg_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+video1_clkin_ck: video1_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+video1_m2_clkin_ck: video1_m2_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+video2_clkin_ck: video2_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+video2_m2_clkin_ck: video2_m2_clkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0>;
+};
+
+abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux at 4ae06118 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	reg = <0x4ae06118 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux at 4ae06114 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+	reg = <0x4ae06114 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_dpll_clk_mux: abe_dpll_clk_mux at 4ae0610c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+	reg = <0x4ae0610c 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll_abe_ck: dpll_abe_ck at 4a0051e0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+	reg = <0x4a0051e0 0x4>, <0x4a0051e4 0x4>, <0x4a0051e8 0x4>, <0x4a0051ec 0x4>;
+	ti,clk-ref = <&abe_dpll_clk_mux>;
+	ti,clk-bypass = <&abe_dpll_bypass_clk_mux>;
+	ti,dpll-regm4xen;
+};
+
+dpll_abe_x2_ck: dpll_abe_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_abe_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0051f0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0051f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+abe_24m_fclk: abe_24m_fclk at 4ae0611c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4ae0611c 0x4>;
+	table = < 8 0 >, < 16 1 >;
+	bit-mask = <0x1>;
+};
+
+abe_clk: abe_clk at 4a005108 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4a005108 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+aess_fclk: aess_fclk at 4ae06178 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&abe_clk>;
+	reg = <0x4ae06178 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_giclk_div: abe_giclk_div at 4ae06174 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&aess_fclk>;
+	reg = <0x4ae06174 0x4>;
+	bit-mask = <0x1>;
+};
+
+abe_lp_clk_div: abe_lp_clk_div at 4ae061d8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2x2_ck>;
+	reg = <0x4ae061d8 0x4>;
+	table = < 16 0 >, < 32 1 >;
+	bit-mask = <0x1>;
+};
+
+abe_sys_clk_div: abe_sys_clk_div at 4ae06120 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae06120 0x4>;
+	bit-mask = <0x1>;
+};
+
+adc_gfclk_mux: adc_gfclk_mux at 4ae061dc {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
+	reg = <0x4ae061dc 0x4>;
+	bit-mask = <0x7>;
+};
+
+dpll_pcie_ref_ck: dpll_pcie_ref_ck at 4a008200 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&sys_clkin1>;
+};
+
+dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck at 4a008210 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_pcie_ref_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008210 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+apll_pcie_ck: apll_pcie_ck at 4a008200 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_pcie_ref_ck>;
+	reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
+	ti,clk-ref = <&dpll_pcie_ref_ck>;
+	ti,clk-bypass = <&dpll_pcie_ref_ck>;
+};
+
+apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&apll_pcie_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&apll_pcie_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+apll_pcie_m2_ck: apll_pcie_m2_ck at 4a008224 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&apll_pcie_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008224 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+sys_clk1_dclk_div: sys_clk1_dclk_div at 4ae061c8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae061c8 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+sys_clk2_dclk_div: sys_clk2_dclk_div at 4ae061cc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin2>;
+	reg = <0x4ae061cc 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_abe_m2_ck: dpll_abe_m2_ck at 4a0051f0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0051f0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+per_abe_x1_dclk_div: per_abe_x1_dclk_div at 4ae061bc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	reg = <0x4ae061bc 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 4a0051f4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0051f4 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_ck: dpll_core_ck at 4a005120 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a005120 0x4>, <0x4a005124 0x4>, <0x4a005128 0x4>, <0x4a00512c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+	ti,dpll-core;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_core_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_core_h12x2_ck: dpll_core_h12x2_ck at 4a00513c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00513c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 4a005160 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
+	reg = <0x4a005160 0x4>, <0x4a005164 0x4>, <0x4a005168 0x4>, <0x4a00516c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&mpu_dpll_hs_clk_div>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 4a005170 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005170 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+mpu_dclk_div: mpu_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_mpu_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_dsp_ck: dpll_dsp_ck at 4a005234 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+	reg = <0x4a005234 0x4>, <0x4a005238 0x4>, <0x4a00523c 0x4>, <0x4a005240 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dsp_dpll_hs_clk_div>;
+};
+
+dpll_dsp_m2_ck: dpll_dsp_m2_ck at 4a005244 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_dsp_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005244 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dsp_gclk_div: dsp_gclk_div at 4ae0618c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_dsp_m2_ck>;
+	reg = <0x4ae0618c 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_iva_ck: dpll_iva_ck at 4a0051a0 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+	reg = <0x4a0051a0 0x4>, <0x4a0051a4 0x4>, <0x4a0051a8 0x4>, <0x4a0051ac 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&iva_dpll_hs_clk_div>;
+};
+
+dpll_iva_m2_ck: dpll_iva_m2_ck at 4a0051b0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_iva_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0051b0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+iva_dclk: iva_dclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_iva_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_gpu_ck: dpll_gpu_ck at 4a0052d8 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a0052d8 0x4>, <0x4a0052dc 0x4>, <0x4a0052e0 0x4>, <0x4a0052e4 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+};
+
+dpll_gpu_m2_ck: dpll_gpu_m2_ck at 4a0052e8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gpu_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052e8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+gpu_dclk: gpu_dclk at 4ae061a0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gpu_m2_ck>;
+	reg = <0x4ae061a0 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_core_m2_ck: dpll_core_m2_ck at 4a005130 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005130 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_ddr_ck: dpll_ddr_ck at 4a005210 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a005210 0x4>, <0x4a005214 0x4>, <0x4a005218 0x4>, <0x4a00521c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck at 4a005220 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_ddr_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005220 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+emif_phy_dclk_div: emif_phy_dclk_div at 4ae06190 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_ddr_m2_ck>;
+	reg = <0x4ae06190 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_gmac_ck: dpll_gmac_ck at 4a0052a8 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+	reg = <0x4a0052a8 0x4>, <0x4a0052ac 0x4>, <0x4a0052b0 0x4>, <0x4a0052b4 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&dpll_abe_m3x2_ck>;
+};
+
+dpll_gmac_m2_ck: dpll_gmac_m2_ck at 4a0052b8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052b8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+gmac_250m_dclk_div: gmac_250m_dclk_div at 4ae0619c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_m2_ck>;
+	reg = <0x4ae0619c 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+video2_dclk_div: video2_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video2_m2_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video1_dclk_div: video1_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video1_m2_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+hdmi_dclk_div: hdmi_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&hdmi_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_per_ck: dpll_per_ck at 4a008140 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+	reg = <0x4a008140 0x4>, <0x4a008144 0x4>, <0x4a008148 0x4>, <0x4a00814c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&per_dpll_hs_clk_div>;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_abe_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+dpll_usb_ck: dpll_usb_ck at 4a008180 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+	ti,clk-bypass = <&usb_dpll_hs_clk_div>;
+	reg = <0x4a008180 0x4>, <0x4a008184 0x4>, <0x4a008188 0x4>, <0x4a00818c 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clkdm-name = "coreaon_clkdm";
+	ti,dpll-j-type;
+};
+
+dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008190 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+l3init_480m_dclk_div: l3init_480m_dclk_div at 4ae061ac {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	reg = <0x4ae061ac 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+usb_otg_dclk_div: usb_otg_dclk_div at 4ae06184 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&usb_otg_clkin_ck>;
+	reg = <0x4ae06184 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+sata_dclk_div: sata_dclk_div at 4ae061c0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae061c0 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck at 4a008210 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_pcie_ref_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008210 0x4>;
+	bit-mask = <0x7f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+pcie2_dclk_div: pcie2_dclk_div at 4ae061b8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_pcie_ref_m2_ck>;
+	reg = <0x4ae061b8 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+pcie_dclk_div: pcie_dclk_div at 4ae061b4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&apll_pcie_m2_ck>;
+	reg = <0x4ae061b4 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+emu_dclk_div: emu_dclk_div at 4ae06194 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae06194 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+secure_32k_dclk_div: secure_32k_dclk_div at 4ae061c4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&secure_32k_clk_src_ck>;
+	reg = <0x4ae061c4 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll_eve_ck: dpll_eve_ck at 4a005284 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+	reg = <0x4a005284 0x4>, <0x4a005288 0x4>, <0x4a00528c 0x4>, <0x4a005290 0x4>;
+	ti,clk-ref = <&sys_clkin1>;
+	ti,clk-bypass = <&eve_dpll_hs_clk_div>;
+};
+
+dpll_eve_m2_ck: dpll_eve_m2_ck at 4a005294 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_eve_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005294 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+eve_dclk_div: eve_dclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_eve_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+clkoutmux0_clk_mux: clkoutmux0_clk_mux at 4ae06158 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+	reg = <0x4ae06158 0x4>;
+	bit-mask = <0x1f>;
+};
+
+clkoutmux1_clk_mux: clkoutmux1_clk_mux at 4ae0615c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+	reg = <0x4ae0615c 0x4>;
+	bit-mask = <0x1f>;
+};
+
+clkoutmux2_clk_mux: clkoutmux2_clk_mux at 4ae06160 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+	reg = <0x4ae06160 0x4>;
+	bit-mask = <0x1f>;
+};
+
+custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin1>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_core_h13x2_ck: dpll_core_h13x2_ck at 4a005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005140 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h14x2_ck: dpll_core_h14x2_ck at 4a005144 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005144 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h22x2_ck: dpll_core_h22x2_ck at 4a005154 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005154 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h23x2_ck: dpll_core_h23x2_ck at 4a005158 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005158 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_core_h24x2_ck: dpll_core_h24x2_ck at 4a00515c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00515c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_ddr_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck at 4a005228 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_ddr_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005228 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_dsp_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck at 4a005248 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_dsp_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a005248 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_gmac_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck at 4a0052c0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052c0 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck at 4a0052c4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052c4 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck at 4a0052c8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052c8 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck at 4a0052bc {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a0052bc 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_x2_ck: dpll_per_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_per_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_per_h11x2_ck: dpll_per_h11x2_ck at 4a008158 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008158 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h12x2_ck: dpll_per_h12x2_ck at 4a00815c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a00815c 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h13x2_ck: dpll_per_h13x2_ck at 4a008160 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008160 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_h14x2_ck: dpll_per_h14x2_ck at 4a008164 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008164 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_per_m2x2_ck: dpll_per_m2x2_ck at 4a008150 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_x2_ck>;
+	ti,autoidle-shift = <8>;
+	reg = <0x4a008150 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	ti,autoidle-low;
+};
+
+dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_usb_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+eve_clk: eve_clk at 4ae06180 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
+	reg = <0x4ae06180 0x4>;
+	bit-mask = <0x1>;
+};
+
+func_128m_clk: func_128m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_h11x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+func_12m_fclk: func_12m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+func_24m_clk: func_24m_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_48m_fclk: func_48m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+func_96m_fclk: func_96m_fclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+gmii_m_clk_div: gmii_m_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_gmac_h11x2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+hdmi_clk2_div: hdmi_clk2_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&hdmi_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+hdmi_div_clk: hdmi_div_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&hdmi_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+hdmi_dpll_clk_mux: hdmi_dpll_clk_mux at 4ae061a4 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	reg = <0x4ae061a4 0x4>;
+	bit-mask = <0x7>;
+};
+
+l3_iclk_div: l3_iclk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_h12x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3init_60m_fclk: l3init_60m_fclk at 4a008104 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_usb_m2_ck>;
+	reg = <0x4a008104 0x4>;
+	table = < 1 0 >, < 8 1 >;
+	bit-mask = <0x1>;
+};
+
+l4_root_clk_div: l4_root_clk_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_iclk_div>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mlb_clk: mlb_clk at 4ae06134 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mlb_clkin_ck>;
+	reg = <0x4ae06134 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+mlbp_clk: mlbp_clk at 4ae06130 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mlbp_clkin_ck>;
+	reg = <0x4ae06130 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div at 4ae06138 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_abe_m2_ck>;
+	reg = <0x4ae06138 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+timer_sys_clk_div: timer_sys_clk_div at 4ae06144 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sys_clkin1>;
+	reg = <0x4ae06144 0x4>;
+	bit-mask = <0x1>;
+};
+
+video1_clk2_div: video1_clk2_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video1_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video1_div_clk: video1_div_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video1_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video1_dpll_clk_mux: video1_dpll_clk_mux at 4ae061d0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	reg = <0x4ae061d0 0x4>;
+	bit-mask = <0x7>;
+};
+
+video2_clk2_div: video2_clk2_div {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video2_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video2_div_clk: video2_div_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&video2_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+video2_dpll_clk_mux: video2_dpll_clk_mux at 4ae061d4 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	reg = <0x4ae061d4 0x4>;
+	bit-mask = <0x7>;
+};
+
+wkupaon_iclk_mux: wkupaon_iclk_mux at 4ae06108 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
+	reg = <0x4ae06108 0x4>;
+	bit-mask = <0x1>;
+};
+
+dss_32khz_clk: dss_32khz_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <11>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_48mhz_clk: dss_48mhz_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&func_48m_fclk>;
+	bit-shift = <9>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_dss_clk: dss_dss_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_h12x2_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_hdmi_clk: dss_hdmi_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&hdmi_dpll_clk_mux>;
+	bit-shift = <10>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_video1_clk: dss_video1_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&video1_dpll_clk_mux>;
+	bit-shift = <12>;
+	reg = <0x4a009120 0x4>;
+};
+
+dss_video2_clk: dss_video2_clk at 4a009120 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&video2_dpll_clk_mux>;
+	bit-shift = <13>;
+	reg = <0x4a009120 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk at 4ae07838 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4ae07838 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 4a009760 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009760 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 4a009768 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009768 0x4>;
+};
+
+gpio4_dbclk: gpio4_dbclk at 4a009770 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009770 0x4>;
+};
+
+gpio5_dbclk: gpio5_dbclk at 4a009778 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009778 0x4>;
+};
+
+gpio6_dbclk: gpio6_dbclk at 4a009780 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009780 0x4>;
+};
+
+gpio7_dbclk: gpio7_dbclk at 4a009810 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009810 0x4>;
+};
+
+gpio8_dbclk: gpio8_dbclk at 4a009818 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009818 0x4>;
+};
+
+mmc1_clk32k: mmc1_clk32k at 4a009328 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009328 0x4>;
+};
+
+mmc2_clk32k: mmc2_clk32k at 4a009330 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009330 0x4>;
+};
+
+mmc3_clk32k: mmc3_clk32k at 4a009820 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009820 0x4>;
+};
+
+mmc4_clk32k: mmc4_clk32k at 4a009828 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a009828 0x4>;
+};
+
+sata_ref_clk: sata_ref_clk at 4a009388 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_clkin1>;
+	bit-shift = <8>;
+	reg = <0x4a009388 0x4>;
+};
+
+usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m at 4a0093f0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_clkdcoldo>;
+	bit-shift = <8>;
+	reg = <0x4a0093f0 0x4>;
+};
+
+usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m at 4a009340 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_usb_clkdcoldo>;
+	bit-shift = <8>;
+	reg = <0x4a009340 0x4>;
+};
+
+usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k at 4a008640 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008640 0x4>;
+};
+
+usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k at 4a008688 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008688 0x4>;
+};
+
+usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k at 4a008698 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_32k_ck>;
+	bit-shift = <8>;
+	reg = <0x4a008698 0x4>;
+};
+
+atl_dpll_clk_mux: atl_dpll_clk_mux at 4a008c00 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
+	bit-shift = <24>;
+	reg = <0x4a008c00 0x4>;
+	bit-mask = <0x3>;
+};
+
+atl_gfclk_mux: atl_gfclk_mux at 4a008c00 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
+	bit-shift = <26>;
+	reg = <0x4a008c00 0x4>;
+	bit-mask = <0x3>;
+};
+
+dcan1_sys_clk_mux: dcan1_sys_clk_mux at 4ae07888 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin1>, <&sys_clkin2>;
+	bit-shift = <24>;
+	reg = <0x4ae07888 0x4>;
+	bit-mask = <0x1>;
+};
+
+gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div at 4a0093d0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_gmac_m2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0093d0 0x4>;
+	table = < 2 0 >;
+	bit-mask = <0x1>;
+};
+
+gmac_rft_clk_mux: gmac_rft_clk_mux at 4a0093d0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
+	bit-shift = <25>;
+	reg = <0x4a0093d0 0x4>;
+	bit-mask = <0x7>;
+};
+
+gpu_core_gclk_mux: gpu_core_gclk_mux at 4a009220 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009220 0x4>;
+	bit-mask = <0x3>;
+};
+
+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux at 4a009220 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+	bit-shift = <26>;
+	reg = <0x4a009220 0x4>;
+	bit-mask = <0x3>;
+};
+
+ipu1_gfclk_mux: ipu1_gfclk_mux at 4a005520 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a005520 0x4>;
+	bit-mask = <0x1>;
+};
+
+l3instr_ts_gclk_div: l3instr_ts_gclk_div at 4a008e50 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&wkupaon_iclk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a008e50 0x4>;
+	table = < 8 0 >, < 16 1 >, < 32 2 >;
+	bit-mask = <0x3>;
+};
+
+mcasp1_ahclkr_mux: mcasp1_ahclkr_mux at 4a005550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <28>;
+	reg = <0x4a005550 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp1_ahclkx_mux: mcasp1_ahclkx_mux at 4a005550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a005550 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux at 4a005550 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a005550 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp2_ahclkr_mux: mcasp2_ahclkr_mux at 4a009860 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <28>;
+	reg = <0x4a009860 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp2_ahclkx_mux: mcasp2_ahclkx_mux at 4a009860 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <28>;
+	reg = <0x4a009860 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux at 4a009860 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009860 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp3_ahclkx_mux: mcasp3_ahclkx_mux at 4a009868 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009868 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux at 4a009868 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009868 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp4_ahclkx_mux: mcasp4_ahclkx_mux at 4a009898 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009898 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux at 4a009898 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009898 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp5_ahclkx_mux: mcasp5_ahclkx_mux at 4a009878 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009878 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux at 4a009878 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009878 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp6_ahclkx_mux: mcasp6_ahclkx_mux at 4a009904 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009904 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux at 4a009904 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009904 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp7_ahclkx_mux: mcasp7_ahclkx_mux at 4a009908 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009908 0x4>;
+	bit-mask = <0xf>;
+};
+
+mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux at 4a009908 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <22>;
+	reg = <0x4a009908 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp8_ahclk_mux: mcasp8_ahclk_mux at 4a009890 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+	bit-shift = <22>;
+	reg = <0x4a009890 0x4>;
+	bit-mask = <0x3>;
+};
+
+mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux at 4a009890 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+	bit-shift = <24>;
+	reg = <0x4a009890 0x4>;
+	bit-mask = <0xf>;
+};
+
+mmc1_fclk_mux: mmc1_fclk_mux at 4a009328 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009328 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc1_fclk_div: mmc1_fclk_div at 4a009328 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc1_fclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009328 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+mmc2_fclk_mux: mmc2_fclk_mux at 4a009330 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009330 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc2_fclk_div: mmc2_fclk_div at 4a009330 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc2_fclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009330 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+mmc3_gfclk_mux: mmc3_gfclk_mux at 4a009820 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009820 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc3_gfclk_div: mmc3_gfclk_div at 4a009820 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc3_gfclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009820 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+mmc4_gfclk_mux: mmc4_gfclk_mux at 4a009828 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009828 0x4>;
+	bit-mask = <0x1>;
+};
+
+mmc4_gfclk_div: mmc4_gfclk_div at 4a009828 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mmc4_gfclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009828 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+qspi_gfclk_mux: qspi_gfclk_mux at 4a009838 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009838 0x4>;
+	bit-mask = <0x1>;
+};
+
+qspi_gfclk_div: qspi_gfclk_div at 4a009838 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&qspi_gfclk_mux>;
+	bit-shift = <25>;
+	reg = <0x4a009838 0x4>;
+	bit-mask = <0x3>;
+	index-power-of-two;
+};
+
+timer10_gfclk_mux: timer10_gfclk_mux at 4a009728 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009728 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer11_gfclk_mux: timer11_gfclk_mux at 4a009730 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009730 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer13_gfclk_mux: timer13_gfclk_mux at 4a0097c8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a0097c8 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer14_gfclk_mux: timer14_gfclk_mux at 4a0097d0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a0097d0 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer15_gfclk_mux: timer15_gfclk_mux at 4a0097d8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a0097d8 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer16_gfclk_mux: timer16_gfclk_mux at 4a009830 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009830 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer1_gfclk_mux: timer1_gfclk_mux at 4ae07840 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4ae07840 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer2_gfclk_mux: timer2_gfclk_mux at 4a009738 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009738 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer3_gfclk_mux: timer3_gfclk_mux at 4a009740 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009740 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer4_gfclk_mux: timer4_gfclk_mux at 4a009748 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009748 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer5_gfclk_mux: timer5_gfclk_mux at 4a005558 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a005558 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer6_gfclk_mux: timer6_gfclk_mux at 4a005560 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a005560 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer7_gfclk_mux: timer7_gfclk_mux at 4a005568 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a005568 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer8_gfclk_mux: timer8_gfclk_mux at 4a005570 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+	bit-shift = <24>;
+	reg = <0x4a005570 0x4>;
+	bit-mask = <0xf>;
+};
+
+timer9_gfclk_mux: timer9_gfclk_mux at 4a009750 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+	bit-shift = <24>;
+	reg = <0x4a009750 0x4>;
+	bit-mask = <0xf>;
+};
+
+uart10_gfclk_mux: uart10_gfclk_mux at 4ae07880 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4ae07880 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart1_gfclk_mux: uart1_gfclk_mux at 4a009840 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009840 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart2_gfclk_mux: uart2_gfclk_mux at 4a009848 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009848 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart3_gfclk_mux: uart3_gfclk_mux at 4a009850 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009850 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart4_gfclk_mux: uart4_gfclk_mux at 4a009858 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009858 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart5_gfclk_mux: uart5_gfclk_mux at 4a009870 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009870 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart6_gfclk_mux: uart6_gfclk_mux at 4a005580 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a005580 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart7_gfclk_mux: uart7_gfclk_mux at 4a0098d0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0098d0 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart8_gfclk_mux: uart8_gfclk_mux at 4a0098e0 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0098e0 0x4>;
+	bit-mask = <0x1>;
+};
+
+uart9_gfclk_mux: uart9_gfclk_mux at 4a0098e8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a0098e8 0x4>;
+	bit-mask = <0x1>;
+};
+
+vip1_gclk_mux: vip1_gclk_mux at 4a009020 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009020 0x4>;
+	bit-mask = <0x1>;
+};
+
+vip2_gclk_mux: vip2_gclk_mux at 4a009028 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009028 0x4>;
+	bit-mask = <0x1>;
+};
+
+vip3_gclk_mux: vip3_gclk_mux at 4a009030 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+	bit-shift = <24>;
+	reg = <0x4a009030 0x4>;
+	bit-mask = <0x1>;
+};
-- 
1.7.9.5

[PATCHv4 14/33] CLK: omap: add dra7 clock init file

[Tero Kristo]

clk-7xx.c now contains the clock init functionality for dra7, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/Makefile  |    2 +-
 drivers/clk/omap/clk-7xx.c |   67 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 68 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/omap/clk-7xx.c

diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index 74385f2..b8dbfda 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1,2 +1,2 @@
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
-					   clk-44xx.o clk-54xx.o
+					   clk-44xx.o clk-54xx.o clk-7xx.o
diff --git a/drivers/clk/omap/clk-7xx.c b/drivers/clk/omap/clk-7xx.c
new file mode 100644
index 0000000..ddb39dd
--- /dev/null
+++ b/drivers/clk/omap/clk-7xx.c
@@ -0,0 +1,67 @@
+/*
+ * DRA7 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk/omap.h>
+
+#define DRA7_DPLL_ABE_DEFFREQ				361267200
+#define DRA7_DPLL_GMAC_DEFFREQ				1000000000
+
+
+static struct omap_dt_clk dra7xx_clks[] = {
+	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+	DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
+};
+
+int __init dra7xx_clk_init(void)
+{
+	int rc;
+	struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+
+	dt_omap_clk_init();
+
+	omap_dt_clocks_register(dra7xx_clks, ARRAY_SIZE(dra7xx_clks));
+
+	omap2_clk_disable_autoidle_all();
+
+	abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux");
+	sys_clkin2 = clk_get_sys(NULL, "sys_clkin2");
+	dpll_ck = clk_get_sys(NULL, "dpll_abe_ck");
+
+	rc = clk_set_parent(abe_dpll_mux, sys_clkin2);
+	if (!rc)
+		rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+	dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
+	rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
+
+	return rc;
+}
-- 
1.7.9.5

[PATCHv4 14/33] CLK: omap: add dra7 clock init file

[Tero Kristo]

clk-7xx.c now contains the clock init functionality for dra7, including
DT clock registration and adding of static clkdev entries.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/Makefile  |    2 +-
 drivers/clk/omap/clk-7xx.c |   67 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 68 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/omap/clk-7xx.c

diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index 74385f2..b8dbfda 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1,2 +1,2 @@
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
-					   clk-44xx.o clk-54xx.o
+					   clk-44xx.o clk-54xx.o clk-7xx.o
diff --git a/drivers/clk/omap/clk-7xx.c b/drivers/clk/omap/clk-7xx.c
new file mode 100644
index 0000000..ddb39dd
--- /dev/null
+++ b/drivers/clk/omap/clk-7xx.c
@@ -0,0 +1,67 @@
+/*
+ * DRA7 Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo (t-kristo at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk/omap.h>
+
+#define DRA7_DPLL_ABE_DEFFREQ				361267200
+#define DRA7_DPLL_GMAC_DEFFREQ				1000000000
+
+
+static struct omap_dt_clk dra7xx_clks[] = {
+	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
+	DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"),
+	DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
+	DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
+};
+
+int __init dra7xx_clk_init(void)
+{
+	int rc;
+	struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+
+	dt_omap_clk_init();
+
+	omap_dt_clocks_register(dra7xx_clks, ARRAY_SIZE(dra7xx_clks));
+
+	omap2_clk_disable_autoidle_all();
+
+	abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux");
+	sys_clkin2 = clk_get_sys(NULL, "sys_clkin2");
+	dpll_ck = clk_get_sys(NULL, "dpll_abe_ck");
+
+	rc = clk_set_parent(abe_dpll_mux, sys_clkin2);
+	if (!rc)
+		rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+
+	dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
+	rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
+
+	return rc;
+}
-- 
1.7.9.5

[PATCHv4 15/33] CLK: OMAP: DPLL: add support for DT property ti,dpll-no-gate

[Tero Kristo]

AM335x has DPLL clocks that should never be attempted to be gated. Adding
ti,dpll-no-gate property for them handles this situation.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/dpll.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
index 66e82be..1d24feada 100644
--- a/drivers/clk/omap/dpll.c
+++ b/drivers/clk/omap/dpll.c
@@ -54,6 +54,13 @@ static const struct clk_ops dpll_x2_ck_ops = {
 	.recalc_rate	= &omap3_clkoutx2_recalc,
 };
 
+static const struct clk_ops dpll_no_gate_ck_ops = {
+	.recalc_rate	= &omap3_dpll_recalc,
+	.get_parent	= &omap2_init_dpll_parent,
+	.round_rate	= &omap2_dpll_round_rate,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+};
+
 struct clk *omap_clk_register_dpll(struct device *dev, const char *name,
 		const char **parent_names, int num_parents, unsigned long flags,
 		struct dpll_data *dpll_data, const char *clkdm_name,
@@ -288,6 +295,9 @@ __init void of_omap4_dpll_setup(struct device_node *node)
 		return;
 	}
 
+	if (of_property_read_bool(node, "ti,dpll-no-gate"))
+		ops = &dpll_no_gate_ck_ops;
+
 	of_omap_dpll_setup(node, ops);
 }
 EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
-- 
1.7.9.5

[PATCHv4 15/33] CLK: OMAP: DPLL: add support for DT property ti, dpll-no-gate

[Tero Kristo]

AM335x has DPLL clocks that should never be attempted to be gated. Adding
ti,dpll-no-gate property for them handles this situation.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/dpll.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
index 66e82be..1d24feada 100644
--- a/drivers/clk/omap/dpll.c
+++ b/drivers/clk/omap/dpll.c
@@ -54,6 +54,13 @@ static const struct clk_ops dpll_x2_ck_ops = {
 	.recalc_rate	= &omap3_clkoutx2_recalc,
 };
 
+static const struct clk_ops dpll_no_gate_ck_ops = {
+	.recalc_rate	= &omap3_dpll_recalc,
+	.get_parent	= &omap2_init_dpll_parent,
+	.round_rate	= &omap2_dpll_round_rate,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+};
+
 struct clk *omap_clk_register_dpll(struct device *dev, const char *name,
 		const char **parent_names, int num_parents, unsigned long flags,
 		struct dpll_data *dpll_data, const char *clkdm_name,
@@ -288,6 +295,9 @@ __init void of_omap4_dpll_setup(struct device_node *node)
 		return;
 	}
 
+	if (of_property_read_bool(node, "ti,dpll-no-gate"))
+		ops = &dpll_no_gate_ck_ops;
+
 	of_omap_dpll_setup(node, ops);
 }
 EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
-- 
1.7.9.5

Re: [PATCHv4 15/33] CLK: OMAP: DPLL: add support for DT property ti,dpll-no-gate

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> AM335x has DPLL clocks that should never be attempted to be gated. Adding
> ti,dpll-no-gate property for them handles this situation.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/dpll.c |   10 ++++++++++
>   1 file changed, 10 insertions(+)
>
> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
> index 66e82be..1d24feada 100644
> --- a/drivers/clk/omap/dpll.c
> +++ b/drivers/clk/omap/dpll.c
> @@ -54,6 +54,13 @@ static const struct clk_ops dpll_x2_ck_ops = {
>   	.recalc_rate	= &omap3_clkoutx2_recalc,
>   };
>
> +static const struct clk_ops dpll_no_gate_ck_ops = {
> +	.recalc_rate	= &omap3_dpll_recalc,
> +	.get_parent	= &omap2_init_dpll_parent,
> +	.round_rate	= &omap2_dpll_round_rate,
> +	.set_rate	= &omap3_noncore_dpll_set_rate,
> +};
> +
>   struct clk *omap_clk_register_dpll(struct device *dev, const char *name,
>   		const char **parent_names, int num_parents, unsigned long flags,
>   		struct dpll_data *dpll_data, const char *clkdm_name,
> @@ -288,6 +295,9 @@ __init void of_omap4_dpll_setup(struct device_node *node)
>   		return;
>   	}
>
> +	if (of_property_read_bool(node, "ti,dpll-no-gate"))
> +		ops = &dpll_no_gate_ck_ops;
> +
>   	of_omap_dpll_setup(node, ops);
>   }
>   EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>
squash this to dpll patch?

-- 
Regards,
Nishanth Menon

[PATCHv4 15/33] CLK: OMAP: DPLL: add support for DT property ti,dpll-no-gate

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> AM335x has DPLL clocks that should never be attempted to be gated. Adding
> ti,dpll-no-gate property for them handles this situation.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/dpll.c |   10 ++++++++++
>   1 file changed, 10 insertions(+)
>
> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
> index 66e82be..1d24feada 100644
> --- a/drivers/clk/omap/dpll.c
> +++ b/drivers/clk/omap/dpll.c
> @@ -54,6 +54,13 @@ static const struct clk_ops dpll_x2_ck_ops = {
>   	.recalc_rate	= &omap3_clkoutx2_recalc,
>   };
>
> +static const struct clk_ops dpll_no_gate_ck_ops = {
> +	.recalc_rate	= &omap3_dpll_recalc,
> +	.get_parent	= &omap2_init_dpll_parent,
> +	.round_rate	= &omap2_dpll_round_rate,
> +	.set_rate	= &omap3_noncore_dpll_set_rate,
> +};
> +
>   struct clk *omap_clk_register_dpll(struct device *dev, const char *name,
>   		const char **parent_names, int num_parents, unsigned long flags,
>   		struct dpll_data *dpll_data, const char *clkdm_name,
> @@ -288,6 +295,9 @@ __init void of_omap4_dpll_setup(struct device_node *node)
>   		return;
>   	}
>
> +	if (of_property_read_bool(node, "ti,dpll-no-gate"))
> +		ops = &dpll_no_gate_ck_ops;
> +
>   	of_omap_dpll_setup(node, ops);
>   }
>   EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>
squash this to dpll patch?

-- 
Regards,
Nishanth Menon

Re: [PATCHv4 15/33] CLK: OMAP: DPLL: add support for DT property ti,dpll-no-gate

[Tero Kristo]

On 07/30/2013 10:18 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> AM335x has DPLL clocks that should never be attempted to be gated. Adding
>> ti,dpll-no-gate property for them handles this situation.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/dpll.c |   10 ++++++++++
>>   1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
>> index 66e82be..1d24feada 100644
>> --- a/drivers/clk/omap/dpll.c
>> +++ b/drivers/clk/omap/dpll.c
>> @@ -54,6 +54,13 @@ static const struct clk_ops dpll_x2_ck_ops = {
>>       .recalc_rate    = &omap3_clkoutx2_recalc,
>>   };
>>
>> +static const struct clk_ops dpll_no_gate_ck_ops = {
>> +    .recalc_rate    = &omap3_dpll_recalc,
>> +    .get_parent    = &omap2_init_dpll_parent,
>> +    .round_rate    = &omap2_dpll_round_rate,
>> +    .set_rate    = &omap3_noncore_dpll_set_rate,
>> +};
>> +
>>   struct clk *omap_clk_register_dpll(struct device *dev, const char
>> *name,
>>           const char **parent_names, int num_parents, unsigned long
>> flags,
>>           struct dpll_data *dpll_data, const char *clkdm_name,
>> @@ -288,6 +295,9 @@ __init void of_omap4_dpll_setup(struct device_node
>> *node)
>>           return;
>>       }
>>
>> +    if (of_property_read_bool(node, "ti,dpll-no-gate"))
>> +        ops = &dpll_no_gate_ck_ops;
>> +
>>       of_omap_dpll_setup(node, ops);
>>   }
>>   EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>>
> squash this to dpll patch?
>

Can do it. Was kept separate just to avoid confusion with previous rev 
of the code.

-Tero

[PATCHv4 15/33] CLK: OMAP: DPLL: add support for DT property ti,dpll-no-gate

[Tero Kristo]

On 07/30/2013 10:18 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> AM335x has DPLL clocks that should never be attempted to be gated. Adding
>> ti,dpll-no-gate property for them handles this situation.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/dpll.c |   10 ++++++++++
>>   1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
>> index 66e82be..1d24feada 100644
>> --- a/drivers/clk/omap/dpll.c
>> +++ b/drivers/clk/omap/dpll.c
>> @@ -54,6 +54,13 @@ static const struct clk_ops dpll_x2_ck_ops = {
>>       .recalc_rate    = &omap3_clkoutx2_recalc,
>>   };
>>
>> +static const struct clk_ops dpll_no_gate_ck_ops = {
>> +    .recalc_rate    = &omap3_dpll_recalc,
>> +    .get_parent    = &omap2_init_dpll_parent,
>> +    .round_rate    = &omap2_dpll_round_rate,
>> +    .set_rate    = &omap3_noncore_dpll_set_rate,
>> +};
>> +
>>   struct clk *omap_clk_register_dpll(struct device *dev, const char
>> *name,
>>           const char **parent_names, int num_parents, unsigned long
>> flags,
>>           struct dpll_data *dpll_data, const char *clkdm_name,
>> @@ -288,6 +295,9 @@ __init void of_omap4_dpll_setup(struct device_node
>> *node)
>>           return;
>>       }
>>
>> +    if (of_property_read_bool(node, "ti,dpll-no-gate"))
>> +        ops = &dpll_no_gate_ck_ops;
>> +
>>       of_omap_dpll_setup(node, ops);
>>   }
>>   EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>>
> squash this to dpll patch?
>

Can do it. Was kept separate just to avoid confusion with previous rev 
of the code.

-Tero

[PATCHv4 16/33] CLK: OMAP: DPLL: do not of_iomap NULL autoidle register

[Tero Kristo]

AM33xx series SoCs do not have autoidle support, and for these the
autoidle register is marked as NULL. Check against a NULL pointer and
do not attempt to of_iomap in this case, as this just creates a bogus
pointer and causes a kernel crash during boot.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/dpll.c |   10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
index 1d24feada..d8a958a 100644
--- a/drivers/clk/omap/dpll.c
+++ b/drivers/clk/omap/dpll.c
@@ -162,6 +162,7 @@ static void __init of_omap_dpll_setup(struct device_node *node,
 	u32 max_multiplier = 2047;
 	u32 max_divider = 128;
 	u32 min_divider = 1;
+	u32 val;
 	int i;
 
 	dd = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
@@ -210,7 +211,14 @@ static void __init of_omap_dpll_setup(struct device_node *node,
 
 	dd->control_reg = of_iomap(node, 0);
 	dd->idlest_reg = of_iomap(node, 1);
-	dd->autoidle_reg = of_iomap(node, 2);
+	/*
+	 * AM33xx DPLLs have no autoidle support, and the autoidle reg
+	 * for these is NULL. Do not attempt to of_iomap in this case,
+	 * as this just creates a bogus pointer and crashes the kernel.
+	 */
+	of_property_read_u32_index(node, "reg", 2 * 2, &val);
+	if (val)
+		dd->autoidle_reg = of_iomap(node, 2);
 	dd->mult_div1_reg = of_iomap(node, 3);
 
 	dd->idlest_mask = idlest_mask;
-- 
1.7.9.5

[PATCHv4 16/33] CLK: OMAP: DPLL: do not of_iomap NULL autoidle register

[Tero Kristo]

AM33xx series SoCs do not have autoidle support, and for these the
autoidle register is marked as NULL. Check against a NULL pointer and
do not attempt to of_iomap in this case, as this just creates a bogus
pointer and causes a kernel crash during boot.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/dpll.c |   10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
index 1d24feada..d8a958a 100644
--- a/drivers/clk/omap/dpll.c
+++ b/drivers/clk/omap/dpll.c
@@ -162,6 +162,7 @@ static void __init of_omap_dpll_setup(struct device_node *node,
 	u32 max_multiplier = 2047;
 	u32 max_divider = 128;
 	u32 min_divider = 1;
+	u32 val;
 	int i;
 
 	dd = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
@@ -210,7 +211,14 @@ static void __init of_omap_dpll_setup(struct device_node *node,
 
 	dd->control_reg = of_iomap(node, 0);
 	dd->idlest_reg = of_iomap(node, 1);
-	dd->autoidle_reg = of_iomap(node, 2);
+	/*
+	 * AM33xx DPLLs have no autoidle support, and the autoidle reg
+	 * for these is NULL. Do not attempt to of_iomap in this case,
+	 * as this just creates a bogus pointer and crashes the kernel.
+	 */
+	of_property_read_u32_index(node, "reg", 2 * 2, &val);
+	if (val)
+		dd->autoidle_reg = of_iomap(node, 2);
 	dd->mult_div1_reg = of_iomap(node, 3);
 
 	dd->idlest_mask = idlest_mask;
-- 
1.7.9.5

Re: [PATCHv4 16/33] CLK: OMAP: DPLL: do not of_iomap NULL autoidle register

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> AM33xx series SoCs do not have autoidle support, and for these the
> autoidle register is marked as NULL. Check against a NULL pointer and
> do not attempt to of_iomap in this case, as this just creates a bogus
> pointer and causes a kernel crash during boot.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/dpll.c |   10 +++++++++-
>   1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
> index 1d24feada..d8a958a 100644
> --- a/drivers/clk/omap/dpll.c
> +++ b/drivers/clk/omap/dpll.c
> @@ -162,6 +162,7 @@ static void __init of_omap_dpll_setup(struct device_node *node,
>   	u32 max_multiplier = 2047;
>   	u32 max_divider = 128;
>   	u32 min_divider = 1;
> +	u32 val;
>   	int i;
>
>   	dd = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
> @@ -210,7 +211,14 @@ static void __init of_omap_dpll_setup(struct device_node *node,
>
>   	dd->control_reg = of_iomap(node, 0);
>   	dd->idlest_reg = of_iomap(node, 1);
> -	dd->autoidle_reg = of_iomap(node, 2);
> +	/*
> +	 * AM33xx DPLLs have no autoidle support, and the autoidle reg
> +	 * for these is NULL. Do not attempt to of_iomap in this case,
> +	 * as this just creates a bogus pointer and crashes the kernel.
> +	 */
> +	of_property_read_u32_index(node, "reg", 2 * 2, &val);
> +	if (val)
> +		dd->autoidle_reg = of_iomap(node, 2);
should we not do that for all the parameters?
OR:
move this as index 3 which is optional and is not defined for am33xx?

>   	dd->mult_div1_reg = of_iomap(node, 3);

>
>   	dd->idlest_mask = idlest_mask;
>
we could probably squash this in original dpll.c as a result?

-- 
Regards,
Nishanth Menon

[PATCHv4 16/33] CLK: OMAP: DPLL: do not of_iomap NULL autoidle register

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> AM33xx series SoCs do not have autoidle support, and for these the
> autoidle register is marked as NULL. Check against a NULL pointer and
> do not attempt to of_iomap in this case, as this just creates a bogus
> pointer and causes a kernel crash during boot.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/dpll.c |   10 +++++++++-
>   1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
> index 1d24feada..d8a958a 100644
> --- a/drivers/clk/omap/dpll.c
> +++ b/drivers/clk/omap/dpll.c
> @@ -162,6 +162,7 @@ static void __init of_omap_dpll_setup(struct device_node *node,
>   	u32 max_multiplier = 2047;
>   	u32 max_divider = 128;
>   	u32 min_divider = 1;
> +	u32 val;
>   	int i;
>
>   	dd = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
> @@ -210,7 +211,14 @@ static void __init of_omap_dpll_setup(struct device_node *node,
>
>   	dd->control_reg = of_iomap(node, 0);
>   	dd->idlest_reg = of_iomap(node, 1);
> -	dd->autoidle_reg = of_iomap(node, 2);
> +	/*
> +	 * AM33xx DPLLs have no autoidle support, and the autoidle reg
> +	 * for these is NULL. Do not attempt to of_iomap in this case,
> +	 * as this just creates a bogus pointer and crashes the kernel.
> +	 */
> +	of_property_read_u32_index(node, "reg", 2 * 2, &val);
> +	if (val)
> +		dd->autoidle_reg = of_iomap(node, 2);
should we not do that for all the parameters?
OR:
move this as index 3 which is optional and is not defined for am33xx?

>   	dd->mult_div1_reg = of_iomap(node, 3);

>
>   	dd->idlest_mask = idlest_mask;
>
we could probably squash this in original dpll.c as a result?

-- 
Regards,
Nishanth Menon

Re: [PATCHv4 16/33] CLK: OMAP: DPLL: do not of_iomap NULL autoidle register

[Tero Kristo]

On 07/30/2013 10:49 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> AM33xx series SoCs do not have autoidle support, and for these the
>> autoidle register is marked as NULL. Check against a NULL pointer and
>> do not attempt to of_iomap in this case, as this just creates a bogus
>> pointer and causes a kernel crash during boot.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/dpll.c |   10 +++++++++-
>>   1 file changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
>> index 1d24feada..d8a958a 100644
>> --- a/drivers/clk/omap/dpll.c
>> +++ b/drivers/clk/omap/dpll.c
>> @@ -162,6 +162,7 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>>       u32 max_multiplier = 2047;
>>       u32 max_divider = 128;
>>       u32 min_divider = 1;
>> +    u32 val;
>>       int i;
>>
>>       dd = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
>> @@ -210,7 +211,14 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>>
>>       dd->control_reg = of_iomap(node, 0);
>>       dd->idlest_reg = of_iomap(node, 1);
>> -    dd->autoidle_reg = of_iomap(node, 2);
>> +    /*
>> +     * AM33xx DPLLs have no autoidle support, and the autoidle reg
>> +     * for these is NULL. Do not attempt to of_iomap in this case,
>> +     * as this just creates a bogus pointer and crashes the kernel.
>> +     */
>> +    of_property_read_u32_index(node, "reg", 2 * 2, &val);
>> +    if (val)
>> +        dd->autoidle_reg = of_iomap(node, 2);
> should we not do that for all the parameters?

Maybe do the check for all.

> OR:
> move this as index 3 which is optional and is not defined for am33xx?
>
>>       dd->mult_div1_reg = of_iomap(node, 3);
>
>>
>>       dd->idlest_mask = idlest_mask;
>>
> we could probably squash this in original dpll.c as a result?
>

Yea, can do that also.

[PATCHv4 16/33] CLK: OMAP: DPLL: do not of_iomap NULL autoidle register

[Tero Kristo]

On 07/30/2013 10:49 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> AM33xx series SoCs do not have autoidle support, and for these the
>> autoidle register is marked as NULL. Check against a NULL pointer and
>> do not attempt to of_iomap in this case, as this just creates a bogus
>> pointer and causes a kernel crash during boot.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/dpll.c |   10 +++++++++-
>>   1 file changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
>> index 1d24feada..d8a958a 100644
>> --- a/drivers/clk/omap/dpll.c
>> +++ b/drivers/clk/omap/dpll.c
>> @@ -162,6 +162,7 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>>       u32 max_multiplier = 2047;
>>       u32 max_divider = 128;
>>       u32 min_divider = 1;
>> +    u32 val;
>>       int i;
>>
>>       dd = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
>> @@ -210,7 +211,14 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>>
>>       dd->control_reg = of_iomap(node, 0);
>>       dd->idlest_reg = of_iomap(node, 1);
>> -    dd->autoidle_reg = of_iomap(node, 2);
>> +    /*
>> +     * AM33xx DPLLs have no autoidle support, and the autoidle reg
>> +     * for these is NULL. Do not attempt to of_iomap in this case,
>> +     * as this just creates a bogus pointer and crashes the kernel.
>> +     */
>> +    of_property_read_u32_index(node, "reg", 2 * 2, &val);
>> +    if (val)
>> +        dd->autoidle_reg = of_iomap(node, 2);
> should we not do that for all the parameters?

Maybe do the check for all.

> OR:
> move this as index 3 which is optional and is not defined for am33xx?
>
>>       dd->mult_div1_reg = of_iomap(node, 3);
>
>>
>>       dd->idlest_mask = idlest_mask;
>>
> we could probably squash this in original dpll.c as a result?
>

Yea, can do that also.

[PATCHv4 17/33] CLK: DT: add support for set-rate-parent flag

[Tero Kristo]

Adding set-rate-parent to clock node now allows a node to forward
clk_set_rate request to its parent clock.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/clk-divider.c      |    6 +++++-
 drivers/clk/clk-fixed-factor.c |    6 +++++-
 drivers/clk/clk-gate.c         |    8 ++++++--
 drivers/clk/clk-mux.c          |    6 +++++-
 4 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index ff24ec2..01d967f 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -388,6 +388,7 @@ void of_divider_clk_setup(struct device_node *node)
 	u32 mask = 0;
 	u32 shift = 0;
 	struct clk_div_table *table;
+	u32 flags = 0;
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
@@ -418,12 +419,15 @@ void of_divider_clk_setup(struct device_node *node)
 	if (of_property_read_bool(node, "hiword-mask"))
 		clk_divider_flags |= CLK_DIVIDER_HIWORD_MASK;
 
+	if (of_property_read_bool(node, "set-rate-parent"))
+		flags |= CLK_SET_RATE_PARENT;
+
 	table = of_clk_get_div_table(node);
 	if (IS_ERR(table))
 		return;
 
 	clk = _register_divider(NULL, clk_name,
-			parent_name, 0,
+			parent_name, flags,
 			reg, (u8) shift, mask,
 			clk_divider_flags, table,
 			NULL);
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 9ff7d51..30aa121 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -107,6 +107,7 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
 	const char *clk_name = node->name;
 	const char *parent_name;
 	u32 div, mult;
+	u32 flags = 0;
 
 	if (of_property_read_u32(node, "clock-div", &div)) {
 		pr_err("%s Fixed factor clock <%s> must have a clock-div property\n",
@@ -123,7 +124,10 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
 	of_property_read_string(node, "clock-output-names", &clk_name);
 	parent_name = of_clk_get_parent_name(node, 0);
 
-	clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
+	if (of_property_read_bool(node, "set-rate-parent"))
+		flags |= CLK_SET_RATE_PARENT;
+
+	clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
 					mult, div);
 	if (!IS_ERR(clk))
 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index cd595ec..0be25b9 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -176,6 +176,7 @@ void of_gate_clk_setup(struct device_node *node)
 	const char *parent_name;
 	u8 clk_gate_flags = 0;
 	u32 bit_idx = 0;
+	u32 flags = 0;
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
@@ -195,8 +196,11 @@ void of_gate_clk_setup(struct device_node *node)
 	if (of_property_read_bool(node, "hiword-mask"))
 		clk_gate_flags |= CLK_GATE_HIWORD_MASK;
 
-	clk = clk_register_gate(NULL, clk_name, parent_name, 0, reg, (u8) bit_idx,
-			clk_gate_flags, NULL);
+	if (of_property_read_bool(node, "set-rate-parent"))
+		flags |= CLK_SET_RATE_PARENT;
+
+	clk = clk_register_gate(NULL, clk_name, parent_name, flags, reg,
+			(u8) bit_idx, clk_gate_flags, NULL);
 
 	if (!IS_ERR(clk))
 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 4751bce..890ddbf 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -184,6 +184,7 @@ void of_mux_clk_setup(struct device_node *node)
 	u8 clk_mux_flags = 0;
 	u32 mask = 0;
 	u32 shift = 0;
+	u32 flags = 0;
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
@@ -219,8 +220,11 @@ void of_mux_clk_setup(struct device_node *node)
 	if (of_property_read_bool(node, "hiword-mask"))
 		clk_mux_flags |= CLK_MUX_HIWORD_MASK;
 
+	if (of_property_read_bool(node, "set-rate-parent"))
+		flags |= CLK_SET_RATE_PARENT;
+
 	clk = clk_register_mux_table(NULL, clk_name, parent_names, num_parents,
-			0, reg, (u8) shift, mask, clk_mux_flags,
+			flags, reg, (u8) shift, mask, clk_mux_flags,
 			NULL, NULL);
 
 	if (!IS_ERR(clk))
-- 
1.7.9.5

[PATCHv4 17/33] CLK: DT: add support for set-rate-parent flag

[Tero Kristo]

Adding set-rate-parent to clock node now allows a node to forward
clk_set_rate request to its parent clock.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/clk-divider.c      |    6 +++++-
 drivers/clk/clk-fixed-factor.c |    6 +++++-
 drivers/clk/clk-gate.c         |    8 ++++++--
 drivers/clk/clk-mux.c          |    6 +++++-
 4 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index ff24ec2..01d967f 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -388,6 +388,7 @@ void of_divider_clk_setup(struct device_node *node)
 	u32 mask = 0;
 	u32 shift = 0;
 	struct clk_div_table *table;
+	u32 flags = 0;
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
@@ -418,12 +419,15 @@ void of_divider_clk_setup(struct device_node *node)
 	if (of_property_read_bool(node, "hiword-mask"))
 		clk_divider_flags |= CLK_DIVIDER_HIWORD_MASK;
 
+	if (of_property_read_bool(node, "set-rate-parent"))
+		flags |= CLK_SET_RATE_PARENT;
+
 	table = of_clk_get_div_table(node);
 	if (IS_ERR(table))
 		return;
 
 	clk = _register_divider(NULL, clk_name,
-			parent_name, 0,
+			parent_name, flags,
 			reg, (u8) shift, mask,
 			clk_divider_flags, table,
 			NULL);
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 9ff7d51..30aa121 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -107,6 +107,7 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
 	const char *clk_name = node->name;
 	const char *parent_name;
 	u32 div, mult;
+	u32 flags = 0;
 
 	if (of_property_read_u32(node, "clock-div", &div)) {
 		pr_err("%s Fixed factor clock <%s> must have a clock-div property\n",
@@ -123,7 +124,10 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
 	of_property_read_string(node, "clock-output-names", &clk_name);
 	parent_name = of_clk_get_parent_name(node, 0);
 
-	clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
+	if (of_property_read_bool(node, "set-rate-parent"))
+		flags |= CLK_SET_RATE_PARENT;
+
+	clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
 					mult, div);
 	if (!IS_ERR(clk))
 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index cd595ec..0be25b9 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -176,6 +176,7 @@ void of_gate_clk_setup(struct device_node *node)
 	const char *parent_name;
 	u8 clk_gate_flags = 0;
 	u32 bit_idx = 0;
+	u32 flags = 0;
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
@@ -195,8 +196,11 @@ void of_gate_clk_setup(struct device_node *node)
 	if (of_property_read_bool(node, "hiword-mask"))
 		clk_gate_flags |= CLK_GATE_HIWORD_MASK;
 
-	clk = clk_register_gate(NULL, clk_name, parent_name, 0, reg, (u8) bit_idx,
-			clk_gate_flags, NULL);
+	if (of_property_read_bool(node, "set-rate-parent"))
+		flags |= CLK_SET_RATE_PARENT;
+
+	clk = clk_register_gate(NULL, clk_name, parent_name, flags, reg,
+			(u8) bit_idx, clk_gate_flags, NULL);
 
 	if (!IS_ERR(clk))
 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 4751bce..890ddbf 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -184,6 +184,7 @@ void of_mux_clk_setup(struct device_node *node)
 	u8 clk_mux_flags = 0;
 	u32 mask = 0;
 	u32 shift = 0;
+	u32 flags = 0;
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
@@ -219,8 +220,11 @@ void of_mux_clk_setup(struct device_node *node)
 	if (of_property_read_bool(node, "hiword-mask"))
 		clk_mux_flags |= CLK_MUX_HIWORD_MASK;
 
+	if (of_property_read_bool(node, "set-rate-parent"))
+		flags |= CLK_SET_RATE_PARENT;
+
 	clk = clk_register_mux_table(NULL, clk_name, parent_names, num_parents,
-			0, reg, (u8) shift, mask, clk_mux_flags,
+			flags, reg, (u8) shift, mask, clk_mux_flags,
 			NULL, NULL);
 
 	if (!IS_ERR(clk))
-- 
1.7.9.5

Re: [PATCHv4 17/33] CLK: DT: add support for set-rate-parent flag

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> Adding set-rate-parent to clock node now allows a node to forward
> clk_set_rate request to its parent clock.

Apologies about previous comment of set-parent missing, the sequence of 
patches messed with me :(. had expected generic clk changes at the start 
of the series followed by the rest.

>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/clk-divider.c      |    6 +++++-
>   drivers/clk/clk-fixed-factor.c |    6 +++++-
>   drivers/clk/clk-gate.c         |    8 ++++++--
>   drivers/clk/clk-mux.c          |    6 +++++-
>   4 files changed, 21 insertions(+), 5 deletions(-)

Documentation/devicetree/bindings/clock/ needs update as well.
[...]

-- 
Regards,
Nishanth Menon

[PATCHv4 17/33] CLK: DT: add support for set-rate-parent flag

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> Adding set-rate-parent to clock node now allows a node to forward
> clk_set_rate request to its parent clock.

Apologies about previous comment of set-parent missing, the sequence of 
patches messed with me :(. had expected generic clk changes at the start 
of the series followed by the rest.

>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/clk-divider.c      |    6 +++++-
>   drivers/clk/clk-fixed-factor.c |    6 +++++-
>   drivers/clk/clk-gate.c         |    8 ++++++--
>   drivers/clk/clk-mux.c          |    6 +++++-
>   4 files changed, 21 insertions(+), 5 deletions(-)

Documentation/devicetree/bindings/clock/ needs update as well.
[...]

-- 
Regards,
Nishanth Menon

[PATCHv4 18/33] ARM: dts: am33xx clock data

[Tero Kristo]

This patch creates a unique node for each clock in the AM33xx power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/am33xx-clocks.dtsi |  663 ++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/am33xx.dtsi        |    7 +
 2 files changed, 670 insertions(+)
 create mode 100644 arch/arm/boot/dts/am33xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
new file mode 100644
index 0000000..1b19443
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -0,0 +1,663 @@
+/*
+ * Device Tree Source for AM33xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clk_32768_ck: clk_32768_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+clk_rc32k_ck: clk_rc32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_24000000_ck: virt_24000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <24000000>;
+};
+
+virt_25000000_ck: virt_25000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <25000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+sys_clkin_ck: sys_clkin_ck@44e10040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+	bit-shift = <22>;
+	reg = <0x44e10040 0x4>;
+	bit-mask = <0x3>;
+};
+
+tclkin_ck: tclkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+dpll_core_ck: dpll_core_ck@44e00490 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x0 0x4>, <0x44e00468 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+	ti,dpll-core;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_core_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_core_m4_ck: dpll_core_m4_ck@44e00480 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	reg = <0x44e00480 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_core_m5_ck: dpll_core_m5_ck@44e00484 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	reg = <0x44e00484 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_core_m6_ck: dpll_core_m6_ck@44e004d8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	reg = <0x44e004d8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_mpu_ck: dpll_mpu_ck@44e00488 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e00488 0x4>, <0x44e00420 0x4>, <0x0 0x4>, <0x44e0042c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck@44e004a8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	reg = <0x44e004a8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_ddr_ck: dpll_ddr_ck@44e00494 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e00494 0x4>, <0x44e00434 0x4>, <0x0 0x4>, <0x44e00440 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+	ti,dpll-no-gate;
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck@44e004a0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_ddr_ck>;
+	reg = <0x44e004a0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_ddr_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_disp_ck: dpll_disp_ck@44e00498 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e00498 0x4>, <0x44e00448 0x4>, <0x0 0x4>, <0x44e00454 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+	ti,dpll-no-gate;
+};
+
+dpll_disp_m2_ck: dpll_disp_m2_ck@44e004a4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_disp_ck>;
+	reg = <0x44e004a4 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	set-rate-parent;
+};
+
+dpll_per_ck: dpll_per_ck@44e0048c {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e0048c 0x4>, <0x44e00470 0x4>, <0x0 0x4>, <0x44e0049c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+	ti,dpll-no-gate;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck@44e004ac {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_ck>;
+	reg = <0x44e004ac 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+adc_tsc_fck: adc_tsc_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+cefuse_fck: cefuse_fck@44e00a20 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_clkin_ck>;
+	bit-shift = <1>;
+	reg = <0x44e00a20 0x4>;
+};
+
+clk_24mhz: clk_24mhz {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+clkdiv32k_ck: clkdiv32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&clk_24mhz>;
+	clock-mult = <1>;
+	clock-div = <732>;
+};
+
+clkdiv32k_ick: clkdiv32k_ick@44e0014c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ck>;
+	reg = <0x44e0014c 0x4>;
+	bit-shift = <1>;
+};
+
+dcan0_fck: dcan0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dcan1_fck: dcan1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3_gclk: l3_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+pruss_ocp_gclk: pruss_ocp_gclk@44e00530 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
+	reg = <0x44e00530 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcasp0_fck: mcasp0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mcasp1_fck: mcasp1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mmu_fck: mmu_fck@44e00914 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_core_m4_ck>;
+	bit-shift = <1>;
+	reg = <0x44e00914 0x4>;
+};
+
+smartreflex0_fck: smartreflex0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+smartreflex1_fck: smartreflex1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sha0_fck: sha0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+aes0_fck: aes0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+timer1_fck: timer1_fck@44e00528 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+	reg = <0x44e00528 0x4>;
+	bit-mask = <0x7>;
+};
+
+timer2_fck: timer2_fck@44e00508 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00508 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer3_fck: timer3_fck@44e0050c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e0050c 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer4_fck: timer4_fck@44e00510 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00510 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer5_fck: timer5_fck@44e00518 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00518 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer6_fck: timer6_fck@44e0051c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e0051c 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer7_fck: timer7_fck@44e00504 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00504 0x4>;
+	bit-mask = <0x3>;
+};
+
+usbotg_fck: usbotg_fck@44e0047c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_ck>;
+	bit-shift = <8>;
+	reg = <0x44e0047c 0x4>;
+};
+
+dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+ieee5000_fck: ieee5000_fck@44e000e4 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_core_m4_div2_ck>;
+	bit-shift = <1>;
+	reg = <0x44e000e4 0x4>;
+};
+
+wdt1_fck: wdt1_fck@44e00538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00538 0x4>;
+	bit-mask = <0x3>;
+};
+
+l4_rtc_gclk: l4_rtc_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+l4hs_gclk: l4hs_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3s_gclk: l3s_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_div2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l4fw_gclk: l4fw_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_div2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l4ls_gclk: l4ls_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_div2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sysclk_div_ck: sysclk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m5_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@44e00520 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
+	reg = <0x44e00520 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@44e0053c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e0053c 0x4>;
+	bit-mask = <0x3>;
+};
+
+gpio0_dbclk: gpio0_dbclk@44e00408 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpio0_dbclk_mux_ck>;
+	bit-shift = <18>;
+	reg = <0x44e00408 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk@44e000ac {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ick>;
+	bit-shift = <18>;
+	reg = <0x44e000ac 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk@44e000b0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ick>;
+	bit-shift = <18>;
+	reg = <0x44e000b0 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk@44e000b4 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ick>;
+	bit-shift = <18>;
+	reg = <0x44e000b4 0x4>;
+};
+
+lcd_gclk: lcd_gclk@44e00534 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+	reg = <0x44e00534 0x4>;
+	bit-mask = <0x3>;
+	set-rate-parent;
+};
+
+mmc_clk: mmc_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@44e0052c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+	bit-shift = <1>;
+	reg = <0x44e0052c 0x4>;
+	bit-mask = <0x1>;
+};
+
+gfx_fck_div_ck: gfx_fck_div_ck@44e0052c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&gfx_fclk_clksel_ck>;
+	reg = <0x44e0052c 0x4>;
+	table = < 1 0 >, < 2 1 >;
+	bit-mask = <0x1>;
+};
+
+sysclkout_pre_ck: sysclkout_pre_ck@44e00700 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+	reg = <0x44e00700 0x4>;
+	bit-mask = <0x7>;
+};
+
+clkout2_div_ck: clkout2_div_ck@44e00700 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sysclkout_pre_ck>;
+	bit-shift = <3>;
+	reg = <0x44e00700 0x4>;
+	table = < 1 0 >, < 2 1 >, < 3 2 >, < 4 3 >, < 5 4 >, < 6 5 >, < 7 6 >, < 8 7 >;
+	bit-mask = <0x7>;
+};
+
+dbg_sysclk_ck: dbg_sysclk_ck@44e00414 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_clkin_ck>;
+	bit-shift = <19>;
+	reg = <0x44e00414 0x4>;
+};
+
+dbg_clka_ck: dbg_clka_ck@44e00414 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_core_m4_ck>;
+	bit-shift = <30>;
+	reg = <0x44e00414 0x4>;
+};
+
+stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@44e00414 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+	bit-shift = <22>;
+	reg = <0x44e00414 0x4>;
+	bit-mask = <0x3>;
+};
+
+trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@44e00414 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+	bit-shift = <20>;
+	reg = <0x44e00414 0x4>;
+	bit-mask = <0x3>;
+};
+
+stm_clk_div_ck: stm_clk_div_ck@44e00414 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&stm_pmd_clock_mux_ck>;
+	bit-shift = <27>;
+	reg = <0x44e00414 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+trace_clk_div_ck: trace_clk_div_ck@44e00414 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&trace_pmd_clk_mux_ck>;
+	bit-shift = <24>;
+	reg = <0x44e00414 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+clkout2_ck: clkout2_ck@44e00700 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkout2_div_ck>;
+	bit-shift = <7>;
+	reg = <0x44e00700 0x4>;
+};
+
+ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m2_ck>;
+	bit-shift = <0>;
+	reg = <0x44e10664 0x4>;
+};
+
+ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m2_ck>;
+	bit-shift = <1>;
+	reg = <0x44e10664 0x4>;
+};
+
+ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m2_ck>;
+	bit-shift = <2>;
+	reg = <0x44e10664 0x4>;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 38b446b..4701e3c 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -531,4 +531,11 @@
 			status = "disabled";
 		};
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "am33xx-clocks.dtsi"
+	};
 };
-- 
1.7.9.5

[PATCHv4 18/33] ARM: dts: am33xx clock data

[Tero Kristo]

This patch creates a unique node for each clock in the AM33xx power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/am33xx-clocks.dtsi |  663 ++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/am33xx.dtsi        |    7 +
 2 files changed, 670 insertions(+)
 create mode 100644 arch/arm/boot/dts/am33xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
new file mode 100644
index 0000000..1b19443
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -0,0 +1,663 @@
+/*
+ * Device Tree Source for AM33xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clk_32768_ck: clk_32768_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+clk_rc32k_ck: clk_rc32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_24000000_ck: virt_24000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <24000000>;
+};
+
+virt_25000000_ck: virt_25000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <25000000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+sys_clkin_ck: sys_clkin_ck at 44e10040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+	bit-shift = <22>;
+	reg = <0x44e10040 0x4>;
+	bit-mask = <0x3>;
+};
+
+tclkin_ck: tclkin_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+dpll_core_ck: dpll_core_ck at 44e00490 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x0 0x4>, <0x44e00468 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+	ti,dpll-core;
+};
+
+dpll_core_x2_ck: dpll_core_x2_ck {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&dpll_core_ck>;
+	ti,dpll-clk-x2;
+};
+
+dpll_core_m4_ck: dpll_core_m4_ck at 44e00480 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	reg = <0x44e00480 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_core_m5_ck: dpll_core_m5_ck at 44e00484 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	reg = <0x44e00484 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_core_m6_ck: dpll_core_m6_ck at 44e004d8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	reg = <0x44e004d8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_mpu_ck: dpll_mpu_ck at 44e00488 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e00488 0x4>, <0x44e00420 0x4>, <0x0 0x4>, <0x44e0042c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+};
+
+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 44e004a8 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_mpu_ck>;
+	reg = <0x44e004a8 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_ddr_ck: dpll_ddr_ck at 44e00494 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e00494 0x4>, <0x44e00434 0x4>, <0x0 0x4>, <0x44e00440 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+	ti,dpll-no-gate;
+};
+
+dpll_ddr_m2_ck: dpll_ddr_m2_ck at 44e004a0 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_ddr_ck>;
+	reg = <0x44e004a0 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_ddr_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+dpll_disp_ck: dpll_disp_ck at 44e00498 {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e00498 0x4>, <0x44e00448 0x4>, <0x0 0x4>, <0x44e00454 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+	ti,dpll-no-gate;
+};
+
+dpll_disp_m2_ck: dpll_disp_m2_ck at 44e004a4 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_disp_ck>;
+	reg = <0x44e004a4 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+	set-rate-parent;
+};
+
+dpll_per_ck: dpll_per_ck at 44e0048c {
+	#clock-cells = <0>;
+	compatible = "ti,omap4-dpll-clock";
+	clocks = <&sys_clkin_ck>;
+	reg = <0x44e0048c 0x4>, <0x44e00470 0x4>, <0x0 0x4>, <0x44e0049c 0x4>;
+	ti,clk-ref = <&sys_clkin_ck>;
+	ti,clk-bypass = <&sys_clkin_ck>;
+	ti,dpll-no-gate;
+};
+
+dpll_per_m2_ck: dpll_per_m2_ck at 44e004ac {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll_per_ck>;
+	reg = <0x44e004ac 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+adc_tsc_fck: adc_tsc_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+cefuse_fck: cefuse_fck at 44e00a20 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_clkin_ck>;
+	bit-shift = <1>;
+	reg = <0x44e00a20 0x4>;
+};
+
+clk_24mhz: clk_24mhz {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+clkdiv32k_ck: clkdiv32k_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&clk_24mhz>;
+	clock-mult = <1>;
+	clock-div = <732>;
+};
+
+clkdiv32k_ick: clkdiv32k_ick at 44e0014c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ck>;
+	reg = <0x44e0014c 0x4>;
+	bit-shift = <1>;
+};
+
+dcan0_fck: dcan0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dcan1_fck: dcan1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3_gclk: l3_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+pruss_ocp_gclk: pruss_ocp_gclk at 44e00530 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
+	reg = <0x44e00530 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcasp0_fck: mcasp0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mcasp1_fck: mcasp1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mmu_fck: mmu_fck at 44e00914 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_core_m4_ck>;
+	bit-shift = <1>;
+	reg = <0x44e00914 0x4>;
+};
+
+smartreflex0_fck: smartreflex0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+smartreflex1_fck: smartreflex1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sha0_fck: sha0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+aes0_fck: aes0_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_clkin_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+timer1_fck: timer1_fck at 44e00528 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+	reg = <0x44e00528 0x4>;
+	bit-mask = <0x7>;
+};
+
+timer2_fck: timer2_fck at 44e00508 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00508 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer3_fck: timer3_fck at 44e0050c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e0050c 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer4_fck: timer4_fck at 44e00510 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00510 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer5_fck: timer5_fck at 44e00518 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00518 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer6_fck: timer6_fck at 44e0051c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e0051c 0x4>;
+	bit-mask = <0x3>;
+};
+
+timer7_fck: timer7_fck at 44e00504 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00504 0x4>;
+	bit-mask = <0x3>;
+};
+
+usbotg_fck: usbotg_fck at 44e0047c {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_ck>;
+	bit-shift = <8>;
+	reg = <0x44e0047c 0x4>;
+};
+
+dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+ieee5000_fck: ieee5000_fck at 44e000e4 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_core_m4_div2_ck>;
+	bit-shift = <1>;
+	reg = <0x44e000e4 0x4>;
+};
+
+wdt1_fck: wdt1_fck at 44e00538 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e00538 0x4>;
+	bit-mask = <0x3>;
+};
+
+l4_rtc_gclk: l4_rtc_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+l4hs_gclk: l4hs_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3s_gclk: l3s_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_div2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l4fw_gclk: l4fw_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_div2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l4ls_gclk: l4ls_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_div2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sysclk_div_ck: sysclk_div_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m4_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_core_m5_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+cpsw_cpts_rft_clk: cpsw_cpts_rft_clk at 44e00520 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
+	reg = <0x44e00520 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck at 44e0053c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+	reg = <0x44e0053c 0x4>;
+	bit-mask = <0x3>;
+};
+
+gpio0_dbclk: gpio0_dbclk at 44e00408 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpio0_dbclk_mux_ck>;
+	bit-shift = <18>;
+	reg = <0x44e00408 0x4>;
+};
+
+gpio1_dbclk: gpio1_dbclk at 44e000ac {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ick>;
+	bit-shift = <18>;
+	reg = <0x44e000ac 0x4>;
+};
+
+gpio2_dbclk: gpio2_dbclk at 44e000b0 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ick>;
+	bit-shift = <18>;
+	reg = <0x44e000b0 0x4>;
+};
+
+gpio3_dbclk: gpio3_dbclk at 44e000b4 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkdiv32k_ick>;
+	bit-shift = <18>;
+	reg = <0x44e000b4 0x4>;
+};
+
+lcd_gclk: lcd_gclk at 44e00534 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+	reg = <0x44e00534 0x4>;
+	bit-mask = <0x3>;
+	set-rate-parent;
+};
+
+mmc_clk: mmc_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll_per_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+gfx_fclk_clksel_ck: gfx_fclk_clksel_ck at 44e0052c {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+	bit-shift = <1>;
+	reg = <0x44e0052c 0x4>;
+	bit-mask = <0x1>;
+};
+
+gfx_fck_div_ck: gfx_fck_div_ck at 44e0052c {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&gfx_fclk_clksel_ck>;
+	reg = <0x44e0052c 0x4>;
+	table = < 1 0 >, < 2 1 >;
+	bit-mask = <0x1>;
+};
+
+sysclkout_pre_ck: sysclkout_pre_ck at 44e00700 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+	reg = <0x44e00700 0x4>;
+	bit-mask = <0x7>;
+};
+
+clkout2_div_ck: clkout2_div_ck at 44e00700 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&sysclkout_pre_ck>;
+	bit-shift = <3>;
+	reg = <0x44e00700 0x4>;
+	table = < 1 0 >, < 2 1 >, < 3 2 >, < 4 3 >, < 5 4 >, < 6 5 >, < 7 6 >, < 8 7 >;
+	bit-mask = <0x7>;
+};
+
+dbg_sysclk_ck: dbg_sysclk_ck at 44e00414 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_clkin_ck>;
+	bit-shift = <19>;
+	reg = <0x44e00414 0x4>;
+};
+
+dbg_clka_ck: dbg_clka_ck at 44e00414 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_core_m4_ck>;
+	bit-shift = <30>;
+	reg = <0x44e00414 0x4>;
+};
+
+stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck at 44e00414 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+	bit-shift = <22>;
+	reg = <0x44e00414 0x4>;
+	bit-mask = <0x3>;
+};
+
+trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck at 44e00414 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+	bit-shift = <20>;
+	reg = <0x44e00414 0x4>;
+	bit-mask = <0x3>;
+};
+
+stm_clk_div_ck: stm_clk_div_ck at 44e00414 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&stm_pmd_clock_mux_ck>;
+	bit-shift = <27>;
+	reg = <0x44e00414 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+trace_clk_div_ck: trace_clk_div_ck at 44e00414 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&trace_pmd_clk_mux_ck>;
+	bit-shift = <24>;
+	reg = <0x44e00414 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+clkout2_ck: clkout2_ck at 44e00700 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkout2_div_ck>;
+	bit-shift = <7>;
+	reg = <0x44e00700 0x4>;
+};
+
+ehrpwm0_tbclk: ehrpwm0_tbclk at 44e10664 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m2_ck>;
+	bit-shift = <0>;
+	reg = <0x44e10664 0x4>;
+};
+
+ehrpwm1_tbclk: ehrpwm1_tbclk at 44e10664 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m2_ck>;
+	bit-shift = <1>;
+	reg = <0x44e10664 0x4>;
+};
+
+ehrpwm2_tbclk: ehrpwm2_tbclk at 44e10664 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll_per_m2_ck>;
+	bit-shift = <2>;
+	reg = <0x44e10664 0x4>;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 38b446b..4701e3c 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -531,4 +531,11 @@
 			status = "disabled";
 		};
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "am33xx-clocks.dtsi"
+	};
 };
-- 
1.7.9.5

[PATCHv4 19/33] CLK: omap: add am33xx clock init file

[Tero Kristo]

clk-33xx.c now contains the clock init functionality for am33xx, including
DT clock registration and adding of static clkdev entries.

This patch also moves the omap2_clk_enable_init_clocks declaration to
the driver include, as this is needed by the am33xx clock init code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.h |    1 -
 drivers/clk/omap/clk-33xx.c |   85 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/omap.h    |    1 +
 3 files changed, 86 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/omap/clk-33xx.c

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index d1a3125..6273f14 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -267,7 +267,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 				void __iomem **idlest_reg,
 				u8 *idlest_bit, u8 *idlest_val);
 int omap2_clk_enable_autoidle_all(void);
-void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
 			       const char *core_ck_name,
diff --git a/drivers/clk/omap/clk-33xx.c b/drivers/clk/omap/clk-33xx.c
new file mode 100644
index 0000000..3ada30e
--- /dev/null
+++ b/drivers/clk/omap/clk-33xx.c
@@ -0,0 +1,85 @@
+/*
+ * AM33XX Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ *     Tero Kristo (t-kristo@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/omap.h>
+
+
+static struct omap_dt_clk am33xx_clks[] = {
+	DT_CLK("cpu0", NULL, "dpll_mpu_ck"),
+	DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
+	DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
+	DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
+	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
+	DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
+	DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
+};
+
+static const char *enable_init_clks[] = {
+	"dpll_ddr_m2_ck",
+	"dpll_mpu_m2_ck",
+	"l3_gclk",
+	"l4hs_gclk",
+	"l4fw_gclk",
+	"l4ls_gclk",
+	/* Required for external peripherals like, Audio codecs */
+	"clkout2_ck",
+};
+
+int __init am33xx_clk_init(void)
+{
+	struct clk *clk1, *clk2;
+
+	dt_omap_clk_init();
+
+	omap_dt_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
+
+	omap2_clk_disable_autoidle_all();
+
+	omap2_clk_enable_init_clocks(enable_init_clks,
+				     ARRAY_SIZE(enable_init_clks));
+
+	/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
+	 *    physically present, in such a case HWMOD enabling of
+	 *    clock would be failure with default parent. And timer
+	 *    probe thinks clock is already enabled, this leads to
+	 *    crash upon accessing timer 3 & 6 registers in probe.
+	 *    Fix by setting parent of both these timers to master
+	 *    oscillator clock.
+	 */
+
+	clk1 = clk_get_sys(NULL, "sys_clkin_ck");
+	clk2 = clk_get_sys(NULL, "timer3_fck");
+	clk_set_parent(clk2, clk1);
+
+	clk2 = clk_get_sys(NULL, "timer6_fck");
+	clk_set_parent(clk2, clk1);
+	/*
+	 * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
+	 * the design/spec, so as a result, for example, timer which supposed
+	 * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
+	 * not expected by any use-case, so change WDT1 clock source to PRCM
+	 * 32KHz clock.
+	 */
+	clk1 = clk_get_sys(NULL, "wdt1_fck");
+	clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
+	clk_set_parent(clk1, clk2);
+
+	return 0;
+}
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index 58ebb80..c8d9468 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -184,6 +184,7 @@ int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
 
 int omap2_clk_disable_autoidle_all(void);
+void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 
 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
-- 
1.7.9.5

[PATCHv4 19/33] CLK: omap: add am33xx clock init file

[Tero Kristo]

clk-33xx.c now contains the clock init functionality for am33xx, including
DT clock registration and adding of static clkdev entries.

This patch also moves the omap2_clk_enable_init_clocks declaration to
the driver include, as this is needed by the am33xx clock init code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.h |    1 -
 drivers/clk/omap/clk-33xx.c |   85 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/omap.h    |    1 +
 3 files changed, 86 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/omap/clk-33xx.c

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index d1a3125..6273f14 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -267,7 +267,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
 				void __iomem **idlest_reg,
 				u8 *idlest_bit, u8 *idlest_val);
 int omap2_clk_enable_autoidle_all(void);
-void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
 			       const char *core_ck_name,
diff --git a/drivers/clk/omap/clk-33xx.c b/drivers/clk/omap/clk-33xx.c
new file mode 100644
index 0000000..3ada30e
--- /dev/null
+++ b/drivers/clk/omap/clk-33xx.c
@@ -0,0 +1,85 @@
+/*
+ * AM33XX Clock init
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc
+ *     Tero Kristo (t-kristo at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/omap.h>
+
+
+static struct omap_dt_clk am33xx_clks[] = {
+	DT_CLK("cpu0", NULL, "dpll_mpu_ck"),
+	DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
+	DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
+	DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
+	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
+	DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
+	DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
+	DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
+};
+
+static const char *enable_init_clks[] = {
+	"dpll_ddr_m2_ck",
+	"dpll_mpu_m2_ck",
+	"l3_gclk",
+	"l4hs_gclk",
+	"l4fw_gclk",
+	"l4ls_gclk",
+	/* Required for external peripherals like, Audio codecs */
+	"clkout2_ck",
+};
+
+int __init am33xx_clk_init(void)
+{
+	struct clk *clk1, *clk2;
+
+	dt_omap_clk_init();
+
+	omap_dt_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
+
+	omap2_clk_disable_autoidle_all();
+
+	omap2_clk_enable_init_clocks(enable_init_clks,
+				     ARRAY_SIZE(enable_init_clks));
+
+	/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
+	 *    physically present, in such a case HWMOD enabling of
+	 *    clock would be failure with default parent. And timer
+	 *    probe thinks clock is already enabled, this leads to
+	 *    crash upon accessing timer 3 & 6 registers in probe.
+	 *    Fix by setting parent of both these timers to master
+	 *    oscillator clock.
+	 */
+
+	clk1 = clk_get_sys(NULL, "sys_clkin_ck");
+	clk2 = clk_get_sys(NULL, "timer3_fck");
+	clk_set_parent(clk2, clk1);
+
+	clk2 = clk_get_sys(NULL, "timer6_fck");
+	clk_set_parent(clk2, clk1);
+	/*
+	 * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
+	 * the design/spec, so as a result, for example, timer which supposed
+	 * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
+	 * not expected by any use-case, so change WDT1 clock source to PRCM
+	 * 32KHz clock.
+	 */
+	clk1 = clk_get_sys(NULL, "wdt1_fck");
+	clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
+	clk_set_parent(clk1, clk2);
+
+	return 0;
+}
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index 58ebb80..c8d9468 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -184,6 +184,7 @@ int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
 
 int omap2_clk_disable_autoidle_all(void);
+void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 
 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
-- 
1.7.9.5

Re: [PATCHv4 19/33] CLK: omap: add am33xx clock init file

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> clk-33xx.c now contains the clock init functionality for am33xx, including
> DT clock registration and adding of static clkdev entries.
>
> This patch also moves the omap2_clk_enable_init_clocks declaration to
> the driver include, as this is needed by the am33xx clock init code.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   arch/arm/mach-omap2/clock.h |    1 -
>   drivers/clk/omap/clk-33xx.c |   85 +++++++++++++++++++++++++++++++++++++++++++
>   include/linux/clk/omap.h    |    1 +
>   3 files changed, 86 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/clk/omap/clk-33xx.c
>
> diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
> index d1a3125..6273f14 100644
> --- a/arch/arm/mach-omap2/clock.h
> +++ b/arch/arm/mach-omap2/clock.h
> @@ -267,7 +267,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
>   				void __iomem **idlest_reg,
>   				u8 *idlest_bit, u8 *idlest_val);
>   int omap2_clk_enable_autoidle_all(void);
> -void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
>   int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
>   void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
>   			       const char *core_ck_name,
> diff --git a/drivers/clk/omap/clk-33xx.c b/drivers/clk/omap/clk-33xx.c
> new file mode 100644
> index 0000000..3ada30e
> --- /dev/null
> +++ b/drivers/clk/omap/clk-33xx.c
[...]
> +static const char *enable_init_clks[] = {
> +	"dpll_ddr_m2_ck",
> +	"dpll_mpu_m2_ck",
> +	"l3_gclk",
> +	"l4hs_gclk",
> +	"l4fw_gclk",
> +	"l4ls_gclk",
> +	/* Required for external peripherals like, Audio codecs */
> +	"clkout2_ck",
> +};

should be a sort of dt property?

-- 
Regards,
Nishanth Menon

[PATCHv4 19/33] CLK: omap: add am33xx clock init file

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> clk-33xx.c now contains the clock init functionality for am33xx, including
> DT clock registration and adding of static clkdev entries.
>
> This patch also moves the omap2_clk_enable_init_clocks declaration to
> the driver include, as this is needed by the am33xx clock init code.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   arch/arm/mach-omap2/clock.h |    1 -
>   drivers/clk/omap/clk-33xx.c |   85 +++++++++++++++++++++++++++++++++++++++++++
>   include/linux/clk/omap.h    |    1 +
>   3 files changed, 86 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/clk/omap/clk-33xx.c
>
> diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
> index d1a3125..6273f14 100644
> --- a/arch/arm/mach-omap2/clock.h
> +++ b/arch/arm/mach-omap2/clock.h
> @@ -267,7 +267,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
>   				void __iomem **idlest_reg,
>   				u8 *idlest_bit, u8 *idlest_val);
>   int omap2_clk_enable_autoidle_all(void);
> -void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
>   int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
>   void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
>   			       const char *core_ck_name,
> diff --git a/drivers/clk/omap/clk-33xx.c b/drivers/clk/omap/clk-33xx.c
> new file mode 100644
> index 0000000..3ada30e
> --- /dev/null
> +++ b/drivers/clk/omap/clk-33xx.c
[...]
> +static const char *enable_init_clks[] = {
> +	"dpll_ddr_m2_ck",
> +	"dpll_mpu_m2_ck",
> +	"l3_gclk",
> +	"l4hs_gclk",
> +	"l4fw_gclk",
> +	"l4ls_gclk",
> +	/* Required for external peripherals like, Audio codecs */
> +	"clkout2_ck",
> +};

should be a sort of dt property?

-- 
Regards,
Nishanth Menon

Re: [PATCHv4 19/33] CLK: omap: add am33xx clock init file

[Tero Kristo]

On 07/30/2013 11:00 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> clk-33xx.c now contains the clock init functionality for am33xx,
>> including
>> DT clock registration and adding of static clkdev entries.
>>
>> This patch also moves the omap2_clk_enable_init_clocks declaration to
>> the driver include, as this is needed by the am33xx clock init code.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   arch/arm/mach-omap2/clock.h |    1 -
>>   drivers/clk/omap/clk-33xx.c |   85
>> +++++++++++++++++++++++++++++++++++++++++++
>>   include/linux/clk/omap.h    |    1 +
>>   3 files changed, 86 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/clk/omap/clk-33xx.c
>>
>> diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
>> index d1a3125..6273f14 100644
>> --- a/arch/arm/mach-omap2/clock.h
>> +++ b/arch/arm/mach-omap2/clock.h
>> @@ -267,7 +267,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap
>> *clk,
>>                   void __iomem **idlest_reg,
>>                   u8 *idlest_bit, u8 *idlest_val);
>>   int omap2_clk_enable_autoidle_all(void);
>> -void omap2_clk_enable_init_clocks(const char **clk_names, u8
>> num_clocks);
>>   int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
>>   void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
>>                      const char *core_ck_name,
>> diff --git a/drivers/clk/omap/clk-33xx.c b/drivers/clk/omap/clk-33xx.c
>> new file mode 100644
>> index 0000000..3ada30e
>> --- /dev/null
>> +++ b/drivers/clk/omap/clk-33xx.c
> [...]
>> +static const char *enable_init_clks[] = {
>> +    "dpll_ddr_m2_ck",
>> +    "dpll_mpu_m2_ck",
>> +    "l3_gclk",
>> +    "l4hs_gclk",
>> +    "l4fw_gclk",
>> +    "l4ls_gclk",
>> +    /* Required for external peripherals like, Audio codecs */
>> +    "clkout2_ck",
>> +};
>
> should be a sort of dt property?
>

Future dev maybe?

I try to avoid adding too many new props with this set....

-Tero

[PATCHv4 19/33] CLK: omap: add am33xx clock init file

[Tero Kristo]

On 07/30/2013 11:00 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> clk-33xx.c now contains the clock init functionality for am33xx,
>> including
>> DT clock registration and adding of static clkdev entries.
>>
>> This patch also moves the omap2_clk_enable_init_clocks declaration to
>> the driver include, as this is needed by the am33xx clock init code.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   arch/arm/mach-omap2/clock.h |    1 -
>>   drivers/clk/omap/clk-33xx.c |   85
>> +++++++++++++++++++++++++++++++++++++++++++
>>   include/linux/clk/omap.h    |    1 +
>>   3 files changed, 86 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/clk/omap/clk-33xx.c
>>
>> diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
>> index d1a3125..6273f14 100644
>> --- a/arch/arm/mach-omap2/clock.h
>> +++ b/arch/arm/mach-omap2/clock.h
>> @@ -267,7 +267,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap
>> *clk,
>>                   void __iomem **idlest_reg,
>>                   u8 *idlest_bit, u8 *idlest_val);
>>   int omap2_clk_enable_autoidle_all(void);
>> -void omap2_clk_enable_init_clocks(const char **clk_names, u8
>> num_clocks);
>>   int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
>>   void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
>>                      const char *core_ck_name,
>> diff --git a/drivers/clk/omap/clk-33xx.c b/drivers/clk/omap/clk-33xx.c
>> new file mode 100644
>> index 0000000..3ada30e
>> --- /dev/null
>> +++ b/drivers/clk/omap/clk-33xx.c
> [...]
>> +static const char *enable_init_clks[] = {
>> +    "dpll_ddr_m2_ck",
>> +    "dpll_mpu_m2_ck",
>> +    "l3_gclk",
>> +    "l4hs_gclk",
>> +    "l4fw_gclk",
>> +    "l4ls_gclk",
>> +    /* Required for external peripherals like, Audio codecs */
>> +    "clkout2_ck",
>> +};
>
> should be a sort of dt property?
>

Future dev maybe?

I try to avoid adding too many new props with this set....

-Tero

Re: [PATCHv4 19/33] CLK: omap: add am33xx clock init file

[Nishanth Menon]

On 07/31/2013 09:59 AM, Tero Kristo wrote:
> On 07/30/2013 11:00 PM, Nishanth Menon wrote:
>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
[...]

>>> diff --git a/drivers/clk/omap/clk-33xx.c b/drivers/clk/omap/clk-33xx.c
>>> new file mode 100644
>>> index 0000000..3ada30e
>>> --- /dev/null
>>> +++ b/drivers/clk/omap/clk-33xx.c
>> [...]
>>> +static const char *enable_init_clks[] = {
>>> +    "dpll_ddr_m2_ck",
>>> +    "dpll_mpu_m2_ck",
>>> +    "l3_gclk",
>>> +    "l4hs_gclk",
>>> +    "l4fw_gclk",
>>> +    "l4ls_gclk",
>>> +    /* Required for external peripherals like, Audio codecs */
>>> +    "clkout2_ck",
>>> +};
>>
>> should be a sort of dt property?
>>
>
> Future dev maybe?
>
> I try to avoid adding too many new props with this set....

it should be trivial to add it in, no? these are the stuff we will have 
to do for a clean omap conversion to dt :( - we can work through the 
details as we present it with Mike on RFCs.

-- 
Regards,
Nishanth Menon

[PATCHv4 19/33] CLK: omap: add am33xx clock init file

[Nishanth Menon]

On 07/31/2013 09:59 AM, Tero Kristo wrote:
> On 07/30/2013 11:00 PM, Nishanth Menon wrote:
>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
[...]

>>> diff --git a/drivers/clk/omap/clk-33xx.c b/drivers/clk/omap/clk-33xx.c
>>> new file mode 100644
>>> index 0000000..3ada30e
>>> --- /dev/null
>>> +++ b/drivers/clk/omap/clk-33xx.c
>> [...]
>>> +static const char *enable_init_clks[] = {
>>> +    "dpll_ddr_m2_ck",
>>> +    "dpll_mpu_m2_ck",
>>> +    "l3_gclk",
>>> +    "l4hs_gclk",
>>> +    "l4fw_gclk",
>>> +    "l4ls_gclk",
>>> +    /* Required for external peripherals like, Audio codecs */
>>> +    "clkout2_ck",
>>> +};
>>
>> should be a sort of dt property?
>>
>
> Future dev maybe?
>
> I try to avoid adding too many new props with this set....

it should be trivial to add it in, no? these are the stuff we will have 
to do for a clean omap conversion to dt :( - we can work through the 
details as we present it with Mike on RFCs.

-- 
Regards,
Nishanth Menon

Re: [PATCHv4 19/33] CLK: omap: add am33xx clock init file

[Tero Kristo]

On 08/01/2013 05:43 PM, Nishanth Menon wrote:
> On 07/31/2013 09:59 AM, Tero Kristo wrote:
>> On 07/30/2013 11:00 PM, Nishanth Menon wrote:
>>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
> [...]
>
>>>> diff --git a/drivers/clk/omap/clk-33xx.c b/drivers/clk/omap/clk-33xx.c
>>>> new file mode 100644
>>>> index 0000000..3ada30e
>>>> --- /dev/null
>>>> +++ b/drivers/clk/omap/clk-33xx.c
>>> [...]
>>>> +static const char *enable_init_clks[] = {
>>>> +    "dpll_ddr_m2_ck",
>>>> +    "dpll_mpu_m2_ck",
>>>> +    "l3_gclk",
>>>> +    "l4hs_gclk",
>>>> +    "l4fw_gclk",
>>>> +    "l4ls_gclk",
>>>> +    /* Required for external peripherals like, Audio codecs */
>>>> +    "clkout2_ck",
>>>> +};
>>>
>>> should be a sort of dt property?
>>>
>>
>> Future dev maybe?
>>
>> I try to avoid adding too many new props with this set....
>
> it should be trivial to add it in, no? these are the stuff we will have
> to do for a clean omap conversion to dt :( - we can work through the
> details as we present it with Mike on RFCs.

Problem with generic props is that they potentially take longer time to 
get in, and we are quite in a hurry with this set.

And these things can be added later.

-Tero

[PATCHv4 19/33] CLK: omap: add am33xx clock init file

[Tero Kristo]

On 08/01/2013 05:43 PM, Nishanth Menon wrote:
> On 07/31/2013 09:59 AM, Tero Kristo wrote:
>> On 07/30/2013 11:00 PM, Nishanth Menon wrote:
>>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
> [...]
>
>>>> diff --git a/drivers/clk/omap/clk-33xx.c b/drivers/clk/omap/clk-33xx.c
>>>> new file mode 100644
>>>> index 0000000..3ada30e
>>>> --- /dev/null
>>>> +++ b/drivers/clk/omap/clk-33xx.c
>>> [...]
>>>> +static const char *enable_init_clks[] = {
>>>> +    "dpll_ddr_m2_ck",
>>>> +    "dpll_mpu_m2_ck",
>>>> +    "l3_gclk",
>>>> +    "l4hs_gclk",
>>>> +    "l4fw_gclk",
>>>> +    "l4ls_gclk",
>>>> +    /* Required for external peripherals like, Audio codecs */
>>>> +    "clkout2_ck",
>>>> +};
>>>
>>> should be a sort of dt property?
>>>
>>
>> Future dev maybe?
>>
>> I try to avoid adding too many new props with this set....
>
> it should be trivial to add it in, no? these are the stuff we will have
> to do for a clean omap conversion to dt :( - we can work through the
> details as we present it with Mike on RFCs.

Problem with generic props is that they potentially take longer time to 
get in, and we are quite in a hurry with this set.

And these things can be added later.

-Tero

[PATCHv4 20/33] ARM: AM33xx: remove old clock data and link in new clock init code

[Tero Kristo]

AM33xx clocks have now been moved to DT, thus remove the old data file
and use the new init code under OMAP clock driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/Makefile          |    1 -
 arch/arm/mach-omap2/cclock33xx_data.c | 1059 ---------------------------------
 drivers/clk/omap/Makefile             |    3 +-
 3 files changed, 2 insertions(+), 1061 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/cclock33xx_data.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 9f8d3ed..a4782e2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -178,7 +178,6 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o dpll44xx.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX)		+= cclock33xx_data.o
 obj-$(CONFIG_SOC_OMAP5)			+= $(clock-common)
 obj-$(CONFIG_SOC_OMAP5)			+= dpll3xxx.o dpll44xx.o
 
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
deleted file mode 100644
index ba6534d..0000000
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ /dev/null
@@ -1,1059 +0,0 @@
-/*
- * AM33XX Clock data
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "am33xx.h"
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "control.h"
-#include "cm.h"
-#include "cm33xx.h"
-#include "cm-regbits-33xx.h"
-#include "prm.h"
-
-/* Modulemode control */
-#define AM33XX_MODULEMODE_HWCTRL_SHIFT		0
-#define AM33XX_MODULEMODE_SWCTRL_SHIFT		1
-
-/*LIST_HEAD(clocks);*/
-
-/* Root clocks */
-
-/* RTC 32k */
-DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
-
-/* On-Chip 32KHz RC OSC */
-DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
-
-/* Crystal input clks */
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-/* Oscillator clock */
-/* 19.2, 24, 25 or 26 MHz */
-static const char *sys_clkin_ck_parents[] = {
-	"virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
-	"virt_26000000_ck",
-};
-
-/*
- * sys_clk in: input to the dpll and also used as funtional clock for,
- *   adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
- *
- */
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
-	       AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
-	       AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
-	       AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
-	       0, NULL);
-
-/* External clock - 12 MHz */
-DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_CORE,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_CORE,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_CORE,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKDCOLDO output */
-static const char *dpll_core_ck_parents[] = {
-	"sys_clkin_ck",
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
-	.recalc_rate	= &omap3_dpll_recalc,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
-	.hw	= {
-		.clk	= &dpll_core_ck,
-	},
-	.dpll_data	= &dpll_core_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-	"dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static const struct clk_ops dpll_x2_ck_ops = {
-	.recalc_rate	= &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
-	.hw	= {
-		.clk	= &dpll_core_x2_ck,
-	},
-	.flags		= CLOCK_CLKOUTX2,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-		   0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
-		   AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
-		   AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
-		   NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-		   0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
-		   AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
-		   AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-		   0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
-		   AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
-		   AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_MPU,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_MPU,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_MPU,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_mpu_ck;
-
-static const struct clk_ops dpll_mpu_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
-	.hw = {
-		.clk	= &dpll_mpu_ck,
-	},
-	.dpll_data	= &dpll_mpu_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
-		   0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
-		   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_DDR */
-static struct dpll_data dpll_ddr_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_DDR,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_DDR,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_DDR,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_ddr_ck;
-
-static const struct clk_ops dpll_ddr_ck_ops = {
-	.recalc_rate	= &omap3_dpll_recalc,
-	.get_parent	= &omap2_init_dpll_parent,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk_hw_omap dpll_ddr_ck_hw = {
-	.hw = {
-		.clk	= &dpll_ddr_ck,
-	},
-	.dpll_data	= &dpll_ddr_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
-		   0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
-		   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-/* emif_fck functional clock */
-DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
-			0x0, 1, 2);
-
-/* DPLL_DISP */
-static struct dpll_data dpll_disp_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_DISP,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_DISP,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_DISP,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_disp_ck;
-
-static struct clk_hw_omap dpll_disp_ck_hw = {
-	.hw = {
-		.clk	= &dpll_disp_ck,
-	},
-	.dpll_data	= &dpll_disp_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
-		   CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
-		   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_PERIPH,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_PER,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_PER,
-	.mult_mask	= AM33XX_DPLL_MULT_PERIPH_MASK,
-	.div1_mask	= AM33XX_DPLL_PER_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-	.flags		= DPLL_J_TYPE,
-};
-
-/* CLKDCOLDO */
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
-	.hw	= {
-		.clk	= &dpll_per_ck,
-	},
-	.dpll_data	= &dpll_per_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/* CLKOUT: fdpll/M2 */
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
-		   AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
-		   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
-		   NULL);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
-			&dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
-			&dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
-			&dpll_core_m4_ck, 0x0, 1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-			1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
-			8);
-
-/*
- * Below clock nodes describes clockdomains derived out
- * of core clock.
- */
-static const struct clk_ops clk_ops_null = {
-};
-
-static const char *l3_gclk_parents[] = {
-	"dpll_core_m4_ck"
-};
-
-static struct clk l3_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
-DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
-
-static struct clk l4hs_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
-DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
-
-static const char *l3s_gclk_parents[] = {
-	"dpll_core_m4_div2_ck"
-};
-
-static struct clk l3s_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
-DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4fw_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
-DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4ls_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
-DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk sysclk_div_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
-DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
-
-/*
- * In order to match the clock domain with hwmod clockdomain entry,
- * separate clock nodes is required for the modules which are
- * directly getting their funtioncal clock from sys_clkin.
- */
-static struct clk adc_tsc_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
-DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
-DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
-DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk sha0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
-DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk aes0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
-DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
-
-/*
- * Modules clock nodes
- *
- * The following clock leaf nodes are added for the moment because:
- *
- *  - hwmod data is not present for these modules, either hwmod
- *    control is not required or its not populated.
- *  - Driver code is not yet migrated to use hwmod/runtime pm
- *  - Modules outside kernel access (to disable them by default)
- *
- *     - mmu (gfx domain)
- *     - cefuse
- *     - usbotg_fck (its additional clock and not really a modulemode)
- *     - ieee5000
- */
-
-DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-		AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-		AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-		0x0, NULL);
-
-/*
- * clkdiv32 is generated from fixed division of 732.4219
- */
-DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
-
-static struct clk clkdiv32k_ick;
-
-static const char *clkdiv32k_ick_parent_names[] = {
-	"clkdiv32k_ck",
-};
-
-static const struct clk_ops clkdiv32k_ick_ops = {
-	.enable         = &omap2_dflt_clk_enable,
-	.disable        = &omap2_dflt_clk_disable,
-	.is_enabled     = &omap2_dflt_clk_is_enabled,
-	.init           = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap clkdiv32k_ick_hw = {
-	.hw	= {
-		.clk	= &clkdiv32k_ick,
-	},
-	.enable_reg	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
-	.enable_bit	= AM33XX_MODULEMODE_SWCTRL_SHIFT,
-	.clkdm_name	= "clk_24mhz_clkdm",
-};
-
-DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
-
-/* "usbotg_fck" is an additional clock and not really a modulemode */
-DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
-		AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
-		0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
-		AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-/* Timers */
-static const struct clksel timer1_clkmux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
-	{ .parent = &tclkin_ck, .rates = div_1_2_rates },
-	{ .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
-	{ .parent = &clk_32768_ck, .rates = div_1_4_rates },
-	{ .parent = NULL },
-};
-
-static const char *timer1_ck_parents[] = {
-	"sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
-	"clk_32768_ck",
-};
-
-static struct clk timer1_fck;
-
-static const struct clk_ops timer1_fck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap timer1_fck_hw = {
-	.hw	= {
-		.clk	= &timer1_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer1_clkmux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER1MS_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_2_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
-
-static const struct clksel timer2_to_7_clk_sel[] = {
-	{ .parent = &tclkin_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_clkin_ck, .rates = div_1_1_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *timer2_to_7_ck_parents[] = {
-	"tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
-};
-
-static struct clk timer2_fck;
-
-static struct clk_hw_omap timer2_fck_hw = {
-	.hw	= {
-		.clk	= &timer2_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER2_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer3_fck;
-
-static struct clk_hw_omap timer3_fck_hw = {
-	.hw	= {
-		.clk	= &timer3_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER3_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer4_fck;
-
-static struct clk_hw_omap timer4_fck_hw = {
-	.hw	= {
-		.clk	= &timer4_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER4_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer5_fck;
-
-static struct clk_hw_omap timer5_fck_hw = {
-	.hw	= {
-		.clk	= &timer5_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER5_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer6_fck;
-
-static struct clk_hw_omap timer6_fck_hw = {
-	.hw	= {
-		.clk	= &timer6_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER6_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer7_fck;
-
-static struct clk_hw_omap timer7_fck_hw = {
-	.hw	= {
-		.clk	= &timer7_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER7_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
-			"dpll_core_m5_ck",
-			&dpll_core_m5_ck,
-			0x0,
-			1, 2);
-
-static const struct clk_ops cpsw_fck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-};
-
-static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
-	{ .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *cpsw_cpts_rft_ck_parents[] = {
-	"dpll_core_m5_ck", "dpll_core_m4_ck",
-};
-
-static struct clk cpsw_cpts_rft_clk;
-
-static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
-	.hw	= {
-		.clk	= &cpsw_cpts_rft_clk,
-	},
-	.clkdm_name	= "cpsw_125mhz_clkdm",
-	.clksel		= cpsw_cpts_rft_clkmux_sel,
-	.clksel_reg	= AM33XX_CM_CPTS_RFT_CLKSEL,
-	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
-
-
-/* gpio */
-static const char *gpio0_ck_parents[] = {
-	"clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel gpio0_dbclk_mux_sel[] = {
-	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-	{ .parent = &clk_32768_ck, .rates = div_1_1_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const struct clk_ops gpio_fck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static struct clk gpio0_dbclk_mux_ck;
-
-static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
-	.hw	= {
-		.clk	= &gpio0_dbclk_mux_ck,
-	},
-	.clkdm_name	= "l4_wkup_clkdm",
-	.clksel		= gpio0_dbclk_mux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_GPIO0_DBCLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
-
-DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
-		AM33XX_CM_WKUP_GPIO0_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-		AM33XX_CM_PER_GPIO1_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-		AM33XX_CM_PER_GPIO2_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-		AM33XX_CM_PER_GPIO3_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
-
-
-static const char *pruss_ck_parents[] = {
-	"l3_gclk", "dpll_disp_m2_ck",
-};
-
-static const struct clksel pruss_ocp_clk_mux_sel[] = {
-	{ .parent = &l3_gclk, .rates = div_1_0_rates },
-	{ .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk pruss_ocp_gclk;
-
-static struct clk_hw_omap pruss_ocp_gclk_hw = {
-	.hw	= {
-		.clk	= &pruss_ocp_gclk,
-	},
-	.clkdm_name	= "pruss_ocp_clkdm",
-	.clksel		= pruss_ocp_clk_mux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_PRUSS_OCP_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
-
-static const char *lcd_ck_parents[] = {
-	"dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel lcd_clk_mux_sel[] = {
-	{ .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
-	{ .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static struct clk lcd_gclk;
-
-static struct clk_hw_omap lcd_gclk_hw = {
-	.hw	= {
-		.clk	= &lcd_gclk,
-	},
-	.clkdm_name	= "lcdc_clkdm",
-	.clksel		= lcd_clk_mux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_LCDC_PIXEL_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
-			gpio_fck_ops, CLK_SET_RATE_PARENT);
-
-DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
-
-static const char *gfx_ck_parents[] = {
-	"dpll_core_m4_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel gfx_clksel_sel[] = {
-	{ .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk gfx_fclk_clksel_ck;
-
-static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
-	.hw	= {
-		.clk	= &gfx_fclk_clksel_ck,
-	},
-	.clksel		= gfx_clksel_sel,
-	.clksel_reg	= AM33XX_CLKSEL_GFX_FCLK,
-	.clksel_mask	= AM33XX_CLKSEL_GFX_FCLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
-
-static const struct clk_div_table div_1_0_2_1_rates[] = {
-	{ .div = 1, .val = 0, },
-	{ .div = 2, .val = 1, },
-	{ .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
-			 &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
-			 AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
-			 0x0, div_1_0_2_1_rates, NULL);
-
-static const char *sysclkout_ck_parents[] = {
-	"clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
-	"lcd_gclk",
-};
-
-static const struct clksel sysclkout_pre_sel[] = {
-	{ .parent = &clk_32768_ck, .rates = div_1_0_rates },
-	{ .parent = &l3_gclk, .rates = div_1_1_rates },
-	{ .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
-	{ .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
-	{ .parent = &lcd_gclk, .rates = div_1_4_rates },
-	{ .parent = NULL },
-};
-
-static struct clk sysclkout_pre_ck;
-
-static struct clk_hw_omap sysclkout_pre_ck_hw = {
-	.hw	= {
-		.clk	= &sysclkout_pre_ck,
-	},
-	.clksel		= sysclkout_pre_sel,
-	.clksel_reg	= AM33XX_CM_CLKOUT_CTRL,
-	.clksel_mask	= AM33XX_CLKOUT2SOURCE_MASK,
-};
-
-DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
-
-/* Divide by 8 clock rates with default clock is 1/1*/
-static const struct clk_div_table div8_rates[] = {
-	{ .div = 1, .val = 0, },
-	{ .div = 2, .val = 1, },
-	{ .div = 3, .val = 2, },
-	{ .div = 4, .val = 3, },
-	{ .div = 5, .val = 4, },
-	{ .div = 6, .val = 5, },
-	{ .div = 7, .val = 6, },
-	{ .div = 8, .val = 7, },
-	{ .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
-			 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
-			 AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
-
-DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
-		AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
-
-static const char *wdt_ck_parents[] = {
-	"clk_rc32k_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel wdt_clkmux_sel[] = {
-	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk wdt1_fck;
-
-static struct clk_hw_omap wdt1_fck_hw = {
-	.hw	= {
-		.clk	= &wdt1_fck,
-	},
-	.clkdm_name	= "l4_wkup_clkdm",
-	.clksel		= wdt_clkmux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_WDT1_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
-
-static const char *pwmss_clk_parents[] = {
-	"dpll_per_m2_ck",
-};
-
-static const struct clk_ops ehrpwm_tbclk_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
-			 NULL, NULL, 0,
-			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-			 AM33XX_PWMSS0_TBCLKEN_SHIFT,
-			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
-			 NULL, NULL, 0,
-			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-			 AM33XX_PWMSS1_TBCLKEN_SHIFT,
-			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
-			 NULL, NULL, 0,
-			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-			 AM33XX_PWMSS2_TBCLKEN_SHIFT,
-			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-/*
- * debugss optional clocks
- */
-DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
-		0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
-		0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
-
-static const char *stm_pmd_clock_mux_ck_parents[] = {
-	"dbg_sysclk_ck", "dbg_clka_ck",
-};
-
-DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
-	       AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
-	       AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
-	       AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-	       AM33XX_TRC_PMD_CLKSEL_SHIFT,
-	       AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
-		   &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		   AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
-		   AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
-		   &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		   AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
-		   AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-/*
- * clkdev
- */
-static struct omap_clk am33xx_clks[] = {
-	CLK(NULL,	"clk_32768_ck",		&clk_32768_ck),
-	CLK(NULL,	"clk_rc32k_ck",		&clk_rc32k_ck),
-	CLK(NULL,	"virt_19200000_ck",	&virt_19200000_ck),
-	CLK(NULL,	"virt_24000000_ck",	&virt_24000000_ck),
-	CLK(NULL,	"virt_25000000_ck",	&virt_25000000_ck),
-	CLK(NULL,	"virt_26000000_ck",	&virt_26000000_ck),
-	CLK(NULL,	"sys_clkin_ck",		&sys_clkin_ck),
-	CLK(NULL,	"tclkin_ck",		&tclkin_ck),
-	CLK(NULL,	"dpll_core_ck",		&dpll_core_ck),
-	CLK(NULL,	"dpll_core_x2_ck",	&dpll_core_x2_ck),
-	CLK(NULL,	"dpll_core_m4_ck",	&dpll_core_m4_ck),
-	CLK(NULL,	"dpll_core_m5_ck",	&dpll_core_m5_ck),
-	CLK(NULL,	"dpll_core_m6_ck",	&dpll_core_m6_ck),
-	CLK(NULL,	"dpll_mpu_ck",		&dpll_mpu_ck),
-	CLK("cpu0",	NULL,			&dpll_mpu_ck),
-	CLK(NULL,	"dpll_mpu_m2_ck",	&dpll_mpu_m2_ck),
-	CLK(NULL,	"dpll_ddr_ck",		&dpll_ddr_ck),
-	CLK(NULL,	"dpll_ddr_m2_ck",	&dpll_ddr_m2_ck),
-	CLK(NULL,	"dpll_ddr_m2_div2_ck",	&dpll_ddr_m2_div2_ck),
-	CLK(NULL,	"dpll_disp_ck",		&dpll_disp_ck),
-	CLK(NULL,	"dpll_disp_m2_ck",	&dpll_disp_m2_ck),
-	CLK(NULL,	"dpll_per_ck",		&dpll_per_ck),
-	CLK(NULL,	"dpll_per_m2_ck",	&dpll_per_m2_ck),
-	CLK(NULL,	"dpll_per_m2_div4_wkupdm_ck",	&dpll_per_m2_div4_wkupdm_ck),
-	CLK(NULL,	"dpll_per_m2_div4_ck",	&dpll_per_m2_div4_ck),
-	CLK(NULL,	"adc_tsc_fck",		&adc_tsc_fck),
-	CLK(NULL,	"cefuse_fck",		&cefuse_fck),
-	CLK(NULL,	"clkdiv32k_ck",		&clkdiv32k_ck),
-	CLK(NULL,	"clkdiv32k_ick",	&clkdiv32k_ick),
-	CLK(NULL,	"dcan0_fck",		&dcan0_fck),
-	CLK("481cc000.d_can",	NULL,		&dcan0_fck),
-	CLK(NULL,	"dcan1_fck",		&dcan1_fck),
-	CLK("481d0000.d_can",	NULL,		&dcan1_fck),
-	CLK(NULL,	"pruss_ocp_gclk",	&pruss_ocp_gclk),
-	CLK(NULL,	"mcasp0_fck",		&mcasp0_fck),
-	CLK(NULL,	"mcasp1_fck",		&mcasp1_fck),
-	CLK(NULL,	"mmu_fck",		&mmu_fck),
-	CLK(NULL,	"smartreflex0_fck",	&smartreflex0_fck),
-	CLK(NULL,	"smartreflex1_fck",	&smartreflex1_fck),
-	CLK(NULL,	"sha0_fck",		&sha0_fck),
-	CLK(NULL,	"aes0_fck",		&aes0_fck),
-	CLK(NULL,	"timer1_fck",		&timer1_fck),
-	CLK(NULL,	"timer2_fck",		&timer2_fck),
-	CLK(NULL,	"timer3_fck",		&timer3_fck),
-	CLK(NULL,	"timer4_fck",		&timer4_fck),
-	CLK(NULL,	"timer5_fck",		&timer5_fck),
-	CLK(NULL,	"timer6_fck",		&timer6_fck),
-	CLK(NULL,	"timer7_fck",		&timer7_fck),
-	CLK(NULL,	"usbotg_fck",		&usbotg_fck),
-	CLK(NULL,	"ieee5000_fck",		&ieee5000_fck),
-	CLK(NULL,	"wdt1_fck",		&wdt1_fck),
-	CLK(NULL,	"l4_rtc_gclk",		&l4_rtc_gclk),
-	CLK(NULL,	"l3_gclk",		&l3_gclk),
-	CLK(NULL,	"dpll_core_m4_div2_ck",	&dpll_core_m4_div2_ck),
-	CLK(NULL,	"l4hs_gclk",		&l4hs_gclk),
-	CLK(NULL,	"l3s_gclk",		&l3s_gclk),
-	CLK(NULL,	"l4fw_gclk",		&l4fw_gclk),
-	CLK(NULL,	"l4ls_gclk",		&l4ls_gclk),
-	CLK(NULL,	"clk_24mhz",		&clk_24mhz),
-	CLK(NULL,	"sysclk_div_ck",	&sysclk_div_ck),
-	CLK(NULL,	"cpsw_125mhz_gclk",	&cpsw_125mhz_gclk),
-	CLK(NULL,	"cpsw_cpts_rft_clk",	&cpsw_cpts_rft_clk),
-	CLK(NULL,	"gpio0_dbclk_mux_ck",	&gpio0_dbclk_mux_ck),
-	CLK(NULL,	"gpio0_dbclk",		&gpio0_dbclk),
-	CLK(NULL,	"gpio1_dbclk",		&gpio1_dbclk),
-	CLK(NULL,	"gpio2_dbclk",		&gpio2_dbclk),
-	CLK(NULL,	"gpio3_dbclk",		&gpio3_dbclk),
-	CLK(NULL,	"lcd_gclk",		&lcd_gclk),
-	CLK(NULL,	"mmc_clk",		&mmc_clk),
-	CLK(NULL,	"gfx_fclk_clksel_ck",	&gfx_fclk_clksel_ck),
-	CLK(NULL,	"gfx_fck_div_ck",	&gfx_fck_div_ck),
-	CLK(NULL,	"sysclkout_pre_ck",	&sysclkout_pre_ck),
-	CLK(NULL,	"clkout2_div_ck",	&clkout2_div_ck),
-	CLK(NULL,	"timer_32k_ck",		&clkdiv32k_ick),
-	CLK(NULL,	"timer_sys_ck",		&sys_clkin_ck),
-	CLK(NULL,	"dbg_sysclk_ck",	&dbg_sysclk_ck),
-	CLK(NULL,	"dbg_clka_ck",		&dbg_clka_ck),
-	CLK(NULL,	"stm_pmd_clock_mux_ck",	&stm_pmd_clock_mux_ck),
-	CLK(NULL,	"trace_pmd_clk_mux_ck",	&trace_pmd_clk_mux_ck),
-	CLK(NULL,	"stm_clk_div_ck",	&stm_clk_div_ck),
-	CLK(NULL,	"trace_clk_div_ck",	&trace_clk_div_ck),
-	CLK(NULL,	"clkout2_ck",		&clkout2_ck),
-	CLK("48300200.ehrpwm",	"tbclk",	&ehrpwm0_tbclk),
-	CLK("48302200.ehrpwm",	"tbclk",	&ehrpwm1_tbclk),
-	CLK("48304200.ehrpwm",	"tbclk",	&ehrpwm2_tbclk),
-};
-
-
-static const char *enable_init_clks[] = {
-	"dpll_ddr_m2_ck",
-	"dpll_mpu_m2_ck",
-	"l3_gclk",
-	"l4hs_gclk",
-	"l4fw_gclk",
-	"l4ls_gclk",
-	"clkout2_ck",	/* Required for external peripherals like, Audio codecs */
-};
-
-int __init am33xx_clk_init(void)
-{
-	if (soc_is_am33xx())
-		cpu_mask = RATE_IN_AM33XX;
-
-	omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
-
-	omap2_clk_disable_autoidle_all();
-
-	omap2_clk_enable_init_clocks(enable_init_clks,
-				     ARRAY_SIZE(enable_init_clks));
-
-	/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
-	 *    physically present, in such a case HWMOD enabling of
-	 *    clock would be failure with default parent. And timer
-	 *    probe thinks clock is already enabled, this leads to
-	 *    crash upon accessing timer 3 & 6 registers in probe.
-	 *    Fix by setting parent of both these timers to master
-	 *    oscillator clock.
-	 */
-
-	clk_set_parent(&timer3_fck, &sys_clkin_ck);
-	clk_set_parent(&timer6_fck, &sys_clkin_ck);
-	/*
-	 * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
-	 * the design/spec, so as a result, for example, timer which supposed
-	 * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
-	 * not expected by any use-case, so change WDT1 clock source to PRCM
-	 * 32KHz clock.
-	 */
-	clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
-
-	return 0;
-}
diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index b8dbfda..c4e8825 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1,2 +1,3 @@
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
-					   clk-44xx.o clk-54xx.o clk-7xx.o
+					   clk-44xx.o clk-54xx.o clk-7xx.o \
+					   clk-33xx.o
-- 
1.7.9.5

[PATCHv4 20/33] ARM: AM33xx: remove old clock data and link in new clock init code

[Tero Kristo]

AM33xx clocks have now been moved to DT, thus remove the old data file
and use the new init code under OMAP clock driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/Makefile          |    1 -
 arch/arm/mach-omap2/cclock33xx_data.c | 1059 ---------------------------------
 drivers/clk/omap/Makefile             |    3 +-
 3 files changed, 2 insertions(+), 1061 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/cclock33xx_data.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 9f8d3ed..a4782e2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -178,7 +178,6 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o dpll44xx.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX)		+= cclock33xx_data.o
 obj-$(CONFIG_SOC_OMAP5)			+= $(clock-common)
 obj-$(CONFIG_SOC_OMAP5)			+= dpll3xxx.o dpll44xx.o
 
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
deleted file mode 100644
index ba6534d..0000000
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ /dev/null
@@ -1,1059 +0,0 @@
-/*
- * AM33XX Clock data
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "am33xx.h"
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "control.h"
-#include "cm.h"
-#include "cm33xx.h"
-#include "cm-regbits-33xx.h"
-#include "prm.h"
-
-/* Modulemode control */
-#define AM33XX_MODULEMODE_HWCTRL_SHIFT		0
-#define AM33XX_MODULEMODE_SWCTRL_SHIFT		1
-
-/*LIST_HEAD(clocks);*/
-
-/* Root clocks */
-
-/* RTC 32k */
-DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
-
-/* On-Chip 32KHz RC OSC */
-DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
-
-/* Crystal input clks */
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-/* Oscillator clock */
-/* 19.2, 24, 25 or 26 MHz */
-static const char *sys_clkin_ck_parents[] = {
-	"virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
-	"virt_26000000_ck",
-};
-
-/*
- * sys_clk in: input to the dpll and also used as funtional clock for,
- *   adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
- *
- */
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
-	       AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
-	       AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
-	       AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
-	       0, NULL);
-
-/* External clock - 12 MHz */
-DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_CORE,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_CORE,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_CORE,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKDCOLDO output */
-static const char *dpll_core_ck_parents[] = {
-	"sys_clkin_ck",
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
-	.recalc_rate	= &omap3_dpll_recalc,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
-	.hw	= {
-		.clk	= &dpll_core_ck,
-	},
-	.dpll_data	= &dpll_core_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-	"dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static const struct clk_ops dpll_x2_ck_ops = {
-	.recalc_rate	= &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
-	.hw	= {
-		.clk	= &dpll_core_x2_ck,
-	},
-	.flags		= CLOCK_CLKOUTX2,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-		   0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
-		   AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
-		   AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
-		   NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-		   0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
-		   AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
-		   AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-		   0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
-		   AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
-		   AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_MPU,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_MPU,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_MPU,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_mpu_ck;
-
-static const struct clk_ops dpll_mpu_ck_ops = {
-	.enable		= &omap3_noncore_dpll_enable,
-	.disable	= &omap3_noncore_dpll_disable,
-	.recalc_rate	= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-	.get_parent	= &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
-	.hw = {
-		.clk	= &dpll_mpu_ck,
-	},
-	.dpll_data	= &dpll_mpu_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
-		   0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
-		   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_DDR */
-static struct dpll_data dpll_ddr_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_DDR,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_DDR,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_DDR,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_ddr_ck;
-
-static const struct clk_ops dpll_ddr_ck_ops = {
-	.recalc_rate	= &omap3_dpll_recalc,
-	.get_parent	= &omap2_init_dpll_parent,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk_hw_omap dpll_ddr_ck_hw = {
-	.hw = {
-		.clk	= &dpll_ddr_ck,
-	},
-	.dpll_data	= &dpll_ddr_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
-		   0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
-		   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-/* emif_fck functional clock */
-DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
-			0x0, 1, 2);
-
-/* DPLL_DISP */
-static struct dpll_data dpll_disp_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_DISP,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_DISP,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_DISP,
-	.mult_mask	= AM33XX_DPLL_MULT_MASK,
-	.div1_mask	= AM33XX_DPLL_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_disp_ck;
-
-static struct clk_hw_omap dpll_disp_ck_hw = {
-	.hw = {
-		.clk	= &dpll_disp_ck,
-	},
-	.dpll_data	= &dpll_disp_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
-		   CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
-		   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
-		   CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-	.mult_div1_reg	= AM33XX_CM_CLKSEL_DPLL_PERIPH,
-	.clk_bypass	= &sys_clkin_ck,
-	.clk_ref	= &sys_clkin_ck,
-	.control_reg	= AM33XX_CM_CLKMODE_DPLL_PER,
-	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-	.idlest_reg	= AM33XX_CM_IDLEST_DPLL_PER,
-	.mult_mask	= AM33XX_DPLL_MULT_PERIPH_MASK,
-	.div1_mask	= AM33XX_DPLL_PER_DIV_MASK,
-	.enable_mask	= AM33XX_DPLL_EN_MASK,
-	.idlest_mask	= AM33XX_ST_DPLL_CLK_MASK,
-	.max_multiplier	= 2047,
-	.max_divider	= 128,
-	.min_divider	= 1,
-	.flags		= DPLL_J_TYPE,
-};
-
-/* CLKDCOLDO */
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
-	.hw	= {
-		.clk	= &dpll_per_ck,
-	},
-	.dpll_data	= &dpll_per_dd,
-	.ops		= &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/* CLKOUT: fdpll/M2 */
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
-		   AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
-		   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
-		   NULL);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
-			&dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
-			&dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
-			&dpll_core_m4_ck, 0x0, 1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-			1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
-			8);
-
-/*
- * Below clock nodes describes clockdomains derived out
- * of core clock.
- */
-static const struct clk_ops clk_ops_null = {
-};
-
-static const char *l3_gclk_parents[] = {
-	"dpll_core_m4_ck"
-};
-
-static struct clk l3_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
-DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
-
-static struct clk l4hs_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
-DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
-
-static const char *l3s_gclk_parents[] = {
-	"dpll_core_m4_div2_ck"
-};
-
-static struct clk l3s_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
-DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4fw_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
-DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4ls_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
-DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk sysclk_div_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
-DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
-
-/*
- * In order to match the clock domain with hwmod clockdomain entry,
- * separate clock nodes is required for the modules which are
- * directly getting their funtioncal clock from sys_clkin.
- */
-static struct clk adc_tsc_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
-DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
-DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
-DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk sha0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
-DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk aes0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
-DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
-
-/*
- * Modules clock nodes
- *
- * The following clock leaf nodes are added for the moment because:
- *
- *  - hwmod data is not present for these modules, either hwmod
- *    control is not required or its not populated.
- *  - Driver code is not yet migrated to use hwmod/runtime pm
- *  - Modules outside kernel access (to disable them by default)
- *
- *     - mmu (gfx domain)
- *     - cefuse
- *     - usbotg_fck (its additional clock and not really a modulemode)
- *     - ieee5000
- */
-
-DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-		AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-		AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-		0x0, NULL);
-
-/*
- * clkdiv32 is generated from fixed division of 732.4219
- */
-DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
-
-static struct clk clkdiv32k_ick;
-
-static const char *clkdiv32k_ick_parent_names[] = {
-	"clkdiv32k_ck",
-};
-
-static const struct clk_ops clkdiv32k_ick_ops = {
-	.enable         = &omap2_dflt_clk_enable,
-	.disable        = &omap2_dflt_clk_disable,
-	.is_enabled     = &omap2_dflt_clk_is_enabled,
-	.init           = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap clkdiv32k_ick_hw = {
-	.hw	= {
-		.clk	= &clkdiv32k_ick,
-	},
-	.enable_reg	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
-	.enable_bit	= AM33XX_MODULEMODE_SWCTRL_SHIFT,
-	.clkdm_name	= "clk_24mhz_clkdm",
-};
-
-DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
-
-/* "usbotg_fck" is an additional clock and not really a modulemode */
-DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
-		AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
-		0x0, NULL);
-
-DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
-		0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
-		AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-/* Timers */
-static const struct clksel timer1_clkmux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
-	{ .parent = &tclkin_ck, .rates = div_1_2_rates },
-	{ .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
-	{ .parent = &clk_32768_ck, .rates = div_1_4_rates },
-	{ .parent = NULL },
-};
-
-static const char *timer1_ck_parents[] = {
-	"sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
-	"clk_32768_ck",
-};
-
-static struct clk timer1_fck;
-
-static const struct clk_ops timer1_fck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap timer1_fck_hw = {
-	.hw	= {
-		.clk	= &timer1_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer1_clkmux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER1MS_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_2_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
-
-static const struct clksel timer2_to_7_clk_sel[] = {
-	{ .parent = &tclkin_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_clkin_ck, .rates = div_1_1_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const char *timer2_to_7_ck_parents[] = {
-	"tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
-};
-
-static struct clk timer2_fck;
-
-static struct clk_hw_omap timer2_fck_hw = {
-	.hw	= {
-		.clk	= &timer2_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER2_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer3_fck;
-
-static struct clk_hw_omap timer3_fck_hw = {
-	.hw	= {
-		.clk	= &timer3_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER3_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer4_fck;
-
-static struct clk_hw_omap timer4_fck_hw = {
-	.hw	= {
-		.clk	= &timer4_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER4_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer5_fck;
-
-static struct clk_hw_omap timer5_fck_hw = {
-	.hw	= {
-		.clk	= &timer5_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER5_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer6_fck;
-
-static struct clk_hw_omap timer6_fck_hw = {
-	.hw	= {
-		.clk	= &timer6_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER6_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer7_fck;
-
-static struct clk_hw_omap timer7_fck_hw = {
-	.hw	= {
-		.clk	= &timer7_fck,
-	},
-	.clkdm_name	= "l4ls_clkdm",
-	.clksel		= timer2_to_7_clk_sel,
-	.clksel_reg	= AM33XX_CLKSEL_TIMER7_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
-			"dpll_core_m5_ck",
-			&dpll_core_m5_ck,
-			0x0,
-			1, 2);
-
-static const struct clk_ops cpsw_fck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-};
-
-static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
-	{ .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static const char *cpsw_cpts_rft_ck_parents[] = {
-	"dpll_core_m5_ck", "dpll_core_m4_ck",
-};
-
-static struct clk cpsw_cpts_rft_clk;
-
-static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
-	.hw	= {
-		.clk	= &cpsw_cpts_rft_clk,
-	},
-	.clkdm_name	= "cpsw_125mhz_clkdm",
-	.clksel		= cpsw_cpts_rft_clkmux_sel,
-	.clksel_reg	= AM33XX_CM_CPTS_RFT_CLKSEL,
-	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
-
-
-/* gpio */
-static const char *gpio0_ck_parents[] = {
-	"clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel gpio0_dbclk_mux_sel[] = {
-	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-	{ .parent = &clk_32768_ck, .rates = div_1_1_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static const struct clk_ops gpio_fck_ops = {
-	.recalc_rate	= &omap2_clksel_recalc,
-	.get_parent	= &omap2_clksel_find_parent_index,
-	.set_parent	= &omap2_clksel_set_parent,
-	.init		= &omap2_init_clk_clkdm,
-};
-
-static struct clk gpio0_dbclk_mux_ck;
-
-static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
-	.hw	= {
-		.clk	= &gpio0_dbclk_mux_ck,
-	},
-	.clkdm_name	= "l4_wkup_clkdm",
-	.clksel		= gpio0_dbclk_mux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_GPIO0_DBCLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
-
-DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
-		AM33XX_CM_WKUP_GPIO0_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-		AM33XX_CM_PER_GPIO1_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-		AM33XX_CM_PER_GPIO2_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-		AM33XX_CM_PER_GPIO3_CLKCTRL,
-		AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
-
-
-static const char *pruss_ck_parents[] = {
-	"l3_gclk", "dpll_disp_m2_ck",
-};
-
-static const struct clksel pruss_ocp_clk_mux_sel[] = {
-	{ .parent = &l3_gclk, .rates = div_1_0_rates },
-	{ .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk pruss_ocp_gclk;
-
-static struct clk_hw_omap pruss_ocp_gclk_hw = {
-	.hw	= {
-		.clk	= &pruss_ocp_gclk,
-	},
-	.clkdm_name	= "pruss_ocp_clkdm",
-	.clksel		= pruss_ocp_clk_mux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_PRUSS_OCP_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
-
-static const char *lcd_ck_parents[] = {
-	"dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel lcd_clk_mux_sel[] = {
-	{ .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
-	{ .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
-
-static struct clk lcd_gclk;
-
-static struct clk_hw_omap lcd_gclk_hw = {
-	.hw	= {
-		.clk	= &lcd_gclk,
-	},
-	.clkdm_name	= "lcdc_clkdm",
-	.clksel		= lcd_clk_mux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_LCDC_PIXEL_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
-			gpio_fck_ops, CLK_SET_RATE_PARENT);
-
-DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
-
-static const char *gfx_ck_parents[] = {
-	"dpll_core_m4_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel gfx_clksel_sel[] = {
-	{ .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk gfx_fclk_clksel_ck;
-
-static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
-	.hw	= {
-		.clk	= &gfx_fclk_clksel_ck,
-	},
-	.clksel		= gfx_clksel_sel,
-	.clksel_reg	= AM33XX_CLKSEL_GFX_FCLK,
-	.clksel_mask	= AM33XX_CLKSEL_GFX_FCLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
-
-static const struct clk_div_table div_1_0_2_1_rates[] = {
-	{ .div = 1, .val = 0, },
-	{ .div = 2, .val = 1, },
-	{ .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
-			 &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
-			 AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
-			 0x0, div_1_0_2_1_rates, NULL);
-
-static const char *sysclkout_ck_parents[] = {
-	"clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
-	"lcd_gclk",
-};
-
-static const struct clksel sysclkout_pre_sel[] = {
-	{ .parent = &clk_32768_ck, .rates = div_1_0_rates },
-	{ .parent = &l3_gclk, .rates = div_1_1_rates },
-	{ .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
-	{ .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
-	{ .parent = &lcd_gclk, .rates = div_1_4_rates },
-	{ .parent = NULL },
-};
-
-static struct clk sysclkout_pre_ck;
-
-static struct clk_hw_omap sysclkout_pre_ck_hw = {
-	.hw	= {
-		.clk	= &sysclkout_pre_ck,
-	},
-	.clksel		= sysclkout_pre_sel,
-	.clksel_reg	= AM33XX_CM_CLKOUT_CTRL,
-	.clksel_mask	= AM33XX_CLKOUT2SOURCE_MASK,
-};
-
-DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
-
-/* Divide by 8 clock rates with default clock is 1/1*/
-static const struct clk_div_table div8_rates[] = {
-	{ .div = 1, .val = 0, },
-	{ .div = 2, .val = 1, },
-	{ .div = 3, .val = 2, },
-	{ .div = 4, .val = 3, },
-	{ .div = 5, .val = 4, },
-	{ .div = 6, .val = 5, },
-	{ .div = 7, .val = 6, },
-	{ .div = 8, .val = 7, },
-	{ .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
-			 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
-			 AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
-
-DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
-		AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
-
-static const char *wdt_ck_parents[] = {
-	"clk_rc32k_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel wdt_clkmux_sel[] = {
-	{ .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-	{ .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk wdt1_fck;
-
-static struct clk_hw_omap wdt1_fck_hw = {
-	.hw	= {
-		.clk	= &wdt1_fck,
-	},
-	.clkdm_name	= "l4_wkup_clkdm",
-	.clksel		= wdt_clkmux_sel,
-	.clksel_reg	= AM33XX_CLKSEL_WDT1_CLK,
-	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
-
-static const char *pwmss_clk_parents[] = {
-	"dpll_per_m2_ck",
-};
-
-static const struct clk_ops ehrpwm_tbclk_ops = {
-	.enable		= &omap2_dflt_clk_enable,
-	.disable	= &omap2_dflt_clk_disable,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
-			 NULL, NULL, 0,
-			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-			 AM33XX_PWMSS0_TBCLKEN_SHIFT,
-			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
-			 NULL, NULL, 0,
-			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-			 AM33XX_PWMSS1_TBCLKEN_SHIFT,
-			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
-			 NULL, NULL, 0,
-			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-			 AM33XX_PWMSS2_TBCLKEN_SHIFT,
-			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-/*
- * debugss optional clocks
- */
-DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
-		0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
-		0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
-
-static const char *stm_pmd_clock_mux_ck_parents[] = {
-	"dbg_sysclk_ck", "dbg_clka_ck",
-};
-
-DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
-	       AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
-	       AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
-	       AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-	       AM33XX_TRC_PMD_CLKSEL_SHIFT,
-	       AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
-		   &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		   AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
-		   AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
-		   &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-		   AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
-		   AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-		   NULL);
-
-/*
- * clkdev
- */
-static struct omap_clk am33xx_clks[] = {
-	CLK(NULL,	"clk_32768_ck",		&clk_32768_ck),
-	CLK(NULL,	"clk_rc32k_ck",		&clk_rc32k_ck),
-	CLK(NULL,	"virt_19200000_ck",	&virt_19200000_ck),
-	CLK(NULL,	"virt_24000000_ck",	&virt_24000000_ck),
-	CLK(NULL,	"virt_25000000_ck",	&virt_25000000_ck),
-	CLK(NULL,	"virt_26000000_ck",	&virt_26000000_ck),
-	CLK(NULL,	"sys_clkin_ck",		&sys_clkin_ck),
-	CLK(NULL,	"tclkin_ck",		&tclkin_ck),
-	CLK(NULL,	"dpll_core_ck",		&dpll_core_ck),
-	CLK(NULL,	"dpll_core_x2_ck",	&dpll_core_x2_ck),
-	CLK(NULL,	"dpll_core_m4_ck",	&dpll_core_m4_ck),
-	CLK(NULL,	"dpll_core_m5_ck",	&dpll_core_m5_ck),
-	CLK(NULL,	"dpll_core_m6_ck",	&dpll_core_m6_ck),
-	CLK(NULL,	"dpll_mpu_ck",		&dpll_mpu_ck),
-	CLK("cpu0",	NULL,			&dpll_mpu_ck),
-	CLK(NULL,	"dpll_mpu_m2_ck",	&dpll_mpu_m2_ck),
-	CLK(NULL,	"dpll_ddr_ck",		&dpll_ddr_ck),
-	CLK(NULL,	"dpll_ddr_m2_ck",	&dpll_ddr_m2_ck),
-	CLK(NULL,	"dpll_ddr_m2_div2_ck",	&dpll_ddr_m2_div2_ck),
-	CLK(NULL,	"dpll_disp_ck",		&dpll_disp_ck),
-	CLK(NULL,	"dpll_disp_m2_ck",	&dpll_disp_m2_ck),
-	CLK(NULL,	"dpll_per_ck",		&dpll_per_ck),
-	CLK(NULL,	"dpll_per_m2_ck",	&dpll_per_m2_ck),
-	CLK(NULL,	"dpll_per_m2_div4_wkupdm_ck",	&dpll_per_m2_div4_wkupdm_ck),
-	CLK(NULL,	"dpll_per_m2_div4_ck",	&dpll_per_m2_div4_ck),
-	CLK(NULL,	"adc_tsc_fck",		&adc_tsc_fck),
-	CLK(NULL,	"cefuse_fck",		&cefuse_fck),
-	CLK(NULL,	"clkdiv32k_ck",		&clkdiv32k_ck),
-	CLK(NULL,	"clkdiv32k_ick",	&clkdiv32k_ick),
-	CLK(NULL,	"dcan0_fck",		&dcan0_fck),
-	CLK("481cc000.d_can",	NULL,		&dcan0_fck),
-	CLK(NULL,	"dcan1_fck",		&dcan1_fck),
-	CLK("481d0000.d_can",	NULL,		&dcan1_fck),
-	CLK(NULL,	"pruss_ocp_gclk",	&pruss_ocp_gclk),
-	CLK(NULL,	"mcasp0_fck",		&mcasp0_fck),
-	CLK(NULL,	"mcasp1_fck",		&mcasp1_fck),
-	CLK(NULL,	"mmu_fck",		&mmu_fck),
-	CLK(NULL,	"smartreflex0_fck",	&smartreflex0_fck),
-	CLK(NULL,	"smartreflex1_fck",	&smartreflex1_fck),
-	CLK(NULL,	"sha0_fck",		&sha0_fck),
-	CLK(NULL,	"aes0_fck",		&aes0_fck),
-	CLK(NULL,	"timer1_fck",		&timer1_fck),
-	CLK(NULL,	"timer2_fck",		&timer2_fck),
-	CLK(NULL,	"timer3_fck",		&timer3_fck),
-	CLK(NULL,	"timer4_fck",		&timer4_fck),
-	CLK(NULL,	"timer5_fck",		&timer5_fck),
-	CLK(NULL,	"timer6_fck",		&timer6_fck),
-	CLK(NULL,	"timer7_fck",		&timer7_fck),
-	CLK(NULL,	"usbotg_fck",		&usbotg_fck),
-	CLK(NULL,	"ieee5000_fck",		&ieee5000_fck),
-	CLK(NULL,	"wdt1_fck",		&wdt1_fck),
-	CLK(NULL,	"l4_rtc_gclk",		&l4_rtc_gclk),
-	CLK(NULL,	"l3_gclk",		&l3_gclk),
-	CLK(NULL,	"dpll_core_m4_div2_ck",	&dpll_core_m4_div2_ck),
-	CLK(NULL,	"l4hs_gclk",		&l4hs_gclk),
-	CLK(NULL,	"l3s_gclk",		&l3s_gclk),
-	CLK(NULL,	"l4fw_gclk",		&l4fw_gclk),
-	CLK(NULL,	"l4ls_gclk",		&l4ls_gclk),
-	CLK(NULL,	"clk_24mhz",		&clk_24mhz),
-	CLK(NULL,	"sysclk_div_ck",	&sysclk_div_ck),
-	CLK(NULL,	"cpsw_125mhz_gclk",	&cpsw_125mhz_gclk),
-	CLK(NULL,	"cpsw_cpts_rft_clk",	&cpsw_cpts_rft_clk),
-	CLK(NULL,	"gpio0_dbclk_mux_ck",	&gpio0_dbclk_mux_ck),
-	CLK(NULL,	"gpio0_dbclk",		&gpio0_dbclk),
-	CLK(NULL,	"gpio1_dbclk",		&gpio1_dbclk),
-	CLK(NULL,	"gpio2_dbclk",		&gpio2_dbclk),
-	CLK(NULL,	"gpio3_dbclk",		&gpio3_dbclk),
-	CLK(NULL,	"lcd_gclk",		&lcd_gclk),
-	CLK(NULL,	"mmc_clk",		&mmc_clk),
-	CLK(NULL,	"gfx_fclk_clksel_ck",	&gfx_fclk_clksel_ck),
-	CLK(NULL,	"gfx_fck_div_ck",	&gfx_fck_div_ck),
-	CLK(NULL,	"sysclkout_pre_ck",	&sysclkout_pre_ck),
-	CLK(NULL,	"clkout2_div_ck",	&clkout2_div_ck),
-	CLK(NULL,	"timer_32k_ck",		&clkdiv32k_ick),
-	CLK(NULL,	"timer_sys_ck",		&sys_clkin_ck),
-	CLK(NULL,	"dbg_sysclk_ck",	&dbg_sysclk_ck),
-	CLK(NULL,	"dbg_clka_ck",		&dbg_clka_ck),
-	CLK(NULL,	"stm_pmd_clock_mux_ck",	&stm_pmd_clock_mux_ck),
-	CLK(NULL,	"trace_pmd_clk_mux_ck",	&trace_pmd_clk_mux_ck),
-	CLK(NULL,	"stm_clk_div_ck",	&stm_clk_div_ck),
-	CLK(NULL,	"trace_clk_div_ck",	&trace_clk_div_ck),
-	CLK(NULL,	"clkout2_ck",		&clkout2_ck),
-	CLK("48300200.ehrpwm",	"tbclk",	&ehrpwm0_tbclk),
-	CLK("48302200.ehrpwm",	"tbclk",	&ehrpwm1_tbclk),
-	CLK("48304200.ehrpwm",	"tbclk",	&ehrpwm2_tbclk),
-};
-
-
-static const char *enable_init_clks[] = {
-	"dpll_ddr_m2_ck",
-	"dpll_mpu_m2_ck",
-	"l3_gclk",
-	"l4hs_gclk",
-	"l4fw_gclk",
-	"l4ls_gclk",
-	"clkout2_ck",	/* Required for external peripherals like, Audio codecs */
-};
-
-int __init am33xx_clk_init(void)
-{
-	if (soc_is_am33xx())
-		cpu_mask = RATE_IN_AM33XX;
-
-	omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
-
-	omap2_clk_disable_autoidle_all();
-
-	omap2_clk_enable_init_clocks(enable_init_clks,
-				     ARRAY_SIZE(enable_init_clks));
-
-	/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
-	 *    physically present, in such a case HWMOD enabling of
-	 *    clock would be failure with default parent. And timer
-	 *    probe thinks clock is already enabled, this leads to
-	 *    crash upon accessing timer 3 & 6 registers in probe.
-	 *    Fix by setting parent of both these timers to master
-	 *    oscillator clock.
-	 */
-
-	clk_set_parent(&timer3_fck, &sys_clkin_ck);
-	clk_set_parent(&timer6_fck, &sys_clkin_ck);
-	/*
-	 * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
-	 * the design/spec, so as a result, for example, timer which supposed
-	 * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
-	 * not expected by any use-case, so change WDT1 clock source to PRCM
-	 * 32KHz clock.
-	 */
-	clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
-
-	return 0;
-}
diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index b8dbfda..c4e8825 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1,2 +1,3 @@
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
-					   clk-44xx.o clk-54xx.o clk-7xx.o
+					   clk-44xx.o clk-54xx.o clk-7xx.o \
+					   clk-33xx.o
-- 
1.7.9.5

[PATCHv4 21/33] CLK: OMAP: DPLL: add omap3 dpll support

[Tero Kristo]

OMAP3 has slightly different DPLLs from those compared to OMAP4. Modified
code for the same.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/dpll.c |   96 +++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 85 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
index d8a958a..ecb1fbd 100644
--- a/drivers/clk/omap/dpll.c
+++ b/drivers/clk/omap/dpll.c
@@ -26,6 +26,11 @@
 #include <linux/of_address.h>
 #include <linux/clk/omap.h>
 
+enum {
+	SUBTYPE_OMAP3_DPLL,
+	SUBTYPE_OMAP4_DPLL,
+};
+
 static const struct clk_ops dpll_m4xen_ck_ops = {
 	.enable		= &omap3_noncore_dpll_enable,
 	.disable	= &omap3_noncore_dpll_disable,
@@ -40,6 +45,13 @@ static const struct clk_ops dpll_core_ck_ops = {
 	.get_parent	= &omap2_init_dpll_parent,
 };
 
+static const struct clk_ops omap3_dpll_core_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.round_rate	= &omap2_dpll_round_rate,
+};
+
 static const struct clk_ops dpll_ck_ops = {
 	.enable		= &omap3_noncore_dpll_enable,
 	.disable	= &omap3_noncore_dpll_disable,
@@ -50,6 +62,26 @@ static const struct clk_ops dpll_ck_ops = {
 	.init		= &omap2_init_clk_clkdm,
 };
 
+static const struct clk_ops omap3_dpll_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.round_rate	= &omap2_dpll_round_rate,
+};
+
+static const struct clk_ops omap3_dpll_per_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.set_rate	= &omap3_dpll4_set_rate,
+	.round_rate	= &omap2_dpll_round_rate,
+};
+
 static const struct clk_ops dpll_x2_ck_ops = {
 	.recalc_rate	= &omap3_clkoutx2_recalc,
 };
@@ -144,7 +176,9 @@ struct clk *omap_clk_register_dpll_x2(struct device *dev, const char *name,
  * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
  */
 static void __init of_omap_dpll_setup(struct device_node *node,
-					const struct clk_ops *ops)
+					const struct clk_ops *ops, u32 freqsel,
+					u32 modes, u8 mul_div_shift,
+					int subtype)
 {
 	struct clk *clk;
 	const char *clk_name = node->name;
@@ -157,8 +191,8 @@ static void __init of_omap_dpll_setup(struct device_node *node,
 	u32 idlest_mask = 0x1;
 	u32 enable_mask = 0x7;
 	u32 autoidle_mask = 0x7;
-	u32 mult_mask = 0x7ff << 8;
-	u32 div1_mask = 0x7f;
+	u32 mult_mask = 0x7ff << (8 + mul_div_shift);
+	u32 div1_mask = 0x7f << mul_div_shift;
 	u32 max_multiplier = 2047;
 	u32 max_divider = 128;
 	u32 min_divider = 1;
@@ -193,7 +227,7 @@ static void __init of_omap_dpll_setup(struct device_node *node,
 
 	clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
 	dd->clk_ref = of_clk_get_from_provider(&clkspec);
-	if (!dd->clk_ref) {
+	if (IS_ERR(dd->clk_ref)) {
 		pr_err("%s: ti,clk-ref for %s not found\n", __func__,
 			clk_name);
 		goto cleanup;
@@ -201,7 +235,7 @@ static void __init of_omap_dpll_setup(struct device_node *node,
 
 	clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
 	dd->clk_bypass = of_clk_get_from_provider(&clkspec);
-	if (!dd->clk_bypass) {
+	if (IS_ERR(dd->clk_bypass)) {
 		pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
 			clk_name);
 		goto cleanup;
@@ -225,14 +259,31 @@ static void __init of_omap_dpll_setup(struct device_node *node,
 	dd->enable_mask = enable_mask;
 	dd->autoidle_mask = autoidle_mask;
 
-	dd->modes = 0xa0;
+	if (!of_property_read_u32(node, "ti,recal-en-bit", &val))
+		dd->recal_en_bit = val;
+
+	if (!of_property_read_u32(node, "ti,recal-st-bit", &val))
+		dd->recal_st_bit = val;
+
+	if (!of_property_read_u32(node, "ti,auto-recal-bit", &val))
+		dd->auto_recal_bit = val;
+
+	of_property_read_u32(node, "ti,modes", &modes);
+
+	dd->modes = modes;
+
+	dd->freqsel_mask = freqsel;
 
 	if (of_property_read_bool(node, "ti,dpll-j-type")) {
 		dd->sddiv_mask = 0xff000000;
-		mult_mask = 0xfff << 8;
-		div1_mask = 0xff;
+		mult_mask = 0xfff << (8 + mul_div_shift);
 		max_multiplier = 4095;
-		max_divider = 256;
+		if (subtype == SUBTYPE_OMAP3_DPLL) {
+			dd->dco_mask = 0xe00000;
+		} else {
+			div1_mask = 0xff << mul_div_shift;
+			max_divider = 256;
+		}
 	}
 
 	if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
@@ -281,7 +332,30 @@ static void __init of_omap_dpll_x2_setup(struct device_node *node)
 
 __init void of_omap3_dpll_setup(struct device_node *node)
 {
-	/* XXX: to be done */
+	const struct clk_ops *ops;
+	u32 freqsel = 0xf0;
+	u32 modes = 0xa0;
+	u8 mul_div_shift = 0;
+
+	ops = &omap3_dpll_ck_ops;
+
+	if (of_property_read_bool(node, "ti,dpll-core")) {
+		ops = &omap3_dpll_core_ck_ops;
+		mul_div_shift = 8;
+		modes = 0x0;
+	}
+
+	if (of_property_read_bool(node, "ti,dpll-peripheral")) {
+		ops = &omap3_dpll_per_ck_ops;
+		freqsel = 0xf00000;
+	}
+
+	if (of_property_read_bool(node, "ti,dpll-j-type"))
+		freqsel = 0x0;
+
+	of_omap_dpll_setup(node, ops, freqsel, modes, mul_div_shift,
+		SUBTYPE_OMAP3_DPLL);
+
 }
 EXPORT_SYMBOL_GPL(of_omap3_dpll_setup);
 CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock", of_omap3_dpll_setup);
@@ -306,7 +380,7 @@ __init void of_omap4_dpll_setup(struct device_node *node)
 	if (of_property_read_bool(node, "ti,dpll-no-gate"))
 		ops = &dpll_no_gate_ck_ops;
 
-	of_omap_dpll_setup(node, ops);
+	of_omap_dpll_setup(node, ops, 0, 0xa0, 0, SUBTYPE_OMAP4_DPLL);
 }
 EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
 CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock", of_omap4_dpll_setup);
-- 
1.7.9.5

[PATCHv4 21/33] CLK: OMAP: DPLL: add omap3 dpll support

[Tero Kristo]

OMAP3 has slightly different DPLLs from those compared to OMAP4. Modified
code for the same.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/dpll.c |   96 +++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 85 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
index d8a958a..ecb1fbd 100644
--- a/drivers/clk/omap/dpll.c
+++ b/drivers/clk/omap/dpll.c
@@ -26,6 +26,11 @@
 #include <linux/of_address.h>
 #include <linux/clk/omap.h>
 
+enum {
+	SUBTYPE_OMAP3_DPLL,
+	SUBTYPE_OMAP4_DPLL,
+};
+
 static const struct clk_ops dpll_m4xen_ck_ops = {
 	.enable		= &omap3_noncore_dpll_enable,
 	.disable	= &omap3_noncore_dpll_disable,
@@ -40,6 +45,13 @@ static const struct clk_ops dpll_core_ck_ops = {
 	.get_parent	= &omap2_init_dpll_parent,
 };
 
+static const struct clk_ops omap3_dpll_core_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.round_rate	= &omap2_dpll_round_rate,
+};
+
 static const struct clk_ops dpll_ck_ops = {
 	.enable		= &omap3_noncore_dpll_enable,
 	.disable	= &omap3_noncore_dpll_disable,
@@ -50,6 +62,26 @@ static const struct clk_ops dpll_ck_ops = {
 	.init		= &omap2_init_clk_clkdm,
 };
 
+static const struct clk_ops omap3_dpll_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.round_rate	= &omap2_dpll_round_rate,
+};
+
+static const struct clk_ops omap3_dpll_per_ck_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.set_rate	= &omap3_dpll4_set_rate,
+	.round_rate	= &omap2_dpll_round_rate,
+};
+
 static const struct clk_ops dpll_x2_ck_ops = {
 	.recalc_rate	= &omap3_clkoutx2_recalc,
 };
@@ -144,7 +176,9 @@ struct clk *omap_clk_register_dpll_x2(struct device *dev, const char *name,
  * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
  */
 static void __init of_omap_dpll_setup(struct device_node *node,
-					const struct clk_ops *ops)
+					const struct clk_ops *ops, u32 freqsel,
+					u32 modes, u8 mul_div_shift,
+					int subtype)
 {
 	struct clk *clk;
 	const char *clk_name = node->name;
@@ -157,8 +191,8 @@ static void __init of_omap_dpll_setup(struct device_node *node,
 	u32 idlest_mask = 0x1;
 	u32 enable_mask = 0x7;
 	u32 autoidle_mask = 0x7;
-	u32 mult_mask = 0x7ff << 8;
-	u32 div1_mask = 0x7f;
+	u32 mult_mask = 0x7ff << (8 + mul_div_shift);
+	u32 div1_mask = 0x7f << mul_div_shift;
 	u32 max_multiplier = 2047;
 	u32 max_divider = 128;
 	u32 min_divider = 1;
@@ -193,7 +227,7 @@ static void __init of_omap_dpll_setup(struct device_node *node,
 
 	clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
 	dd->clk_ref = of_clk_get_from_provider(&clkspec);
-	if (!dd->clk_ref) {
+	if (IS_ERR(dd->clk_ref)) {
 		pr_err("%s: ti,clk-ref for %s not found\n", __func__,
 			clk_name);
 		goto cleanup;
@@ -201,7 +235,7 @@ static void __init of_omap_dpll_setup(struct device_node *node,
 
 	clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
 	dd->clk_bypass = of_clk_get_from_provider(&clkspec);
-	if (!dd->clk_bypass) {
+	if (IS_ERR(dd->clk_bypass)) {
 		pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
 			clk_name);
 		goto cleanup;
@@ -225,14 +259,31 @@ static void __init of_omap_dpll_setup(struct device_node *node,
 	dd->enable_mask = enable_mask;
 	dd->autoidle_mask = autoidle_mask;
 
-	dd->modes = 0xa0;
+	if (!of_property_read_u32(node, "ti,recal-en-bit", &val))
+		dd->recal_en_bit = val;
+
+	if (!of_property_read_u32(node, "ti,recal-st-bit", &val))
+		dd->recal_st_bit = val;
+
+	if (!of_property_read_u32(node, "ti,auto-recal-bit", &val))
+		dd->auto_recal_bit = val;
+
+	of_property_read_u32(node, "ti,modes", &modes);
+
+	dd->modes = modes;
+
+	dd->freqsel_mask = freqsel;
 
 	if (of_property_read_bool(node, "ti,dpll-j-type")) {
 		dd->sddiv_mask = 0xff000000;
-		mult_mask = 0xfff << 8;
-		div1_mask = 0xff;
+		mult_mask = 0xfff << (8 + mul_div_shift);
 		max_multiplier = 4095;
-		max_divider = 256;
+		if (subtype == SUBTYPE_OMAP3_DPLL) {
+			dd->dco_mask = 0xe00000;
+		} else {
+			div1_mask = 0xff << mul_div_shift;
+			max_divider = 256;
+		}
 	}
 
 	if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
@@ -281,7 +332,30 @@ static void __init of_omap_dpll_x2_setup(struct device_node *node)
 
 __init void of_omap3_dpll_setup(struct device_node *node)
 {
-	/* XXX: to be done */
+	const struct clk_ops *ops;
+	u32 freqsel = 0xf0;
+	u32 modes = 0xa0;
+	u8 mul_div_shift = 0;
+
+	ops = &omap3_dpll_ck_ops;
+
+	if (of_property_read_bool(node, "ti,dpll-core")) {
+		ops = &omap3_dpll_core_ck_ops;
+		mul_div_shift = 8;
+		modes = 0x0;
+	}
+
+	if (of_property_read_bool(node, "ti,dpll-peripheral")) {
+		ops = &omap3_dpll_per_ck_ops;
+		freqsel = 0xf00000;
+	}
+
+	if (of_property_read_bool(node, "ti,dpll-j-type"))
+		freqsel = 0x0;
+
+	of_omap_dpll_setup(node, ops, freqsel, modes, mul_div_shift,
+		SUBTYPE_OMAP3_DPLL);
+
 }
 EXPORT_SYMBOL_GPL(of_omap3_dpll_setup);
 CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock", of_omap3_dpll_setup);
@@ -306,7 +380,7 @@ __init void of_omap4_dpll_setup(struct device_node *node)
 	if (of_property_read_bool(node, "ti,dpll-no-gate"))
 		ops = &dpll_no_gate_ck_ops;
 
-	of_omap_dpll_setup(node, ops);
+	of_omap_dpll_setup(node, ops, 0, 0xa0, 0, SUBTYPE_OMAP4_DPLL);
 }
 EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
 CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock", of_omap4_dpll_setup);
-- 
1.7.9.5

Re: [PATCHv4 21/33] CLK: OMAP: DPLL: add omap3 dpll support

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> OMAP3 has slightly different DPLLs from those compared to OMAP4. Modified
> code for the same.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/dpll.c |   96 +++++++++++++++++++++++++++++++++++++++++------
>   1 file changed, 85 insertions(+), 11 deletions(-)
>
:) wont repeat the binding crib again..

> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
> index d8a958a..ecb1fbd 100644
> --- a/drivers/clk/omap/dpll.c
> +++ b/drivers/clk/omap/dpll.c
> @@ -26,6 +26,11 @@
>   #include <linux/of_address.h>
>   #include <linux/clk/omap.h>
>
> +enum {
> +	SUBTYPE_OMAP3_DPLL,
> +	SUBTYPE_OMAP4_DPLL,
> +};
> +
>   static const struct clk_ops dpll_m4xen_ck_ops = {
>   	.enable		= &omap3_noncore_dpll_enable,
>   	.disable	= &omap3_noncore_dpll_disable,
> @@ -40,6 +45,13 @@ static const struct clk_ops dpll_core_ck_ops = {
>   	.get_parent	= &omap2_init_dpll_parent,
>   };
>
> +static const struct clk_ops omap3_dpll_core_ck_ops = {
> +	.init		= &omap2_init_clk_clkdm,
> +	.get_parent	= &omap2_init_dpll_parent,
> +	.recalc_rate	= &omap3_dpll_recalc,
> +	.round_rate	= &omap2_dpll_round_rate,
> +};
> +
>   static const struct clk_ops dpll_ck_ops = {
>   	.enable		= &omap3_noncore_dpll_enable,
>   	.disable	= &omap3_noncore_dpll_disable,
> @@ -50,6 +62,26 @@ static const struct clk_ops dpll_ck_ops = {
>   	.init		= &omap2_init_clk_clkdm,
>   };
>
> +static const struct clk_ops omap3_dpll_ck_ops = {
> +	.init		= &omap2_init_clk_clkdm,
> +	.enable		= &omap3_noncore_dpll_enable,
> +	.disable	= &omap3_noncore_dpll_disable,
> +	.get_parent	= &omap2_init_dpll_parent,
> +	.recalc_rate	= &omap3_dpll_recalc,
> +	.set_rate	= &omap3_noncore_dpll_set_rate,
> +	.round_rate	= &omap2_dpll_round_rate,
> +};
> +
> +static const struct clk_ops omap3_dpll_per_ck_ops = {
> +	.init		= &omap2_init_clk_clkdm,
> +	.enable		= &omap3_noncore_dpll_enable,
> +	.disable	= &omap3_noncore_dpll_disable,
> +	.get_parent	= &omap2_init_dpll_parent,
> +	.recalc_rate	= &omap3_dpll_recalc,
> +	.set_rate	= &omap3_dpll4_set_rate,
> +	.round_rate	= &omap2_dpll_round_rate,
> +};
> +
>   static const struct clk_ops dpll_x2_ck_ops = {
>   	.recalc_rate	= &omap3_clkoutx2_recalc,
>   };
> @@ -144,7 +176,9 @@ struct clk *omap_clk_register_dpll_x2(struct device *dev, const char *name,
>    * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
>    */
>   static void __init of_omap_dpll_setup(struct device_node *node,
> -					const struct clk_ops *ops)
> +					const struct clk_ops *ops, u32 freqsel,
> +					u32 modes, u8 mul_div_shift,
> +					int subtype)
>   {
>   	struct clk *clk;
>   	const char *clk_name = node->name;
> @@ -157,8 +191,8 @@ static void __init of_omap_dpll_setup(struct device_node *node,
>   	u32 idlest_mask = 0x1;
>   	u32 enable_mask = 0x7;
>   	u32 autoidle_mask = 0x7;
> -	u32 mult_mask = 0x7ff << 8;
> -	u32 div1_mask = 0x7f;
> +	u32 mult_mask = 0x7ff << (8 + mul_div_shift);
> +	u32 div1_mask = 0x7f << mul_div_shift;
>   	u32 max_multiplier = 2047;
>   	u32 max_divider = 128;
>   	u32 min_divider = 1;
> @@ -193,7 +227,7 @@ static void __init of_omap_dpll_setup(struct device_node *node,
>
>   	clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
>   	dd->clk_ref = of_clk_get_from_provider(&clkspec);
> -	if (!dd->clk_ref) {
> +	if (IS_ERR(dd->clk_ref)) {

belongs to original patch.

>   		pr_err("%s: ti,clk-ref for %s not found\n", __func__,
>   			clk_name);
>   		goto cleanup;
> @@ -201,7 +235,7 @@ static void __init of_omap_dpll_setup(struct device_node *node,
>
>   	clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
>   	dd->clk_bypass = of_clk_get_from_provider(&clkspec);
> -	if (!dd->clk_bypass) {
> +	if (IS_ERR(dd->clk_bypass)) {

same

>   		pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
>   			clk_name);
>   		goto cleanup;
> @@ -225,14 +259,31 @@ static void __init of_omap_dpll_setup(struct device_node *node,
>   	dd->enable_mask = enable_mask;
>   	dd->autoidle_mask = autoidle_mask;
>
> -	dd->modes = 0xa0;
> +	if (!of_property_read_u32(node, "ti,recal-en-bit", &val))
> +		dd->recal_en_bit = val;
> +
> +	if (!of_property_read_u32(node, "ti,recal-st-bit", &val))
> +		dd->recal_st_bit = val;
> +
> +	if (!of_property_read_u32(node, "ti,auto-recal-bit", &val))
> +		dd->auto_recal_bit = val;

now I understand what it means.

> +
> +	of_property_read_u32(node, "ti,modes", &modes);
i see we pass in modes, and read ti,modes to &modes. it is a bit sketchy 
without bindings documentation.

> +
> +	dd->modes = modes;

Should have belonged to original patch.

> +
> +	dd->freqsel_mask = freqsel;
>
>   	if (of_property_read_bool(node, "ti,dpll-j-type")) {
>   		dd->sddiv_mask = 0xff000000;
> -		mult_mask = 0xfff << 8;
> -		div1_mask = 0xff;
> +		mult_mask = 0xfff << (8 + mul_div_shift);
>   		max_multiplier = 4095;
> -		max_divider = 256;
> +		if (subtype == SUBTYPE_OMAP3_DPLL) {
> +			dd->dco_mask = 0xe00000;
> +		} else {
> +			div1_mask = 0xff << mul_div_shift;
> +			max_divider = 256;
> +		}
>   	}
>
>   	if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
> @@ -281,7 +332,30 @@ static void __init of_omap_dpll_x2_setup(struct device_node *node)
>
>   __init void of_omap3_dpll_setup(struct device_node *node)
>   {
> -	/* XXX: to be done */
> +	const struct clk_ops *ops;
> +	u32 freqsel = 0xf0;
> +	u32 modes = 0xa0;
> +	u8 mul_div_shift = 0;
> +
> +	ops = &omap3_dpll_ck_ops;
> +
> +	if (of_property_read_bool(node, "ti,dpll-core")) {
> +		ops = &omap3_dpll_core_ck_ops;
> +		mul_div_shift = 8;
> +		modes = 0x0;
> +	}
> +
> +	if (of_property_read_bool(node, "ti,dpll-peripheral")) {
> +		ops = &omap3_dpll_per_ck_ops;
> +		freqsel = 0xf00000;
> +	}
> +
> +	if (of_property_read_bool(node, "ti,dpll-j-type"))
> +		freqsel = 0x0;
> +
> +	of_omap_dpll_setup(node, ops, freqsel, modes, mul_div_shift,
> +		SUBTYPE_OMAP3_DPLL);
> +
>   }
>   EXPORT_SYMBOL_GPL(of_omap3_dpll_setup);
>   CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock", of_omap3_dpll_setup);
> @@ -306,7 +380,7 @@ __init void of_omap4_dpll_setup(struct device_node *node)
>   	if (of_property_read_bool(node, "ti,dpll-no-gate"))
>   		ops = &dpll_no_gate_ck_ops;
>
> -	of_omap_dpll_setup(node, ops);
> +	of_omap_dpll_setup(node, ops, 0, 0xa0, 0, SUBTYPE_OMAP4_DPLL);
what is 0xa0?

>   }
>   EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>   CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock", of_omap4_dpll_setup);
>

I think this should be squashed and a single dpll.c introduction to be done.


-- 
Regards,
Nishanth Menon

[PATCHv4 21/33] CLK: OMAP: DPLL: add omap3 dpll support

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> OMAP3 has slightly different DPLLs from those compared to OMAP4. Modified
> code for the same.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/dpll.c |   96 +++++++++++++++++++++++++++++++++++++++++------
>   1 file changed, 85 insertions(+), 11 deletions(-)
>
:) wont repeat the binding crib again..

> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
> index d8a958a..ecb1fbd 100644
> --- a/drivers/clk/omap/dpll.c
> +++ b/drivers/clk/omap/dpll.c
> @@ -26,6 +26,11 @@
>   #include <linux/of_address.h>
>   #include <linux/clk/omap.h>
>
> +enum {
> +	SUBTYPE_OMAP3_DPLL,
> +	SUBTYPE_OMAP4_DPLL,
> +};
> +
>   static const struct clk_ops dpll_m4xen_ck_ops = {
>   	.enable		= &omap3_noncore_dpll_enable,
>   	.disable	= &omap3_noncore_dpll_disable,
> @@ -40,6 +45,13 @@ static const struct clk_ops dpll_core_ck_ops = {
>   	.get_parent	= &omap2_init_dpll_parent,
>   };
>
> +static const struct clk_ops omap3_dpll_core_ck_ops = {
> +	.init		= &omap2_init_clk_clkdm,
> +	.get_parent	= &omap2_init_dpll_parent,
> +	.recalc_rate	= &omap3_dpll_recalc,
> +	.round_rate	= &omap2_dpll_round_rate,
> +};
> +
>   static const struct clk_ops dpll_ck_ops = {
>   	.enable		= &omap3_noncore_dpll_enable,
>   	.disable	= &omap3_noncore_dpll_disable,
> @@ -50,6 +62,26 @@ static const struct clk_ops dpll_ck_ops = {
>   	.init		= &omap2_init_clk_clkdm,
>   };
>
> +static const struct clk_ops omap3_dpll_ck_ops = {
> +	.init		= &omap2_init_clk_clkdm,
> +	.enable		= &omap3_noncore_dpll_enable,
> +	.disable	= &omap3_noncore_dpll_disable,
> +	.get_parent	= &omap2_init_dpll_parent,
> +	.recalc_rate	= &omap3_dpll_recalc,
> +	.set_rate	= &omap3_noncore_dpll_set_rate,
> +	.round_rate	= &omap2_dpll_round_rate,
> +};
> +
> +static const struct clk_ops omap3_dpll_per_ck_ops = {
> +	.init		= &omap2_init_clk_clkdm,
> +	.enable		= &omap3_noncore_dpll_enable,
> +	.disable	= &omap3_noncore_dpll_disable,
> +	.get_parent	= &omap2_init_dpll_parent,
> +	.recalc_rate	= &omap3_dpll_recalc,
> +	.set_rate	= &omap3_dpll4_set_rate,
> +	.round_rate	= &omap2_dpll_round_rate,
> +};
> +
>   static const struct clk_ops dpll_x2_ck_ops = {
>   	.recalc_rate	= &omap3_clkoutx2_recalc,
>   };
> @@ -144,7 +176,9 @@ struct clk *omap_clk_register_dpll_x2(struct device *dev, const char *name,
>    * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
>    */
>   static void __init of_omap_dpll_setup(struct device_node *node,
> -					const struct clk_ops *ops)
> +					const struct clk_ops *ops, u32 freqsel,
> +					u32 modes, u8 mul_div_shift,
> +					int subtype)
>   {
>   	struct clk *clk;
>   	const char *clk_name = node->name;
> @@ -157,8 +191,8 @@ static void __init of_omap_dpll_setup(struct device_node *node,
>   	u32 idlest_mask = 0x1;
>   	u32 enable_mask = 0x7;
>   	u32 autoidle_mask = 0x7;
> -	u32 mult_mask = 0x7ff << 8;
> -	u32 div1_mask = 0x7f;
> +	u32 mult_mask = 0x7ff << (8 + mul_div_shift);
> +	u32 div1_mask = 0x7f << mul_div_shift;
>   	u32 max_multiplier = 2047;
>   	u32 max_divider = 128;
>   	u32 min_divider = 1;
> @@ -193,7 +227,7 @@ static void __init of_omap_dpll_setup(struct device_node *node,
>
>   	clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
>   	dd->clk_ref = of_clk_get_from_provider(&clkspec);
> -	if (!dd->clk_ref) {
> +	if (IS_ERR(dd->clk_ref)) {

belongs to original patch.

>   		pr_err("%s: ti,clk-ref for %s not found\n", __func__,
>   			clk_name);
>   		goto cleanup;
> @@ -201,7 +235,7 @@ static void __init of_omap_dpll_setup(struct device_node *node,
>
>   	clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
>   	dd->clk_bypass = of_clk_get_from_provider(&clkspec);
> -	if (!dd->clk_bypass) {
> +	if (IS_ERR(dd->clk_bypass)) {

same

>   		pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
>   			clk_name);
>   		goto cleanup;
> @@ -225,14 +259,31 @@ static void __init of_omap_dpll_setup(struct device_node *node,
>   	dd->enable_mask = enable_mask;
>   	dd->autoidle_mask = autoidle_mask;
>
> -	dd->modes = 0xa0;
> +	if (!of_property_read_u32(node, "ti,recal-en-bit", &val))
> +		dd->recal_en_bit = val;
> +
> +	if (!of_property_read_u32(node, "ti,recal-st-bit", &val))
> +		dd->recal_st_bit = val;
> +
> +	if (!of_property_read_u32(node, "ti,auto-recal-bit", &val))
> +		dd->auto_recal_bit = val;

now I understand what it means.

> +
> +	of_property_read_u32(node, "ti,modes", &modes);
i see we pass in modes, and read ti,modes to &modes. it is a bit sketchy 
without bindings documentation.

> +
> +	dd->modes = modes;

Should have belonged to original patch.

> +
> +	dd->freqsel_mask = freqsel;
>
>   	if (of_property_read_bool(node, "ti,dpll-j-type")) {
>   		dd->sddiv_mask = 0xff000000;
> -		mult_mask = 0xfff << 8;
> -		div1_mask = 0xff;
> +		mult_mask = 0xfff << (8 + mul_div_shift);
>   		max_multiplier = 4095;
> -		max_divider = 256;
> +		if (subtype == SUBTYPE_OMAP3_DPLL) {
> +			dd->dco_mask = 0xe00000;
> +		} else {
> +			div1_mask = 0xff << mul_div_shift;
> +			max_divider = 256;
> +		}
>   	}
>
>   	if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
> @@ -281,7 +332,30 @@ static void __init of_omap_dpll_x2_setup(struct device_node *node)
>
>   __init void of_omap3_dpll_setup(struct device_node *node)
>   {
> -	/* XXX: to be done */
> +	const struct clk_ops *ops;
> +	u32 freqsel = 0xf0;
> +	u32 modes = 0xa0;
> +	u8 mul_div_shift = 0;
> +
> +	ops = &omap3_dpll_ck_ops;
> +
> +	if (of_property_read_bool(node, "ti,dpll-core")) {
> +		ops = &omap3_dpll_core_ck_ops;
> +		mul_div_shift = 8;
> +		modes = 0x0;
> +	}
> +
> +	if (of_property_read_bool(node, "ti,dpll-peripheral")) {
> +		ops = &omap3_dpll_per_ck_ops;
> +		freqsel = 0xf00000;
> +	}
> +
> +	if (of_property_read_bool(node, "ti,dpll-j-type"))
> +		freqsel = 0x0;
> +
> +	of_omap_dpll_setup(node, ops, freqsel, modes, mul_div_shift,
> +		SUBTYPE_OMAP3_DPLL);
> +
>   }
>   EXPORT_SYMBOL_GPL(of_omap3_dpll_setup);
>   CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock", of_omap3_dpll_setup);
> @@ -306,7 +380,7 @@ __init void of_omap4_dpll_setup(struct device_node *node)
>   	if (of_property_read_bool(node, "ti,dpll-no-gate"))
>   		ops = &dpll_no_gate_ck_ops;
>
> -	of_omap_dpll_setup(node, ops);
> +	of_omap_dpll_setup(node, ops, 0, 0xa0, 0, SUBTYPE_OMAP4_DPLL);
what is 0xa0?

>   }
>   EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>   CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock", of_omap4_dpll_setup);
>

I think this should be squashed and a single dpll.c introduction to be done.


-- 
Regards,
Nishanth Menon

Re: [PATCHv4 21/33] CLK: OMAP: DPLL: add omap3 dpll support

[Tero Kristo]

On 07/30/2013 11:08 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> OMAP3 has slightly different DPLLs from those compared to OMAP4. Modified
>> code for the same.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/dpll.c |   96
>> +++++++++++++++++++++++++++++++++++++++++------
>>   1 file changed, 85 insertions(+), 11 deletions(-)
>>
> :) wont repeat the binding crib again..
>
>> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
>> index d8a958a..ecb1fbd 100644
>> --- a/drivers/clk/omap/dpll.c
>> +++ b/drivers/clk/omap/dpll.c
>> @@ -26,6 +26,11 @@
>>   #include <linux/of_address.h>
>>   #include <linux/clk/omap.h>
>>
>> +enum {
>> +    SUBTYPE_OMAP3_DPLL,
>> +    SUBTYPE_OMAP4_DPLL,
>> +};
>> +
>>   static const struct clk_ops dpll_m4xen_ck_ops = {
>>       .enable        = &omap3_noncore_dpll_enable,
>>       .disable    = &omap3_noncore_dpll_disable,
>> @@ -40,6 +45,13 @@ static const struct clk_ops dpll_core_ck_ops = {
>>       .get_parent    = &omap2_init_dpll_parent,
>>   };
>>
>> +static const struct clk_ops omap3_dpll_core_ck_ops = {
>> +    .init        = &omap2_init_clk_clkdm,
>> +    .get_parent    = &omap2_init_dpll_parent,
>> +    .recalc_rate    = &omap3_dpll_recalc,
>> +    .round_rate    = &omap2_dpll_round_rate,
>> +};
>> +
>>   static const struct clk_ops dpll_ck_ops = {
>>       .enable        = &omap3_noncore_dpll_enable,
>>       .disable    = &omap3_noncore_dpll_disable,
>> @@ -50,6 +62,26 @@ static const struct clk_ops dpll_ck_ops = {
>>       .init        = &omap2_init_clk_clkdm,
>>   };
>>
>> +static const struct clk_ops omap3_dpll_ck_ops = {
>> +    .init        = &omap2_init_clk_clkdm,
>> +    .enable        = &omap3_noncore_dpll_enable,
>> +    .disable    = &omap3_noncore_dpll_disable,
>> +    .get_parent    = &omap2_init_dpll_parent,
>> +    .recalc_rate    = &omap3_dpll_recalc,
>> +    .set_rate    = &omap3_noncore_dpll_set_rate,
>> +    .round_rate    = &omap2_dpll_round_rate,
>> +};
>> +
>> +static const struct clk_ops omap3_dpll_per_ck_ops = {
>> +    .init        = &omap2_init_clk_clkdm,
>> +    .enable        = &omap3_noncore_dpll_enable,
>> +    .disable    = &omap3_noncore_dpll_disable,
>> +    .get_parent    = &omap2_init_dpll_parent,
>> +    .recalc_rate    = &omap3_dpll_recalc,
>> +    .set_rate    = &omap3_dpll4_set_rate,
>> +    .round_rate    = &omap2_dpll_round_rate,
>> +};
>> +
>>   static const struct clk_ops dpll_x2_ck_ops = {
>>       .recalc_rate    = &omap3_clkoutx2_recalc,
>>   };
>> @@ -144,7 +176,9 @@ struct clk *omap_clk_register_dpll_x2(struct
>> device *dev, const char *name,
>>    * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
>>    */
>>   static void __init of_omap_dpll_setup(struct device_node *node,
>> -                    const struct clk_ops *ops)
>> +                    const struct clk_ops *ops, u32 freqsel,
>> +                    u32 modes, u8 mul_div_shift,
>> +                    int subtype)
>>   {
>>       struct clk *clk;
>>       const char *clk_name = node->name;
>> @@ -157,8 +191,8 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>>       u32 idlest_mask = 0x1;
>>       u32 enable_mask = 0x7;
>>       u32 autoidle_mask = 0x7;
>> -    u32 mult_mask = 0x7ff << 8;
>> -    u32 div1_mask = 0x7f;
>> +    u32 mult_mask = 0x7ff << (8 + mul_div_shift);
>> +    u32 div1_mask = 0x7f << mul_div_shift;
>>       u32 max_multiplier = 2047;
>>       u32 max_divider = 128;
>>       u32 min_divider = 1;
>> @@ -193,7 +227,7 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>>
>>       clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
>>       dd->clk_ref = of_clk_get_from_provider(&clkspec);
>> -    if (!dd->clk_ref) {
>> +    if (IS_ERR(dd->clk_ref)) {
>
> belongs to original patch.

Agree.

>
>>           pr_err("%s: ti,clk-ref for %s not found\n", __func__,
>>               clk_name);
>>           goto cleanup;
>> @@ -201,7 +235,7 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>>
>>       clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
>>       dd->clk_bypass = of_clk_get_from_provider(&clkspec);
>> -    if (!dd->clk_bypass) {
>> +    if (IS_ERR(dd->clk_bypass)) {
>
> same

Ditto.

>
>>           pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
>>               clk_name);
>>           goto cleanup;
>> @@ -225,14 +259,31 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>>       dd->enable_mask = enable_mask;
>>       dd->autoidle_mask = autoidle_mask;
>>
>> -    dd->modes = 0xa0;
>> +    if (!of_property_read_u32(node, "ti,recal-en-bit", &val))
>> +        dd->recal_en_bit = val;
>> +
>> +    if (!of_property_read_u32(node, "ti,recal-st-bit", &val))
>> +        dd->recal_st_bit = val;
>> +
>> +    if (!of_property_read_u32(node, "ti,auto-recal-bit", &val))
>> +        dd->auto_recal_bit = val;
>
> now I understand what it means.

I am not quite sure you do, as I don't quite get your comment here. :) 
You referring to that dd->modes part?

>
>> +
>> +    of_property_read_u32(node, "ti,modes", &modes);
> i see we pass in modes, and read ti,modes to &modes. it is a bit sketchy
> without bindings documentation.

ti,modes can be used to override the default modes.

>
>> +
>> +    dd->modes = modes;
>
> Should have belonged to original patch.

If I squash this then we are fine.

>
>> +
>> +    dd->freqsel_mask = freqsel;
>>
>>       if (of_property_read_bool(node, "ti,dpll-j-type")) {
>>           dd->sddiv_mask = 0xff000000;
>> -        mult_mask = 0xfff << 8;
>> -        div1_mask = 0xff;
>> +        mult_mask = 0xfff << (8 + mul_div_shift);
>>           max_multiplier = 4095;
>> -        max_divider = 256;
>> +        if (subtype == SUBTYPE_OMAP3_DPLL) {
>> +            dd->dco_mask = 0xe00000;
>> +        } else {
>> +            div1_mask = 0xff << mul_div_shift;
>> +            max_divider = 256;
>> +        }
>>       }
>>
>>       if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
>> @@ -281,7 +332,30 @@ static void __init of_omap_dpll_x2_setup(struct
>> device_node *node)
>>
>>   __init void of_omap3_dpll_setup(struct device_node *node)
>>   {
>> -    /* XXX: to be done */
>> +    const struct clk_ops *ops;
>> +    u32 freqsel = 0xf0;
>> +    u32 modes = 0xa0;
>> +    u8 mul_div_shift = 0;
>> +
>> +    ops = &omap3_dpll_ck_ops;
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-core")) {
>> +        ops = &omap3_dpll_core_ck_ops;
>> +        mul_div_shift = 8;
>> +        modes = 0x0;
>> +    }
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-peripheral")) {
>> +        ops = &omap3_dpll_per_ck_ops;
>> +        freqsel = 0xf00000;
>> +    }
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-j-type"))
>> +        freqsel = 0x0;
>> +
>> +    of_omap_dpll_setup(node, ops, freqsel, modes, mul_div_shift,
>> +        SUBTYPE_OMAP3_DPLL);
>> +
>>   }
>>   EXPORT_SYMBOL_GPL(of_omap3_dpll_setup);
>>   CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock",
>> of_omap3_dpll_setup);
>> @@ -306,7 +380,7 @@ __init void of_omap4_dpll_setup(struct device_node
>> *node)
>>       if (of_property_read_bool(node, "ti,dpll-no-gate"))
>>           ops = &dpll_no_gate_ck_ops;
>>
>> -    of_omap_dpll_setup(node, ops);
>> +    of_omap_dpll_setup(node, ops, 0, 0xa0, 0, SUBTYPE_OMAP4_DPLL);
> what is 0xa0?

Magic modes for DPLL. I'll copy over the macro def as mentioned in one 
of the previous patches.

>
>>   }
>>   EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>>   CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock",
>> of_omap4_dpll_setup);
>>
>
> I think this should be squashed and a single dpll.c introduction to be
> done.

Ok.

>
>

[PATCHv4 21/33] CLK: OMAP: DPLL: add omap3 dpll support

[Tero Kristo]

On 07/30/2013 11:08 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> OMAP3 has slightly different DPLLs from those compared to OMAP4. Modified
>> code for the same.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/dpll.c |   96
>> +++++++++++++++++++++++++++++++++++++++++------
>>   1 file changed, 85 insertions(+), 11 deletions(-)
>>
> :) wont repeat the binding crib again..
>
>> diff --git a/drivers/clk/omap/dpll.c b/drivers/clk/omap/dpll.c
>> index d8a958a..ecb1fbd 100644
>> --- a/drivers/clk/omap/dpll.c
>> +++ b/drivers/clk/omap/dpll.c
>> @@ -26,6 +26,11 @@
>>   #include <linux/of_address.h>
>>   #include <linux/clk/omap.h>
>>
>> +enum {
>> +    SUBTYPE_OMAP3_DPLL,
>> +    SUBTYPE_OMAP4_DPLL,
>> +};
>> +
>>   static const struct clk_ops dpll_m4xen_ck_ops = {
>>       .enable        = &omap3_noncore_dpll_enable,
>>       .disable    = &omap3_noncore_dpll_disable,
>> @@ -40,6 +45,13 @@ static const struct clk_ops dpll_core_ck_ops = {
>>       .get_parent    = &omap2_init_dpll_parent,
>>   };
>>
>> +static const struct clk_ops omap3_dpll_core_ck_ops = {
>> +    .init        = &omap2_init_clk_clkdm,
>> +    .get_parent    = &omap2_init_dpll_parent,
>> +    .recalc_rate    = &omap3_dpll_recalc,
>> +    .round_rate    = &omap2_dpll_round_rate,
>> +};
>> +
>>   static const struct clk_ops dpll_ck_ops = {
>>       .enable        = &omap3_noncore_dpll_enable,
>>       .disable    = &omap3_noncore_dpll_disable,
>> @@ -50,6 +62,26 @@ static const struct clk_ops dpll_ck_ops = {
>>       .init        = &omap2_init_clk_clkdm,
>>   };
>>
>> +static const struct clk_ops omap3_dpll_ck_ops = {
>> +    .init        = &omap2_init_clk_clkdm,
>> +    .enable        = &omap3_noncore_dpll_enable,
>> +    .disable    = &omap3_noncore_dpll_disable,
>> +    .get_parent    = &omap2_init_dpll_parent,
>> +    .recalc_rate    = &omap3_dpll_recalc,
>> +    .set_rate    = &omap3_noncore_dpll_set_rate,
>> +    .round_rate    = &omap2_dpll_round_rate,
>> +};
>> +
>> +static const struct clk_ops omap3_dpll_per_ck_ops = {
>> +    .init        = &omap2_init_clk_clkdm,
>> +    .enable        = &omap3_noncore_dpll_enable,
>> +    .disable    = &omap3_noncore_dpll_disable,
>> +    .get_parent    = &omap2_init_dpll_parent,
>> +    .recalc_rate    = &omap3_dpll_recalc,
>> +    .set_rate    = &omap3_dpll4_set_rate,
>> +    .round_rate    = &omap2_dpll_round_rate,
>> +};
>> +
>>   static const struct clk_ops dpll_x2_ck_ops = {
>>       .recalc_rate    = &omap3_clkoutx2_recalc,
>>   };
>> @@ -144,7 +176,9 @@ struct clk *omap_clk_register_dpll_x2(struct
>> device *dev, const char *name,
>>    * of_omap_dpll_setup() - Setup function for OMAP DPLL clocks
>>    */
>>   static void __init of_omap_dpll_setup(struct device_node *node,
>> -                    const struct clk_ops *ops)
>> +                    const struct clk_ops *ops, u32 freqsel,
>> +                    u32 modes, u8 mul_div_shift,
>> +                    int subtype)
>>   {
>>       struct clk *clk;
>>       const char *clk_name = node->name;
>> @@ -157,8 +191,8 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>>       u32 idlest_mask = 0x1;
>>       u32 enable_mask = 0x7;
>>       u32 autoidle_mask = 0x7;
>> -    u32 mult_mask = 0x7ff << 8;
>> -    u32 div1_mask = 0x7f;
>> +    u32 mult_mask = 0x7ff << (8 + mul_div_shift);
>> +    u32 div1_mask = 0x7f << mul_div_shift;
>>       u32 max_multiplier = 2047;
>>       u32 max_divider = 128;
>>       u32 min_divider = 1;
>> @@ -193,7 +227,7 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>>
>>       clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
>>       dd->clk_ref = of_clk_get_from_provider(&clkspec);
>> -    if (!dd->clk_ref) {
>> +    if (IS_ERR(dd->clk_ref)) {
>
> belongs to original patch.

Agree.

>
>>           pr_err("%s: ti,clk-ref for %s not found\n", __func__,
>>               clk_name);
>>           goto cleanup;
>> @@ -201,7 +235,7 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>>
>>       clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
>>       dd->clk_bypass = of_clk_get_from_provider(&clkspec);
>> -    if (!dd->clk_bypass) {
>> +    if (IS_ERR(dd->clk_bypass)) {
>
> same

Ditto.

>
>>           pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
>>               clk_name);
>>           goto cleanup;
>> @@ -225,14 +259,31 @@ static void __init of_omap_dpll_setup(struct
>> device_node *node,
>>       dd->enable_mask = enable_mask;
>>       dd->autoidle_mask = autoidle_mask;
>>
>> -    dd->modes = 0xa0;
>> +    if (!of_property_read_u32(node, "ti,recal-en-bit", &val))
>> +        dd->recal_en_bit = val;
>> +
>> +    if (!of_property_read_u32(node, "ti,recal-st-bit", &val))
>> +        dd->recal_st_bit = val;
>> +
>> +    if (!of_property_read_u32(node, "ti,auto-recal-bit", &val))
>> +        dd->auto_recal_bit = val;
>
> now I understand what it means.

I am not quite sure you do, as I don't quite get your comment here. :) 
You referring to that dd->modes part?

>
>> +
>> +    of_property_read_u32(node, "ti,modes", &modes);
> i see we pass in modes, and read ti,modes to &modes. it is a bit sketchy
> without bindings documentation.

ti,modes can be used to override the default modes.

>
>> +
>> +    dd->modes = modes;
>
> Should have belonged to original patch.

If I squash this then we are fine.

>
>> +
>> +    dd->freqsel_mask = freqsel;
>>
>>       if (of_property_read_bool(node, "ti,dpll-j-type")) {
>>           dd->sddiv_mask = 0xff000000;
>> -        mult_mask = 0xfff << 8;
>> -        div1_mask = 0xff;
>> +        mult_mask = 0xfff << (8 + mul_div_shift);
>>           max_multiplier = 4095;
>> -        max_divider = 256;
>> +        if (subtype == SUBTYPE_OMAP3_DPLL) {
>> +            dd->dco_mask = 0xe00000;
>> +        } else {
>> +            div1_mask = 0xff << mul_div_shift;
>> +            max_divider = 256;
>> +        }
>>       }
>>
>>       if (of_property_read_bool(node, "ti,dpll-regm4xen")) {
>> @@ -281,7 +332,30 @@ static void __init of_omap_dpll_x2_setup(struct
>> device_node *node)
>>
>>   __init void of_omap3_dpll_setup(struct device_node *node)
>>   {
>> -    /* XXX: to be done */
>> +    const struct clk_ops *ops;
>> +    u32 freqsel = 0xf0;
>> +    u32 modes = 0xa0;
>> +    u8 mul_div_shift = 0;
>> +
>> +    ops = &omap3_dpll_ck_ops;
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-core")) {
>> +        ops = &omap3_dpll_core_ck_ops;
>> +        mul_div_shift = 8;
>> +        modes = 0x0;
>> +    }
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-peripheral")) {
>> +        ops = &omap3_dpll_per_ck_ops;
>> +        freqsel = 0xf00000;
>> +    }
>> +
>> +    if (of_property_read_bool(node, "ti,dpll-j-type"))
>> +        freqsel = 0x0;
>> +
>> +    of_omap_dpll_setup(node, ops, freqsel, modes, mul_div_shift,
>> +        SUBTYPE_OMAP3_DPLL);
>> +
>>   }
>>   EXPORT_SYMBOL_GPL(of_omap3_dpll_setup);
>>   CLK_OF_DECLARE(omap3_dpll_clock, "ti,omap3-dpll-clock",
>> of_omap3_dpll_setup);
>> @@ -306,7 +380,7 @@ __init void of_omap4_dpll_setup(struct device_node
>> *node)
>>       if (of_property_read_bool(node, "ti,dpll-no-gate"))
>>           ops = &dpll_no_gate_ck_ops;
>>
>> -    of_omap_dpll_setup(node, ops);
>> +    of_omap_dpll_setup(node, ops, 0, 0xa0, 0, SUBTYPE_OMAP4_DPLL);
> what is 0xa0?

Magic modes for DPLL. I'll copy over the macro def as mentioned in one 
of the previous patches.

>
>>   }
>>   EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>>   CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock",
>> of_omap4_dpll_setup);
>>
>
> I think this should be squashed and a single dpll.c introduction to be
> done.

Ok.

>
>

Re: [PATCHv4 21/33] CLK: OMAP: DPLL: add omap3 dpll support

[Nishanth Menon]

On 07/31/2013 10:03 AM, Tero Kristo wrote:
> On 07/30/2013 11:08 PM, Nishanth Menon wrote:
>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
[...]

>>
>>>           pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
>>>               clk_name);
>>>           goto cleanup;
>>> @@ -225,14 +259,31 @@ static void __init of_omap_dpll_setup(struct
>>> device_node *node,
>>>       dd->enable_mask = enable_mask;
>>>       dd->autoidle_mask = autoidle_mask;
>>>
>>> -    dd->modes = 0xa0;
>>> +    if (!of_property_read_u32(node, "ti,recal-en-bit", &val))
>>> +        dd->recal_en_bit = val;
>>> +
>>> +    if (!of_property_read_u32(node, "ti,recal-st-bit", &val))
>>> +        dd->recal_st_bit = val;
>>> +
>>> +    if (!of_property_read_u32(node, "ti,auto-recal-bit", &val))
>>> +        dd->auto_recal_bit = val;
>>
>> now I understand what it means.
>
> I am not quite sure you do, as I don't quite get your comment here. :)
> You referring to that dd->modes part?

yep.

>
>>
>>> +
>>> +    of_property_read_u32(node, "ti,modes", &modes);
>> i see we pass in modes, and read ti,modes to &modes. it is a bit sketchy
>> without bindings documentation.
>
> ti,modes can be used to override the default modes.

I get it, but prefer seeing it in Documentation/devicetree/bindings/... 
So that you would not have to repeat it anymore :D

>
>>
>>> +
>>> +    dd->modes = modes;
>>
>> Should have belonged to original patch.
>
> If I squash this then we are fine.

yes, thanks.

>>>
>>> -    of_omap_dpll_setup(node, ops);
>>> +    of_omap_dpll_setup(node, ops, 0, 0xa0, 0, SUBTYPE_OMAP4_DPLL);
>> what is 0xa0?
>
> Magic modes for DPLL. I'll copy over the macro def as mentioned in one
> of the previous patches.

yes, please..

>
>>
>>>   }
>>>   EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>>>   CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock",
>>> of_omap4_dpll_setup);
>>>
>>
>> I think this should be squashed and a single dpll.c introduction to be
>> done.
>
> Ok.

thanks.

-- 
Regards,
Nishanth Menon

[PATCHv4 21/33] CLK: OMAP: DPLL: add omap3 dpll support

[Nishanth Menon]

On 07/31/2013 10:03 AM, Tero Kristo wrote:
> On 07/30/2013 11:08 PM, Nishanth Menon wrote:
>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
[...]

>>
>>>           pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
>>>               clk_name);
>>>           goto cleanup;
>>> @@ -225,14 +259,31 @@ static void __init of_omap_dpll_setup(struct
>>> device_node *node,
>>>       dd->enable_mask = enable_mask;
>>>       dd->autoidle_mask = autoidle_mask;
>>>
>>> -    dd->modes = 0xa0;
>>> +    if (!of_property_read_u32(node, "ti,recal-en-bit", &val))
>>> +        dd->recal_en_bit = val;
>>> +
>>> +    if (!of_property_read_u32(node, "ti,recal-st-bit", &val))
>>> +        dd->recal_st_bit = val;
>>> +
>>> +    if (!of_property_read_u32(node, "ti,auto-recal-bit", &val))
>>> +        dd->auto_recal_bit = val;
>>
>> now I understand what it means.
>
> I am not quite sure you do, as I don't quite get your comment here. :)
> You referring to that dd->modes part?

yep.

>
>>
>>> +
>>> +    of_property_read_u32(node, "ti,modes", &modes);
>> i see we pass in modes, and read ti,modes to &modes. it is a bit sketchy
>> without bindings documentation.
>
> ti,modes can be used to override the default modes.

I get it, but prefer seeing it in Documentation/devicetree/bindings/... 
So that you would not have to repeat it anymore :D

>
>>
>>> +
>>> +    dd->modes = modes;
>>
>> Should have belonged to original patch.
>
> If I squash this then we are fine.

yes, thanks.

>>>
>>> -    of_omap_dpll_setup(node, ops);
>>> +    of_omap_dpll_setup(node, ops, 0, 0xa0, 0, SUBTYPE_OMAP4_DPLL);
>> what is 0xa0?
>
> Magic modes for DPLL. I'll copy over the macro def as mentioned in one
> of the previous patches.

yes, please..

>
>>
>>>   }
>>>   EXPORT_SYMBOL_GPL(of_omap4_dpll_setup);
>>>   CLK_OF_DECLARE(omap4_dpll_clock, "ti,omap4-dpll-clock",
>>> of_omap4_dpll_setup);
>>>
>>
>> I think this should be squashed and a single dpll.c introduction to be
>> done.
>
> Ok.

thanks.

-- 
Regards,
Nishanth Menon

[PATCHv4 22/33] CLK: OMAP: update gate clock setup for OMAP3

[Tero Kristo]

OMAP3 gate clocks are handled through the clk driver now. Basic gate
clock can't be used as the OMAP3 gate clocks have some special features,
namely the idle status linkage which is on separate register.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/gate.c |   27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
index 7186bb2..b560ff4 100644
--- a/drivers/clk/omap/gate.c
+++ b/drivers/clk/omap/gate.c
@@ -28,12 +28,19 @@
 
 #ifdef CONFIG_OF
 
-static const struct clk_ops omap_gate_clk_ops = {
+static const struct clk_ops omap_gate_clkdm_clk_ops = {
 	.init		= &omap2_init_clk_clkdm,
 	.enable		= &omap2_clkops_enable_clkdm,
 	.disable	= &omap2_clkops_disable_clkdm,
 };
 
+static const struct clk_ops omap_gate_clk_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
 void __init of_omap_gate_clk_setup(struct device_node *node)
 {
 	struct clk *clk;
@@ -43,6 +50,7 @@ void __init of_omap_gate_clk_setup(struct device_node *node)
 	int num_parents;
 	const char **parent_names;
 	int i;
+	u32 val;
 
 	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
 	if (!clk_hw) {
@@ -56,7 +64,22 @@ void __init of_omap_gate_clk_setup(struct device_node *node)
 	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
 
 	init.name = clk_name;
-	init.ops = &omap_gate_clk_ops;
+	init.flags = 0;
+
+	if (of_property_read_u32_index(node, "reg", 0, &val)) {
+		/* No register, clkdm control only */
+		init.ops = &omap_gate_clkdm_clk_ops;
+	} else {
+		init.ops = &omap_gate_clk_ops;
+		clk_hw->enable_reg = of_iomap(node, 0);
+		of_property_read_u32(node, "ti,enable-bit", &val);
+		clk_hw->enable_bit = val;
+
+		if (of_property_read_bool(node, "ti,dss-clk"))
+			clk_hw->ops = &clkhwops_omap3430es2_dss_usbhost_wait;
+		else
+			clk_hw->ops = &clkhwops_wait;
+	}
 
 	num_parents = of_clk_get_parent_count(node);
 	if (num_parents < 1) {
-- 
1.7.9.5

[PATCHv4 22/33] CLK: OMAP: update gate clock setup for OMAP3

[Tero Kristo]

OMAP3 gate clocks are handled through the clk driver now. Basic gate
clock can't be used as the OMAP3 gate clocks have some special features,
namely the idle status linkage which is on separate register.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/gate.c |   27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
index 7186bb2..b560ff4 100644
--- a/drivers/clk/omap/gate.c
+++ b/drivers/clk/omap/gate.c
@@ -28,12 +28,19 @@
 
 #ifdef CONFIG_OF
 
-static const struct clk_ops omap_gate_clk_ops = {
+static const struct clk_ops omap_gate_clkdm_clk_ops = {
 	.init		= &omap2_init_clk_clkdm,
 	.enable		= &omap2_clkops_enable_clkdm,
 	.disable	= &omap2_clkops_disable_clkdm,
 };
 
+static const struct clk_ops omap_gate_clk_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
 void __init of_omap_gate_clk_setup(struct device_node *node)
 {
 	struct clk *clk;
@@ -43,6 +50,7 @@ void __init of_omap_gate_clk_setup(struct device_node *node)
 	int num_parents;
 	const char **parent_names;
 	int i;
+	u32 val;
 
 	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
 	if (!clk_hw) {
@@ -56,7 +64,22 @@ void __init of_omap_gate_clk_setup(struct device_node *node)
 	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
 
 	init.name = clk_name;
-	init.ops = &omap_gate_clk_ops;
+	init.flags = 0;
+
+	if (of_property_read_u32_index(node, "reg", 0, &val)) {
+		/* No register, clkdm control only */
+		init.ops = &omap_gate_clkdm_clk_ops;
+	} else {
+		init.ops = &omap_gate_clk_ops;
+		clk_hw->enable_reg = of_iomap(node, 0);
+		of_property_read_u32(node, "ti,enable-bit", &val);
+		clk_hw->enable_bit = val;
+
+		if (of_property_read_bool(node, "ti,dss-clk"))
+			clk_hw->ops = &clkhwops_omap3430es2_dss_usbhost_wait;
+		else
+			clk_hw->ops = &clkhwops_wait;
+	}
 
 	num_parents = of_clk_get_parent_count(node);
 	if (num_parents < 1) {
-- 
1.7.9.5

Re: [PATCHv4 22/33] CLK: OMAP: update gate clock setup for OMAP3

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> OMAP3 gate clocks are handled through the clk driver now. Basic gate
> clock can't be used as the OMAP3 gate clocks have some special features,
> namely the idle status linkage which is on separate register.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/gate.c |   27 +++++++++++++++++++++++++--
>   1 file changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
> index 7186bb2..b560ff4 100644
> --- a/drivers/clk/omap/gate.c
> +++ b/drivers/clk/omap/gate.c
> @@ -28,12 +28,19 @@
>
>   #ifdef CONFIG_OF
>
> -static const struct clk_ops omap_gate_clk_ops = {
> +static const struct clk_ops omap_gate_clkdm_clk_ops = {
>   	.init		= &omap2_init_clk_clkdm,
>   	.enable		= &omap2_clkops_enable_clkdm,
>   	.disable	= &omap2_clkops_disable_clkdm,
>   };
>
> +static const struct clk_ops omap_gate_clk_ops = {
> +	.init		= &omap2_init_clk_clkdm,
> +	.enable		= &omap2_dflt_clk_enable,
> +	.disable	= &omap2_dflt_clk_disable,
> +	.is_enabled	= &omap2_dflt_clk_is_enabled,
> +};
> +
>   void __init of_omap_gate_clk_setup(struct device_node *node)
>   {
>   	struct clk *clk;
> @@ -43,6 +50,7 @@ void __init of_omap_gate_clk_setup(struct device_node *node)
>   	int num_parents;
>   	const char **parent_names;
>   	int i;
> +	u32 val;
>
>   	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
>   	if (!clk_hw) {
> @@ -56,7 +64,22 @@ void __init of_omap_gate_clk_setup(struct device_node *node)
>   	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
>
>   	init.name = clk_name;
> -	init.ops = &omap_gate_clk_ops;
> +	init.flags = 0;
> +
> +	if (of_property_read_u32_index(node, "reg", 0, &val)) {
> +		/* No register, clkdm control only */
> +		init.ops = &omap_gate_clkdm_clk_ops;
> +	} else {
> +		init.ops = &omap_gate_clk_ops;
> +		clk_hw->enable_reg = of_iomap(node, 0);
> +		of_property_read_u32(node, "ti,enable-bit", &val);
> +		clk_hw->enable_bit = val;
> +
> +		if (of_property_read_bool(node, "ti,dss-clk"))
> +			clk_hw->ops = &clkhwops_omap3430es2_dss_usbhost_wait;

umm, it was going relatively ok so far, till i hit this :( it is 
probably a quirk... but still..

> +		else
> +			clk_hw->ops = &clkhwops_wait;
> +	}
>
>   	num_parents = of_clk_get_parent_count(node);
>   	if (num_parents < 1) {
>

but still no usage of "ti,omap-gate-clock" makes me question the need 
for this file.

-- 
Regards,
Nishanth Menon

[PATCHv4 22/33] CLK: OMAP: update gate clock setup for OMAP3

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> OMAP3 gate clocks are handled through the clk driver now. Basic gate
> clock can't be used as the OMAP3 gate clocks have some special features,
> namely the idle status linkage which is on separate register.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/gate.c |   27 +++++++++++++++++++++++++--
>   1 file changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
> index 7186bb2..b560ff4 100644
> --- a/drivers/clk/omap/gate.c
> +++ b/drivers/clk/omap/gate.c
> @@ -28,12 +28,19 @@
>
>   #ifdef CONFIG_OF
>
> -static const struct clk_ops omap_gate_clk_ops = {
> +static const struct clk_ops omap_gate_clkdm_clk_ops = {
>   	.init		= &omap2_init_clk_clkdm,
>   	.enable		= &omap2_clkops_enable_clkdm,
>   	.disable	= &omap2_clkops_disable_clkdm,
>   };
>
> +static const struct clk_ops omap_gate_clk_ops = {
> +	.init		= &omap2_init_clk_clkdm,
> +	.enable		= &omap2_dflt_clk_enable,
> +	.disable	= &omap2_dflt_clk_disable,
> +	.is_enabled	= &omap2_dflt_clk_is_enabled,
> +};
> +
>   void __init of_omap_gate_clk_setup(struct device_node *node)
>   {
>   	struct clk *clk;
> @@ -43,6 +50,7 @@ void __init of_omap_gate_clk_setup(struct device_node *node)
>   	int num_parents;
>   	const char **parent_names;
>   	int i;
> +	u32 val;
>
>   	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
>   	if (!clk_hw) {
> @@ -56,7 +64,22 @@ void __init of_omap_gate_clk_setup(struct device_node *node)
>   	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
>
>   	init.name = clk_name;
> -	init.ops = &omap_gate_clk_ops;
> +	init.flags = 0;
> +
> +	if (of_property_read_u32_index(node, "reg", 0, &val)) {
> +		/* No register, clkdm control only */
> +		init.ops = &omap_gate_clkdm_clk_ops;
> +	} else {
> +		init.ops = &omap_gate_clk_ops;
> +		clk_hw->enable_reg = of_iomap(node, 0);
> +		of_property_read_u32(node, "ti,enable-bit", &val);
> +		clk_hw->enable_bit = val;
> +
> +		if (of_property_read_bool(node, "ti,dss-clk"))
> +			clk_hw->ops = &clkhwops_omap3430es2_dss_usbhost_wait;

umm, it was going relatively ok so far, till i hit this :( it is 
probably a quirk... but still..

> +		else
> +			clk_hw->ops = &clkhwops_wait;
> +	}
>
>   	num_parents = of_clk_get_parent_count(node);
>   	if (num_parents < 1) {
>

but still no usage of "ti,omap-gate-clock" makes me question the need 
for this file.

-- 
Regards,
Nishanth Menon

Re: [PATCHv4 22/33] CLK: OMAP: update gate clock setup for OMAP3

[Tero Kristo]

On 07/30/2013 11:13 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> OMAP3 gate clocks are handled through the clk driver now. Basic gate
>> clock can't be used as the OMAP3 gate clocks have some special features,
>> namely the idle status linkage which is on separate register.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/gate.c |   27 +++++++++++++++++++++++++--
>>   1 file changed, 25 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
>> index 7186bb2..b560ff4 100644
>> --- a/drivers/clk/omap/gate.c
>> +++ b/drivers/clk/omap/gate.c
>> @@ -28,12 +28,19 @@
>>
>>   #ifdef CONFIG_OF
>>
>> -static const struct clk_ops omap_gate_clk_ops = {
>> +static const struct clk_ops omap_gate_clkdm_clk_ops = {
>>       .init        = &omap2_init_clk_clkdm,
>>       .enable        = &omap2_clkops_enable_clkdm,
>>       .disable    = &omap2_clkops_disable_clkdm,
>>   };
>>
>> +static const struct clk_ops omap_gate_clk_ops = {
>> +    .init        = &omap2_init_clk_clkdm,
>> +    .enable        = &omap2_dflt_clk_enable,
>> +    .disable    = &omap2_dflt_clk_disable,
>> +    .is_enabled    = &omap2_dflt_clk_is_enabled,
>> +};
>> +
>>   void __init of_omap_gate_clk_setup(struct device_node *node)
>>   {
>>       struct clk *clk;
>> @@ -43,6 +50,7 @@ void __init of_omap_gate_clk_setup(struct
>> device_node *node)
>>       int num_parents;
>>       const char **parent_names;
>>       int i;
>> +    u32 val;
>>
>>       clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
>>       if (!clk_hw) {
>> @@ -56,7 +64,22 @@ void __init of_omap_gate_clk_setup(struct
>> device_node *node)
>>       of_property_read_string(node, "ti,clkdm-name",
>> &clk_hw->clkdm_name);
>>
>>       init.name = clk_name;
>> -    init.ops = &omap_gate_clk_ops;
>> +    init.flags = 0;
>> +
>> +    if (of_property_read_u32_index(node, "reg", 0, &val)) {
>> +        /* No register, clkdm control only */
>> +        init.ops = &omap_gate_clkdm_clk_ops;
>> +    } else {
>> +        init.ops = &omap_gate_clk_ops;
>> +        clk_hw->enable_reg = of_iomap(node, 0);
>> +        of_property_read_u32(node, "ti,enable-bit", &val);
>> +        clk_hw->enable_bit = val;
>> +
>> +        if (of_property_read_bool(node, "ti,dss-clk"))
>> +            clk_hw->ops = &clkhwops_omap3430es2_dss_usbhost_wait;
>
> umm, it was going relatively ok so far, till i hit this :( it is
> probably a quirk... but still..

Some of the clocks need special hwops for them to work properly it 
seems... It looks nasty yea but the best I could think of.

>
>> +        else
>> +            clk_hw->ops = &clkhwops_wait;
>> +    }
>>
>>       num_parents = of_clk_get_parent_count(node);
>>       if (num_parents < 1) {
>>
>
> but still no usage of "ti,omap-gate-clock" makes me question the need
> for this file.
>

Yea, no ti,omap-gate-clock, but there is ti,gate-clock. Just look harder.

[PATCHv4 22/33] CLK: OMAP: update gate clock setup for OMAP3

[Tero Kristo]

On 07/30/2013 11:13 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> OMAP3 gate clocks are handled through the clk driver now. Basic gate
>> clock can't be used as the OMAP3 gate clocks have some special features,
>> namely the idle status linkage which is on separate register.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/gate.c |   27 +++++++++++++++++++++++++--
>>   1 file changed, 25 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
>> index 7186bb2..b560ff4 100644
>> --- a/drivers/clk/omap/gate.c
>> +++ b/drivers/clk/omap/gate.c
>> @@ -28,12 +28,19 @@
>>
>>   #ifdef CONFIG_OF
>>
>> -static const struct clk_ops omap_gate_clk_ops = {
>> +static const struct clk_ops omap_gate_clkdm_clk_ops = {
>>       .init        = &omap2_init_clk_clkdm,
>>       .enable        = &omap2_clkops_enable_clkdm,
>>       .disable    = &omap2_clkops_disable_clkdm,
>>   };
>>
>> +static const struct clk_ops omap_gate_clk_ops = {
>> +    .init        = &omap2_init_clk_clkdm,
>> +    .enable        = &omap2_dflt_clk_enable,
>> +    .disable    = &omap2_dflt_clk_disable,
>> +    .is_enabled    = &omap2_dflt_clk_is_enabled,
>> +};
>> +
>>   void __init of_omap_gate_clk_setup(struct device_node *node)
>>   {
>>       struct clk *clk;
>> @@ -43,6 +50,7 @@ void __init of_omap_gate_clk_setup(struct
>> device_node *node)
>>       int num_parents;
>>       const char **parent_names;
>>       int i;
>> +    u32 val;
>>
>>       clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
>>       if (!clk_hw) {
>> @@ -56,7 +64,22 @@ void __init of_omap_gate_clk_setup(struct
>> device_node *node)
>>       of_property_read_string(node, "ti,clkdm-name",
>> &clk_hw->clkdm_name);
>>
>>       init.name = clk_name;
>> -    init.ops = &omap_gate_clk_ops;
>> +    init.flags = 0;
>> +
>> +    if (of_property_read_u32_index(node, "reg", 0, &val)) {
>> +        /* No register, clkdm control only */
>> +        init.ops = &omap_gate_clkdm_clk_ops;
>> +    } else {
>> +        init.ops = &omap_gate_clk_ops;
>> +        clk_hw->enable_reg = of_iomap(node, 0);
>> +        of_property_read_u32(node, "ti,enable-bit", &val);
>> +        clk_hw->enable_bit = val;
>> +
>> +        if (of_property_read_bool(node, "ti,dss-clk"))
>> +            clk_hw->ops = &clkhwops_omap3430es2_dss_usbhost_wait;
>
> umm, it was going relatively ok so far, till i hit this :( it is
> probably a quirk... but still..

Some of the clocks need special hwops for them to work properly it 
seems... It looks nasty yea but the best I could think of.

>
>> +        else
>> +            clk_hw->ops = &clkhwops_wait;
>> +    }
>>
>>       num_parents = of_clk_get_parent_count(node);
>>       if (num_parents < 1) {
>>
>
> but still no usage of "ti,omap-gate-clock" makes me question the need
> for this file.
>

Yea, no ti,omap-gate-clock, but there is ti,gate-clock. Just look harder.

[PATCHv4 23/33] CLK: OMAP: add interface clock support for OMAP3

[Tero Kristo]

OMAP3 has interface clocks in addition to functional clocks, which
require special handling for the autoidle and idle status register
offsets mainly.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/Makefile    |    2 +-
 drivers/clk/omap/clk.c       |    3 ++
 drivers/clk/omap/interface.c |  110 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 114 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/omap/interface.c

diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index c4e8825..faaeb62 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1,3 +1,3 @@
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
 					   clk-44xx.o clk-54xx.o clk-7xx.o \
-					   clk-33xx.o
+					   clk-33xx.o interface.o
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index 8c89714..5cbefde 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -30,6 +30,9 @@ static const struct of_device_id clk_match[] = {
 	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
 	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
 	{.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
+	{.compatible = "ti,interface-clock",
+		.data = of_omap_interface_clk_setup, },
+	{.compatible = "ti,omap3-dpll-clock", .data = of_omap3_dpll_setup, },
 	{},
 };
 
diff --git a/drivers/clk/omap/interface.c b/drivers/clk/omap/interface.c
new file mode 100644
index 0000000..f1f1a1a
--- /dev/null
+++ b/drivers/clk/omap/interface.c
@@ -0,0 +1,110 @@
+/*
+ * OMAP interface clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/omap.h>
+
+#ifdef CONFIG_OF
+
+static const struct clk_ops omap_interface_clk_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
+void __init of_omap_interface_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	struct clk_init_data init;
+	struct clk_hw_omap *clk_hw;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names;
+	int i;
+	u32 val;
+
+	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return;
+	}
+
+	clk_hw->hw.init = &init;
+	clk_hw->ops = &clkhwops_iclk_wait;
+	clk_hw->enable_reg = of_iomap(node, 0);
+
+	if (!of_property_read_u32(node, "ti,enable-bit", &val))
+		clk_hw->enable_bit = val;
+
+	if (of_property_read_bool(node, "ti,iclk-no-wait"))
+		clk_hw->ops = &clkhwops_iclk;
+
+	if (of_property_read_bool(node, "ti,iclk-hsotgusb"))
+		clk_hw->ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait;
+
+	if (of_property_read_bool(node, "ti,iclk-dss"))
+		clk_hw->ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait;
+
+	if (of_property_read_bool(node, "ti,iclk-ssi"))
+		clk_hw->ops = &clkhwops_omap3430es2_iclk_ssi_wait;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
+
+	init.name = clk_name;
+	init.ops = &omap_interface_clk_ops;
+	init.flags = 0;
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: omap interface_clk %s must have parent(s)\n",
+			__func__, node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	init.num_parents = num_parents;
+	init.parent_names = parent_names;
+
+	clk = clk_register(NULL, &clk_hw->hw);
+
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		omap2_init_clk_hw_omap_clocks(clk);
+		return;
+	}
+
+cleanup:
+	kfree(clk_hw);
+}
+EXPORT_SYMBOL(of_omap_interface_clk_setup);
+CLK_OF_DECLARE(omap_interface_clk, "ti,omap-interface-clock",
+		of_omap_interface_clk_setup);
+#endif
-- 
1.7.9.5

[PATCHv4 23/33] CLK: OMAP: add interface clock support for OMAP3

[Tero Kristo]

OMAP3 has interface clocks in addition to functional clocks, which
require special handling for the autoidle and idle status register
offsets mainly.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/Makefile    |    2 +-
 drivers/clk/omap/clk.c       |    3 ++
 drivers/clk/omap/interface.c |  110 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 114 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/omap/interface.c

diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index c4e8825..faaeb62 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1,3 +1,3 @@
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
 					   clk-44xx.o clk-54xx.o clk-7xx.o \
-					   clk-33xx.o
+					   clk-33xx.o interface.o
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index 8c89714..5cbefde 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -30,6 +30,9 @@ static const struct of_device_id clk_match[] = {
 	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
 	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
 	{.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
+	{.compatible = "ti,interface-clock",
+		.data = of_omap_interface_clk_setup, },
+	{.compatible = "ti,omap3-dpll-clock", .data = of_omap3_dpll_setup, },
 	{},
 };
 
diff --git a/drivers/clk/omap/interface.c b/drivers/clk/omap/interface.c
new file mode 100644
index 0000000..f1f1a1a
--- /dev/null
+++ b/drivers/clk/omap/interface.c
@@ -0,0 +1,110 @@
+/*
+ * OMAP interface clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/omap.h>
+
+#ifdef CONFIG_OF
+
+static const struct clk_ops omap_interface_clk_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
+void __init of_omap_interface_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	struct clk_init_data init;
+	struct clk_hw_omap *clk_hw;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names;
+	int i;
+	u32 val;
+
+	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return;
+	}
+
+	clk_hw->hw.init = &init;
+	clk_hw->ops = &clkhwops_iclk_wait;
+	clk_hw->enable_reg = of_iomap(node, 0);
+
+	if (!of_property_read_u32(node, "ti,enable-bit", &val))
+		clk_hw->enable_bit = val;
+
+	if (of_property_read_bool(node, "ti,iclk-no-wait"))
+		clk_hw->ops = &clkhwops_iclk;
+
+	if (of_property_read_bool(node, "ti,iclk-hsotgusb"))
+		clk_hw->ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait;
+
+	if (of_property_read_bool(node, "ti,iclk-dss"))
+		clk_hw->ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait;
+
+	if (of_property_read_bool(node, "ti,iclk-ssi"))
+		clk_hw->ops = &clkhwops_omap3430es2_iclk_ssi_wait;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
+
+	init.name = clk_name;
+	init.ops = &omap_interface_clk_ops;
+	init.flags = 0;
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: omap interface_clk %s must have parent(s)\n",
+			__func__, node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	init.num_parents = num_parents;
+	init.parent_names = parent_names;
+
+	clk = clk_register(NULL, &clk_hw->hw);
+
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		omap2_init_clk_hw_omap_clocks(clk);
+		return;
+	}
+
+cleanup:
+	kfree(clk_hw);
+}
+EXPORT_SYMBOL(of_omap_interface_clk_setup);
+CLK_OF_DECLARE(omap_interface_clk, "ti,omap-interface-clock",
+		of_omap_interface_clk_setup);
+#endif
-- 
1.7.9.5

Re: [PATCHv4 23/33] CLK: OMAP: add interface clock support for OMAP3

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> OMAP3 has interface clocks in addition to functional clocks, which
is it just OMAP3?

> require special handling for the autoidle and idle status register
> offsets mainly.

>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/Makefile    |    2 +-
>   drivers/clk/omap/clk.c       |    3 ++
>   drivers/clk/omap/interface.c |  110 ++++++++++++++++++++++++++++++++++++++++++
should this be isolated off for omap3?

>   3 files changed, 114 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/clk/omap/interface.c
>
> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
> index c4e8825..faaeb62 100644
> --- a/drivers/clk/omap/Makefile
> +++ b/drivers/clk/omap/Makefile
> @@ -1,3 +1,3 @@
>   obj-y					+= clk.o dpll.o autoidle.o gate.o \
>   					   clk-44xx.o clk-54xx.o clk-7xx.o \
> -					   clk-33xx.o
> +					   clk-33xx.o interface.o
> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
> index 8c89714..5cbefde 100644
> --- a/drivers/clk/omap/clk.c
> +++ b/drivers/clk/omap/clk.c
> @@ -30,6 +30,9 @@ static const struct of_device_id clk_match[] = {
>   	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
>   	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
>   	{.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
> +	{.compatible = "ti,interface-clock",
> +		.data = of_omap_interface_clk_setup, },

> +	{.compatible = "ti,omap3-dpll-clock", .data = of_omap3_dpll_setup, },
I dont see how this line has anything to do with the patch.
>   	{},
>   };
>
> diff --git a/drivers/clk/omap/interface.c b/drivers/clk/omap/interface.c
> new file mode 100644
> index 0000000..f1f1a1a
> --- /dev/null
> +++ b/drivers/clk/omap/interface.c
> @@ -0,0 +1,110 @@
> +/*
> + * OMAP interface clock support
> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * Tero Kristo <t-kristo@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/string.h>
> +#include <linux/log2.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk/omap.h>
> +
> +#ifdef CONFIG_OF
> +
> +static const struct clk_ops omap_interface_clk_ops = {
> +	.init		= &omap2_init_clk_clkdm,
> +	.enable		= &omap2_dflt_clk_enable,
> +	.disable	= &omap2_dflt_clk_disable,
> +	.is_enabled	= &omap2_dflt_clk_is_enabled,
> +};
> +
> +void __init of_omap_interface_clk_setup(struct device_node *node)
> +{
> +	struct clk *clk;
> +	struct clk_init_data init;
> +	struct clk_hw_omap *clk_hw;
> +	const char *clk_name = node->name;
> +	int num_parents;
> +	const char **parent_names;
> +	int i;
> +	u32 val;
> +
> +	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
> +	if (!clk_hw) {
> +		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
> +		return;
> +	}
> +
> +	clk_hw->hw.init = &init;
> +	clk_hw->ops = &clkhwops_iclk_wait;
> +	clk_hw->enable_reg = of_iomap(node, 0);
> +
> +	if (!of_property_read_u32(node, "ti,enable-bit", &val))
> +		clk_hw->enable_bit = val;
> +
> +	if (of_property_read_bool(node, "ti,iclk-no-wait"))
> +		clk_hw->ops = &clkhwops_iclk;
> +
> +	if (of_property_read_bool(node, "ti,iclk-hsotgusb"))
> +		clk_hw->ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait;
> +
> +	if (of_property_read_bool(node, "ti,iclk-dss"))
> +		clk_hw->ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait;
> +
> +	if (of_property_read_bool(node, "ti,iclk-ssi"))
> +		clk_hw->ops = &clkhwops_omap3430es2_iclk_ssi_wait;
> +
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
> +
> +	init.name = clk_name;
> +	init.ops = &omap_interface_clk_ops;
> +	init.flags = 0;
> +
> +	num_parents = of_clk_get_parent_count(node);
> +	if (num_parents < 1) {
> +		pr_err("%s: omap interface_clk %s must have parent(s)\n",
> +			__func__, node->name);
> +		goto cleanup;
> +	}
> +
> +	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
> +
> +	for (i = 0; i < num_parents; i++)
> +		parent_names[i] = of_clk_get_parent_name(node, i);
> +
> +	init.num_parents = num_parents;
> +	init.parent_names = parent_names;
> +
> +	clk = clk_register(NULL, &clk_hw->hw);
> +
> +	if (!IS_ERR(clk)) {
> +		of_clk_add_provider(node, of_clk_src_simple_get, clk);
> +		omap2_init_clk_hw_omap_clocks(clk);
> +		return;
> +	}
> +
> +cleanup:
the usual stuff about parent name, error checks init = { 0 } etc..

> +	kfree(clk_hw);
> +}
> +EXPORT_SYMBOL(of_omap_interface_clk_setup);
> +CLK_OF_DECLARE(omap_interface_clk, "ti,omap-interface-clock",
> +		of_omap_interface_clk_setup);
> +#endif
>


-- 
Regards,
Nishanth Menon

[PATCHv4 23/33] CLK: OMAP: add interface clock support for OMAP3

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> OMAP3 has interface clocks in addition to functional clocks, which
is it just OMAP3?

> require special handling for the autoidle and idle status register
> offsets mainly.

>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   drivers/clk/omap/Makefile    |    2 +-
>   drivers/clk/omap/clk.c       |    3 ++
>   drivers/clk/omap/interface.c |  110 ++++++++++++++++++++++++++++++++++++++++++
should this be isolated off for omap3?

>   3 files changed, 114 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/clk/omap/interface.c
>
> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
> index c4e8825..faaeb62 100644
> --- a/drivers/clk/omap/Makefile
> +++ b/drivers/clk/omap/Makefile
> @@ -1,3 +1,3 @@
>   obj-y					+= clk.o dpll.o autoidle.o gate.o \
>   					   clk-44xx.o clk-54xx.o clk-7xx.o \
> -					   clk-33xx.o
> +					   clk-33xx.o interface.o
> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
> index 8c89714..5cbefde 100644
> --- a/drivers/clk/omap/clk.c
> +++ b/drivers/clk/omap/clk.c
> @@ -30,6 +30,9 @@ static const struct of_device_id clk_match[] = {
>   	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
>   	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
>   	{.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
> +	{.compatible = "ti,interface-clock",
> +		.data = of_omap_interface_clk_setup, },

> +	{.compatible = "ti,omap3-dpll-clock", .data = of_omap3_dpll_setup, },
I dont see how this line has anything to do with the patch.
>   	{},
>   };
>
> diff --git a/drivers/clk/omap/interface.c b/drivers/clk/omap/interface.c
> new file mode 100644
> index 0000000..f1f1a1a
> --- /dev/null
> +++ b/drivers/clk/omap/interface.c
> @@ -0,0 +1,110 @@
> +/*
> + * OMAP interface clock support
> + *
> + * Copyright (C) 2013 Texas Instruments, Inc.
> + *
> + * Tero Kristo <t-kristo@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/string.h>
> +#include <linux/log2.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk/omap.h>
> +
> +#ifdef CONFIG_OF
> +
> +static const struct clk_ops omap_interface_clk_ops = {
> +	.init		= &omap2_init_clk_clkdm,
> +	.enable		= &omap2_dflt_clk_enable,
> +	.disable	= &omap2_dflt_clk_disable,
> +	.is_enabled	= &omap2_dflt_clk_is_enabled,
> +};
> +
> +void __init of_omap_interface_clk_setup(struct device_node *node)
> +{
> +	struct clk *clk;
> +	struct clk_init_data init;
> +	struct clk_hw_omap *clk_hw;
> +	const char *clk_name = node->name;
> +	int num_parents;
> +	const char **parent_names;
> +	int i;
> +	u32 val;
> +
> +	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
> +	if (!clk_hw) {
> +		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
> +		return;
> +	}
> +
> +	clk_hw->hw.init = &init;
> +	clk_hw->ops = &clkhwops_iclk_wait;
> +	clk_hw->enable_reg = of_iomap(node, 0);
> +
> +	if (!of_property_read_u32(node, "ti,enable-bit", &val))
> +		clk_hw->enable_bit = val;
> +
> +	if (of_property_read_bool(node, "ti,iclk-no-wait"))
> +		clk_hw->ops = &clkhwops_iclk;
> +
> +	if (of_property_read_bool(node, "ti,iclk-hsotgusb"))
> +		clk_hw->ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait;
> +
> +	if (of_property_read_bool(node, "ti,iclk-dss"))
> +		clk_hw->ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait;
> +
> +	if (of_property_read_bool(node, "ti,iclk-ssi"))
> +		clk_hw->ops = &clkhwops_omap3430es2_iclk_ssi_wait;
> +
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +	of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
> +
> +	init.name = clk_name;
> +	init.ops = &omap_interface_clk_ops;
> +	init.flags = 0;
> +
> +	num_parents = of_clk_get_parent_count(node);
> +	if (num_parents < 1) {
> +		pr_err("%s: omap interface_clk %s must have parent(s)\n",
> +			__func__, node->name);
> +		goto cleanup;
> +	}
> +
> +	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
> +
> +	for (i = 0; i < num_parents; i++)
> +		parent_names[i] = of_clk_get_parent_name(node, i);
> +
> +	init.num_parents = num_parents;
> +	init.parent_names = parent_names;
> +
> +	clk = clk_register(NULL, &clk_hw->hw);
> +
> +	if (!IS_ERR(clk)) {
> +		of_clk_add_provider(node, of_clk_src_simple_get, clk);
> +		omap2_init_clk_hw_omap_clocks(clk);
> +		return;
> +	}
> +
> +cleanup:
the usual stuff about parent name, error checks init = { 0 } etc..

> +	kfree(clk_hw);
> +}
> +EXPORT_SYMBOL(of_omap_interface_clk_setup);
> +CLK_OF_DECLARE(omap_interface_clk, "ti,omap-interface-clock",
> +		of_omap_interface_clk_setup);
> +#endif
>


-- 
Regards,
Nishanth Menon

Re: [PATCHv4 23/33] CLK: OMAP: add interface clock support for OMAP3

[Tero Kristo]

On 07/30/2013 11:23 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> OMAP3 has interface clocks in addition to functional clocks, which
> is it just OMAP3?

Yea, only omap3 is using this code. Basically because there is control 
for the module specific interface clocks which is absent from omap4+. 
Personally I think modelling the interface clocks in the first place in 
kernel side was a bad idea, and should have just enabled all of them and 
enable autoidles for them at the same point.

>
>> require special handling for the autoidle and idle status register
>> offsets mainly.
>
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/Makefile    |    2 +-
>>   drivers/clk/omap/clk.c       |    3 ++
>>   drivers/clk/omap/interface.c |  110
>> ++++++++++++++++++++++++++++++++++++++++++
> should this be isolated off for omap3?

You mean within makefile or?

>
>>   3 files changed, 114 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/clk/omap/interface.c
>>
>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>> index c4e8825..faaeb62 100644
>> --- a/drivers/clk/omap/Makefile
>> +++ b/drivers/clk/omap/Makefile
>> @@ -1,3 +1,3 @@
>>   obj-y                    += clk.o dpll.o autoidle.o gate.o \
>>                          clk-44xx.o clk-54xx.o clk-7xx.o \
>> -                       clk-33xx.o
>> +                       clk-33xx.o interface.o
>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>> index 8c89714..5cbefde 100644
>> --- a/drivers/clk/omap/clk.c
>> +++ b/drivers/clk/omap/clk.c
>> @@ -30,6 +30,9 @@ static const struct of_device_id clk_match[] = {
>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>>       {.compatible = "ti,omap4-dpll-clock", .data =
>> of_omap4_dpll_setup, },
>>       {.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
>> +    {.compatible = "ti,interface-clock",
>> +        .data = of_omap_interface_clk_setup, },
>
>> +    {.compatible = "ti,omap3-dpll-clock", .data =
>> of_omap3_dpll_setup, },
> I dont see how this line has anything to do with the patch.

Yea, seems it should have been part of the omap3 dpll introduction one.

>>       {},
>>   };
>>
>> diff --git a/drivers/clk/omap/interface.c b/drivers/clk/omap/interface.c
>> new file mode 100644
>> index 0000000..f1f1a1a
>> --- /dev/null
>> +++ b/drivers/clk/omap/interface.c
>> @@ -0,0 +1,110 @@
>> +/*
>> + * OMAP interface clock support
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * Tero Kristo <t-kristo@ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +#include <linux/string.h>
>> +#include <linux/log2.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk/omap.h>
>> +
>> +#ifdef CONFIG_OF
>> +
>> +static const struct clk_ops omap_interface_clk_ops = {
>> +    .init        = &omap2_init_clk_clkdm,
>> +    .enable        = &omap2_dflt_clk_enable,
>> +    .disable    = &omap2_dflt_clk_disable,
>> +    .is_enabled    = &omap2_dflt_clk_is_enabled,
>> +};
>> +
>> +void __init of_omap_interface_clk_setup(struct device_node *node)
>> +{
>> +    struct clk *clk;
>> +    struct clk_init_data init;
>> +    struct clk_hw_omap *clk_hw;
>> +    const char *clk_name = node->name;
>> +    int num_parents;
>> +    const char **parent_names;
>> +    int i;
>> +    u32 val;
>> +
>> +    clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
>> +    if (!clk_hw) {
>> +        pr_err("%s: could not allocate clk_hw_omap\n", __func__);
>> +        return;
>> +    }
>> +
>> +    clk_hw->hw.init = &init;
>> +    clk_hw->ops = &clkhwops_iclk_wait;
>> +    clk_hw->enable_reg = of_iomap(node, 0);
>> +
>> +    if (!of_property_read_u32(node, "ti,enable-bit", &val))
>> +        clk_hw->enable_bit = val;
>> +
>> +    if (of_property_read_bool(node, "ti,iclk-no-wait"))
>> +        clk_hw->ops = &clkhwops_iclk;
>> +
>> +    if (of_property_read_bool(node, "ti,iclk-hsotgusb"))
>> +        clk_hw->ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait;
>> +
>> +    if (of_property_read_bool(node, "ti,iclk-dss"))
>> +        clk_hw->ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait;
>> +
>> +    if (of_property_read_bool(node, "ti,iclk-ssi"))
>> +        clk_hw->ops = &clkhwops_omap3430es2_iclk_ssi_wait;
>> +
>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>> +    of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
>> +
>> +    init.name = clk_name;
>> +    init.ops = &omap_interface_clk_ops;
>> +    init.flags = 0;
>> +
>> +    num_parents = of_clk_get_parent_count(node);
>> +    if (num_parents < 1) {
>> +        pr_err("%s: omap interface_clk %s must have parent(s)\n",
>> +            __func__, node->name);
>> +        goto cleanup;
>> +    }
>> +
>> +    parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
>> +
>> +    for (i = 0; i < num_parents; i++)
>> +        parent_names[i] = of_clk_get_parent_name(node, i);
>> +
>> +    init.num_parents = num_parents;
>> +    init.parent_names = parent_names;
>> +
>> +    clk = clk_register(NULL, &clk_hw->hw);
>> +
>> +    if (!IS_ERR(clk)) {
>> +        of_clk_add_provider(node, of_clk_src_simple_get, clk);
>> +        omap2_init_clk_hw_omap_clocks(clk);
>> +        return;
>> +    }
>> +
>> +cleanup:
> the usual stuff about parent name, error checks init = { 0 } etc..

Yea, will add those.

>
>> +    kfree(clk_hw);
>> +}
>> +EXPORT_SYMBOL(of_omap_interface_clk_setup);
>> +CLK_OF_DECLARE(omap_interface_clk, "ti,omap-interface-clock",
>> +        of_omap_interface_clk_setup);
>> +#endif
>>
>
>

[PATCHv4 23/33] CLK: OMAP: add interface clock support for OMAP3

[Tero Kristo]

On 07/30/2013 11:23 PM, Nishanth Menon wrote:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>> OMAP3 has interface clocks in addition to functional clocks, which
> is it just OMAP3?

Yea, only omap3 is using this code. Basically because there is control 
for the module specific interface clocks which is absent from omap4+. 
Personally I think modelling the interface clocks in the first place in 
kernel side was a bad idea, and should have just enabled all of them and 
enable autoidles for them at the same point.

>
>> require special handling for the autoidle and idle status register
>> offsets mainly.
>
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/clk/omap/Makefile    |    2 +-
>>   drivers/clk/omap/clk.c       |    3 ++
>>   drivers/clk/omap/interface.c |  110
>> ++++++++++++++++++++++++++++++++++++++++++
> should this be isolated off for omap3?

You mean within makefile or?

>
>>   3 files changed, 114 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/clk/omap/interface.c
>>
>> diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
>> index c4e8825..faaeb62 100644
>> --- a/drivers/clk/omap/Makefile
>> +++ b/drivers/clk/omap/Makefile
>> @@ -1,3 +1,3 @@
>>   obj-y                    += clk.o dpll.o autoidle.o gate.o \
>>                          clk-44xx.o clk-54xx.o clk-7xx.o \
>> -                       clk-33xx.o
>> +                       clk-33xx.o interface.o
>> diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
>> index 8c89714..5cbefde 100644
>> --- a/drivers/clk/omap/clk.c
>> +++ b/drivers/clk/omap/clk.c
>> @@ -30,6 +30,9 @@ static const struct of_device_id clk_match[] = {
>>       {.compatible = "gate-clock", .data = of_gate_clk_setup, },
>>       {.compatible = "ti,omap4-dpll-clock", .data =
>> of_omap4_dpll_setup, },
>>       {.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
>> +    {.compatible = "ti,interface-clock",
>> +        .data = of_omap_interface_clk_setup, },
>
>> +    {.compatible = "ti,omap3-dpll-clock", .data =
>> of_omap3_dpll_setup, },
> I dont see how this line has anything to do with the patch.

Yea, seems it should have been part of the omap3 dpll introduction one.

>>       {},
>>   };
>>
>> diff --git a/drivers/clk/omap/interface.c b/drivers/clk/omap/interface.c
>> new file mode 100644
>> index 0000000..f1f1a1a
>> --- /dev/null
>> +++ b/drivers/clk/omap/interface.c
>> @@ -0,0 +1,110 @@
>> +/*
>> + * OMAP interface clock support
>> + *
>> + * Copyright (C) 2013 Texas Instruments, Inc.
>> + *
>> + * Tero Kristo <t-kristo@ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +#include <linux/string.h>
>> +#include <linux/log2.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk/omap.h>
>> +
>> +#ifdef CONFIG_OF
>> +
>> +static const struct clk_ops omap_interface_clk_ops = {
>> +    .init        = &omap2_init_clk_clkdm,
>> +    .enable        = &omap2_dflt_clk_enable,
>> +    .disable    = &omap2_dflt_clk_disable,
>> +    .is_enabled    = &omap2_dflt_clk_is_enabled,
>> +};
>> +
>> +void __init of_omap_interface_clk_setup(struct device_node *node)
>> +{
>> +    struct clk *clk;
>> +    struct clk_init_data init;
>> +    struct clk_hw_omap *clk_hw;
>> +    const char *clk_name = node->name;
>> +    int num_parents;
>> +    const char **parent_names;
>> +    int i;
>> +    u32 val;
>> +
>> +    clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
>> +    if (!clk_hw) {
>> +        pr_err("%s: could not allocate clk_hw_omap\n", __func__);
>> +        return;
>> +    }
>> +
>> +    clk_hw->hw.init = &init;
>> +    clk_hw->ops = &clkhwops_iclk_wait;
>> +    clk_hw->enable_reg = of_iomap(node, 0);
>> +
>> +    if (!of_property_read_u32(node, "ti,enable-bit", &val))
>> +        clk_hw->enable_bit = val;
>> +
>> +    if (of_property_read_bool(node, "ti,iclk-no-wait"))
>> +        clk_hw->ops = &clkhwops_iclk;
>> +
>> +    if (of_property_read_bool(node, "ti,iclk-hsotgusb"))
>> +        clk_hw->ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait;
>> +
>> +    if (of_property_read_bool(node, "ti,iclk-dss"))
>> +        clk_hw->ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait;
>> +
>> +    if (of_property_read_bool(node, "ti,iclk-ssi"))
>> +        clk_hw->ops = &clkhwops_omap3430es2_iclk_ssi_wait;
>> +
>> +    of_property_read_string(node, "clock-output-names", &clk_name);
>> +    of_property_read_string(node, "ti,clkdm-name", &clk_hw->clkdm_name);
>> +
>> +    init.name = clk_name;
>> +    init.ops = &omap_interface_clk_ops;
>> +    init.flags = 0;
>> +
>> +    num_parents = of_clk_get_parent_count(node);
>> +    if (num_parents < 1) {
>> +        pr_err("%s: omap interface_clk %s must have parent(s)\n",
>> +            __func__, node->name);
>> +        goto cleanup;
>> +    }
>> +
>> +    parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
>> +
>> +    for (i = 0; i < num_parents; i++)
>> +        parent_names[i] = of_clk_get_parent_name(node, i);
>> +
>> +    init.num_parents = num_parents;
>> +    init.parent_names = parent_names;
>> +
>> +    clk = clk_register(NULL, &clk_hw->hw);
>> +
>> +    if (!IS_ERR(clk)) {
>> +        of_clk_add_provider(node, of_clk_src_simple_get, clk);
>> +        omap2_init_clk_hw_omap_clocks(clk);
>> +        return;
>> +    }
>> +
>> +cleanup:
> the usual stuff about parent name, error checks init = { 0 } etc..

Yea, will add those.

>
>> +    kfree(clk_hw);
>> +}
>> +EXPORT_SYMBOL(of_omap_interface_clk_setup);
>> +CLK_OF_DECLARE(omap_interface_clk, "ti,omap-interface-clock",
>> +        of_omap_interface_clk_setup);
>> +#endif
>>
>
>

Re: [PATCHv4 23/33] CLK: OMAP: add interface clock support for OMAP3

[Nishanth Menon]

On 07/31/2013 10:09 AM, Tero Kristo wrote:
> On 07/30/2013 11:23 PM, Nishanth Menon wrote:
>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>> OMAP3 has interface clocks in addition to functional clocks, which
>> is it just OMAP3?
>
> Yea, only omap3 is using this code. Basically because there is control
> for the module specific interface clocks which is absent from omap4+.
> Personally I think modelling the interface clocks in the first place in
> kernel side was a bad idea, and should have just enabled all of them and
> enable autoidles for them at the same point.

Not all autoidles work unfortunately, which is why they got modelled :D 
some even have the weird tendency to hang up L3/L4 interconnect when the 
OCP statemachines required inside the IP block for the autoidle PRCM 
handshake has been, umm... "not well implemented" ;) forcing us to use 
S/w supervised mode of operations.


>
>>
>>> require special handling for the autoidle and idle status register
>>> offsets mainly.
>>
>>>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>> ---
>>>   drivers/clk/omap/Makefile    |    2 +-
>>>   drivers/clk/omap/clk.c       |    3 ++
>>>   drivers/clk/omap/interface.c |  110
>>> ++++++++++++++++++++++++++++++++++++++++++
>> should this be isolated off for omap3?
>
> You mean within makefile or?

omap3-interface-clock.c or something more sensible and Makefile? I dont 
really have any strong opinions on this anyways.. interface.c is fine 
with me as well as the nodes are not probed unless compatible flags are 
set..

just trying to save a few bits in code space by building only if OMAP3 
is present.. /me shrugs..


-- 
Regards,
Nishanth Menon

[PATCHv4 23/33] CLK: OMAP: add interface clock support for OMAP3

[Nishanth Menon]

On 07/31/2013 10:09 AM, Tero Kristo wrote:
> On 07/30/2013 11:23 PM, Nishanth Menon wrote:
>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>> OMAP3 has interface clocks in addition to functional clocks, which
>> is it just OMAP3?
>
> Yea, only omap3 is using this code. Basically because there is control
> for the module specific interface clocks which is absent from omap4+.
> Personally I think modelling the interface clocks in the first place in
> kernel side was a bad idea, and should have just enabled all of them and
> enable autoidles for them at the same point.

Not all autoidles work unfortunately, which is why they got modelled :D 
some even have the weird tendency to hang up L3/L4 interconnect when the 
OCP statemachines required inside the IP block for the autoidle PRCM 
handshake has been, umm... "not well implemented" ;) forcing us to use 
S/w supervised mode of operations.


>
>>
>>> require special handling for the autoidle and idle status register
>>> offsets mainly.
>>
>>>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>> ---
>>>   drivers/clk/omap/Makefile    |    2 +-
>>>   drivers/clk/omap/clk.c       |    3 ++
>>>   drivers/clk/omap/interface.c |  110
>>> ++++++++++++++++++++++++++++++++++++++++++
>> should this be isolated off for omap3?
>
> You mean within makefile or?

omap3-interface-clock.c or something more sensible and Makefile? I dont 
really have any strong opinions on this anyways.. interface.c is fine 
with me as well as the nodes are not probed unless compatible flags are 
set..

just trying to save a few bits in code space by building only if OMAP3 
is present.. /me shrugs..


-- 
Regards,
Nishanth Menon

[PATCHv4 24/33] CLK: OMAP: move some defines from machine to driver header

[Tero Kristo]

This is done in preparation for adding support for OMAP3 clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.h |   10 ----------
 include/linux/clk/omap.h    |   16 ++++++++++++++++
 2 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 6273f14..949d293 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -257,9 +257,6 @@ extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
 
 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
 
-int omap2_dflt_clk_enable(struct clk_hw *hw);
-void omap2_dflt_clk_disable(struct clk_hw *hw);
-int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
 				   void __iomem **other_reg,
 				   u8 *other_bit);
@@ -286,14 +283,7 @@ extern const struct clksel_rate gfx_l3_rates[];
 extern const struct clksel_rate dsp_ick_rates[];
 extern struct clk dummy_ck;
 
-extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
-extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clk_hw_omap_ops clkhwops_iclk;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index c8d9468..24bdd83 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -183,19 +183,35 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
 
+int omap2_dflt_clk_enable(struct clk_hw *hw);
+void omap2_dflt_clk_disable(struct clk_hw *hw);
+int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
+
+int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
+			 unsigned long parent_rate);
+
 int omap2_clk_disable_autoidle_all(void);
 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 
 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_wait;
+extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
+extern const struct clk_hw_omap_ops clkhwops_iclk;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 
 /* DT functions */
 int dt_omap_clk_init(void);
 extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
 void of_omap4_dpll_setup(struct device_node *node);
+void of_omap3_dpll_setup(struct device_node *node);
 void of_omap_fixed_factor_setup(struct device_node *node);
 void of_omap_divider_setup(struct device_node *node);
 void of_omap_gate_clk_setup(struct device_node *node);
+void of_omap_interface_clk_setup(struct device_node *node);
 void of_omap_clk_allow_autoidle_all(void);
 void of_omap_clk_deny_autoidle_all(void);
 
-- 
1.7.9.5

[PATCHv4 24/33] CLK: OMAP: move some defines from machine to driver header

[Tero Kristo]

This is done in preparation for adding support for OMAP3 clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/clock.h |   10 ----------
 include/linux/clk/omap.h    |   16 ++++++++++++++++
 2 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 6273f14..949d293 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -257,9 +257,6 @@ extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
 
 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
 
-int omap2_dflt_clk_enable(struct clk_hw *hw);
-void omap2_dflt_clk_disable(struct clk_hw *hw);
-int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
 				   void __iomem **other_reg,
 				   u8 *other_bit);
@@ -286,14 +283,7 @@ extern const struct clksel_rate gfx_l3_rates[];
 extern const struct clksel_rate dsp_ick_rates[];
 extern struct clk dummy_ck;
 
-extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
-extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clk_hw_omap_ops clkhwops_iclk;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index c8d9468..24bdd83 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -183,19 +183,35 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
 
+int omap2_dflt_clk_enable(struct clk_hw *hw);
+void omap2_dflt_clk_disable(struct clk_hw *hw);
+int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
+
+int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
+			 unsigned long parent_rate);
+
 int omap2_clk_disable_autoidle_all(void);
 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 
 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_wait;
+extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
+extern const struct clk_hw_omap_ops clkhwops_iclk;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 
 /* DT functions */
 int dt_omap_clk_init(void);
 extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
 void of_omap4_dpll_setup(struct device_node *node);
+void of_omap3_dpll_setup(struct device_node *node);
 void of_omap_fixed_factor_setup(struct device_node *node);
 void of_omap_divider_setup(struct device_node *node);
 void of_omap_gate_clk_setup(struct device_node *node);
+void of_omap_interface_clk_setup(struct device_node *node);
 void of_omap_clk_allow_autoidle_all(void);
 void of_omap_clk_deny_autoidle_all(void);
 
-- 
1.7.9.5

[PATCHv4 25/33] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm

[Tero Kristo]

If the main clock for a hwmod is of basic clock type, it is illegal to type
cast this to clk_hw_omap and will result in bogus data. Fixed by checking
the clock flags before attempting the type cast.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5cc5123..a6a59bd 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -656,6 +656,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
 	if (oh->clkdm) {
 		return oh->clkdm;
 	} else if (oh->_clk) {
+		if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
+			return NULL;
 		clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
 		return  clk->clkdm;
 	}
-- 
1.7.9.5

[PATCHv4 25/33] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm

[Tero Kristo]

If the main clock for a hwmod is of basic clock type, it is illegal to type
cast this to clk_hw_omap and will result in bogus data. Fixed by checking
the clock flags before attempting the type cast.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5cc5123..a6a59bd 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -656,6 +656,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
 	if (oh->clkdm) {
 		return oh->clkdm;
 	} else if (oh->_clk) {
+		if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
+			return NULL;
 		clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
 		return  clk->clkdm;
 	}
-- 
1.7.9.5

[PATCHv4 26/33] CLK: omap: gate: add support for OMAP36xx dpllx_mx_ck:s

[Tero Kristo]

OMAP3630 dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
value after their respective PWRDN bits are set.  Any dummy write
(Any other value different from the Read value) to the
corresponding CM_CLKSEL register will refresh the dividers.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/gate.c |   57 ++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 56 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
index b560ff4..50c7f2e 100644
--- a/drivers/clk/omap/gate.c
+++ b/drivers/clk/omap/gate.c
@@ -28,6 +28,10 @@
 
 #ifdef CONFIG_OF
 
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
+
 static const struct clk_ops omap_gate_clkdm_clk_ops = {
 	.init		= &omap2_init_clk_clkdm,
 	.enable		= &omap2_clkops_enable_clkdm,
@@ -41,6 +45,54 @@ static const struct clk_ops omap_gate_clk_ops = {
 	.is_enabled	= &omap2_dflt_clk_is_enabled,
 };
 
+static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap36xx_gate_clk_enable_with_hsdiv_restore,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
+/**
+ * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
+ *         from HSDivider PWRDN problem Implements Errata ID: i556.
+ * @clk: DPLL output struct clk
+ *
+ * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
+ * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
+ * valueafter their respective PWRDN bits are set.  Any dummy write
+ * (Any other value different from the Read value) to the
+ * corresponding CM_CLKSEL register will refresh the dividers.
+ */
+static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
+{
+	struct clk_divider *parent;
+	struct clk_hw *parent_hw;
+	u32 dummy_v, orig_v;
+	int ret;
+
+	/* Clear PWRDN bit of HSDIVIDER */
+	ret = omap2_dflt_clk_enable(clk);
+
+	/* Parent is the x2 node, get parent of parent for the m2 div */
+	parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk)));
+	parent = to_clk_divider(parent_hw);
+
+	/* Restore the dividers */
+	if (!ret) {
+		orig_v = __raw_readl(parent->reg);
+		dummy_v = orig_v;
+
+		/* Write any other value different from the Read value */
+		dummy_v ^= (1 << parent->shift);
+		__raw_writel(dummy_v, parent->reg);
+
+		/* Write the original divider */
+		__raw_writel(orig_v, parent->reg);
+	}
+
+	return ret;
+}
+
 void __init of_omap_gate_clk_setup(struct device_node *node)
 {
 	struct clk *clk;
@@ -70,7 +122,10 @@ void __init of_omap_gate_clk_setup(struct device_node *node)
 		/* No register, clkdm control only */
 		init.ops = &omap_gate_clkdm_clk_ops;
 	} else {
-		init.ops = &omap_gate_clk_ops;
+		if (of_property_read_bool(node, "ti,hsdiv-restore"))
+			init.ops = &omap_gate_clk_hsdiv_restore_ops;
+		else
+			init.ops = &omap_gate_clk_ops;
 		clk_hw->enable_reg = of_iomap(node, 0);
 		of_property_read_u32(node, "ti,enable-bit", &val);
 		clk_hw->enable_bit = val;
-- 
1.7.9.5

[PATCHv4 26/33] CLK: omap: gate: add support for OMAP36xx dpllx_mx_ck:s

[Tero Kristo]

OMAP3630 dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
value after their respective PWRDN bits are set.  Any dummy write
(Any other value different from the Read value) to the
corresponding CM_CLKSEL register will refresh the dividers.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/omap/gate.c |   57 ++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 56 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c
index b560ff4..50c7f2e 100644
--- a/drivers/clk/omap/gate.c
+++ b/drivers/clk/omap/gate.c
@@ -28,6 +28,10 @@
 
 #ifdef CONFIG_OF
 
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
+
 static const struct clk_ops omap_gate_clkdm_clk_ops = {
 	.init		= &omap2_init_clk_clkdm,
 	.enable		= &omap2_clkops_enable_clkdm,
@@ -41,6 +45,54 @@ static const struct clk_ops omap_gate_clk_ops = {
 	.is_enabled	= &omap2_dflt_clk_is_enabled,
 };
 
+static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
+	.init		= &omap2_init_clk_clkdm,
+	.enable		= &omap36xx_gate_clk_enable_with_hsdiv_restore,
+	.disable	= &omap2_dflt_clk_disable,
+	.is_enabled	= &omap2_dflt_clk_is_enabled,
+};
+
+/**
+ * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
+ *         from HSDivider PWRDN problem Implements Errata ID: i556.
+ * @clk: DPLL output struct clk
+ *
+ * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
+ * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
+ * valueafter their respective PWRDN bits are set.  Any dummy write
+ * (Any other value different from the Read value) to the
+ * corresponding CM_CLKSEL register will refresh the dividers.
+ */
+static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
+{
+	struct clk_divider *parent;
+	struct clk_hw *parent_hw;
+	u32 dummy_v, orig_v;
+	int ret;
+
+	/* Clear PWRDN bit of HSDIVIDER */
+	ret = omap2_dflt_clk_enable(clk);
+
+	/* Parent is the x2 node, get parent of parent for the m2 div */
+	parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk)));
+	parent = to_clk_divider(parent_hw);
+
+	/* Restore the dividers */
+	if (!ret) {
+		orig_v = __raw_readl(parent->reg);
+		dummy_v = orig_v;
+
+		/* Write any other value different from the Read value */
+		dummy_v ^= (1 << parent->shift);
+		__raw_writel(dummy_v, parent->reg);
+
+		/* Write the original divider */
+		__raw_writel(orig_v, parent->reg);
+	}
+
+	return ret;
+}
+
 void __init of_omap_gate_clk_setup(struct device_node *node)
 {
 	struct clk *clk;
@@ -70,7 +122,10 @@ void __init of_omap_gate_clk_setup(struct device_node *node)
 		/* No register, clkdm control only */
 		init.ops = &omap_gate_clkdm_clk_ops;
 	} else {
-		init.ops = &omap_gate_clk_ops;
+		if (of_property_read_bool(node, "ti,hsdiv-restore"))
+			init.ops = &omap_gate_clk_hsdiv_restore_ops;
+		else
+			init.ops = &omap_gate_clk_ops;
 		clk_hw->enable_reg = of_iomap(node, 0);
 		of_property_read_u32(node, "ti,enable-bit", &val);
 		clk_hw->enable_bit = val;
-- 
1.7.9.5

[PATCHv4 27/33] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name

[Tero Kristo]

DT clocks are mostly missing clkdm info now, and this causes an issue with
counter32k which makes its slave idlemode wrong and prevents core idle.

Fixed by initializing the hwmod clkdm pointers for omap3 also which makes
sure the clkdm flag matching logic works properly.

This patch also changes the return value for _init_clkdm to 0 for
incorrect clkdm_name, as this a warning, not a fatal error.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index a6a59bd..da26659 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1544,7 +1544,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
 	if (!oh->clkdm) {
 		pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
 			oh->name, oh->clkdm_name);
-		return -EINVAL;
+		return 0;
 	}
 
 	pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
@@ -4115,6 +4115,7 @@ void __init omap_hwmod_init(void)
 		soc_ops.assert_hardreset = _omap2_assert_hardreset;
 		soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
 		soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+		soc_ops.init_clkdm = _init_clkdm;
 	} else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
 		soc_ops.enable_module = _omap4_enable_module;
 		soc_ops.disable_module = _omap4_disable_module;
-- 
1.7.9.5

[PATCHv4 27/33] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name

[Tero Kristo]

DT clocks are mostly missing clkdm info now, and this causes an issue with
counter32k which makes its slave idlemode wrong and prevents core idle.

Fixed by initializing the hwmod clkdm pointers for omap3 also which makes
sure the clkdm flag matching logic works properly.

This patch also changes the return value for _init_clkdm to 0 for
incorrect clkdm_name, as this a warning, not a fatal error.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index a6a59bd..da26659 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1544,7 +1544,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
 	if (!oh->clkdm) {
 		pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
 			oh->name, oh->clkdm_name);
-		return -EINVAL;
+		return 0;
 	}
 
 	pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
@@ -4115,6 +4115,7 @@ void __init omap_hwmod_init(void)
 		soc_ops.assert_hardreset = _omap2_assert_hardreset;
 		soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
 		soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+		soc_ops.init_clkdm = _init_clkdm;
 	} else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
 		soc_ops.enable_module = _omap4_enable_module;
 		soc_ops.disable_module = _omap4_disable_module;
-- 
1.7.9.5

[PATCHv4 28/33] ARM: dts: omap3 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP3 power,
reset and clock manager (PRCM).

TODO: add still missing am35xx only clock nodes

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap3.dtsi                       |    7 +
 arch/arm/boot/dts/omap3430es1-clocks.dtsi          |  166 ++
 arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi    |  240 +++
 arch/arm/boot/dts/omap34xx.dtsi                    |    9 +
 .../omap36xx-am35xx-omap3430es2plus-clocks.dtsi    |  214 +++
 arch/arm/boot/dts/omap36xx-clocks.dtsi             |   97 ++
 .../boot/dts/omap36xx-omap3430es2plus-clocks.dtsi  |  185 +++
 arch/arm/boot/dts/omap36xx.dtsi                    |   10 +
 arch/arm/boot/dts/omap3xxx-clocks.dtsi             | 1594 ++++++++++++++++++++
 9 files changed, 2522 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap3430es1-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap36xx-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap3xxx-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 7d95cda..939cc20 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -533,4 +533,11 @@
 			ram-bits = <12>;
 		};
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap3xxx-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
new file mode 100644
index 0000000..1d85f45
--- /dev/null
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -0,0 +1,166 @@
+/*
+ * Device Tree Source for OMAP3430 ES1 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+gfx_l3_fck: gfx_l3_fck@48004b40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l3_ick>;
+	reg = <0x48004b40 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+gfx_l3_ck: gfx_l3_ck {
+	#clock-cells = <0>;
+	compatible = ;
+};
+
+gfx_l3_ick: gfx_l3_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&gfx_l3_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gfx_cg1_ck: gfx_cg1_ck@48004b00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&gfx_l3_fck>;
+	reg = <0x48004b00 0x4>;
+	ti,clkdm-name = "gfx_3430es1_clkdm";
+	ti,enable-bit = <1>;
+};
+
+gfx_cg2_ck: gfx_cg2_ck@48004b00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&gfx_l3_fck>;
+	reg = <0x48004b00 0x4>;
+	ti,clkdm-name = "gfx_3430es1_clkdm";
+	ti,enable-bit = <2>;
+};
+
+d2d_26m_fck: d2d_26m_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "d2d_clkdm";
+	ti,enable-bit = <3>;
+};
+
+fshostusb_fck: fshostusb_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <5>;
+};
+
+ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&corex2_fck>;
+	bit-shift = <8>;
+	reg = <0x48004a40 0x4>;
+	table = < 1 1 >, < 2 2 >, < 3 3 >, < 4 4 >, < 6 6 >, < 8 8 >;
+	bit-mask = <0xf>;
+};
+
+ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1@48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&ssi_ssr_div_fck_3430es1>;
+	bit-shift = <0>;
+	reg = <0x48004a00 0x4>;
+};
+
+ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&ssi_ssr_fck_3430es1>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l3_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l3_clkdm";
+	ti,enable-bit = <4>;
+	ti,iclk-no-wait;
+};
+
+fac_ick: fac_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <8>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+ssi_ick_3430es1: ssi_ick_3430es1@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&ssi_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-no-wait;
+};
+
+usb_l4_div_ick: usb_l4_div_ick@48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l4_ick>;
+	bit-shift = <4>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+usb_l4_ick: usb_l4_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&usb_l4_div_ick>;
+	bit-shift = <5>;
+	reg = <0x48004a10 0x4>;
+};
+
+dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1@48004e00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m4x2_ck>;
+	reg = <0x48004e00 0x4>;
+	bit-shift = <0>;
+};
+
+dss_ick_3430es1: dss_ick_3430es1@48004e10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l4_ick>;
+	reg = <0x48004e10 0x4>;
+	ti,clkdm-name = "dss_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-no-wait;
+};
diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
new file mode 100644
index 0000000..8da7ba1
--- /dev/null
+++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
@@ -0,0 +1,240 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+security_l4_ick2: security_l4_ick2 {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+aes1_ick: aes1_ick@48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l4_ick2>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <3>;
+};
+
+rng_ick: rng_ick@48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l4_ick2>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <2>;
+};
+
+sha11_ick: sha11_ick@48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l4_ick2>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <1>;
+};
+
+des1_ick: des1_ick@48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l4_ick2>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <0>;
+};
+
+cam_mclk: cam_mclk@48004f00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m5x2_ck>;
+	bit-shift = <0>;
+	reg = <0x48004f00 0x4>;
+	set-rate-parent;
+};
+
+cam_ick: cam_ick@48004f10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l4_ick>;
+	reg = <0x48004f10 0x4>;
+	ti,clkdm-name = "cam_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-no-wait;
+};
+
+csi2_96m_fck: csi2_96m_fck@48004f00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004f00 0x4>;
+	bit-shift = <1>;
+};
+
+security_l3_ick: security_l3_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+pka_ick: pka_ick@48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l3_ick>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <4>;
+};
+
+icr_ick: icr_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <29>;
+};
+
+des2_ick: des2_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <26>;
+};
+
+mspro_ick: mspro_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <23>;
+};
+
+mailboxes_ick: mailboxes_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <7>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sr1_fck: sr1_fck@48004c00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004c00 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <6>;
+};
+
+sr2_fck: sr2_fck@48004c00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004c00 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <7>;
+};
+
+sr_l4_ick: sr_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll2_fck: dpll2_fck@48004040 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&core_ck>;
+	bit-shift = <19>;
+	reg = <0x48004040 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+dpll2_ck: dpll2_ck@48004004 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,modes = <0xa2>;
+	ti,clk-bypass = <&dpll2_fck>;
+	reg = <0x48004004 0x4>, <0x48004024 0x4>, <0x48004034 0x4>, <0x48004040 0x4>;
+	ti,clkdm-name = "dpll2_clkdm";
+	ti,clk-ref = <&sys_ck>;
+	ti,recal-en-bit = <0x8>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x8>;
+};
+
+dpll2_m2_ck: dpll2_m2_ck@48004044 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll2_ck>;
+	reg = <0x48004044 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+iva2_ck: iva2_ck@48004000 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll2_m2_ck>;
+	reg = <0x48004000 0x4>;
+	ti,clkdm-name = "iva2_clkdm";
+	ti,enable-bit = <0>;
+};
+
+modem_fck: modem_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "d2d_clkdm";
+	ti,enable-bit = <31>;
+};
+
+sad2d_ick: sad2d_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l3_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "d2d_clkdm";
+	ti,enable-bit = <3>;
+};
+
+mad2d_ick: mad2d_ick@48004a18 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l3_ick>;
+	reg = <0x48004a18 0x4>;
+	ti,clkdm-name = "d2d_clkdm";
+	ti,enable-bit = <3>;
+};
+
+mspro_fck: mspro_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <23>;
+};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 5355d61..5f3c2ca 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -25,4 +25,13 @@
 			clock-latency = <300000>; /* From legacy driver */
 		};
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap34xx-omap36xx-clocks.dtsi"
+		/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+		/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 0000000..e0bdfb3
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,214 @@
+/*
+ * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dpll5_ck: dpll5_ck@48004d04 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,modes = <0x82>;
+	ti,clk-bypass = <&sys_ck>;
+	reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>;
+	ti,clkdm-name = "dpll5_clkdm";
+	ti,clk-ref = <&sys_ck>;
+	ti,recal-en-bit = <0x19>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x19>;
+};
+
+dpll5_m2_ck: dpll5_m2_ck@48004d50 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll5_ck>;
+	reg = <0x48004d50 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+core_d3_ck: core_d3_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_ck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+core_d4_ck: core_d4_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+core_d6_ck: core_d6_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_ck>;
+	clock-mult = <1>;
+	clock-div = <6>;
+};
+
+omap_192m_alwon_fck: omap_192m_alwon_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+core_d2_ck: core_d2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+corex2_d3_fck: corex2_d3_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&corex2_fck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+corex2_d5_fck: corex2_d5_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&corex2_fck>;
+	clock-mult = <1>;
+	clock-div = <5>;
+};
+
+sgx_mux_fck: sgx_mux_fck@48004b40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
+	reg = <0x48004b40 0x4>;
+	table = <&core_d3_ck 0>, <&core_d4_ck 1>, <&core_d6_ck 2>, <&cm_96m_fck 3>, <&omap_192m_alwon_fck 4>, <&core_d2_ck 5>, <&corex2_d3_fck 6>, <&corex2_d5_fck 7>;
+	bit-mask = <0x7>;
+};
+
+sgx_fck: sgx_fck@48004b00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sgx_mux_fck>;
+	bit-shift = <1>;
+	reg = <0x48004b00 0x4>;
+};
+
+sgx_ick: sgx_ick@48004b10 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&l3_ick>;
+	reg = <0x48004b10 0x4>;
+	ti,clkdm-name = "sgx_clkdm";
+	ti,enable-bit = <0>;
+};
+
+cpefuse_fck: cpefuse_fck@48004a08 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004a08 0x4>;
+	bit-shift = <0>;
+};
+
+ts_fck: ts_fck@48004a08 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&omap_32k_fck>;
+	reg = <0x48004a08 0x4>;
+	bit-shift = <1>;
+};
+
+usbtll_fck: usbtll_fck@48004a08 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll5_m2_ck>;
+	reg = <0x48004a08 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <2>;
+};
+
+usbtll_ick: usbtll_ick@48004a18 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a18 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <2>;
+};
+
+mmchs3_ick: mmchs3_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <30>;
+};
+
+mmchs3_fck: mmchs3_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <30>;
+};
+
+dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m4x2_ck>;
+	reg = <0x48004e00 0x4>;
+	ti,clkdm-name = "dss_clkdm";
+	ti,enable-bit = <0>;
+	ti,dss-clk;
+};
+
+dss_ick_3430es2: dss_ick_3430es2@48004e10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l4_ick>;
+	reg = <0x48004e10 0x4>;
+	ti,clkdm-name = "dss_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-dss;
+};
+
+usbhost_120m_fck: usbhost_120m_fck@48005400 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll5_m2_ck>;
+	reg = <0x48005400 0x4>;
+	bit-shift = <1>;
+};
+
+usbhost_48m_fck: usbhost_48m_fck@48005400 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&omap_48m_fck>;
+	reg = <0x48005400 0x4>;
+	ti,clkdm-name = "usbhost_clkdm";
+	ti,enable-bit = <0>;
+	ti,dss-clk;
+};
+
+usbhost_ick: usbhost_ick@48005410 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l4_ick>;
+	reg = <0x48005410 0x4>;
+	ti,clkdm-name = "usbhost_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-dss;
+};
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
new file mode 100644
index 0000000..a52faa4
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -0,0 +1,97 @@
+/*
+ * Device Tree Source for OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dpll4_ck: dpll4_ck@48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,autoidle-mask = <0x38>;
+	ti,idlest-mask = <0x2>;
+	ti,clkdm-name = "dpll4_clkdm";
+	ti,recal-en-bit = <0x6>;
+	ti,auto-recal-bit = <0x13>;
+	ti,enable-mask = <0x70000>;
+	ti,recal-st-bit = <0x6>;
+	ti,clk-bypass = <&sys_ck>;
+	ti,modes = <0x82>;
+	ti,dco-mask = <0xe00000>;
+	reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>;
+	ti,clk-ref = <&sys_ck>;
+	ti,dpll-j-type;
+	ti,dpll-peripheral;
+};
+
+dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m2x2_mul_ck>;
+	bit-shift = <0x1b>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+	ti,hsdiv-restore;
+};
+
+dpll3_m3x2_ck: dpll3_m3x2_ck@48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll3_m3x2_mul_ck>;
+	bit-shift = <0xc>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+	ti,hsdiv-restore;
+};
+
+dpll4_m3x2_ck: dpll4_m3x2_ck@48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m3x2_mul_ck>;
+	bit-shift = <0x1c>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+	ti,hsdiv-restore;
+};
+
+dpll4_m5x2_ck: dpll4_m5x2_ck@48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m5x2_mul_ck>;
+	bit-shift = <0x1e>;
+	reg = <0x48004d00 0x4>;
+	ti,hsdiv-restore;
+	set-rate-parent;
+	set-bit-to-disable;
+};
+
+dpll4_m6x2_ck: dpll4_m6x2_ck@48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m6x2_mul_ck>;
+	bit-shift = <0x1f>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+	ti,hsdiv-restore;
+};
+
+omap_192m_alwon_fck: omap_192m_alwon_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+uart4_fck: uart4_fck@48005000 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&per_48m_fck>;
+	reg = <0x48005000 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <18>;
+};
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 0000000..0b93647
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,185 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&corex2_fck>;
+	bit-shift = <8>;
+	reg = <0x48004a40 0x4>;
+	table = < 1 1 >, < 2 2 >, < 3 3 >, < 4 4 >, < 6 6 >, < 8 8 >;
+	bit-mask = <0xf>;
+};
+
+ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2@48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&ssi_ssr_div_fck_3430es2>;
+	bit-shift = <0>;
+	reg = <0x48004a00 0x4>;
+};
+
+ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&ssi_ssr_fck_3430es2>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l3_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l3_clkdm";
+	ti,enable-bit = <4>;
+	ti,iclk-hsotgusb;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&ssi_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-ssi;
+};
+
+dpll5_ck: dpll5_ck@48004d04 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,modes = <0x82>;
+	ti,clk-bypass = <&sys_ck>;
+	reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>;
+	ti,clkdm-name = "dpll5_clkdm";
+	ti,clk-ref = <&sys_ck>;
+	ti,recal-en-bit = <0x19>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x19>;
+};
+
+dpll5_m2_ck: dpll5_m2_ck@48004d50 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll5_ck>;
+	reg = <0x48004d50 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll5_m2_d20_ck: dpll5_m2_d20_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll5_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <20>;
+};
+
+sys_d2_ck: sys_d2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+omap_96m_d2_fck: omap_96m_d2_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+omap_96m_d4_fck: omap_96m_d4_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+omap_96m_d8_fck: omap_96m_d8_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+omap_96m_d10_fck: omap_96m_d10_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <10>;
+};
+
+dpll5_m2_d4_ck: dpll5_m2_d4_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll5_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+dpll5_m2_d8_ck: dpll5_m2_d8_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll5_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+dpll5_m2_d16_ck: dpll5_m2_d16_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll5_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+usim_mux_fck: usim_mux_fck@48004c40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_ck>, <&dpll5_m2_d20_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>;
+	bit-shift = <3>;
+	reg = <0x48004c40 0x4>;
+	table = <&sys_ck 1>, <&dpll5_m2_d20_ck 10>, <&sys_d2_ck 2>, <&omap_96m_d2_fck 3>, <&omap_96m_d4_fck 4>, <&omap_96m_d8_fck 5>, <&omap_96m_d10_fck 6>, <&dpll5_m2_d4_ck 7>, <&dpll5_m2_d8_ck 8>, <&dpll5_m2_d16_ck 9>;
+	bit-mask = <0xf>;
+};
+
+usim_fck: usim_fck@48004c00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&usim_mux_fck>;
+	bit-shift = <9>;
+	reg = <0x48004c00 0x4>;
+};
+
+usim_ick: usim_ick@48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <9>;
+};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f8b3765..583c212 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -35,4 +35,14 @@
 			clock-frequency = <48000000>;
 		};
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap36xx-clocks.dtsi"
+		/include/ "omap34xx-omap36xx-clocks.dtsi"
+		/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+		/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
new file mode 100644
index 0000000..18a723f
--- /dev/null
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -0,0 +1,1594 @@
+/*
+ * Device Tree Source for OMAP3 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dummy_apb_pclk: dummy_apb_pclk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0x0>;
+};
+
+omap_32k_fck: omap_32k_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_12m_ck: virt_12m_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+virt_13m_ck: virt_13m_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <13000000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+virt_38_4m_ck: virt_38_4m_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <38400000>;
+};
+
+virt_16_8m_ck: virt_16_8m_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <16800000>;
+};
+
+osc_sys_ck: osc_sys_ck@48306d40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
+	reg = <0x48306d40 0x4>;
+	bit-mask = <0x7>;
+};
+
+sys_ck: sys_ck@48307270 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&osc_sys_ck>;
+	bit-shift = <6>;
+	reg = <0x48307270 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+dpll4_ck: dpll4_ck@48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,autoidle-mask = <0x38>;
+	ti,modes = <0x82>;
+	ti,clk-bypass = <&sys_ck>;
+	ti,idlest-mask = <0x2>;
+	reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>;
+	ti,clkdm-name = "dpll4_clkdm";
+	ti,clk-ref = <&sys_ck>;
+	ti,recal-en-bit = <0x6>;
+	ti,auto-recal-bit = <0x13>;
+	ti,enable-mask = <0x70000>;
+	ti,recal-st-bit = <0x6>;
+	ti,dpll-peripheral;
+};
+
+dpll4_m2_ck: dpll4_m2_ck@48004d48 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	reg = <0x48004d48 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m2_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m2x2_mul_ck>;
+	bit-shift = <0x1b>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+omap_96m_alwon_fck: omap_96m_alwon_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll3_ck: dpll3_ck@48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,clk-bypass = <&sys_ck>;
+	reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d40 0x4>;
+	ti,clk-ref = <&sys_ck>;
+	ti,clkdm-name = "dpll3_clkdm";
+	ti,recal-en-bit = <0x5>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x5>;
+	ti,dpll-core;
+};
+
+dpll3_m3_ck: dpll3_m3_ck@48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll3_ck>;
+	bit-shift = <16>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m3_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll3_m3x2_ck: dpll3_m3x2_ck@48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll3_m3x2_mul_ck>;
+	bit-shift = <0xc>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+emu_core_alwon_ck: emu_core_alwon_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sys_altclk: sys_altclk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0x0>;
+};
+
+mcbsp_clks: mcbsp_clks {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0x0>;
+};
+
+sys_clkout1: sys_clkout1@48306d70 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&osc_sys_ck>;
+	reg = <0x48306d70 0x4>;
+	bit-shift = <7>;
+};
+
+dpll1_ck: dpll1_ck@48004904 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,clk-bypass = <&dpll1_fck>;
+	reg = <0x48004904 0x4>, <0x48004924 0x4>, <0x48004934 0x4>, <0x48004940 0x4>;
+	ti,clk-ref = <&sys_ck>;
+	ti,clkdm-name = "dpll1_clkdm";
+	ti,recal-en-bit = <0x7>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x7>;
+};
+
+dpll1_x2_ck: dpll1_x2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll1_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll1_x2m2_ck: dpll1_x2m2_ck@48004944 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll1_x2_ck>;
+	reg = <0x48004944 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll3_m2_ck: dpll3_m2_ck@48004d40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll3_ck>;
+	bit-shift = <27>;
+	reg = <0x48004d40 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+core_ck: core_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll3_x2_ck: dpll3_x2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll3_m2x2_ck: dpll3_m2x2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m2_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_x2_ck: dpll4_x2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+cm_96m_fck: cm_96m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_alwon_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+omap_96m_fck: omap_96m_fck@48004d40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&cm_96m_fck>, <&sys_ck>;
+	bit-shift = <6>;
+	reg = <0x48004d40 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll4_m3_ck: dpll4_m3_ck@48004e40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	bit-shift = <8>;
+	reg = <0x48004e40 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m3_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m3x2_ck: dpll4_m3x2_ck@48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m3x2_mul_ck>;
+	bit-shift = <0x1c>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+omap_54m_fck: omap_54m_fck@48004d40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
+	bit-shift = <5>;
+	reg = <0x48004d40 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm_96m_d2_fck: cm_96m_d2_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&cm_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+omap_48m_fck: omap_48m_fck@48004d40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
+	bit-shift = <3>;
+	reg = <0x48004d40 0x4>;
+	table = <&cm_96m_d2_fck 0>, <&sys_altclk 1>;
+	bit-mask = <0x1>;
+};
+
+omap_12m_fck: omap_12m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_48m_fck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+dpll4_m4_ck: dpll4_m4_ck@48004e40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	reg = <0x48004e40 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m4_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m4x2_ck: dpll4_m4x2_ck@48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m4x2_mul_ck>;
+	bit-shift = <0x1d>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+dpll4_m5_ck: dpll4_m5_ck@48004f40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	reg = <0x48004f40 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m5_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m5x2_ck: dpll4_m5x2_ck@48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m5x2_mul_ck>;
+	bit-shift = <0x1e>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+dpll4_m6_ck: dpll4_m6_ck@48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	bit-shift = <24>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m6_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m6x2_ck: dpll4_m6x2_ck@48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m6x2_mul_ck>;
+	bit-shift = <0x1f>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+emu_per_alwon_ck: emu_per_alwon_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m6x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+clkout2_src_mux_ck: clkout2_src_mux_ck@48004d70 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
+	reg = <0x48004d70 0x4>;
+	bit-mask = <0x3>;
+};
+
+clkout2_src_ck: clkout2_src_ck@48004d70 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkout2_src_mux_ck>;
+	bit-shift = <7>;
+	reg = <0x48004d70 0x4>;
+};
+
+sys_clkout2: sys_clkout2@48004d70 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&clkout2_src_ck>;
+	bit-shift = <3>;
+	reg = <0x48004d70 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+corex2_fck: corex2_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll1_fck: dpll1_fck@48004940 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&core_ck>;
+	bit-shift = <19>;
+	reg = <0x48004940 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+mpu_ck: mpu_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll1_x2m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+arm_fck: arm_fck@48004924 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mpu_ck>;
+	reg = <0x48004924 0x4>;
+	bit-mask = <0x1>;
+};
+
+emu_mpu_alwon_ck: emu_mpu_alwon_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&mpu_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3_ick: l3_ick@48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&core_ck>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+l4_ick: l4_ick@48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l3_ick>;
+	bit-shift = <2>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+rm_ick: rm_ick@48004c40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l4_ick>;
+	bit-shift = <1>;
+	reg = <0x48004c40 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+gpt10_mux_fck: gpt10_mux_fck@48004a40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <6>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt10_fck: gpt10_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt10_mux_fck>;
+	bit-shift = <11>;
+	reg = <0x48004a00 0x4>;
+};
+
+gpt11_mux_fck: gpt11_mux_fck@48004a40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <7>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt11_fck: gpt11_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt11_mux_fck>;
+	bit-shift = <12>;
+	reg = <0x48004a00 0x4>;
+};
+
+core_96m_fck: core_96m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mmchs2_fck: mmchs2_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <25>;
+};
+
+mmchs1_fck: mmchs1_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <24>;
+};
+
+i2c3_fck: i2c3_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <17>;
+};
+
+i2c2_fck: i2c2_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <16>;
+};
+
+i2c1_fck: i2c1_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <15>;
+};
+
+mcbsp5_mux_fck: mcbsp5_mux_fck@480022d8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&core_96m_fck>, <&mcbsp_clks>;
+	bit-shift = <4>;
+	reg = <0x480022d8 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp5_fck: mcbsp5_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp5_mux_fck>;
+	bit-shift = <10>;
+	reg = <0x48004a00 0x4>;
+};
+
+mcbsp1_mux_fck: mcbsp1_mux_fck@48002274 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&core_96m_fck>, <&mcbsp_clks>;
+	bit-shift = <2>;
+	reg = <0x48002274 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp1_fck: mcbsp1_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp1_mux_fck>;
+	bit-shift = <9>;
+	reg = <0x48004a00 0x4>;
+};
+
+core_48m_fck: core_48m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_48m_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mcspi4_fck: mcspi4_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <21>;
+};
+
+mcspi3_fck: mcspi3_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <20>;
+};
+
+mcspi2_fck: mcspi2_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <19>;
+};
+
+mcspi1_fck: mcspi1_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <18>;
+};
+
+uart2_fck: uart2_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <14>;
+};
+
+uart1_fck: uart1_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <13>;
+};
+
+core_12m_fck: core_12m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_12m_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+hdq_fck: hdq_fck@48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_12m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <22>;
+};
+
+core_l3_ick: core_l3_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sdrc_ick: sdrc_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_l3_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l3_clkdm";
+	ti,enable-bit = <1>;
+};
+
+gpmc_fck: gpmc_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_l3_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+core_l4_ick: core_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mmchs2_ick: mmchs2_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <25>;
+};
+
+mmchs1_ick: mmchs1_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <24>;
+};
+
+hdq_ick: hdq_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <22>;
+};
+
+mcspi4_ick: mcspi4_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <21>;
+};
+
+mcspi3_ick: mcspi3_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <20>;
+};
+
+mcspi2_ick: mcspi2_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <19>;
+};
+
+mcspi1_ick: mcspi1_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <18>;
+};
+
+i2c3_ick: i2c3_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <17>;
+};
+
+i2c2_ick: i2c2_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <16>;
+};
+
+i2c1_ick: i2c1_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <15>;
+};
+
+uart2_ick: uart2_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <14>;
+};
+
+uart1_ick: uart1_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <13>;
+};
+
+gpt11_ick: gpt11_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <12>;
+};
+
+gpt10_ick: gpt10_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <11>;
+};
+
+mcbsp5_ick: mcbsp5_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <10>;
+};
+
+mcbsp1_ick: mcbsp1_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <9>;
+};
+
+omapctrl_ick: omapctrl_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <6>;
+};
+
+dss_tv_fck: dss_tv_fck@48004e00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&omap_54m_fck>;
+	reg = <0x48004e00 0x4>;
+	bit-shift = <2>;
+};
+
+dss_96m_fck: dss_96m_fck@48004e00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&omap_96m_fck>;
+	reg = <0x48004e00 0x4>;
+	bit-shift = <2>;
+};
+
+dss2_alwon_fck: dss2_alwon_fck@48004e00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004e00 0x4>;
+	bit-shift = <1>;
+};
+
+gpt1_mux_fck: gpt1_mux_fck@48004c40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	reg = <0x48004c40 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt1_fck: gpt1_fck@48004c00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt1_mux_fck>;
+	bit-shift = <0>;
+	reg = <0x48004c00 0x4>;
+};
+
+aes2_ick: aes2_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <28>;
+};
+
+wkup_32k_fck: wkup_32k_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_32k_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gpio1_dbck: gpio1_dbck@48004c00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&wkup_32k_fck>;
+	reg = <0x48004c00 0x4>;
+	bit-shift = <3>;
+};
+
+sha12_ick: sha12_ick@48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <27>;
+};
+
+wdt2_fck: wdt2_fck@48004c00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&wkup_32k_fck>;
+	reg = <0x48004c00 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <5>;
+};
+
+wkup_l4_ick: wkup_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+wdt2_ick: wdt2_ick@48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <5>;
+};
+
+wdt1_ick: wdt1_ick@48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <4>;
+};
+
+gpio1_ick: gpio1_ick@48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <3>;
+};
+
+omap_32ksync_ick: omap_32ksync_ick@48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <2>;
+};
+
+gpt12_ick: gpt12_ick@48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <1>;
+};
+
+gpt1_ick: gpt1_ick@48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <0>;
+};
+
+per_96m_fck: per_96m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_alwon_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+per_48m_fck: per_48m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_48m_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+uart3_fck: uart3_fck@48005000 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&per_48m_fck>;
+	reg = <0x48005000 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <11>;
+};
+
+gpt2_mux_fck: gpt2_mux_fck@48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt2_fck: gpt2_fck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt2_mux_fck>;
+	bit-shift = <3>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt3_mux_fck: gpt3_mux_fck@48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <1>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt3_fck: gpt3_fck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt3_mux_fck>;
+	bit-shift = <4>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt4_mux_fck: gpt4_mux_fck@48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <2>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt4_fck: gpt4_fck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt4_mux_fck>;
+	bit-shift = <5>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt5_mux_fck: gpt5_mux_fck@48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <3>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt5_fck: gpt5_fck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt5_mux_fck>;
+	bit-shift = <6>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt6_mux_fck: gpt6_mux_fck@48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <4>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt6_fck: gpt6_fck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt6_mux_fck>;
+	bit-shift = <7>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt7_mux_fck: gpt7_mux_fck@48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <5>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt7_fck: gpt7_fck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt7_mux_fck>;
+	bit-shift = <8>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt8_mux_fck: gpt8_mux_fck@48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <6>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt8_fck: gpt8_fck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt8_mux_fck>;
+	bit-shift = <9>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt9_mux_fck: gpt9_mux_fck@48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <7>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt9_fck: gpt9_fck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt9_mux_fck>;
+	bit-shift = <10>;
+	reg = <0x48005000 0x4>;
+};
+
+per_32k_alwon_fck: per_32k_alwon_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_32k_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gpio6_dbck: gpio6_dbck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <17>;
+};
+
+gpio5_dbck: gpio5_dbck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <16>;
+};
+
+gpio4_dbck: gpio4_dbck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <15>;
+};
+
+gpio3_dbck: gpio3_dbck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <14>;
+};
+
+gpio2_dbck: gpio2_dbck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <13>;
+};
+
+wdt3_fck: wdt3_fck@48005000 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <12>;
+};
+
+per_l4_ick: per_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gpio6_ick: gpio6_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <17>;
+};
+
+gpio5_ick: gpio5_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <16>;
+};
+
+gpio4_ick: gpio4_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <15>;
+};
+
+gpio3_ick: gpio3_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <14>;
+};
+
+gpio2_ick: gpio2_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <13>;
+};
+
+wdt3_ick: wdt3_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <12>;
+};
+
+uart3_ick: uart3_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <11>;
+};
+
+uart4_ick: uart4_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <18>;
+};
+
+gpt9_ick: gpt9_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <10>;
+};
+
+gpt8_ick: gpt8_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <9>;
+};
+
+gpt7_ick: gpt7_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <8>;
+};
+
+gpt6_ick: gpt6_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <7>;
+};
+
+gpt5_ick: gpt5_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <6>;
+};
+
+gpt4_ick: gpt4_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <5>;
+};
+
+gpt3_ick: gpt3_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <4>;
+};
+
+gpt2_ick: gpt2_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <3>;
+};
+
+mcbsp2_ick: mcbsp2_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <0>;
+};
+
+mcbsp3_ick: mcbsp3_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <1>;
+};
+
+mcbsp4_ick: mcbsp4_ick@48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <2>;
+};
+
+mcbsp2_mux_fck: mcbsp2_mux_fck@48002274 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_96m_fck>, <&mcbsp_clks>;
+	bit-shift = <6>;
+	reg = <0x48002274 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp2_fck: mcbsp2_fck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp2_mux_fck>;
+	bit-shift = <0>;
+	reg = <0x48005000 0x4>;
+};
+
+mcbsp3_mux_fck: mcbsp3_mux_fck@480022d8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_96m_fck>, <&mcbsp_clks>;
+	reg = <0x480022d8 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp3_fck: mcbsp3_fck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp3_mux_fck>;
+	bit-shift = <1>;
+	reg = <0x48005000 0x4>;
+};
+
+mcbsp4_mux_fck: mcbsp4_mux_fck@480022d8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_96m_fck>, <&mcbsp_clks>;
+	bit-shift = <2>;
+	reg = <0x480022d8 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp4_fck: mcbsp4_fck@48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp4_mux_fck>;
+	bit-shift = <2>;
+	reg = <0x48005000 0x4>;
+};
+
+emu_src_mux_ck: emu_src_mux_ck@48005140 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3>;
+};
+
+emu_src_ck: emu_src_ck {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&emu_src_mux_ck>;
+	ti,clkdm-name = "emu_clkdm";
+};
+
+pclk_fck: pclk_fck@48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&emu_src_ck>;
+	bit-shift = <8>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+pclkx2_fck: pclkx2_fck@48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&emu_src_ck>;
+	bit-shift = <6>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+atclk_fck: atclk_fck@48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&emu_src_ck>;
+	bit-shift = <4>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+traceclk_src_fck: traceclk_src_fck@48005140 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+	bit-shift = <2>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3>;
+};
+
+traceclk_fck: traceclk_fck@48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&traceclk_src_fck>;
+	bit-shift = <11>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+secure_32k_fck: secure_32k_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+gpt12_fck: gpt12_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&secure_32k_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+wdt1_fck: wdt1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&secure_32k_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
-- 
1.7.9.5

[PATCHv4 28/33] ARM: dts: omap3 clock data

[Tero Kristo]

This patch creates a unique node for each clock in the OMAP3 power,
reset and clock manager (PRCM).

TODO: add still missing am35xx only clock nodes

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap3.dtsi                       |    7 +
 arch/arm/boot/dts/omap3430es1-clocks.dtsi          |  166 ++
 arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi    |  240 +++
 arch/arm/boot/dts/omap34xx.dtsi                    |    9 +
 .../omap36xx-am35xx-omap3430es2plus-clocks.dtsi    |  214 +++
 arch/arm/boot/dts/omap36xx-clocks.dtsi             |   97 ++
 .../boot/dts/omap36xx-omap3430es2plus-clocks.dtsi  |  185 +++
 arch/arm/boot/dts/omap36xx.dtsi                    |   10 +
 arch/arm/boot/dts/omap3xxx-clocks.dtsi             | 1594 ++++++++++++++++++++
 9 files changed, 2522 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap3430es1-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap36xx-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
 create mode 100644 arch/arm/boot/dts/omap3xxx-clocks.dtsi

diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 7d95cda..939cc20 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -533,4 +533,11 @@
 			ram-bits = <12>;
 		};
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap3xxx-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
new file mode 100644
index 0000000..1d85f45
--- /dev/null
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -0,0 +1,166 @@
+/*
+ * Device Tree Source for OMAP3430 ES1 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+gfx_l3_fck: gfx_l3_fck at 48004b40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l3_ick>;
+	reg = <0x48004b40 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+gfx_l3_ck: gfx_l3_ck {
+	#clock-cells = <0>;
+	compatible = ;
+};
+
+gfx_l3_ick: gfx_l3_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&gfx_l3_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gfx_cg1_ck: gfx_cg1_ck at 48004b00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&gfx_l3_fck>;
+	reg = <0x48004b00 0x4>;
+	ti,clkdm-name = "gfx_3430es1_clkdm";
+	ti,enable-bit = <1>;
+};
+
+gfx_cg2_ck: gfx_cg2_ck at 48004b00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&gfx_l3_fck>;
+	reg = <0x48004b00 0x4>;
+	ti,clkdm-name = "gfx_3430es1_clkdm";
+	ti,enable-bit = <2>;
+};
+
+d2d_26m_fck: d2d_26m_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "d2d_clkdm";
+	ti,enable-bit = <3>;
+};
+
+fshostusb_fck: fshostusb_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <5>;
+};
+
+ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 at 48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&corex2_fck>;
+	bit-shift = <8>;
+	reg = <0x48004a40 0x4>;
+	table = < 1 1 >, < 2 2 >, < 3 3 >, < 4 4 >, < 6 6 >, < 8 8 >;
+	bit-mask = <0xf>;
+};
+
+ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&ssi_ssr_div_fck_3430es1>;
+	bit-shift = <0>;
+	reg = <0x48004a00 0x4>;
+};
+
+ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&ssi_ssr_fck_3430es1>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l3_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l3_clkdm";
+	ti,enable-bit = <4>;
+	ti,iclk-no-wait;
+};
+
+fac_ick: fac_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <8>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+ssi_ick_3430es1: ssi_ick_3430es1 at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&ssi_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-no-wait;
+};
+
+usb_l4_div_ick: usb_l4_div_ick at 48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l4_ick>;
+	bit-shift = <4>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+usb_l4_ick: usb_l4_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&usb_l4_div_ick>;
+	bit-shift = <5>;
+	reg = <0x48004a10 0x4>;
+};
+
+dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 at 48004e00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m4x2_ck>;
+	reg = <0x48004e00 0x4>;
+	bit-shift = <0>;
+};
+
+dss_ick_3430es1: dss_ick_3430es1 at 48004e10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l4_ick>;
+	reg = <0x48004e10 0x4>;
+	ti,clkdm-name = "dss_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-no-wait;
+};
diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
new file mode 100644
index 0000000..8da7ba1
--- /dev/null
+++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
@@ -0,0 +1,240 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+security_l4_ick2: security_l4_ick2 {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+aes1_ick: aes1_ick at 48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l4_ick2>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <3>;
+};
+
+rng_ick: rng_ick at 48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l4_ick2>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <2>;
+};
+
+sha11_ick: sha11_ick at 48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l4_ick2>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <1>;
+};
+
+des1_ick: des1_ick at 48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l4_ick2>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <0>;
+};
+
+cam_mclk: cam_mclk at 48004f00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m5x2_ck>;
+	bit-shift = <0>;
+	reg = <0x48004f00 0x4>;
+	set-rate-parent;
+};
+
+cam_ick: cam_ick at 48004f10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l4_ick>;
+	reg = <0x48004f10 0x4>;
+	ti,clkdm-name = "cam_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-no-wait;
+};
+
+csi2_96m_fck: csi2_96m_fck at 48004f00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004f00 0x4>;
+	bit-shift = <1>;
+};
+
+security_l3_ick: security_l3_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+pka_ick: pka_ick at 48004a14 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&security_l3_ick>;
+	reg = <0x48004a14 0x4>;
+	ti,enable-bit = <4>;
+};
+
+icr_ick: icr_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <29>;
+};
+
+des2_ick: des2_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <26>;
+};
+
+mspro_ick: mspro_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <23>;
+};
+
+mailboxes_ick: mailboxes_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <7>;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sr1_fck: sr1_fck at 48004c00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004c00 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <6>;
+};
+
+sr2_fck: sr2_fck at 48004c00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004c00 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <7>;
+};
+
+sr_l4_ick: sr_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll2_fck: dpll2_fck at 48004040 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&core_ck>;
+	bit-shift = <19>;
+	reg = <0x48004040 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+dpll2_ck: dpll2_ck at 48004004 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,modes = <0xa2>;
+	ti,clk-bypass = <&dpll2_fck>;
+	reg = <0x48004004 0x4>, <0x48004024 0x4>, <0x48004034 0x4>, <0x48004040 0x4>;
+	ti,clkdm-name = "dpll2_clkdm";
+	ti,clk-ref = <&sys_ck>;
+	ti,recal-en-bit = <0x8>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x8>;
+};
+
+dpll2_m2_ck: dpll2_m2_ck at 48004044 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll2_ck>;
+	reg = <0x48004044 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+iva2_ck: iva2_ck at 48004000 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll2_m2_ck>;
+	reg = <0x48004000 0x4>;
+	ti,clkdm-name = "iva2_clkdm";
+	ti,enable-bit = <0>;
+};
+
+modem_fck: modem_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "d2d_clkdm";
+	ti,enable-bit = <31>;
+};
+
+sad2d_ick: sad2d_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l3_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "d2d_clkdm";
+	ti,enable-bit = <3>;
+};
+
+mad2d_ick: mad2d_ick at 48004a18 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l3_ick>;
+	reg = <0x48004a18 0x4>;
+	ti,clkdm-name = "d2d_clkdm";
+	ti,enable-bit = <3>;
+};
+
+mspro_fck: mspro_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <23>;
+};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 5355d61..5f3c2ca 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -25,4 +25,13 @@
 			clock-latency = <300000>; /* From legacy driver */
 		};
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap34xx-omap36xx-clocks.dtsi"
+		/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+		/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 0000000..e0bdfb3
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,214 @@
+/*
+ * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dpll5_ck: dpll5_ck at 48004d04 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,modes = <0x82>;
+	ti,clk-bypass = <&sys_ck>;
+	reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>;
+	ti,clkdm-name = "dpll5_clkdm";
+	ti,clk-ref = <&sys_ck>;
+	ti,recal-en-bit = <0x19>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x19>;
+};
+
+dpll5_m2_ck: dpll5_m2_ck at 48004d50 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll5_ck>;
+	reg = <0x48004d50 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+core_d3_ck: core_d3_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_ck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+core_d4_ck: core_d4_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+core_d6_ck: core_d6_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_ck>;
+	clock-mult = <1>;
+	clock-div = <6>;
+};
+
+omap_192m_alwon_fck: omap_192m_alwon_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+core_d2_ck: core_d2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+corex2_d3_fck: corex2_d3_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&corex2_fck>;
+	clock-mult = <1>;
+	clock-div = <3>;
+};
+
+corex2_d5_fck: corex2_d5_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&corex2_fck>;
+	clock-mult = <1>;
+	clock-div = <5>;
+};
+
+sgx_mux_fck: sgx_mux_fck at 48004b40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
+	reg = <0x48004b40 0x4>;
+	table = <&core_d3_ck 0>, <&core_d4_ck 1>, <&core_d6_ck 2>, <&cm_96m_fck 3>, <&omap_192m_alwon_fck 4>, <&core_d2_ck 5>, <&corex2_d3_fck 6>, <&corex2_d5_fck 7>;
+	bit-mask = <0x7>;
+};
+
+sgx_fck: sgx_fck at 48004b00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sgx_mux_fck>;
+	bit-shift = <1>;
+	reg = <0x48004b00 0x4>;
+};
+
+sgx_ick: sgx_ick at 48004b10 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&l3_ick>;
+	reg = <0x48004b10 0x4>;
+	ti,clkdm-name = "sgx_clkdm";
+	ti,enable-bit = <0>;
+};
+
+cpefuse_fck: cpefuse_fck at 48004a08 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004a08 0x4>;
+	bit-shift = <0>;
+};
+
+ts_fck: ts_fck at 48004a08 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&omap_32k_fck>;
+	reg = <0x48004a08 0x4>;
+	bit-shift = <1>;
+};
+
+usbtll_fck: usbtll_fck at 48004a08 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll5_m2_ck>;
+	reg = <0x48004a08 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <2>;
+};
+
+usbtll_ick: usbtll_ick at 48004a18 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a18 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <2>;
+};
+
+mmchs3_ick: mmchs3_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <30>;
+};
+
+mmchs3_fck: mmchs3_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <30>;
+};
+
+dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 at 48004e00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m4x2_ck>;
+	reg = <0x48004e00 0x4>;
+	ti,clkdm-name = "dss_clkdm";
+	ti,enable-bit = <0>;
+	ti,dss-clk;
+};
+
+dss_ick_3430es2: dss_ick_3430es2 at 48004e10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l4_ick>;
+	reg = <0x48004e10 0x4>;
+	ti,clkdm-name = "dss_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-dss;
+};
+
+usbhost_120m_fck: usbhost_120m_fck at 48005400 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll5_m2_ck>;
+	reg = <0x48005400 0x4>;
+	bit-shift = <1>;
+};
+
+usbhost_48m_fck: usbhost_48m_fck at 48005400 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&omap_48m_fck>;
+	reg = <0x48005400 0x4>;
+	ti,clkdm-name = "usbhost_clkdm";
+	ti,enable-bit = <0>;
+	ti,dss-clk;
+};
+
+usbhost_ick: usbhost_ick at 48005410 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&l4_ick>;
+	reg = <0x48005410 0x4>;
+	ti,clkdm-name = "usbhost_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-dss;
+};
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
new file mode 100644
index 0000000..a52faa4
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -0,0 +1,97 @@
+/*
+ * Device Tree Source for OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dpll4_ck: dpll4_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,autoidle-mask = <0x38>;
+	ti,idlest-mask = <0x2>;
+	ti,clkdm-name = "dpll4_clkdm";
+	ti,recal-en-bit = <0x6>;
+	ti,auto-recal-bit = <0x13>;
+	ti,enable-mask = <0x70000>;
+	ti,recal-st-bit = <0x6>;
+	ti,clk-bypass = <&sys_ck>;
+	ti,modes = <0x82>;
+	ti,dco-mask = <0xe00000>;
+	reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>;
+	ti,clk-ref = <&sys_ck>;
+	ti,dpll-j-type;
+	ti,dpll-peripheral;
+};
+
+dpll4_m2x2_ck: dpll4_m2x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m2x2_mul_ck>;
+	bit-shift = <0x1b>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+	ti,hsdiv-restore;
+};
+
+dpll3_m3x2_ck: dpll3_m3x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll3_m3x2_mul_ck>;
+	bit-shift = <0xc>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+	ti,hsdiv-restore;
+};
+
+dpll4_m3x2_ck: dpll4_m3x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m3x2_mul_ck>;
+	bit-shift = <0x1c>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+	ti,hsdiv-restore;
+};
+
+dpll4_m5x2_ck: dpll4_m5x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m5x2_mul_ck>;
+	bit-shift = <0x1e>;
+	reg = <0x48004d00 0x4>;
+	ti,hsdiv-restore;
+	set-rate-parent;
+	set-bit-to-disable;
+};
+
+dpll4_m6x2_ck: dpll4_m6x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&dpll4_m6x2_mul_ck>;
+	bit-shift = <0x1f>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+	ti,hsdiv-restore;
+};
+
+omap_192m_alwon_fck: omap_192m_alwon_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+uart4_fck: uart4_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&per_48m_fck>;
+	reg = <0x48005000 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <18>;
+};
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 0000000..0b93647
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,185 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 at 48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&corex2_fck>;
+	bit-shift = <8>;
+	reg = <0x48004a40 0x4>;
+	table = < 1 1 >, < 2 2 >, < 3 3 >, < 4 4 >, < 6 6 >, < 8 8 >;
+	bit-mask = <0xf>;
+};
+
+ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&ssi_ssr_div_fck_3430es2>;
+	bit-shift = <0>;
+	reg = <0x48004a00 0x4>;
+};
+
+ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&ssi_ssr_fck_3430es2>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l3_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l3_clkdm";
+	ti,enable-bit = <4>;
+	ti,iclk-hsotgusb;
+};
+
+ssi_l4_ick: ssi_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+ssi_ick_3430es2: ssi_ick_3430es2 at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&ssi_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <0>;
+	ti,iclk-ssi;
+};
+
+dpll5_ck: dpll5_ck at 48004d04 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,modes = <0x82>;
+	ti,clk-bypass = <&sys_ck>;
+	reg = <0x48004d04 0x4>, <0x48004d24 0x4>, <0x48004d34 0x4>, <0x48004d4c 0x4>;
+	ti,clkdm-name = "dpll5_clkdm";
+	ti,clk-ref = <&sys_ck>;
+	ti,recal-en-bit = <0x19>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x19>;
+};
+
+dpll5_m2_ck: dpll5_m2_ck at 48004d50 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll5_ck>;
+	reg = <0x48004d50 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll5_m2_d20_ck: dpll5_m2_d20_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll5_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <20>;
+};
+
+sys_d2_ck: sys_d2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_ck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+omap_96m_d2_fck: omap_96m_d2_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+omap_96m_d4_fck: omap_96m_d4_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+omap_96m_d8_fck: omap_96m_d8_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+omap_96m_d10_fck: omap_96m_d10_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <10>;
+};
+
+dpll5_m2_d4_ck: dpll5_m2_d4_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll5_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+dpll5_m2_d8_ck: dpll5_m2_d8_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll5_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <8>;
+};
+
+dpll5_m2_d16_ck: dpll5_m2_d16_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll5_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <16>;
+};
+
+usim_mux_fck: usim_mux_fck at 48004c40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_ck>, <&dpll5_m2_d20_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>;
+	bit-shift = <3>;
+	reg = <0x48004c40 0x4>;
+	table = <&sys_ck 1>, <&dpll5_m2_d20_ck 10>, <&sys_d2_ck 2>, <&omap_96m_d2_fck 3>, <&omap_96m_d4_fck 4>, <&omap_96m_d8_fck 5>, <&omap_96m_d10_fck 6>, <&dpll5_m2_d4_ck 7>, <&dpll5_m2_d8_ck 8>, <&dpll5_m2_d16_ck 9>;
+	bit-mask = <0xf>;
+};
+
+usim_fck: usim_fck at 48004c00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&usim_mux_fck>;
+	bit-shift = <9>;
+	reg = <0x48004c00 0x4>;
+};
+
+usim_ick: usim_ick at 48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <9>;
+};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f8b3765..583c212 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -35,4 +35,14 @@
 			clock-frequency = <48000000>;
 		};
 	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap36xx-clocks.dtsi"
+		/include/ "omap34xx-omap36xx-clocks.dtsi"
+		/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+		/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+	};
 };
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
new file mode 100644
index 0000000..18a723f
--- /dev/null
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -0,0 +1,1594 @@
+/*
+ * Device Tree Source for OMAP3 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+dummy_apb_pclk: dummy_apb_pclk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0x0>;
+};
+
+omap_32k_fck: omap_32k_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+virt_12m_ck: virt_12m_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <12000000>;
+};
+
+virt_13m_ck: virt_13m_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <13000000>;
+};
+
+virt_19200000_ck: virt_19200000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <19200000>;
+};
+
+virt_26000000_ck: virt_26000000_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <26000000>;
+};
+
+virt_38_4m_ck: virt_38_4m_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <38400000>;
+};
+
+virt_16_8m_ck: virt_16_8m_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <16800000>;
+};
+
+osc_sys_ck: osc_sys_ck at 48306d40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
+	reg = <0x48306d40 0x4>;
+	bit-mask = <0x7>;
+};
+
+sys_ck: sys_ck at 48307270 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&osc_sys_ck>;
+	bit-shift = <6>;
+	reg = <0x48307270 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+dpll4_ck: dpll4_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,autoidle-mask = <0x38>;
+	ti,modes = <0x82>;
+	ti,clk-bypass = <&sys_ck>;
+	ti,idlest-mask = <0x2>;
+	reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d44 0x4>;
+	ti,clkdm-name = "dpll4_clkdm";
+	ti,clk-ref = <&sys_ck>;
+	ti,recal-en-bit = <0x6>;
+	ti,auto-recal-bit = <0x13>;
+	ti,enable-mask = <0x70000>;
+	ti,recal-st-bit = <0x6>;
+	ti,dpll-peripheral;
+};
+
+dpll4_m2_ck: dpll4_m2_ck at 48004d48 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	reg = <0x48004d48 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m2_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m2x2_ck: dpll4_m2x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m2x2_mul_ck>;
+	bit-shift = <0x1b>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+omap_96m_alwon_fck: omap_96m_alwon_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll3_ck: dpll3_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,clk-bypass = <&sys_ck>;
+	reg = <0x48004d00 0x4>, <0x48004d20 0x4>, <0x48004d30 0x4>, <0x48004d40 0x4>;
+	ti,clk-ref = <&sys_ck>;
+	ti,clkdm-name = "dpll3_clkdm";
+	ti,recal-en-bit = <0x5>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x5>;
+	ti,dpll-core;
+};
+
+dpll3_m3_ck: dpll3_m3_ck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll3_ck>;
+	bit-shift = <16>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m3_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll3_m3x2_ck: dpll3_m3x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll3_m3x2_mul_ck>;
+	bit-shift = <0xc>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+emu_core_alwon_ck: emu_core_alwon_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m3x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sys_altclk: sys_altclk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0x0>;
+};
+
+mcbsp_clks: mcbsp_clks {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <0x0>;
+};
+
+sys_clkout1: sys_clkout1 at 48306d70 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&osc_sys_ck>;
+	reg = <0x48306d70 0x4>;
+	bit-shift = <7>;
+};
+
+dpll1_ck: dpll1_ck at 48004904 {
+	#clock-cells = <0>;
+	compatible = "ti,omap3-dpll-clock";
+	clocks = <&sys_ck>;
+	ti,clk-bypass = <&dpll1_fck>;
+	reg = <0x48004904 0x4>, <0x48004924 0x4>, <0x48004934 0x4>, <0x48004940 0x4>;
+	ti,clk-ref = <&sys_ck>;
+	ti,clkdm-name = "dpll1_clkdm";
+	ti,recal-en-bit = <0x7>;
+	ti,auto-recal-bit = <0x3>;
+	ti,recal-st-bit = <0x7>;
+};
+
+dpll1_x2_ck: dpll1_x2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll1_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll1_x2m2_ck: dpll1_x2m2_ck at 48004944 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll1_x2_ck>;
+	reg = <0x48004944 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+dpll3_m2_ck: dpll3_m2_ck at 48004d40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll3_ck>;
+	bit-shift = <27>;
+	reg = <0x48004d40 0x4>;
+	bit-mask = <0x1f>;
+	index-starts-at-one;
+};
+
+core_ck: core_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll3_x2_ck: dpll3_x2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll3_m2x2_ck: dpll3_m2x2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m2_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_x2_ck: dpll4_x2_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+cm_96m_fck: cm_96m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_alwon_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+omap_96m_fck: omap_96m_fck at 48004d40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&cm_96m_fck>, <&sys_ck>;
+	bit-shift = <6>;
+	reg = <0x48004d40 0x4>;
+	bit-mask = <0x1>;
+};
+
+dpll4_m3_ck: dpll4_m3_ck at 48004e40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	bit-shift = <8>;
+	reg = <0x48004e40 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m3_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m3x2_ck: dpll4_m3x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m3x2_mul_ck>;
+	bit-shift = <0x1c>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+omap_54m_fck: omap_54m_fck at 48004d40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
+	bit-shift = <5>;
+	reg = <0x48004d40 0x4>;
+	bit-mask = <0x1>;
+};
+
+cm_96m_d2_fck: cm_96m_d2_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&cm_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <2>;
+};
+
+omap_48m_fck: omap_48m_fck at 48004d40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
+	bit-shift = <3>;
+	reg = <0x48004d40 0x4>;
+	table = <&cm_96m_d2_fck 0>, <&sys_altclk 1>;
+	bit-mask = <0x1>;
+};
+
+omap_12m_fck: omap_12m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_48m_fck>;
+	clock-mult = <1>;
+	clock-div = <4>;
+};
+
+dpll4_m4_ck: dpll4_m4_ck at 48004e40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	reg = <0x48004e40 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m4_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m4x2_ck: dpll4_m4x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m4x2_mul_ck>;
+	bit-shift = <0x1d>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+dpll4_m5_ck: dpll4_m5_ck at 48004f40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	reg = <0x48004f40 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m5_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m5x2_ck: dpll4_m5x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m5x2_mul_ck>;
+	bit-shift = <0x1e>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+dpll4_m6_ck: dpll4_m6_ck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&dpll4_ck>;
+	bit-shift = <24>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3f>;
+	index-starts-at-one;
+};
+
+dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m6_ck>;
+	clock-mult = <2>;
+	clock-div = <1>;
+};
+
+dpll4_m6x2_ck: dpll4_m6x2_ck at 48004d00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&dpll4_m6x2_mul_ck>;
+	bit-shift = <0x1f>;
+	reg = <0x48004d00 0x4>;
+	set-bit-to-disable;
+};
+
+emu_per_alwon_ck: emu_per_alwon_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll4_m6x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+clkout2_src_mux_ck: clkout2_src_mux_ck at 48004d70 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
+	reg = <0x48004d70 0x4>;
+	bit-mask = <0x3>;
+};
+
+clkout2_src_ck: clkout2_src_ck at 48004d70 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&clkout2_src_mux_ck>;
+	bit-shift = <7>;
+	reg = <0x48004d70 0x4>;
+};
+
+sys_clkout2: sys_clkout2 at 48004d70 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&clkout2_src_ck>;
+	bit-shift = <3>;
+	reg = <0x48004d70 0x4>;
+	bit-mask = <0x7>;
+	index-power-of-two;
+};
+
+corex2_fck: corex2_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll3_m2x2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+dpll1_fck: dpll1_fck at 48004940 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&core_ck>;
+	bit-shift = <19>;
+	reg = <0x48004940 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+mpu_ck: mpu_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&dpll1_x2m2_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+arm_fck: arm_fck at 48004924 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&mpu_ck>;
+	reg = <0x48004924 0x4>;
+	bit-mask = <0x1>;
+};
+
+emu_mpu_alwon_ck: emu_mpu_alwon_ck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&mpu_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+l3_ick: l3_ick at 48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&core_ck>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+l4_ick: l4_ick at 48004a40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l3_ick>;
+	bit-shift = <2>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+rm_ick: rm_ick at 48004c40 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&l4_ick>;
+	bit-shift = <1>;
+	reg = <0x48004c40 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+gpt10_mux_fck: gpt10_mux_fck at 48004a40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <6>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt10_fck: gpt10_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt10_mux_fck>;
+	bit-shift = <11>;
+	reg = <0x48004a00 0x4>;
+};
+
+gpt11_mux_fck: gpt11_mux_fck at 48004a40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <7>;
+	reg = <0x48004a40 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt11_fck: gpt11_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt11_mux_fck>;
+	bit-shift = <12>;
+	reg = <0x48004a00 0x4>;
+};
+
+core_96m_fck: core_96m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mmchs2_fck: mmchs2_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <25>;
+};
+
+mmchs1_fck: mmchs1_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <24>;
+};
+
+i2c3_fck: i2c3_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <17>;
+};
+
+i2c2_fck: i2c2_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <16>;
+};
+
+i2c1_fck: i2c1_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_96m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <15>;
+};
+
+mcbsp5_mux_fck: mcbsp5_mux_fck at 480022d8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&core_96m_fck>, <&mcbsp_clks>;
+	bit-shift = <4>;
+	reg = <0x480022d8 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp5_fck: mcbsp5_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp5_mux_fck>;
+	bit-shift = <10>;
+	reg = <0x48004a00 0x4>;
+};
+
+mcbsp1_mux_fck: mcbsp1_mux_fck at 48002274 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&core_96m_fck>, <&mcbsp_clks>;
+	bit-shift = <2>;
+	reg = <0x48002274 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp1_fck: mcbsp1_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp1_mux_fck>;
+	bit-shift = <9>;
+	reg = <0x48004a00 0x4>;
+};
+
+core_48m_fck: core_48m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_48m_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mcspi4_fck: mcspi4_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <21>;
+};
+
+mcspi3_fck: mcspi3_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <20>;
+};
+
+mcspi2_fck: mcspi2_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <19>;
+};
+
+mcspi1_fck: mcspi1_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <18>;
+};
+
+uart2_fck: uart2_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <14>;
+};
+
+uart1_fck: uart1_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_48m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <13>;
+};
+
+core_12m_fck: core_12m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_12m_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+hdq_fck: hdq_fck at 48004a00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_12m_fck>;
+	reg = <0x48004a00 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <22>;
+};
+
+core_l3_ick: core_l3_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l3_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+sdrc_ick: sdrc_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&core_l3_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l3_clkdm";
+	ti,enable-bit = <1>;
+};
+
+gpmc_fck: gpmc_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&core_l3_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+core_l4_ick: core_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+mmchs2_ick: mmchs2_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <25>;
+};
+
+mmchs1_ick: mmchs1_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <24>;
+};
+
+hdq_ick: hdq_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <22>;
+};
+
+mcspi4_ick: mcspi4_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <21>;
+};
+
+mcspi3_ick: mcspi3_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <20>;
+};
+
+mcspi2_ick: mcspi2_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <19>;
+};
+
+mcspi1_ick: mcspi1_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <18>;
+};
+
+i2c3_ick: i2c3_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <17>;
+};
+
+i2c2_ick: i2c2_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <16>;
+};
+
+i2c1_ick: i2c1_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <15>;
+};
+
+uart2_ick: uart2_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <14>;
+};
+
+uart1_ick: uart1_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <13>;
+};
+
+gpt11_ick: gpt11_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <12>;
+};
+
+gpt10_ick: gpt10_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <11>;
+};
+
+mcbsp5_ick: mcbsp5_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <10>;
+};
+
+mcbsp1_ick: mcbsp1_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <9>;
+};
+
+omapctrl_ick: omapctrl_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <6>;
+};
+
+dss_tv_fck: dss_tv_fck at 48004e00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&omap_54m_fck>;
+	reg = <0x48004e00 0x4>;
+	bit-shift = <2>;
+};
+
+dss_96m_fck: dss_96m_fck at 48004e00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&omap_96m_fck>;
+	reg = <0x48004e00 0x4>;
+	bit-shift = <2>;
+};
+
+dss2_alwon_fck: dss2_alwon_fck at 48004e00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&sys_ck>;
+	reg = <0x48004e00 0x4>;
+	bit-shift = <1>;
+};
+
+gpt1_mux_fck: gpt1_mux_fck at 48004c40 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	reg = <0x48004c40 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt1_fck: gpt1_fck at 48004c00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt1_mux_fck>;
+	bit-shift = <0>;
+	reg = <0x48004c00 0x4>;
+};
+
+aes2_ick: aes2_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <28>;
+};
+
+wkup_32k_fck: wkup_32k_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_32k_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gpio1_dbck: gpio1_dbck at 48004c00 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&wkup_32k_fck>;
+	reg = <0x48004c00 0x4>;
+	bit-shift = <3>;
+};
+
+sha12_ick: sha12_ick at 48004a10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&core_l4_ick>;
+	reg = <0x48004a10 0x4>;
+	ti,clkdm-name = "core_l4_clkdm";
+	ti,enable-bit = <27>;
+};
+
+wdt2_fck: wdt2_fck at 48004c00 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&wkup_32k_fck>;
+	reg = <0x48004c00 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <5>;
+};
+
+wkup_l4_ick: wkup_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&sys_ck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+wdt2_ick: wdt2_ick at 48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <5>;
+};
+
+wdt1_ick: wdt1_ick at 48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <4>;
+};
+
+gpio1_ick: gpio1_ick at 48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <3>;
+};
+
+omap_32ksync_ick: omap_32ksync_ick at 48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <2>;
+};
+
+gpt12_ick: gpt12_ick at 48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <1>;
+};
+
+gpt1_ick: gpt1_ick at 48004c10 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&wkup_l4_ick>;
+	reg = <0x48004c10 0x4>;
+	ti,clkdm-name = "wkup_clkdm";
+	ti,enable-bit = <0>;
+};
+
+per_96m_fck: per_96m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_96m_alwon_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+per_48m_fck: per_48m_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_48m_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+uart3_fck: uart3_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&per_48m_fck>;
+	reg = <0x48005000 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <11>;
+};
+
+gpt2_mux_fck: gpt2_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt2_fck: gpt2_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt2_mux_fck>;
+	bit-shift = <3>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt3_mux_fck: gpt3_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <1>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt3_fck: gpt3_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt3_mux_fck>;
+	bit-shift = <4>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt4_mux_fck: gpt4_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <2>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt4_fck: gpt4_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt4_mux_fck>;
+	bit-shift = <5>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt5_mux_fck: gpt5_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <3>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt5_fck: gpt5_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt5_mux_fck>;
+	bit-shift = <6>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt6_mux_fck: gpt6_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <4>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt6_fck: gpt6_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt6_mux_fck>;
+	bit-shift = <7>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt7_mux_fck: gpt7_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <5>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt7_fck: gpt7_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt7_mux_fck>;
+	bit-shift = <8>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt8_mux_fck: gpt8_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <6>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt8_fck: gpt8_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt8_mux_fck>;
+	bit-shift = <9>;
+	reg = <0x48005000 0x4>;
+};
+
+gpt9_mux_fck: gpt9_mux_fck at 48005040 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&omap_32k_fck>, <&sys_ck>;
+	bit-shift = <7>;
+	reg = <0x48005040 0x4>;
+	bit-mask = <0x1>;
+};
+
+gpt9_fck: gpt9_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&gpt9_mux_fck>;
+	bit-shift = <10>;
+	reg = <0x48005000 0x4>;
+};
+
+per_32k_alwon_fck: per_32k_alwon_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&omap_32k_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gpio6_dbck: gpio6_dbck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <17>;
+};
+
+gpio5_dbck: gpio5_dbck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <16>;
+};
+
+gpio4_dbck: gpio4_dbck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <15>;
+};
+
+gpio3_dbck: gpio3_dbck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <14>;
+};
+
+gpio2_dbck: gpio2_dbck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	bit-shift = <13>;
+};
+
+wdt3_fck: wdt3_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&per_32k_alwon_fck>;
+	reg = <0x48005000 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <12>;
+};
+
+per_l4_ick: per_l4_ick {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&l4_ick>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+gpio6_ick: gpio6_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <17>;
+};
+
+gpio5_ick: gpio5_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <16>;
+};
+
+gpio4_ick: gpio4_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <15>;
+};
+
+gpio3_ick: gpio3_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <14>;
+};
+
+gpio2_ick: gpio2_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <13>;
+};
+
+wdt3_ick: wdt3_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <12>;
+};
+
+uart3_ick: uart3_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <11>;
+};
+
+uart4_ick: uart4_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <18>;
+};
+
+gpt9_ick: gpt9_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <10>;
+};
+
+gpt8_ick: gpt8_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <9>;
+};
+
+gpt7_ick: gpt7_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <8>;
+};
+
+gpt6_ick: gpt6_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <7>;
+};
+
+gpt5_ick: gpt5_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <6>;
+};
+
+gpt4_ick: gpt4_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <5>;
+};
+
+gpt3_ick: gpt3_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <4>;
+};
+
+gpt2_ick: gpt2_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <3>;
+};
+
+mcbsp2_ick: mcbsp2_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <0>;
+};
+
+mcbsp3_ick: mcbsp3_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <1>;
+};
+
+mcbsp4_ick: mcbsp4_ick at 48005010 {
+	#clock-cells = <0>;
+	compatible = "ti,interface-clock";
+	clocks = <&per_l4_ick>;
+	reg = <0x48005010 0x4>;
+	ti,clkdm-name = "per_clkdm";
+	ti,enable-bit = <2>;
+};
+
+mcbsp2_mux_fck: mcbsp2_mux_fck at 48002274 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_96m_fck>, <&mcbsp_clks>;
+	bit-shift = <6>;
+	reg = <0x48002274 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp2_fck: mcbsp2_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp2_mux_fck>;
+	bit-shift = <0>;
+	reg = <0x48005000 0x4>;
+};
+
+mcbsp3_mux_fck: mcbsp3_mux_fck at 480022d8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_96m_fck>, <&mcbsp_clks>;
+	reg = <0x480022d8 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp3_fck: mcbsp3_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp3_mux_fck>;
+	bit-shift = <1>;
+	reg = <0x48005000 0x4>;
+};
+
+mcbsp4_mux_fck: mcbsp4_mux_fck at 480022d8 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&per_96m_fck>, <&mcbsp_clks>;
+	bit-shift = <2>;
+	reg = <0x480022d8 0x4>;
+	bit-mask = <0x1>;
+};
+
+mcbsp4_fck: mcbsp4_fck at 48005000 {
+	#clock-cells = <0>;
+	compatible = "gate-clock";
+	clocks = <&mcbsp4_mux_fck>;
+	bit-shift = <2>;
+	reg = <0x48005000 0x4>;
+};
+
+emu_src_mux_ck: emu_src_mux_ck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3>;
+};
+
+emu_src_ck: emu_src_ck {
+	#clock-cells = <0>;
+	compatible = "ti,gate-clock";
+	clocks = <&emu_src_mux_ck>;
+	ti,clkdm-name = "emu_clkdm";
+};
+
+pclk_fck: pclk_fck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&emu_src_ck>;
+	bit-shift = <8>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+pclkx2_fck: pclkx2_fck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&emu_src_ck>;
+	bit-shift = <6>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+atclk_fck: atclk_fck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&emu_src_ck>;
+	bit-shift = <4>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3>;
+	index-starts-at-one;
+};
+
+traceclk_src_fck: traceclk_src_fck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "mux-clock";
+	clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+	bit-shift = <2>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x3>;
+};
+
+traceclk_fck: traceclk_fck at 48005140 {
+	#clock-cells = <0>;
+	compatible = "divider-clock";
+	clocks = <&traceclk_src_fck>;
+	bit-shift = <11>;
+	reg = <0x48005140 0x4>;
+	bit-mask = <0x7>;
+	index-starts-at-one;
+};
+
+secure_32k_fck: secure_32k_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <32768>;
+};
+
+gpt12_fck: gpt12_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&secure_32k_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
+
+wdt1_fck: wdt1_fck {
+	#clock-cells = <0>;
+	compatible = "fixed-factor-clock";
+	clocks = <&secure_32k_fck>;
+	clock-mult = <1>;
+	clock-div = <1>;
+};
-- 
1.7.9.5

[PATCHv4 30/33] clk: OMAP: DRA7: Add APLL support

[Tero Kristo]

From: Keerthy <j-keerthy@ti.com>

The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.

APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital PLL, the phase detection is done
using an analog circuit.

Signed-off-by: Keerthy <j-keerthy@ti.com>
---
 arch/arm/mach-omap2/clock.h |    1 -
 drivers/clk/omap/Makefile   |    3 +-
 drivers/clk/omap/apll.c     |  213 +++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/omap/clk.c      |    1 +
 include/linux/clk/omap.h    |    3 +
 5 files changed, 219 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/omap/apll.c

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 949d293..5f1c7d4 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -38,7 +38,6 @@ struct omap_clk {
 	}
 
 struct clockdomain;
-#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 
 #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name)	\
 	static struct clk _name = {				\
diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index 85b0dc7..6bceb27 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1,3 +1,4 @@
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
 					   clk-44xx.o clk-54xx.o clk-7xx.o \
-					   clk-33xx.o interface.o clk-3xxx.o
+					   clk-33xx.o interface.o clk-3xxx.o \
+					   apll.o
diff --git a/drivers/clk/omap/apll.c b/drivers/clk/omap/apll.c
new file mode 100644
index 0000000..3a216b8
--- /dev/null
+++ b/drivers/clk/omap/apll.c
@@ -0,0 +1,213 @@
+/*
+ * OMAP APLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * J Keerthy <j-keerthy@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/omap.h>
+#include <linux/delay.h>
+
+#define APLL_FORCE_LOCK 0x1
+#define APLL_AUTO_IDLE	0x2
+#define MAX_APLL_WAIT_TRIES		1000000
+
+int dra7_apll_enable(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	int r = 0, i = 0;
+	struct dpll_data *ad;
+	const char *clk_name;
+	u8 state = 1;
+	u32 v;
+
+	ad = clk->dpll_data;
+	if (!ad)
+		return -EINVAL;
+
+	clk_name = __clk_get_name(clk->hw.clk);
+
+	state <<= __ffs(ad->idlest_mask);
+
+	/* Check is already locked */
+	if ((__raw_readl(ad->idlest_reg) & ad->idlest_mask) == state)
+		return r;
+
+	v = __raw_readl(ad->control_reg);
+	v &= ~ad->enable_mask;
+	v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
+	__raw_writel(v, ad->control_reg);
+
+	state <<= __ffs(ad->idlest_mask);
+
+	while (((__raw_readl(ad->idlest_reg) & ad->idlest_mask) != state) &&
+	       i < MAX_APLL_WAIT_TRIES) {
+		i++;
+		udelay(1);
+	}
+
+	if (i == MAX_APLL_WAIT_TRIES) {
+		pr_warn("clock: %s failed transition to '%s'\n",
+		       clk_name, (state) ? "locked" : "bypassed");
+	} else {
+		pr_debug("clock: %s transition to '%s' in %d loops\n",
+			 clk_name, (state) ? "locked" : "bypassed", i);
+
+		r = 0;
+	}
+
+	return r;
+}
+
+void dra7_apll_disable(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	struct dpll_data *ad;
+	u8 state = 1;
+	u32 v;
+
+	ad = clk->dpll_data;
+
+	state <<= __ffs(ad->idlest_mask);
+
+	v = __raw_readl(ad->control_reg);
+	v &= ~ad->enable_mask;
+	v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
+	__raw_writel(v, ad->control_reg);
+}
+
+u8 dra7_init_apll_parent(struct clk_hw *hw)
+{
+	return 0;
+}
+
+static const struct clk_ops apll_ck_ops = {
+	.enable		= &dra7_apll_enable,
+	.disable	= &dra7_apll_disable,
+	.get_parent	= &dra7_init_apll_parent,
+};
+
+struct clk *omap_clk_register_apll(struct device *dev, const char *name,
+		const char **parent_names, int num_parents, unsigned long flags,
+		struct dpll_data *dpll_data, const char *clkdm_name,
+		const struct clk_ops *ops)
+{
+	struct clk *clk;
+	struct clk_init_data init;
+	struct clk_hw_omap *clk_hw;
+
+	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk_hw->dpll_data = dpll_data;
+	clk_hw->hw.init = &init;
+
+	init.name = name;
+	init.ops = ops;
+	init.flags = flags;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+
+	/* register the clock */
+	clk = clk_register(dev, &clk_hw->hw);
+
+	return clk;
+}
+
+#ifdef CONFIG_OF
+
+__init void of_dra7_apll_setup(struct device_node *node)
+{
+	const struct clk_ops *ops;
+	struct clk *clk;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names;
+	struct of_phandle_args clkspec;
+	u8 apll_flags = 0;
+	struct dpll_data *ad;
+	u32 idlest_mask = 0x1;
+	u32 autoidle_mask = 0x3;
+	int i;
+
+	ops = &apll_ck_ops;
+	ad = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
+	if (!ad) {
+		pr_err("%s: could not allocate dpll_data\n", __func__);
+		return;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: omap dpll %s must have parent(s)\n",
+			__func__, node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
+	ad->clk_ref = of_clk_get_from_provider(&clkspec);
+	if (!ad->clk_ref) {
+		pr_err("%s: ti,clk-ref for %s not found\n", __func__,
+			clk_name);
+		goto cleanup;
+	}
+
+	clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
+	ad->clk_bypass = of_clk_get_from_provider(&clkspec);
+	if (!ad->clk_bypass) {
+		pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
+			clk_name);
+		goto cleanup;
+	}
+
+	ad->control_reg = of_iomap(node, 0);
+	ad->idlest_reg = of_iomap(node, 1);
+
+	ad->idlest_mask = idlest_mask;
+	ad->enable_mask = autoidle_mask;
+
+	clk = omap_clk_register_apll(NULL, clk_name, parent_names,
+				num_parents, apll_flags, ad,
+				NULL, ops);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	return;
+
+cleanup:
+	kfree(ad);
+	return;
+
+}
+EXPORT_SYMBOL_GPL(of_dra7_apll_setup);
+CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
+#endif
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index 5cbefde..476f6cb 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -29,6 +29,7 @@ static const struct of_device_id clk_match[] = {
 	{.compatible = "divider-clock", .data = of_omap_divider_setup, },
 	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
 	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
+	{.compatible = "ti,dra7-apll-clock", .data = of_dra7_apll_setup, },
 	{.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
 	{.compatible = "ti,interface-clock",
 		.data = of_omap_interface_clk_setup, },
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index 35008d9..0d70cd1 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -162,6 +162,8 @@ struct omap_dt_clk {
 		.node_name = name,	\
 	}
 
+#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
+
 void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap3_noncore_dpll_enable(struct clk_hw *hw);
 void omap3_noncore_dpll_disable(struct clk_hw *hw);
@@ -209,6 +211,7 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 int dt_omap_clk_init(void);
 extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
 void of_omap4_dpll_setup(struct device_node *node);
+void of_dra7_apll_setup(struct device_node *node);
 void of_omap3_dpll_setup(struct device_node *node);
 void of_omap_fixed_factor_setup(struct device_node *node);
 void of_omap_divider_setup(struct device_node *node);
-- 
1.7.9.5

[PATCHv4 30/33] clk: OMAP: DRA7: Add APLL support

[Tero Kristo]

From: Keerthy <j-keerthy@ti.com>

The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.

APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital PLL, the phase detection is done
using an analog circuit.

Signed-off-by: Keerthy <j-keerthy@ti.com>
---
 arch/arm/mach-omap2/clock.h |    1 -
 drivers/clk/omap/Makefile   |    3 +-
 drivers/clk/omap/apll.c     |  213 +++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/omap/clk.c      |    1 +
 include/linux/clk/omap.h    |    3 +
 5 files changed, 219 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/omap/apll.c

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 949d293..5f1c7d4 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -38,7 +38,6 @@ struct omap_clk {
 	}
 
 struct clockdomain;
-#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 
 #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name)	\
 	static struct clk _name = {				\
diff --git a/drivers/clk/omap/Makefile b/drivers/clk/omap/Makefile
index 85b0dc7..6bceb27 100644
--- a/drivers/clk/omap/Makefile
+++ b/drivers/clk/omap/Makefile
@@ -1,3 +1,4 @@
 obj-y					+= clk.o dpll.o autoidle.o gate.o \
 					   clk-44xx.o clk-54xx.o clk-7xx.o \
-					   clk-33xx.o interface.o clk-3xxx.o
+					   clk-33xx.o interface.o clk-3xxx.o \
+					   apll.o
diff --git a/drivers/clk/omap/apll.c b/drivers/clk/omap/apll.c
new file mode 100644
index 0000000..3a216b8
--- /dev/null
+++ b/drivers/clk/omap/apll.c
@@ -0,0 +1,213 @@
+/*
+ * OMAP APLL clock support
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * J Keerthy <j-keerthy@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/omap.h>
+#include <linux/delay.h>
+
+#define APLL_FORCE_LOCK 0x1
+#define APLL_AUTO_IDLE	0x2
+#define MAX_APLL_WAIT_TRIES		1000000
+
+int dra7_apll_enable(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	int r = 0, i = 0;
+	struct dpll_data *ad;
+	const char *clk_name;
+	u8 state = 1;
+	u32 v;
+
+	ad = clk->dpll_data;
+	if (!ad)
+		return -EINVAL;
+
+	clk_name = __clk_get_name(clk->hw.clk);
+
+	state <<= __ffs(ad->idlest_mask);
+
+	/* Check is already locked */
+	if ((__raw_readl(ad->idlest_reg) & ad->idlest_mask) == state)
+		return r;
+
+	v = __raw_readl(ad->control_reg);
+	v &= ~ad->enable_mask;
+	v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
+	__raw_writel(v, ad->control_reg);
+
+	state <<= __ffs(ad->idlest_mask);
+
+	while (((__raw_readl(ad->idlest_reg) & ad->idlest_mask) != state) &&
+	       i < MAX_APLL_WAIT_TRIES) {
+		i++;
+		udelay(1);
+	}
+
+	if (i == MAX_APLL_WAIT_TRIES) {
+		pr_warn("clock: %s failed transition to '%s'\n",
+		       clk_name, (state) ? "locked" : "bypassed");
+	} else {
+		pr_debug("clock: %s transition to '%s' in %d loops\n",
+			 clk_name, (state) ? "locked" : "bypassed", i);
+
+		r = 0;
+	}
+
+	return r;
+}
+
+void dra7_apll_disable(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	struct dpll_data *ad;
+	u8 state = 1;
+	u32 v;
+
+	ad = clk->dpll_data;
+
+	state <<= __ffs(ad->idlest_mask);
+
+	v = __raw_readl(ad->control_reg);
+	v &= ~ad->enable_mask;
+	v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
+	__raw_writel(v, ad->control_reg);
+}
+
+u8 dra7_init_apll_parent(struct clk_hw *hw)
+{
+	return 0;
+}
+
+static const struct clk_ops apll_ck_ops = {
+	.enable		= &dra7_apll_enable,
+	.disable	= &dra7_apll_disable,
+	.get_parent	= &dra7_init_apll_parent,
+};
+
+struct clk *omap_clk_register_apll(struct device *dev, const char *name,
+		const char **parent_names, int num_parents, unsigned long flags,
+		struct dpll_data *dpll_data, const char *clkdm_name,
+		const struct clk_ops *ops)
+{
+	struct clk *clk;
+	struct clk_init_data init;
+	struct clk_hw_omap *clk_hw;
+
+	clk_hw = kzalloc(sizeof(struct clk_hw_omap), GFP_KERNEL);
+	if (!clk_hw) {
+		pr_err("%s: could not allocate clk_hw_omap\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk_hw->dpll_data = dpll_data;
+	clk_hw->hw.init = &init;
+
+	init.name = name;
+	init.ops = ops;
+	init.flags = flags;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+
+	/* register the clock */
+	clk = clk_register(dev, &clk_hw->hw);
+
+	return clk;
+}
+
+#ifdef CONFIG_OF
+
+__init void of_dra7_apll_setup(struct device_node *node)
+{
+	const struct clk_ops *ops;
+	struct clk *clk;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names;
+	struct of_phandle_args clkspec;
+	u8 apll_flags = 0;
+	struct dpll_data *ad;
+	u32 idlest_mask = 0x1;
+	u32 autoidle_mask = 0x3;
+	int i;
+
+	ops = &apll_ck_ops;
+	ad = kzalloc(sizeof(struct dpll_data), GFP_KERNEL);
+	if (!ad) {
+		pr_err("%s: could not allocate dpll_data\n", __func__);
+		return;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: omap dpll %s must have parent(s)\n",
+			__func__, node->name);
+		goto cleanup;
+	}
+
+	parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	clkspec.np = of_parse_phandle(node, "ti,clk-ref", 0);
+	ad->clk_ref = of_clk_get_from_provider(&clkspec);
+	if (!ad->clk_ref) {
+		pr_err("%s: ti,clk-ref for %s not found\n", __func__,
+			clk_name);
+		goto cleanup;
+	}
+
+	clkspec.np = of_parse_phandle(node, "ti,clk-bypass", 0);
+	ad->clk_bypass = of_clk_get_from_provider(&clkspec);
+	if (!ad->clk_bypass) {
+		pr_err("%s: ti,clk-bypass for %s not found\n", __func__,
+			clk_name);
+		goto cleanup;
+	}
+
+	ad->control_reg = of_iomap(node, 0);
+	ad->idlest_reg = of_iomap(node, 1);
+
+	ad->idlest_mask = idlest_mask;
+	ad->enable_mask = autoidle_mask;
+
+	clk = omap_clk_register_apll(NULL, clk_name, parent_names,
+				num_parents, apll_flags, ad,
+				NULL, ops);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	return;
+
+cleanup:
+	kfree(ad);
+	return;
+
+}
+EXPORT_SYMBOL_GPL(of_dra7_apll_setup);
+CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
+#endif
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
index 5cbefde..476f6cb 100644
--- a/drivers/clk/omap/clk.c
+++ b/drivers/clk/omap/clk.c
@@ -29,6 +29,7 @@ static const struct of_device_id clk_match[] = {
 	{.compatible = "divider-clock", .data = of_omap_divider_setup, },
 	{.compatible = "gate-clock", .data = of_gate_clk_setup, },
 	{.compatible = "ti,omap4-dpll-clock", .data = of_omap4_dpll_setup, },
+	{.compatible = "ti,dra7-apll-clock", .data = of_dra7_apll_setup, },
 	{.compatible = "ti,gate-clock", .data = of_omap_gate_clk_setup, },
 	{.compatible = "ti,interface-clock",
 		.data = of_omap_interface_clk_setup, },
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index 35008d9..0d70cd1 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -162,6 +162,8 @@ struct omap_dt_clk {
 		.node_name = name,	\
 	}
 
+#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
+
 void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap3_noncore_dpll_enable(struct clk_hw *hw);
 void omap3_noncore_dpll_disable(struct clk_hw *hw);
@@ -209,6 +211,7 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 int dt_omap_clk_init(void);
 extern void omap_dt_clocks_register(struct omap_dt_clk *oclks, int cnt);
 void of_omap4_dpll_setup(struct device_node *node);
+void of_dra7_apll_setup(struct device_node *node);
 void of_omap3_dpll_setup(struct device_node *node);
 void of_omap_fixed_factor_setup(struct device_node *node);
 void of_omap_divider_setup(struct device_node *node);
-- 
1.7.9.5

[PATCHv4 31/33] ARM: dts: clk: Add apll related clocks

[Tero Kristo]

From: Keerthy <j-keerthy@ti.com>

The patch adds a mux node to choose the parent of apll_pcie_ck node.

Signed-off-by: Keerthy <j-keerthy@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |   19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 8477ff9..e923311 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -328,13 +328,24 @@ dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@4a008210 {
 	ti,autoidle-low;
 };
 
+/* APLL_PCIE */
+
+/* mux clock to select the reference clock */
+apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+	compatible = "mux-clock";
+	clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a00821c 0x4>;
+	bit-mask = <0x80>;
+};
+
 apll_pcie_ck: apll_pcie_ck@4a008200 {
 	#clock-cells = <0>;
-	compatible = "ti,omap4-dpll-clock";
-	clocks = <&dpll_pcie_ref_ck>;
-	reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
-	ti,clk-ref = <&dpll_pcie_ref_ck>;
+	clocks = <&apll_pcie_in_clk_mux>;
+	reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
 	ti,clk-bypass = <&dpll_pcie_ref_ck>;
+	ti,clk-ref = <&apll_pcie_in_clk_mux>;
+	compatible = "ti,dra7-apll-clock";
 };
 
 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
-- 
1.7.9.5

[PATCHv4 31/33] ARM: dts: clk: Add apll related clocks

[Tero Kristo]

From: Keerthy <j-keerthy@ti.com>

The patch adds a mux node to choose the parent of apll_pcie_ck node.

Signed-off-by: Keerthy <j-keerthy@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |   19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 8477ff9..e923311 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -328,13 +328,24 @@ dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck at 4a008210 {
 	ti,autoidle-low;
 };
 
+/* APLL_PCIE */
+
+/* mux clock to select the reference clock */
+apll_pcie_in_clk_mux: apll_pcie_in_clk_mux at 4ae06118 {
+	compatible = "mux-clock";
+	clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a00821c 0x4>;
+	bit-mask = <0x80>;
+};
+
 apll_pcie_ck: apll_pcie_ck at 4a008200 {
 	#clock-cells = <0>;
-	compatible = "ti,omap4-dpll-clock";
-	clocks = <&dpll_pcie_ref_ck>;
-	reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>;
-	ti,clk-ref = <&dpll_pcie_ref_ck>;
+	clocks = <&apll_pcie_in_clk_mux>;
+	reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
 	ti,clk-bypass = <&dpll_pcie_ref_ck>;
+	ti,clk-ref = <&apll_pcie_in_clk_mux>;
+	compatible = "ti,dra7-apll-clock";
 };
 
 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
-- 
1.7.9.5

[PATCHv4 32/33] clk: OMAP: DRA7: Change apll_pcie_m2_ck to fixed factor clock

[Tero Kristo]

From: Keerthy <j-keerthy@ti.com>

This patch changes apll_pcie_m2_ck to fixed factor
clock as there are no configurable divider associated to m2.

Signed-off-by: Keerthy <j-keerthy@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |    9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index e923311..fcc14d4 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -366,13 +366,10 @@ apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
 
 apll_pcie_m2_ck: apll_pcie_m2_ck@4a008224 {
 	#clock-cells = <0>;
-	compatible = "divider-clock";
+	compatible = "fixed-factor-clock";
 	clocks = <&apll_pcie_ck>;
-	ti,autoidle-shift = <8>;
-	reg = <0x4a008224 0x4>;
-	bit-mask = <0x7f>;
-	index-starts-at-one;
-	ti,autoidle-low;
+	clock-mult = <1>;
+	clock-div = <1>;
 };
 
 sys_clk1_dclk_div: sys_clk1_dclk_div@4ae061c8 {
-- 
1.7.9.5

[PATCHv4 32/33] clk: OMAP: DRA7: Change apll_pcie_m2_ck to fixed factor clock

[Tero Kristo]

From: Keerthy <j-keerthy@ti.com>

This patch changes apll_pcie_m2_ck to fixed factor
clock as there are no configurable divider associated to m2.

Signed-off-by: Keerthy <j-keerthy@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |    9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index e923311..fcc14d4 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -366,13 +366,10 @@ apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
 
 apll_pcie_m2_ck: apll_pcie_m2_ck at 4a008224 {
 	#clock-cells = <0>;
-	compatible = "divider-clock";
+	compatible = "fixed-factor-clock";
 	clocks = <&apll_pcie_ck>;
-	ti,autoidle-shift = <8>;
-	reg = <0x4a008224 0x4>;
-	bit-mask = <0x7f>;
-	index-starts-at-one;
-	ti,autoidle-low;
+	clock-mult = <1>;
+	clock-div = <1>;
 };
 
 sys_clk1_dclk_div: sys_clk1_dclk_div at 4ae061c8 {
-- 
1.7.9.5

[PATCHv4 33/33] clk: DTS: DRA7: Add PCIe related clock nodes

[Tero Kristo]

From: Keerthy <j-keerthy@ti.com>

This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.

Signed-off-by: Keerthy <j-keerthy@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |   24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index fcc14d4..32b9985 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -2087,3 +2087,27 @@ vip3_gclk_mux: vip3_gclk_mux@4a009030 {
 	reg = <0x4a009030 0x4>;
 	bit-mask = <0x1>;
 };
+
+optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+	compatible = "divider-clock";
+	clocks = <&apll_pcie_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a00821c 0x4>;
+	bit-mask = <0x100>;
+};
+
+optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
+	compatible = "gate-clock";
+	clocks = <&apll_pcie_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a0093b0 0x4>;
+	bit-shift = <9>;
+};
+
+optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
+	compatible = "gate-clock";
+	clocks = <&optfclk_pciephy_div>;
+	#clock-cells = <0>;
+	reg = <0x4a0093b0 0x4>;
+	bit-shift = <10>;
+};
-- 
1.7.9.5

[PATCHv4 33/33] clk: DTS: DRA7: Add PCIe related clock nodes

[Tero Kristo]

From: Keerthy <j-keerthy@ti.com>

This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.

Signed-off-by: Keerthy <j-keerthy@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |   24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index fcc14d4..32b9985 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -2087,3 +2087,27 @@ vip3_gclk_mux: vip3_gclk_mux at 4a009030 {
 	reg = <0x4a009030 0x4>;
 	bit-mask = <0x1>;
 };
+
+optfclk_pciephy_div: optfclk_pciephy_div at 4a00821c {
+	compatible = "divider-clock";
+	clocks = <&apll_pcie_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a00821c 0x4>;
+	bit-mask = <0x100>;
+};
+
+optfclk_pciephy_clk: optfclk_pciephy_clk at 4a0093b0 {
+	compatible = "gate-clock";
+	clocks = <&apll_pcie_ck>;
+	#clock-cells = <0>;
+	reg = <0x4a0093b0 0x4>;
+	bit-shift = <9>;
+};
+
+optfclk_pciephy_div_clk: optfclk_pciephy_div_clk at 4a0093b0 {
+	compatible = "gate-clock";
+	clocks = <&optfclk_pciephy_div>;
+	#clock-cells = <0>;
+	reg = <0x4a0093b0 0x4>;
+	bit-shift = <10>;
+};
-- 
1.7.9.5

Re: [PATCHv4 00/33] ARM: OMAP: clock conversion to DT

[Tero Kristo]

Hrmph,

Seems like the old devicetree list was terminated yesterday, so if you 
reply to this you will get some bounces. Sorry about that.

-Tero

On 07/23/2013 10:19 AM, Tero Kristo wrote:
> Hi,
>
> Changes compared to previous version:
>
> - Clock init files moved from mach-omap2/ to drivers/clk/omap/
> - AM33xx support added [patches 15-20]
> - OMAP3 support added [patches 21-29]
> - DRA7 APLL support added (thanks Keerthy) [patches 30-33]
>
> Test branch on top of 3.11-rc1 available here:
>
> git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
> branch: mainline-3.11-rc1-omap-dt-clks
>
> Testing done:
>
> - boot + suspend tested on OMAP3 beagle C4 (omap3530)
> - boot + suspend tested on OMAP4 panda ES (omap4460)
> - boot tested on beagle bone (am335x)
>
> A boot test was also executed for DRA7 and OMAP5 on a separate branch
> (mainline does not have OMAP5 / DRA7 support so far.)
>
> TODO:
> - Add AM35xx support (OMAP3 derivative, AM35xx only clock nodes missing)
>
> Overall diffstat added just for fun:
>
>   arch/arm/boot/dts/am33xx-clocks.dtsi               |  663 ++++
>   arch/arm/boot/dts/am33xx.dtsi                      |    7 +
>   arch/arm/boot/dts/dra7xx-clocks.dtsi               | 2113 ++++++++++++
>   arch/arm/boot/dts/omap3.dtsi                       |    7 +
>   arch/arm/boot/dts/omap3430es1-clocks.dtsi          |  166 +
>   arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi    |  240 ++
>   arch/arm/boot/dts/omap34xx.dtsi                    |    9 +
>   .../omap36xx-am35xx-omap3430es2plus-clocks.dtsi    |  214 ++
>   arch/arm/boot/dts/omap36xx-clocks.dtsi             |   97 +
>   .../boot/dts/omap36xx-omap3430es2plus-clocks.dtsi  |  185 +
>   arch/arm/boot/dts/omap36xx.dtsi                    |   10 +
>   arch/arm/boot/dts/omap3xxx-clocks.dtsi             | 1594 +++++++++
>   arch/arm/boot/dts/omap443x-clocks.dtsi             |   17 +
>   arch/arm/boot/dts/omap443x.dtsi                    |    8 +
>   arch/arm/boot/dts/omap4460.dtsi                    |    8 +
>   arch/arm/boot/dts/omap446x-clocks.dtsi             |   27 +
>   arch/arm/boot/dts/omap44xx-clocks.dtsi             | 1654 +++++++++
>   arch/arm/boot/dts/omap54xx-clocks.dtsi             | 1416 ++++++++
>   arch/arm/mach-omap2/Makefile                       |    5 +-
>   arch/arm/mach-omap2/cclock33xx_data.c              | 1059 ------
>   arch/arm/mach-omap2/cclock3xxx_data.c              | 3641 --------------------
>   arch/arm/mach-omap2/cclock44xx_data.c              | 1730 ----------
>   arch/arm/mach-omap2/clock.c                        |    6 +
>   arch/arm/mach-omap2/clock.h                        |  163 +-
>   arch/arm/mach-omap2/clock3xxx.h                    |    7 +-
>   arch/arm/mach-omap2/io.c                           |    7 +-
>   arch/arm/mach-omap2/omap_hwmod.c                   |    5 +-
>   drivers/clk/Makefile                               |    1 +
>   drivers/clk/clk-divider.c                          |    6 +-
>   drivers/clk/clk-fixed-factor.c                     |    6 +-
>   drivers/clk/clk-gate.c                             |    8 +-
>   drivers/clk/clk-mux.c                              |    6 +-
>   drivers/clk/clkdev.c                               |   32 +
>   drivers/clk/omap/Makefile                          |    4 +
>   drivers/clk/omap/apll.c                            |  213 ++
>   drivers/clk/omap/autoidle.c                        |  130 +
>   drivers/clk/omap/clk-33xx.c                        |   85 +
>   drivers/clk/omap/clk-3xxx.c                        |  171 +
>   drivers/clk/omap/clk-44xx.c                        |  118 +
>   drivers/clk/omap/clk-54xx.c                        |   58 +
>   drivers/clk/omap/clk-7xx.c                         |   67 +
>   drivers/clk/omap/clk.c                             |   84 +
>   drivers/clk/omap/dpll.c                            |  387 +++
>   drivers/clk/omap/gate.c                            |  166 +
>   drivers/clk/omap/interface.c                       |  110 +
>   include/linux/clk/omap.h                           |  223 ++
>   46 files changed, 10327 insertions(+), 6606 deletions(-)
>
> -Tero
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

[PATCHv4 00/33] ARM: OMAP: clock conversion to DT

[Tero Kristo]

Hrmph,

Seems like the old devicetree list was terminated yesterday, so if you 
reply to this you will get some bounces. Sorry about that.

-Tero

On 07/23/2013 10:19 AM, Tero Kristo wrote:
> Hi,
>
> Changes compared to previous version:
>
> - Clock init files moved from mach-omap2/ to drivers/clk/omap/
> - AM33xx support added [patches 15-20]
> - OMAP3 support added [patches 21-29]
> - DRA7 APLL support added (thanks Keerthy) [patches 30-33]
>
> Test branch on top of 3.11-rc1 available here:
>
> git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
> branch: mainline-3.11-rc1-omap-dt-clks
>
> Testing done:
>
> - boot + suspend tested on OMAP3 beagle C4 (omap3530)
> - boot + suspend tested on OMAP4 panda ES (omap4460)
> - boot tested on beagle bone (am335x)
>
> A boot test was also executed for DRA7 and OMAP5 on a separate branch
> (mainline does not have OMAP5 / DRA7 support so far.)
>
> TODO:
> - Add AM35xx support (OMAP3 derivative, AM35xx only clock nodes missing)
>
> Overall diffstat added just for fun:
>
>   arch/arm/boot/dts/am33xx-clocks.dtsi               |  663 ++++
>   arch/arm/boot/dts/am33xx.dtsi                      |    7 +
>   arch/arm/boot/dts/dra7xx-clocks.dtsi               | 2113 ++++++++++++
>   arch/arm/boot/dts/omap3.dtsi                       |    7 +
>   arch/arm/boot/dts/omap3430es1-clocks.dtsi          |  166 +
>   arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi    |  240 ++
>   arch/arm/boot/dts/omap34xx.dtsi                    |    9 +
>   .../omap36xx-am35xx-omap3430es2plus-clocks.dtsi    |  214 ++
>   arch/arm/boot/dts/omap36xx-clocks.dtsi             |   97 +
>   .../boot/dts/omap36xx-omap3430es2plus-clocks.dtsi  |  185 +
>   arch/arm/boot/dts/omap36xx.dtsi                    |   10 +
>   arch/arm/boot/dts/omap3xxx-clocks.dtsi             | 1594 +++++++++
>   arch/arm/boot/dts/omap443x-clocks.dtsi             |   17 +
>   arch/arm/boot/dts/omap443x.dtsi                    |    8 +
>   arch/arm/boot/dts/omap4460.dtsi                    |    8 +
>   arch/arm/boot/dts/omap446x-clocks.dtsi             |   27 +
>   arch/arm/boot/dts/omap44xx-clocks.dtsi             | 1654 +++++++++
>   arch/arm/boot/dts/omap54xx-clocks.dtsi             | 1416 ++++++++
>   arch/arm/mach-omap2/Makefile                       |    5 +-
>   arch/arm/mach-omap2/cclock33xx_data.c              | 1059 ------
>   arch/arm/mach-omap2/cclock3xxx_data.c              | 3641 --------------------
>   arch/arm/mach-omap2/cclock44xx_data.c              | 1730 ----------
>   arch/arm/mach-omap2/clock.c                        |    6 +
>   arch/arm/mach-omap2/clock.h                        |  163 +-
>   arch/arm/mach-omap2/clock3xxx.h                    |    7 +-
>   arch/arm/mach-omap2/io.c                           |    7 +-
>   arch/arm/mach-omap2/omap_hwmod.c                   |    5 +-
>   drivers/clk/Makefile                               |    1 +
>   drivers/clk/clk-divider.c                          |    6 +-
>   drivers/clk/clk-fixed-factor.c                     |    6 +-
>   drivers/clk/clk-gate.c                             |    8 +-
>   drivers/clk/clk-mux.c                              |    6 +-
>   drivers/clk/clkdev.c                               |   32 +
>   drivers/clk/omap/Makefile                          |    4 +
>   drivers/clk/omap/apll.c                            |  213 ++
>   drivers/clk/omap/autoidle.c                        |  130 +
>   drivers/clk/omap/clk-33xx.c                        |   85 +
>   drivers/clk/omap/clk-3xxx.c                        |  171 +
>   drivers/clk/omap/clk-44xx.c                        |  118 +
>   drivers/clk/omap/clk-54xx.c                        |   58 +
>   drivers/clk/omap/clk-7xx.c                         |   67 +
>   drivers/clk/omap/clk.c                             |   84 +
>   drivers/clk/omap/dpll.c                            |  387 +++
>   drivers/clk/omap/gate.c                            |  166 +
>   drivers/clk/omap/interface.c                       |  110 +
>   include/linux/clk/omap.h                           |  223 ++
>   46 files changed, 10327 insertions(+), 6606 deletions(-)
>
> -Tero
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

Re: [PATCHv4 00/33] ARM: OMAP: clock conversion to DT

[Roger Quadros]

[-- Attachment #1: Type: text/plain, Size: 930 bytes --]

On 07/23/2013 10:19 AM, Tero Kristo wrote:
> Hi,
> 
> Changes compared to previous version:
> 
> - Clock init files moved from mach-omap2/ to drivers/clk/omap/
> - AM33xx support added [patches 15-20]
> - OMAP3 support added [patches 21-29]
> - DRA7 APLL support added (thanks Keerthy) [patches 30-33]
> 
> Test branch on top of 3.11-rc1 available here:
> 
> git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
> branch: mainline-3.11-rc1-omap-dt-clks
> 
> Testing done:
> 
> - boot + suspend tested on OMAP3 beagle C4 (omap3530)
> - boot + suspend tested on OMAP4 panda ES (omap4460)
> - boot tested on beagle bone (am335x)
> 
> A boot test was also executed for DRA7 and OMAP5 on a separate branch
> (mainline does not have OMAP5 / DRA7 support so far.)

Thanks to your hints, I was able to get this to work with 3.11-rc1 on omap5 uevm
using the following 3 patches. Please include them in your series. Thanks.

cheers,
-roger

[-- Attachment #2: 0001-ARM-dts-OMAP5-Provide-clock-tree-data.patch --]
[-- Type: text/x-patch, Size: 802 bytes --]

>From f7e38deadead5f584c9de4f2f19bb5ab50a2641d Mon Sep 17 00:00:00 2001
From: Roger Quadros <rogerq@ti.com>
Date: Wed, 24 Jul 2013 17:02:56 +0300
Subject: [PATCH 1/3] ARM: dts: OMAP5: Provide clock tree data

Include the clock tree data for OMAP5

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index e643620..bc31022 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -45,6 +45,13 @@
 		};
 	};
 
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		/include/ "omap54xx-clocks.dtsi"
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		/* PPI secure/nonsecure IRQ */
-- 
1.7.4.1


[-- Attachment #3: 0002-CLK-omap5-Call-clock-init-function-at-boot.patch --]
[-- Type: text/x-patch, Size: 1311 bytes --]

>From 810920058782e4d51c0aab5694fc7cffc53e9758 Mon Sep 17 00:00:00 2001
From: Roger Quadros <rogerq@ti.com>
Date: Wed, 24 Jul 2013 17:05:00 +0300
Subject: [PATCH 2/3] CLK: omap5: Call clock init function at boot

omap5xxx_clk_init() needs to be called at boot.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/mach-omap2/io.c |    1 +
 include/linux/clk/omap.h |    2 ++
 2 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index f3b7876..7d42e26 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -653,6 +653,7 @@ void __init omap5_init_early(void)
 	omap54xx_clockdomains_init();
 	omap54xx_hwmod_init();
 	omap_hwmod_init_postsetup();
+	omap_clk_init = omap5xxx_clk_init;
 }
 #endif
 
diff --git a/include/linux/clk/omap.h b/include/linux/clk/omap.h
index 0d70cd1..4b82485 100644
--- a/include/linux/clk/omap.h
+++ b/include/linux/clk/omap.h
@@ -197,6 +197,8 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 
 void omap3_clk_lock_dpll5(void);
 
+int omap5xxx_clk_init(void);
+
 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
-- 
1.7.4.1


[-- Attachment #4: 0003-CLK-omap5-Initialize-USB_DPLL-at-boot.patch --]
[-- Type: text/x-patch, Size: 1552 bytes --]

>From 8836bc00aea3c97206244c3f8a66e2726c835854 Mon Sep 17 00:00:00 2001
From: Roger Quadros <rogerq@ti.com>
Date: Wed, 24 Jul 2013 16:30:55 +0300
Subject: [PATCH 3/3] CLK: omap5: Initialize USB_DPLL at boot

USB_DPLL must be initialized and locked at boot so that
USB modules can work.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 drivers/clk/omap/clk-54xx.c |   13 ++++++++++++-
 1 files changed, 12 insertions(+), 1 deletions(-)

diff --git a/drivers/clk/omap/clk-54xx.c b/drivers/clk/omap/clk-54xx.c
index ade0481..a0b3c14 100644
--- a/drivers/clk/omap/clk-54xx.c
+++ b/drivers/clk/omap/clk-54xx.c
@@ -19,6 +19,12 @@
 
 #define OMAP5_DPLL_ABE_DEFFREQ				98304000
 
+/*
+ * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
+ * states it must be at 960MHz
+ */
+#define OMAP5_DPLL_USB_DEFFREQ				960000000
+
 static struct omap_dt_clk omap54xx_clks[] = {
 	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
 	DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"),
@@ -37,7 +43,7 @@ static struct omap_dt_clk omap54xx_clks[] = {
 int __init omap5xxx_clk_init(void)
 {
 	int rc;
-	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck;
+	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
 
 	dt_omap_clk_init();
 
@@ -54,5 +60,10 @@ int __init omap5xxx_clk_init(void)
 	if (rc)
 		pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 
+	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
+	rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
+	if (rc)
+		pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
 	return 0;
 }
-- 
1.7.4.1

[PATCHv4 00/33] ARM: OMAP: clock conversion to DT

[Roger Quadros]

On 07/23/2013 10:19 AM, Tero Kristo wrote:
> Hi,
> 
> Changes compared to previous version:
> 
> - Clock init files moved from mach-omap2/ to drivers/clk/omap/
> - AM33xx support added [patches 15-20]
> - OMAP3 support added [patches 21-29]
> - DRA7 APLL support added (thanks Keerthy) [patches 30-33]
> 
> Test branch on top of 3.11-rc1 available here:
> 
> git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
> branch: mainline-3.11-rc1-omap-dt-clks
> 
> Testing done:
> 
> - boot + suspend tested on OMAP3 beagle C4 (omap3530)
> - boot + suspend tested on OMAP4 panda ES (omap4460)
> - boot tested on beagle bone (am335x)
> 
> A boot test was also executed for DRA7 and OMAP5 on a separate branch
> (mainline does not have OMAP5 / DRA7 support so far.)

Thanks to your hints, I was able to get this to work with 3.11-rc1 on omap5 uevm
using the following 3 patches. Please include them in your series. Thanks.

cheers,
-roger
-------------- next part --------------
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Re: [PATCHv4 00/33] ARM: OMAP: clock conversion to DT

[Tero Kristo]

On 07/24/2013 05:16 PM, Roger Quadros wrote:
> On 07/23/2013 10:19 AM, Tero Kristo wrote:
>> Hi,
>>
>> Changes compared to previous version:
>>
>> - Clock init files moved from mach-omap2/ to drivers/clk/omap/
>> - AM33xx support added [patches 15-20]
>> - OMAP3 support added [patches 21-29]
>> - DRA7 APLL support added (thanks Keerthy) [patches 30-33]
>>
>> Test branch on top of 3.11-rc1 available here:
>>
>> git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
>> branch: mainline-3.11-rc1-omap-dt-clks
>>
>> Testing done:
>>
>> - boot + suspend tested on OMAP3 beagle C4 (omap3530)
>> - boot + suspend tested on OMAP4 panda ES (omap4460)
>> - boot tested on beagle bone (am335x)
>>
>> A boot test was also executed for DRA7 and OMAP5 on a separate branch
>> (mainline does not have OMAP5 / DRA7 support so far.)
>
> Thanks to your hints, I was able to get this to work with 3.11-rc1 on omap5 uevm
> using the following 3 patches. Please include them in your series. Thanks.

Your patches don't apply cleanly to mainline currently, as the omap5 
base support is still not merged. I deliberately left out the full omap5 
integration because of that. Lets see how and when the integration 
proceeds, but I can track your patches meanwhile.

-Tero

[PATCHv4 00/33] ARM: OMAP: clock conversion to DT

[Tero Kristo]

On 07/24/2013 05:16 PM, Roger Quadros wrote:
> On 07/23/2013 10:19 AM, Tero Kristo wrote:
>> Hi,
>>
>> Changes compared to previous version:
>>
>> - Clock init files moved from mach-omap2/ to drivers/clk/omap/
>> - AM33xx support added [patches 15-20]
>> - OMAP3 support added [patches 21-29]
>> - DRA7 APLL support added (thanks Keerthy) [patches 30-33]
>>
>> Test branch on top of 3.11-rc1 available here:
>>
>> git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
>> branch: mainline-3.11-rc1-omap-dt-clks
>>
>> Testing done:
>>
>> - boot + suspend tested on OMAP3 beagle C4 (omap3530)
>> - boot + suspend tested on OMAP4 panda ES (omap4460)
>> - boot tested on beagle bone (am335x)
>>
>> A boot test was also executed for DRA7 and OMAP5 on a separate branch
>> (mainline does not have OMAP5 / DRA7 support so far.)
>
> Thanks to your hints, I was able to get this to work with 3.11-rc1 on omap5 uevm
> using the following 3 patches. Please include them in your series. Thanks.

Your patches don't apply cleanly to mainline currently, as the omap5 
base support is still not merged. I deliberately left out the full omap5 
integration because of that. Lets see how and when the integration 
proceeds, but I can track your patches meanwhile.

-Tero

Re: [PATCHv4 00/33] ARM: OMAP: clock conversion to DT

[Roger Quadros]

On 07/24/2013 05:29 PM, Tero Kristo wrote:
> On 07/24/2013 05:16 PM, Roger Quadros wrote:
>> On 07/23/2013 10:19 AM, Tero Kristo wrote:
>>> Hi,
>>>
>>> Changes compared to previous version:
>>>
>>> - Clock init files moved from mach-omap2/ to drivers/clk/omap/
>>> - AM33xx support added [patches 15-20]
>>> - OMAP3 support added [patches 21-29]
>>> - DRA7 APLL support added (thanks Keerthy) [patches 30-33]
>>>
>>> Test branch on top of 3.11-rc1 available here:
>>>
>>> git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
>>> branch: mainline-3.11-rc1-omap-dt-clks
>>>
>>> Testing done:
>>>
>>> - boot + suspend tested on OMAP3 beagle C4 (omap3530)
>>> - boot + suspend tested on OMAP4 panda ES (omap4460)
>>> - boot tested on beagle bone (am335x)
>>>
>>> A boot test was also executed for DRA7 and OMAP5 on a separate branch
>>> (mainline does not have OMAP5 / DRA7 support so far.)
>>
>> Thanks to your hints, I was able to get this to work with 3.11-rc1 on omap5 uevm
>> using the following 3 patches. Please include them in your series. Thanks.
> 
> Your patches don't apply cleanly to mainline currently, as the omap5 base support is still not merged. I deliberately left out the full omap5 integration because of that. Lets see how and when the integration proceeds, but I can track your patches meanwhile.
>

Strange, I didn't use any out of tree patch. Just 3.11-rc1 with your 33 patches on top.

Are you on 3.11-rc2?

cheers,
-roger

[PATCHv4 00/33] ARM: OMAP: clock conversion to DT

[Roger Quadros]

On 07/24/2013 05:29 PM, Tero Kristo wrote:
> On 07/24/2013 05:16 PM, Roger Quadros wrote:
>> On 07/23/2013 10:19 AM, Tero Kristo wrote:
>>> Hi,
>>>
>>> Changes compared to previous version:
>>>
>>> - Clock init files moved from mach-omap2/ to drivers/clk/omap/
>>> - AM33xx support added [patches 15-20]
>>> - OMAP3 support added [patches 21-29]
>>> - DRA7 APLL support added (thanks Keerthy) [patches 30-33]
>>>
>>> Test branch on top of 3.11-rc1 available here:
>>>
>>> git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
>>> branch: mainline-3.11-rc1-omap-dt-clks
>>>
>>> Testing done:
>>>
>>> - boot + suspend tested on OMAP3 beagle C4 (omap3530)
>>> - boot + suspend tested on OMAP4 panda ES (omap4460)
>>> - boot tested on beagle bone (am335x)
>>>
>>> A boot test was also executed for DRA7 and OMAP5 on a separate branch
>>> (mainline does not have OMAP5 / DRA7 support so far.)
>>
>> Thanks to your hints, I was able to get this to work with 3.11-rc1 on omap5 uevm
>> using the following 3 patches. Please include them in your series. Thanks.
> 
> Your patches don't apply cleanly to mainline currently, as the omap5 base support is still not merged. I deliberately left out the full omap5 integration because of that. Lets see how and when the integration proceeds, but I can track your patches meanwhile.
>

Strange, I didn't use any out of tree patch. Just 3.11-rc1 with your 33 patches on top.

Are you on 3.11-rc2?

cheers,
-roger

Re: [PATCHv4 00/33] ARM: OMAP: clock conversion to DT

[Tero Kristo]

On 07/24/2013 05:34 PM, Roger Quadros wrote:
> On 07/24/2013 05:29 PM, Tero Kristo wrote:
>> On 07/24/2013 05:16 PM, Roger Quadros wrote:
>>> On 07/23/2013 10:19 AM, Tero Kristo wrote:
>>>> Hi,
>>>>
>>>> Changes compared to previous version:
>>>>
>>>> - Clock init files moved from mach-omap2/ to drivers/clk/omap/
>>>> - AM33xx support added [patches 15-20]
>>>> - OMAP3 support added [patches 21-29]
>>>> - DRA7 APLL support added (thanks Keerthy) [patches 30-33]
>>>>
>>>> Test branch on top of 3.11-rc1 available here:
>>>>
>>>> git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
>>>> branch: mainline-3.11-rc1-omap-dt-clks
>>>>
>>>> Testing done:
>>>>
>>>> - boot + suspend tested on OMAP3 beagle C4 (omap3530)
>>>> - boot + suspend tested on OMAP4 panda ES (omap4460)
>>>> - boot tested on beagle bone (am335x)
>>>>
>>>> A boot test was also executed for DRA7 and OMAP5 on a separate branch
>>>> (mainline does not have OMAP5 / DRA7 support so far.)
>>>
>>> Thanks to your hints, I was able to get this to work with 3.11-rc1 on omap5 uevm
>>> using the following 3 patches. Please include them in your series. Thanks.
>>
>> Your patches don't apply cleanly to mainline currently, as the omap5 base support is still not merged. I deliberately left out the full omap5 integration because of that. Lets see how and when the integration proceeds, but I can track your patches meanwhile.
>>
>
> Strange, I didn't use any out of tree patch. Just 3.11-rc1 with your 33 patches on top.
>
> Are you on 3.11-rc2?

Oh, so OMAP5 hwmod data was actually merged now, cool. Sorry about the 
fuss. I can include your patches to the next rev if one is made.

-Tero

[PATCHv4 00/33] ARM: OMAP: clock conversion to DT

[Tero Kristo]

On 07/24/2013 05:34 PM, Roger Quadros wrote:
> On 07/24/2013 05:29 PM, Tero Kristo wrote:
>> On 07/24/2013 05:16 PM, Roger Quadros wrote:
>>> On 07/23/2013 10:19 AM, Tero Kristo wrote:
>>>> Hi,
>>>>
>>>> Changes compared to previous version:
>>>>
>>>> - Clock init files moved from mach-omap2/ to drivers/clk/omap/
>>>> - AM33xx support added [patches 15-20]
>>>> - OMAP3 support added [patches 21-29]
>>>> - DRA7 APLL support added (thanks Keerthy) [patches 30-33]
>>>>
>>>> Test branch on top of 3.11-rc1 available here:
>>>>
>>>> git://gitorious.org/~kristo/omap-pm/omap-pm-work.git
>>>> branch: mainline-3.11-rc1-omap-dt-clks
>>>>
>>>> Testing done:
>>>>
>>>> - boot + suspend tested on OMAP3 beagle C4 (omap3530)
>>>> - boot + suspend tested on OMAP4 panda ES (omap4460)
>>>> - boot tested on beagle bone (am335x)
>>>>
>>>> A boot test was also executed for DRA7 and OMAP5 on a separate branch
>>>> (mainline does not have OMAP5 / DRA7 support so far.)
>>>
>>> Thanks to your hints, I was able to get this to work with 3.11-rc1 on omap5 uevm
>>> using the following 3 patches. Please include them in your series. Thanks.
>>
>> Your patches don't apply cleanly to mainline currently, as the omap5 base support is still not merged. I deliberately left out the full omap5 integration because of that. Lets see how and when the integration proceeds, but I can track your patches meanwhile.
>>
>
> Strange, I didn't use any out of tree patch. Just 3.11-rc1 with your 33 patches on top.
>
> Are you on 3.11-rc2?

Oh, so OMAP5 hwmod data was actually merged now, cool. Sorry about the 
fuss. I can include your patches to the next rev if one is made.

-Tero

Re: [PATCHv4 29/33] CLK: omap: add omap3 clock init file

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> clk-3xxx.c now contains the clock init functionality for omap3, including
> DT clock registration and adding of static clkdev entries.
>
> This patch also splits the OMAP3 clock registration code under mach-omap2
> to use OMAP3 subtype specific clk init functions.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   arch/arm/mach-omap2/Makefile          |    2 +-
>   arch/arm/mach-omap2/cclock3xxx_data.c | 3641 ---------------------------------

Tony and a lot of people is not going to like removing support for 
non-dt boot for OMAP3 before "it's time is due" ;)



-- 
Regards,
Nishanth Menon

[PATCHv4 29/33] CLK: omap: add omap3 clock init file

[Nishanth Menon]

On 07/23/2013 02:20 AM, Tero Kristo wrote:
> clk-3xxx.c now contains the clock init functionality for omap3, including
> DT clock registration and adding of static clkdev entries.
>
> This patch also splits the OMAP3 clock registration code under mach-omap2
> to use OMAP3 subtype specific clk init functions.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>   arch/arm/mach-omap2/Makefile          |    2 +-
>   arch/arm/mach-omap2/cclock3xxx_data.c | 3641 ---------------------------------

Tony and a lot of people is not going to like removing support for 
non-dt boot for OMAP3 before "it's time is due" ;)



-- 
Regards,
Nishanth Menon

Re: [PATCHv4 29/33] CLK: omap: add omap3 clock init file

[Tony Lindgren]

* Nishanth Menon <nm@ti.com> [130730 13:26]:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
> >clk-3xxx.c now contains the clock init functionality for omap3, including
> >DT clock registration and adding of static clkdev entries.
> >
> >This patch also splits the OMAP3 clock registration code under mach-omap2
> >to use OMAP3 subtype specific clk init functions.
> >
> >Signed-off-by: Tero Kristo <t-kristo@ti.com>
> >---
> >  arch/arm/mach-omap2/Makefile          |    2 +-
> >  arch/arm/mach-omap2/cclock3xxx_data.c | 3641 ---------------------------------
> 
> Tony and a lot of people is not going to like removing support for
> non-dt boot for OMAP3 before "it's time is due" ;)

I think the only showstopper for that is that we need the
pending pinctrl changes merged first to keep off-idle working.
So the omap3 legacy code removal probably needs to wait until
v3.13 merge window. For omap4 and am33xx we can do it now.

Regards,

Tony

[PATCHv4 29/33] CLK: omap: add omap3 clock init file

[Tony Lindgren]

* Nishanth Menon <nm@ti.com> [130730 13:26]:
> On 07/23/2013 02:20 AM, Tero Kristo wrote:
> >clk-3xxx.c now contains the clock init functionality for omap3, including
> >DT clock registration and adding of static clkdev entries.
> >
> >This patch also splits the OMAP3 clock registration code under mach-omap2
> >to use OMAP3 subtype specific clk init functions.
> >
> >Signed-off-by: Tero Kristo <t-kristo@ti.com>
> >---
> >  arch/arm/mach-omap2/Makefile          |    2 +-
> >  arch/arm/mach-omap2/cclock3xxx_data.c | 3641 ---------------------------------
> 
> Tony and a lot of people is not going to like removing support for
> non-dt boot for OMAP3 before "it's time is due" ;)

I think the only showstopper for that is that we need the
pending pinctrl changes merged first to keep off-idle working.
So the omap3 legacy code removal probably needs to wait until
v3.13 merge window. For omap4 and am33xx we can do it now.

Regards,

Tony

Re: [PATCHv4 29/33] CLK: omap: add omap3 clock init file

[Tero Kristo]

On 07/31/2013 09:35 AM, Tony Lindgren wrote:
> * Nishanth Menon <nm@ti.com> [130730 13:26]:
>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>> clk-3xxx.c now contains the clock init functionality for omap3, including
>>> DT clock registration and adding of static clkdev entries.
>>>
>>> This patch also splits the OMAP3 clock registration code under mach-omap2
>>> to use OMAP3 subtype specific clk init functions.
>>>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>> ---
>>>   arch/arm/mach-omap2/Makefile          |    2 +-
>>>   arch/arm/mach-omap2/cclock3xxx_data.c | 3641 ---------------------------------
>>
>> Tony and a lot of people is not going to like removing support for
>> non-dt boot for OMAP3 before "it's time is due" ;)
>
> I think the only showstopper for that is that we need the
> pending pinctrl changes merged first to keep off-idle working.
> So the omap3 legacy code removal probably needs to wait until
> v3.13 merge window. For omap4 and am33xx we can do it now.
>
> Regards,
>
> Tony
>

I'll modify the series in such way that OMAP3 retains the legacy clock 
data within the kernel for now, and will use either DT or kernel data 
based on init type. Kernel data can then be removed when time is ripe 
for it.

-Tero

[PATCHv4 29/33] CLK: omap: add omap3 clock init file

[Tero Kristo]

On 07/31/2013 09:35 AM, Tony Lindgren wrote:
> * Nishanth Menon <nm@ti.com> [130730 13:26]:
>> On 07/23/2013 02:20 AM, Tero Kristo wrote:
>>> clk-3xxx.c now contains the clock init functionality for omap3, including
>>> DT clock registration and adding of static clkdev entries.
>>>
>>> This patch also splits the OMAP3 clock registration code under mach-omap2
>>> to use OMAP3 subtype specific clk init functions.
>>>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>> ---
>>>   arch/arm/mach-omap2/Makefile          |    2 +-
>>>   arch/arm/mach-omap2/cclock3xxx_data.c | 3641 ---------------------------------
>>
>> Tony and a lot of people is not going to like removing support for
>> non-dt boot for OMAP3 before "it's time is due" ;)
>
> I think the only showstopper for that is that we need the
> pending pinctrl changes merged first to keep off-idle working.
> So the omap3 legacy code removal probably needs to wait until
> v3.13 merge window. For omap4 and am33xx we can do it now.
>
> Regards,
>
> Tony
>

I'll modify the series in such way that OMAP3 retains the legacy clock 
data within the kernel for now, and will use either DT or kernel data 
based on init type. Kernel data can then be removed when time is ripe 
for it.

-Tero

Re: [PATCHv4 29/33] CLK: omap: add omap3 clock init file

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [130731 08:17]:
> On 07/31/2013 09:35 AM, Tony Lindgren wrote:
> >* Nishanth Menon <nm@ti.com> [130730 13:26]:
> >>
> >>Tony and a lot of people is not going to like removing support for
> >>non-dt boot for OMAP3 before "it's time is due" ;)
> >
> >I think the only showstopper for that is that we need the
> >pending pinctrl changes merged first to keep off-idle working.
> >So the omap3 legacy code removal probably needs to wait until
> >v3.13 merge window. For omap4 and am33xx we can do it now.
> 
> I'll modify the series in such way that OMAP3 retains the legacy
> clock data within the kernel for now, and will use either DT or
> kernel data based on init type. Kernel data can then be removed when
> time is ripe for it.

OK thanks sounds good to me.

Regards,

Tony

[PATCHv4 29/33] CLK: omap: add omap3 clock init file

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [130731 08:17]:
> On 07/31/2013 09:35 AM, Tony Lindgren wrote:
> >* Nishanth Menon <nm@ti.com> [130730 13:26]:
> >>
> >>Tony and a lot of people is not going to like removing support for
> >>non-dt boot for OMAP3 before "it's time is due" ;)
> >
> >I think the only showstopper for that is that we need the
> >pending pinctrl changes merged first to keep off-idle working.
> >So the omap3 legacy code removal probably needs to wait until
> >v3.13 merge window. For omap4 and am33xx we can do it now.
> 
> I'll modify the series in such way that OMAP3 retains the legacy
> clock data within the kernel for now, and will use either DT or
> kernel data based on init type. Kernel data can then be removed when
> time is ripe for it.

OK thanks sounds good to me.

Regards,

Tony