* [U-Boot] [UBOOT][PATCHv6 1/6] omap5: add qspi support
2013-10-07 10:22 [U-Boot] [UBOOT][PATCHv6 0/6] Add TI qspi controller with memory mapped support Sourav Poddar
@ 2013-10-07 10:22 ` Sourav Poddar
2013-10-07 10:23 ` [U-Boot] [UBOOT][PATCHv6 2/6] armv7: hw_data: change clock divider setting Sourav Poddar
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Sourav Poddar @ 2013-10-07 10:22 UTC (permalink / raw)
To: u-boot
From: Matt Porter <matt.porter@linaro.org>
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
arch/arm/cpu/armv7/omap5/hw_data.c | 8 ++++++++
arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 +
arch/arm/include/asm/arch-omap5/omap.h | 3 +++
arch/arm/include/asm/arch-omap5/spl.h | 1 +
arch/arm/include/asm/omap_common.h | 1 +
5 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index fbbc486..c00bfb8 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -426,6 +426,10 @@ void enable_basic_clocks(void)
#ifdef CONFIG_DRIVER_TI_CPSW
(*prcm)->cm_gmac_gmac_clkctrl,
#endif
+
+#ifdef CONFIG_TI_QSPI
+ (*prcm)->cm_l4per_qspi_clkctrl,
+#endif
0
};
@@ -454,6 +458,10 @@ void enable_basic_clocks(void)
clk_modules_explicit_en_essential,
1);
+#ifdef CONFIG_TI_QSPI
+ setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
+#endif
+
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 579818d..0b1bb46 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -933,6 +933,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_l4per_gpio8_clkctrl = 0x4a009818,
.cm_l4per_mmcsd3_clkctrl = 0x4a009820,
.cm_l4per_mmcsd4_clkctrl = 0x4a009828,
+ .cm_l4per_qspi_clkctrl = 0x4a009838,
.cm_l4per_uart1_clkctrl = 0x4a009840,
.cm_l4per_uart2_clkctrl = 0x4a009848,
.cm_l4per_uart3_clkctrl = 0x4a009850,
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index e9a51d3..414d37a 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -61,6 +61,9 @@
/* GPMC */
#define OMAP54XX_GPMC_BASE 0x50000000
+/* QSPI */
+#define QSPI_BASE 0x4B300000
+
/*
* Hardware Register Details
*/
diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h
index fe8b0c0..57f0de5 100644
--- a/arch/arm/include/asm/arch-omap5/spl.h
+++ b/arch/arm/include/asm/arch-omap5/spl.h
@@ -15,6 +15,7 @@
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 7
+#define BOOT_DEVICE_SPI 10
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 5e2f027..f865c14 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -266,6 +266,7 @@ struct prcm_regs {
u32 cm_l4per_mmcsd4_clkctrl;
u32 cm_l4per_msprohg_clkctrl;
u32 cm_l4per_slimbus2_clkctrl;
+ u32 cm_l4per_qspi_clkctrl;
u32 cm_l4per_uart1_clkctrl;
u32 cm_l4per_uart2_clkctrl;
u32 cm_l4per_uart3_clkctrl;
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [UBOOT][PATCHv6 2/6] armv7: hw_data: change clock divider setting.
2013-10-07 10:22 [U-Boot] [UBOOT][PATCHv6 0/6] Add TI qspi controller with memory mapped support Sourav Poddar
2013-10-07 10:22 ` [U-Boot] [UBOOT][PATCHv6 1/6] omap5: add qspi support Sourav Poddar
@ 2013-10-07 10:23 ` Sourav Poddar
2013-10-07 10:23 ` [U-Boot] [UBOOT][PATCHv6 3/6] sf: Add memory mapped read support Sourav Poddar
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Sourav Poddar @ 2013-10-07 10:23 UTC (permalink / raw)
To: u-boot
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,
f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)
fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
arch/arm/cpu/armv7/omap5/hw_data.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index c00bfb8..a1b249e 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -170,7 +170,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
- {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
+ {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [UBOOT][PATCHv6 3/6] sf: Add memory mapped read support
2013-10-07 10:22 [U-Boot] [UBOOT][PATCHv6 0/6] Add TI qspi controller with memory mapped support Sourav Poddar
2013-10-07 10:22 ` [U-Boot] [UBOOT][PATCHv6 1/6] omap5: add qspi support Sourav Poddar
2013-10-07 10:23 ` [U-Boot] [UBOOT][PATCHv6 2/6] armv7: hw_data: change clock divider setting Sourav Poddar
@ 2013-10-07 10:23 ` Sourav Poddar
2013-10-07 10:23 ` [U-Boot] [UBOOT][PATCHv6 4/6] spi: add TI QSPI driver Sourav Poddar
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Sourav Poddar @ 2013-10-07 10:23 UTC (permalink / raw)
To: u-boot
Qspi controller can have a memory mapped port which can be used for
data read. Added support to enable memory mapped port read.
This patch enables the following:
- It enables exchange of memory map address between mtd and qspi
through the introduction of "memory_map" flag.
- Add support to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
"SPI_XFER_MEM_MAP" and "SPI_XFER_MEM_MAP_END".
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v5->v6:
Add proper tab space
drivers/mtd/spi/sf_ops.c | 2 ++
drivers/mtd/spi/sf_probe.c | 1 +
include/spi.h | 3 +++
3 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index c009af5..2396e22 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -269,7 +269,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
/* Handle memory-mapped SPI */
if (flash->memory_map) {
+ spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
memcpy(data, flash->memory_map + offset, len);
+ spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
return 0;
}
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 1525636..6aa7086 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -203,6 +203,7 @@ struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, u8 *idcode)
flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256;
flash->sector_size = params->sector_size;
flash->size = flash->sector_size * params->nr_sectors;
+ flash->memory_map = spi->memory_map;
/* Compute erase sector and command */
if (params->flags & SECT_4K) {
diff --git a/include/spi.h b/include/spi.h
index c44ebe8..c2086fc 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -27,6 +27,8 @@
/* SPI transfer flags */
#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
#define SPI_XFER_END 0x02 /* Deassert CS after transfer */
+#define SPI_XFER_MMAP 0x08 /* Memory Mapped start */
+#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
@@ -46,6 +48,7 @@ struct spi_slave {
unsigned int bus;
unsigned int cs;
unsigned int max_write_size;
+ void *memory_map;
};
/**
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [UBOOT][PATCHv6 4/6] spi: add TI QSPI driver
2013-10-07 10:22 [U-Boot] [UBOOT][PATCHv6 0/6] Add TI qspi controller with memory mapped support Sourav Poddar
` (2 preceding siblings ...)
2013-10-07 10:23 ` [U-Boot] [UBOOT][PATCHv6 3/6] sf: Add memory mapped read support Sourav Poddar
@ 2013-10-07 10:23 ` Sourav Poddar
2013-10-07 10:23 ` [U-Boot] [UBOOT][PATCHv6 5/6] dra7xx_evm: add SPL API, QSPI, and serial flash support Sourav Poddar
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Sourav Poddar @ 2013-10-07 10:23 UTC (permalink / raw)
To: u-boot
From: Matt Porter <matt.porter@linaro.org>
Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.
Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
v5->v6:
- Added ti related comments
- Created ti spec func for ti code
- Fixed few checkpatch.pl errors
- Rearranged the code.
drivers/spi/Makefile | 1 +
drivers/spi/ti_qspi.c | 311 +++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 312 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/ti_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..e5941b0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 0000000..5a5b482
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,311 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/omap.h>
+#include <malloc.h>
+#include <spi.h>
+
+/* ti qpsi register bit masks */
+#define QSPI_TIMEOUT 2000000
+#define QSPI_FCLK 192000000
+/* clock control */
+#define QSPI_CLK_EN (1 << 31)
+#define QSPI_CLK_DIV_MAX 0xffff
+/* command */
+#define QSPI_EN_CS(n) (n << 28)
+#define QSPI_WLEN(n) ((n-1) << 19)
+#define QSPI_3_PIN (1 << 18)
+#define QSPI_RD_SNGL (1 << 16)
+#define QSPI_WR_SNGL (2 << 16)
+#define QSPI_INVAL (4 << 16)
+#define QSPI_RD_QUAD (7 << 16)
+/* device control */
+#define QSPI_DD(m, n) (m << (3 + n*8))
+#define QSPI_CKPHA(n) (1 << (2 + n*8))
+#define QSPI_CSPOL(n) (1 << (1 + n*8))
+#define QSPI_CKPOL(n) (1 << (n*8))
+/* status */
+#define QSPI_WC (1 << 1)
+#define QSPI_BUSY (1 << 0)
+#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
+#define QSPI_XFER_DONE QSPI_WC
+#define MM_SWITCH 0x01
+#define MEM_CS 0x100
+#define MEM_CS_UNSELECT 0xfffff0ff
+#define MMAP_START_ADDR 0x5c000000
+#define CORE_CTRL_IO 0x4a002558
+
+#define QSPI_CMD_READ (0x3 << 0)
+#define QSPI_CMD_READ_QUAD (0x6b << 0)
+#define QSPI_CMD_READ_FAST (0x0b << 0)
+#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8)
+#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
+#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
+#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
+#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
+#define QSPI_CMD_WRITE (0x2 << 16)
+#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
+
+/* ti qspi register set */
+struct ti_qspi_regs {
+ u32 pid;
+ u32 pad0[3];
+ u32 sysconfig;
+ u32 pad1[3];
+ u32 int_stat_raw;
+ u32 int_stat_en;
+ u32 int_en_set;
+ u32 int_en_ctlr;
+ u32 intc_eoi;
+ u32 pad2[3];
+ u32 clk_ctrl;
+ u32 dc;
+ u32 cmd;
+ u32 status;
+ u32 data;
+ u32 setup0;
+ u32 setup1;
+ u32 setup2;
+ u32 setup3;
+ u32 memswitch;
+ u32 data1;
+ u32 data2;
+ u32 data3;
+};
+
+/* ti qspi slave */
+struct ti_qspi_slave {
+ struct spi_slave slave;
+ struct ti_qspi_regs *base;
+ unsigned int mode;
+ u32 cmd;
+ u32 dc;
+};
+
+static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct ti_qspi_slave, slave);
+}
+
+static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
+{
+ struct spi_slave *slave = &qslave->slave;
+ u32 memval = 0;
+
+ slave->memory_map = (void *)MMAP_START_ADDR;
+
+ memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
+ QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
+ QSPI_NUM_DUMMY_BITS;
+
+ writel(memval, &qslave->base->setup0);
+}
+
+static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
+{
+ struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+ uint clk_div;
+
+ debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
+
+ if (!hz)
+ clk_div = 0;
+ else
+ clk_div = (QSPI_FCLK / hz) - 1;
+
+ /* disable SCLK */
+ writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN,
+ &qslave->base->clk_ctrl);
+
+ /* assign clk_div values */
+ if (clk_div < 0)
+ clk_div = 0;
+ else if (clk_div > QSPI_CLK_DIV_MAX)
+ clk_div = QSPI_CLK_DIV_MAX;
+
+ /* enable SCLK */
+ writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+
+ debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
+
+ writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
+}
+
+void spi_init(void)
+{
+ /* nothing to do */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct ti_qspi_slave *qslave;
+
+ qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
+ if (!qslave) {
+ printf("SPI_error: Fail to allocate ti_qspi_slave\n");
+ return NULL;
+ }
+
+ qslave->base = (struct ti_qspi_regs *)QSPI_BASE;
+ qslave->mode = mode;
+
+ ti_spi_set_speed(&qslave->slave, max_hz);
+
+#ifdef CONFIG_TI_SPI_MMAP
+ ti_spi_setup_spi_register(qslave);
+#endif
+
+ return &qslave->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+ free(qslave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+
+ debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
+
+ qslave->dc = 0;
+ if (qslave->mode & SPI_CPHA)
+ qslave->dc |= QSPI_CKPHA(slave->cs);
+ if (qslave->mode & SPI_CPOL)
+ qslave->dc |= QSPI_CKPOL(slave->cs);
+ if (qslave->mode & SPI_CS_HIGH)
+ qslave->dc |= QSPI_CSPOL(slave->cs);
+
+ writel(qslave->dc, &qslave->base->dc);
+ writel(0, &qslave->base->cmd);
+ writel(0, &qslave->base->data);
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+
+ debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
+
+ writel(0, &qslave->base->dc);
+ writel(0, &qslave->base->cmd);
+ writel(0, &qslave->base->data);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+ uint words = bitlen >> 3; /* fixed 8-bit word length */
+ const uchar *txp = dout;
+ uchar *rxp = din;
+ uint status;
+ int timeout, val;
+
+ debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
+ slave->bus, slave->cs, bitlen, words, flags);
+
+ /* Setup mmap flags */
+ if (flags & SPI_XFER_MMAP) {
+ writel(MM_SWITCH, &qslave->base->memswitch);
+ val = readl(CORE_CTRL_IO);
+ val |= MEM_CS;
+ writel(val, CORE_CTRL_IO);
+ return 0;
+ } else if (flags & SPI_XFER_MMAP_END) {
+ writel(~MM_SWITCH, &qslave->base->memswitch);
+ val = readl(CORE_CTRL_IO);
+ val &= MEM_CS_UNSELECT;
+ writel(val, CORE_CTRL_IO);
+ return 0;
+ }
+
+ if (bitlen == 0)
+ return -1;
+
+ if (bitlen % 8) {
+ debug("spi_xfer: Non byte aligned SPI transfer\n");
+ return -1;
+ }
+
+ /* Setup command reg */
+ qslave->cmd = 0;
+ qslave->cmd |= QSPI_WLEN(8);
+ qslave->cmd |= QSPI_EN_CS(slave->cs);
+ if (flags & SPI_3WIRE)
+ qslave->cmd |= QSPI_3_PIN;
+ qslave->cmd |= 0xfff;
+
+ while (words--) {
+ if (txp) {
+ debug("tx cmd %08x dc %08x data %02x\n",
+ qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp);
+ writel(*txp++, &qslave->base->data);
+ writel(qslave->cmd | QSPI_WR_SNGL,
+ &qslave->base->cmd);
+ status = readl(&qslave->base->status);
+ timeout = QSPI_TIMEOUT;
+ while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
+ if (--timeout < 0) {
+ printf("spi_xfer: TX timeout!\n");
+ return -1;
+ }
+ status = readl(&qslave->base->status);
+ }
+ debug("tx done, status %08x\n", status);
+ }
+ if (rxp) {
+ qslave->cmd |= QSPI_RD_SNGL;
+ debug("rx cmd %08x dc %08x\n",
+ qslave->cmd, qslave->dc);
+ writel(qslave->cmd, &qslave->base->cmd);
+ status = readl(&qslave->base->status);
+ timeout = QSPI_TIMEOUT;
+ while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
+ if (--timeout < 0) {
+ printf("spi_xfer: RX timeout!\n");
+ return -1;
+ }
+ status = readl(&qslave->base->status);
+ }
+ *rxp++ = readl(&qslave->base->data);
+ debug("rx done, status %08x, read %02x\n",
+ status, *(rxp-1));
+ }
+ }
+
+ /* Terminate frame */
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(slave);
+
+ return 0;
+}
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [UBOOT][PATCHv6 5/6] dra7xx_evm: add SPL API, QSPI, and serial flash support
2013-10-07 10:22 [U-Boot] [UBOOT][PATCHv6 0/6] Add TI qspi controller with memory mapped support Sourav Poddar
` (3 preceding siblings ...)
2013-10-07 10:23 ` [U-Boot] [UBOOT][PATCHv6 4/6] spi: add TI QSPI driver Sourav Poddar
@ 2013-10-07 10:23 ` Sourav Poddar
2013-10-07 10:23 ` [U-Boot] [UBOOT][PATCHv6 6/6] README: qspi usecase and testing documentation Sourav Poddar
2013-10-07 14:31 ` [U-Boot] [UBOOT][PATCHv6 0/6] Add TI qspi controller with memory mapped support Jagan Teki
6 siblings, 0 replies; 9+ messages in thread
From: Sourav Poddar @ 2013-10-07 10:23 UTC (permalink / raw)
To: u-boot
From: Matt Porter <matt.porter@linaro.org>
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v5->v6:
change MMAP name to amore readable name.
board/ti/dra7xx/mux_data.h | 10 ++++++++++
include/configs/dra7xx_evm.h | 19 +++++++++++++++++++
2 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 0a86594..6965cc5 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -51,5 +51,15 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{RGMII0_RXD2, (IEN | M0) },
{RGMII0_RXD1, (IEN | M0) },
{RGMII0_RXD0, (IEN | M0) },
+ {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
+ {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
+ {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
+ {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
+ {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
+ {GPMC_A18, (M1)}, /* QSPI1_SCLK */
+ {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
+ {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
+ {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
+ {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
};
#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 4fbe768..f9cfd18 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -42,4 +42,23 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 2
+/* SPI */
+#undef CONFIG_OMAP3_SPI
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_TI_SPI_MMAP
+#define CONFIG_SF_DEFAULT_SPEED 48000000
+#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+
#endif /* __CONFIG_DRA7XX_EVM_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [UBOOT][PATCHv6 6/6] README: qspi usecase and testing documentation.
2013-10-07 10:22 [U-Boot] [UBOOT][PATCHv6 0/6] Add TI qspi controller with memory mapped support Sourav Poddar
` (4 preceding siblings ...)
2013-10-07 10:23 ` [U-Boot] [UBOOT][PATCHv6 5/6] dra7xx_evm: add SPL API, QSPI, and serial flash support Sourav Poddar
@ 2013-10-07 10:23 ` Sourav Poddar
2013-10-07 14:31 ` [U-Boot] [UBOOT][PATCHv6 0/6] Add TI qspi controller with memory mapped support Jagan Teki
6 siblings, 0 replies; 9+ messages in thread
From: Sourav Poddar @ 2013-10-07 10:23 UTC (permalink / raw)
To: u-boot
Contains documentation and testing details for qspi flash
interface.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
doc/SPI/README.ti_qspi_dra_test | 48 +++++++++++++++++++++++++++++++++++++++
doc/SPI/README.ti_qspi_flash | 47 ++++++++++++++++++++++++++++++++++++++
2 files changed, 95 insertions(+), 0 deletions(-)
create mode 100644 doc/SPI/README.ti_qspi_dra_test
create mode 100644 doc/SPI/README.ti_qspi_flash
diff --git a/doc/SPI/README.ti_qspi_dra_test b/doc/SPI/README.ti_qspi_dra_test
new file mode 100644
index 0000000..fe37857
--- /dev/null
+++ b/doc/SPI/README.ti_qspi_dra_test
@@ -0,0 +1,48 @@
+-------------------------------------------------
+ Simple steps used to test the QSPI at U-Boot
+-------------------------------------------------
+
+For #1, build the patched U-Boot and load MLO/u-boot.img
+
+----------------------------------
+Boot from another medium like MMC
+----------------------------------
+
+U-Boot# mmc dev 0
+mmc0 is current device
+U-Boot# fatload mmc 0 0x82000000 MLO
+reading MLO
+55872 bytes read in 8 ms (6.7 MiB/s)
+U-Boot# fatload mmc 0 0x83000000 u-boot.img
+reading u-boot.img
+248600 bytes read in 19 ms (12.5 MiB/s)
+
+--------------------------------------------------
+Commands to erase/write u-boot/mlo to flash device
+--------------------------------------------------
+U-Boot# sf probe 0
+SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB, mapped at 5c000000
+SF: Warning - Only lower 16MiB accessible, Full access #define CONFIG_SPI_FLASH_BAR
+U-Boot# sf erase 0 0x10000
+SF: 65536 bytes @ 0x0 Erased: OK
+U-Boot# sf erase 0x20000 0x10000
+SF: 65536 bytes @ 0x20000 Erased: OK
+U-Boot# sf erase 0x30000 0x10000
+SF: 65536 bytes @ 0x30000 Erased: OK
+U-Boot# sf erase 0x40000 0x10000
+SF: 65536 bytes @ 0x40000 Erased: OK
+U-Boot# sf erase 0x50000 0x10000
+SF: 65536 bytes @ 0x50000 Erased: OK
+U-Boot# sf erase 0x60000 0x10000
+SF: 65536 bytes @ 0x60000 Erased: OK
+U-Boot# sf write 82000000 0 0x10000
+SF: 65536 bytes @ 0x0 Written: OK
+U-Boot# sf write 83000000 0x20000 0x60000
+SF: 393216 bytes @ 0x20000 Written: OK
+
+For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power
+on. ROM should find the GP header at offset 0 and load/execute SPL. SPL
+then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to
+find a U-Boot image header at offset 0x20000 (set in the config file)
+and proceeds to load that image using the U-Boot image payload offset/size
+from the header. It will then start U-Boot.
diff --git a/doc/SPI/README.ti_qspi_flash b/doc/SPI/README.ti_qspi_flash
new file mode 100644
index 0000000..1b86d01
--- /dev/null
+++ b/doc/SPI/README.ti_qspi_flash
@@ -0,0 +1,47 @@
+QSPI U-boot support
+------------------
+
+Host processor is connected to serial flash device via qpsi
+interface. QSPI is a kind of spi module that allows single,
+dual and quad read access to external spi devices. The module
+has a memory mapped interface which provide direct interface
+for accessing data form external spi devices.
+
+The one QSPI in the device is primarily intended for fast booting
+from Quad SPI flash devices.
+
+Usecase
+-------
+
+MLO/u-boot.img will be flashed from SD/MMC to the flash device
+using serial flash erase and write commands. Then, switch settings
+will be changed to qspi boot. Then, the ROM code will read MLO
+from the predefined location in the flash, where it was flashed and
+execute it after storing it in SDRAM. Then, the MLO will read
+u-boot.img from flash and execute it from SDRAM.
+
+SPI mode
+-------
+SPI mode uses mtd spi framework for transfer and reception of data.
+Can be used in:
+1. Normal mode: use single pin for transfers
+2. Dual Mode: use two pins for transfers.
+3. Quad mode: use four pin for transfer
+
+Memory mapped read mode
+-----------------------
+In this, SPI controller is configured using configuration port and then
+controler is switched to memory mapped port for data read.
+
+Driver
+------
+drivers/qspi/ti_qspi.c
+ - Newly created file which is responsible for configuring the
+ qspi controller and also for providing the low level api which
+ is responsible for transferring the datas from host controller
+ to flash device and vice versa.
+
+Testing
+-------
+A seperated file named README.dra_qspi_test has been created which gives all the
+details about the commands required to test qspi at u-boot level.
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [UBOOT][PATCHv6 0/6] Add TI qspi controller with memory mapped support.
2013-10-07 10:22 [U-Boot] [UBOOT][PATCHv6 0/6] Add TI qspi controller with memory mapped support Sourav Poddar
` (5 preceding siblings ...)
2013-10-07 10:23 ` [U-Boot] [UBOOT][PATCHv6 6/6] README: qspi usecase and testing documentation Sourav Poddar
@ 2013-10-07 14:31 ` Jagan Teki
2013-10-07 15:17 ` Sourav Poddar
6 siblings, 1 reply; 9+ messages in thread
From: Jagan Teki @ 2013-10-07 14:31 UTC (permalink / raw)
To: u-boot
On Mon, Oct 7, 2013 at 3:52 PM, Sourav Poddar <sourav.poddar@ti.com> wrote:
> This patch series add support for TI qspi controller and in the process also
> add support for quad read and memory mapped read
> in mtd spi framework.
>
> Testing details:
> Did a boot from qspi mode on DRA7xx.
> Testing details present in the last patch of
> the series.
>
> Currently, TI qpsi controller supports only 16MB access.
> Access for higher MB area will be added later.
>
> Patches are available at:
> git://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v7
>
> Matt Porter (3):
> omap5: add qspi support
> spi: add TI QSPI driver
> dra7xx_evm: add SPL API, QSPI, and serial flash support
>
> Sourav Poddar (3):
> armv7: hw_data: change clock divider setting.
> sf: Add memory mapped read support
> README: qspi usecase and testing documentation.
>
> arch/arm/cpu/armv7/omap5/hw_data.c | 10 +-
> arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 +
> arch/arm/include/asm/arch-omap5/omap.h | 3 +
> arch/arm/include/asm/arch-omap5/spl.h | 1 +
> arch/arm/include/asm/omap_common.h | 1 +
> board/ti/dra7xx/mux_data.h | 10 +
> doc/SPI/README.ti_qspi_dra_test | 48 +++++
> doc/SPI/README.ti_qspi_flash | 47 +++++
> drivers/mtd/spi/sf_ops.c | 2 +
> drivers/mtd/spi/sf_probe.c | 1 +
> drivers/spi/Makefile | 1 +
> drivers/spi/ti_qspi.c | 311 ++++++++++++++++++++++++++++++++
> include/configs/dra7xx_evm.h | 19 ++
> include/spi.h | 3 +
> 14 files changed, 457 insertions(+), 1 deletions(-)
> create mode 100644 doc/SPI/README.ti_qspi_dra_test
> create mode 100644 doc/SPI/README.ti_qspi_flash
> create mode 100644 drivers/spi/ti_qspi.c
>
Applied to u-boot-spi/master
--
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [UBOOT][PATCHv6 0/6] Add TI qspi controller with memory mapped support.
2013-10-07 14:31 ` [U-Boot] [UBOOT][PATCHv6 0/6] Add TI qspi controller with memory mapped support Jagan Teki
@ 2013-10-07 15:17 ` Sourav Poddar
0 siblings, 0 replies; 9+ messages in thread
From: Sourav Poddar @ 2013-10-07 15:17 UTC (permalink / raw)
To: u-boot
On Monday 07 October 2013 08:01 PM, Jagan Teki wrote:
> On Mon, Oct 7, 2013 at 3:52 PM, Sourav Poddar<sourav.poddar@ti.com> wrote:
>> This patch series add support for TI qspi controller and in the process also
>> add support for quad read and memory mapped read
>> in mtd spi framework.
>>
>> Testing details:
>> Did a boot from qspi mode on DRA7xx.
>> Testing details present in the last patch of
>> the series.
>>
>> Currently, TI qpsi controller supports only 16MB access.
>> Access for higher MB area will be added later.
>>
>> Patches are available at:
>> git://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v7
>>
>> Matt Porter (3):
>> omap5: add qspi support
>> spi: add TI QSPI driver
>> dra7xx_evm: add SPL API, QSPI, and serial flash support
>>
>> Sourav Poddar (3):
>> armv7: hw_data: change clock divider setting.
>> sf: Add memory mapped read support
>> README: qspi usecase and testing documentation.
>>
>> arch/arm/cpu/armv7/omap5/hw_data.c | 10 +-
>> arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 +
>> arch/arm/include/asm/arch-omap5/omap.h | 3 +
>> arch/arm/include/asm/arch-omap5/spl.h | 1 +
>> arch/arm/include/asm/omap_common.h | 1 +
>> board/ti/dra7xx/mux_data.h | 10 +
>> doc/SPI/README.ti_qspi_dra_test | 48 +++++
>> doc/SPI/README.ti_qspi_flash | 47 +++++
>> drivers/mtd/spi/sf_ops.c | 2 +
>> drivers/mtd/spi/sf_probe.c | 1 +
>> drivers/spi/Makefile | 1 +
>> drivers/spi/ti_qspi.c | 311 ++++++++++++++++++++++++++++++++
>> include/configs/dra7xx_evm.h | 19 ++
>> include/spi.h | 3 +
>> 14 files changed, 457 insertions(+), 1 deletions(-)
>> create mode 100644 doc/SPI/README.ti_qspi_dra_test
>> create mode 100644 doc/SPI/README.ti_qspi_flash
>> create mode 100644 drivers/spi/ti_qspi.c
>>
> Applied to u-boot-spi/master
>
Thanks!
^ permalink raw reply [flat|nested] 9+ messages in thread