* [Qemu-devel] [PATCH 01/15] target-tricore: Add target stubs and qom-cpu
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-07 19:09 ` Richard Henderson
` (2 more replies)
2014-07-07 18:13 ` [Qemu-devel] [PATCH 02/15] target-tricore: Add board for systemmode Bastian Koppelmann
` (13 subsequent siblings)
14 siblings, 3 replies; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add TriCore target stubs, QOM cpu and basic machine.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
arch_init.c | 2 +
configure | 13 ++
cpu-exec.c | 11 +-
cpus.c | 6 +
default-configs/tricore-softmmu.mak | 3 +
include/elf.h | 2 +
include/sysemu/arch_init.h | 1 +
target-tricore/Makefile.objs | 2 +
target-tricore/cpu-qom.h | 71 +++++++
target-tricore/cpu.c | 121 ++++++++++++
target-tricore/cpu.h | 380 ++++++++++++++++++++++++++++++++++++
target-tricore/helper.c | 36 ++++
target-tricore/helper.h | 0
target-tricore/machine.c | 21 ++
target-tricore/op_helper.c | 27 +++
target-tricore/translate.c | 108 ++++++++++
target-tricore/translate_init.c | 21 ++
target-tricore/tricore-defs.h | 28 +++
user-exec.c | 17 ++
19 files changed, 869 insertions(+), 1 deletion(-)
create mode 100644 default-configs/tricore-softmmu.mak
create mode 100644 target-tricore/Makefile.objs
create mode 100644 target-tricore/cpu-qom.h
create mode 100644 target-tricore/cpu.c
create mode 100644 target-tricore/cpu.h
create mode 100644 target-tricore/helper.c
create mode 100644 target-tricore/helper.h
create mode 100644 target-tricore/machine.c
create mode 100644 target-tricore/op_helper.c
create mode 100644 target-tricore/translate.c
create mode 100644 target-tricore/translate_init.c
create mode 100644 target-tricore/tricore-defs.h
diff --git a/arch_init.c b/arch_init.c
index 8ddaf35..29a5821 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -104,6 +104,8 @@ int graphic_depth = 32;
#define QEMU_ARCH QEMU_ARCH_XTENSA
#elif defined(TARGET_UNICORE32)
#define QEMU_ARCH QEMU_ARCH_UNICORE32
+#elif defined(TARGET_TRICORE)
+#define QEMU_ARCH QEMU_ARCH_TRICORE
#endif
const uint32_t arch_type = QEMU_ARCH;
diff --git a/configure b/configure
index 7dd43fd..a976862 100755
--- a/configure
+++ b/configure
@@ -495,6 +495,8 @@ elif check_define __mips__ ; then
cpu="mips"
elif check_define __ia64__ ; then
cpu="ia64"
+elif check_define __tricore__ ; then
+ cpu="tricore"
elif check_define __s390__ ; then
if check_define __s390x__ ; then
cpu="s390x"
@@ -533,6 +535,9 @@ case "$cpu" in
mips*)
cpu="mips"
;;
+ tricore*)
+ cpu="tricore"
+ ;;
sparc|sun4[cdmuv])
cpu="sparc"
;;
@@ -4958,6 +4963,10 @@ case "$target_name" in
TARGET_BASE_ARCH=mips
echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak
;;
+ tricore)
+ TARGET_ARCH=tricore
+ target_phys_bits=32
+ ;;
moxie)
;;
or32)
@@ -5155,6 +5164,10 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
echo "CONFIG_MIPS_DIS=y" >> $config_target_mak
echo "CONFIG_MIPS_DIS=y" >> config-all-disas.mak
;;
+ tricore*)
+ echo "CONFIG_TRICORE_DIS=y" >> $config_target_mak
+ echo "CONFIG_TRICORE_DIS=y" >> config-all-disas.mak
+ ;;
moxie*)
echo "CONFIG_MOXIE_DIS=y" >> $config_target_mak
echo "CONFIG_MOXIE_DIS=y" >> config-all-disas.mak
diff --git a/cpu-exec.c b/cpu-exec.c
index 38e5f02..bcfa943 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -277,6 +277,7 @@ int cpu_exec(CPUArchState *env)
#elif defined(TARGET_CRIS)
#elif defined(TARGET_S390X)
#elif defined(TARGET_XTENSA)
+#elif defined(TARGET_TRICORE)
/* XXXXX */
#else
#error unsupported target CPU
@@ -327,7 +328,8 @@ int cpu_exec(CPUArchState *env)
}
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
- defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
+ defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || \
+ defined(TARGET_UNICORE32) || defined(TARGET_TRICORE)
if (interrupt_request & CPU_INTERRUPT_HALT) {
cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
cpu->halted = 1;
@@ -443,6 +445,12 @@ int cpu_exec(CPUArchState *env)
cc->do_interrupt(cpu);
next_tb = 0;
}
+#elif defined(TARGET_TRICORE)
+ if ((interrupt_request & CPU_INTERRUPT_HARD)) {
+ cc->do_interrupt(cpu);
+ next_tb = 0;
+ }
+
#elif defined(TARGET_OPENRISC)
{
int idx = -1;
@@ -724,6 +732,7 @@ int cpu_exec(CPUArchState *env)
| env->cc_dest | (env->cc_x << 4);
#elif defined(TARGET_MICROBLAZE)
#elif defined(TARGET_MIPS)
+#elif defined(TARGET_TRICORE)
#elif defined(TARGET_MOXIE)
#elif defined(TARGET_OPENRISC)
#elif defined(TARGET_SH4)
diff --git a/cpus.c b/cpus.c
index 5e7f2cf..fb0be13 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1342,6 +1342,9 @@ CpuInfoList *qmp_query_cpus(Error **errp)
#elif defined(TARGET_MIPS)
MIPSCPU *mips_cpu = MIPS_CPU(cpu);
CPUMIPSState *env = &mips_cpu->env;
+#elif defined(TARGET_TRICORE)
+ TRICORECPU *tricore_cpu = TRICORE_CPU(cpu);
+ CPUTRICOREState *env = &tricore_cpu->env;
#endif
cpu_synchronize_state(cpu);
@@ -1366,6 +1369,9 @@ CpuInfoList *qmp_query_cpus(Error **errp)
#elif defined(TARGET_MIPS)
info->value->has_PC = true;
info->value->PC = env->active_tc.PC;
+#elif defined(TARGET_TRICORE)
+ info->value->has_PC = true;
+ info->value->PC = env->active_tc.PC;
#endif
/* XXX: waiting for the qapi to support GSList */
diff --git a/default-configs/tricore-softmmu.mak b/default-configs/tricore-softmmu.mak
new file mode 100644
index 0000000..48ccd12
--- /dev/null
+++ b/default-configs/tricore-softmmu.mak
@@ -0,0 +1,3 @@
+include pci.mak
+CONFIG_PFLASH_CFI01=y
+CONFIG_SMC91C111=y
diff --git a/include/elf.h b/include/elf.h
index e88d52f..70107f0 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -92,6 +92,8 @@ typedef int64_t Elf64_Sxword;
#define EM_SPARCV9 43 /* SPARC v9 64-bit */
+#define EM_TRICORE 44 /* Infineon TriCore */
+
#define EM_IA_64 50 /* HP/Intel IA-64 */
#define EM_X86_64 62 /* AMD x86-64 */
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
index 182d48d..3fc56ef 100644
--- a/include/sysemu/arch_init.h
+++ b/include/sysemu/arch_init.h
@@ -22,6 +22,7 @@ enum {
QEMU_ARCH_OPENRISC = 8192,
QEMU_ARCH_UNICORE32 = 0x4000,
QEMU_ARCH_MOXIE = 0x8000,
+ QEMU_ARCH_TRICORE = 0x16000,
};
extern const uint32_t arch_type;
diff --git a/target-tricore/Makefile.objs b/target-tricore/Makefile.objs
new file mode 100644
index 0000000..b5c7458
--- /dev/null
+++ b/target-tricore/Makefile.objs
@@ -0,0 +1,2 @@
+obj-y += translate.o helper.o cpu.o op_helper.o
+obj-$(CONFIG_SOFTMMU) += machine.o
diff --git a/target-tricore/cpu-qom.h b/target-tricore/cpu-qom.h
new file mode 100644
index 0000000..1d57594
--- /dev/null
+++ b/target-tricore/cpu-qom.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2012-2013 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_TRICORE_CPU_QOM_H
+#define QEMU_TRICORE_CPU_QOM_H
+
+#include "qom/cpu.h"
+
+
+#define TYPE_TRICORE_CPU "tricore-cpu"
+
+#define TRICORE_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(TRICORECPUClass, (klass), TYPE_TRICORE_CPU)
+#define TRICORE_CPU(obj) \
+ OBJECT_CHECK(TRICORECPU, (obj), TYPE_TRICORE_CPU)
+#define TRICORE_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(TRICORECPUClass, (obj), TYPE_TRICORE_CPU)
+
+typedef struct TRICORECPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ DeviceRealize parent_realize;
+ void (*parent_reset)(CPUState *cpu);
+} TRICORECPUClass;
+
+/**
+ * TRICORECPU:
+ * @env: #CPUTRICOREState
+ *
+ * A TRICORE CPU.
+ */
+typedef struct TRICORECPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUTRICOREState env;
+} TRICORECPU;
+
+static inline TRICORECPU *tricore_env_get_cpu(CPUTRICOREState *env)
+{
+ return TRICORE_CPU(container_of(env, TRICORECPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(tricore_env_get_cpu(e))
+
+#define ENV_OFFSET offsetof(TRICORECPU, env)
+
+hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+void tricore_cpu_do_interrupt(CPUState *cpu);
+void tricore_cpu_dump_state(CPUState *cpu, FILE *f,
+ fprintf_function cpu_fprintf, int flags);
+
+
+#endif /*QEMU_TRICORE_CPU_QOM_H */
diff --git a/target-tricore/cpu.c b/target-tricore/cpu.c
new file mode 100644
index 0000000..2d0bb76
--- /dev/null
+++ b/target-tricore/cpu.c
@@ -0,0 +1,121 @@
+/*
+ * TRICORE emulation for qemu: main translation routines.
+ *
+ * Copyright (c) 2012-2013 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+#include "qemu-common.h"
+
+
+static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ TRICORECPU *cpu = TRICORE_CPU(cs);
+ CPUTRICOREState *env = &cpu->env;
+
+ env->active_tc.PC = value & ~(target_ulong)1;
+}
+
+static void tricore_cpu_synchronize_from_tb(CPUState *cs,
+ TranslationBlock *tb)
+{
+ TRICORECPU *cpu = TRICORE_CPU(cs);
+ CPUTRICOREState *env = &cpu->env;
+
+ env->active_tc.PC = tb->pc;
+}
+
+static void tricore_cpu_reset(CPUState *s)
+{
+ TRICORECPU *cpu = TRICORE_CPU(s);
+ TRICORECPUClass *tcc = TRICORE_CPU_GET_CLASS(cpu);
+ CPUTRICOREState *env = &cpu->env;
+
+ tcc->parent_reset(s);
+
+ tlb_flush(s, 1);
+
+ cpu_state_reset(env);
+}
+
+static bool tricore_cpu_has_work(CPUState *cs)
+{
+ return true;
+}
+
+static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+ CPUState *cs = CPU(dev);
+ TRICORECPUClass *tcc = TRICORE_CPU_GET_CLASS(dev);
+
+ cpu_reset(cs);
+ qemu_init_vcpu(cs);
+
+ tcc->parent_realize(dev, errp);
+}
+
+
+static void tricore_cpu_initfn(Object *obj)
+{
+ CPUState *cs = CPU(obj);
+ TRICORECPU *cpu = TRICORE_CPU(obj);
+ CPUTRICOREState *env = &cpu->env;
+
+ cs->env_ptr = env;
+ cpu_exec_init(env);
+
+ if (tcg_enabled()) {
+ tricore_tcg_init();
+ }
+}
+
+static void tricore_cpu_class_init(ObjectClass *c, void *data)
+{
+ TRICORECPUClass *mcc = TRICORE_CPU_CLASS(c);
+ CPUClass *cc = CPU_CLASS(c);
+ DeviceClass *dc = DEVICE_CLASS(c);
+
+ mcc->parent_realize = dc->realize;
+ dc->realize = tricore_cpu_realizefn;
+
+ mcc->parent_reset = cc->reset;
+ cc->reset = tricore_cpu_reset;
+ cc->has_work = tricore_cpu_has_work;
+
+ cc->do_interrupt = tricore_cpu_do_interrupt;
+ cc->dump_state = tricore_cpu_dump_state;
+ cc->set_pc = tricore_cpu_set_pc;
+ cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
+
+}
+
+
+static const TypeInfo tricore_cpu_type_info = {
+ .name = TYPE_TRICORE_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(TRICORECPU),
+ .instance_init = tricore_cpu_initfn,
+ .abstract = false,
+ .class_size = sizeof(TRICORECPUClass),
+ .class_init = tricore_cpu_class_init,
+};
+
+static void tricore_cpu_register_types(void)
+{
+ type_register_static(&tricore_cpu_type_info);
+}
+
+type_init(tricore_cpu_register_types)
diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h
new file mode 100644
index 0000000..8cbcda3
--- /dev/null
+++ b/target-tricore/cpu.h
@@ -0,0 +1,380 @@
+/*
+ * TRICORE emulation for qemu: main CPU struct.
+ *
+ * Copyright (c) 2012-2013 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#if !defined(__TRICORE_CPU_H__)
+#define __TRICORE_CPU_H__
+
+#include "tricore-defs.h"
+#include "config.h"
+#include "qemu-common.h"
+#include "exec/cpu-defs.h"
+#include "fpu/softfloat.h"
+
+#define ELF_MACHINE EM_TRICORE
+
+#define CPUArchState struct CPUTRICOREState
+
+struct CPUTRICOREState;
+
+#define TRICORE_CPU_IRQ 0
+#define TRICORE_CPU_FIQ 1
+struct tricore_boot_info;
+
+#define NB_MMU_MODES 3
+
+typedef struct TCState TCState;
+struct TCState {
+ /* CSFR Register */
+#define MASK_PCXI_PCPN 0xff000000
+#define MASK_PCXI_PIE 0x00800000
+#define MASK_PCXI_UL 0x00400000
+#define MASK_PCXI_PCXS 0x000f0000
+#define MASK_PCXI_PCXO 0x0000ffff
+ target_ulong PCXI;
+#define MASK_PSW_USB 0xff000000
+#define MASK_USB_C 0x80000000
+#define MASK_USB_V 0x40000000
+#define MASK_USB_SV 0x20000000
+#define MASK_USB_AV 0x10000000
+#define MASK_USB_SAV 0x08000000
+#define MASK_PSW_PRS 0x00003000
+#define MASK_PSW_IO 0x00000c00
+#define MASK_PSW_IS 0x00000200
+#define MASK_PSW_GW 0x00000100
+#define MASK_PSW_CDE 0x00000080
+#define MASK_PSW_CDC 0x0000007f
+ target_ulong PSW;
+ target_ulong PC;
+#define MASK_SYSCON_PRO_TEN 0x2
+#define MASK_SYSCON_FCD_SF 0x1
+ target_ulong SYSCON;
+#define MASK_CPUID_MOD 0xffff0000
+#define MASK_CPUID_MOD_32B 0x0000ff00
+#define MASK_CPUID_REV 0x000000ff
+ target_ulong CPU_ID;
+ target_ulong BIV;
+ target_ulong BTV;
+ target_ulong ISP;
+#define MASK_ICR_PIPN 0x00ff0000
+#define MASK_ICR_IE 0x00000100
+#define MASK_ICR_CCPN 0x000000ff
+ target_ulong ICR;
+#define MASK_FCX_FCXS 0x000f0000
+#define MASK_FCX_FCXO 0x0000ffff
+ target_ulong FCX;
+#define MASK_LCX_LCXS 0x000f0000
+#define MASK_LCX_LCX0 0x0000ffff
+ target_ulong LCX;
+ target_ulong COMPAT;
+
+ /* Mem Protection Register */
+ target_ulong DPR0_0L;
+ target_ulong DPR0_0U;
+ target_ulong DPR0_1L;
+ target_ulong DPR0_1U;
+ target_ulong DPR0_2L;
+ target_ulong DPR0_2U;
+ target_ulong DPR0_3L;
+ target_ulong DPR0_3U;
+
+ target_ulong DPR1_0L;
+ target_ulong DPR1_0U;
+ target_ulong DPR1_1L;
+ target_ulong DPR1_1U;
+ target_ulong DPR1_2L;
+ target_ulong DPR1_2U;
+ target_ulong DPR1_3L;
+ target_ulong DPR1_3U;
+
+ target_ulong DPR2_0L;
+ target_ulong DPR2_0U;
+ target_ulong DPR2_1L;
+ target_ulong DPR2_1U;
+ target_ulong DPR2_2L;
+ target_ulong DPR2_2U;
+ target_ulong DPR2_3L;
+ target_ulong DPR2_3U;
+
+ target_ulong DPR3_0L;
+ target_ulong DPR3_0U;
+ target_ulong DPR3_1L;
+ target_ulong DPR3_1U;
+ target_ulong DPR3_2L;
+ target_ulong DPR3_2U;
+ target_ulong DPR3_3L;
+ target_ulong DPR3_3U;
+
+ target_ulong CPR0_0L;
+ target_ulong CPR0_0U;
+ target_ulong CPR0_1L;
+ target_ulong CPR0_1U;
+ target_ulong CPR0_2L;
+ target_ulong CPR0_2U;
+ target_ulong CPR0_3L;
+ target_ulong CPR0_3U;
+
+ target_ulong CPR1_0L;
+ target_ulong CPR1_0U;
+ target_ulong CPR1_1L;
+ target_ulong CPR1_1U;
+ target_ulong CPR1_2L;
+ target_ulong CPR1_2U;
+ target_ulong CPR1_3L;
+ target_ulong CPR1_3U;
+
+ target_ulong CPR2_0L;
+ target_ulong CPR2_0U;
+ target_ulong CPR2_1L;
+ target_ulong CPR2_1U;
+ target_ulong CPR2_2L;
+ target_ulong CPR2_2U;
+ target_ulong CPR2_3L;
+ target_ulong CPR2_3U;
+
+ target_ulong CPR3_0L;
+ target_ulong CPR3_0U;
+ target_ulong CPR3_1L;
+ target_ulong CPR3_1U;
+ target_ulong CPR3_2L;
+ target_ulong CPR3_2U;
+ target_ulong CPR3_3L;
+ target_ulong CPR3_3U;
+
+ target_ulong DPM0;
+ target_ulong DPM1;
+ target_ulong DPM2;
+ target_ulong DPM3;
+
+ target_ulong CPM0;
+ target_ulong CPM1;
+ target_ulong CPM2;
+ target_ulong CPM3;
+
+ /* Memory Management Registers */
+ target_ulong MMU_CON;
+ target_ulong MMU_ASI;
+ target_ulong MMU_TVA;
+ target_ulong MMU_TPA;
+ target_ulong MMU_TPX;
+ target_ulong MMU_TFA;
+ /* {1.3.1 only */
+ target_ulong BMACON;
+ target_ulong SMACON;
+ target_ulong DIEAR;
+ target_ulong DIETR;
+ target_ulong CCDIER;
+ target_ulong MIECON;
+ target_ulong PIEAR;
+ target_ulong PIETR;
+ target_ulong CCPIER;
+ /*} */
+ /* Debug Registers */
+ target_ulong DBGSR;
+ target_ulong EXEVT;
+ target_ulong CREVT;
+ target_ulong SWEVT;
+ target_ulong TR0EVT;
+ target_ulong TR1EVT;
+ target_ulong DMS;
+ target_ulong DCX;
+ target_ulong DBGTCR;
+ target_ulong CCTRL;
+ target_ulong CCNT;
+ target_ulong ICNT;
+ target_ulong M1CNT;
+ target_ulong M2CNT;
+ target_ulong M3CNT;
+ /* Floating Point Registers */
+ /* XXX: */
+
+ /* GPR Register */
+ target_ulong gpr_a[16];
+ target_ulong gpr_d[16];
+};
+
+typedef struct tricore_def_t tricore_def_t;
+
+typedef struct CPUTRICOREState CPUTRICOREState;
+struct CPUTRICOREState {
+ TCState active_tc;
+
+ /* QEMU */
+ int error_code;
+ uint32_t hflags; /* CPU State */
+
+ #define TRICORE_PSW_IO 0x600
+
+ #define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */
+ #define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */
+ #define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */
+
+ CPU_COMMON
+
+ const tricore_def_t *cpu_model;
+ void *irq[8];
+ struct QEMUTimer *timer; /* Internal timer */
+};
+
+/* TriCore Traps Classes*/
+enum {
+ TRAPC_NONE = -1,
+ TRAPC_MMU = 0,
+ TRAPC_PROT = 1,
+ TRAPC_INSN_ERR = 2,
+ TRAPC_CTX_MNG = 3,
+ TRAPC_SYSBUS = 4,
+ TRAPC_ASSERT = 5,
+ TRAPC_SYSCALL = 6,
+ TRAPC_NMI = 7,
+};
+
+/* Class 0 TIN */
+enum {
+ TIN0_VAF = 0,
+ TIN0_VAP = 1,
+};
+
+/* Class 1 TIN */
+enum {
+ TIN1_PRIV = 1,
+ TIN1_MPR = 2,
+ TIN1_MPW = 3,
+ TIN1_MPX = 4,
+ TIN1_MPP = 5,
+ TIN1_MPN = 6,
+ TIN1_GRWP = 7,
+};
+
+/* Class 2 TIN */
+enum {
+ TIN2_IOPC = 1,
+ TIN2_UOPC = 2,
+ TIN2_OPD = 3,
+ TIN2_ALN = 4,
+ TIN2_MEM = 5,
+};
+
+/* Class 3 TIN */
+enum {
+ TIN3_FCD = 1,
+ TIN3_CDO = 2,
+ TIN3_CDU = 3,
+ TIN3_FCU = 4,
+ TIN3_CSU = 5,
+ TIN3_CTYP = 6,
+ TIN3_NEST = 7,
+};
+
+/* Class 4 TIN */
+enum {
+ TIN4_PSE = 1,
+ TIN4_DSE = 2,
+ TIN4_DAE = 3,
+ TIN4_CAE = 4,
+ TIN4_PIE = 5,
+ TIN4_DIE = 6,
+};
+
+/* Class 5 TIN */
+enum {
+ TIN5_OVF = 1,
+ TIN5_SOVF = 1,
+};
+
+/* Class 6 TIN
+ *
+ * Is always TIN6_SYS
+ */
+
+/* Class 7 TIN */
+enum {
+ TIN7_NMI = 0,
+};
+
+#include "cpu-qom.h"
+
+#define MMU_USER_IDX 2
+
+void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf);
+
+#define cpu_exec cpu_tricore_exec
+#define cpu_signal_handler cpu_tricore_signal_handler
+#define cpu_list tricore_cpu_list
+
+static inline int cpu_mmu_index(CPUTRICOREState *env)
+{
+ return 0;
+}
+
+
+
+#include "exec/cpu-all.h"
+
+enum {
+ /* 1 bit to define user level / supervisor access */
+ ACCESS_USER = 0x00,
+ ACCESS_SUPER = 0x01,
+ /* 1 bit to indicate direction */
+ ACCESS_STORE = 0x02,
+ /* Type of instruction that generated the access */
+ ACCESS_CODE = 0x10, /* Code fetch access */
+ ACCESS_INT = 0x20, /* Integer load/store access */
+ ACCESS_FLOAT = 0x30, /* floating point load/store access */
+};
+
+void cpu_state_reset(CPUTRICOREState *s);
+int cpu_tricore_exec(CPUTRICOREState *s);
+void tricore_tcg_init(void);
+int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc);
+
+static inline void cpu_get_tb_cpu_state(CPUTRICOREState *env, target_ulong *pc,
+ target_ulong *cs_base, int *flags)
+{
+ *pc = env->active_tc.PC;
+ *cs_base = 0;
+ *flags = 0;
+}
+
+TRICORECPU *cpu_tricore_init(const char *cpu_model);
+
+static inline CPUTRICOREState *cpu_init(const char *cpu_model)
+{
+ TRICORECPU *cpu = cpu_tricore_init(cpu_model);
+ if (cpu == NULL) {
+ return NULL;
+ }
+ return &cpu->env;
+
+}
+
+
+/* helpers.c */
+int cpu_tricore_handle_mmu_fault(CPUState *cpu, target_ulong address,
+ int rw, int mmu_idx);
+#define cpu_handle_mmu_fault cpu_tricore_handle_mmu_fault
+
+#include "exec/exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUTRICOREState *env, TranslationBlock *tb)
+{
+ env->active_tc.PC = tb->pc;
+}
+
+void do_interrupt(CPUTRICOREState *env);
+
+#endif /*__TRICORE_CPU_H__ */
diff --git a/target-tricore/helper.c b/target-tricore/helper.c
new file mode 100644
index 0000000..f8d586a
--- /dev/null
+++ b/target-tricore/helper.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2012-2013 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdarg.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+#include <signal.h>
+
+#include "cpu.h"
+
+int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address,
+ int rw, int mmu_idx)
+{
+ return 0;
+}
+
+void tricore_cpu_do_interrupt(CPUState *cs)
+{
+}
+
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
new file mode 100644
index 0000000..e69de29
diff --git a/target-tricore/machine.c b/target-tricore/machine.c
new file mode 100644
index 0000000..48e706a
--- /dev/null
+++ b/target-tricore/machine.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw/hw.h"
+#include "hw/boards.h"
+
+#include "cpu.h"
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
new file mode 100644
index 0000000..275790b
--- /dev/null
+++ b/target-tricore/op_helper.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include <stdlib.h>
+#include "cpu.h"
+#include "qemu/host-utils.h"
+#include "exec/helper-proto.h"
+#include "exec/cpu_ldst.h"
+
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
+ uintptr_t retaddr)
+{
+}
+
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
new file mode 100644
index 0000000..f92f654
--- /dev/null
+++ b/target-tricore/translate.c
@@ -0,0 +1,108 @@
+/*
+ * TRICORE emulation for qemu: main translation routines.
+ *
+ * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#include "cpu.h"
+#include "disas/disas.h"
+#include "tcg-op.h"
+#include "exec/cpu_ldst.h"
+
+#include "exec/helper-proto.h"
+#include "exec/helper-gen.h"
+
+
+static const char *regnames_a[] = {
+ "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
+ "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
+ "a12" , "a13" , "a14" , "a15",
+ };
+
+static const char *regnames_d[] = {
+ "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
+ "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
+ "d12" , "d13" , "d14" , "d15",
+ };
+
+void tricore_cpu_dump_state(CPUState *cs, FILE *f,
+ fprintf_function cpu_fprintf, int flags)
+{
+ TRICORECPU *cpu = TRICORE_CPU(cs);
+ CPUTRICOREState *env = &cpu->env;
+ int i;
+
+ cpu_fprintf(f, "PC=%08x\n", env->active_tc.PC);
+ for (i = 0; i < 16; ++i) {
+ if ((i & 3) == 0) {
+ cpu_fprintf(f, "GPR A%02d:", i);
+ }
+ cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_a[i],
+ env->active_tc.gpr_a[i]);
+ }
+ for (i = 0; i < 16; ++i) {
+ if ((i & 3) == 0) {
+ cpu_fprintf(f, "GPR D%02d:", i);
+ }
+ cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_d[i],
+ env->active_tc.gpr_d[i]);
+ }
+
+}
+
+static inline void
+gen_intermediate_code_internal(TRICORECPU *cpu, struct TranslationBlock *tb,
+ int search_pc)
+{
+}
+
+void
+gen_intermediate_code(CPUTRICOREState *env, struct TranslationBlock *tb)
+{
+ gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false);
+}
+
+void
+gen_intermediate_code_pc(CPUTRICOREState *env, struct TranslationBlock *tb)
+{
+ gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true);
+}
+
+void
+restore_state_to_opc(CPUTRICOREState *env, TranslationBlock *tb, int pc_pos)
+{
+ env->active_tc.PC = tcg_ctx.gen_opc_pc[pc_pos];
+}
+/*
+ *
+ * Initialization
+ *
+ */
+#include "translate_init.c"
+
+void cpu_state_reset(CPUTRICOREState *env)
+{
+}
+
+void tricore_tcg_init(void)
+{
+}
+
+TRICORECPU *cpu_tricore_init(const char *cpu_model)
+{
+ return NULL;
+}
diff --git a/target-tricore/translate_init.c b/target-tricore/translate_init.c
new file mode 100644
index 0000000..d37d2ba
--- /dev/null
+++ b/target-tricore/translate_init.c
@@ -0,0 +1,21 @@
+/*
+ *
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+}
diff --git a/target-tricore/tricore-defs.h b/target-tricore/tricore-defs.h
new file mode 100644
index 0000000..4350b03
--- /dev/null
+++ b/target-tricore/tricore-defs.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if !defined(__QEMU_TRICORE_DEFS_H__)
+#define __QEMU_TRICORE_DEFS_H__
+
+#define TARGET_PAGE_BITS 14
+#define TARGET_LONG_BITS 32
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+
+#define TRICORE_TLB_MAX 128
+
+#endif /* __QEMU_TRICORE_DEFS_H__ */
diff --git a/user-exec.c b/user-exec.c
index 1ff8673..beba4d5 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -614,6 +614,23 @@ int cpu_signal_handler(int host_signum, void *pinfo,
is_write, &uc->uc_sigmask, puc);
}
+#elif defined(__tricore__)
+
+int cpu_signal_handler(int host_signum, void *pinfo,
+ void *puc)
+{
+ printf("cpu_signal_handler\n");
+ /* siginfo_t *info = pinfo;
+ struct ucontext *uc = puc;
+ greg_t pc = uc->uc_mcontext.pc;
+ int is_write;
+ is_write = 0;
+ return handle_cpu_signal(pc, (unsigned long)info->si_addr,
+ is_write, &uc->uc_sigmask, puc);*/
+ return 0;
+}
+
+
#elif defined(__hppa__)
int cpu_signal_handler(int host_signum, void *pinfo,
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 01/15] target-tricore: Add target stubs and qom-cpu
2014-07-07 18:13 ` [Qemu-devel] [PATCH 01/15] target-tricore: Add target stubs and qom-cpu Bastian Koppelmann
@ 2014-07-07 19:09 ` Richard Henderson
2014-07-07 19:14 ` Richard Henderson
2014-07-07 19:24 ` Peter Maydell
2 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2014-07-07 19:09 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: peter.maydell
On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> QEMU_ARCH_MOXIE = 0x8000,
> + QEMU_ARCH_TRICORE = 0x16000,
Hexidecimal, not decimal doubling.
This file is a mess, I agree. A separate patch to standardize the existing
numbers to hex would be appreciated.
r~
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Qemu-devel] [PATCH 01/15] target-tricore: Add target stubs and qom-cpu
2014-07-07 18:13 ` [Qemu-devel] [PATCH 01/15] target-tricore: Add target stubs and qom-cpu Bastian Koppelmann
2014-07-07 19:09 ` Richard Henderson
@ 2014-07-07 19:14 ` Richard Henderson
2014-07-07 19:24 ` Peter Maydell
2 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2014-07-07 19:14 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: peter.maydell
On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> +
> + /* GPR Register */
> + target_ulong gpr_a[16];
> + target_ulong gpr_d[16];
> +};
> +
> +typedef struct tricore_def_t tricore_def_t;
> +
> +typedef struct CPUTRICOREState CPUTRICOREState;
> +struct CPUTRICOREState {
> + TCState active_tc;
You'll get better code generation if you put the gprs first. Some hosts will
need a 2 insn sequence for large offsets, and even x86 will have a code size
benefit from having offsets < 128.
Is there any real need for the active_tc thing, or did you just copy MIPS?
Personally, I dislike it, and unless you're planning on using structure
assignment to copy data around during certain context switches, please drop it.
r~
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 01/15] target-tricore: Add target stubs and qom-cpu
2014-07-07 18:13 ` [Qemu-devel] [PATCH 01/15] target-tricore: Add target stubs and qom-cpu Bastian Koppelmann
2014-07-07 19:09 ` Richard Henderson
2014-07-07 19:14 ` Richard Henderson
@ 2014-07-07 19:24 ` Peter Maydell
2014-07-11 11:05 ` Bastian Koppelmann
2 siblings, 1 reply; 33+ messages in thread
From: Peter Maydell @ 2014-07-07 19:24 UTC (permalink / raw)
To: Bastian Koppelmann; +Cc: QEMU Developers, Richard Henderson
On 7 July 2014 19:13, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> wrote:
> Add TriCore target stubs, QOM cpu and basic machine.
>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
> arch_init.c | 2 +
> configure | 13 ++
> cpu-exec.c | 11 +-
> cpus.c | 6 +
> default-configs/tricore-softmmu.mak | 3 +
> include/elf.h | 2 +
> include/sysemu/arch_init.h | 1 +
> target-tricore/Makefile.objs | 2 +
> target-tricore/cpu-qom.h | 71 +++++++
> target-tricore/cpu.c | 121 ++++++++++++
> target-tricore/cpu.h | 380 ++++++++++++++++++++++++++++++++++++
> target-tricore/helper.c | 36 ++++
> target-tricore/helper.h | 0
> target-tricore/machine.c | 21 ++
> target-tricore/op_helper.c | 27 +++
> target-tricore/translate.c | 108 ++++++++++
> target-tricore/translate_init.c | 21 ++
> target-tricore/tricore-defs.h | 28 +++
> user-exec.c | 17 ++
> 19 files changed, 869 insertions(+), 1 deletion(-)
> create mode 100644 default-configs/tricore-softmmu.mak
> create mode 100644 target-tricore/Makefile.objs
> create mode 100644 target-tricore/cpu-qom.h
> create mode 100644 target-tricore/cpu.c
> create mode 100644 target-tricore/cpu.h
> create mode 100644 target-tricore/helper.c
> create mode 100644 target-tricore/helper.h
> create mode 100644 target-tricore/machine.c
> create mode 100644 target-tricore/op_helper.c
> create mode 100644 target-tricore/translate.c
> create mode 100644 target-tricore/translate_init.c
> create mode 100644 target-tricore/tricore-defs.h
I think you probably want the configure and default-configs changes
to be at the end of the patch series (or at least part way through it),
not at the start.
The general approach is:
* some patches which implement the basic absolute minimum
functionality, usefully split up
* then add the configure and default-configs changes that allow
the user to select the target and include it in the default target
list
> diff --git a/configure b/configure
> index 7dd43fd..a976862 100755
> --- a/configure
> +++ b/configure
> @@ -495,6 +495,8 @@ elif check_define __mips__ ; then
> cpu="mips"
> elif check_define __ia64__ ; then
> cpu="ia64"
> +elif check_define __tricore__ ; then
> + cpu="tricore"
> elif check_define __s390__ ; then
> if check_define __s390x__ ; then
> cpu="s390x"
This is for supporting compilation of QEMU on a tricore
*host*. That is a bit pointless since you don't provide a
TCG target backend. In any case if you want to add support
for that I suggest restricting it to its own separate patchset.
> @@ -533,6 +535,9 @@ case "$cpu" in
> mips*)
> cpu="mips"
> ;;
> + tricore*)
> + cpu="tricore"
> + ;;
Also host CPU related. (I suggest looking at where the
configure script handles the "moxie" target type, since that's
an example of a CPU type we handle only as a guest CPU
and not as a host CPU, so it's a good indication of where you
need to add tricore cases.)
> sparc|sun4[cdmuv])
> cpu="sparc"
> ;;
> @@ -4958,6 +4963,10 @@ case "$target_name" in
> TARGET_BASE_ARCH=mips
> echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak
> ;;
> + tricore)
> + TARGET_ARCH=tricore
You don't need this line, because the default value for
TARGET_ARCH is the target name; only those cases in this
case statement where the CPU target name might be different
need to set TARGET_ARCH specifically.
> + target_phys_bits=32
> + ;;
> moxie)
> ;;
> or32)
> @@ -5155,6 +5164,10 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
> echo "CONFIG_MIPS_DIS=y" >> $config_target_mak
> echo "CONFIG_MIPS_DIS=y" >> config-all-disas.mak
> ;;
> + tricore*)
> + echo "CONFIG_TRICORE_DIS=y" >> $config_target_mak
> + echo "CONFIG_TRICORE_DIS=y" >> config-all-disas.mak
> + ;;
Diffstat says you haven't got a disassembler in this patch,
so what is this for? Don't add it until/unless you add the
disassembler code.
> --- /dev/null
> +++ b/target-tricore/machine.c
> @@ -0,0 +1,21 @@
> +/*
> + * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "hw/hw.h"
> +#include "hw/boards.h"
> +
> +#include "cpu.h"
This file has no content; don't add it until it's got some useful code in it...
> diff --git a/user-exec.c b/user-exec.c
> index 1ff8673..beba4d5 100644
> --- a/user-exec.c
> +++ b/user-exec.c
> @@ -614,6 +614,23 @@ int cpu_signal_handler(int host_signum, void *pinfo,
> is_write, &uc->uc_sigmask, puc);
> }
>
> +#elif defined(__tricore__)
> +
> +int cpu_signal_handler(int host_signum, void *pinfo,
> + void *puc)
> +{
> + printf("cpu_signal_handler\n");
> + /* siginfo_t *info = pinfo;
> + struct ucontext *uc = puc;
> + greg_t pc = uc->uc_mcontext.pc;
> + int is_write;
> + is_write = 0;
> + return handle_cpu_signal(pc, (unsigned long)info->si_addr,
> + is_write, &uc->uc_sigmask, puc);*/
> + return 0;
> +}
> +
> +
This is also host-CPU support; don't put it in this patchset.
(Also, don't include commented out code like that...)
thanks
-- PMM
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 01/15] target-tricore: Add target stubs and qom-cpu
2014-07-07 19:24 ` Peter Maydell
@ 2014-07-11 11:05 ` Bastian Koppelmann
2014-07-11 11:10 ` Peter Maydell
0 siblings, 1 reply; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-11 11:05 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, Richard Henderson
Hi Peter,
On 07/07/2014 08:24 PM, Peter Maydell wrote:
> I think you probably want the configure and default-configs changes to
> be at the end of the patch series (or at least part way through it),
> not at the start. The general approach is: * some patches which
> implement the basic absolute minimum functionality, usefully split up
> * then add the configure and default-configs changes that allow the
> user to select the target and include it in the default target list
Would you recommend to add the part, which activates the target, at the
end of this patch series or at the end of the implementation of the target?
thanks,
Bastian
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Qemu-devel] [PATCH 01/15] target-tricore: Add target stubs and qom-cpu
2014-07-11 11:05 ` Bastian Koppelmann
@ 2014-07-11 11:10 ` Peter Maydell
0 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2014-07-11 11:10 UTC (permalink / raw)
To: Bastian Koppelmann; +Cc: QEMU Developers, Richard Henderson
On 11 July 2014 12:05, Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
> On 07/07/2014 08:24 PM, Peter Maydell wrote:
>> I think you probably want the configure and default-configs changes to be
>> at the end of the patch series (or at least part way through it), not at the
>> start. The general approach is: * some patches which implement the basic
>> absolute minimum functionality, usefully split up * then add the configure
>> and default-configs changes that allow the user to select the target and
>> include it in the default target list
>
> Would you recommend to add the part, which activates the target, at the end
> of this patch series or at the end of the implementation of the target?
I would add it at the point where the target can at least build
and attempt to execute a guest binary, even if every instruction
is actually undefined.
thanks
-- PMM
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 02/15] target-tricore: Add board for systemmode
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
2014-07-07 18:13 ` [Qemu-devel] [PATCH 01/15] target-tricore: Add target stubs and qom-cpu Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-07 18:13 ` [Qemu-devel] [PATCH 03/15] target-tricore: Add softmmu support Bastian Koppelmann
` (12 subsequent siblings)
14 siblings, 0 replies; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 130 +++++++++++++++++++++++++++++++++++++++++
include/hw/tricore/tricore.h | 54 +++++++++++++++++
3 files changed, 185 insertions(+)
create mode 100644 hw/tricore/Makefile.objs
create mode 100644 hw/tricore/tricore_testboard.c
create mode 100644 include/hw/tricore/tricore.h
diff --git a/hw/tricore/Makefile.objs b/hw/tricore/Makefile.objs
new file mode 100644
index 0000000..435e095
--- /dev/null
+++ b/hw/tricore/Makefile.objs
@@ -0,0 +1 @@
+obj-y += tricore_testboard.o
diff --git a/hw/tricore/tricore_testboard.c b/hw/tricore/tricore_testboard.c
new file mode 100644
index 0000000..e5574f6
--- /dev/null
+++ b/hw/tricore/tricore_testboard.c
@@ -0,0 +1,130 @@
+/*
+ * TriCore Baseboard System emulation.
+ *
+ * Copyright (c) 2014 Bastian Koppelmann
+ *
+ * This code is licensed under the GPL.
+ */
+
+#include "hw/hw.h"
+#include "hw/devices.h"
+#include "net/net.h"
+#include "sysemu/sysemu.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "sysemu/blockdev.h"
+#include "exec/address-spaces.h"
+#include "hw/block/flash.h"
+#include "elf.h"
+#include "hw/tricore/tricore.h"
+
+#define TRICORE_FLASH_ADDR 0xa0000000
+#define TRICORE_FLASH_SIZE (2 * 1024 * 1024)
+#define TRICORE_FLASH_SECT_SIZE (256 * 1024)
+
+
+/* Board init. */
+
+static struct tricore_boot_info tricoretb_binfo;
+
+static void tricore_load_kernel(CPUTRICOREState *env)
+{
+ int64_t entry;
+ long kernel_size;
+
+ kernel_size = load_elf(tricoretb_binfo.kernel_filename, NULL,
+ NULL, (uint64_t *)&entry, NULL,
+ NULL, 0,
+ ELF_MACHINE, 1);
+ if (kernel_size <= 0) {
+ fprintf(stderr, "qemu: no kernel file '%s'\n",
+ tricoretb_binfo.kernel_filename);
+ exit(1);
+ }
+ env->active_tc.PC = entry;
+
+}
+
+static void tricore_testboard_init(MachineState *machine, int board_id)
+{
+ TRICORECPU *cpu;
+ CPUTRICOREState *env;
+
+ MemoryRegion *sysmem = get_system_memory();
+ MemoryRegion *ext_cram = g_new(MemoryRegion, 1);
+ MemoryRegion *ext_dram = g_new(MemoryRegion, 1);
+ MemoryRegion *int_cram = g_new(MemoryRegion, 1);
+ MemoryRegion *int_dram = g_new(MemoryRegion, 1);
+ MemoryRegion *pcp_data = g_new(MemoryRegion, 1);
+ MemoryRegion *pcp_text = g_new(MemoryRegion, 1);
+ DriveInfo *dinfo;
+
+ if (!machine->cpu_model) {
+ machine->cpu_model = "TC1796";
+ }
+ cpu = cpu_tricore_init(machine->cpu_model);
+ env = &cpu->env;
+ if (!cpu) {
+ fprintf(stderr, "Unable to find CPU definition\n");
+ exit(1);
+ }
+ memory_region_init_ram(ext_cram, NULL, "powerlink_ext_c.ram", 2*1024*1024);
+ vmstate_register_ram_global(ext_cram);
+ memory_region_init_ram(ext_dram, NULL, "powerlink_ext_d.ram", 4*1024*1024);
+ vmstate_register_ram_global(ext_dram);
+ memory_region_init_ram(int_cram, NULL, "powerlink_int_c.ram", 48*1024);
+ vmstate_register_ram_global(int_cram);
+ memory_region_init_ram(int_dram, NULL, "powerlink_int_d.ram", 48*1024);
+ vmstate_register_ram_global(int_dram);
+ memory_region_init_ram(pcp_data, NULL, "powerlink_pcp_data.ram", 16*1024);
+ vmstate_register_ram_global(pcp_data);
+ memory_region_init_ram(pcp_text, NULL, "powerlink_pcp_text.ram", 32*1024);
+ vmstate_register_ram_global(pcp_text);
+
+ memory_region_add_subregion(sysmem, 0x80000000, ext_cram);
+ memory_region_add_subregion(sysmem, 0xa1000000, ext_dram);
+ memory_region_add_subregion(sysmem, 0xd4000000, int_cram);
+ memory_region_add_subregion(sysmem, 0xd0000000, int_dram);
+ memory_region_add_subregion(sysmem, 0xf0050000, pcp_data);
+ memory_region_add_subregion(sysmem, 0xf0060000, pcp_text);
+
+ dinfo = drive_get(IF_PFLASH, 0, 0);
+ if (!pflash_cfi01_register(TRICORE_FLASH_ADDR, NULL,
+ "tricore_testboard.flash",
+ TRICORE_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
+ TRICORE_FLASH_SECT_SIZE,
+ TRICORE_FLASH_SIZE / TRICORE_FLASH_SECT_SIZE,
+ 2, 0x00, 0x00, 0x0000, 0x0, 0)) {
+
+ fprintf(stderr, "qemu: Error registering flash memory.\n");
+ } else {
+ env->active_tc.PC = TRICORE_FLASH_ADDR;
+ }
+
+ tricoretb_binfo.ram_size = machine->ram_size;
+ tricoretb_binfo.kernel_filename = machine->kernel_filename;
+
+ if (machine->kernel_filename) {
+ tricore_load_kernel(env);
+ }
+}
+
+static void tricoreboard_init(MachineState *machine)
+{
+ tricore_testboard_init(machine, 0x183);
+}
+
+static QEMUMachine ttb_machine = {
+ .name = "TriCore testboard",
+ .desc = "Just for testing",
+ .init = tricoreboard_init,
+ .is_default = 1,
+};
+
+static void tricore_testboard_machine_init(void)
+{
+ qemu_register_machine(&ttb_machine);
+}
+
+machine_init(tricore_testboard_machine_init);
+
diff --git a/include/hw/tricore/tricore.h b/include/hw/tricore/tricore.h
new file mode 100644
index 0000000..4e68174
--- /dev/null
+++ b/include/hw/tricore/tricore.h
@@ -0,0 +1,54 @@
+#ifndef TRICORE_MISC_H
+#define TRICORE_MISC_H 1
+
+#include "exec/memory.h"
+#include "hw/irq.h"
+
+struct tricore_boot_info {
+ uint64_t ram_size;
+ const char *kernel_filename;
+ const char *kernel_cmdline;
+ const char *initrd_filename;
+ const char *dtb_filename;
+ hwaddr loader_start;
+ /* multicore boards that use the default secondary core boot functions
+ * need to put the address of the secondary boot code, the boot reg,
+ * and the GIC address in the next 3 values, respectively. boards that
+ * have their own boot functions can use these values as they want.
+ */
+ hwaddr smp_loader_start;
+ hwaddr smp_bootreg_addr;
+ hwaddr gic_cpu_if_addr;
+ int nb_cpus;
+ int board_id;
+ int (*atag_board)(const struct tricore_boot_info *info, void *p);
+ /* multicore boards that use the default secondary core boot functions
+ * can ignore these two function calls. If the default functions won't
+ * work, then write_secondary_boot() should write a suitable blob of
+ * code mimicking the secondary CPU startup process used by the board's
+ * boot loader/boot ROM code, and secondary_cpu_reset_hook() should
+ * perform any necessary CPU reset handling and set the PC for the
+ * secondary CPUs to point at this boot blob.
+ */
+ void (*write_secondary_boot)(TRICORECPU *cpu,
+ const struct tricore_boot_info *info);
+ void (*secondary_cpu_reset_hook)(TRICORECPU *cpu,
+ const struct tricore_boot_info *info);
+ /* if a board is able to create a dtb without a dtb file then it
+ * sets get_dtb. This will only be used if no dtb file is provided
+ * by the user. On success, sets *size to the length of the created
+ * dtb, and returns a pointer to it. (The caller must free this memory
+ * with g_free() when it has finished with it.) On failure, returns NULL.
+ */
+ void *(*get_dtb)(const struct tricore_boot_info *info, int *size);
+ /* if a board needs to be able to modify a device tree provided by
+ * the user it should implement this hook.
+ */
+ void (*modify_dtb)(const struct tricore_boot_info *info, void *fdt);
+ /* Used internally by arm_boot.c */
+ int is_linux;
+ hwaddr initrd_start;
+ hwaddr initrd_size;
+ hwaddr entry;
+};
+#endif
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PATCH 03/15] target-tricore: Add softmmu support
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
2014-07-07 18:13 ` [Qemu-devel] [PATCH 01/15] target-tricore: Add target stubs and qom-cpu Bastian Koppelmann
2014-07-07 18:13 ` [Qemu-devel] [PATCH 02/15] target-tricore: Add board for systemmode Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-07 18:13 ` [Qemu-devel] [PATCH 04/15] target-tricore: Add initialization for translation Bastian Koppelmann
` (11 subsequent siblings)
14 siblings, 0 replies; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/helper.c | 54 +++++++++++++++++++++++++++++++++++++++++++++-
target-tricore/op_helper.c | 33 +++++++++++++++++++++++++++-
2 files changed, 85 insertions(+), 2 deletions(-)
diff --git a/target-tricore/helper.c b/target-tricore/helper.c
index f8d586a..a50677a 100644
--- a/target-tricore/helper.c
+++ b/target-tricore/helper.c
@@ -24,10 +24,62 @@
#include "cpu.h"
+enum {
+ TLBRET_DIRTY = -4,
+ TLBRET_INVALID = -3,
+ TLBRET_NOMATCH = -2,
+ TLBRET_BADADDR = -1,
+ TLBRET_MATCH = 0
+};
+
+#if defined(CONFIG_SOFTMMU)
+static int get_physical_address(CPUTRICOREState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ int rw, int access_type)
+{
+ int ret = TLBRET_MATCH;
+
+ *physical = address & 0xFFFFFFFF;
+ *prot = PAGE_READ | PAGE_WRITE;
+
+ return ret;
+}
+#endif
+
+/* TODO: Add exeption support*/
+static void raise_mmu_exception(CPUTRICOREState *env, target_ulong address,
+ int rw, int tlb_error)
+{
+}
+
int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address,
int rw, int mmu_idx)
{
- return 0;
+ TRICORECPU *cpu = TRICORE_CPU(cs);
+ CPUTRICOREState *env = &cpu->env;
+ hwaddr physical;
+ int prot;
+ int access_type;
+ int ret = 0;
+
+ rw &= 1;
+ access_type = ACCESS_INT;
+ ret = get_physical_address(env, &physical, &prot,
+ address, rw, access_type);
+ qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx
+ " prot %d\n", __func__, address, ret, physical, prot);
+
+ if (ret == TLBRET_MATCH) {
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
+ physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
+ mmu_idx, TARGET_PAGE_SIZE);
+ ret = 0;
+ } else if (ret < 0) {
+ raise_mmu_exception(env, address, rw, ret);
+ ret = 1;
+ }
+
+ return ret;
}
void tricore_cpu_do_interrupt(CPUState *cs)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 275790b..2e5981f 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -20,8 +20,39 @@
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
+static inline void QEMU_NORETURN do_raise_exception_err(CPUTRICOREState *env,
+ uint32_t exception,
+ int error_code,
+ uintptr_t pc)
+{
+ CPUState *cs = CPU(tricore_env_get_cpu(env));
+ cs->exception_index = exception;
+ env->error_code = error_code;
+
+ if (pc) {
+ /* now we have a real cpu fault */
+ cpu_restore_state(cs, pc);
+ }
+
+ cpu_loop_exit(cs);
+}
+
+static inline void QEMU_NORETURN do_raise_exception(CPUTRICOREState *env,
+ uint32_t exception,
+ uintptr_t pc)
+{
+ do_raise_exception_err(env, exception, 0, pc);
+}
+
void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
+ int ret;
+ ret = cpu_tricore_handle_mmu_fault(cs, addr, is_write, mmu_idx);
+ if (ret) {
+ TRICORECPU *cpu = TRICORE_CPU(cs);
+ CPUTRICOREState *env = &cpu->env;
+ do_raise_exception_err(env, cs->exception_index,
+ env->error_code, retaddr);
+ }
}
-
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PATCH 04/15] target-tricore: Add initialization for translation
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (2 preceding siblings ...)
2014-07-07 18:13 ` [Qemu-devel] [PATCH 03/15] target-tricore: Add softmmu support Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-07 18:13 ` [Qemu-devel] [PATCH 05/15] target-tricore: Add masks and opcodes for decoding Bastian Koppelmann
` (10 subsequent siblings)
14 siblings, 0 replies; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/translate.c | 160 +++++++++++++++++++++++++++++++++++++++-
target-tricore/translate_init.c | 30 ++++++++
2 files changed, 189 insertions(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index f92f654..2b23afa 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -26,6 +26,18 @@
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
+/*
+ * TCG registers
+ */
+static TCGv cpu_PC;
+static TCGv cpu_PCXI;
+static TCGv cpu_PSW;
+static TCGv cpu_ICR;
+/* GPR registers */
+static TCGv cpu_gpr_a[16];
+static TCGv cpu_gpr_d[16];
+static TCGv_ptr cpu_env;
+#include "exec/gen-icount.h"
static const char *regnames_a[] = {
"a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
@@ -39,6 +51,25 @@ static const char *regnames_d[] = {
"d12" , "d13" , "d14" , "d15",
};
+typedef struct DisasContext {
+ struct TranslationBlock *tb;
+ target_ulong pc, saved_pc;
+ uint32_t opcode;
+ int singlestep_enabled;
+ /* Routine used to access memory */
+ int mem_idx;
+ uint32_t hflags, saved_hflags;
+ int bstate;
+} DisasContext;
+
+enum {
+
+ BS_NONE = 0,
+ BS_STOP = 1,
+ BS_BRANCH = 2,
+ BS_EXCP = 3,
+};
+
void tricore_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf, int flags)
{
@@ -64,10 +95,92 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f,
}
+static int insn_bytes;
+
+static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
+{
+}
+
+static void decode_32Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
+{
+}
+
+static void decode_opc(CPUTRICOREState *env, DisasContext *ctx, int *is_branch)
+{
+ /* 16-Bit Instruction */
+ if ((ctx->opcode & 0x1) == 0) {
+ insn_bytes = 2;
+ decode_16Bit_opc(env, ctx);
+ /* 32-Bit Instruction */
+ } else {
+ insn_bytes = 4;
+ decode_32Bit_opc(env, ctx);
+ }
+}
+
static inline void
gen_intermediate_code_internal(TRICORECPU *cpu, struct TranslationBlock *tb,
int search_pc)
{
+ CPUState *cs = CPU(cpu);
+ CPUTRICOREState *env = &cpu->env;
+ DisasContext ctx;
+ target_ulong pc_start;
+ int num_insns;
+ uint16_t *gen_opc_end;
+
+ if (search_pc) {
+ qemu_log("search pc %d\n", search_pc);
+ }
+
+ num_insns = 0;
+ insn_bytes = 4;
+
+ pc_start = tb->pc;
+ gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
+ ctx.pc = pc_start;
+ ctx.saved_pc = -1;
+ ctx.tb = tb;
+ ctx.singlestep_enabled = cs->singlestep_enabled;
+ ctx.bstate = BS_NONE;
+ ctx.mem_idx = cpu_mmu_index(env);
+
+ tcg_clear_temp_count();
+ gen_tb_start();
+ while (ctx.bstate == BS_NONE) {
+ ctx.opcode = cpu_ldl_code(env, ctx.pc);
+ decode_opc(env, &ctx, 0);
+
+ num_insns++;
+
+ ctx.pc += insn_bytes;
+ if (tcg_ctx.gen_opc_ptr >= gen_opc_end) {
+ break;
+ }
+ if (singlestep) {
+ break;
+ }
+ }
+
+ gen_tb_end(tb, num_insns);
+ *tcg_ctx.gen_opc_ptr = INDEX_op_end;
+ if (search_pc) {
+ printf("done_generating search pc\n");
+ } else {
+ tb->size = ctx.pc - pc_start;
+ tb->icount = num_insns;
+ }
+ if (tcg_check_temp_count()) {
+ printf("LEAK at %08x\n", env->active_tc.PC);
+ }
+
+#ifdef DEBUG_DISAS
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
+ qemu_log("IN: %s\n", lookup_symbol(pc_start));
+ log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
+ qemu_log("\n");
+ }
+#endif
}
void
@@ -96,13 +209,58 @@ restore_state_to_opc(CPUTRICOREState *env, TranslationBlock *tb, int pc_pos)
void cpu_state_reset(CPUTRICOREState *env)
{
+ /* Reset Regs to Default Value */
+ env->active_tc.PSW = 0xb80;
+}
+
+static void tricore_tcg_init_csfr(void)
+{
+ cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, active_tc.PCXI), "PCXI");
+ cpu_PSW = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, active_tc.PSW), "PSW");
+ cpu_PC = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, active_tc.PC), "PC");
+ cpu_ICR = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, active_tc.ICR), "ICR");
}
void tricore_tcg_init(void)
{
+ int i;
+ static int inited;
+ if (inited) {
+ return;
+ }
+ cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ /* reg init */
+ for (i = 0 ; i < 16 ; i++) {
+ cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, active_tc.gpr_a[i]),
+ regnames_a[i]);
+ }
+ for (i = 0 ; i < 16 ; i++) {
+ cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, active_tc.gpr_d[i]),
+ regnames_d[i]);
+ }
+ tricore_tcg_init_csfr();
}
TRICORECPU *cpu_tricore_init(const char *cpu_model)
{
- return NULL;
+ TRICORECPU *cpu;
+ CPUTRICOREState *env;
+ const tricore_def_t *def;
+
+ def = cpu_tricore_find_by_name(cpu_model);
+ if (!def) {
+ return NULL;
+ }
+ cpu = TRICORE_CPU(object_new(TYPE_TRICORE_CPU));
+ env = &cpu->env;
+ env->cpu_model = def;
+
+ object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+ return cpu;
}
diff --git a/target-tricore/translate_init.c b/target-tricore/translate_init.c
index d37d2ba..9eee7dd 100644
--- a/target-tricore/translate_init.c
+++ b/target-tricore/translate_init.c
@@ -16,6 +16,36 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+struct tricore_def_t {
+ const char *name;
+};
+
+
+static const tricore_def_t tricore_defs[] = {
+ {
+ .name = "TC1796",
+ },
+
+};
+
+static const tricore_def_t *cpu_tricore_find_by_name(const char *name)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tricore_defs); i++) {
+ if (strcasecmp(name, tricore_defs[i].name) == 0) {
+ return &tricore_defs[i];
+ }
+ }
+ return NULL;
+}
+
void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tricore_defs); i++) {
+ (*cpu_fprintf)(f, "TRICORE '%s'\n",
+ tricore_defs[i].name);
+ }
}
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PATCH 05/15] target-tricore: Add masks and opcodes for decoding
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (3 preceding siblings ...)
2014-07-07 18:13 ` [Qemu-devel] [PATCH 04/15] target-tricore: Add initialization for translation Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-07 19:37 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 06/15] target-tricore: Add instructions of SRC opcode format Bastian Koppelmann
` (9 subsequent siblings)
14 siblings, 1 reply; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add masks and opcodes for decoding TriCore instructions
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/translate.c | 1 +
target-tricore/tricore-opcodes.h | 1405 ++++++++++++++++++++++++++++++++++++++
2 files changed, 1406 insertions(+)
create mode 100644 target-tricore/tricore-opcodes.h
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 2b23afa..e0de874 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -26,6 +26,7 @@
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
+#include "tricore-opcodes.h"
/*
* TCG registers
*/
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
new file mode 100644
index 0000000..22948ec
--- /dev/null
+++ b/target-tricore/tricore-opcodes.h
@@ -0,0 +1,1405 @@
+/*
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Opcode Masks for Tricore
+ * Format MASK_OP_InstrFormatName_Field
+ */
+
+/* This creates a mask with bits start .. end set to 1 and applies it to op */
+#define MASK_BITS(op, start, end) (op & (((1 << (end-start+1)) - 1) << start))
+#define MASK_BITS_SHIFT(op, start, end) (MASK_BITS(op, start, end) >> start)
+
+/* new opcode masks */
+
+#define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7)
+
+/* 16-Bit Formats */
+#define MASK_OP_SB_DISP8(op) MASK_BITS_SHIFT(op, 8, 15)
+
+#define MASK_OP_SBC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SBC_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SBR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SBR_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SBRN_N(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SBRN_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SC_CONST8(op) MASK_BITS_SHIFT(op, 8, 15)
+
+#define MASK_OP_SLR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SLR_D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SLRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SLRO_D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SR_OP2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SRC_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SRO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SRO_OFF4(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SRR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SRRS_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SRRS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
+#define MASK_OP_SRRS_N(op) MASK_BITS_SHIFT(op, 6, 7)
+
+#define MASK_OP_SSR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SSR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
+
+#define MASK_OP_SSRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_SSRO_S1(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* 32-Bit Formats */
+
+/* ABS Format */
+#define MASK_OP_ABS_OFF18(op) (MASK_BITS_SHIFT(op, 16, 21) + \
+ (MASK_BITS(op, 28, 31) >> 22) + \
+ (MASK_BITS(op, 22, 25) >> 12) + \
+ (MASK_BITS(op, 12, 15) << 16))
+#define MASK_OP_ABS_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
+#define MASK_OP_ABS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* ABSB Format */
+#define MASK_OP_ABSB_OFF18(op) MASK_OP_ABS_OFF18(op)
+#define MASK_OP_ABSB_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
+#define MASK_OP_ABSB_B(op) MASK_BITS_SHIFT(op, 11, 11)
+#define MASK_OP_ABSB_BPOS(op) MASK_BITS_SHIFT(op, 7, 10)
+
+/* B Format */
+#define MASK_OP_B_DISP24(op) (MASK_BITS_SHIFT(op, 16, 31) + \
+ (MASK_BITS(op, 8, 15) << 8))
+/* BIT Format */
+#define MASK_OP_BIT_D(op) MASK_BITS_SHIFT(op, 28, 31)
+#define MASK_OP_BIT_POS2(op) MASK_BITS_SHIFT(op, 23, 27)
+#define MASK_OP_BIT_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
+#define MASK_OP_BIT_POS1(op) MASK_BITS_SHIFT(op, 16, 20)
+#define MASK_OP_BIT_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_BIT_S1(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* BO Format */
+#define MASK_OP_BO_OFF10(op) (MASK_BITS_SHIFT(op, 16, 21) + \
+ (MASK_BITS(op, 28, 31) >> 22))
+#define MASK_OP_BO_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
+#define MASK_OP_BO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_BO_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* BOL Format */
+#define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
+ (MASK_BITS(op, 28, 31) >> 22)) + \
+ (MASK_BITS(op, 22, 27) >> 12))
+
+#define MASK_OP_BOL_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_BOL_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* BRC Format */
+#define MASK_OP_BRC_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
+#define MASK_OP_BRC_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
+#define MASK_OP_BRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_BRC_S1(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* BRN Format */
+#define MASK_OP_BRN_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
+#define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
+#define MASK_OP_BRN_N(op) (MASK_BITS_SHIFT(op, 12, 15) + \
+ (MASK_BITS(op, 7, 7) >> 3))
+#define MASK_OP_BRN_S1(op) MASK_BITS_SHIFT(op, 8, 11)
+/* BRR Format */
+#define MASK_OP_BRR_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
+#define MASK_OP_BRR_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
+#define MASK_OP_BRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_BRR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* META MASK for similar instr Formats */
+#define MASK_OP_META_D(op) MASK_BITS_SHIFT(op, 28, 31)
+#define MASK_OP_META_S1(op) MASK_BITS_SHIFT(op, 8, 11)
+
+/* RC Format */
+#define MASK_OP_RC_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RC_OP2(op) MASK_BITS_SHIFT(op, 21, 27)
+#define MASK_OP_RC_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
+#define MASK_OP_RC_S1(op) MASK_OP_META_S1(op)
+
+/* RCPW Format */
+
+#define MASK_OP_RCPW_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RCPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
+#define MASK_OP_RCPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
+#define MASK_OP_RCPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
+#define MASK_OP_RCPW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RCPW_S1(op) MASK_OP_META_S1(op)
+
+/* RCR Format */
+
+#define MASK_OP_RCR_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RCR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RCR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
+#define MASK_OP_RCR_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
+#define MASK_OP_RCR_S1(op) MASK_OP_META_S1(op)
+
+/* RCRR Format */
+
+#define MASK_OP_RCRR_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RCRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RCRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
+#define MASK_OP_RCRR_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RCRR_S1(op) MASK_OP_META_S1(op)
+
+/* RCRW Format */
+
+#define MASK_OP_RCRW_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RCRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RCRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
+#define MASK_OP_RCRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
+#define MASK_OP_RCRW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RCRW_S1(op) MASK_OP_META_S1(op)
+
+/* RLC Format */
+
+#define MASK_OP_RLC_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RLC_CONST16(op) MASK_BITS_SHIFT(op, 12, 27)
+#define MASK_OP_RLC_S1(op) MASK_OP_META_S1(op)
+
+/* RR Format */
+#define MASK_OP_RR_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RR_OP2(op) MASK_BITS_SHIFT(op, 20, 27)
+#define MASK_OP_RR_N(op) MASK_BITS_SHIFT(op, 16, 17)
+#define MASK_OP_RR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RR_S1(op) MASK_OP_META_S1(op)
+
+/* RR1 Format */
+#define MASK_OP_RR1_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RR1_OP2(op) MASK_BITS_SHIFT(op, 18, 27)
+#define MASK_OP_RR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
+#define MASK_OP_RR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RR1_S1(op) MASK_OP_META_S1(op)
+
+/* RR2 Format */
+#define MASK_OP_RR2_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RR2_OP2(op) MASK_BITS_SHIFT(op, 16, 27)
+#define MASK_OP_RR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RR2_S1(op) MASK_OP_META_S1(op)
+
+/* RRPW Format */
+#define MASK_OP_RRPW_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RRPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
+#define MASK_OP_RRPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
+#define MASK_OP_RRPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
+#define MASK_OP_RRPW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RRPW_S1(op) MASK_OP_META_S1(op)
+
+/* RRR Format */
+#define MASK_OP_RRR_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RRR_OP2(op) MASK_BITS_SHIFT(op, 20, 23)
+#define MASK_OP_RRR_N(op) MASK_BITS_SHIFT(op, 16, 17)
+#define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RRR_S1(op) MASK_OP_META_S1(op)
+
+/* RRR1 Format */
+#define MASK_OP_RRR1_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RRR1_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RRR1_OP2(op) MASK_BITS_SHIFT(op, 18, 23)
+#define MASK_OP_RRR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
+#define MASK_OP_RRR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RRR1_S1(op) MASK_OP_META_S1(op)
+
+/* RRR2 Format */
+#define MASK_OP_RRR2_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RRR2_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RRR2_OP2(op) MASK_BITS_SHIFT(op, 16, 23)
+#define MASK_OP_RRR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op)
+
+/* RRRR Format */
+#define MASK_OP_RRRR_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RRRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RRRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
+#define MASK_OP_RRRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RRRR_S1(op) MASK_OP_META_S1(op)
+
+/* RRRW Format */
+#define MASK_OP_RRRW_D(op) MASK_OP_META_D(op)
+#define MASK_OP_RRRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
+#define MASK_OP_RRRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
+#define MASK_OP_RRRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
+#define MASK_OP_RRRW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
+#define MASK_OP_RRRW_S1(op) MASK_OP_META_S1(op)
+
+/* SYS Format */
+#define MASK_OP_SYS_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
+#define MASK_OP_SYS_S1D(op) MASK_OP_META_S1(op)
+
+
+
+/*
+ * Tricore Opcodes Enums
+ *
+ * Format: OPC(1|2|M)_InstrLen_Name
+ * OPC1 = only op1 field is used
+ * OPC2 = op1 and op2 field used part of OPCM
+ * OPCM = op1 field used to group Instr
+ * InstrLen = 16|32
+ * Name = Name of Instr
+ */
+
+/* 16-Bit */
+enum {
+
+ OPCM_16_SR_SYSTEM = 0x00,
+ OPCM_16_SR_ACCU = 0x32,
+
+ OPC1_16_SRC_ADD = 0xc2,
+ OPC1_16_SRC_ADD_A15 = 0x92,
+ OPC1_16_SRC_ADD_15A = 0x9a,
+ OPC1_16_SRR_ADD = 0x42,
+ OPC1_16_SRR_ADD_A15 = 0x12,
+ OPC1_16_SRR_ADD_15A = 0x1a,
+ OPC1_16_SRC_ADD_A = 0xb0,
+ OPC1_16_SRR_ADD_A = 0x30,
+ OPC1_16_SRR_ADDS = 0x22,
+ OPC1_16_SRRS_ADDSC_A = 0x10,
+ OPC1_16_SC_AND = 0x16,
+ OPC1_16_SRR_AND = 0x26,
+ OPC1_16_SC_BISR = 0xe0,
+ OPC1_16_SRC_CADD = 0x8a,
+ OPC1_16_SRC_CADDN = 0xca,
+ OPC1_16_SB_CALL = 0x5c,
+ OPC1_16_SRC_CMOV = 0xaa,
+ OPC1_16_SRR_CMOV = 0x2a,
+ OPC1_16_SRC_CMOVN = 0xea,
+ OPC1_16_SRR_CMOVN = 0x6a,
+ OPC1_16_SRC_EQ = 0xba,
+ OPC1_16_SRR_EQ = 0x3a,
+ OPC1_16_SB_J = 0x3c,
+ OPC1_16_SBC_JEQ = 0x1e,
+ OPC1_16_SBR_JEQ = 0x3e,
+ OPC1_16_SBR_JGEZ = 0xce,
+ OPC1_16_SBR_JGTZ = 0x4e,
+ OPC1_16_SR_JI = 0xdc,
+ OPC1_16_SBR_JLEZ = 0x8e,
+ OPC1_16_SBR_JLTZ = 0x0e,
+ OPC1_16_SBC_JNE = 0x5e,
+ OPC1_16_SBR_JNE = 0x7e,
+ OPC1_16_SB_JNZ = 0xee,
+ OPC1_16_SBR_JNZ = 0xf6,
+ OPC1_16_SBR_JNZ_A = 0x7c,
+ OPC1_16_SBRN_JNZ_T = 0xae,
+ OPC1_16_SB_JZ = 0x6e,
+ OPC1_16_SBR_JZ = 0x76,
+ OPC1_16_SBR_JZ_A = 0xbc,
+ OPC1_16_SBRN_JZ_T = 0x2e,
+ OPC1_16_SC_LD_A = 0xd8,
+ OPC1_16_SLR_LD_A = 0xd4,
+ OPC1_16_SLR_LD_A_POSTINC = 0xc4,
+ OPC1_16_SLRO_LD_A = 0xc8,
+ OPC1_16_SRO_LD_A = 0xcc,
+ OPC1_16_SLR_LD_BU = 0x14,
+ OPC1_16_SLR_LD_BU_POSTINC = 0x04,
+ OPC1_16_SLRO_LD_BU = 0x08,
+ OPC1_16_SRO_LD_BU = 0x0c,
+ OPC1_16_SLR_LD_H = 0x94,
+ OPC1_16_SLR_LD_H_POSTINC = 0x84,
+ OPC1_16_SLRO_LD_H = 0x88,
+ OPC1_16_SRO_LD_H = 0x8c,
+ OPC1_16_SC_LD_W = 0x58,
+ OPC1_16_SLR_LD_W = 0x54,
+ OPC1_16_SLR_LD_W_POSTINC = 0x44,
+ OPC1_16_SLRO_LD_W = 0x48,
+ OPC1_16_SRO_LD_W = 0x4c,
+ OPC1_16_SBR_LOOP = 0xfc,
+ OPC1_16_SRC_LT = 0xfa,
+ OPC1_16_SRR_LT = 0x7a,
+ OPC1_16_SC_MOV = 0xda,
+ OPC1_16_SRC_MOV = 0x82,
+ OPC1_16_SRR_MOV = 0x02,
+ OPC1_16_SRC_MOV_E = 0xd2,/* 1.6 only */
+ OPC1_16_SRC_MOV_A = 0xa0,
+ OPC1_16_SRR_MOV_A = 0x60,
+ OPC1_16_SRR_MOV_AA = 0x40,
+ OPC1_16_SRR_MOV_D = 0x80,
+ OPC1_16_SRR_MUL = 0xe2,
+ OPC1_16_SR_NOT = 0x46,
+ OPC1_16_SC_OR = 0x96,
+ OPC1_16_SRR_OR = 0xa6,
+ OPC1_16_SRC_SH = 0x06,
+ OPC1_16_SRC_SHA = 0x86,
+ OPC1_16_SC_ST_A = 0xf8,
+ OPC1_16_SRO_ST_A = 0xec,
+ OPC1_16_SSR_ST_A = 0xf4,
+ OPC1_16_SSR_ST_A_POSTINC = 0xe4,
+ OPC1_16_SSRO_ST_A = 0xe8,
+ OPC1_16_SRO_ST_B = 0x2c,
+ OPC1_16_SSR_ST_B = 0x34,
+ OPC1_16_SSR_ST_B_POSTINC = 0x24,
+ OPC1_16_SSRO_ST_B = 0x28,
+ OPC1_16_SRO_ST_H = 0xac,
+ OPC1_16_SSR_ST_H = 0xb4,
+ OPC1_16_SSR_ST_H_POSTINC = 0xa4,
+ OPC1_16_SSRO_ST_H = 0xa8,
+ OPC1_16_SC_ST_W = 0x78,
+ OPC1_16_SRO_ST_W = 0x6c,
+ OPC1_16_SSR_ST_W = 0x74,
+ OPC1_16_SSR_ST_W_POSTINC = 0x64,
+ OPC1_16_SSRO_ST_W = 0x68,
+ OPC1_16_SRR_SUB = 0xa2,
+ OPC1_16_SRR_SUB_A15B = 0x52,
+ OPC1_16_SRR_SUB_15AB = 0x5a,
+ OPC1_16_SC_SUB_A = 0x20,
+ OPC1_16_SRR_SUBS = 0x62,
+ OPC1_16_SRR_XOR = 0xc6,
+
+};
+
+/*
+ * SR Format
+ */
+/* OPCM_16_SR_SYSTEM */
+enum {
+
+ OPC2_16_SR_NOP = 0x00,
+ OPC2_16_SR_RET = 0x09,
+ OPC2_16_SR_RFE = 0x08,
+ OPC2_16_SR_DEBUG = 0x0a,
+};
+/* OPCM_16_SR_ACCU */
+enum {
+ OPC2_16_SR_RSUB = 0x05,
+ OPC2_16_SR_SAT_B = 0x00,
+ OPC2_16_SR_SAT_BU = 0x01,
+ OPC2_16_SR_SAT_H = 0x02,
+ OPC2_16_SR_SAT_HU = 0x03,
+
+};
+
+/* 32-Bit */
+
+enum {
+/* ABS Format 1, M */
+ OPCM_32_ABS_LDW = 0x85,
+ OPCM_32_ABS_LDB = 0x05,
+ OPCM_32_ABS_LDMST_SWAP = 0xe5,
+ OPCM_32_ABS_LDST_CONTEXT = 0x15,
+ OPCM_32_ABS_STORE = 0xa5,
+ OPCM_32_ABS_STOREB_H = 0x25,
+ OPC1_32_ABS_STOREQ = 0x65,
+ OPC1_32_ABS_LD_Q = 0x45,
+ OPC1_32_ABS_LEA = 0xc5,
+/* ABSB Format */
+ OPC1_32_ABSB_ST_T = 0xd5,
+/* B Format */
+ OPC1_32_B_CALL = 0x6d,
+ OPC1_32_B_CALLA = 0xed,
+ OPC1_32_B_J = 0x1d,
+ OPC1_32_B_JA = 0x9d,
+ OPC1_32_B_JL = 0x5d,
+ OPC1_32_B_JLA = 0xdd,
+/* Bit Format */
+ OPCM_32_BIT_ANDACC = 0x47,
+ OPCM_32_BIT_LOGICAL_T1 = 0x87,
+ OPCM_32_BIT_INSERT = 0x67,
+ OPCM_32_BIT_LOGICAL_T2 = 0x07,
+ OPCM_32_BIT_ORAND = 0xc7,
+ OPCM_32_BIT_SH_LOGIC1 = 0x27,
+ OPCM_32_BIT_SH_LOGIC2 = 0xa7,
+/* BO Format */
+ OPCM_32_BO_ADDRMODE_POST_PRE_BASE = 0x89,
+ OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR = 0xa9,
+ OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE = 0x09,
+ OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR = 0x29,
+ OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE = 0x49,
+ OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR = 0x69,
+/* BOL Format */
+ OPC1_32_BOL_LD_A_LONGOFF = 0x99,
+ OPC1_32_BOL_LD_W_LONFOFF = 0x19,
+ OPC1_32_BOL_LEA_LONGOFF = 0xd9,
+ OPC1_32_BOL_ST_W_LONGOFF = 0x59,
+ OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */
+/* BRC Format */
+ OPCM_32_BRC_EQ_NEQ = 0xdf,
+ OPCM_32_BRC_GE = 0xff,
+ OPCM_32_BRC_JLT = 0xbf,
+ OPCM_32_BRC_JNE = 0x9f,
+/* BRN Format */
+ OPCM_32_BRN_JTT = 0x6f,
+/* BRR Format */
+ OPCM_32_BRR_EQ_NEQ = 0x5f,
+ OPCM_32_BRR_ADDR_EQ_NEQ = 0x7d,
+ OPCM_32_BRR_GE = 0x7f,
+ OPCM_32_BRR_JLT = 0x3f,
+ OPCM_32_BRR_JNE = 0x1f,
+ OPCM_32_BRR_JNZ = 0xbd,
+ OPCM_32_BRR_LOOP = 0xfd,
+/* RC Format */
+ OPCM_32_RC_LOGICAL_SHIFT = 0x8f,
+ OPCM_32_RC_ACCUMULATOR = 0x8b,
+ OPCM_32_RC_SERVICEROUTINE = 0xad,
+ OPCM_32_RC_MUL = 0x53,
+/* RCPW Format */
+ OPCM_32_RCPW_MASK_INSERT = 0xb7,
+/* RCR Format */
+ OPCM_32_RCR_COND_SELECT = 0xab,
+ OPCM_32_RCR_MADD = 0x13,
+ OPCM_32_RCR_MSUB = 0x33,
+/* RCRR Format */
+ OPC1_32_RCRR_INSERT = 0x97,
+/* RCRW Format */
+ OPCM_32_RCRW_MASK_INSERT = 0xd7,
+/* RLC Format */
+ OPC1_32_RLC_ADDI = 0x1b,
+ OPC1_32_RLC_ADDIH = 0x9b,
+ OPC1_32_RLC_ADDIH_A = 0x11,
+ OPC1_32_RLC_MFCR = 0x4d,
+ OPC1_32_RLC_MOV = 0x3b,
+ OPC1_32_RLC_MOV_U = 0xbb,
+ OPC1_32_RLC_MOV_H = 0x7b,
+ OPC1_32_RLC_MOVH_A = 0x91,
+ OPC1_32_RLC_MTCR = 0xcd,
+/* RR Format */
+ OPCM_32_RR_LOGICAL_SHIFT = 0x0f,
+ OPCM_32_RR_ACCUMULATOR = 0x0b,
+ OPCM_32_RR_ADRESS = 0x01,
+ OPCM_32_RR_FLOAT = 0x4b,
+ OPCM_32_RR_IDIRECT = 0x2d,
+/* RR1 Format */
+ OPCM_32_RR1_MUL = 0xb3,
+ OPCM_32_RR1_MULQ = 0x93,
+/* RR2 Format */
+ OPCM_32_RR2_MUL = 0x73,
+/* RRPW Format */
+ OPCM_32_RRPW_EXTRACT_INSERT = 0x37,
+ OPC1_32_RRPW_DEXTR = 0x77,
+/* RRR Format */
+ OPCM_32_RRR_COND_SELECT = 0x2b,
+ OPCM_32_RRR_FLOAT = 0x6b,
+/* RRR1 Format */
+ OPCM_32_RRR1_MADD = 0x83,
+ OPCM_32_RRR1_MADDQ_H = 0x43,
+ OPCM_32_RRR1_MADDSU_H = 0xc3,
+ OPCM_32_RRR1_MSUB_H = 0xa3,
+ OPCM_32_RRR1_MSUB_Q = 0x63,
+ OPCM_32_RRR1_MSUBADS_H = 0xe3,
+/* RRR2 Format */
+ OPCM_32_RRR2_MADD = 0x03,
+ OPCM_32_RRR2_MSUB = 0x23,
+/* RRRR Format */
+ OPCM_32_RRRR_EXTRACT_INSERT = 0x17,
+/* RRRW Format */
+ OPCM_32_RRRW_EXTRACT_INSERT = 0x57,
+/* SYS Format */
+ OPCM_32_SYS_INTERRUPTS = 0x0d,
+ OPC1_32_SYS_RSTV = 0x2f,
+};
+
+
+
+/*
+ * ABS Format
+ */
+
+/* OPCM_32_ABS_LDW */
+enum {
+
+ OPC2_32_ABS_LD_A = 0x02,
+ OPC2_32_ABS_LD_D = 0x01,
+ OPC2_32_ABS_LD_DA = 0x03,
+ OPC2_32_ABS_LD_W = 0x00,
+};
+
+/* OPCM_32_ABS_LDB */
+enum {
+ OPC2_32_ABS_LD_B = 0x00,
+ OPC2_32_ABS_LD_BU = 0x01,
+ OPC2_32_ABS_LD_H = 0x02,
+ OPC2_32_ABS_LD_HU = 0x03,
+};
+/* OPCM_32_ABS_LDMST_SWAP */
+enum {
+ OPC2_32_ABS_LDMST = 0x01,
+ OPC2_32_ABS_SWAP_W = 0x00,
+};
+/* OPCM_32_ABS_LDST_CONTEXT */
+enum {
+ OPC2_32_ABS_LDLCX = 0x02,
+ OPC2_32_ABS_LDUCX = 0x03,
+ OPC2_32_ABS_STLCX = 0x00,
+ OPC2_32_ABS_STUCX = 0x01,
+};
+/* OPCM_32_ABS_STORE */
+enum {
+ OPC2_32_ABS_ST_A = 0x02,
+ OPC2_32_ABS_ST_D = 0x01,
+ OPC2_32_ABS_ST_DA = 0x03,
+ OPC2_32_ABS_ST_W = 0x00,
+};
+/* OPCM_32_ABS_STOREB_H */
+enum {
+ OPC2_32_ABS_ST_B = 0x00,
+ OPC2_32_ABS_ST_H = 0x02,
+};
+/*
+ * Bit Format
+ */
+/* OPCM_32_BIT_ANDACC */
+enum {
+ OPC2_32_BIT_AND_AND_T = 0x00,
+ OPC2_32_BIT_AND_ANDN_T = 0x03,
+ OPC2_32_BIT_AND_NOR_T = 0x02,
+ OPC2_32_BIT_AND_OR_T = 0x01,
+};
+/* OPCM_32_BIT_LOGICAL_T */
+enum {
+ OPC2_32_BIT_AND_T = 0x00,
+ OPC2_32_BIT_ANDN_T = 0x03,
+ OPC2_32_BIT_NOR_T = 0x02,
+ OPC2_32_BIT_OR_T = 0x01,
+};
+/* OPCM_32_BIT_INSERT */
+enum {
+ OPC2_32_BIT_INS_T = 0x00,
+ OPC2_32_BIT_INSN_T = 0x01,
+};
+/* OPCM_32_BIT_LOGICAL_T2 */
+enum {
+ OPC2_32_BIT_NAND_T = 0x00,
+ OPC2_32_BIT_ORN_T = 0x01,
+ OPC2_32_BIT_XNOR_T = 0x02,
+ OPC2_32_BIT_XOR_T = 0x03,
+};
+/* OPCM_32_BIT_ORAND */
+enum {
+ OPC2_32_BIT_OR_AND_T = 0x00,
+ OPC2_32_BIT_OR_ANDN_T = 0x03,
+ OPC2_32_BIT_OR_NOR_T = 0x02,
+ OPC2_32_BIT_OR_OR_T = 0x01,
+};
+/*OPCM_32_BIT_SH_LOGIC1 */
+enum {
+ OPC2_32_BIT_SH_AND_T = 0x00,
+ OPC2_32_BIT_SH_ANDN_T = 0x03,
+ OPC2_32_BIT_SH_NOR_T = 0x02,
+ OPC2_32_BIT_SH_OR_T = 0x01,
+};
+/* OPCM_32_BIT_SH_LOGIC2 */
+enum {
+ OPC2_32_BIT_SH_NAND_T = 0x00,
+ OPC2_32_BIT_SH_ORN_T = 0x01,
+ OPC2_32_BIT_SH_XNOR_T = 0x02,
+ OPC2_32_BIT_SH_XOR_T = 0x03,
+};
+/*
+ * BO Format
+ */
+/* OPCM_32_BO_ADDRMODE_POST_PRE_BASE */
+enum {
+ OPC2_32_BO_CACHEA_I_SHORTOFF = 0x2e,
+ OPC2_32_BO_CACHEA_I_POSTINC = 0x0e,
+ OPC2_32_BO_CACHEA_I_PREINC = 0x1e,
+ OPC2_32_BO_CACHEA_W_SHORTOFF = 0x2c,
+ OPC2_32_BO_CACHEA_W_POSTINC = 0x0c,
+ OPC2_32_BO_CACHEA_W_PREINC = 0x1c,
+ OPC2_32_BO_CACHEA_WI_SHORTOFF = 0x2d,
+ OPC2_32_BO_CACHEA_WI_POSTINC = 0x0d,
+ OPC2_32_BO_CACHEA_WI_PREINC = 0x1d,
+ /* 1.3.1 only */
+ OPC2_32_BO_CACHEI_W_SHORTOFF = 0x2b,
+ OPC2_32_BO_CACHEI_W_POSTINC = 0x0b,
+ OPC2_32_BO_CACHEI_W_PREINC = 0x1b,
+ OPC2_32_BO_CACHEI_WI_SHORTOFF = 0x2f,
+ OPC2_32_BO_CACHEI_WI_POSTINC = 0x0f,
+ OPC2_32_BO_CACHEI_WI_PREINC = 0x1f,
+ /* end 1.3.1 only */
+ OPC2_32_BO_ST_A_SHORTOFF = 0x26,
+ OPC2_32_BO_ST_A_POSTINC = 0x06,
+ OPC2_32_BO_ST_A_PREINC = 0x16,
+ OPC2_32_BO_ST_B_SHORTOFF = 0x20,
+ OPC2_32_BO_ST_B_POSTINC = 0x00,
+ OPC2_32_BO_ST_B_PREINC = 0x10,
+ OPC2_32_BO_ST_D_SHORTOFF = 0x25,
+ OPC2_32_BO_ST_D_POSTINC = 0x05,
+ OPC2_32_BO_ST_D_PREINC = 0x15,
+ OPC2_32_BO_ST_DA_SHORTOFF = 0x27,
+ OPC2_32_BO_ST_DA_POSTINC = 0x07,
+ OPC2_32_BO_ST_DA_PREINC = 0x17,
+ OPC2_32_BO_ST_H_SHORTOFF = 0x22,
+ OPC2_32_BO_ST_H_POSTINC = 0x02,
+ OPC2_32_BO_ST_H_PREINC = 0x12,
+ OPC2_32_BO_ST_Q_SHORTOFF = 0x28,
+ OPC2_32_BO_ST_Q_POSTINC = 0x08,
+ OPC2_32_BO_ST_Q_PREINC = 0x18,
+ OPC2_32_BO_ST_W_SHORTOFF = 0x24,
+ OPC2_32_BO_ST_W_POSTINC = 0x04,
+ OPC2_32_BO_ST_W_PREINC = 0x14,
+};
+/* OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR */
+enum {
+ OPC2_32_BO_CACHEA_I_BR = 0x0e,
+ OPC2_32_BO_CACHEA_I_CIRC = 0x1e,
+ OPC2_32_BO_CACHEA_W_BR = 0x0c,
+ OPC2_32_BO_CACHEA_W_CIRC = 0x1c,
+ OPC2_32_BO_CACHEA_WI_BR = 0x0d,
+ OPC2_32_BO_CACHEA_WI_CIRC = 0x1d,
+ OPC2_32_BO_ST_A_BR = 0x06,
+ OPC2_32_BO_ST_A_CIRC = 0x16,
+ OPC2_32_BO_ST_B_BR = 0x00,
+ OPC2_32_BO_ST_B_CIRC = 0x10,
+ OPC2_32_BO_ST_D_BR = 0x05,
+ OPC2_32_BO_ST_D_CIRC = 0x15,
+ OPC2_32_BO_ST_DA_BR = 0x07,
+ OPC2_32_BO_ST_DA_CIRC = 0x17,
+ OPC2_32_BO_ST_H_BR = 0x02,
+ OPC2_32_BO_ST_H_CIRC = 0x12,
+ OPC2_32_BO_ST_Q_BR = 0x08,
+ OPC2_32_BO_ST_Q_CIRC = 0x18,
+ OPC2_32_BO_ST_W_BR = 0x04,
+ OPC2_32_BO_ST_W_CIRC = 0x14,
+};
+/* OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE */
+enum {
+ OPC2_32_BO_LD_A_SHORTOFF = 0x26,
+ OPC2_32_BO_LD_A_POSTINC = 0x06,
+ OPC2_32_BO_LD_A_PREINC = 0x16,
+ OPC2_32_BO_LD_B_SHORTOFF = 0x20,
+ OPC2_32_BO_LD_B_POSTINC = 0x00,
+ OPC2_32_BO_LD_B_PREINC = 0x10,
+ OPC2_32_BO_LD_BU_SHORTOFF = 0x21,
+ OPC2_32_BO_LD_BU_POSTINC = 0x01,
+ OPC2_32_BO_LD_BU_PREINC = 0x11,
+ OPC2_32_BO_LD_D_SHORTOFF = 0x25,
+ OPC2_32_BO_LD_D_POSTINC = 0x05,
+ OPC2_32_BO_LD_D_PREINC = 0x15,
+ OPC2_32_BO_LD_DA_SHORTOFF = 0x27,
+ OPC2_32_BO_LD_DA_POSTINC = 0x07,
+ OPC2_32_BO_LD_DA_PREINC = 0x17,
+ OPC2_32_BO_LD_H_SHORTOFF = 0x22,
+ OPC2_32_BO_LD_H_POSTINC = 0x02,
+ OPC2_32_BO_LD_H_PREINC = 0x12,
+ OPC2_32_BO_LD_HU_SHORTOFF = 0x23,
+ OPC2_32_BO_LD_HU_POSTINC = 0x03,
+ OPC2_32_BO_LD_HU_PREINC = 0x13,
+ OPC2_32_BO_LD_Q_SHORTOFF = 0x28,
+ OPC2_32_BO_LD_Q_POSTINC = 0x08,
+ OPC2_32_BO_LD_Q_PREINC = 0x18,
+ OPC2_32_BO_LD_W_SHORTOFF = 0x24,
+ OPC2_32_BO_LD_W_POSTINC = 0x04,
+ OPC2_32_BO_LD_W_PREINC = 0x14,
+};
+/* OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR */
+enum {
+ OPC2_32_BO_LD_A_BR = 0x06,
+ OPC2_32_BO_LD_A_CIRC = 0x16,
+ OPC2_32_BO_LD_B_BR = 0x00,
+ OPC2_32_BO_LD_B_CIRC = 0x10,
+ OPC2_32_BO_LD_BU_BR = 0x01,
+ OPC2_32_BO_LD_BU_CIRC = 0x11,
+ OPC2_32_BO_LD_D_BR = 0x05,
+ OPC2_32_BO_LD_D_CIRC = 0x15,
+ OPC2_32_BO_LD_DA_BR = 0x07,
+ OPC2_32_BO_LD_DA_CIRC = 0x17,
+ OPC2_32_BO_LD_H_BR = 0x02,
+ OPC2_32_BO_LD_H_CIRC = 0x12,
+ OPC2_32_BO_LD_HU_BR = 0x03,
+ OPC2_32_BO_LD_HU_CIRC = 0x13,
+ OPC2_32_BO_LD_Q_BR = 0x08,
+ OPC2_32_BO_LD_Q_CIRC = 0x18,
+ OPC2_32_BO_LD_W_BR = 0x04,
+ OPC2_32_BO_LD_W_CIRC = 0x14,
+};
+/* OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE */
+enum {
+ OPC2_32_BO_LDLCX_SHORTOFF = 0x24,
+ OPC2_32_BO_LDMST_SHORTOFF = 0x21,
+ OPC2_32_BO_LDMST_POSTINC = 0x01,
+ OPC2_32_BO_LDMST_PREINC = 0x11,
+ OPC2_32_BO_LDUCX_SHORTOFF = 0x25,
+ OPC2_32_BO_LEA_SHORTOFF = 0x28,
+ OPC2_32_BO_STLCX_SHORTOFF = 0x26,
+ OPC2_32_BO_STUCX_SHORTOFF = 0x27,
+ OPC2_32_BO_SWAP_W_SHORTOFF = 0x20,
+ OPC2_32_BO_SWAP_W_POSTINC = 0x00,
+ OPC2_32_BO_SWAP_W_PREINC = 0x10,
+};
+/*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR */
+enum {
+ OPC2_32_BO_LDMST_BR = 0x01,
+ OPC2_32_BO_LDMST_CIRC = 0x11,
+ OPC2_32_BO_SWAP_W_BR = 0x00,
+ OPC2_32_BO_SWAP_W_CIRC = 0x10,
+};
+/*
+ * BRC Format
+ */
+/*OPCM_32_BRC_EQ_NEQ */
+enum {
+ OPC2_32_BRC_JEQ = 0x00,
+ OPC2_32_BRC_JNE = 0x01,
+};
+/* OPCM_32_BRC_GE */
+enum {
+ OP2_BRC_JGE = 0x00,
+ OPC_BRC_JGE_U = 0x01,
+};
+/* OPCM_32_BRC_JLT */
+enum {
+ OPC2_32_BRC_JLT = 0x00,
+ OPC2_32_BRC_JLT_U = 0x01,
+};
+/* OPCM_32_BRC_JNE */
+enum {
+ OPC2_32_BRC_JNED = 0x01,
+ OPC2_32_BRC_JNEI = 0x00,
+};
+/*
+ * BRN Format
+ */
+/* OPCM_32_BRN_JTT */
+enum {
+ OPC2_32_BRN_JNZ_T = 0x01,
+ OPC2_32_BRN_JZ_T = 0x00,
+};
+/*
+ * BRR Format
+ */
+/* OPCM_32_BRR_EQ_NEQ */
+enum {
+ OPC2_32_BRR_JEQ = 0x00,
+ OPC2_32_BRR_JNE = 0x01,
+};
+/* OPCM_32_BRR_ADDR_EQ_NEQ */
+enum {
+ OPC2_32_BRR_JEQ_A = 0x00,
+ OPC2_32_BRR_JNE_A = 0x01,
+};
+/*OPCM_32_BRR_GE */
+enum {
+ OPC2_32_BRR_JGE = 0x00,
+ OPC2_32_BRR_JGE_U = 0x01,
+};
+/* OPCM_32_BRR_JLT */
+enum {
+ OPC2_32_BRR_JLT = 0x00,
+ OPC2_32_BRR_JLT_U = 0x01,
+};
+/* OPCM_32_BRR_JNE */
+enum {
+ OPC2_32_BRR_JNED = 0x01,
+ OPC2_32_BRR_JNEI = 0x00,
+};
+/* OPCM_32_BRR_JNZ */
+enum {
+ OPC2_32_BRR_JNZ_A = 0x01,
+ OPC2_32_BRR_JZ_A = 0x00,
+};
+/* OPCM_32_BRR_LOOP */
+enum {
+ OPC2_32_BRR_LOOP = 0x00,
+ OPC2_32_BRR_LOOPU = 0x01,
+};
+/*
+ * RC Format
+ */
+/* OPCM_32_RC_LOGICAL_SHIFT */
+enum {
+ OPC2_32_RC_AND = 0x08,
+ OPC2_32_RC_ANDN = 0x0e,
+ OPC2_32_RC_NAND = 0x09,
+ OPC2_32_RC_NOR = 0x0b,
+ OPC2_32_RC_OR = 0x0a,
+ OPC2_32_RC_ORN = 0x0f,
+ OPC2_32_RC_SH = 0x00,
+ OPC2_32_RC_SH_H = 0x40,
+ OPC2_32_RC_SHA = 0x01,
+ OPC2_32_RC_SHA_H = 0x41,
+ OPC2_32_RC_SHAS = 0x02,
+ OPC2_32_RC_XNOR = 0x0d,
+ OPC2_32_RC_XOR = 0x0c,
+};
+/* OPCM_32_RC_ACCUMULATOR */
+enum {
+ OPC2_32_RC_ABSDIF = 0x0e,
+ OPC2_32_RC_ABSDIFS = 0x0f,
+ OPC2_32_RC_ADD = 0x00,
+ OPC2_32_RC_ADDC = 0x05,
+ OPC2_32_RC_ADDS = 0x02,
+ OPC2_32_RC_ADDS_U = 0x03,
+ OPC2_32_RC_ADDX = 0x04,
+ OPC2_32_RC_AND_EQ = 0x20,
+ OPC2_32_RC_AND_GE = 0x24,
+ OPC2_32_RC_AND_GE_U = 0x25,
+ OPC2_32_RC_AND_LT = 0x22,
+ OPC2_32_RC_AND_LT_U = 0x23,
+ OPC2_32_RC_AND_NE = 0x21,
+ OPC2_32_RC_EQ = 0x10,
+ OPC2_32_RC_EQANY_B = 0x56,
+ OPC2_32_RC_EQANY_H = 0x76,
+ OPC2_32_RC_GE = 0x14,
+ OPC2_32_RC_GE_U = 0x15,
+ OPC2_32_RC_LT = 0x12,
+ OPC2_32_RC_LT_U = 0x13,
+ OPC2_32_RC_MAX = 0x1a,
+ OPC2_32_RC_MAX_U = 0x1b,
+ OPC2_32_RC_MIN = 0x18,
+ OPC2_32_RC_MIN_U = 0x19,
+ OPC2_32_RC_NE = 0x11,
+ OPC2_32_RC_OR_EQ = 0x27,
+ OPC2_32_RC_OR_GE = 0x2b,
+ OPC2_32_RC_OR_GE_U = 0x2c,
+ OPC2_32_RC_OR_LT = 0x29,
+ OPC2_32_RC_OR_LT_U = 0x2a,
+ OPC2_32_RC_OR_NE = 0x28,
+ OPC2_32_RC_RSUB = 0x08,
+ OPC2_32_RC_RSUBS = 0x0a,
+ OPC2_32_RC_RSUBS_U = 0x0b,
+ OPC2_32_RC_SH_EQ = 0x37,
+ OPC2_32_RC_SH_GE = 0x3b,
+ OPC2_32_RC_SH_GE_U = 0x3c,
+ OPC2_32_RC_SH_LT = 0x39,
+ OPC2_32_RC_SH_LT_U = 0x3a,
+ OPC2_32_RC_SH_NE = 0x38,
+ OPC2_32_RC_XOR_EQ = 0x2f,
+ OPC2_32_RC_XOR_GE = 0x33,
+ OPC2_32_RC_XOR_GE_U = 0x34,
+ OPC2_32_RC_XOR_LT = 0x31,
+ OPC2_32_RC_XOR_LT_U = 0x32,
+ OPC2_32_RC_XOR_NE = 0x30,
+};
+/* OPCM_32_RC_SERVICEROUTINE */
+enum {
+ OPC2_32_RC_BISR = 0x00,
+ OPC2_32_RC_SYSCALL = 0x04,
+};
+/* OPCM_32_RC_MUL */
+enum {
+ OPC2_32_RC_MUL_32 = 0x01,
+ OPC2_32_RC_MUL_64 = 0x03,
+ OPC2_32_RC_MULS_32 = 0x05,
+ OPC2_32_RC_MUL_U_64 = 0x02,
+ OPC2_32_RC_MULS_U_32 = 0x04,
+};
+/*
+ * RCPW Format
+ */
+/* OPCM_32_RCPW_MASK_INSERT */
+enum {
+ OPC2_32_RCPW_IMASK = 0x01,
+ OPC2_32_RCPW_INSERT = 0x00,
+};
+/*
+ * RCR Format
+ */
+/* OPCM_32_RCR_COND_SELECT */
+enum {
+ OPC2_32_RCR_CADD = 0x00,
+ OPC2_32_RCR_CADDN = 0x01,
+ OPC2_32_RCR_SEL = 0x04,
+ OPC2_32_RCR_SELN = 0x05,
+};
+/* OPCM_32_RCR_MADD */
+enum {
+ OPC2_32_RCR_MADD_32 = 0x01,
+ OPC2_32_RCR_MADD_64 = 0x03,
+ OPC2_32_RCR_MADDS_32 = 0x05,
+ OPC2_32_RCR_MADDS_64 = 0x07,
+ OPC2_32_RCR_MADD_U_64 = 0x02,
+ OPC2_32_RCR_MADDS_U_32 = 0x04,
+ OPC2_32_RCR_MADDS_U_64 = 0x06,
+};
+/* OPCM_32_RCR_MSUB */
+enum {
+ OPC2_32_RCR_MSUB_32 = 0x01,
+ OPC2_32_RCR_MSUB_64 = 0x03,
+ OPC2_32_RCR_MSUBS_32 = 0x05,
+ OPC2_32_RCR_MSUBS_64 = 0x07,
+ OPC2_32_RCR_MSUB_U_32 = 0x02,
+ OPC2_32_RCR_MSUBS_U_32 = 0x04,
+ OPC2_32_RCR_MSUBS_U_64 = 0x06,
+};
+/*
+ * RCRW Format
+ */
+/* OPCM_32_RCRW_MASK_INSERT */
+enum {
+ OPC2_32_RCRW_IMASK = 0x01,
+ OPC2_32_RCRW_INSERT = 0x00,
+};
+
+/*
+ * RR Format
+ */
+/* OPCM_32_RR_LOGICAL_SHIFT */
+enum {
+ OPC2_32_RR_AND = 0x08,
+ OPC2_32_RR_ANDN = 0x0e,
+ OPC2_32_RR_CLO = 0x1c,
+ OPC2_32_RR_CLO_H = 0x7d,
+ OPC2_32_RR_CLS = 0x1d,
+ OPC2_32_RR_CLS_H = 0x7e,
+ OPC2_32_RR_CLZ = 0x1b,
+ OPC2_32_RR_CLZ_H = 0x7c,
+ OPC2_32_RR_NAND = 0x09,
+ OPC2_32_RR_NOR = 0x0b,
+ OPC2_32_RR_OR = 0x0a,
+ OPC2_32_RR_ORN = 0x0f,
+ OPC2_32_RR_SH = 0x00,
+ OPC2_32_RR_SH_H = 0x40,
+ OPC2_32_RR_SHA = 0x01,
+ OPC2_32_RR_SHA_H = 0x41,
+ OPC2_32_RR_SHAS = 0x02,
+ OPC2_32_RR_XNOR = 0x0d,
+ OPC2_32_RR_XOR = 0x0c,
+};
+/* OPCM_32_RR_ACCUMULATOR */
+enum {
+ OPC2_32_RR_ABS = 0x1c,
+ OPC2_32_RR_ABS_B = 0x5c,
+ OPC2_32_RR_ABS_H = 0x7c,
+ OPC2_32_RR_ABSDIF = 0x0e,
+ OPC2_32_RR_ABSDIF_B = 0x4e,
+ OPC2_32_RR_ABSDIF_H = 0x6e,
+ OPC2_32_RR_ABSDIFS = 0x0f,
+ OPC2_32_RR_ABSDIFS_H = 0x6f,
+ OPC2_32_RR_ABSS = 0x1d,
+ OPC2_32_RR_ABSS_H = 0x7d,
+ OPC2_32_RR_ADD = 0x00,
+ OPC2_32_RR_ADD_B = 0x40,
+ OPC2_32_RR_ADD_H = 0x60,
+ OPC2_32_RR_ADDC = 0x05,
+ OPC2_32_RR_ADDS = 0x02,
+ OPC2_32_RR_ADDS_H = 0x62,
+ OPC2_32_RR_ADDS_HU = 0x63,
+ OPC2_32_RR_ADDS_U = 0x03,
+ OPC2_32_RR_ADDX = 0x04,
+ OPC2_32_RR_AND_EQ = 0x20,
+ OPC2_32_RR_AND_GE = 0x24,
+ OPC2_32_RR_AND_GE_U = 0x25,
+ OPC2_32_RR_AND_LT = 0x22,
+ OPC2_32_RR_AND_LT_U = 0x23,
+ OPC2_32_RR_AND_NE = 0x21,
+ OPC2_32_RR_EQ = 0x10,
+ OPC2_32_RR_EQ_B = 0x50,
+ OPC2_32_RR_EQ_H = 0x70,
+ OPC2_32_RR_EQ_W = 0x90,
+ OPC2_32_RR_EQANY_B = 0x56,
+ OPC2_32_RR_EQANY_H = 0x76,
+ OPC2_32_RR_GE = 0x14,
+ OPC2_32_RR_GE_U = 0x15,
+ OPC2_32_RR_LT = 0x12,
+ OPC2_32_RR_LT_U = 0x13,
+ OPC2_32_RR_LT_B = 0x52,
+ OPC2_32_RR_LT_BU = 0x53,
+ OPC2_32_RR_LT_H = 0x72,
+ OPC2_32_RR_LT_HU = 0x73,
+ OPC2_32_RR_LT_W = 0x92,
+ OPC2_32_RR_LT_WU = 0x93,
+ OPC2_32_RR_MAX = 0x1a,
+ OPC2_32_RR_MAX_U = 0x1b,
+ OPC2_32_RR_MAX_B = 0x5a,
+ OPC2_32_RR_MAX_BU = 0x5b,
+ OPC2_32_RR_MAX_H = 0x7a,
+ OPC2_32_RR_MAX_HU = 0x7b,
+ OPC2_32_RR_MIN = 0x19,
+ OPC2_32_RR_MIN_U = 0x18,
+ OPC2_32_RR_MIN_B = 0x58,
+ OPC2_32_RR_MIN_BU = 0x59,
+ OPC2_32_RR_MIN_H = 0x78,
+ OPC2_32_RR_MIN_HU = 0x79,
+ OPC2_32_RR_MOV = 0x1f,
+ OPC2_32_RR_NE = 0x11,
+ OPC2_32_RR_OR_EQ = 0x27,
+ OPC2_32_RR_OR_GE = 0x2b,
+ OPC2_32_RR_OR_GE_U = 0x2c,
+ OPC2_32_RR_OR_LT = 0x29,
+ OPC2_32_RR_OR_LT_U = 0x2a,
+ OPC2_32_RR_OR_NE = 0x28,
+ OPC2_32_RR_SAT_B = 0x5e,
+ OPC2_32_RR_SAT_BU = 0x5f,
+ OPC2_32_RR_SAT_H = 0x7e,
+ OPC2_32_RR_SAT_HU = 0x7f,
+ OPC2_32_RR_SH_EQ = 0x37,
+ OPC2_32_RR_SH_GE = 0x3b,
+ OPC2_32_RR_SH_GE_U = 0x3c,
+ OPC2_32_RR_SH_LT = 0x39,
+ OPC2_32_RR_SH_LT_U = 0x3a,
+ OPC2_32_RR_SH_NE = 0x38,
+ OPC2_32_RR_SUB = 0x08,
+ OPC2_32_RR_SUB_B = 0x48,
+ OPC2_32_RR_SUB_H = 0x68,
+ OPC2_32_RR_SUBC = 0x0d,
+ OPC2_32_RR_SUBS = 0x0a,
+ OPC2_32_RR_SUBS_U = 0x0b,
+ OPC2_32_RR_SUBS_H = 0x6a,
+ OPC2_32_RR_SUBS_HU = 0x6b,
+ OPC2_32_RR_SUBX = 0x0c,
+ OPC2_32_RR_XOR_EQ = 0x2f,
+ OPC2_32_RR_XOR_GE = 0x33,
+ OPC2_32_RR_XOR_GE_U = 0x34,
+ OPC2_32_RR_XOR_LT = 0x31,
+ OPC2_32_RR_XOR_LT_U = 0x32,
+ OPC2_32_RR_XOR_NE = 0x30,
+};
+/* OPCM_32_RR_ADRESS */
+enum {
+ OPC2_32_RR_ADD_A = 0x01,
+ OPC2_32_RR_ADDSC_A = 0x60,
+ OPC2_32_RR_ADDSC_AT = 0x62,
+ OPC2_32_RR_EQ_A = 0x40,
+ OPC2_32_RR_EQZ = 0x48,
+ OPC2_32_RR_GE_A = 0x43,
+ OPC2_32_RR_LT_A = 0x42,
+ OPC2_32_RR_MOV_A = 0x63,
+ OPC2_32_RR_MOV_AA = 0x00,
+ OPC2_32_RR_MOV_D = 0x4c,
+ OPC2_32_RR_NE_A = 0x41,
+ OPC2_32_RR_NEZ_A = 0x49,
+ OPC2_32_RR_SUB_A = 0x02,
+};
+/* OPCM_32_RR_FLOAT */
+enum {
+ OPC2_32_RR_BMERGE = 0x01,
+ OPC2_32_RR_BSPLIT = 0x09,
+ OPC2_32_RR_DVINIT_B = 0x5a,
+ OPC2_32_RR_DVINIT_BU = 0x4a,
+ OPC2_32_RR_DVINIT_H = 0x3a,
+ OPC2_32_RR_DVINIT_HU = 0x2a,
+ OPC2_32_RR_DVINIT = 0x1a,
+ OPC2_32_RR_DVINIT_U = 0x0a,
+ OPC2_32_RR_PARITY = 0x02,
+ OPC2_32_RR_UNPACK = 0x08,
+};
+/* OPCM_32_RR_IDIRECT */
+enum {
+ OPC2_32_RR_JI = 0x03,
+ OPC2_32_RR_JLI = 0x02,
+ OPC2_32_RR_CALLI = 0x00,
+};
+/*
+ * RR1 Format
+ */
+/* OPCM_32_RR1_MUL */
+enum {
+ OPC2_32_RR1_MUL_H_32_LL = 0x1a,
+ OPC2_32_RR1_MUL_H_32_LU = 0x19,
+ OPC2_32_RR1_MUL_H_32_UL = 0x18,
+ OPC2_32_RR1_MUL_H_32_UU = 0x1b,
+ OPC2_32_RR1_MULM_H_64_LL = 0x1e,
+ OPC2_32_RR1_MULM_H_64_LU = 0x1d,
+ OPC2_32_RR1_MULM_H_64_UL = 0x1c,
+ OPC2_32_RR1_MULM_H_64_UU = 0x1f,
+ OPC2_32_RR1_MULR_H_16_LL = 0x0e,
+ OPC2_32_RR1_MULR_H_16_LU = 0x0d,
+ OPC2_32_RR1_MULR_H_16_UL = 0x0c,
+ OPC2_32_RR1_MULR_H_16_UU = 0x0f,
+};
+/* OPCM_32_RR1_MULQ */
+enum {
+ OPC2_32_RR1_MUL_Q_32 = 0x02,
+ OPC2_32_RR1_MUL_Q_64 = 0x1b,
+ OPC2_32_RR1_MUL_Q_32_L = 0x01,
+ OPC2_32_RR1_MUL_Q_64_L = 0x19,
+ OPC2_32_RR1_MUL_Q_32_U = 0x00,
+ OPC2_32_RR1_MUL_Q_64_U = 0x18,
+ OPC2_32_RR1_MUL_Q_32_LL = 0x05,
+ OPC2_32_RR1_MUL_Q_32_UU = 0x04,
+ OPC2_32_RR1_MULR_Q_32_L = 0x07,
+ OPC2_32_RR1_MULR_Q_32_U = 0x06,
+};
+/*
+ * RR2 Format
+ */
+/* OPCM_32_RR2_MUL */
+enum {
+ OPC2_32_RR2_MUL_32 = 0x0a,
+ OPC2_32_RR2_MUL_64 = 0x6a,
+ OPC2_32_RR2_MULS_32 = 0x8a,
+ OPC2_32_RR2_MUL_U_64 = 0x68,
+ OPC2_32_RR2_MULS_U_32 = 0x88,
+};
+/*
+ * RRPW Format
+ */
+/* OPCM_32_RRPW_EXTRACT_INSERT */
+enum {
+
+ OPC2_32_RRPW_EXTR = 0x02,
+ OPC2_32_RRPW_EXTR_U = 0x03,
+ OPC2_32_RRPW_IMASK = 0x01,
+ OPC2_32_RRPW_INSERT = 0x00,
+};
+/*
+ * RRR Format
+ */
+/* OPCM_32_RRR_COND_SELECT */
+enum {
+ OPC2_32_RRR_CADD = 0x00,
+ OPC2_32_RRR_CADDN = 0x01,
+ OPC2_32_RRR_CSUB = 0x02,
+ OPC2_32_RRR_CSUBN = 0x03,
+ OPC2_32_RRR_SEL = 0x04,
+ OPC2_32_RRR_SELN = 0x05,
+};
+/* OPCM_32_RRR_FLOAT */
+enum {
+ OPC2_32_RRR_DVADJ = 0x0d,
+ OPC2_32_RRR_DVSTEP = 0x0f,
+ OPC2_32_RRR_DVSTEP_U = 0x0e,
+ OPC2_32_RRR_IXMAX = 0x0a,
+ OPC2_32_RRR_IXMAX_U = 0x0b,
+ OPC2_32_RRR_IXMIN = 0x08,
+ OPC2_32_RRR_IXMIN_U = 0x09,
+ OPC2_32_RRR_PACK = 0x00,
+};
+/*
+ * RRR1 Format
+ */
+/* OPCM_32_RRR1_MADD */
+enum {
+ OPC2_32_RRR1_MADD_H_LL = 0x1a,
+ OPC2_32_RRR1_MADD_H_LU = 0x19,
+ OPC2_32_RRR1_MADD_H_UL = 0x18,
+ OPC2_32_RRR1_MADD_H_UU = 0x1b,
+ OPC2_32_RRR1_MADDS_H_LL = 0x3a,
+ OPC2_32_RRR1_MADDS_H_LU = 0x39,
+ OPC2_32_RRR1_MADDS_H_UL = 0x38,
+ OPC2_32_RRR1_MADDS_H_UU = 0x3b,
+ OPC2_32_RRR1_MADDM_H_LL = 0x1e,
+ OPC2_32_RRR1_MADDM_H_LU = 0x1d,
+ OPC2_32_RRR1_MADDM_H_UL = 0x1c,
+ OPC2_32_RRR1_MADDM_H_UU = 0x1f,
+ OPC2_32_RRR1_MADDMS_H_LL = 0x3e,
+ OPC2_32_RRR1_MADDMS_H_LU = 0x3d,
+ OPC2_32_RRR1_MADDMS_H_UL = 0x3c,
+ OPC2_32_RRR1_MADDMS_H_UU = 0x3f,
+ OPC2_32_RRR1_MADDR_H_LL = 0x0e,
+ OPC2_32_RRR1_MADDR_H_LU = 0x0d,
+ OPC2_32_RRR1_MADDR_H_UL = 0x0c,
+ OPC2_32_RRR1_MADDR_H_UU = 0x0f,
+ OPC2_32_RRR1_MADDRS_H_LL = 0x2e,
+ OPC2_32_RRR1_MADDRS_H_LU = 0x2d,
+ OPC2_32_RRR1_MADDRS_H_UL = 0x2c,
+ OPC2_32_RRR1_MADDRS_H_UU = 0x2f,
+};
+/* OPCM_32_RRR1_MADDQ_H */
+enum {
+ OPC2_32_RRR1_MADD_Q_32 = 0x02,
+ OPC2_32_RRR1_MADD_Q_64 = 0x1b,
+ OPC2_32_RRR1_MADD_Q_32_L = 0x01,
+ OPC2_32_RRR1_MADD_Q_64_L = 0x19,
+ OPC2_32_RRR1_MADD_Q_32_U = 0x00,
+ OPC2_32_RRR1_MADD_Q_64_U = 0x18,
+ OPC2_32_RRR1_MADD_Q_32_LL = 0x05,
+ OPC2_32_RRR1_MADD_Q_64_LL = 0x1d,
+ OPC2_32_RRR1_MADD_Q_32_UU = 0x04,
+ OPC2_32_RRR1_MADD_Q_64_UU = 0x1c,
+ OPC2_32_RRR1_MADDS_Q_32 = 0x22,
+ OPC2_32_RRR1_MADDS_Q_64 = 0x3b,
+ OPC2_32_RRR1_MADDS_Q_32_L = 0x21,
+ OPC2_32_RRR1_MADDS_Q_64_L = 0x39,
+ OPC2_32_RRR1_MADDS_Q_32_U = 0x20,
+ OPC2_32_RRR1_MADDS_Q_64_U = 0x38,
+ OPC2_32_RRR1_MADDS_Q_32_LL = 0x25,
+ OPC2_32_RRR1_MADDS_Q_64_LL = 0x3d,
+ OPC2_32_RRR1_MADDS_Q_32_UU = 0x24,
+ OPC2_32_RRR1_MADDS_Q_64_UU = 0x3c,
+ OPC2_32_RRR1_MADDR_H_16_UL = 0x1e,
+ OPC2_32_RRR1_MADDRS_H_16_UL = 0x3e,
+ OPC2_32_RRR1_MADDR_Q_32_L = 0x07,
+ OPC2_32_RRR1_MADDR_Q_32_U = 0x06,
+ OPC2_32_RRR1_MADDRS_Q_32_LL = 0x27,
+ OPC2_32_RRR1_MADDRS_Q_32_UU = 0x26,
+};
+/* OPCM_32_RRR1_MADDSU_H */
+enum {
+ OPC2_32_RRR1_MADDSU_H_32_LL = 0x1a,
+ OPC2_32_RRR1_MADDSU_H_32_LU = 0x19,
+ OPC2_32_RRR1_MADDSU_H_32_UL = 0x18,
+ OPC2_32_RRR1_MADDSU_H_32_UU = 0x1b,
+ OPC2_32_RRR1_MADDSUS_H_32_LL = 0x3a,
+ OPC2_32_RRR1_MADDSUS_H_32_LU = 0x39,
+ OPC2_32_RRR1_MADDSUS_H_32_UL = 0x38,
+ OPC2_32_RRR1_MADDSUS_H_32_UU = 0x3b,
+ OPC2_32_RRR1_MADDSUM_H_64_LL = 0x1e,
+ OPC2_32_RRR1_MADDSUM_H_64_LU = 0x1d,
+ OPC2_32_RRR1_MADDSUM_H_64_UL = 0x1c,
+ OPC2_32_RRR1_MADDSUM_H_64_UU = 0x1f,
+ OPC2_32_RRR1_MADDSUMS_H_64_LL = 0x3e,
+ OPC2_32_RRR1_MADDSUMS_H_64_LU = 0x3d,
+ OPC2_32_RRR1_MADDSUMS_H_64_UL = 0x3c,
+ OPC2_32_RRR1_MADDSUMS_H_64_UU = 0x3f,
+ OPC2_32_RRR1_MADDSUR_H_16_LL = 0x0e,
+ OPC2_32_RRR1_MADDSUR_H_16_LU = 0x0d,
+ OPC2_32_RRR1_MADDSUR_H_16_UL = 0x0c,
+ OPC2_32_RRR1_MADDSUR_H_16_UU = 0x0f,
+ OPC2_32_RRR1_MADDSURS_H_16_LL = 0x2e,
+ OPC2_32_RRR1_MADDSURS_H_16_LU = 0x2d,
+ OPC2_32_RRR1_MADDSURS_H_16_UL = 0x2c,
+ OPC2_32_RRR1_MADDSURS_H_16_UU = 0x2f,
+};
+/* OPCM_32_RRR1_MSUB_H */
+enum {
+ OPC2_32_RRR1_MSUB_H_32_LL = 0x1a,
+ OPC2_32_RRR1_MSUB_H_32_LU = 0x19,
+ OPC2_32_RRR1_MSUB_H_32_UL = 0x18,
+ OPC2_32_RRR1_MSUB_H_32_UU = 0x1b,
+ OPC2_32_RRR1_MSUBS_H_32_LL = 0x3a,
+ OPC2_32_RRR1_MSUBS_H_32_LU = 0x39,
+ OPC2_32_RRR1_MSUBS_H_32_UL = 0x38,
+ OPC2_32_RRR1_MSUBS_H_32_UU = 0x3b,
+ OPC2_32_RRR1_MSUBM_H_64_LL = 0x1e,
+ OPC2_32_RRR1_MSUBM_H_64_LU = 0x1d,
+ OPC2_32_RRR1_MSUBM_H_64_UL = 0x1c,
+ OPC2_32_RRR1_MSUBM_H_64_UU = 0x1f,
+ OPC2_32_RRR1_MSUBMS_H_64_LL = 0x3e,
+ OPC2_32_RRR1_MSUBMS_H_64_LU = 0x3d,
+ OPC2_32_RRR1_MSUBMS_H_64_UL = 0x3c,
+ OPC2_32_RRR1_MSUBMS_H_64_UU = 0x3f,
+ OPC2_32_RRR1_MSUBR_H_16_LL = 0x0e,
+ OPC2_32_RRR1_MSUBR_H_16_LU = 0x0d,
+ OPC2_32_RRR1_MSUBR_H_16_UL = 0x0c,
+ OPC2_32_RRR1_MSUBR_H_16_UU = 0x0f,
+ OPC2_32_RRR1_MSUBRS_H_16_LL = 0x2e,
+ OPC2_32_RRR1_MSUBRS_H_16_LU = 0x2d,
+ OPC2_32_RRR1_MSUBRS_H_16_UL = 0x2c,
+ OPC2_32_RRR1_MSUBRS_H_16_UU = 0x2f,
+};
+/* OPCM_32_RRR1_MSUB_Q */
+enum {
+ OPC2_32_RRR1_MSUB_Q_32 = 0x02,
+ OPC2_32_RRR1_MSUB_Q_64 = 0x1b,
+ OPC2_32_RRR1_MSUB_Q_32_L = 0x01,
+ OPC2_32_RRR1_MSUB_Q_64_L = 0x19,
+ OPC2_32_RRR1_MSUB_Q_32_U = 0x00,
+ OPC2_32_RRR1_MSUB_Q_64_U = 0x18,
+ OPC2_32_RRR1_MSUB_Q_32_LL = 0x05,
+ OPC2_32_RRR1_MSUB_Q_64_LL = 0x1d,
+ OPC2_32_RRR1_MSUB_Q_32_UU = 0x04,
+ OPC2_32_RRR1_MSUB_Q_64_UU = 0x1c,
+ OPC2_32_RRR1_MSUBS_Q_32 = 0x22,
+ OPC2_32_RRR1_MSUBS_Q_64 = 0x3b,
+ OPC2_32_RRR1_MSUBS_Q_32_L = 0x21,
+ OPC2_32_RRR1_MSUBS_Q_64_L = 0x39,
+ OPC2_32_RRR1_MSUBS_Q_32_U = 0x20,
+ OPC2_32_RRR1_MSUBS_Q_64_U = 0x38,
+ OPC2_32_RRR1_MSUBS_Q_32_LL = 0x25,
+ OPC2_32_RRR1_MSUBS_Q_64_LL = 0x3d,
+ OPC2_32_RRR1_MSUBS_Q_32_UU = 0x24,
+ OPC2_32_RRR1_MSUBS_Q_64_UU = 0x3c,
+ OPC2_32_RRR1_MSUBR_H_32_UL = 0x1e,
+ OPC2_32_RRR1_MSUBRS_H_32_UL = 0x3e,
+ OPC2_32_RRR1_MSUBR_Q_32_LL = 0x07,
+ OPC2_32_RRR1_MSUBR_Q_32_UU = 0x06,
+ OPC2_32_RRR1_MSUBRS_Q_32_LL = 0x27,
+ OPC2_32_RRR1_MSUBRS_Q_32_UU = 0x26,
+};
+/* OPCM_32_RRR1_MSUBADS_H */
+enum {
+ OPC2_32_RRR1_MSUBAD_H_32_LL = 0x1a,
+ OPC2_32_RRR1_MSUBAD_H_32_LU = 0x19,
+ OPC2_32_RRR1_MSUBAD_H_32_UL = 0x18,
+ OPC2_32_RRR1_MSUBAD_H_32_UU = 0x1b,
+ OPC2_32_RRR1_MSUBADS_H_32_LL = 0x3a,
+ OPC2_32_RRR1_MSUBADS_H_32_LU = 0x39,
+ OPC2_32_RRR1_MSUBADS_H_32_UL = 0x38,
+ OPC2_32_RRR1_MSUBADS_H_32_UU = 0x3b,
+ OPC2_32_RRR1_MSUBADM_H_64_LL = 0x1e,
+ OPC2_32_RRR1_MSUBADM_H_64_LU = 0x1d,
+ OPC2_32_RRR1_MSUBADM_H_64_UL = 0x1c,
+ OPC2_32_RRR1_MSUBADM_H_64_UU = 0x1f,
+ OPC2_32_RRR1_MSUBADMS_H_64_LL = 0x3e,
+ OPC2_32_RRR1_MSUBADMS_H_64_LU = 0x3d,
+ OPC2_32_RRR1_MSUBADMS_H_64_UL = 0x3c,
+ OPC2_32_RRR1_MSUBADMS_H_16_UU = 0x3f,
+ OPC2_32_RRR1_MSUBADR_H_16_LL = 0x0e,
+ OPC2_32_RRR1_MSUBADR_H_16_LU = 0x0d,
+ OPC2_32_RRR1_MSUBADR_H_16_UL = 0x0c,
+ OPC2_32_RRR1_MSUBADR_H_16_UU = 0x0f,
+ OPC2_32_RRR1_MSUBADRS_H_16_LL = 0x2e,
+ OPC2_32_RRR1_MSUBADRS_H_16_LU = 0x2d,
+ OPC2_32_RRR1_MSUBADRS_H_16_UL = 0x2c,
+ OPC2_32_RRR1_MSUBADRS_H_16_UU = 0x2f,
+};
+/*
+ * RRR2 Format
+ */
+/* OPCM_32_RRR2_MADD */
+enum {
+ OPC2_32_RRR2_MADD_32 = 0x0a,
+ OPC2_32_RRR2_MADD_64 = 0x6a,
+ OPC2_32_RRR2_MADDS_32 = 0x8a,
+ OPC2_32_RRR2_MADDS_64 = 0xea,
+ OPC2_32_RRR2_MADD_U_32 = 0x68,
+ OPC2_32_RRR2_MADDS_U_32 = 0x88,
+ OPC2_32_RRR2_MADDS_U_64 = 0xe8,
+};
+/* OPCM_32_RRR2_MSUB */
+enum {
+ OPC2_32_RRR2_MSUB_32 = 0x0a,
+ OPC2_32_RRR2_MSUB_64 = 0x6a,
+ OPC2_32_RRR2_MSUBS_32 = 0x8a,
+ OPC2_32_RRR2_MSUBS_64 = 0xea,
+ OPC2_32_RRR2_MSUB_U_64 = 0x68,
+ OPC2_32_RRR2_MSUBS_U_32 = 0x88,
+ OPC2_32_RRR2_MSUBS_U_64 = 0xe8,
+};
+/*
+ * RRRR Format
+ */
+/* OPCM_32_RRRR_EXTRACT_INSERT */
+enum {
+ OPC2_32_RRRR_DEXTR = 0x04,
+ OPC2_32_RRRR_EXTR = 0x02,
+ OPC2_32_RRRR_EXTR_U = 0x03,
+ OPC2_32_RRRR_INSERT = 0x00,
+};
+/*
+ * RRRW Format
+ */
+/* OPCM_32_RRRW_EXTRACT_INSERT */
+enum {
+ OPC2_32_RRRW_EXTR = 0x02,
+ OPC2_32_RRRW_EXTR_U = 0x03,
+ OPC2_32_RRRW_IMASK = 0x01,
+ OPC2_32_RRRW_INSERT = 0x00,
+};
+/*
+ * SYS Format
+ */
+/* OPCM_32_SYS_INTERRUPTS */
+enum {
+ OPC2_32_SYS_DEBUG = 0x04,
+ OPC2_32_SYS_DISABLE = 0x0d,
+ OPC2_32_SYS_DSYNC = 0x12,
+ OPC2_32_SYS_ENABLE = 0x0c,
+ OPC2_32_SYS_ISYNC = 0x13,
+ OPC2_32_SYS_NOP = 0x00,
+ OPC2_32_SYS_RET = 0x06,
+ OPC2_32_SYS_RFE = 0x07,
+ OPC2_32_SYS_RFM = 0x05,
+ OPC2_32_SYS_RSLCX = 0x09,
+ OPC2_32_SYS_SVLCX = 0x08,
+ OPC2_32_SYS_TRAPSV = 0x15,
+ OPC2_32_SYS_TRAPV = 0x14,
+};
+
+
+
+
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 05/15] target-tricore: Add masks and opcodes for decoding
2014-07-07 18:13 ` [Qemu-devel] [PATCH 05/15] target-tricore: Add masks and opcodes for decoding Bastian Koppelmann
@ 2014-07-07 19:37 ` Richard Henderson
0 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2014-07-07 19:37 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: peter.maydell
On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> +/* This creates a mask with bits start .. end set to 1 and applies it to op */
> +#define MASK_BITS(op, start, end) (op & (((1 << (end-start+1)) - 1) << start))
This is extract32(op, (start), (end) - (start)) << (start)
Do you ever use the unshifted bits, and if so, why?
> +#define MASK_BITS_SHIFT(op, start, end) (MASK_BITS(op, start, end) >> start)
This is extract32(op, (start), (end) - (start))
I note that quite a few times within the later patch you actually sign-extend
this result, duplicating the field width all over the place. It might be
better to just use sextract32 as required in the first place to treat the
fields that ought to be sign-extended as sign-extended.
r~
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 06/15] target-tricore: Add instructions of SRC opcode format
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (4 preceding siblings ...)
2014-07-07 18:13 ` [Qemu-devel] [PATCH 05/15] target-tricore: Add masks and opcodes for decoding Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-07 20:06 ` Richard Henderson
2014-07-07 20:56 ` Max Filippov
2014-07-07 18:13 ` [Qemu-devel] [PATCH 07/15] target-tricore: Add instructions of SRR " Bastian Koppelmann
` (8 subsequent siblings)
14 siblings, 2 replies; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SRC opcode format.
Add helper for sh arithmetic carry.
Add micro-op generator functions for conditional add/sub/mov and sh.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/helper.h | 19 +++++
target-tricore/op_helper.c | 36 +++++++++
target-tricore/translate.c | 197 ++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 251 insertions(+), 1 deletion(-)
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index e69de29..acea104 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Arithmetic */
+DEF_HELPER_3(shac, i32, env, i32, i32)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 2e5981f..b9fbfad 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -20,6 +20,42 @@
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
+
+target_ulong helper_shac(CPUTRICOREState *env, target_ulong r1,
+ target_ulong r2)
+{
+ target_ulong carry_out, msk, msk_start, msk_len, cond, shift_count, ret;
+ int const6;
+ const6 = r2 & 0x3f;
+
+ if (const6 >= 0) {
+ if (const6 != 0) {
+ msk_start = 32 - const6;
+ msk_len = 31-msk_start;
+ msk = ((1 << msk_len) - 1) << msk_start;
+ carry_out = ((r1 & msk) != 0);
+ } else {
+ carry_out = 0;
+ }
+ ret = r1 << const6;
+ } else {
+ shift_count = 0 - const6;
+ cond = r1 & 0x80000000;
+ if (cond != 0) {
+ msk = (((1 << shift_count) - 1) << (32 - shift_count));
+ } else {
+ msk = 0;
+ }
+ ret = msk | (r1 >> shift_count);
+ msk = (1 << (shift_count - 1)) - 1;
+ carry_out = ((r1 & msk) != 0);
+ }
+ if (carry_out) {
+ /* TODO: carry out */
+ }
+ return ret;
+}
+
static inline void QEMU_NORETURN do_raise_exception_err(CPUTRICOREState *env,
uint32_t exception,
int error_code,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index e0de874..ad595b2 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -27,6 +27,8 @@
#include "exec/helper-gen.h"
#include "tricore-opcodes.h"
+
+static int insn_bytes;
/*
* TCG registers
*/
@@ -96,10 +98,203 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f,
}
-static int insn_bytes;
+/*
+ * Helper functions for translation
+ */
+
+static int sign_extend(uint32_t val, uint32_t width)
+{
+ int sval;
+ /* LSL. */
+ val <<= 31 - width;
+ sval = val;
+ /* ASR. */
+ sval >>= 31 - width;
+ return sval;
+}
+
+/*
+ * Functions to generate micro-ops
+ */
+/* Functions for arithmetic instructions */
+
+#define OP_COND(insn)\
+static inline void gen_cond_##insn(int cond, TCGv r1, TCGv r2, TCGv r3, \
+ TCGv r4) \
+{ \
+ int label = gen_new_label(); \
+ int label2 = gen_new_label(); \
+ \
+ tcg_gen_brcondi_tl(cond, r4, 0, label); \
+ tcg_gen_mov_tl(r3, r1); \
+ tcg_gen_br(label2); \
+ gen_set_label(label); \
+ tcg_gen_##insn ## _tl(r3, r1, r2); \
+ gen_set_label(label2); \
+} \
+ \
+static inline void gen_condi_##insn(int cond, TCGv r1, int32_t r2, \
+ TCGv r3, TCGv r4) \
+{ \
+ TCGv temp = tcg_const_i32(r2); \
+ gen_cond_##insn(cond, r1, temp, r3, r4); \
+ tcg_temp_free(temp); \
+}
+
+
+static inline void gen_cond_mov(int cond, TCGv r1, TCGv r2, TCGv r3,
+ TCGv r4)
+{
+ int label = gen_new_label();
+ int label2 = gen_new_label();
+
+ tcg_gen_brcondi_tl(cond, r4, 0, label);
+ tcg_gen_mov_tl(r3, r1);
+ tcg_gen_br(label2);
+ gen_set_label(label);
+ tcg_gen_mov_tl(r3, r2);
+ gen_set_label(label2);
+}
+
+static inline void gen_condi_mov(int cond, TCGv r1, int32_t r2, TCGv r3,
+ TCGv r4)
+{
+ TCGv temp = tcg_const_i32(r2);
+ gen_cond_mov(cond, r1, temp , r3, r4);
+ tcg_temp_free(temp);
+}
+OP_COND(add)
+OP_COND(sub)
+
+static void gen_sh(TCGv ret, TCGv r1, TCGv r2)
+{
+ int label, label2;
+ label = gen_new_label();
+ label2 = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_GE, r2, 0, label);
+ /* r1 >>(-r2) */
+ tcg_gen_shr_tl(ret, r1, r2);
+ tcg_gen_brcond_tl(TCG_COND_EQ, r2, r2, label2);
+ gen_set_label(label);
+ /* r1 << r2 */
+ tcg_gen_shl_tl(ret, r1, r2);
+ gen_set_label(label2);
+}
+
+static void gen_shi(TCGv ret, TCGv r1, int32_t r2)
+{
+ TCGv temp = tcg_const_i32(r2);
+ gen_sh(ret, r1, temp);
+ tcg_temp_free(temp);
+}
+
+static void gen_shac(TCGv ret, TCGv r1, TCGv r2)
+{
+ gen_helper_shac(ret, cpu_env, r1, r2);
+}
+
+static void gen_shaci(TCGv ret, TCGv r1, int32_t con)
+{
+ TCGv temp = tcg_const_i32(con);
+
+ gen_shac(ret, r1, temp);
+
+ tcg_temp_free(temp);
+}
+
+/*
+ * Functions for decoding instructions
+ */
static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
{
+ target_ulong op1;
+ int r1;
+ uint16_t const16;
+ op1 = MASK_OP_MAJOR(ctx->opcode);
+
+ switch (op1) {
+
+ case OPC1_16_SRC_ADD:
+ const16 = sign_extend(MASK_OP_SRC_CONST4(ctx->opcode), 3);
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], const16);
+ break;
+ case OPC1_16_SRC_ADD_A15:
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ const16 = MASK_OP_SRC_CONST4(ctx->opcode);
+ tcg_gen_addi_tl(cpu_gpr_d[15], cpu_gpr_d[r1],
+ sign_extend(const16, 3));
+ break;
+ case OPC1_16_SRC_ADD_15A:
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ const16 = MASK_OP_SRC_CONST4(ctx->opcode);
+ tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[15],
+ sign_extend(const16, 3));
+ break;
+ case OPC1_16_SRC_ADD_A:
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ const16 = sign_extend(MASK_OP_SRC_CONST4(ctx->opcode), 3);
+ tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const16);
+ break;
+ case OPC1_16_SRC_CADD:
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ const16 = sign_extend(MASK_OP_SRC_CONST4(ctx->opcode), 3);
+ gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const16, cpu_gpr_d[r1],
+ cpu_gpr_d[15]);
+ break;
+ case OPC1_16_SRC_CADDN:
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ const16 = sign_extend(MASK_OP_SRC_CONST4(ctx->opcode), 3);
+ gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const16, cpu_gpr_d[r1],
+ cpu_gpr_d[15]);
+ break;
+ case OPC1_16_SRC_CMOV:
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ const16 = sign_extend(MASK_OP_SRC_CONST4(ctx->opcode), 3);
+ gen_condi_mov(TCG_COND_EQ, cpu_gpr_d[r1], const16, cpu_gpr_d[r1],
+ cpu_gpr_d[15]);
+ break;
+ case OPC1_16_SRC_CMOVN:
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ const16 = sign_extend(MASK_OP_SRC_CONST4(ctx->opcode), 3);
+ gen_condi_mov(TCG_COND_NE, cpu_gpr_d[r1], const16, cpu_gpr_d[r1],
+ cpu_gpr_d[15]);
+ break;
+ case OPC1_16_SRC_EQ:
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ const16 = sign_extend(MASK_OP_SRC_CONST4(ctx->opcode), 3);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
+ const16);
+ break;
+ case OPC1_16_SRC_LT:
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ const16 = sign_extend(MASK_OP_SRC_CONST4(ctx->opcode), 3);
+ tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
+ const16);
+ break;
+ case OPC1_16_SRC_MOV:
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ const16 = MASK_OP_SRC_CONST4(ctx->opcode);
+ tcg_gen_movi_tl(cpu_gpr_d[r1], const16);
+ break;
+ case OPC1_16_SRC_MOV_A:
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ const16 = MASK_OP_SRC_CONST4(ctx->opcode);
+ tcg_gen_movi_tl(cpu_gpr_a[r1], const16);
+ break;
+ case OPC1_16_SRC_SH:
+ const16 = sign_extend(MASK_OP_SRC_CONST4(ctx->opcode), 3);
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const16);
+ break;
+ case OPC1_16_SRC_SHA:
+ r1 = MASK_OP_SRC_S1D(ctx->opcode);
+ const16 = MASK_OP_SRC_CONST4(ctx->opcode);
+ /* FIXME: const too long */
+ gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const16 & 0x1f);
+ break;
+ }
}
static void decode_32Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 06/15] target-tricore: Add instructions of SRC opcode format
2014-07-07 18:13 ` [Qemu-devel] [PATCH 06/15] target-tricore: Add instructions of SRC opcode format Bastian Koppelmann
@ 2014-07-07 20:06 ` Richard Henderson
2014-07-07 20:56 ` Max Filippov
1 sibling, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2014-07-07 20:06 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: peter.maydell
On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> +target_ulong helper_shac(CPUTRICOREState *env, target_ulong r1,
> + target_ulong r2)
Align the r2 argument properly.
> + shift_count = 0 - const6;
> + cond = r1 & 0x80000000;
> + if (cond != 0) {
> + msk = (((1 << shift_count) - 1) << (32 - shift_count));
> + } else {
> + msk = 0;
> + }
> + ret = msk | (r1 >> shift_count);
Surely using a normal signed right shift is easier here.
> +static int sign_extend(uint32_t val, uint32_t width)
> +{
> + int sval;
> + /* LSL. */
> + val <<= 31 - width;
> + sval = val;
> + /* ASR. */
> + sval >>= 31 - width;
> + return sval;
> +}
This is sextract32.
> +#define OP_COND(insn)\
> +static inline void gen_cond_##insn(int cond, TCGv r1, TCGv r2, TCGv r3, \
> + TCGv r4) \
> +{ \
> + int label = gen_new_label(); \
> + int label2 = gen_new_label(); \
> + \
> + tcg_gen_brcondi_tl(cond, r4, 0, label); \
> + tcg_gen_mov_tl(r3, r1); \
> + tcg_gen_br(label2); \
> + gen_set_label(label); \
> + tcg_gen_##insn ## _tl(r3, r1, r2); \
> + gen_set_label(label2); \
> +} \
Use tcg_gen_movcond_tl with the "insn" computation into a temporary.
> +static inline void gen_cond_mov(int cond, TCGv r1, TCGv r2, TCGv r3,
> + TCGv r4)
> +{
> + int label = gen_new_label();
> + int label2 = gen_new_label();
> +
> + tcg_gen_brcondi_tl(cond, r4, 0, label);
> + tcg_gen_mov_tl(r3, r1);
> + tcg_gen_br(label2);
> + gen_set_label(label);
> + tcg_gen_mov_tl(r3, r2);
> + gen_set_label(label2);
> +}
Use movcond.
> +static void gen_sh(TCGv ret, TCGv r1, TCGv r2)
> +{
> + int label, label2;
> + label = gen_new_label();
> + label2 = gen_new_label();
> + tcg_gen_brcondi_tl(TCG_COND_GE, r2, 0, label);
> + /* r1 >>(-r2) */
> + tcg_gen_shr_tl(ret, r1, r2);
> + tcg_gen_brcond_tl(TCG_COND_EQ, r2, r2, label2);
> + gen_set_label(label);
> + /* r1 << r2 */
> + tcg_gen_shl_tl(ret, r1, r2);
> + gen_set_label(label2);
The r2==r2 brcond is just silly. There's br (no cond) for that.
The branches are going to break most of the code that uses this, since TCG
temporaries not allocated with _local are discarded. And TCG temporaries
allocated *with* _local are more expensive, and thus best avoided when possible.
You'll be best off performing both shifts unconditionally and selecting the
correct result with movcond.
I do not see code to handle extracting the relevant bits from 0:5, nor perform
the required negation, nor handle the special case of -32 (resulting in zero),
nor are you examining the correct bit for the sign.
Note that the case of shift-by-32-equals-zero case can be handled easily, since
the 2's compliment negation is 1's compliment + 1. Thus the whole operation
can be implemented like
count = r2 & 31;
lret = r1 << count;
count = count ^ 31; /* one's complement of the field */
rret = r1 >> count; /* shr by count ... */
rret = r1 >> 1; /* ... + 1 */
neg = r2 & 32;
ret = neg ? rret : lret;
> +static void gen_shi(TCGv ret, TCGv r1, int32_t r2)
> +{
> + TCGv temp = tcg_const_i32(r2);
> + gen_sh(ret, r1, temp);
> + tcg_temp_free(temp);
> +}
You'd do well to examine the contents of the immediate here, performing the
checks at compile time that you'd perform at runtime in the fully variable
function above. While the TCG optimizer might be able to clean up the code,
shifts are common enough that it's worth the effort to do the right thing in
the first place.
> + case OPC1_16_SRC_ADD:
> + const16 = sign_extend(MASK_OP_SRC_CONST4(ctx->opcode), 3);
> + r1 = MASK_OP_SRC_S1D(ctx->opcode);
Surely this function can be improved by hoisting this computation. It's
identical for every entry, since they're all the same insn format. Note that
you can afford to compute both const16 and r2 at the top, even though only one
or the other will be used.
r~
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 06/15] target-tricore: Add instructions of SRC opcode format
2014-07-07 18:13 ` [Qemu-devel] [PATCH 06/15] target-tricore: Add instructions of SRC opcode format Bastian Koppelmann
2014-07-07 20:06 ` Richard Henderson
@ 2014-07-07 20:56 ` Max Filippov
1 sibling, 0 replies; 33+ messages in thread
From: Max Filippov @ 2014-07-07 20:56 UTC (permalink / raw)
To: Bastian Koppelmann; +Cc: Peter Maydell, qemu-devel, Richard Henderson
Hi Bastian,
On Mon, Jul 7, 2014 at 10:13 PM, Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
> Add instructions of SRC opcode format.
> Add helper for sh arithmetic carry.
> Add micro-op generator functions for conditional add/sub/mov and sh.
>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
> target-tricore/helper.h | 19 +++++
> target-tricore/op_helper.c | 36 +++++++++
> target-tricore/translate.c | 197 ++++++++++++++++++++++++++++++++++++++++++++-
> 3 files changed, 251 insertions(+), 1 deletion(-)
>
> diff --git a/target-tricore/helper.h b/target-tricore/helper.h
> index e69de29..acea104 100644
> --- a/target-tricore/helper.h
> +++ b/target-tricore/helper.h
[...]
> +target_ulong helper_shac(CPUTRICOREState *env, target_ulong r1,
> + target_ulong r2)
> +{
> + target_ulong carry_out, msk, msk_start, msk_len, cond, shift_count, ret;
> + int const6;
> + const6 = r2 & 0x3f;
> +
> + if (const6 >= 0) {
There's no way const6 may be negative here, if you meant 'negative 6-bit-wide
signed integer' then you need to change the way you calculate const6 to e.g.
const6 = sextract32(r2, 0, 6);
--
Thanks.
-- Max
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 07/15] target-tricore: Add instructions of SRR opcode format
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (5 preceding siblings ...)
2014-07-07 18:13 ` [Qemu-devel] [PATCH 06/15] target-tricore: Add instructions of SRC opcode format Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-07 20:17 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 08/15] target-tricore: Add instructions of SSR " Bastian Koppelmann
` (7 subsequent siblings)
14 siblings, 1 reply; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SRR opcode format.
Add micro-op generator function for ssov.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/translate.c | 140 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 139 insertions(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index ad595b2..108619c 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -203,14 +203,34 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t con)
tcg_temp_free(temp);
}
+static inline void gen_ssov(TCGv ret, TCGv arg, int32_t cons)
+{
+ int l1 = gen_new_label();
+ TCGv temp = tcg_temp_local_new();
+ int32_t max_pos = (0x1u << (cons - 1)) - 1;
+ int32_t max_neg = -(0x1u << (cons - 1));
+
+ tcg_gen_movi_tl(temp, max_pos);
+ tcg_gen_brcondi_tl(TCG_COND_GT, arg, max_pos, l1);
+ tcg_gen_movi_tl(temp, max_neg);
+ tcg_gen_brcondi_tl(TCG_COND_LT, arg, max_neg, l1);
+ tcg_gen_mov_tl(temp, arg);
+ gen_set_label(l1);
+ tcg_gen_mov_tl(ret, temp);
+
+ tcg_temp_free(temp);
+}
+
/*
* Functions for decoding instructions
*/
static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
{
target_ulong op1;
- int r1;
+ int r1, r2;
uint16_t const16;
+ TCGv temp;
+
op1 = MASK_OP_MAJOR(ctx->opcode);
switch (op1) {
@@ -294,6 +314,124 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
/* FIXME: const too long */
gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const16 & 0x1f);
break;
+/* SRR-Format */
+ case OPC1_16_SRR_ADD:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_add_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_ADD_A15:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_add_tl(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_ADD_15A:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_add_tl(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_ADD_A:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
+ break;
+ case OPC1_16_SRR_ADDS:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+
+ temp = tcg_temp_local_new();
+ tcg_gen_add_tl(temp, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ gen_ssov(cpu_gpr_d[r1], temp, 32);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SRR_AND:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_CMOV:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ gen_cond_mov(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
+ cpu_gpr_d[r1], cpu_gpr_d[15]);
+ break;
+ case OPC1_16_SRR_CMOVN:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ gen_cond_mov(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
+ cpu_gpr_d[r1], cpu_gpr_d[15]);
+ break;
+ case OPC1_16_SRR_EQ:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
+ cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_LT:
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
+ cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_MOV:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_MOV_A:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_MOV_AA:
+ r1 = MASK_OP_SRR_S2(ctx->opcode);
+ r2 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_mov_tl(cpu_gpr_a[r2], cpu_gpr_a[r1]);
+ break;
+ case OPC1_16_SRR_MOV_D:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
+ break;
+ case OPC1_16_SRR_MUL:
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ tcg_gen_mul_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_OR:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_SUB:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_sub_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_SUB_A15B:
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ tcg_gen_sub_tl(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_SUB_15AB:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_sub_tl(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_SUBS:
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ temp = tcg_temp_local_new();
+ tcg_gen_sub_tl(temp, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ gen_ssov(cpu_gpr_d[r1], temp, 32);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SRR_XOR:
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
}
}
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 07/15] target-tricore: Add instructions of SRR opcode format
2014-07-07 18:13 ` [Qemu-devel] [PATCH 07/15] target-tricore: Add instructions of SRR " Bastian Koppelmann
@ 2014-07-07 20:17 ` Richard Henderson
0 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2014-07-07 20:17 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: peter.maydell
On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> Add instructions of SRR opcode format.
> Add micro-op generator function for ssov.
>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
> target-tricore/translate.c | 140 ++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 139 insertions(+), 1 deletion(-)
>
> diff --git a/target-tricore/translate.c b/target-tricore/translate.c
> index ad595b2..108619c 100644
> --- a/target-tricore/translate.c
> +++ b/target-tricore/translate.c
> @@ -203,14 +203,34 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t con)
> tcg_temp_free(temp);
> }
>
> +static inline void gen_ssov(TCGv ret, TCGv arg, int32_t cons)
> +{
> + int l1 = gen_new_label();
> + TCGv temp = tcg_temp_local_new();
> + int32_t max_pos = (0x1u << (cons - 1)) - 1;
> + int32_t max_neg = -(0x1u << (cons - 1));
> +
> + tcg_gen_movi_tl(temp, max_pos);
> + tcg_gen_brcondi_tl(TCG_COND_GT, arg, max_pos, l1);
> + tcg_gen_movi_tl(temp, max_neg);
> + tcg_gen_brcondi_tl(TCG_COND_LT, arg, max_neg, l1);
> + tcg_gen_mov_tl(temp, arg);
> + gen_set_label(l1);
> + tcg_gen_mov_tl(ret, temp);
> +
> + tcg_temp_free(temp);
> +}
Movcond, but...
> + case OPC1_16_SRR_ADDS:
> + r2 = MASK_OP_SRR_S2(ctx->opcode);
> + r1 = MASK_OP_SRR_S1D(ctx->opcode);
> +
> + temp = tcg_temp_local_new();
> + tcg_gen_add_tl(temp, cpu_gpr_d[r1], cpu_gpr_d[r2]);
> + gen_ssov(cpu_gpr_d[r1], temp, 32);
> + tcg_temp_free(temp);
> + break;
... you can't detect 32-bit overflow this way. One has to use 33-bit (or more)
arithmetic to perform the comparisons that you use here.
There are several ways this could be open-coded in TCG, but I'd be surprised if
this insn is used often enough to be worth it. It'll be simpler and easier to
just use a helper function.
> + case OPC1_16_SRR_SUBS:
Likewise.
r~
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 08/15] target-tricore: Add instructions of SSR opcode format
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (6 preceding siblings ...)
2014-07-07 18:13 ` [Qemu-devel] [PATCH 07/15] target-tricore: Add instructions of SRR " Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-07 20:22 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 09/15] target-tricore: Add instructions of SRRS and SLRO " Bastian Koppelmann
` (6 subsequent siblings)
14 siblings, 1 reply; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/translate.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 108619c..7553870 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -432,6 +432,63 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
r2 = MASK_OP_SRR_S2(ctx->opcode);
tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
+/* SSR-format */
+ case OPC1_16_SSR_ST_A:
+ r1 = MASK_OP_SSR_S1(ctx->opcode);
+ r2 = MASK_OP_SSR_S2(ctx->opcode);
+ tcg_gen_qemu_st32(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ break;
+ case OPC1_16_SSR_ST_A_POSTINC:
+ r1 = MASK_OP_SSR_S1(ctx->opcode);
+ r2 = MASK_OP_SSR_S2(ctx->opcode);
+ tcg_gen_qemu_st32(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+ break;
+ case OPC1_16_SSR_ST_B:
+ r1 = MASK_OP_SSR_S1(ctx->opcode);
+ r2 = MASK_OP_SSR_S2(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff);
+ tcg_gen_qemu_st8(temp, cpu_gpr_a[r2], ctx->mem_idx);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SSR_ST_B_POSTINC:
+ r1 = MASK_OP_SSR_S1(ctx->opcode);
+ r2 = MASK_OP_SSR_S2(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff);
+ tcg_gen_qemu_st8(temp, cpu_gpr_a[r2], ctx->mem_idx);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SSR_ST_H:
+ r1 = MASK_OP_SSR_S1(ctx->opcode);
+ r2 = MASK_OP_SSR_S2(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xffff);
+ tcg_gen_qemu_st16(temp, cpu_gpr_a[r2], ctx->mem_idx);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SSR_ST_H_POSTINC:
+ r1 = MASK_OP_SSR_S1(ctx->opcode);
+ r2 = MASK_OP_SSR_S2(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xffff);
+ tcg_gen_qemu_st16(temp, cpu_gpr_a[r2], ctx->mem_idx);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SSR_ST_W:
+ r2 = MASK_OP_SSR_S2(ctx->opcode);
+ r1 = MASK_OP_SSR_S1(ctx->opcode);
+ tcg_gen_qemu_st32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ break;
+ case OPC1_16_SSR_ST_W_POSTINC:
+ r2 = MASK_OP_SSR_S2(ctx->opcode);
+ r1 = MASK_OP_SSR_S1(ctx->opcode);
+ tcg_gen_qemu_st32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+ break;
}
}
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 08/15] target-tricore: Add instructions of SSR opcode format
2014-07-07 18:13 ` [Qemu-devel] [PATCH 08/15] target-tricore: Add instructions of SSR " Bastian Koppelmann
@ 2014-07-07 20:22 ` Richard Henderson
0 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2014-07-07 20:22 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: peter.maydell
On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> + case OPC1_16_SSR_ST_B:
> + r1 = MASK_OP_SSR_S1(ctx->opcode);
> + r2 = MASK_OP_SSR_S2(ctx->opcode);
> + temp = tcg_temp_new();
> + tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff);
> + tcg_gen_qemu_st8(temp, cpu_gpr_a[r2], ctx->mem_idx);
> + tcg_temp_free(temp);
The andi is just silly. Of course the st8 will only examine the low 8 bits.
Likewise for the _H insns.
r~
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 09/15] target-tricore: Add instructions of SRRS and SLRO opcode format.
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (7 preceding siblings ...)
2014-07-07 18:13 ` [Qemu-devel] [PATCH 08/15] target-tricore: Add instructions of SSR " Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-07 20:30 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 10/15] target-tricore: Add instructions of SB " Bastian Koppelmann
` (5 subsequent siblings)
14 siblings, 1 reply; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for indirect loads.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/translate.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 7553870..39f29bb 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -116,6 +116,26 @@ static int sign_extend(uint32_t val, uint32_t width)
/*
* Functions to generate micro-ops
*/
+
+/* Functions for load/save to/from memory */
+#define OP_MEM_INDIRECT(insn) \
+static inline void gen_indirect_##insn(DisasContext *ctx, TCGv r1, TCGv r2, \
+ int16_t con) \
+{ \
+ TCGv temp = tcg_temp_new(); \
+ TCGv tempPC = tcg_const_i32(ctx->pc); \
+ tcg_gen_addi_tl(temp, r2, con); \
+ tcg_gen_qemu_##insn(r1, temp, ctx->mem_idx); \
+ tcg_temp_free(tempPC); \
+ tcg_temp_free(temp); \
+}
+OP_MEM_INDIRECT(ld8s)
+OP_MEM_INDIRECT(ld8u)
+OP_MEM_INDIRECT(ld16s)
+OP_MEM_INDIRECT(ld16u)
+OP_MEM_INDIRECT(ld32s)
+OP_MEM_INDIRECT(ld32u)
+
/* Functions for arithmetic instructions */
#define OP_COND(insn)\
@@ -489,6 +509,38 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
tcg_gen_qemu_st32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
break;
+/* SRRS-format */
+ case OPC1_16_SRRS_ADDSC_A:
+ r2 = MASK_OP_SRRS_S2(ctx->opcode);
+ r1 = MASK_OP_SRRS_S1D(ctx->opcode);
+ const16 = MASK_OP_SRRS_N(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
+ tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
+
+ tcg_temp_free(temp);
+ break;
+/* SLRO-format */
+ case OPC1_16_SLRO_LD_A:
+ r1 = MASK_OP_SLRO_D(ctx->opcode);
+ const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+ gen_indirect_ld32s(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4);
+ break;
+ case OPC1_16_SLRO_LD_BU:
+ r1 = MASK_OP_SLRO_D(ctx->opcode);
+ const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+ gen_indirect_ld8u(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16);
+ break;
+ case OPC1_16_SLRO_LD_H:
+ r1 = MASK_OP_SLRO_D(ctx->opcode);
+ const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+ gen_indirect_ld16s(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2);
+ break;
+ case OPC1_16_SLRO_LD_W:
+ r1 = MASK_OP_SLRO_D(ctx->opcode);
+ const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
+ gen_indirect_ld32s(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4);
+ break;
}
}
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 09/15] target-tricore: Add instructions of SRRS and SLRO opcode format.
2014-07-07 18:13 ` [Qemu-devel] [PATCH 09/15] target-tricore: Add instructions of SRRS and SLRO " Bastian Koppelmann
@ 2014-07-07 20:30 ` Richard Henderson
0 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2014-07-07 20:30 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: peter.maydell
On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> +/* Functions for load/save to/from memory */
> +#define OP_MEM_INDIRECT(insn) \
> +static inline void gen_indirect_##insn(DisasContext *ctx, TCGv r1, TCGv r2, \
> + int16_t con) \
> +{ \
> + TCGv temp = tcg_temp_new(); \
> + TCGv tempPC = tcg_const_i32(ctx->pc); \
> + tcg_gen_addi_tl(temp, r2, con); \
> + tcg_gen_qemu_##insn(r1, temp, ctx->mem_idx); \
> + tcg_temp_free(tempPC); \
> + tcg_temp_free(temp); \
> +}
> +OP_MEM_INDIRECT(ld8s)
> +OP_MEM_INDIRECT(ld8u)
> +OP_MEM_INDIRECT(ld16s)
> +OP_MEM_INDIRECT(ld16u)
> +OP_MEM_INDIRECT(ld32s)
> +OP_MEM_INDIRECT(ld32u)
Please just rearrange all of your memory operations to use the new TCGMemOp
enumeration and the common tcg_gen_qemu_{ld,st}_tl functions.
I nearly suggested that for patch 8, but it's quite obvious here.
tempPC is unused here.
Why call this "indirect"? A better term would be "offset".
r~
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 10/15] target-tricore: Add instructions of SB opcode format
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (8 preceding siblings ...)
2014-07-07 18:13 ` [Qemu-devel] [PATCH 09/15] target-tricore: Add instructions of SRRS and SLRO " Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-08 4:41 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 11/15] target-tricore: Add instructions of SBC and SBRN " Bastian Koppelmann
` (4 subsequent siblings)
14 siblings, 1 reply; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/helper.h | 5 ++
target-tricore/op_helper.c | 192 +++++++++++++++++++++++++++++++++++++++++++++
target-tricore/translate.c | 85 ++++++++++++++++++++
3 files changed, 282 insertions(+)
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index acea104..0d79d1d 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -17,3 +17,8 @@
/* Arithmetic */
DEF_HELPER_3(shac, i32, env, i32, i32)
+
+/* CSA */
+DEF_HELPER_3(call, void, env, i32, i32)
+DEF_HELPER_1(ret, void, env)
+
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index b9fbfad..5267fd0 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -56,6 +56,198 @@ target_ulong helper_shac(CPUTRICOREState *env, target_ulong r1,
return ret;
}
+/* context save area (CSA) related helpers */
+
+enum {
+ CONTEXT_LOWER = 0,
+ CONTEXT_UPPER = 1,
+};
+
+static int cdc_increment(TCState *tc)
+{
+ tc->PSW++;
+ return 0;
+}
+
+static int cdc_decrement(TCState *tc)
+{
+ tc->PSW--;
+ return 0;
+}
+
+static void save_context(CPUTRICOREState *env, int ea, int ul,
+ target_ulong *new_FCX)
+{
+ *new_FCX = cpu_ldl_data(env, ea);
+ cpu_stl_data(env, ea, env->active_tc.PCXI);
+ if (ul == CONTEXT_UPPER) {
+ cpu_stl_data(env, ea+4, env->active_tc.PSW);
+ cpu_stl_data(env, ea+8, env->active_tc.gpr_a[10]);
+ cpu_stl_data(env, ea+12, env->active_tc.gpr_a[11]);
+ cpu_stl_data(env, ea+16, env->active_tc.gpr_d[8]);
+ cpu_stl_data(env, ea+20, env->active_tc.gpr_d[9]);
+ cpu_stl_data(env, ea+24, env->active_tc.gpr_d[10]);
+ cpu_stl_data(env, ea+28, env->active_tc.gpr_d[11]);
+ cpu_stl_data(env, ea+32, env->active_tc.gpr_a[12]);
+ cpu_stl_data(env, ea+36, env->active_tc.gpr_a[13]);
+ cpu_stl_data(env, ea+40, env->active_tc.gpr_a[14]);
+ cpu_stl_data(env, ea+44, env->active_tc.gpr_a[15]);
+ cpu_stl_data(env, ea+48, env->active_tc.gpr_d[12]);
+ cpu_stl_data(env, ea+52, env->active_tc.gpr_d[13]);
+ cpu_stl_data(env, ea+56, env->active_tc.gpr_d[14]);
+ cpu_stl_data(env, ea+60, env->active_tc.gpr_d[15]);
+ } else {
+ cpu_stl_data(env, ea+4, env->active_tc.gpr_a[11]);
+ cpu_stl_data(env, ea+8, env->active_tc.gpr_a[2]);
+ cpu_stl_data(env, ea+12, env->active_tc.gpr_a[3]);
+ cpu_stl_data(env, ea+16, env->active_tc.gpr_d[0]);
+ cpu_stl_data(env, ea+20, env->active_tc.gpr_d[1]);
+ cpu_stl_data(env, ea+24, env->active_tc.gpr_d[2]);
+ cpu_stl_data(env, ea+28, env->active_tc.gpr_d[3]);
+ cpu_stl_data(env, ea+32, env->active_tc.gpr_a[4]);
+ cpu_stl_data(env, ea+36, env->active_tc.gpr_a[5]);
+ cpu_stl_data(env, ea+40, env->active_tc.gpr_a[6]);
+ cpu_stl_data(env, ea+44, env->active_tc.gpr_a[7]);
+ cpu_stl_data(env, ea+48, env->active_tc.gpr_d[4]);
+ cpu_stl_data(env, ea+52, env->active_tc.gpr_d[5]);
+ cpu_stl_data(env, ea+56, env->active_tc.gpr_d[6]);
+ cpu_stl_data(env, ea+60, env->active_tc.gpr_d[7]);
+ }
+}
+
+static void restore_context(CPUTRICOREState *env, int ea, int ul,
+ target_ulong *new_PCXI, target_ulong *new_PSW)
+{
+ *new_PCXI = cpu_ldl_data(env, ea);
+ if (ul == CONTEXT_UPPER) {
+ *new_PSW = cpu_ldl_data(env, ea+4);
+ env->active_tc.gpr_a[10] = cpu_ldl_data(env, ea+8);
+ env->active_tc.gpr_a[11] = cpu_ldl_data(env, ea+12);
+ env->active_tc.gpr_d[8] = cpu_ldl_data(env, ea+16);
+ env->active_tc.gpr_d[9] = cpu_ldl_data(env, ea+20);
+ env->active_tc.gpr_d[10] = cpu_ldl_data(env, ea+24);
+ env->active_tc.gpr_d[11] = cpu_ldl_data(env, ea+28);
+ env->active_tc.gpr_a[12] = cpu_ldl_data(env, ea+32);
+ env->active_tc.gpr_a[13] = cpu_ldl_data(env, ea+36);
+ env->active_tc.gpr_a[14] = cpu_ldl_data(env, ea+40);
+ env->active_tc.gpr_a[15] = cpu_ldl_data(env, ea+44);
+ env->active_tc.gpr_d[12] = cpu_ldl_data(env, ea+48);
+ env->active_tc.gpr_d[13] = cpu_ldl_data(env, ea+52);
+ env->active_tc.gpr_d[14] = cpu_ldl_data(env, ea+56);
+ env->active_tc.gpr_d[15] = cpu_ldl_data(env, ea+60);
+ } else {
+ env->active_tc.gpr_a[11] = cpu_ldl_data(env, ea+4);
+ env->active_tc.gpr_a[2] = cpu_ldl_data(env, ea+8);
+ env->active_tc.gpr_a[3] = cpu_ldl_data(env, ea+12);
+ env->active_tc.gpr_d[0] = cpu_ldl_data(env, ea+16);
+ env->active_tc.gpr_d[1] = cpu_ldl_data(env, ea+20);
+ env->active_tc.gpr_d[2] = cpu_ldl_data(env, ea+24);
+ env->active_tc.gpr_d[3] = cpu_ldl_data(env, ea+28);
+ env->active_tc.gpr_a[4] = cpu_ldl_data(env, ea+32);
+ env->active_tc.gpr_a[5] = cpu_ldl_data(env, ea+36);
+ env->active_tc.gpr_a[6] = cpu_ldl_data(env, ea+40);
+ env->active_tc.gpr_a[7] = cpu_ldl_data(env, ea+44);
+ env->active_tc.gpr_d[4] = cpu_ldl_data(env, ea+48);
+ env->active_tc.gpr_d[5] = cpu_ldl_data(env, ea+52);
+ env->active_tc.gpr_d[6] = cpu_ldl_data(env, ea+56);
+ env->active_tc.gpr_d[7] = cpu_ldl_data(env, ea+60);
+ }
+ cpu_stl_data(env, ea, env->active_tc.FCX);
+}
+
+void helper_call(CPUTRICOREState *env, uint32_t pc,
+ uint32_t insnsize)
+{
+ target_ulong ret_address;
+ target_ulong tmp_FCX;
+ target_ulong ea;
+ target_ulong new_FCX;
+
+ /* if (FCX == 0) trap(FCU); */
+ if (env->active_tc.FCX == 0) {
+ printf("FCU trap");
+ }
+ /* if (PSW.CDE) then if (cdc_increment()) then trap(CDO); */
+ if (env->active_tc.PSW & MASK_PSW_CDE) {
+ if (cdc_increment(&(env->active_tc))) {
+ printf("CDO trap\n");
+ }
+ }
+ /* PSW.CDE = 1;*/
+ env->active_tc.PSW |= MASK_PSW_CDE;
+ /* ret_addr = PC + 4; */
+ ret_address = pc + insnsize;
+ /* tmp_FCX = FCX; */
+ tmp_FCX = env->active_tc.FCX;
+ /* EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; */
+ ea = ((env->active_tc.FCX & MASK_FCX_FCXS) << 12) +
+ ((env->active_tc.FCX & MASK_FCX_FCXO) << 6);
+ /* new_FCX = M(EA, word);
+ M(EA, 16 * word) = {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11],
+ A[12], A[13], A[14], A[15], D[12], D[13], D[14],
+ D[15]}; */
+ save_context(env, ea, 1, &new_FCX);
+
+ /* PCXI.PCPN = ICR.CCPN; */
+ env->active_tc.PCXI = (env->active_tc.PCXI & 0xffffff) +
+ ((env->active_tc.ICR & MASK_ICR_CCPN) << 24);
+ /* PCXI.PIE = ICR.IE; */
+ env->active_tc.PCXI = ((env->active_tc.PCXI & ~MASK_PCXI_PIE) +
+ ((env->active_tc.ICR & MASK_ICR_IE) << 15));
+ /* PCXI.UL = 1; */
+ env->active_tc.PCXI |= MASK_PCXI_UL;
+
+ /* PCXI[19: 0] = FCX[19: 0]; */
+ env->active_tc.PCXI = (env->active_tc.PCXI & 0xfff00000) +
+ (env->active_tc.FCX & 0xfffff);
+ /* FCX[19: 0] = new_FCX[19: 0]; */
+ env->active_tc.FCX = (env->active_tc.FCX & 0xfff00000) +
+ (new_FCX & 0xfffff);
+ /* A[11] = ret_addr[31: 0]; */
+ env->active_tc.gpr_a[11] = ret_address;
+
+ /* if (tmp_FCX == LCX) trap(FCD);*/
+ if (tmp_FCX == env->active_tc.LCX) {
+ printf("FCD trap\n");
+ }
+}
+
+void helper_ret(CPUTRICOREState *env)
+{
+ target_ulong ea;
+ target_ulong new_PCXI;
+ target_ulong new_PSW;
+ /* if (PSW.CDE) then if (cdc_decrement()) then trap(CDU);*/
+ if (env->active_tc.PSW & MASK_PSW_CDE) {
+ if (cdc_decrement(&(env->active_tc))) {
+ printf("CDU trap\n");
+ }
+ }
+ /* if (PCXI[19: 0] == 0) then trap(CSU); */
+ if ((env->active_tc.PCXI & 0xfffff) == 0) {
+ printf("CSU trap\n");
+ }
+ /* if (PCXI.UL == 0) then trap(CTYP); */
+ if ((env->active_tc.PCXI & MASK_PCXI_UL) == 0) {
+ printf("CTYP trap\n");
+ }
+ /* PC = {A11 [31: 1], 1’b0}; */
+ env->active_tc.PC = env->active_tc.gpr_a[11] & 0xfffffffe;
+
+ /* EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0}; */
+ ea = ((env->active_tc.PCXI & MASK_PCXI_PCXS) << 12) +
+ ((env->active_tc.PCXI & MASK_PCXI_PCXO) << 6);
+ /* {new_PCXI, new_PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12],
+ A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word);
+ M(EA, word) = FCX; */
+ restore_context(env, ea, CONTEXT_UPPER, &new_PCXI, &new_PSW);
+ /* FCX[19: 0] = PCXI[19: 0]; */
+ env->active_tc.FCX = (env->active_tc.FCX & 0xfff00000) +
+ (env->active_tc.PCXI & 0x000fffff);
+ /* PCXI = new_PCXI; */
+ env->active_tc.PCXI = new_PCXI;
+}
+
static inline void QEMU_NORETURN do_raise_exception_err(CPUTRICOREState *env,
uint32_t exception,
int error_code,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 39f29bb..f32e1d1 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -117,6 +117,15 @@ static int sign_extend(uint32_t val, uint32_t width)
* Functions to generate micro-ops
*/
+/* Makros for generating helpers */
+#define gen_helper_2arg(name, arg0, arg1) do { \
+ TCGv_i32 helper_tmp0 = tcg_const_i32(arg0); \
+ TCGv_i32 helper_tmp1 = tcg_const_i32(arg1); \
+ gen_helper_##name(cpu_env, helper_tmp0, helper_tmp1); \
+ tcg_temp_free_i32(helper_tmp0); \
+ tcg_temp_free_i32(helper_tmp1); \
+ } while (0)
+
/* Functions for load/save to/from memory */
#define OP_MEM_INDIRECT(insn) \
static inline void gen_indirect_##insn(DisasContext *ctx, TCGv r1, TCGv r2, \
@@ -241,6 +250,64 @@ static inline void gen_ssov(TCGv ret, TCGv arg, int32_t cons)
tcg_temp_free(temp);
}
+/* helpers for generating program flow micro-ops */
+
+static inline void gen_save_pc(target_ulong pc)
+{
+ tcg_gen_movi_tl(cpu_PC, pc);
+}
+
+static inline void gen_branch_cond(DisasContext *ctx, int cond, TCGv r1,
+ TCGv r2, int16_t address)
+{
+ int jumpLabel;
+ jumpLabel = gen_new_label();
+ tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
+
+ gen_save_pc(ctx->pc + insn_bytes);
+ tcg_gen_exit_tb(0);
+
+ gen_set_label(jumpLabel);
+ gen_save_pc(ctx->pc + address * 2);
+ tcg_gen_exit_tb(0);
+
+}
+
+static inline void gen_branch_condi(DisasContext *ctx, int cond, TCGv r1,
+ int r2, int16_t address)
+{
+ TCGv temp = tcg_const_i32(r2);
+ gen_branch_cond(ctx, cond, r1, temp, address);
+ tcg_temp_free(temp);
+}
+
+static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
+ int r1, int r2 , int32_t constant , int32_t offset)
+{
+
+ switch (opc) {
+/* SB-format jumps */
+ case OPC1_16_SB_J:
+ case OPC1_32_B_J:
+ gen_save_pc(ctx->pc+offset*2);
+ tcg_gen_exit_tb(0);
+ break;
+ case OPC1_16_SB_CALL:
+ gen_helper_2arg(call, ctx->pc, insn_bytes);
+ gen_save_pc(ctx->pc+sign_extend(offset, 7)*2);
+ tcg_gen_exit_tb(0);
+ case OPC1_16_SB_JZ:
+ gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
+ break;
+ case OPC1_16_SB_JNZ:
+ gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
+ break;
+ default:
+ printf("Branch Error at %x\n", ctx->pc);
+ }
+ ctx->bstate = BS_BRANCH;
+}
+
/*
* Functions for decoding instructions
*/
@@ -249,6 +316,7 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
target_ulong op1;
int r1, r2;
uint16_t const16;
+ int32_t address;
TCGv temp;
op1 = MASK_OP_MAJOR(ctx->opcode);
@@ -541,6 +609,23 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
gen_indirect_ld32s(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4);
break;
+/* SB-format */
+ case OPC1_16_SB_CALL:
+ address = MASK_OP_SB_DISP8(ctx->opcode);
+ gen_compute_branch(ctx, op1, 0, 0, 0, address);
+ break;
+ case OPC1_16_SB_J:
+ address = MASK_OP_SB_DISP8(ctx->opcode);
+ gen_compute_branch(ctx, op1, 0, 0, 0, address);
+ break;
+ case OPC1_16_SB_JNZ:
+ address = sign_extend(MASK_OP_SB_DISP8(ctx->opcode), 7);
+ gen_compute_branch(ctx, op1, 0, 0, 0, address);
+ break;
+ case OPC1_16_SB_JZ:
+ address = sign_extend(MASK_OP_SB_DISP8(ctx->opcode), 7);
+ gen_compute_branch(ctx, op1, 0, 0, 0, address);
+ break;
}
}
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 10/15] target-tricore: Add instructions of SB opcode format
2014-07-07 18:13 ` [Qemu-devel] [PATCH 10/15] target-tricore: Add instructions of SB " Bastian Koppelmann
@ 2014-07-08 4:41 ` Richard Henderson
0 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2014-07-08 4:41 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: peter.maydell
On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
> index b9fbfad..5267fd0 100644
> --- a/target-tricore/op_helper.c
> +++ b/target-tricore/op_helper.c
> @@ -56,6 +56,198 @@ target_ulong helper_shac(CPUTRICOREState *env, target_ulong r1,
> return ret;
> }
>
> +/* context save area (CSA) related helpers */
> +
> +enum {
> + CONTEXT_LOWER = 0,
> + CONTEXT_UPPER = 1,
> +};
> +
> +static int cdc_increment(TCState *tc)
> +{
> + tc->PSW++;
> + return 0;
> +}
> +
> +static int cdc_decrement(TCState *tc)
> +{
> + tc->PSW--;
> + return 0;
> +}
I guess these will be filled in more later?
> +static void save_context(CPUTRICOREState *env, int ea, int ul,
> + target_ulong *new_FCX)
> +{
> + *new_FCX = cpu_ldl_data(env, ea);
> + cpu_stl_data(env, ea, env->active_tc.PCXI);
> + if (ul == CONTEXT_UPPER) {
> + cpu_stl_data(env, ea+4, env->active_tc.PSW);
> + cpu_stl_data(env, ea+8, env->active_tc.gpr_a[10]);
> + cpu_stl_data(env, ea+12, env->active_tc.gpr_a[11]);
> + cpu_stl_data(env, ea+16, env->active_tc.gpr_d[8]);
> + cpu_stl_data(env, ea+20, env->active_tc.gpr_d[9]);
> + cpu_stl_data(env, ea+24, env->active_tc.gpr_d[10]);
> + cpu_stl_data(env, ea+28, env->active_tc.gpr_d[11]);
> + cpu_stl_data(env, ea+32, env->active_tc.gpr_a[12]);
> + cpu_stl_data(env, ea+36, env->active_tc.gpr_a[13]);
> + cpu_stl_data(env, ea+40, env->active_tc.gpr_a[14]);
> + cpu_stl_data(env, ea+44, env->active_tc.gpr_a[15]);
> + cpu_stl_data(env, ea+48, env->active_tc.gpr_d[12]);
> + cpu_stl_data(env, ea+52, env->active_tc.gpr_d[13]);
> + cpu_stl_data(env, ea+56, env->active_tc.gpr_d[14]);
> + cpu_stl_data(env, ea+60, env->active_tc.gpr_d[15]);
I wonder if this ought to be split into separate functions. Certainly you know
for a call that it's going to be the upper context, so why test?
> +static inline void gen_branch_cond(DisasContext *ctx, int cond, TCGv r1,
> + TCGv r2, int16_t address)
> +{
> + int jumpLabel;
> + jumpLabel = gen_new_label();
> + tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
> +
> + gen_save_pc(ctx->pc + insn_bytes);
insn_bytes should be part of ctx. Alternately, pre-compute ctx->next_pc =
ctx->pc + insn_bytes, since that appears to be more useful.
> + tcg_gen_exit_tb(0);
> +
> + gen_set_label(jumpLabel);
> + gen_save_pc(ctx->pc + address * 2);
> + tcg_gen_exit_tb(0);
> +
> +}
Watch the useless blank lines.
You'll want to emit goto_tb opcodes when appropriate. See examples in other
targets for when this is possible.
> + case OPC1_16_SB_CALL:
> + gen_helper_2arg(call, ctx->pc, insn_bytes);
> + gen_save_pc(ctx->pc+sign_extend(offset, 7)*2);
> + tcg_gen_exit_tb(0);
Why pass pc and insn_bytes to helper_call, when all that happens inside is that
they're added together? Or for that matter why pass either at all since you
could just as well emit
tcg_gen_movi_tl(cpu_gen_a[11], ctx->pc + insn_bytes);
And again you'll want to emit goto_tb if possible.
> +/* SB-format */
> + case OPC1_16_SB_CALL:
> + address = MASK_OP_SB_DISP8(ctx->opcode);
> + gen_compute_branch(ctx, op1, 0, 0, 0, address);
> + break;
> + case OPC1_16_SB_J:
> + address = MASK_OP_SB_DISP8(ctx->opcode);
> + gen_compute_branch(ctx, op1, 0, 0, 0, address);
> + break;
> + case OPC1_16_SB_JNZ:
> + address = sign_extend(MASK_OP_SB_DISP8(ctx->opcode), 7);
> + gen_compute_branch(ctx, op1, 0, 0, 0, address);
> + break;
> + case OPC1_16_SB_JZ:
> + address = sign_extend(MASK_OP_SB_DISP8(ctx->opcode), 7);
> + gen_compute_branch(ctx, op1, 0, 0, 0, address);
Surely all these should be one common call to gen_compute_branch.
r~
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 11/15] target-tricore: Add instructions of SBC and SBRN opcode format
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (9 preceding siblings ...)
2014-07-07 18:13 ` [Qemu-devel] [PATCH 10/15] target-tricore: Add instructions of SB " Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-08 4:47 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 12/15] target-tricore: Add instructions of SBR " Bastian Koppelmann
` (3 subsequent siblings)
14 siblings, 1 reply; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/translate.c | 45 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index f32e1d1..69d99d3 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -284,6 +284,7 @@ static inline void gen_branch_condi(DisasContext *ctx, int cond, TCGv r1,
static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
int r1, int r2 , int32_t constant , int32_t offset)
{
+ TCGv temp;
switch (opc) {
/* SB-format jumps */
@@ -302,6 +303,26 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
case OPC1_16_SB_JNZ:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
break;
+/* SBC-format jumps */
+ case OPC1_16_SBC_JEQ:
+ gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
+ break;
+ case OPC1_16_SBC_JNE:
+ gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
+ break;
+/* SBRN-format jumps */
+ case OPC1_16_SBRN_JZ_T:
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
+ gen_branch_condi(ctx, TCG_COND_NE, temp, 0x1 << constant, offset);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SBRN_JNZ_T:
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
+ gen_branch_condi(ctx, TCG_COND_EQ, temp, 0x1 << constant, offset);
+ tcg_temp_free(temp);
+ break;
default:
printf("Branch Error at %x\n", ctx->pc);
}
@@ -626,7 +647,29 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
address = sign_extend(MASK_OP_SB_DISP8(ctx->opcode), 7);
gen_compute_branch(ctx, op1, 0, 0, 0, address);
break;
- }
+/* SBC-format */
+ case OPC1_16_SBC_JEQ:
+ address = MASK_OP_SBC_DISP4(ctx->opcode);
+ const16 = sign_extend(MASK_OP_SBC_CONST4(ctx->opcode), 3);
+ gen_compute_branch(ctx, op1, 0, 0, const16, address);
+ break;
+ case OPC1_16_SBC_JNE:
+ address = MASK_OP_SBC_DISP4(ctx->opcode);
+ const16 = sign_extend(MASK_OP_SBC_CONST4(ctx->opcode), 3);
+ gen_compute_branch(ctx, op1, 0, 0, const16, address);
+ break;
+/* SBRN-format */
+ case OPC1_16_SBRN_JNZ_T:
+ address = MASK_OP_SBRN_DISP4(ctx->opcode);
+ const16 = MASK_OP_SBRN_N(ctx->opcode);
+ gen_compute_branch(ctx, op1, 0, 0, const16, address);
+ break;
+ case OPC1_16_SBRN_JZ_T:
+ address = MASK_OP_SBRN_DISP4(ctx->opcode);
+ const16 = MASK_OP_SBRN_N(ctx->opcode);
+ gen_compute_branch(ctx, op1, 0, 0, const16, address);
+ break;
+ }
}
static void decode_32Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 11/15] target-tricore: Add instructions of SBC and SBRN opcode format
2014-07-07 18:13 ` [Qemu-devel] [PATCH 11/15] target-tricore: Add instructions of SBC and SBRN " Bastian Koppelmann
@ 2014-07-08 4:47 ` Richard Henderson
0 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2014-07-08 4:47 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: peter.maydell
On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> +/* SBRN-format jumps */
> + case OPC1_16_SBRN_JZ_T:
> + temp = tcg_temp_new();
> + tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
> + gen_branch_condi(ctx, TCG_COND_NE, temp, 0x1 << constant, offset);
> + tcg_temp_free(temp);
> + break;
> + case OPC1_16_SBRN_JNZ_T:
> + temp = tcg_temp_new();
> + tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
> + gen_branch_condi(ctx, TCG_COND_EQ, temp, 0x1 << constant, offset);
> + tcg_temp_free(temp);
> + break;
Compare vs zero after the andi.
r~
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 12/15] target-tricore: Add instructions of SBR opcode format
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (10 preceding siblings ...)
2014-07-07 18:13 ` [Qemu-devel] [PATCH 11/15] target-tricore: Add instructions of SBC and SBRN " Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-08 5:26 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 13/15] target-tricore: Add instructions of SC " Bastian Koppelmann
` (2 subsequent siblings)
14 siblings, 1 reply; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/translate.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 69d99d3..5b11396 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -281,6 +281,22 @@ static inline void gen_branch_condi(DisasContext *ctx, int cond, TCGv r1,
tcg_temp_free(temp);
}
+static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
+{
+ int l1;
+ l1 = gen_new_label();
+
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], 0, l1);
+ gen_save_pc(ctx->pc+offset);
+ tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
+ tcg_gen_exit_tb(0);
+ gen_set_label(l1);
+ gen_save_pc(ctx->pc+insn_bytes);
+ tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
+ tcg_gen_exit_tb(0);
+}
+
+
static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
int r1, int r2 , int32_t constant , int32_t offset)
{
@@ -323,6 +339,42 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
gen_branch_condi(ctx, TCG_COND_EQ, temp, 0x1 << constant, offset);
tcg_temp_free(temp);
break;
+/* SBR-format jumps */
+ case OPC1_16_SBR_JEQ:
+ gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
+ offset);
+ break;
+ case OPC1_16_SBR_JNE:
+ gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
+ offset);
+ break;
+ case OPC1_16_SBR_JNZ:
+ gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JNZ_A:
+ gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JGEZ:
+ gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JGTZ:
+ gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JLEZ:
+ gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JLTZ:
+ gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JZ:
+ gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_JZ_A:
+ gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
+ break;
+ case OPC1_16_SBR_LOOP:
+ gen_loop(ctx, r1, 0xffffffe0+(offset<<1));
+ break;
default:
printf("Branch Error at %x\n", ctx->pc);
}
@@ -669,6 +721,23 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
const16 = MASK_OP_SBRN_N(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, const16, address);
break;
+/* SBR-format */
+ case OPC1_16_SBR_JEQ:
+ case OPC1_16_SBR_JGEZ:
+ case OPC1_16_SBR_JGTZ:
+ case OPC1_16_SBR_JLEZ:
+ case OPC1_16_SBR_JLTZ:
+ case OPC1_16_SBR_JNE:
+ case OPC1_16_SBR_JNZ:
+ case OPC1_16_SBR_JNZ_A:
+ case OPC1_16_SBR_JZ:
+ case OPC1_16_SBR_JZ_A:
+ case OPC1_16_SBR_LOOP:
+ r1 = MASK_OP_SBR_S2(ctx->opcode);
+ address = MASK_OP_SBR_DISP4(ctx->opcode);
+ gen_compute_branch(ctx, op1, r1, 0, 0, address);
+ break;
+
}
}
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 12/15] target-tricore: Add instructions of SBR opcode format
2014-07-07 18:13 ` [Qemu-devel] [PATCH 12/15] target-tricore: Add instructions of SBR " Bastian Koppelmann
@ 2014-07-08 5:26 ` Richard Henderson
0 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2014-07-08 5:26 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: peter.maydell
On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> Add instructions of SBR opcode format.
> Add gen_loop micro-op generator function.
>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
> target-tricore/translate.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 69 insertions(+)
>
> diff --git a/target-tricore/translate.c b/target-tricore/translate.c
> index 69d99d3..5b11396 100644
> --- a/target-tricore/translate.c
> +++ b/target-tricore/translate.c
> @@ -281,6 +281,22 @@ static inline void gen_branch_condi(DisasContext *ctx, int cond, TCGv r1,
> tcg_temp_free(temp);
> }
>
> +static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
> +{
> + int l1;
> + l1 = gen_new_label();
> +
> + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], 0, l1);
> + gen_save_pc(ctx->pc+offset);
> + tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
> + tcg_gen_exit_tb(0);
> + gen_set_label(l1);
> + gen_save_pc(ctx->pc+insn_bytes);
> + tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
> + tcg_gen_exit_tb(0);
Given that TCG does not register allocate over blocks, you're probably better
off subtracting first and comparing against -1, that way you don't need to keep
re-loading a[r1] from memory.
Again, goto_tb.
> + gen_loop(ctx, r1, 0xffffffe0+(offset<<1));
> + break;
I'd be happier seeing offset * 2 - 32.
r~
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 13/15] target-tricore: Add instructions of SC opcode format
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (11 preceding siblings ...)
2014-07-07 18:13 ` [Qemu-devel] [PATCH 12/15] target-tricore: Add instructions of SBR " Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-08 5:32 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 14/15] target-tricore: Add instructions of SLR, SSRO and SRO " Bastian Koppelmann
2014-07-07 18:13 ` [Qemu-devel] [PATCH 15/15] target-tricore: Add instructions of SR " Bastian Koppelmann
14 siblings, 1 reply; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SC opcode format.
Add makro to generate helper with 1 arg.
Add micro-op generator functions for indirect loads.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/helper.h | 2 +-
target-tricore/op_helper.c | 40 +++++++++++++++++++++++++++++++++++++
target-tricore/translate.c | 49 ++++++++++++++++++++++++++++++++++++++++++++--
3 files changed, 88 insertions(+), 3 deletions(-)
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 0d79d1d..8d70784 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -21,4 +21,4 @@ DEF_HELPER_3(shac, i32, env, i32, i32)
/* CSA */
DEF_HELPER_3(call, void, env, i32, i32)
DEF_HELPER_1(ret, void, env)
-
+DEF_HELPER_2(bisr, void, env, i32)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 5267fd0..499697b 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -248,6 +248,46 @@ void helper_ret(CPUTRICOREState *env)
env->active_tc.PCXI = new_PCXI;
}
+void helper_bisr(CPUTRICOREState *env, uint32_t const9)
+{
+ target_ulong tmp_FCX;
+ target_ulong ea;
+ target_ulong new_FCX;
+
+ if (env->active_tc.FCX == 0) {
+ printf("FCU trap\n");
+ }
+
+ tmp_FCX = env->active_tc.FCX;
+ ea = ((env->active_tc.FCX & 0xf0000) << 12) +
+ ((env->active_tc.FCX & 0xffff) << 6);
+
+ save_context(env, ea, 0, &new_FCX);
+
+ /* PCXI.PCPN = ICR.CCPN */
+ env->active_tc.PCXI = (env->active_tc.PCXI & 0xffffff) +
+ ((env->active_tc.ICR & MASK_ICR_CCPN) << 24);
+ /* PCXI.PIE = ICR.IE */
+ env->active_tc.PCXI = ((env->active_tc.PCXI & ~MASK_PCXI_PIE) +
+ ((env->active_tc.ICR & MASK_ICR_IE) << 15));
+ /* PCXI.UL = 0 */
+ env->active_tc.PCXI &= ~(MASK_PCXI_UL);
+ /* PCXI[19: 0] = FCX[19: 0] */
+ env->active_tc.PCXI = (env->active_tc.PCXI & 0xfff00000) +
+ (env->active_tc.FCX & 0xfffff);
+ /* FXC[19: 0] = new_FCX[19: 0] */
+ env->active_tc.FCX = (env->active_tc.FCX & 0xfff00000) +
+ (new_FCX & 0xfffff);
+ /* ICR.IE = 1 */
+ env->active_tc.ICR |= MASK_ICR_IE;
+
+ env->active_tc.ICR |= (const9 & 0xff); /* ICR.CCPN = const9[7: 0];*/
+
+ if (tmp_FCX == env->active_tc.LCX) {
+ printf("FCD trap\n");
+ }
+}
+
static inline void QEMU_NORETURN do_raise_exception_err(CPUTRICOREState *env,
uint32_t exception,
int error_code,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 5b11396..e98af65 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -118,6 +118,11 @@ static int sign_extend(uint32_t val, uint32_t width)
*/
/* Makros for generating helpers */
+#define gen_helper_1arg(name, arg) do { \
+ TCGv_i32 helper_tmp = tcg_const_i32(arg); \
+ gen_helper_##name(cpu_env, helper_tmp); \
+ tcg_temp_free_i32(helper_tmp); \
+ } while (0)
#define gen_helper_2arg(name, arg0, arg1) do { \
TCGv_i32 helper_tmp0 = tcg_const_i32(arg0); \
TCGv_i32 helper_tmp1 = tcg_const_i32(arg1); \
@@ -145,6 +150,10 @@ OP_MEM_INDIRECT(ld16u)
OP_MEM_INDIRECT(ld32s)
OP_MEM_INDIRECT(ld32u)
+OP_MEM_INDIRECT(st8)
+OP_MEM_INDIRECT(st16)
+OP_MEM_INDIRECT(st32)
+
/* Functions for arithmetic instructions */
#define OP_COND(insn)\
@@ -737,8 +746,44 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
address = MASK_OP_SBR_DISP4(ctx->opcode);
gen_compute_branch(ctx, op1, r1, 0, 0, address);
break;
-
- }
+/* SC-format */
+ case OPC1_16_SC_AND:
+ const16 = MASK_OP_SC_CONST8(ctx->opcode);
+ tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
+ break;
+ case OPC1_16_SC_BISR:
+ const16 = MASK_OP_SC_CONST8(ctx->opcode);
+ gen_helper_1arg(bisr, const16);
+ break;
+ case OPC1_16_SC_LD_A:
+ const16 = MASK_OP_SC_CONST8(ctx->opcode);
+ gen_indirect_ld32s(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4);
+ break;
+ case OPC1_16_SC_LD_W:
+ const16 = MASK_OP_SC_CONST8(ctx->opcode);
+ gen_indirect_ld32s(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4);
+ break;
+ case OPC1_16_SC_MOV:
+ const16 = MASK_OP_SC_CONST8(ctx->opcode);
+ tcg_gen_movi_tl(cpu_gpr_d[15], const16);
+ break;
+ case OPC1_16_SC_OR:
+ const16 = MASK_OP_SC_CONST8(ctx->opcode);
+ tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
+ break;
+ case OPC1_16_SC_ST_A:
+ const16 = MASK_OP_SC_CONST8(ctx->opcode);
+ gen_indirect_st32(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4);
+ break;
+ case OPC1_16_SC_ST_W:
+ const16 = MASK_OP_SC_CONST8(ctx->opcode);
+ gen_indirect_st32(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4);
+ break;
+ case OPC1_16_SC_SUB_A:
+ const16 = MASK_OP_SC_CONST8(ctx->opcode);
+ tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
+ break;
+ }
}
static void decode_32Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PATCH 14/15] target-tricore: Add instructions of SLR, SSRO and SRO opcode format
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (12 preceding siblings ...)
2014-07-07 18:13 ` [Qemu-devel] [PATCH 13/15] target-tricore: Add instructions of SC " Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-08 5:36 ` Richard Henderson
2014-07-07 18:13 ` [Qemu-devel] [PATCH 15/15] target-tricore: Add instructions of SR " Bastian Koppelmann
14 siblings, 1 reply; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/translate.c | 149 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 149 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index e98af65..628bd8b 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -783,6 +783,155 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
const16 = MASK_OP_SC_CONST8(ctx->opcode);
tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
break;
+/* SLR-format */
+ case OPC1_16_SLR_LD_A:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld32s(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ break;
+ case OPC1_16_SLR_LD_A_POSTINC:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld32s(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+ break;
+ case OPC1_16_SLR_LD_BU:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld8u(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ break;
+ case OPC1_16_SLR_LD_BU_POSTINC:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld8u(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
+ break;
+ case OPC1_16_SLR_LD_H:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld16s(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ break;
+ case OPC1_16_SLR_LD_H_POSTINC:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld16s(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
+ break;
+ case OPC1_16_SLR_LD_W:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld32s(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ break;
+ case OPC1_16_SLR_LD_W_POSTINC:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld32s(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+ break;
+/* SRO-format */
+ case OPC1_16_SRO_LD_A:
+ address = MASK_OP_SRO_OFF4(ctx->opcode);
+ r2 = MASK_OP_SRO_S2(ctx->opcode);
+ gen_indirect_ld32s(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4);
+ break;
+ case OPC1_16_SRO_LD_BU:
+ r1 = MASK_OP_SRO_S2(ctx->opcode);
+ const16 = MASK_OP_SRO_OFF4(ctx->opcode);
+ gen_indirect_ld8u(ctx, cpu_gpr_d[15], cpu_gpr_a[r1], const16);
+ break;
+ case OPC1_16_SRO_LD_H:
+ r1 = MASK_OP_SRO_S2(ctx->opcode);
+ const16 = MASK_OP_SRO_OFF4(ctx->opcode);
+ gen_indirect_ld16s(ctx, cpu_gpr_d[15], cpu_gpr_a[r1], const16);
+ break;
+ case OPC1_16_SRO_LD_W:
+ address = MASK_OP_SRO_OFF4(ctx->opcode);
+ r2 = MASK_OP_SRO_S2(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address * 4);
+ tcg_gen_qemu_ld32u(cpu_gpr_d[15], temp, ctx->mem_idx);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SRO_ST_A:
+ const16 = MASK_OP_SRO_OFF4(ctx->opcode);
+ r1 = MASK_OP_SRO_S2(ctx->opcode);
+ gen_indirect_st32(ctx, cpu_gpr_a[15], cpu_gpr_a[r1], const16 * 4);
+ break;
+ case OPC1_16_SRO_ST_B:
+ r1 = MASK_OP_SRO_S2(ctx->opcode);
+ const16 = MASK_OP_SRO_OFF4(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0xff);
+ gen_indirect_st8(ctx, temp, cpu_gpr_a[r1], const16);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SRO_ST_H:
+ r1 = MASK_OP_SRO_S2(ctx->opcode);
+ const16 = MASK_OP_SRO_OFF4(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0xffff);
+ gen_indirect_st16(ctx, temp, cpu_gpr_a[r1], const16 * 2);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SRO_ST_W:
+ r1 = MASK_OP_SRO_S2(ctx->opcode);
+ const16 = MASK_OP_SRO_OFF4(ctx->opcode);
+ gen_indirect_st32(ctx, cpu_gpr_d[15], cpu_gpr_a[r1], const16 * 4);
+ break;
+/* SSRO-format */
+ case OPC1_16_SSRO_ST_A:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ gen_indirect_st32(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4);
+ break;
+ case OPC1_16_SSRO_ST_B:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff);
+ gen_indirect_st8(ctx, temp, cpu_gpr_a[15], const16);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SSRO_ST_H:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xffff);
+ gen_indirect_st16(ctx, temp, cpu_gpr_a[15], const16 * 2);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SSRO_ST_W:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ gen_indirect_st32(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4);
+ break;
+/* SSRO-format */
+ case OPC1_16_SSRO_ST_A:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ gen_indirect_st32(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4);
+ break;
+ case OPC1_16_SSRO_ST_B:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff);
+ gen_indirect_st8(ctx, temp, cpu_gpr_a[15], const16);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SSRO_ST_H:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xffff);
+ gen_indirect_st16(ctx, temp, cpu_gpr_a[15], const16 * 2);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SSRO_ST_W:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ gen_indirect_st32(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4);
+ break;
}
}
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PATCH 15/15] target-tricore: Add instructions of SR opcode format
2014-07-07 18:13 [Qemu-devel] [PATCH 00/15] TriCore architecture guest implementation Bastian Koppelmann
` (13 preceding siblings ...)
2014-07-07 18:13 ` [Qemu-devel] [PATCH 14/15] target-tricore: Add instructions of SLR, SSRO and SRO " Bastian Koppelmann
@ 2014-07-07 18:13 ` Bastian Koppelmann
2014-07-08 5:58 ` Richard Henderson
14 siblings, 1 reply; 33+ messages in thread
From: Bastian Koppelmann @ 2014-07-07 18:13 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, rth
Add instructions of SR opcode format.
Add micro-op generator functions for saturate and rsubi.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/helper.h | 1 +
target-tricore/op_helper.c | 58 ++++++++++++++++++
target-tricore/translate.c | 144 +++++++++++++++++++++++++++++++++++++--------
3 files changed, 180 insertions(+), 23 deletions(-)
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 8d70784..3595e38 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -22,3 +22,4 @@ DEF_HELPER_3(shac, i32, env, i32, i32)
DEF_HELPER_3(call, void, env, i32, i32)
DEF_HELPER_1(ret, void, env)
DEF_HELPER_2(bisr, void, env, i32)
+DEF_HELPER_1(rfe, void, env)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 499697b..dc7b9b5 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -75,6 +75,27 @@ static int cdc_decrement(TCState *tc)
return 0;
}
+static bool cdc_zero(TCState *tc)
+{
+ int i;
+ int cdc = tc->PSW & MASK_PSW_CDC;
+ /* Returns TRUE if PSW.CDC.COUNT == 0 or if PSW.CDC ==
+ 7'b1111111, otherwise returns FALSE. */
+ if (cdc == 0x7f) {
+ return true;
+ }
+ /* find CDC.COUNT */
+ for (i = 7; i > 0; i--) {
+ if ((cdc & (1 << i)) == 0) {
+ if ((cdc & ~(0x7f << i)) == 0) {
+ return true;
+ }
+ }
+ }
+
+ return false;
+}
+
static void save_context(CPUTRICOREState *env, int ea, int ul,
target_ulong *new_FCX)
{
@@ -288,6 +309,43 @@ void helper_bisr(CPUTRICOREState *env, uint32_t const9)
}
}
+void helper_rfe(CPUTRICOREState *env)
+{
+ target_ulong ea;
+ target_ulong new_PCXI;
+ target_ulong new_PSW;
+ /* if (PCXI[19: 0] == 0) then trap(CSU); */
+ if ((env->active_tc.PCXI & 0xfffff) == 0) {
+ printf("CSU trap\n");
+ }
+ /* if (PCXI.UL == 0) then trap(CTYP); */
+ if ((env->active_tc.PCXI & MASK_PCXI_UL) == 0) {
+ printf("CTYP trap\n");
+ }
+ /* if (!cdc_zero() AND PSW.CDE) then trap(NEST); */
+ if (!cdc_zero(&env->active_tc) && (env->active_tc.PSW & MASK_PSW_CDE)) {
+ printf("MNG trap\n");
+ }
+ /* ICR.IE = PCXI.PIE; */
+ env->active_tc.ICR = (env->active_tc.ICR & ~MASK_ICR_IE) +
+ ((env->active_tc.PCXI & MASK_PCXI_PIE) >> 15);
+ /* ICR.CCPN = PCXI.PCPN; */
+ env->active_tc.ICR = (env->active_tc.ICR & ~MASK_ICR_CCPN) +
+ ((env->active_tc.PCXI & MASK_PCXI_PCPN) >> 24);
+ /*EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0};*/
+ ea = ((env->active_tc.PCXI & MASK_PCXI_PCXS) << 12) +
+ ((env->active_tc.PCXI & MASK_PCXI_PCXO) << 6);
+ /*{new_PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12],
+ A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word);
+ M(EA, word) = FCX;*/
+ restore_context(env, ea, CONTEXT_UPPER, &new_PCXI, &new_PSW);
+ /* FCX[19: 0] = PCXI[19: 0]; */
+ env->active_tc.FCX = (env->active_tc.FCX & 0xfff00000) +
+ (env->active_tc.PCXI & 0x000fffff);
+ /* PCXI = new_PCXI; */
+ env->active_tc.PCXI = new_PCXI;
+}
+
static inline void QEMU_NORETURN do_raise_exception_err(CPUTRICOREState *env,
uint32_t exception,
int error_code,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 628bd8b..44b9af6 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -156,6 +156,38 @@ OP_MEM_INDIRECT(st32)
/* Functions for arithmetic instructions */
+static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
+{
+ TCGv sat_neg = tcg_const_i32(low);
+ int l1 = gen_new_label();
+ int l2 = gen_new_label();
+
+ /* sat_neg = (arg < low ) ? low : arg; */
+ tcg_gen_brcondi_tl(TCG_COND_LT, arg, low, l1);
+ tcg_gen_mov_tl(sat_neg, arg);
+ gen_set_label(l1);
+
+ /* ret = (sat_neg > up ) ? up : sat_neg; */
+ tcg_gen_movi_tl(ret, up);
+ tcg_gen_brcondi_tl(TCG_COND_GT, sat_neg, up, l2);
+ tcg_gen_mov_tl(ret, sat_neg);
+ gen_set_label(l2);
+
+ tcg_temp_free(sat_neg);
+}
+
+static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
+{
+ int l1 = gen_new_label();
+
+ /* sat_neg = (arg > up ) ? up : arg; */
+ tcg_gen_movi_tl(ret, up);
+ tcg_gen_brcondi_tl(TCG_COND_GTU, arg, up, l1);
+ tcg_gen_mov_tl(ret, arg);
+ gen_set_label(l1);
+
+}
+
#define OP_COND(insn)\
static inline void gen_cond_##insn(int cond, TCGv r1, TCGv r2, TCGv r3, \
TCGv r4) \
@@ -205,6 +237,14 @@ static inline void gen_condi_mov(int cond, TCGv r1, int32_t r2, TCGv r3,
OP_COND(add)
OP_COND(sub)
+static void gen_rsubi(TCGv ret, int32_t cons, TCGv r2)
+{
+ TCGv temp = tcg_temp_new();
+ tcg_gen_movi_tl(temp, cons);
+ tcg_gen_sub_tl(ret, temp, r2);
+ tcg_temp_free(temp);
+}
+
static void gen_sh(TCGv ret, TCGv r1, TCGv r2)
{
int label, label2;
@@ -384,6 +424,15 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
case OPC1_16_SBR_LOOP:
gen_loop(ctx, r1, 0xffffffe0+(offset<<1));
break;
+/* SR-format jumps */
+ case OPC1_16_SR_JI:
+ tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xffffffff);
+ tcg_gen_exit_tb(0);
+ break;
+ case OPC2_16_SR_RET:
+ gen_helper_ret(cpu_env);
+ tcg_gen_exit_tb(0);
+ break;
default:
printf("Branch Error at %x\n", ctx->pc);
}
@@ -393,6 +442,63 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
/*
* Functions for decoding instructions
*/
+
+static void decode_sr_system(CPUTRICOREState *env, DisasContext *ctx)
+{
+ uint32_t op2;
+ op2 = MASK_OP_SR_OP2(ctx->opcode);
+
+ switch (op2) {
+ case OPC2_16_SR_NOP:
+ printf("NOP Instruction at %08x\n", ctx->pc);
+ ctx->bstate = BS_STOP;
+ break;
+ case OPC2_16_SR_RET:
+ gen_compute_branch(ctx, op2, 0, 0, 0, 0);
+ break;
+ case OPC2_16_SR_RFE:
+ gen_helper_rfe(cpu_env);
+ break;
+ case OPC2_16_SR_DEBUG:
+ printf("DEBUG Instruction at %08x\n", ctx->pc);
+ ctx->bstate = BS_STOP;
+ break;
+ default:
+ printf("default sr_system Instruction at %08x\n", ctx->pc);
+ }
+}
+
+static void decode_sr_accu(CPUTRICOREState *env, DisasContext *ctx)
+{
+ uint32_t op2;
+ uint32_t r1;
+
+ r1 = MASK_OP_SR_S1D(ctx->opcode);
+ op2 = MASK_OP_SR_OP2(ctx->opcode);
+
+ switch (op2) {
+
+ case OPC2_16_SR_RSUB:
+ gen_rsubi(cpu_gpr_d[r1], 0, cpu_gpr_d[r1]);
+ break;
+ case OPC2_16_SR_SAT_B:
+ gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
+ break;
+ case OPC2_16_SR_SAT_BU:
+ gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
+ break;
+ case OPC2_16_SR_SAT_H:
+ gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
+ break;
+ case OPC2_16_SR_SAT_HU:
+ gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
+ break;
+ default:
+ printf("default sr_accu Instruction at %08x\n", ctx->pc);
+ break;
+ }
+}
+
static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
{
target_ulong op1;
@@ -905,32 +1011,24 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
gen_indirect_st32(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4);
break;
-/* SSRO-format */
- case OPC1_16_SSRO_ST_A:
- r1 = MASK_OP_SSRO_S1(ctx->opcode);
- const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
- gen_indirect_st32(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4);
+/* SR-format */
+ case OPCM_16_SR_SYSTEM:
+ decode_sr_system(env, ctx);
break;
- case OPC1_16_SSRO_ST_B:
- r1 = MASK_OP_SSRO_S1(ctx->opcode);
- const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
- temp = tcg_temp_new();
- tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff);
- gen_indirect_st8(ctx, temp, cpu_gpr_a[15], const16);
- tcg_temp_free(temp);
+ case OPCM_16_SR_ACCU:
+ decode_sr_accu(env, ctx);
break;
- case OPC1_16_SSRO_ST_H:
- r1 = MASK_OP_SSRO_S1(ctx->opcode);
- const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
- temp = tcg_temp_new();
- tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xffff);
- gen_indirect_st16(ctx, temp, cpu_gpr_a[15], const16 * 2);
- tcg_temp_free(temp);
+ case OPC1_16_SR_JI:
+ r1 = MASK_OP_SR_S1D(ctx->opcode);
+ gen_compute_branch(ctx, op1, r1, 0, 0, 0);
break;
- case OPC1_16_SSRO_ST_W:
- r1 = MASK_OP_SSRO_S1(ctx->opcode);
- const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
- gen_indirect_st32(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4);
+ case OPC1_16_SR_NOT:
+ if (MASK_OP_SR_OP2(ctx->opcode) == 0x0) {
+ printf("Wrong OP2 at at %08x\n", ctx->pc);
+ break;
+ }
+ r1 = MASK_OP_SR_S1D(ctx->opcode);
+ tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
break;
}
}
--
2.0.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 15/15] target-tricore: Add instructions of SR opcode format
2014-07-07 18:13 ` [Qemu-devel] [PATCH 15/15] target-tricore: Add instructions of SR " Bastian Koppelmann
@ 2014-07-08 5:58 ` Richard Henderson
0 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2014-07-08 5:58 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel; +Cc: peter.maydell
On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> +static bool cdc_zero(TCState *tc)
> +{
> + int i;
> + int cdc = tc->PSW & MASK_PSW_CDC;
> + /* Returns TRUE if PSW.CDC.COUNT == 0 or if PSW.CDC ==
> + 7'b1111111, otherwise returns FALSE. */
> + if (cdc == 0x7f) {
> + return true;
> + }
> + /* find CDC.COUNT */
> + for (i = 7; i > 0; i--) {
> + if ((cdc & (1 << i)) == 0) {
> + if ((cdc & ~(0x7f << i)) == 0) {
> + return true;
> + }
> + }
> + }
Consider using clo32 instead of a loop.
> +static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
> +{
> + TCGv sat_neg = tcg_const_i32(low);
> + int l1 = gen_new_label();
> + int l2 = gen_new_label();
> +
> + /* sat_neg = (arg < low ) ? low : arg; */
> + tcg_gen_brcondi_tl(TCG_COND_LT, arg, low, l1);
> + tcg_gen_mov_tl(sat_neg, arg);
> + gen_set_label(l1);
> +
> + /* ret = (sat_neg > up ) ? up : sat_neg; */
> + tcg_gen_movi_tl(ret, up);
> + tcg_gen_brcondi_tl(TCG_COND_GT, sat_neg, up, l2);
> + tcg_gen_mov_tl(ret, sat_neg);
> + gen_set_label(l2);
> +
> + tcg_temp_free(sat_neg);
> +}
Again with the movcond.
> +static void gen_rsubi(TCGv ret, int32_t cons, TCGv r2)
> +{
> + TCGv temp = tcg_temp_new();
> + tcg_gen_movi_tl(temp, cons);
> + tcg_gen_sub_tl(ret, temp, r2);
> + tcg_temp_free(temp);
This is tcg_gen_subfi_tl.
> +/* SR-format jumps */
> + case OPC1_16_SR_JI:
> + tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xffffffff);
Huh? This is a noop.
> +static void decode_sr_system(CPUTRICOREState *env, DisasContext *ctx)
> +{
> + uint32_t op2;
> + op2 = MASK_OP_SR_OP2(ctx->opcode);
> +
> + switch (op2) {
> + case OPC2_16_SR_NOP:
> + printf("NOP Instruction at %08x\n", ctx->pc);
> + ctx->bstate = BS_STOP;
Why stop?
> + case OPC2_16_SR_RFE:
> + gen_helper_rfe(cpu_env);
> + break;
But you do need one here.
> + case OPC2_16_SR_DEBUG:
> + printf("DEBUG Instruction at %08x\n", ctx->pc);
> + ctx->bstate = BS_STOP;
Raise the EXP_DEBUG exception?
> + case OPC1_16_SR_NOT:
> + if (MASK_OP_SR_OP2(ctx->opcode) == 0x0) {
> + printf("Wrong OP2 at at %08x\n", ctx->pc);
You're really going to have to clean up the printfs...
r~
^ permalink raw reply [flat|nested] 33+ messages in thread