[RFC PATCH v15 00/11] ARM: qcom: cpuidle support for 8064, 8074, 8084

[RFC PATCH v15 00/11] ARM: qcom: cpuidle support for 8064, 8074, 8084

[Lina Iyer]

Hi,

I was able to use Daniel's series for the cpuidle_ops [5] and test it on QCOM
SOCs. This alleviates the concerns raised in the previous revision of the QCOM
cpuidle driver.

The previous revision of the QCOM cpuidle driver [1], creates cpuidle device
after a successful probe of the SPM device for the CPU.  There was a concern
regarding the initialization of unnecesary devices on a multi-v7 configuration
[2]. The solutions proposed to solve this problem didnt turn up elegant either
because of the restriction with the existing cpuidle framework.

With Daniel's patches [5], I was able to address the concerns with the cpuidle
driver and devices intialization. Please take a look at this series. The crux
of the difference from the previous series [1] is in the spm_drv_probe() and
registering of the cpuidle_ops and use of ARM generic cpuidle driver.

Changes since v14:
- Support for cpuidle_ops
- SPM probe changes to register cpuidle
- Rebase on top of 4.0-rc1
- Remove SCM patches from series. Rebased on top of Kumar's tree[4]
- Removed cpuidle-qcom.c in favor of ARM generic cpuidle driver
- Included Daniel's change for supporting creating cpuidle devices by platform

Tested on: 8074, 8084.

Thanks,
Lina

[1]. http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/308118.html
[2]. http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/308465.html
[3]. http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/311071.html
[4]. http://www.spinics.net/lists/linux-arm-msm/msg13630.html
[5]. https://lkml.org/lkml/2015/3/3/271

Daniel Lezcano (1):
  ARM: cpuidle: Register per cpuidle device

Lina Iyer (10):
  ARM: qcom: Add Subsystem Power Manager (SPM) driver
  ARM: cpuidle: qcom: Add documentation for qcom cpuidle states.
  ARM: cpuidle: Register cpuidle_ops for QCOM cpus
  ARM: dts: qcom: Add power-controller device node for 8074 Krait CPUs
  ARM: dts: qcom: Add power-controller device node for 8084 Krait CPUs
  ARM: dts: qcom: Update power-controller device node for 8064 Krait
    CPUs
  ARM: dts: qcom: Add idle states device nodes for 8074
  ARM: dts: qcom: Add idle states device nodes for 8084
  ARM: dts: qcom: Add idle state device nodes for 8064
  ARM: qcom: Update defconfig

 .../bindings/arm/msm/qcom,idle-state.txt           |  81 ++++
 .../devicetree/bindings/arm/msm/qcom,saw2.txt      |  31 +-
 arch/arm/boot/dts/qcom-apq8064.dtsi                |  38 +-
 arch/arm/boot/dts/qcom-apq8084.dtsi                |  48 ++-
 arch/arm/boot/dts/qcom-msm8974.dtsi                |  48 ++-
 arch/arm/configs/qcom_defconfig                    |   2 +
 arch/arm/include/asm/cpuidle_ops.h                 |   5 +
 drivers/cpuidle/cpuidle-arm.c                      |  34 +-
 drivers/soc/qcom/Kconfig                           |   7 +
 drivers/soc/qcom/Makefile                          |   1 +
 drivers/soc/qcom/spm.c                             | 422 +++++++++++++++++++++
 11 files changed, 700 insertions(+), 17 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
 create mode 100644 drivers/soc/qcom/spm.c

-- 
2.1.0

[RFC PATCH v15 00/11] ARM: qcom: cpuidle support for 8064, 8074, 8084

[Lina Iyer]

Hi,

I was able to use Daniel's series for the cpuidle_ops [5] and test it on QCOM
SOCs. This alleviates the concerns raised in the previous revision of the QCOM
cpuidle driver.

The previous revision of the QCOM cpuidle driver [1], creates cpuidle device
after a successful probe of the SPM device for the CPU.  There was a concern
regarding the initialization of unnecesary devices on a multi-v7 configuration
[2]. The solutions proposed to solve this problem didnt turn up elegant either
because of the restriction with the existing cpuidle framework.

With Daniel's patches [5], I was able to address the concerns with the cpuidle
driver and devices intialization. Please take a look at this series. The crux
of the difference from the previous series [1] is in the spm_drv_probe() and
registering of the cpuidle_ops and use of ARM generic cpuidle driver.

Changes since v14:
- Support for cpuidle_ops
- SPM probe changes to register cpuidle
- Rebase on top of 4.0-rc1
- Remove SCM patches from series. Rebased on top of Kumar's tree[4]
- Removed cpuidle-qcom.c in favor of ARM generic cpuidle driver
- Included Daniel's change for supporting creating cpuidle devices by platform

Tested on: 8074, 8084.

Thanks,
Lina

[1]. http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/308118.html
[2]. http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/308465.html
[3]. http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/311071.html
[4]. http://www.spinics.net/lists/linux-arm-msm/msg13630.html
[5]. https://lkml.org/lkml/2015/3/3/271

Daniel Lezcano (1):
  ARM: cpuidle: Register per cpuidle device

Lina Iyer (10):
  ARM: qcom: Add Subsystem Power Manager (SPM) driver
  ARM: cpuidle: qcom: Add documentation for qcom cpuidle states.
  ARM: cpuidle: Register cpuidle_ops for QCOM cpus
  ARM: dts: qcom: Add power-controller device node for 8074 Krait CPUs
  ARM: dts: qcom: Add power-controller device node for 8084 Krait CPUs
  ARM: dts: qcom: Update power-controller device node for 8064 Krait
    CPUs
  ARM: dts: qcom: Add idle states device nodes for 8074
  ARM: dts: qcom: Add idle states device nodes for 8084
  ARM: dts: qcom: Add idle state device nodes for 8064
  ARM: qcom: Update defconfig

 .../bindings/arm/msm/qcom,idle-state.txt           |  81 ++++
 .../devicetree/bindings/arm/msm/qcom,saw2.txt      |  31 +-
 arch/arm/boot/dts/qcom-apq8064.dtsi                |  38 +-
 arch/arm/boot/dts/qcom-apq8084.dtsi                |  48 ++-
 arch/arm/boot/dts/qcom-msm8974.dtsi                |  48 ++-
 arch/arm/configs/qcom_defconfig                    |   2 +
 arch/arm/include/asm/cpuidle_ops.h                 |   5 +
 drivers/cpuidle/cpuidle-arm.c                      |  34 +-
 drivers/soc/qcom/Kconfig                           |   7 +
 drivers/soc/qcom/Makefile                          |   1 +
 drivers/soc/qcom/spm.c                             | 422 +++++++++++++++++++++
 11 files changed, 700 insertions(+), 17 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
 create mode 100644 drivers/soc/qcom/spm.c

-- 
2.1.0

[RFC PATCH v15 01/11] ARM: cpuidle: Register per cpuidle device

[Lina Iyer]

From: Daniel Lezcano <daniel.lezcano@linaro.org>

Some architectures have some cpus which does not support idle states.

Let the underlying low level code to return -ENOSYS when it is not
possible to set an idle state.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
[Minor clean ups and fixes of the per-cpu variable]
---
 drivers/cpuidle/cpuidle-arm.c | 34 +++++++++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-arm.c b/drivers/cpuidle/cpuidle-arm.c
index 1c94b88..f7cdb73 100644
--- a/drivers/cpuidle/cpuidle-arm.c
+++ b/drivers/cpuidle/cpuidle-arm.c
@@ -17,11 +17,14 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/slab.h>
 
 #include <asm/cpuidle.h>
 
 #include "dt_idle_states.h"
 
+static DEFINE_PER_CPU(struct cpuidle_device, *cpuidle_arm_dev);
+
 /*
  * arm_enter_idle_state - Programs CPU to enter the specified state
  *
@@ -93,6 +96,7 @@ static const struct of_device_id arm_idle_state_match[] __initconst = {
 static int __init arm_idle_init(void)
 {
 	int cpu, ret;
+	struct cpuidle_device *dev;
 	struct cpuidle_driver *drv = &arm_idle_driver;
 
 	/*
@@ -105,18 +109,46 @@ static int __init arm_idle_init(void)
 	if (ret <= 0)
 		return ret ? : -ENODEV;
 
+
+	ret = cpuidle_register_driver(drv);
+	if (ret) {
+		pr_err("Failed to register cpuidle driver\n");
+		return ret;
+	}
+
 	/*
 	 * Call arch CPU operations in order to initialize
 	 * idle states suspend back-end specific data
 	 */
 	for_each_possible_cpu(cpu) {
+
 		ret = arm_cpuidle_init(cpu);
+		/*
+		 * This cpu does not support any idle states
+		 */
+		if (ret == -ENOSYS)
+			continue;
+
 		if (ret) {
 			pr_err("CPU %d failed to init idle CPU ops\n", cpu);
 			return ret;
 		}
+
+		dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+		if (!dev)
+			return -ENOMEM;
+
+		dev->cpu = cpu;
+		ret = cpuidle_register_device(dev);
+		if (ret) {
+			pr_err("Failed to register cpuidle device for CPU %d\n",
+			       cpu);
+			return ret;
+		}
+
+		per_cpu(cpuidle_arm_dev, cpu) = dev;
 	}
 
-	return cpuidle_register(drv, NULL);
+	return 0;
 }
 device_initcall(arm_idle_init);
-- 
2.1.0

[RFC PATCH v15 01/11] ARM: cpuidle: Register per cpuidle device

[Lina Iyer]

From: Daniel Lezcano <daniel.lezcano@linaro.org>

Some architectures have some cpus which does not support idle states.

Let the underlying low level code to return -ENOSYS when it is not
possible to set an idle state.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
[Minor clean ups and fixes of the per-cpu variable]
---
 drivers/cpuidle/cpuidle-arm.c | 34 +++++++++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-arm.c b/drivers/cpuidle/cpuidle-arm.c
index 1c94b88..f7cdb73 100644
--- a/drivers/cpuidle/cpuidle-arm.c
+++ b/drivers/cpuidle/cpuidle-arm.c
@@ -17,11 +17,14 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/slab.h>
 
 #include <asm/cpuidle.h>
 
 #include "dt_idle_states.h"
 
+static DEFINE_PER_CPU(struct cpuidle_device, *cpuidle_arm_dev);
+
 /*
  * arm_enter_idle_state - Programs CPU to enter the specified state
  *
@@ -93,6 +96,7 @@ static const struct of_device_id arm_idle_state_match[] __initconst = {
 static int __init arm_idle_init(void)
 {
 	int cpu, ret;
+	struct cpuidle_device *dev;
 	struct cpuidle_driver *drv = &arm_idle_driver;
 
 	/*
@@ -105,18 +109,46 @@ static int __init arm_idle_init(void)
 	if (ret <= 0)
 		return ret ? : -ENODEV;
 
+
+	ret = cpuidle_register_driver(drv);
+	if (ret) {
+		pr_err("Failed to register cpuidle driver\n");
+		return ret;
+	}
+
 	/*
 	 * Call arch CPU operations in order to initialize
 	 * idle states suspend back-end specific data
 	 */
 	for_each_possible_cpu(cpu) {
+
 		ret = arm_cpuidle_init(cpu);
+		/*
+		 * This cpu does not support any idle states
+		 */
+		if (ret == -ENOSYS)
+			continue;
+
 		if (ret) {
 			pr_err("CPU %d failed to init idle CPU ops\n", cpu);
 			return ret;
 		}
+
+		dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+		if (!dev)
+			return -ENOMEM;
+
+		dev->cpu = cpu;
+		ret = cpuidle_register_device(dev);
+		if (ret) {
+			pr_err("Failed to register cpuidle device for CPU %d\n",
+			       cpu);
+			return ret;
+		}
+
+		per_cpu(cpuidle_arm_dev, cpu) = dev;
 	}
 
-	return cpuidle_register(drv, NULL);
+	return 0;
 }
 device_initcall(arm_idle_init);
-- 
2.1.0

Re: [RFC PATCH v15 01/11] ARM: cpuidle: Register per cpuidle device

[Andy Gross]

On Mon, Mar 09, 2015 at 09:16:36AM -0600, Lina Iyer wrote:
> From: Daniel Lezcano <daniel.lezcano@linaro.org>
> 
> Some architectures have some cpus which does not support idle states.
> 
> Let the underlying low level code to return -ENOSYS when it is not
> possible to set an idle state.
> 
> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
> [Minor clean ups and fixes of the per-cpu variable]
> ---
>  drivers/cpuidle/cpuidle-arm.c | 34 +++++++++++++++++++++++++++++++++-
>  1 file changed, 33 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cpuidle/cpuidle-arm.c b/drivers/cpuidle/cpuidle-arm.c
> index 1c94b88..f7cdb73 100644
> --- a/drivers/cpuidle/cpuidle-arm.c
> +++ b/drivers/cpuidle/cpuidle-arm.c
> @@ -17,11 +17,14 @@
>  #include <linux/kernel.h>
>  #include <linux/module.h>
>  #include <linux/of.h>
> +#include <linux/slab.h>
>  
>  #include <asm/cpuidle.h>
>  
>  #include "dt_idle_states.h"
>  
> +static DEFINE_PER_CPU(struct cpuidle_device, *cpuidle_arm_dev);
> +
>  /*
>   * arm_enter_idle_state - Programs CPU to enter the specified state
>   *
> @@ -93,6 +96,7 @@ static const struct of_device_id arm_idle_state_match[] __initconst = {
>  static int __init arm_idle_init(void)
>  {
>  	int cpu, ret;
> +	struct cpuidle_device *dev;
>  	struct cpuidle_driver *drv = &arm_idle_driver;
>  
>  	/*
> @@ -105,18 +109,46 @@ static int __init arm_idle_init(void)
>  	if (ret <= 0)
>  		return ret ? : -ENODEV;
>  
> +
> +	ret = cpuidle_register_driver(drv);
> +	if (ret) {
> +		pr_err("Failed to register cpuidle driver\n");
> +		return ret;
> +	}
> +
>  	/*
>  	 * Call arch CPU operations in order to initialize
>  	 * idle states suspend back-end specific data
>  	 */
>  	for_each_possible_cpu(cpu) {
> +
>  		ret = arm_cpuidle_init(cpu);
> +		/*
> +		 * This cpu does not support any idle states
> +		 */
> +		if (ret == -ENOSYS)
> +			continue;
> +
>  		if (ret) {
>  			pr_err("CPU %d failed to init idle CPU ops\n", cpu);
>  			return ret;
>  		}
> +
> +		dev = kzalloc(sizeof(*dev), GFP_KERNEL);

devm_kzalloc?  Otherwise, failures could lead to lost memory.

> +		if (!dev)
> +			return -ENOMEM;
> +
> +		dev->cpu = cpu;
> +		ret = cpuidle_register_device(dev);
> +		if (ret) {
> +			pr_err("Failed to register cpuidle device for CPU %d\n",
> +			       cpu);
> +			return ret;
> +		}
> +
> +		per_cpu(cpuidle_arm_dev, cpu) = dev;
>  	}
>  
> -	return cpuidle_register(drv, NULL);
> +	return 0;
>  }
>  device_initcall(arm_idle_init);
> -- 
> 2.1.0
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[RFC PATCH v15 01/11] ARM: cpuidle: Register per cpuidle device

[Andy Gross]

On Mon, Mar 09, 2015 at 09:16:36AM -0600, Lina Iyer wrote:
> From: Daniel Lezcano <daniel.lezcano@linaro.org>
> 
> Some architectures have some cpus which does not support idle states.
> 
> Let the underlying low level code to return -ENOSYS when it is not
> possible to set an idle state.
> 
> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
> [Minor clean ups and fixes of the per-cpu variable]
> ---
>  drivers/cpuidle/cpuidle-arm.c | 34 +++++++++++++++++++++++++++++++++-
>  1 file changed, 33 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cpuidle/cpuidle-arm.c b/drivers/cpuidle/cpuidle-arm.c
> index 1c94b88..f7cdb73 100644
> --- a/drivers/cpuidle/cpuidle-arm.c
> +++ b/drivers/cpuidle/cpuidle-arm.c
> @@ -17,11 +17,14 @@
>  #include <linux/kernel.h>
>  #include <linux/module.h>
>  #include <linux/of.h>
> +#include <linux/slab.h>
>  
>  #include <asm/cpuidle.h>
>  
>  #include "dt_idle_states.h"
>  
> +static DEFINE_PER_CPU(struct cpuidle_device, *cpuidle_arm_dev);
> +
>  /*
>   * arm_enter_idle_state - Programs CPU to enter the specified state
>   *
> @@ -93,6 +96,7 @@ static const struct of_device_id arm_idle_state_match[] __initconst = {
>  static int __init arm_idle_init(void)
>  {
>  	int cpu, ret;
> +	struct cpuidle_device *dev;
>  	struct cpuidle_driver *drv = &arm_idle_driver;
>  
>  	/*
> @@ -105,18 +109,46 @@ static int __init arm_idle_init(void)
>  	if (ret <= 0)
>  		return ret ? : -ENODEV;
>  
> +
> +	ret = cpuidle_register_driver(drv);
> +	if (ret) {
> +		pr_err("Failed to register cpuidle driver\n");
> +		return ret;
> +	}
> +
>  	/*
>  	 * Call arch CPU operations in order to initialize
>  	 * idle states suspend back-end specific data
>  	 */
>  	for_each_possible_cpu(cpu) {
> +
>  		ret = arm_cpuidle_init(cpu);
> +		/*
> +		 * This cpu does not support any idle states
> +		 */
> +		if (ret == -ENOSYS)
> +			continue;
> +
>  		if (ret) {
>  			pr_err("CPU %d failed to init idle CPU ops\n", cpu);
>  			return ret;
>  		}
> +
> +		dev = kzalloc(sizeof(*dev), GFP_KERNEL);

devm_kzalloc?  Otherwise, failures could lead to lost memory.

> +		if (!dev)
> +			return -ENOMEM;
> +
> +		dev->cpu = cpu;
> +		ret = cpuidle_register_device(dev);
> +		if (ret) {
> +			pr_err("Failed to register cpuidle device for CPU %d\n",
> +			       cpu);
> +			return ret;
> +		}
> +
> +		per_cpu(cpuidle_arm_dev, cpu) = dev;
>  	}
>  
> -	return cpuidle_register(drv, NULL);
> +	return 0;
>  }
>  device_initcall(arm_idle_init);
> -- 
> 2.1.0
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [RFC PATCH v15 01/11] ARM: cpuidle: Register per cpuidle device

[Lina Iyer]

On Mon, Mar 09 2015 at 15:29 -0600, Andy Gross wrote:
>On Mon, Mar 09, 2015 at 09:16:36AM -0600, Lina Iyer wrote:
>> From: Daniel Lezcano <daniel.lezcano@linaro.org>
>>
>> Some architectures have some cpus which does not support idle states.
>>
>> Let the underlying low level code to return -ENOSYS when it is not
>> possible to set an idle state.
>>
>> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
>> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
>> [Minor clean ups and fixes of the per-cpu variable]
>> ---
>>  drivers/cpuidle/cpuidle-arm.c | 34 +++++++++++++++++++++++++++++++++-
>>  1 file changed, 33 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/cpuidle/cpuidle-arm.c b/drivers/cpuidle/cpuidle-arm.c
>> index 1c94b88..f7cdb73 100644
>> --- a/drivers/cpuidle/cpuidle-arm.c
>> +++ b/drivers/cpuidle/cpuidle-arm.c
>> @@ -17,11 +17,14 @@
>>  #include <linux/kernel.h>
>>  #include <linux/module.h>
>>  #include <linux/of.h>
>> +#include <linux/slab.h>
>>
>>  #include <asm/cpuidle.h>
>>
>>  #include "dt_idle_states.h"
>>
>> +static DEFINE_PER_CPU(struct cpuidle_device, *cpuidle_arm_dev);
>> +
>>  /*
>>   * arm_enter_idle_state - Programs CPU to enter the specified state
>>   *
>> @@ -93,6 +96,7 @@ static const struct of_device_id arm_idle_state_match[] __initconst = {
>>  static int __init arm_idle_init(void)
>>  {
>>  	int cpu, ret;
>> +	struct cpuidle_device *dev;
>>  	struct cpuidle_driver *drv = &arm_idle_driver;
>>
>>  	/*
>> @@ -105,18 +109,46 @@ static int __init arm_idle_init(void)
>>  	if (ret <= 0)
>>  		return ret ? : -ENODEV;
>>
>> +
>> +	ret = cpuidle_register_driver(drv);
>> +	if (ret) {
>> +		pr_err("Failed to register cpuidle driver\n");
>> +		return ret;
>> +	}
>> +
>>  	/*
>>  	 * Call arch CPU operations in order to initialize
>>  	 * idle states suspend back-end specific data
>>  	 */
>>  	for_each_possible_cpu(cpu) {
>> +
>>  		ret = arm_cpuidle_init(cpu);
>> +		/*
>> +		 * This cpu does not support any idle states
>> +		 */
>> +		if (ret == -ENOSYS)
>> +			continue;
>> +
>>  		if (ret) {
>>  			pr_err("CPU %d failed to init idle CPU ops\n", cpu);
>>  			return ret;
>>  		}
>> +
>> +		dev = kzalloc(sizeof(*dev), GFP_KERNEL);
>
>devm_kzalloc?  Otherwise, failures could lead to lost memory.
>
I dont have a local device to work with for allocation. May be I can get
the cpu device node and the device therefore for allocation. Thoughts?

>> +		if (!dev)
>> +			return -ENOMEM;
>> +
>> +		dev->cpu = cpu;
>> +		ret = cpuidle_register_device(dev);
>> +		if (ret) {
>> +			pr_err("Failed to register cpuidle device for CPU %d\n",
>> +			       cpu);
>> +			return ret;
>> +		}
>> +
>> +		per_cpu(cpuidle_arm_dev, cpu) = dev;
>>  	}
>>
>> -	return cpuidle_register(drv, NULL);
>> +	return 0;
>>  }
>>  device_initcall(arm_idle_init);
>> --
>> 2.1.0
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>-- 
>Qualcomm Innovation Center, Inc.
>The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>a Linux Foundation Collaborative Project
>

[RFC PATCH v15 01/11] ARM: cpuidle: Register per cpuidle device

[Lina Iyer]

On Mon, Mar 09 2015 at 15:29 -0600, Andy Gross wrote:
>On Mon, Mar 09, 2015 at 09:16:36AM -0600, Lina Iyer wrote:
>> From: Daniel Lezcano <daniel.lezcano@linaro.org>
>>
>> Some architectures have some cpus which does not support idle states.
>>
>> Let the underlying low level code to return -ENOSYS when it is not
>> possible to set an idle state.
>>
>> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
>> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
>> [Minor clean ups and fixes of the per-cpu variable]
>> ---
>>  drivers/cpuidle/cpuidle-arm.c | 34 +++++++++++++++++++++++++++++++++-
>>  1 file changed, 33 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/cpuidle/cpuidle-arm.c b/drivers/cpuidle/cpuidle-arm.c
>> index 1c94b88..f7cdb73 100644
>> --- a/drivers/cpuidle/cpuidle-arm.c
>> +++ b/drivers/cpuidle/cpuidle-arm.c
>> @@ -17,11 +17,14 @@
>>  #include <linux/kernel.h>
>>  #include <linux/module.h>
>>  #include <linux/of.h>
>> +#include <linux/slab.h>
>>
>>  #include <asm/cpuidle.h>
>>
>>  #include "dt_idle_states.h"
>>
>> +static DEFINE_PER_CPU(struct cpuidle_device, *cpuidle_arm_dev);
>> +
>>  /*
>>   * arm_enter_idle_state - Programs CPU to enter the specified state
>>   *
>> @@ -93,6 +96,7 @@ static const struct of_device_id arm_idle_state_match[] __initconst = {
>>  static int __init arm_idle_init(void)
>>  {
>>  	int cpu, ret;
>> +	struct cpuidle_device *dev;
>>  	struct cpuidle_driver *drv = &arm_idle_driver;
>>
>>  	/*
>> @@ -105,18 +109,46 @@ static int __init arm_idle_init(void)
>>  	if (ret <= 0)
>>  		return ret ? : -ENODEV;
>>
>> +
>> +	ret = cpuidle_register_driver(drv);
>> +	if (ret) {
>> +		pr_err("Failed to register cpuidle driver\n");
>> +		return ret;
>> +	}
>> +
>>  	/*
>>  	 * Call arch CPU operations in order to initialize
>>  	 * idle states suspend back-end specific data
>>  	 */
>>  	for_each_possible_cpu(cpu) {
>> +
>>  		ret = arm_cpuidle_init(cpu);
>> +		/*
>> +		 * This cpu does not support any idle states
>> +		 */
>> +		if (ret == -ENOSYS)
>> +			continue;
>> +
>>  		if (ret) {
>>  			pr_err("CPU %d failed to init idle CPU ops\n", cpu);
>>  			return ret;
>>  		}
>> +
>> +		dev = kzalloc(sizeof(*dev), GFP_KERNEL);
>
>devm_kzalloc?  Otherwise, failures could lead to lost memory.
>
I dont have a local device to work with for allocation. May be I can get
the cpu device node and the device therefore for allocation. Thoughts?

>> +		if (!dev)
>> +			return -ENOMEM;
>> +
>> +		dev->cpu = cpu;
>> +		ret = cpuidle_register_device(dev);
>> +		if (ret) {
>> +			pr_err("Failed to register cpuidle device for CPU %d\n",
>> +			       cpu);
>> +			return ret;
>> +		}
>> +
>> +		per_cpu(cpuidle_arm_dev, cpu) = dev;
>>  	}
>>
>> -	return cpuidle_register(drv, NULL);
>> +	return 0;
>>  }
>>  device_initcall(arm_idle_init);
>> --
>> 2.1.0
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>-- 
>Qualcomm Innovation Center, Inc.
>The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>a Linux Foundation Collaborative Project
>

Re: [RFC PATCH v15 01/11] ARM: cpuidle: Register per cpuidle device

[Andy Gross]

On Mon, Mar 09, 2015 at 03:40:06PM -0600, Lina Iyer wrote:
<snip>

> >> 	for_each_possible_cpu(cpu) {
> >>+
> >> 		ret = arm_cpuidle_init(cpu);
> >>+		/*
> >>+		 * This cpu does not support any idle states
> >>+		 */
> >>+		if (ret == -ENOSYS)
> >>+			continue;
> >>+
> >> 		if (ret) {
> >> 			pr_err("CPU %d failed to init idle CPU ops\n", cpu);
> >> 			return ret;
> >> 		}
> >>+
> >>+		dev = kzalloc(sizeof(*dev), GFP_KERNEL);
> >
> >devm_kzalloc?  Otherwise, failures could lead to lost memory.
> >
> I dont have a local device to work with for allocation. May be I can get
> the cpu device node and the device therefore for allocation. Thoughts?

Ah, well the cpu device node could be used.  My only concern is that dev cannot
be referenced after the cpu is removed.

> >>+		if (!dev)
> >>+			return -ENOMEM;
> >>+
> >>+		dev->cpu = cpu;
> >>+		ret = cpuidle_register_device(dev);
> >>+		if (ret) {
> >>+			pr_err("Failed to register cpuidle device for CPU %d\n",
> >>+			       cpu);

<snip>

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[RFC PATCH v15 01/11] ARM: cpuidle: Register per cpuidle device

[Andy Gross]

On Mon, Mar 09, 2015 at 03:40:06PM -0600, Lina Iyer wrote:
<snip>

> >> 	for_each_possible_cpu(cpu) {
> >>+
> >> 		ret = arm_cpuidle_init(cpu);
> >>+		/*
> >>+		 * This cpu does not support any idle states
> >>+		 */
> >>+		if (ret == -ENOSYS)
> >>+			continue;
> >>+
> >> 		if (ret) {
> >> 			pr_err("CPU %d failed to init idle CPU ops\n", cpu);
> >> 			return ret;
> >> 		}
> >>+
> >>+		dev = kzalloc(sizeof(*dev), GFP_KERNEL);
> >
> >devm_kzalloc?  Otherwise, failures could lead to lost memory.
> >
> I dont have a local device to work with for allocation. May be I can get
> the cpu device node and the device therefore for allocation. Thoughts?

Ah, well the cpu device node could be used.  My only concern is that dev cannot
be referenced after the cpu is removed.

> >>+		if (!dev)
> >>+			return -ENOMEM;
> >>+
> >>+		dev->cpu = cpu;
> >>+		ret = cpuidle_register_device(dev);
> >>+		if (ret) {
> >>+			pr_err("Failed to register cpuidle device for CPU %d\n",
> >>+			       cpu);

<snip>

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [RFC PATCH v15 01/11] ARM: cpuidle: Register per cpuidle device

[Russell King - ARM Linux]

On Mon, Mar 09, 2015 at 09:16:36AM -0600, Lina Iyer wrote:
> @@ -105,18 +109,46 @@ static int __init arm_idle_init(void)
>  	if (ret <= 0)
>  		return ret ? : -ENODEV;
>  
> +

A bit better formatting would be nice - you don't need the extra blank
line here.

> +	ret = cpuidle_register_driver(drv);
> +	if (ret) {
> +		pr_err("Failed to register cpuidle driver\n");
> +		return ret;
> +	}
> +
>  	/*
>  	 * Call arch CPU operations in order to initialize
>  	 * idle states suspend back-end specific data
>  	 */
>  	for_each_possible_cpu(cpu) {
> +

This blank line is not necessary either.

>  		ret = arm_cpuidle_init(cpu);

However, a blank line here would be a good thing.

> +		/*
> +		 * This cpu does not support any idle states
> +		 */

Also, formatting this as /* This cpu does not support any idle states */ is
acceptable too, and doesn't waste as many lines.

> +		if (ret == -ENOSYS)
> +			continue;
> +
>  		if (ret) {
>  			pr_err("CPU %d failed to init idle CPU ops\n", cpu);
>  			return ret;
>  		}
> +
> +		dev = kzalloc(sizeof(*dev), GFP_KERNEL);
> +		if (!dev)
> +			return -ENOMEM;
> +
> +		dev->cpu = cpu;
> +		ret = cpuidle_register_device(dev);
> +		if (ret) {
> +			pr_err("Failed to register cpuidle device for CPU %d\n",
> +			       cpu);
> +			return ret;

It looks like we leak the 'dev' allocation here.

Also, other error paths, it looks like we leave the previously registered
cpuidle devices in place.  That may be acceptable if the intention is to
initialise as many CPUs as possible - but we then miss the
cpuidle_register() call below, which seems to make the registered devices
useless.  It's a little inconsistent.

Also, it's useful to report why something fails - printing the error code
can help debugging if it isn't already printed elsewhere.

> +		}
> +
> +		per_cpu(cpuidle_arm_dev, cpu) = dev;
>  	}
>  
> -	return cpuidle_register(drv, NULL);
> +	return 0;
>  }
>  device_initcall(arm_idle_init);

-- 
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
according to speedtest.net.

[RFC PATCH v15 01/11] ARM: cpuidle: Register per cpuidle device

[Russell King - ARM Linux]

On Mon, Mar 09, 2015 at 09:16:36AM -0600, Lina Iyer wrote:
> @@ -105,18 +109,46 @@ static int __init arm_idle_init(void)
>  	if (ret <= 0)
>  		return ret ? : -ENODEV;
>  
> +

A bit better formatting would be nice - you don't need the extra blank
line here.

> +	ret = cpuidle_register_driver(drv);
> +	if (ret) {
> +		pr_err("Failed to register cpuidle driver\n");
> +		return ret;
> +	}
> +
>  	/*
>  	 * Call arch CPU operations in order to initialize
>  	 * idle states suspend back-end specific data
>  	 */
>  	for_each_possible_cpu(cpu) {
> +

This blank line is not necessary either.

>  		ret = arm_cpuidle_init(cpu);

However, a blank line here would be a good thing.

> +		/*
> +		 * This cpu does not support any idle states
> +		 */

Also, formatting this as /* This cpu does not support any idle states */ is
acceptable too, and doesn't waste as many lines.

> +		if (ret == -ENOSYS)
> +			continue;
> +
>  		if (ret) {
>  			pr_err("CPU %d failed to init idle CPU ops\n", cpu);
>  			return ret;
>  		}
> +
> +		dev = kzalloc(sizeof(*dev), GFP_KERNEL);
> +		if (!dev)
> +			return -ENOMEM;
> +
> +		dev->cpu = cpu;
> +		ret = cpuidle_register_device(dev);
> +		if (ret) {
> +			pr_err("Failed to register cpuidle device for CPU %d\n",
> +			       cpu);
> +			return ret;

It looks like we leak the 'dev' allocation here.

Also, other error paths, it looks like we leave the previously registered
cpuidle devices in place.  That may be acceptable if the intention is to
initialise as many CPUs as possible - but we then miss the
cpuidle_register() call below, which seems to make the registered devices
useless.  It's a little inconsistent.

Also, it's useful to report why something fails - printing the error code
can help debugging if it isn't already printed elsewhere.

> +		}
> +
> +		per_cpu(cpuidle_arm_dev, cpu) = dev;
>  	}
>  
> -	return cpuidle_register(drv, NULL);
> +	return 0;
>  }
>  device_initcall(arm_idle_init);

-- 
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
according to speedtest.net.

Re: [RFC PATCH v15 01/11] ARM: cpuidle: Register per cpuidle device

[Lina Iyer]

On Tue, Mar 10 2015 at 04:37 -0600, Russell King - ARM Linux wrote:
>On Mon, Mar 09, 2015 at 09:16:36AM -0600, Lina Iyer wrote:
>> @@ -105,18 +109,46 @@ static int __init arm_idle_init(void)
>>  	if (ret <= 0)
>>  		return ret ? : -ENODEV;
>>
>> +
>
>A bit better formatting would be nice - you don't need the extra blank
>line here.
>
>> +	ret = cpuidle_register_driver(drv);
>> +	if (ret) {
>> +		pr_err("Failed to register cpuidle driver\n");
>> +		return ret;
>> +	}
>> +
>>  	/*
>>  	 * Call arch CPU operations in order to initialize
>>  	 * idle states suspend back-end specific data
>>  	 */
>>  	for_each_possible_cpu(cpu) {
>> +
>
>This blank line is not necessary either.
>
>>  		ret = arm_cpuidle_init(cpu);
>
>However, a blank line here would be a good thing.
>
Sure.
>> +		/*
>> +		 * This cpu does not support any idle states
>> +		 */
>
>Also, formatting this as /* This cpu does not support any idle states */ is
>acceptable too, and doesn't waste as many lines.
>
Will fix.
>> +		if (ret == -ENOSYS)
>> +			continue;
>> +
>>  		if (ret) {
>>  			pr_err("CPU %d failed to init idle CPU ops\n", cpu);
>>  			return ret;
>>  		}
>> +
>> +		dev = kzalloc(sizeof(*dev), GFP_KERNEL);
>> +		if (!dev)
>> +			return -ENOMEM;
>> +
>> +		dev->cpu = cpu;
>> +		ret = cpuidle_register_device(dev);
>> +		if (ret) {
>> +			pr_err("Failed to register cpuidle device for CPU %d\n",
>> +			       cpu);
>> +			return ret;
>
>It looks like we leak the 'dev' allocation here.
>

True, I will amend that.

>Also, other error paths, it looks like we leave the previously registered
>cpuidle devices in place.  That may be acceptable if the intention is to
>initialise as many CPUs as possible - but we then miss the
>cpuidle_register() call below, which seems to make the registered devices
>useless.  It's a little inconsistent.
>
>Also, it's useful to report why something fails - printing the error code
>can help debugging if it isn't already printed elsewhere.
>
Fair point.
>> +		}
>> +
>> +		per_cpu(cpuidle_arm_dev, cpu) = dev;
>>  	}
>>
>> -	return cpuidle_register(drv, NULL);
>> +	return 0;
>>  }
>>  device_initcall(arm_idle_init);
>
>-- 
>FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
>according to speedtest.net.

[RFC PATCH v15 01/11] ARM: cpuidle: Register per cpuidle device

[Lina Iyer]

On Tue, Mar 10 2015 at 04:37 -0600, Russell King - ARM Linux wrote:
>On Mon, Mar 09, 2015 at 09:16:36AM -0600, Lina Iyer wrote:
>> @@ -105,18 +109,46 @@ static int __init arm_idle_init(void)
>>  	if (ret <= 0)
>>  		return ret ? : -ENODEV;
>>
>> +
>
>A bit better formatting would be nice - you don't need the extra blank
>line here.
>
>> +	ret = cpuidle_register_driver(drv);
>> +	if (ret) {
>> +		pr_err("Failed to register cpuidle driver\n");
>> +		return ret;
>> +	}
>> +
>>  	/*
>>  	 * Call arch CPU operations in order to initialize
>>  	 * idle states suspend back-end specific data
>>  	 */
>>  	for_each_possible_cpu(cpu) {
>> +
>
>This blank line is not necessary either.
>
>>  		ret = arm_cpuidle_init(cpu);
>
>However, a blank line here would be a good thing.
>
Sure.
>> +		/*
>> +		 * This cpu does not support any idle states
>> +		 */
>
>Also, formatting this as /* This cpu does not support any idle states */ is
>acceptable too, and doesn't waste as many lines.
>
Will fix.
>> +		if (ret == -ENOSYS)
>> +			continue;
>> +
>>  		if (ret) {
>>  			pr_err("CPU %d failed to init idle CPU ops\n", cpu);
>>  			return ret;
>>  		}
>> +
>> +		dev = kzalloc(sizeof(*dev), GFP_KERNEL);
>> +		if (!dev)
>> +			return -ENOMEM;
>> +
>> +		dev->cpu = cpu;
>> +		ret = cpuidle_register_device(dev);
>> +		if (ret) {
>> +			pr_err("Failed to register cpuidle device for CPU %d\n",
>> +			       cpu);
>> +			return ret;
>
>It looks like we leak the 'dev' allocation here.
>

True, I will amend that.

>Also, other error paths, it looks like we leave the previously registered
>cpuidle devices in place.  That may be acceptable if the intention is to
>initialise as many CPUs as possible - but we then miss the
>cpuidle_register() call below, which seems to make the registered devices
>useless.  It's a little inconsistent.
>
>Also, it's useful to report why something fails - printing the error code
>can help debugging if it isn't already printed elsewhere.
>
Fair point.
>> +		}
>> +
>> +		per_cpu(cpuidle_arm_dev, cpu) = dev;
>>  	}
>>
>> -	return cpuidle_register(drv, NULL);
>> +	return 0;
>>  }
>>  device_initcall(arm_idle_init);
>
>-- 
>FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
>according to speedtest.net.

[RFC PATCH v15 02/11] ARM: qcom: Add Subsystem Power Manager (SPM) driver

[Lina Iyer]

SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an interrupt at the GIC, which
then completes the rest of low power mode sequence and brings the core
out of low power mode.

The SPM has a set of control registers that configure the SPMs
individually based on the type of the core and the runtime conditions.
SPM is a finite state machine block to which a sequence is provided and
it interprets the bytes and executes them in sequence. Each low power
mode that the core can enter into is provided to the SPM as a sequence.

Configure the SPM to set the core (cpu or L2) into its low power mode,
the index of the first command in the sequence is set in the SPM_CTL
register. When the core executes ARM wfi instruction, it triggers the
SPM state machine to start executing from that index. The SPM state
machine waits until the interrupt occurs and starts executing the rest
of the sequence until it hits the end of the sequence. The end of the
sequence jumps the core out of its low power mode.

Add support for an idle driver to set up the SPM to place the core in
Standby or Standalone power collapse mode when the core is idle.

Based on work by: Mahesh Sivasubramanian <msivasub@codeaurora.org>,
Ai Li <ali@codeaurora.org>, Praveen Chidambaram <pchidamb@codeaurora.org>
Original tree available at -
git://codeaurora.org/quic/la/kernel/msm-3.10.git

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 .../devicetree/bindings/arm/msm/qcom,saw2.txt      |  31 +-
 drivers/soc/qcom/Kconfig                           |   7 +
 drivers/soc/qcom/Makefile                          |   1 +
 drivers/soc/qcom/spm.c                             | 422 +++++++++++++++++++++
 4 files changed, 455 insertions(+), 6 deletions(-)
 create mode 100644 drivers/soc/qcom/spm.c

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
index 1505fb8..690c3c0 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
@@ -2,11 +2,20 @@ SPM AVS Wrapper 2 (SAW2)
 
 The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
 Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
-micro-controller that transitions a piece of hardware (like a processor or
+power-controller that transitions a piece of hardware (like a processor or
 subsystem) into and out of low power modes via a direct connection to
 the PMIC. It can also be wired up to interact with other processors in the
 system, notifying them when a low power state is entered or exited.
 
+Multiple revisions of the SAW hardware are supported using these Device Nodes.
+SAW2 revisions differ in the register offset and configuration data. Also, the
+same revision of the SAW in different SoCs may have different configuration
+data due the the differences in hardware capabilities. Hence the SoC name, the
+version of the SAW hardware in that SoC and the distinction between cpu (big
+or Little) or cache, may be needed to uniquely identify the SAW register
+configuration and initialization data. The compatible string is used to
+indicate this parameter.
+
 PROPERTIES
 
 - compatible:
@@ -14,10 +23,13 @@ PROPERTIES
 	Value type: <string>
 	Definition: shall contain "qcom,saw2". A more specific value should be
 		    one of:
-			 "qcom,saw2-v1"
-			 "qcom,saw2-v1.1"
-			 "qcom,saw2-v2"
-			 "qcom,saw2-v2.1"
+			"qcom,saw2-v1"
+			"qcom,saw2-v1.1"
+			"qcom,saw2-v2"
+			"qcom,saw2-v2.1"
+			"qcom,apq8064-saw2-v1.1-cpu"
+			"qcom,msm8974-saw2-v2.1-cpu"
+			"qcom,apq8084-saw2-v2.1-cpu"
 
 - reg:
 	Usage: required
@@ -26,10 +38,17 @@ PROPERTIES
 		    the register region. An optional second element specifies
 		    the base address and size of the alias register region.
 
+- regulator:
+	Usage: optional
+	Value type: boolean
+	Definition: Indicates that this SPM device acts as a regulator device
+			device for the core (CPU or Cache) the SPM is attached
+			to.
 
 Example:
 
-	regulator@2099000 {
+	power-controller@2099000 {
 		compatible = "qcom,saw2";
 		reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+		regulator;
 	};
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 7bd2c94..628bcba 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -9,3 +9,10 @@ config QCOM_GSBI
           functions for connecting the underlying serial UART, SPI, and I2C
           devices to the output pins.
 
+config QCOM_PM
+	bool "Qualcomm Power Management"
+	depends on ARCH_QCOM
+	help
+	  QCOM Platform specific power driver to manage cores and L2 low power
+	  modes. It interface with various system drivers to put the cores in
+	  low power modes.
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 4389012..931d385 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_QCOM_GSBI)	+=	qcom_gsbi.o
+obj-$(CONFIG_QCOM_PM)	+=	spm.o
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
new file mode 100644
index 0000000..85b33ee
--- /dev/null
+++ b/drivers/soc/qcom/spm.c
@@ -0,0 +1,422 @@
+/*
+ * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014,2015, Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/qcom_scm.h>
+
+#include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+
+#define MAX_PMIC_DATA		2
+#define MAX_SEQ_DATA		64
+#define SPM_CTL_INDEX		0x7f
+#define SPM_CTL_INDEX_SHIFT	4
+#define SPM_CTL_EN		BIT(0)
+
+enum pm_sleep_mode {
+	PM_SLEEP_MODE_STBY,
+	PM_SLEEP_MODE_RET,
+	PM_SLEEP_MODE_SPC,
+	PM_SLEEP_MODE_PC,
+	PM_SLEEP_MODE_NR,
+};
+
+enum spm_reg {
+	SPM_REG_CFG,
+	SPM_REG_SPM_CTL,
+	SPM_REG_DLY,
+	SPM_REG_PMIC_DLY,
+	SPM_REG_PMIC_DATA_0,
+	SPM_REG_PMIC_DATA_1,
+	SPM_REG_VCTL,
+	SPM_REG_SEQ_ENTRY,
+	SPM_REG_SPM_STS,
+	SPM_REG_PMIC_STS,
+	SPM_REG_NR,
+};
+
+struct spm_reg_data {
+	const u8 *reg_offset;
+	u32 spm_cfg;
+	u32 spm_dly;
+	u32 pmic_dly;
+	u32 pmic_data[MAX_PMIC_DATA];
+	u8 seq[MAX_SEQ_DATA];
+	u8 start_index[PM_SLEEP_MODE_NR];
+};
+
+struct spm_driver_data {
+	void __iomem *reg_base;
+	const struct spm_reg_data *reg_data;
+};
+
+static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = {
+	[SPM_REG_CFG]		= 0x08,
+	[SPM_REG_SPM_CTL]	= 0x30,
+	[SPM_REG_DLY]		= 0x34,
+	[SPM_REG_SEQ_ENTRY]	= 0x80,
+};
+
+/* SPM register data for 8974, 8084 */
+static const struct spm_reg_data spm_reg_8974_8084_cpu  = {
+	.reg_offset = spm_reg_offset_v2_1,
+	.spm_cfg = 0x1,
+	.spm_dly = 0x3C102800,
+	.seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
+		0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
+		0x0F },
+	.start_index[PM_SLEEP_MODE_STBY] = 0,
+	.start_index[PM_SLEEP_MODE_SPC] = 3,
+};
+
+static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = {
+	[SPM_REG_CFG]		= 0x08,
+	[SPM_REG_SPM_CTL]	= 0x20,
+	[SPM_REG_PMIC_DLY]	= 0x24,
+	[SPM_REG_PMIC_DATA_0]	= 0x28,
+	[SPM_REG_PMIC_DATA_1]	= 0x2C,
+	[SPM_REG_SEQ_ENTRY]	= 0x80,
+};
+
+/* SPM register data for 8064 */
+static const struct spm_reg_data spm_reg_8064_cpu = {
+	.reg_offset = spm_reg_offset_v1_1,
+	.spm_cfg = 0x1F,
+	.pmic_dly = 0x02020004,
+	.pmic_data[0] = 0x0084009C,
+	.pmic_data[1] = 0x00A4001C,
+	.seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
+		0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
+	.start_index[PM_SLEEP_MODE_STBY] = 0,
+	.start_index[PM_SLEEP_MODE_SPC] = 2,
+};
+
+static DEFINE_PER_CPU(struct spm_driver_data *, cpu_spm_drv);
+
+typedef int (*idle_fn)(int);
+static DEFINE_PER_CPU(idle_fn*, qcom_idle_ops);
+
+static inline void spm_register_write(struct spm_driver_data *drv,
+					enum spm_reg reg, u32 val)
+{
+	if (drv->reg_data->reg_offset[reg])
+		writel_relaxed(val, drv->reg_base +
+				drv->reg_data->reg_offset[reg]);
+}
+
+/* Ensure a guaranteed write, before return */
+static inline void spm_register_write_sync(struct spm_driver_data *drv,
+					enum spm_reg reg, u32 val)
+{
+	u32 ret;
+
+	if (!drv->reg_data->reg_offset[reg])
+		return;
+
+	do {
+		writel_relaxed(val, drv->reg_base +
+				drv->reg_data->reg_offset[reg]);
+		ret = readl_relaxed(drv->reg_base +
+				drv->reg_data->reg_offset[reg]);
+		if (ret == val)
+			break;
+		cpu_relax();
+	} while (1);
+}
+
+static inline u32 spm_register_read(struct spm_driver_data *drv,
+					enum spm_reg reg)
+{
+	return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
+}
+
+static void spm_set_low_power_mode(enum pm_sleep_mode mode)
+{
+	struct spm_driver_data *drv = per_cpu(cpu_spm_drv,
+						smp_processor_id());
+	u32 start_index;
+	u32 ctl_val;
+
+	start_index = drv->reg_data->start_index[mode];
+
+	ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
+	ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
+	ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
+	ctl_val |= SPM_CTL_EN;
+	spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
+}
+
+static int qcom_pm_collapse(unsigned long int unused)
+{
+	qcom_scm_cpu_power_down(QCOM_SCM_L2_ON);
+
+	/*
+	 * Returns here only if there was a pending interrupt and we did not
+	 * power down as a result.
+	 */
+	return -1;
+}
+
+static int qcom_cpu_standby(int cpuarg)
+{
+	spm_set_low_power_mode(PM_SLEEP_MODE_STBY);
+	cpu_do_idle();
+
+	return 0;
+}
+
+static int qcom_cpu_spc(int cpu)
+{
+	int ret;
+
+	spm_set_low_power_mode(PM_SLEEP_MODE_SPC);
+	cpu_pm_enter();
+	ret = cpu_suspend(0, qcom_pm_collapse);
+	/*
+	 * ARM common code may execute WFI, and if the SPM mode is not reset,
+	 * then we may accidently do power down state.
+	 * SPM is configured to reset to do STBY, but that relies on the
+	 * SPM state machine to be executed. When an interrupt is pending as we
+	 * enter idle state, SPM would not execute its state machine, so the
+	 * SPM may remain configured to do power down state.
+	 * Reset the state back to standby.
+	 */
+	spm_set_low_power_mode(PM_SLEEP_MODE_STBY);
+	cpu_pm_exit();
+
+	return ret;
+}
+
+static int qcom_idle_enter(int cpu, unsigned long index)
+{
+	if (!per_cpu(qcom_idle_ops, cpu)[index])
+		return -EOPNOTSUPP;
+
+	return per_cpu(qcom_idle_ops, cpu)[index](cpu);
+}
+
+const struct of_device_id qcom_idle_state_match[] __initconst = {
+	{ .compatible = "qcom,idle-state-stby", .data = qcom_cpu_standby },
+	{ .compatible = "qcom,idle-state-spc", .data = qcom_cpu_spc },
+	{ },
+};
+
+static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
+{
+	const struct of_device_id *match_id;
+	struct device_node *state_node;
+	int i;
+	int state_count = 0;
+	idle_fn idle_fns[CPUIDLE_STATE_MAX];
+	idle_fn *fns;
+	cpumask_t mask;
+	bool use_scm_power_down = false;
+
+	for (i = 0; ; i++) {
+		state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
+		if (!state_node)
+			break;
+
+		if (!of_device_is_available(state_node))
+			continue;
+
+		if (i == CPUIDLE_STATE_MAX) {
+			pr_warn("%s: cpuidle states reached max possible\n",
+					__func__);
+			break;
+		}
+
+		match_id = of_match_node(qcom_idle_state_match, state_node);
+		if (!match_id)
+			return -ENODEV;
+
+		idle_fns[state_count] = match_id->data;
+
+		/* Check if any of the states allow power down */
+		if (match_id->data == qcom_cpu_spc)
+			use_scm_power_down = true;
+
+		state_count++;
+	}
+
+	if (!state_count) {
+		pr_warn("No idle ops founds for cpu %d\n", cpu);
+		return -ENODEV;
+	}
+
+	fns = kcalloc(state_count, sizeof(*fns), GFP_KERNEL);
+	if (!fns)
+		return -ENOMEM;
+
+	for (i = 0; i < state_count; i++)
+		fns[i] = idle_fns[i];
+
+	if (use_scm_power_down) {
+		/* We have atlease one power down mode */
+		cpumask_clear(&mask);
+		cpumask_set_cpu(cpu, &mask);
+		qcom_scm_set_warm_boot_addr(cpu_resume, &mask);
+	}
+
+	per_cpu(qcom_idle_ops, cpu) = fns;
+
+	/*
+	 * Condition: cpuidle_driver_register() needs to happen before
+	 * cpuidle_register_device().
+	 * Check if the SPM probe has happened -
+	 * - If SPM probed successfully before arm_idle_init(), then defer
+	 *   the registration of cpuidle_device back to arm_idle_init()
+	 * - If the SPM probe happens in the future, then let the SPM probe
+	 *   register the cpuidle device, return -ENOSYS.
+	 */
+	return per_cpu(cpu_spm_drv, cpu) ? 0 : -ENOSYS;
+}
+
+struct cpuidle_ops qcom_kpss_v1_cpuidle_ops __initdata = {
+	.name = "qcom,kpss-acc-v1",
+	.suspend = qcom_idle_enter,
+	.init = qcom_cpuidle_init,
+};
+
+struct cpuidle_ops qcom_kpss_v2_cpuidle_ops __initdata = {
+	.name = "qcom,kpss-acc-v2",
+	.suspend = qcom_idle_enter,
+	.init = qcom_cpuidle_init,
+};
+
+static struct spm_driver_data *spm_get_drv(struct platform_device *pdev,
+		int *spm_cpu)
+{
+	struct spm_driver_data *drv = NULL;
+	struct device_node *cpu_node, *saw_node;
+	int cpu;
+	bool found;
+
+	for_each_possible_cpu(cpu) {
+		cpu_node = of_cpu_device_node_get(cpu);
+		if (!cpu_node)
+			continue;
+		saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
+		found = (saw_node == pdev->dev.of_node);
+		of_node_put(saw_node);
+		of_node_put(cpu_node);
+		if (found)
+			break;
+	}
+
+	if (found) {
+		drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
+		if (drv)
+			*spm_cpu = cpu;
+	}
+
+	return drv;
+}
+
+static const struct of_device_id spm_match_table[] = {
+	{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
+	  .data = &spm_reg_8974_8084_cpu },
+	{ .compatible = "qcom,apq8084-saw2-v2.1-cpu",
+	  .data = &spm_reg_8974_8084_cpu },
+	{ .compatible = "qcom,apq8064-saw2-v1.1-cpu",
+	  .data = &spm_reg_8064_cpu },
+	{ },
+};
+
+static int spm_dev_probe(struct platform_device *pdev)
+{
+	struct spm_driver_data *drv;
+	struct resource *res;
+	const struct of_device_id *match_id;
+	void __iomem *addr;
+	int cpu;
+	int ret = 0;
+
+	drv = spm_get_drv(pdev, &cpu);
+	if (!drv)
+		return -EINVAL;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	drv->reg_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(drv->reg_base))
+		return PTR_ERR(drv->reg_base);
+
+	match_id = of_match_node(spm_match_table, pdev->dev.of_node);
+	if (!match_id)
+		return -ENODEV;
+
+	drv->reg_data = match_id->data;
+
+	/* Write the SPM sequences first.. */
+	addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
+	__iowrite32_copy(addr, drv->reg_data->seq,
+			ARRAY_SIZE(drv->reg_data->seq) / 4);
+
+	/*
+	 * ..and then the control registers.
+	 * On some SoC if the control registers are written first and if the
+	 * CPU was held in reset, the reset signal could trigger the SPM state
+	 * machine, before the sequences are completely written.
+	 */
+	spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
+	spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
+	spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
+	spm_register_write(drv, SPM_REG_PMIC_DATA_0,
+				drv->reg_data->pmic_data[0]);
+	spm_register_write(drv, SPM_REG_PMIC_DATA_1,
+				drv->reg_data->pmic_data[1]);
+
+	per_cpu(cpu_spm_drv, cpu) = drv;
+
+	/* If the cpuidle ops have already been registered with cpuidle,
+	 * then we have been waiting on this SPM probe to register the
+	 * cpuidle device.
+	 */
+	if (per_cpu(qcom_idle_ops, cpu)) {
+		struct cpuidle_device *dev;
+
+		dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
+		if (!dev)
+			return -ENOMEM;
+		dev->cpu = cpu;
+		ret = cpuidle_register_device(dev);
+	}
+
+	return ret;
+}
+
+static struct platform_driver spm_driver = {
+	.probe = spm_dev_probe,
+	.driver = {
+		.name = "saw",
+		.of_match_table = spm_match_table,
+	},
+};
+module_platform_driver(spm_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("SAW power controller driver");
+MODULE_ALIAS("platform:saw");
-- 
2.1.0

[RFC PATCH v15 02/11] ARM: qcom: Add Subsystem Power Manager (SPM) driver

[Lina Iyer]

SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an interrupt at the GIC, which
then completes the rest of low power mode sequence and brings the core
out of low power mode.

The SPM has a set of control registers that configure the SPMs
individually based on the type of the core and the runtime conditions.
SPM is a finite state machine block to which a sequence is provided and
it interprets the bytes and executes them in sequence. Each low power
mode that the core can enter into is provided to the SPM as a sequence.

Configure the SPM to set the core (cpu or L2) into its low power mode,
the index of the first command in the sequence is set in the SPM_CTL
register. When the core executes ARM wfi instruction, it triggers the
SPM state machine to start executing from that index. The SPM state
machine waits until the interrupt occurs and starts executing the rest
of the sequence until it hits the end of the sequence. The end of the
sequence jumps the core out of its low power mode.

Add support for an idle driver to set up the SPM to place the core in
Standby or Standalone power collapse mode when the core is idle.

Based on work by: Mahesh Sivasubramanian <msivasub@codeaurora.org>,
Ai Li <ali@codeaurora.org>, Praveen Chidambaram <pchidamb@codeaurora.org>
Original tree available at -
git://codeaurora.org/quic/la/kernel/msm-3.10.git

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 .../devicetree/bindings/arm/msm/qcom,saw2.txt      |  31 +-
 drivers/soc/qcom/Kconfig                           |   7 +
 drivers/soc/qcom/Makefile                          |   1 +
 drivers/soc/qcom/spm.c                             | 422 +++++++++++++++++++++
 4 files changed, 455 insertions(+), 6 deletions(-)
 create mode 100644 drivers/soc/qcom/spm.c

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
index 1505fb8..690c3c0 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
@@ -2,11 +2,20 @@ SPM AVS Wrapper 2 (SAW2)
 
 The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
 Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
-micro-controller that transitions a piece of hardware (like a processor or
+power-controller that transitions a piece of hardware (like a processor or
 subsystem) into and out of low power modes via a direct connection to
 the PMIC. It can also be wired up to interact with other processors in the
 system, notifying them when a low power state is entered or exited.
 
+Multiple revisions of the SAW hardware are supported using these Device Nodes.
+SAW2 revisions differ in the register offset and configuration data. Also, the
+same revision of the SAW in different SoCs may have different configuration
+data due the the differences in hardware capabilities. Hence the SoC name, the
+version of the SAW hardware in that SoC and the distinction between cpu (big
+or Little) or cache, may be needed to uniquely identify the SAW register
+configuration and initialization data. The compatible string is used to
+indicate this parameter.
+
 PROPERTIES
 
 - compatible:
@@ -14,10 +23,13 @@ PROPERTIES
 	Value type: <string>
 	Definition: shall contain "qcom,saw2". A more specific value should be
 		    one of:
-			 "qcom,saw2-v1"
-			 "qcom,saw2-v1.1"
-			 "qcom,saw2-v2"
-			 "qcom,saw2-v2.1"
+			"qcom,saw2-v1"
+			"qcom,saw2-v1.1"
+			"qcom,saw2-v2"
+			"qcom,saw2-v2.1"
+			"qcom,apq8064-saw2-v1.1-cpu"
+			"qcom,msm8974-saw2-v2.1-cpu"
+			"qcom,apq8084-saw2-v2.1-cpu"
 
 - reg:
 	Usage: required
@@ -26,10 +38,17 @@ PROPERTIES
 		    the register region. An optional second element specifies
 		    the base address and size of the alias register region.
 
+- regulator:
+	Usage: optional
+	Value type: boolean
+	Definition: Indicates that this SPM device acts as a regulator device
+			device for the core (CPU or Cache) the SPM is attached
+			to.
 
 Example:
 
-	regulator at 2099000 {
+	power-controller at 2099000 {
 		compatible = "qcom,saw2";
 		reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+		regulator;
 	};
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 7bd2c94..628bcba 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -9,3 +9,10 @@ config QCOM_GSBI
           functions for connecting the underlying serial UART, SPI, and I2C
           devices to the output pins.
 
+config QCOM_PM
+	bool "Qualcomm Power Management"
+	depends on ARCH_QCOM
+	help
+	  QCOM Platform specific power driver to manage cores and L2 low power
+	  modes. It interface with various system drivers to put the cores in
+	  low power modes.
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 4389012..931d385 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_QCOM_GSBI)	+=	qcom_gsbi.o
+obj-$(CONFIG_QCOM_PM)	+=	spm.o
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
new file mode 100644
index 0000000..85b33ee
--- /dev/null
+++ b/drivers/soc/qcom/spm.c
@@ -0,0 +1,422 @@
+/*
+ * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014,2015, Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/qcom_scm.h>
+
+#include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+
+#define MAX_PMIC_DATA		2
+#define MAX_SEQ_DATA		64
+#define SPM_CTL_INDEX		0x7f
+#define SPM_CTL_INDEX_SHIFT	4
+#define SPM_CTL_EN		BIT(0)
+
+enum pm_sleep_mode {
+	PM_SLEEP_MODE_STBY,
+	PM_SLEEP_MODE_RET,
+	PM_SLEEP_MODE_SPC,
+	PM_SLEEP_MODE_PC,
+	PM_SLEEP_MODE_NR,
+};
+
+enum spm_reg {
+	SPM_REG_CFG,
+	SPM_REG_SPM_CTL,
+	SPM_REG_DLY,
+	SPM_REG_PMIC_DLY,
+	SPM_REG_PMIC_DATA_0,
+	SPM_REG_PMIC_DATA_1,
+	SPM_REG_VCTL,
+	SPM_REG_SEQ_ENTRY,
+	SPM_REG_SPM_STS,
+	SPM_REG_PMIC_STS,
+	SPM_REG_NR,
+};
+
+struct spm_reg_data {
+	const u8 *reg_offset;
+	u32 spm_cfg;
+	u32 spm_dly;
+	u32 pmic_dly;
+	u32 pmic_data[MAX_PMIC_DATA];
+	u8 seq[MAX_SEQ_DATA];
+	u8 start_index[PM_SLEEP_MODE_NR];
+};
+
+struct spm_driver_data {
+	void __iomem *reg_base;
+	const struct spm_reg_data *reg_data;
+};
+
+static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = {
+	[SPM_REG_CFG]		= 0x08,
+	[SPM_REG_SPM_CTL]	= 0x30,
+	[SPM_REG_DLY]		= 0x34,
+	[SPM_REG_SEQ_ENTRY]	= 0x80,
+};
+
+/* SPM register data for 8974, 8084 */
+static const struct spm_reg_data spm_reg_8974_8084_cpu  = {
+	.reg_offset = spm_reg_offset_v2_1,
+	.spm_cfg = 0x1,
+	.spm_dly = 0x3C102800,
+	.seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
+		0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
+		0x0F },
+	.start_index[PM_SLEEP_MODE_STBY] = 0,
+	.start_index[PM_SLEEP_MODE_SPC] = 3,
+};
+
+static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = {
+	[SPM_REG_CFG]		= 0x08,
+	[SPM_REG_SPM_CTL]	= 0x20,
+	[SPM_REG_PMIC_DLY]	= 0x24,
+	[SPM_REG_PMIC_DATA_0]	= 0x28,
+	[SPM_REG_PMIC_DATA_1]	= 0x2C,
+	[SPM_REG_SEQ_ENTRY]	= 0x80,
+};
+
+/* SPM register data for 8064 */
+static const struct spm_reg_data spm_reg_8064_cpu = {
+	.reg_offset = spm_reg_offset_v1_1,
+	.spm_cfg = 0x1F,
+	.pmic_dly = 0x02020004,
+	.pmic_data[0] = 0x0084009C,
+	.pmic_data[1] = 0x00A4001C,
+	.seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
+		0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
+	.start_index[PM_SLEEP_MODE_STBY] = 0,
+	.start_index[PM_SLEEP_MODE_SPC] = 2,
+};
+
+static DEFINE_PER_CPU(struct spm_driver_data *, cpu_spm_drv);
+
+typedef int (*idle_fn)(int);
+static DEFINE_PER_CPU(idle_fn*, qcom_idle_ops);
+
+static inline void spm_register_write(struct spm_driver_data *drv,
+					enum spm_reg reg, u32 val)
+{
+	if (drv->reg_data->reg_offset[reg])
+		writel_relaxed(val, drv->reg_base +
+				drv->reg_data->reg_offset[reg]);
+}
+
+/* Ensure a guaranteed write, before return */
+static inline void spm_register_write_sync(struct spm_driver_data *drv,
+					enum spm_reg reg, u32 val)
+{
+	u32 ret;
+
+	if (!drv->reg_data->reg_offset[reg])
+		return;
+
+	do {
+		writel_relaxed(val, drv->reg_base +
+				drv->reg_data->reg_offset[reg]);
+		ret = readl_relaxed(drv->reg_base +
+				drv->reg_data->reg_offset[reg]);
+		if (ret == val)
+			break;
+		cpu_relax();
+	} while (1);
+}
+
+static inline u32 spm_register_read(struct spm_driver_data *drv,
+					enum spm_reg reg)
+{
+	return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
+}
+
+static void spm_set_low_power_mode(enum pm_sleep_mode mode)
+{
+	struct spm_driver_data *drv = per_cpu(cpu_spm_drv,
+						smp_processor_id());
+	u32 start_index;
+	u32 ctl_val;
+
+	start_index = drv->reg_data->start_index[mode];
+
+	ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
+	ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
+	ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
+	ctl_val |= SPM_CTL_EN;
+	spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
+}
+
+static int qcom_pm_collapse(unsigned long int unused)
+{
+	qcom_scm_cpu_power_down(QCOM_SCM_L2_ON);
+
+	/*
+	 * Returns here only if there was a pending interrupt and we did not
+	 * power down as a result.
+	 */
+	return -1;
+}
+
+static int qcom_cpu_standby(int cpuarg)
+{
+	spm_set_low_power_mode(PM_SLEEP_MODE_STBY);
+	cpu_do_idle();
+
+	return 0;
+}
+
+static int qcom_cpu_spc(int cpu)
+{
+	int ret;
+
+	spm_set_low_power_mode(PM_SLEEP_MODE_SPC);
+	cpu_pm_enter();
+	ret = cpu_suspend(0, qcom_pm_collapse);
+	/*
+	 * ARM common code may execute WFI, and if the SPM mode is not reset,
+	 * then we may accidently do power down state.
+	 * SPM is configured to reset to do STBY, but that relies on the
+	 * SPM state machine to be executed. When an interrupt is pending as we
+	 * enter idle state, SPM would not execute its state machine, so the
+	 * SPM may remain configured to do power down state.
+	 * Reset the state back to standby.
+	 */
+	spm_set_low_power_mode(PM_SLEEP_MODE_STBY);
+	cpu_pm_exit();
+
+	return ret;
+}
+
+static int qcom_idle_enter(int cpu, unsigned long index)
+{
+	if (!per_cpu(qcom_idle_ops, cpu)[index])
+		return -EOPNOTSUPP;
+
+	return per_cpu(qcom_idle_ops, cpu)[index](cpu);
+}
+
+const struct of_device_id qcom_idle_state_match[] __initconst = {
+	{ .compatible = "qcom,idle-state-stby", .data = qcom_cpu_standby },
+	{ .compatible = "qcom,idle-state-spc", .data = qcom_cpu_spc },
+	{ },
+};
+
+static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
+{
+	const struct of_device_id *match_id;
+	struct device_node *state_node;
+	int i;
+	int state_count = 0;
+	idle_fn idle_fns[CPUIDLE_STATE_MAX];
+	idle_fn *fns;
+	cpumask_t mask;
+	bool use_scm_power_down = false;
+
+	for (i = 0; ; i++) {
+		state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
+		if (!state_node)
+			break;
+
+		if (!of_device_is_available(state_node))
+			continue;
+
+		if (i == CPUIDLE_STATE_MAX) {
+			pr_warn("%s: cpuidle states reached max possible\n",
+					__func__);
+			break;
+		}
+
+		match_id = of_match_node(qcom_idle_state_match, state_node);
+		if (!match_id)
+			return -ENODEV;
+
+		idle_fns[state_count] = match_id->data;
+
+		/* Check if any of the states allow power down */
+		if (match_id->data == qcom_cpu_spc)
+			use_scm_power_down = true;
+
+		state_count++;
+	}
+
+	if (!state_count) {
+		pr_warn("No idle ops founds for cpu %d\n", cpu);
+		return -ENODEV;
+	}
+
+	fns = kcalloc(state_count, sizeof(*fns), GFP_KERNEL);
+	if (!fns)
+		return -ENOMEM;
+
+	for (i = 0; i < state_count; i++)
+		fns[i] = idle_fns[i];
+
+	if (use_scm_power_down) {
+		/* We have atlease one power down mode */
+		cpumask_clear(&mask);
+		cpumask_set_cpu(cpu, &mask);
+		qcom_scm_set_warm_boot_addr(cpu_resume, &mask);
+	}
+
+	per_cpu(qcom_idle_ops, cpu) = fns;
+
+	/*
+	 * Condition: cpuidle_driver_register() needs to happen before
+	 * cpuidle_register_device().
+	 * Check if the SPM probe has happened -
+	 * - If SPM probed successfully before arm_idle_init(), then defer
+	 *   the registration of cpuidle_device back to arm_idle_init()
+	 * - If the SPM probe happens in the future, then let the SPM probe
+	 *   register the cpuidle device, return -ENOSYS.
+	 */
+	return per_cpu(cpu_spm_drv, cpu) ? 0 : -ENOSYS;
+}
+
+struct cpuidle_ops qcom_kpss_v1_cpuidle_ops __initdata = {
+	.name = "qcom,kpss-acc-v1",
+	.suspend = qcom_idle_enter,
+	.init = qcom_cpuidle_init,
+};
+
+struct cpuidle_ops qcom_kpss_v2_cpuidle_ops __initdata = {
+	.name = "qcom,kpss-acc-v2",
+	.suspend = qcom_idle_enter,
+	.init = qcom_cpuidle_init,
+};
+
+static struct spm_driver_data *spm_get_drv(struct platform_device *pdev,
+		int *spm_cpu)
+{
+	struct spm_driver_data *drv = NULL;
+	struct device_node *cpu_node, *saw_node;
+	int cpu;
+	bool found;
+
+	for_each_possible_cpu(cpu) {
+		cpu_node = of_cpu_device_node_get(cpu);
+		if (!cpu_node)
+			continue;
+		saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
+		found = (saw_node == pdev->dev.of_node);
+		of_node_put(saw_node);
+		of_node_put(cpu_node);
+		if (found)
+			break;
+	}
+
+	if (found) {
+		drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
+		if (drv)
+			*spm_cpu = cpu;
+	}
+
+	return drv;
+}
+
+static const struct of_device_id spm_match_table[] = {
+	{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
+	  .data = &spm_reg_8974_8084_cpu },
+	{ .compatible = "qcom,apq8084-saw2-v2.1-cpu",
+	  .data = &spm_reg_8974_8084_cpu },
+	{ .compatible = "qcom,apq8064-saw2-v1.1-cpu",
+	  .data = &spm_reg_8064_cpu },
+	{ },
+};
+
+static int spm_dev_probe(struct platform_device *pdev)
+{
+	struct spm_driver_data *drv;
+	struct resource *res;
+	const struct of_device_id *match_id;
+	void __iomem *addr;
+	int cpu;
+	int ret = 0;
+
+	drv = spm_get_drv(pdev, &cpu);
+	if (!drv)
+		return -EINVAL;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	drv->reg_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(drv->reg_base))
+		return PTR_ERR(drv->reg_base);
+
+	match_id = of_match_node(spm_match_table, pdev->dev.of_node);
+	if (!match_id)
+		return -ENODEV;
+
+	drv->reg_data = match_id->data;
+
+	/* Write the SPM sequences first.. */
+	addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
+	__iowrite32_copy(addr, drv->reg_data->seq,
+			ARRAY_SIZE(drv->reg_data->seq) / 4);
+
+	/*
+	 * ..and then the control registers.
+	 * On some SoC if the control registers are written first and if the
+	 * CPU was held in reset, the reset signal could trigger the SPM state
+	 * machine, before the sequences are completely written.
+	 */
+	spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
+	spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
+	spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
+	spm_register_write(drv, SPM_REG_PMIC_DATA_0,
+				drv->reg_data->pmic_data[0]);
+	spm_register_write(drv, SPM_REG_PMIC_DATA_1,
+				drv->reg_data->pmic_data[1]);
+
+	per_cpu(cpu_spm_drv, cpu) = drv;
+
+	/* If the cpuidle ops have already been registered with cpuidle,
+	 * then we have been waiting on this SPM probe to register the
+	 * cpuidle device.
+	 */
+	if (per_cpu(qcom_idle_ops, cpu)) {
+		struct cpuidle_device *dev;
+
+		dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
+		if (!dev)
+			return -ENOMEM;
+		dev->cpu = cpu;
+		ret = cpuidle_register_device(dev);
+	}
+
+	return ret;
+}
+
+static struct platform_driver spm_driver = {
+	.probe = spm_dev_probe,
+	.driver = {
+		.name = "saw",
+		.of_match_table = spm_match_table,
+	},
+};
+module_platform_driver(spm_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("SAW power controller driver");
+MODULE_ALIAS("platform:saw");
-- 
2.1.0

Re: [RFC PATCH v15 02/11] ARM: qcom: Add Subsystem Power Manager (SPM) driver

[Kumar Gala]

On Mar 9, 2015, at 10:16 AM, Lina Iyer <lina.iyer@linaro.org> wrote:

> SPM is a hardware block that controls the peripheral logic surrounding
> the application cores (cpu/l$). When the core executes WFI instruction,
> the SPM takes over the putting the core in low power state as
> configured. The wake up for the SPM is an interrupt at the GIC, which
> then completes the rest of low power mode sequence and brings the core
> out of low power mode.
> 
> The SPM has a set of control registers that configure the SPMs
> individually based on the type of the core and the runtime conditions.
> SPM is a finite state machine block to which a sequence is provided and
> it interprets the bytes and executes them in sequence. Each low power
> mode that the core can enter into is provided to the SPM as a sequence.
> 
> Configure the SPM to set the core (cpu or L2) into its low power mode,
> the index of the first command in the sequence is set in the SPM_CTL
> register. When the core executes ARM wfi instruction, it triggers the
> SPM state machine to start executing from that index. The SPM state
> machine waits until the interrupt occurs and starts executing the rest
> of the sequence until it hits the end of the sequence. The end of the
> sequence jumps the core out of its low power mode.
> 
> Add support for an idle driver to set up the SPM to place the core in
> Standby or Standalone power collapse mode when the core is idle.
> 
> Based on work by: Mahesh Sivasubramanian <msivasub@codeaurora.org>,
> Ai Li <ali@codeaurora.org>, Praveen Chidambaram <pchidamb@codeaurora.org>
> Original tree available at -
> git://codeaurora.org/quic/la/kernel/msm-3.10.git
> 
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Kevin Hilman <khilman@linaro.org>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
> ---
> .../devicetree/bindings/arm/msm/qcom,saw2.txt      |  31 +-
> drivers/soc/qcom/Kconfig                           |   7 +
> drivers/soc/qcom/Makefile                          |   1 +
> drivers/soc/qcom/spm.c                             | 422 +++++++++++++++++++++
> 4 files changed, 455 insertions(+), 6 deletions(-)
> create mode 100644 drivers/soc/qcom/spm.c
> 
> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
> index 1505fb8..690c3c0 100644
> --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
> @@ -2,11 +2,20 @@ SPM AVS Wrapper 2 (SAW2)
> 
> The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
> Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
> -micro-controller that transitions a piece of hardware (like a processor or
> +power-controller that transitions a piece of hardware (like a processor or
> subsystem) into and out of low power modes via a direct connection to
> the PMIC. It can also be wired up to interact with other processors in the
> system, notifying them when a low power state is entered or exited.
> 
> +Multiple revisions of the SAW hardware are supported using these Device Nodes.
> +SAW2 revisions differ in the register offset and configuration data. Also, the
> +same revision of the SAW in different SoCs may have different configuration
> +data due the the differences in hardware capabilities. Hence the SoC name, the
> +version of the SAW hardware in that SoC and the distinction between cpu (big
> +or Little) or cache, may be needed to uniquely identify the SAW register
> +configuration and initialization data. The compatible string is used to
> +indicate this parameter.
> +
> PROPERTIES
> 
> - compatible:
> @@ -14,10 +23,13 @@ PROPERTIES
> 	Value type: <string>
> 	Definition: shall contain "qcom,saw2". A more specific value should be
> 		    one of:
> -			 "qcom,saw2-v1"
> -			 "qcom,saw2-v1.1"
> -			 "qcom,saw2-v2"
> -			 "qcom,saw2-v2.1"
> +			"qcom,saw2-v1"
> +			"qcom,saw2-v1.1"
> +			"qcom,saw2-v2"
> +			"qcom,saw2-v2.1"
> +			"qcom,apq8064-saw2-v1.1-cpu"
> +			"qcom,msm8974-saw2-v2.1-cpu"
> +			"qcom,apq8084-saw2-v2.1-cpu”
> 

We don’t seem to use the "qcom,saw2-v1*” variants so should we just drop them?


> - reg:
> 	Usage: required
> @@ -26,10 +38,17 @@ PROPERTIES
> 		    the register region. An optional second element specifies
> 		    the base address and size of the alias register region.
> 
> +- regulator:
> +	Usage: optional
> +	Value type: boolean
> +	Definition: Indicates that this SPM device acts as a regulator device
> +			device for the core (CPU or Cache) the SPM is attached
> +			to.
> 
> Example:
> 
> -	regulator@2099000 {
> +	power-controller@2099000 {
> 		compatible = "qcom,saw2";
> 		reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
> +		regulator;
> 	};

- k

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[RFC PATCH v15 02/11] ARM: qcom: Add Subsystem Power Manager (SPM) driver

[Kumar Gala]

On Mar 9, 2015, at 10:16 AM, Lina Iyer <lina.iyer@linaro.org> wrote:

> SPM is a hardware block that controls the peripheral logic surrounding
> the application cores (cpu/l$). When the core executes WFI instruction,
> the SPM takes over the putting the core in low power state as
> configured. The wake up for the SPM is an interrupt at the GIC, which
> then completes the rest of low power mode sequence and brings the core
> out of low power mode.
> 
> The SPM has a set of control registers that configure the SPMs
> individually based on the type of the core and the runtime conditions.
> SPM is a finite state machine block to which a sequence is provided and
> it interprets the bytes and executes them in sequence. Each low power
> mode that the core can enter into is provided to the SPM as a sequence.
> 
> Configure the SPM to set the core (cpu or L2) into its low power mode,
> the index of the first command in the sequence is set in the SPM_CTL
> register. When the core executes ARM wfi instruction, it triggers the
> SPM state machine to start executing from that index. The SPM state
> machine waits until the interrupt occurs and starts executing the rest
> of the sequence until it hits the end of the sequence. The end of the
> sequence jumps the core out of its low power mode.
> 
> Add support for an idle driver to set up the SPM to place the core in
> Standby or Standalone power collapse mode when the core is idle.
> 
> Based on work by: Mahesh Sivasubramanian <msivasub@codeaurora.org>,
> Ai Li <ali@codeaurora.org>, Praveen Chidambaram <pchidamb@codeaurora.org>
> Original tree available at -
> git://codeaurora.org/quic/la/kernel/msm-3.10.git
> 
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Kevin Hilman <khilman@linaro.org>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
> ---
> .../devicetree/bindings/arm/msm/qcom,saw2.txt      |  31 +-
> drivers/soc/qcom/Kconfig                           |   7 +
> drivers/soc/qcom/Makefile                          |   1 +
> drivers/soc/qcom/spm.c                             | 422 +++++++++++++++++++++
> 4 files changed, 455 insertions(+), 6 deletions(-)
> create mode 100644 drivers/soc/qcom/spm.c
> 
> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
> index 1505fb8..690c3c0 100644
> --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
> @@ -2,11 +2,20 @@ SPM AVS Wrapper 2 (SAW2)
> 
> The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
> Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
> -micro-controller that transitions a piece of hardware (like a processor or
> +power-controller that transitions a piece of hardware (like a processor or
> subsystem) into and out of low power modes via a direct connection to
> the PMIC. It can also be wired up to interact with other processors in the
> system, notifying them when a low power state is entered or exited.
> 
> +Multiple revisions of the SAW hardware are supported using these Device Nodes.
> +SAW2 revisions differ in the register offset and configuration data. Also, the
> +same revision of the SAW in different SoCs may have different configuration
> +data due the the differences in hardware capabilities. Hence the SoC name, the
> +version of the SAW hardware in that SoC and the distinction between cpu (big
> +or Little) or cache, may be needed to uniquely identify the SAW register
> +configuration and initialization data. The compatible string is used to
> +indicate this parameter.
> +
> PROPERTIES
> 
> - compatible:
> @@ -14,10 +23,13 @@ PROPERTIES
> 	Value type: <string>
> 	Definition: shall contain "qcom,saw2". A more specific value should be
> 		    one of:
> -			 "qcom,saw2-v1"
> -			 "qcom,saw2-v1.1"
> -			 "qcom,saw2-v2"
> -			 "qcom,saw2-v2.1"
> +			"qcom,saw2-v1"
> +			"qcom,saw2-v1.1"
> +			"qcom,saw2-v2"
> +			"qcom,saw2-v2.1"
> +			"qcom,apq8064-saw2-v1.1-cpu"
> +			"qcom,msm8974-saw2-v2.1-cpu"
> +			"qcom,apq8084-saw2-v2.1-cpu?
> 

We don?t seem to use the "qcom,saw2-v1*? variants so should we just drop them?


> - reg:
> 	Usage: required
> @@ -26,10 +38,17 @@ PROPERTIES
> 		    the register region. An optional second element specifies
> 		    the base address and size of the alias register region.
> 
> +- regulator:
> +	Usage: optional
> +	Value type: boolean
> +	Definition: Indicates that this SPM device acts as a regulator device
> +			device for the core (CPU or Cache) the SPM is attached
> +			to.
> 
> Example:
> 
> -	regulator at 2099000 {
> +	power-controller at 2099000 {
> 		compatible = "qcom,saw2";
> 		reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
> +		regulator;
> 	};

- k

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [RFC PATCH v15 02/11] ARM: qcom: Add Subsystem Power Manager (SPM) driver

[Lina Iyer]

On Tue, Mar 10 2015 at 11:26 -0600, Kumar Gala wrote:
>
>On Mar 9, 2015, at 10:16 AM, Lina Iyer <lina.iyer@linaro.org> wrote:
>
>> SPM is a hardware block that controls the peripheral logic surrounding
>> the application cores (cpu/l$). When the core executes WFI instruction,
>> the SPM takes over the putting the core in low power state as
>> configured. The wake up for the SPM is an interrupt at the GIC, which
>> then completes the rest of low power mode sequence and brings the core
>> out of low power mode.
>>
>> The SPM has a set of control registers that configure the SPMs
>> individually based on the type of the core and the runtime conditions.
>> SPM is a finite state machine block to which a sequence is provided and
>> it interprets the bytes and executes them in sequence. Each low power
>> mode that the core can enter into is provided to the SPM as a sequence.
>>
>> Configure the SPM to set the core (cpu or L2) into its low power mode,
>> the index of the first command in the sequence is set in the SPM_CTL
>> register. When the core executes ARM wfi instruction, it triggers the
>> SPM state machine to start executing from that index. The SPM state
>> machine waits until the interrupt occurs and starts executing the rest
>> of the sequence until it hits the end of the sequence. The end of the
>> sequence jumps the core out of its low power mode.
>>
>> Add support for an idle driver to set up the SPM to place the core in
>> Standby or Standalone power collapse mode when the core is idle.
>>
>> Based on work by: Mahesh Sivasubramanian <msivasub@codeaurora.org>,
>> Ai Li <ali@codeaurora.org>, Praveen Chidambaram <pchidamb@codeaurora.org>
>> Original tree available at -
>> git://codeaurora.org/quic/la/kernel/msm-3.10.git
>>
>> Cc: Stephen Boyd <sboyd@codeaurora.org>
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Cc: Kevin Hilman <khilman@linaro.org>
>> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
>> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
>> ---
>> .../devicetree/bindings/arm/msm/qcom,saw2.txt      |  31 +-
>> drivers/soc/qcom/Kconfig                           |   7 +
>> drivers/soc/qcom/Makefile                          |   1 +
>> drivers/soc/qcom/spm.c                             | 422 +++++++++++++++++++++
>> 4 files changed, 455 insertions(+), 6 deletions(-)
>> create mode 100644 drivers/soc/qcom/spm.c
>>
>> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
>> index 1505fb8..690c3c0 100644
>> --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
>> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
>> @@ -2,11 +2,20 @@ SPM AVS Wrapper 2 (SAW2)
>>
>> The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
>> Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
>> -micro-controller that transitions a piece of hardware (like a processor or
>> +power-controller that transitions a piece of hardware (like a processor or
>> subsystem) into and out of low power modes via a direct connection to
>> the PMIC. It can also be wired up to interact with other processors in the
>> system, notifying them when a low power state is entered or exited.
>>
>> +Multiple revisions of the SAW hardware are supported using these Device Nodes.
>> +SAW2 revisions differ in the register offset and configuration data. Also, the
>> +same revision of the SAW in different SoCs may have different configuration
>> +data due the the differences in hardware capabilities. Hence the SoC name, the
>> +version of the SAW hardware in that SoC and the distinction between cpu (big
>> +or Little) or cache, may be needed to uniquely identify the SAW register
>> +configuration and initialization data. The compatible string is used to
>> +indicate this parameter.
>> +
>> PROPERTIES
>>
>> - compatible:
>> @@ -14,10 +23,13 @@ PROPERTIES
>> 	Value type: <string>
>> 	Definition: shall contain "qcom,saw2". A more specific value should be
>> 		    one of:
>> -			 "qcom,saw2-v1"
>> -			 "qcom,saw2-v1.1"
>> -			 "qcom,saw2-v2"
>> -			 "qcom,saw2-v2.1"
>> +			"qcom,saw2-v1"
>> +			"qcom,saw2-v1.1"
>> +			"qcom,saw2-v2"
>> +			"qcom,saw2-v2.1"
>> +			"qcom,apq8064-saw2-v1.1-cpu"
>> +			"qcom,msm8974-saw2-v2.1-cpu"
>> +			"qcom,apq8084-saw2-v2.1-cpu”
>>
>
>We don’t seem to use the "qcom,saw2-v1*” variants so should we just drop them?

Sure. Will fix in the next.
>
>
>> - reg:
>> 	Usage: required
>> @@ -26,10 +38,17 @@ PROPERTIES
>> 		    the register region. An optional second element specifies
>> 		    the base address and size of the alias register region.
>>
>> +- regulator:
>> +	Usage: optional
>> +	Value type: boolean
>> +	Definition: Indicates that this SPM device acts as a regulator device
>> +			device for the core (CPU or Cache) the SPM is attached
>> +			to.
>>
>> Example:
>>
>> -	regulator@2099000 {
>> +	power-controller@2099000 {
>> 		compatible = "qcom,saw2";
>> 		reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
>> +		regulator;
>> 	};
>
>- k
>
>-- 
>Qualcomm Innovation Center, Inc.
>The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>a Linux Foundation Collaborative Project
>

[RFC PATCH v15 02/11] ARM: qcom: Add Subsystem Power Manager (SPM) driver

[Lina Iyer]

On Tue, Mar 10 2015 at 11:26 -0600, Kumar Gala wrote:
>
>On Mar 9, 2015, at 10:16 AM, Lina Iyer <lina.iyer@linaro.org> wrote:
>
>> SPM is a hardware block that controls the peripheral logic surrounding
>> the application cores (cpu/l$). When the core executes WFI instruction,
>> the SPM takes over the putting the core in low power state as
>> configured. The wake up for the SPM is an interrupt at the GIC, which
>> then completes the rest of low power mode sequence and brings the core
>> out of low power mode.
>>
>> The SPM has a set of control registers that configure the SPMs
>> individually based on the type of the core and the runtime conditions.
>> SPM is a finite state machine block to which a sequence is provided and
>> it interprets the bytes and executes them in sequence. Each low power
>> mode that the core can enter into is provided to the SPM as a sequence.
>>
>> Configure the SPM to set the core (cpu or L2) into its low power mode,
>> the index of the first command in the sequence is set in the SPM_CTL
>> register. When the core executes ARM wfi instruction, it triggers the
>> SPM state machine to start executing from that index. The SPM state
>> machine waits until the interrupt occurs and starts executing the rest
>> of the sequence until it hits the end of the sequence. The end of the
>> sequence jumps the core out of its low power mode.
>>
>> Add support for an idle driver to set up the SPM to place the core in
>> Standby or Standalone power collapse mode when the core is idle.
>>
>> Based on work by: Mahesh Sivasubramanian <msivasub@codeaurora.org>,
>> Ai Li <ali@codeaurora.org>, Praveen Chidambaram <pchidamb@codeaurora.org>
>> Original tree available at -
>> git://codeaurora.org/quic/la/kernel/msm-3.10.git
>>
>> Cc: Stephen Boyd <sboyd@codeaurora.org>
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Cc: Kevin Hilman <khilman@linaro.org>
>> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
>> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
>> ---
>> .../devicetree/bindings/arm/msm/qcom,saw2.txt      |  31 +-
>> drivers/soc/qcom/Kconfig                           |   7 +
>> drivers/soc/qcom/Makefile                          |   1 +
>> drivers/soc/qcom/spm.c                             | 422 +++++++++++++++++++++
>> 4 files changed, 455 insertions(+), 6 deletions(-)
>> create mode 100644 drivers/soc/qcom/spm.c
>>
>> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
>> index 1505fb8..690c3c0 100644
>> --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
>> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
>> @@ -2,11 +2,20 @@ SPM AVS Wrapper 2 (SAW2)
>>
>> The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
>> Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
>> -micro-controller that transitions a piece of hardware (like a processor or
>> +power-controller that transitions a piece of hardware (like a processor or
>> subsystem) into and out of low power modes via a direct connection to
>> the PMIC. It can also be wired up to interact with other processors in the
>> system, notifying them when a low power state is entered or exited.
>>
>> +Multiple revisions of the SAW hardware are supported using these Device Nodes.
>> +SAW2 revisions differ in the register offset and configuration data. Also, the
>> +same revision of the SAW in different SoCs may have different configuration
>> +data due the the differences in hardware capabilities. Hence the SoC name, the
>> +version of the SAW hardware in that SoC and the distinction between cpu (big
>> +or Little) or cache, may be needed to uniquely identify the SAW register
>> +configuration and initialization data. The compatible string is used to
>> +indicate this parameter.
>> +
>> PROPERTIES
>>
>> - compatible:
>> @@ -14,10 +23,13 @@ PROPERTIES
>> 	Value type: <string>
>> 	Definition: shall contain "qcom,saw2". A more specific value should be
>> 		    one of:
>> -			 "qcom,saw2-v1"
>> -			 "qcom,saw2-v1.1"
>> -			 "qcom,saw2-v2"
>> -			 "qcom,saw2-v2.1"
>> +			"qcom,saw2-v1"
>> +			"qcom,saw2-v1.1"
>> +			"qcom,saw2-v2"
>> +			"qcom,saw2-v2.1"
>> +			"qcom,apq8064-saw2-v1.1-cpu"
>> +			"qcom,msm8974-saw2-v2.1-cpu"
>> +			"qcom,apq8084-saw2-v2.1-cpu?
>>
>
>We don?t seem to use the "qcom,saw2-v1*? variants so should we just drop them?

Sure. Will fix in the next.
>
>
>> - reg:
>> 	Usage: required
>> @@ -26,10 +38,17 @@ PROPERTIES
>> 		    the register region. An optional second element specifies
>> 		    the base address and size of the alias register region.
>>
>> +- regulator:
>> +	Usage: optional
>> +	Value type: boolean
>> +	Definition: Indicates that this SPM device acts as a regulator device
>> +			device for the core (CPU or Cache) the SPM is attached
>> +			to.
>>
>> Example:
>>
>> -	regulator at 2099000 {
>> +	power-controller at 2099000 {
>> 		compatible = "qcom,saw2";
>> 		reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
>> +		regulator;
>> 	};
>
>- k
>
>-- 
>Qualcomm Innovation Center, Inc.
>The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>a Linux Foundation Collaborative Project
>

Re: [RFC PATCH v15 02/11] ARM: qcom: Add Subsystem Power Manager (SPM) driver

[Lina Iyer]

On Mon, Mar 09 2015 at 09:17 -0600, Lina Iyer wrote:

[...]

>+static int qcom_pm_collapse(unsigned long int unused)
>+{
>+	qcom_scm_cpu_power_down(QCOM_SCM_L2_ON);

Rebase against latest SCM patches. Change to QCOM_SCM_CPU_PWR_DOWN_L2_ON.
>+
>+	/*
>+	 * Returns here only if there was a pending interrupt and we did not
>+	 * power down as a result.
>+	 */
>+	return -1;
>+}
>+
>+static int qcom_cpu_standby(int cpuarg)
>+{
>+	spm_set_low_power_mode(PM_SLEEP_MODE_STBY);
>+	cpu_do_idle();
>+
>+	return 0;
>+}
>+
>+static int qcom_cpu_spc(int cpu)
>+{
>+	int ret;
>+
>+	spm_set_low_power_mode(PM_SLEEP_MODE_SPC);
>+	cpu_pm_enter();
Remove this. This is now done by cpuidle driver.

>+	ret = cpu_suspend(0, qcom_pm_collapse);
>+	/*
>+	 * ARM common code may execute WFI, and if the SPM mode is not reset,
>+	 * then we may accidently do power down state.
>+	 * SPM is configured to reset to do STBY, but that relies on the
>+	 * SPM state machine to be executed. When an interrupt is pending as we
>+	 * enter idle state, SPM would not execute its state machine, so the
>+	 * SPM may remain configured to do power down state.
>+	 * Reset the state back to standby.
>+	 */
>+	spm_set_low_power_mode(PM_SLEEP_MODE_STBY);
>+	cpu_pm_exit();
And this..

[RFC PATCH v15 02/11] ARM: qcom: Add Subsystem Power Manager (SPM) driver

[Lina Iyer]

On Mon, Mar 09 2015 at 09:17 -0600, Lina Iyer wrote:

[...]

>+static int qcom_pm_collapse(unsigned long int unused)
>+{
>+	qcom_scm_cpu_power_down(QCOM_SCM_L2_ON);

Rebase against latest SCM patches. Change to QCOM_SCM_CPU_PWR_DOWN_L2_ON.
>+
>+	/*
>+	 * Returns here only if there was a pending interrupt and we did not
>+	 * power down as a result.
>+	 */
>+	return -1;
>+}
>+
>+static int qcom_cpu_standby(int cpuarg)
>+{
>+	spm_set_low_power_mode(PM_SLEEP_MODE_STBY);
>+	cpu_do_idle();
>+
>+	return 0;
>+}
>+
>+static int qcom_cpu_spc(int cpu)
>+{
>+	int ret;
>+
>+	spm_set_low_power_mode(PM_SLEEP_MODE_SPC);
>+	cpu_pm_enter();
Remove this. This is now done by cpuidle driver.

>+	ret = cpu_suspend(0, qcom_pm_collapse);
>+	/*
>+	 * ARM common code may execute WFI, and if the SPM mode is not reset,
>+	 * then we may accidently do power down state.
>+	 * SPM is configured to reset to do STBY, but that relies on the
>+	 * SPM state machine to be executed. When an interrupt is pending as we
>+	 * enter idle state, SPM would not execute its state machine, so the
>+	 * SPM may remain configured to do power down state.
>+	 * Reset the state back to standby.
>+	 */
>+	spm_set_low_power_mode(PM_SLEEP_MODE_STBY);
>+	cpu_pm_exit();
And this..

Re: [RFC PATCH v15 02/11] ARM: qcom: Add Subsystem Power Manager (SPM) driver

[Stephen Boyd]

On 03/09/15 08:16, Lina Iyer wrote:
> +
> +static int qcom_idle_enter(int cpu, unsigned long index)
> +{
> +	if (!per_cpu(qcom_idle_ops, cpu)[index])
> +		return -EOPNOTSUPP;

Is this case still happening?

> +
> +	return per_cpu(qcom_idle_ops, cpu)[index](cpu);
> +}
> +
> +const struct of_device_id qcom_idle_state_match[] __initconst = {

static?

> +	{ .compatible = "qcom,idle-state-stby", .data = qcom_cpu_standby },
> +	{ .compatible = "qcom,idle-state-spc", .data = qcom_cpu_spc },
> +	{ },
> +};
> +
> +static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
> +{
> +	const struct of_device_id *match_id;
> +	struct device_node *state_node;
> +	int i;
> +	int state_count = 0;
> +	idle_fn idle_fns[CPUIDLE_STATE_MAX];
> +	idle_fn *fns;
> +	cpumask_t mask;
> +	bool use_scm_power_down = false;
> +
> +	for (i = 0; ; i++) {
> +		state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
> +		if (!state_node)
> +			break;
> +
> +		if (!of_device_is_available(state_node))
> +			continue;
> +
> +		if (i == CPUIDLE_STATE_MAX) {
> +			pr_warn("%s: cpuidle states reached max possible\n",
> +					__func__);
> +			break;
> +		}
> +
> +		match_id = of_match_node(qcom_idle_state_match, state_node);
> +		if (!match_id)
> +			return -ENODEV;
> +
> +		idle_fns[state_count] = match_id->data;
> +
> +		/* Check if any of the states allow power down */
> +		if (match_id->data == qcom_cpu_spc)
> +			use_scm_power_down = true;
> +
> +		state_count++;
> +	}
> +
> +	if (!state_count) {
> +		pr_warn("No idle ops founds for cpu %d\n", cpu);

Maybe pr_debug? It's not the end of the world that we don't have cpuidle.

> +		return -ENODEV;
> +	}
> +
> +	fns = kcalloc(state_count, sizeof(*fns), GFP_KERNEL);
> +	if (!fns)
> +		return -ENOMEM;
> +
> +	for (i = 0; i < state_count; i++)
> +		fns[i] = idle_fns[i];
> +
> +	if (use_scm_power_down) {
> +		/* We have atlease one power down mode */

s/atlease/at least/

> +		cpumask_clear(&mask);
> +		cpumask_set_cpu(cpu, &mask);
> +		qcom_scm_set_warm_boot_addr(cpu_resume, &mask);
> +	}
> +
> +	per_cpu(qcom_idle_ops, cpu) = fns;
> +
> +	/*
> +	 * Condition: cpuidle_driver_register() needs to happen before
> +	 * cpuidle_register_device().
> +	 * Check if the SPM probe has happened -
> +	 * - If SPM probed successfully before arm_idle_init(), then defer
> +	 *   the registration of cpuidle_device back to arm_idle_init()
> +	 * - If the SPM probe happens in the future, then let the SPM probe
> +	 *   register the cpuidle device, return -ENOSYS.
> +	 */
> +	return per_cpu(cpu_spm_drv, cpu) ? 0 : -ENOSYS;
> +}
> +
> +struct cpuidle_ops qcom_kpss_v1_cpuidle_ops __initdata = {
> +	.name = "qcom,kpss-acc-v1",
> +	.suspend = qcom_idle_enter,
> +	.init = qcom_cpuidle_init,
> +};
> +
> +struct cpuidle_ops qcom_kpss_v2_cpuidle_ops __initdata = {
> +	.name = "qcom,kpss-acc-v2",
> +	.suspend = qcom_idle_enter,
> +	.init = qcom_cpuidle_init,
> +};
> +
>

This just looks weird because of the macro magic in Daniel's series. Any
reason we can't use the linker instead of doing preprocessor magic so
that it looks like these structures are actually used?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[RFC PATCH v15 02/11] ARM: qcom: Add Subsystem Power Manager (SPM) driver

[Stephen Boyd]

On 03/09/15 08:16, Lina Iyer wrote:
> +
> +static int qcom_idle_enter(int cpu, unsigned long index)
> +{
> +	if (!per_cpu(qcom_idle_ops, cpu)[index])
> +		return -EOPNOTSUPP;

Is this case still happening?

> +
> +	return per_cpu(qcom_idle_ops, cpu)[index](cpu);
> +}
> +
> +const struct of_device_id qcom_idle_state_match[] __initconst = {

static?

> +	{ .compatible = "qcom,idle-state-stby", .data = qcom_cpu_standby },
> +	{ .compatible = "qcom,idle-state-spc", .data = qcom_cpu_spc },
> +	{ },
> +};
> +
> +static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
> +{
> +	const struct of_device_id *match_id;
> +	struct device_node *state_node;
> +	int i;
> +	int state_count = 0;
> +	idle_fn idle_fns[CPUIDLE_STATE_MAX];
> +	idle_fn *fns;
> +	cpumask_t mask;
> +	bool use_scm_power_down = false;
> +
> +	for (i = 0; ; i++) {
> +		state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
> +		if (!state_node)
> +			break;
> +
> +		if (!of_device_is_available(state_node))
> +			continue;
> +
> +		if (i == CPUIDLE_STATE_MAX) {
> +			pr_warn("%s: cpuidle states reached max possible\n",
> +					__func__);
> +			break;
> +		}
> +
> +		match_id = of_match_node(qcom_idle_state_match, state_node);
> +		if (!match_id)
> +			return -ENODEV;
> +
> +		idle_fns[state_count] = match_id->data;
> +
> +		/* Check if any of the states allow power down */
> +		if (match_id->data == qcom_cpu_spc)
> +			use_scm_power_down = true;
> +
> +		state_count++;
> +	}
> +
> +	if (!state_count) {
> +		pr_warn("No idle ops founds for cpu %d\n", cpu);

Maybe pr_debug? It's not the end of the world that we don't have cpuidle.

> +		return -ENODEV;
> +	}
> +
> +	fns = kcalloc(state_count, sizeof(*fns), GFP_KERNEL);
> +	if (!fns)
> +		return -ENOMEM;
> +
> +	for (i = 0; i < state_count; i++)
> +		fns[i] = idle_fns[i];
> +
> +	if (use_scm_power_down) {
> +		/* We have atlease one power down mode */

s/atlease/at least/

> +		cpumask_clear(&mask);
> +		cpumask_set_cpu(cpu, &mask);
> +		qcom_scm_set_warm_boot_addr(cpu_resume, &mask);
> +	}
> +
> +	per_cpu(qcom_idle_ops, cpu) = fns;
> +
> +	/*
> +	 * Condition: cpuidle_driver_register() needs to happen before
> +	 * cpuidle_register_device().
> +	 * Check if the SPM probe has happened -
> +	 * - If SPM probed successfully before arm_idle_init(), then defer
> +	 *   the registration of cpuidle_device back to arm_idle_init()
> +	 * - If the SPM probe happens in the future, then let the SPM probe
> +	 *   register the cpuidle device, return -ENOSYS.
> +	 */
> +	return per_cpu(cpu_spm_drv, cpu) ? 0 : -ENOSYS;
> +}
> +
> +struct cpuidle_ops qcom_kpss_v1_cpuidle_ops __initdata = {
> +	.name = "qcom,kpss-acc-v1",
> +	.suspend = qcom_idle_enter,
> +	.init = qcom_cpuidle_init,
> +};
> +
> +struct cpuidle_ops qcom_kpss_v2_cpuidle_ops __initdata = {
> +	.name = "qcom,kpss-acc-v2",
> +	.suspend = qcom_idle_enter,
> +	.init = qcom_cpuidle_init,
> +};
> +
>

This just looks weird because of the macro magic in Daniel's series. Any
reason we can't use the linker instead of doing preprocessor magic so
that it looks like these structures are actually used?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [RFC PATCH v15 02/11] ARM: qcom: Add Subsystem Power Manager (SPM) driver

[Lina Iyer]

On Mon, Mar 16 2015 at 15:51 -0600, Stephen Boyd wrote:
>On 03/09/15 08:16, Lina Iyer wrote:
>> +
>> +static int qcom_idle_enter(int cpu, unsigned long index)
>> +{
>> +	if (!per_cpu(qcom_idle_ops, cpu)[index])
>> +		return -EOPNOTSUPP;
>
>Is this case still happening?
>
I think, I can remove it safely now.
>> +
>> +	return per_cpu(qcom_idle_ops, cpu)[index](cpu);
>> +}
>> +
>> +const struct of_device_id qcom_idle_state_match[] __initconst = {
>
>static?
>
Ok

>> +	{ .compatible = "qcom,idle-state-stby", .data = qcom_cpu_standby },
>> +	{ .compatible = "qcom,idle-state-spc", .data = qcom_cpu_spc },
>> +	{ },
>> +};
>> +
>> +static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
>> +{
>> +	const struct of_device_id *match_id;
>> +	struct device_node *state_node;
>> +	int i;
>> +	int state_count = 0;
>> +	idle_fn idle_fns[CPUIDLE_STATE_MAX];
>> +	idle_fn *fns;
>> +	cpumask_t mask;
>> +	bool use_scm_power_down = false;
>> +
>> +	for (i = 0; ; i++) {
>> +		state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
>> +		if (!state_node)
>> +			break;
>> +
>> +		if (!of_device_is_available(state_node))
>> +			continue;
>> +
>> +		if (i == CPUIDLE_STATE_MAX) {
>> +			pr_warn("%s: cpuidle states reached max possible\n",
>> +					__func__);
>> +			break;
>> +		}
>> +
>> +		match_id = of_match_node(qcom_idle_state_match, state_node);
>> +		if (!match_id)
>> +			return -ENODEV;
>> +
>> +		idle_fns[state_count] = match_id->data;
>> +
>> +		/* Check if any of the states allow power down */
>> +		if (match_id->data == qcom_cpu_spc)
>> +			use_scm_power_down = true;
>> +
>> +		state_count++;
>> +	}
>> +
>> +	if (!state_count) {
>> +		pr_warn("No idle ops founds for cpu %d\n", cpu);
>
>Maybe pr_debug? It's not the end of the world that we don't have cpuidle.
>
Sure.

>> +		return -ENODEV;
>> +	}
>> +
>> +	fns = kcalloc(state_count, sizeof(*fns), GFP_KERNEL);
>> +	if (!fns)
>> +		return -ENOMEM;
>> +
>> +	for (i = 0; i < state_count; i++)
>> +		fns[i] = idle_fns[i];
>> +
>> +	if (use_scm_power_down) {
>> +		/* We have atlease one power down mode */
>
>s/atlease/at least/
>
Thanks!

>> +		cpumask_clear(&mask);
>> +		cpumask_set_cpu(cpu, &mask);
>> +		qcom_scm_set_warm_boot_addr(cpu_resume, &mask);
>> +	}
>> +
>> +	per_cpu(qcom_idle_ops, cpu) = fns;
>> +
>> +	/*
>> +	 * Condition: cpuidle_driver_register() needs to happen before
>> +	 * cpuidle_register_device().
>> +	 * Check if the SPM probe has happened -
>> +	 * - If SPM probed successfully before arm_idle_init(), then defer
>> +	 *   the registration of cpuidle_device back to arm_idle_init()
>> +	 * - If the SPM probe happens in the future, then let the SPM probe
>> +	 *   register the cpuidle device, return -ENOSYS.
>> +	 */
>> +	return per_cpu(cpu_spm_drv, cpu) ? 0 : -ENOSYS;
>> +}
>> +
>> +struct cpuidle_ops qcom_kpss_v1_cpuidle_ops __initdata = {
>> +	.name = "qcom,kpss-acc-v1",
>> +	.suspend = qcom_idle_enter,
>> +	.init = qcom_cpuidle_init,
>> +};
>> +
>> +struct cpuidle_ops qcom_kpss_v2_cpuidle_ops __initdata = {
>> +	.name = "qcom,kpss-acc-v2",
>> +	.suspend = qcom_idle_enter,
>> +	.init = qcom_cpuidle_init,
>> +};
>> +
>>
>
>This just looks weird because of the macro magic in Daniel's series. Any
>reason we can't use the linker instead of doing preprocessor magic so
>that it looks like these structures are actually used?
>
Hmm.. Will wait on Daniel's response to your other mail.

>-- 
>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
>a Linux Foundation Collaborative Project
>

[RFC PATCH v15 02/11] ARM: qcom: Add Subsystem Power Manager (SPM) driver

[Lina Iyer]

On Mon, Mar 16 2015 at 15:51 -0600, Stephen Boyd wrote:
>On 03/09/15 08:16, Lina Iyer wrote:
>> +
>> +static int qcom_idle_enter(int cpu, unsigned long index)
>> +{
>> +	if (!per_cpu(qcom_idle_ops, cpu)[index])
>> +		return -EOPNOTSUPP;
>
>Is this case still happening?
>
I think, I can remove it safely now.
>> +
>> +	return per_cpu(qcom_idle_ops, cpu)[index](cpu);
>> +}
>> +
>> +const struct of_device_id qcom_idle_state_match[] __initconst = {
>
>static?
>
Ok

>> +	{ .compatible = "qcom,idle-state-stby", .data = qcom_cpu_standby },
>> +	{ .compatible = "qcom,idle-state-spc", .data = qcom_cpu_spc },
>> +	{ },
>> +};
>> +
>> +static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
>> +{
>> +	const struct of_device_id *match_id;
>> +	struct device_node *state_node;
>> +	int i;
>> +	int state_count = 0;
>> +	idle_fn idle_fns[CPUIDLE_STATE_MAX];
>> +	idle_fn *fns;
>> +	cpumask_t mask;
>> +	bool use_scm_power_down = false;
>> +
>> +	for (i = 0; ; i++) {
>> +		state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
>> +		if (!state_node)
>> +			break;
>> +
>> +		if (!of_device_is_available(state_node))
>> +			continue;
>> +
>> +		if (i == CPUIDLE_STATE_MAX) {
>> +			pr_warn("%s: cpuidle states reached max possible\n",
>> +					__func__);
>> +			break;
>> +		}
>> +
>> +		match_id = of_match_node(qcom_idle_state_match, state_node);
>> +		if (!match_id)
>> +			return -ENODEV;
>> +
>> +		idle_fns[state_count] = match_id->data;
>> +
>> +		/* Check if any of the states allow power down */
>> +		if (match_id->data == qcom_cpu_spc)
>> +			use_scm_power_down = true;
>> +
>> +		state_count++;
>> +	}
>> +
>> +	if (!state_count) {
>> +		pr_warn("No idle ops founds for cpu %d\n", cpu);
>
>Maybe pr_debug? It's not the end of the world that we don't have cpuidle.
>
Sure.

>> +		return -ENODEV;
>> +	}
>> +
>> +	fns = kcalloc(state_count, sizeof(*fns), GFP_KERNEL);
>> +	if (!fns)
>> +		return -ENOMEM;
>> +
>> +	for (i = 0; i < state_count; i++)
>> +		fns[i] = idle_fns[i];
>> +
>> +	if (use_scm_power_down) {
>> +		/* We have atlease one power down mode */
>
>s/atlease/at least/
>
Thanks!

>> +		cpumask_clear(&mask);
>> +		cpumask_set_cpu(cpu, &mask);
>> +		qcom_scm_set_warm_boot_addr(cpu_resume, &mask);
>> +	}
>> +
>> +	per_cpu(qcom_idle_ops, cpu) = fns;
>> +
>> +	/*
>> +	 * Condition: cpuidle_driver_register() needs to happen before
>> +	 * cpuidle_register_device().
>> +	 * Check if the SPM probe has happened -
>> +	 * - If SPM probed successfully before arm_idle_init(), then defer
>> +	 *   the registration of cpuidle_device back to arm_idle_init()
>> +	 * - If the SPM probe happens in the future, then let the SPM probe
>> +	 *   register the cpuidle device, return -ENOSYS.
>> +	 */
>> +	return per_cpu(cpu_spm_drv, cpu) ? 0 : -ENOSYS;
>> +}
>> +
>> +struct cpuidle_ops qcom_kpss_v1_cpuidle_ops __initdata = {
>> +	.name = "qcom,kpss-acc-v1",
>> +	.suspend = qcom_idle_enter,
>> +	.init = qcom_cpuidle_init,
>> +};
>> +
>> +struct cpuidle_ops qcom_kpss_v2_cpuidle_ops __initdata = {
>> +	.name = "qcom,kpss-acc-v2",
>> +	.suspend = qcom_idle_enter,
>> +	.init = qcom_cpuidle_init,
>> +};
>> +
>>
>
>This just looks weird because of the macro magic in Daniel's series. Any
>reason we can't use the linker instead of doing preprocessor magic so
>that it looks like these structures are actually used?
>
Hmm.. Will wait on Daniel's response to your other mail.

>-- 
>Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
>a Linux Foundation Collaborative Project
>

[RFC PATCH v15 04/11] ARM: cpuidle: Register cpuidle_ops for QCOM cpus

[Lina Iyer]

Register cpuidle ops for Krait Processor Sub-System.
Supports v1 and v2 versions of KPSS.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 arch/arm/include/asm/cpuidle_ops.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/include/asm/cpuidle_ops.h b/arch/arm/include/asm/cpuidle_ops.h
index be0a612..40cb262 100644
--- a/arch/arm/include/asm/cpuidle_ops.h
+++ b/arch/arm/include/asm/cpuidle_ops.h
@@ -1,3 +1,8 @@
 /*
  * List of cpuidle operations
  */
+
+#if IS_ENABLED(CONFIG_QCOM_PM)
+CPUIDLE_OPS(qcom_kpss_v1)
+CPUIDLE_OPS(qcom_kpss_v2)
+#endif
-- 
2.1.0

[RFC PATCH v15 04/11] ARM: cpuidle: Register cpuidle_ops for QCOM cpus

[Lina Iyer]

Register cpuidle ops for Krait Processor Sub-System.
Supports v1 and v2 versions of KPSS.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 arch/arm/include/asm/cpuidle_ops.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/include/asm/cpuidle_ops.h b/arch/arm/include/asm/cpuidle_ops.h
index be0a612..40cb262 100644
--- a/arch/arm/include/asm/cpuidle_ops.h
+++ b/arch/arm/include/asm/cpuidle_ops.h
@@ -1,3 +1,8 @@
 /*
  * List of cpuidle operations
  */
+
+#if IS_ENABLED(CONFIG_QCOM_PM)
+CPUIDLE_OPS(qcom_kpss_v1)
+CPUIDLE_OPS(qcom_kpss_v2)
+#endif
-- 
2.1.0

Re: [RFC PATCH v15 04/11] ARM: cpuidle: Register cpuidle_ops for QCOM cpus

[Stephen Boyd]

On 03/09/15 08:16, Lina Iyer wrote:
> Register cpuidle ops for Krait Processor Sub-System.
> Supports v1 and v2 versions of KPSS.
>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Kevin Hilman <khilman@linaro.org>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
> ---
>  arch/arm/include/asm/cpuidle_ops.h | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/include/asm/cpuidle_ops.h b/arch/arm/include/asm/cpuidle_ops.h
> index be0a612..40cb262 100644
> --- a/arch/arm/include/asm/cpuidle_ops.h
> +++ b/arch/arm/include/asm/cpuidle_ops.h
> @@ -1,3 +1,8 @@
>  /*
>   * List of cpuidle operations
>   */
> +
> +#if IS_ENABLED(CONFIG_QCOM_PM)

Why not #ifdef CONFIG_QCOM_PM? I thought IS_ENABLED was for C code where
you want to put it in an if () statement.

> +CPUIDLE_OPS(qcom_kpss_v1)
> +CPUIDLE_OPS(qcom_kpss_v2)
> +#endif


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[RFC PATCH v15 04/11] ARM: cpuidle: Register cpuidle_ops for QCOM cpus

[Stephen Boyd]

On 03/09/15 08:16, Lina Iyer wrote:
> Register cpuidle ops for Krait Processor Sub-System.
> Supports v1 and v2 versions of KPSS.
>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Kevin Hilman <khilman@linaro.org>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
> ---
>  arch/arm/include/asm/cpuidle_ops.h | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/include/asm/cpuidle_ops.h b/arch/arm/include/asm/cpuidle_ops.h
> index be0a612..40cb262 100644
> --- a/arch/arm/include/asm/cpuidle_ops.h
> +++ b/arch/arm/include/asm/cpuidle_ops.h
> @@ -1,3 +1,8 @@
>  /*
>   * List of cpuidle operations
>   */
> +
> +#if IS_ENABLED(CONFIG_QCOM_PM)

Why not #ifdef CONFIG_QCOM_PM? I thought IS_ENABLED was for C code where
you want to put it in an if () statement.

> +CPUIDLE_OPS(qcom_kpss_v1)
> +CPUIDLE_OPS(qcom_kpss_v2)
> +#endif


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [RFC PATCH v15 04/11] ARM: cpuidle: Register cpuidle_ops for QCOM cpus

[Daniel Lezcano]

On 03/11/2015 07:16 PM, Stephen Boyd wrote:
> On 03/09/15 08:16, Lina Iyer wrote:
>> Register cpuidle ops for Krait Processor Sub-System.
>> Supports v1 and v2 versions of KPSS.
>>
>> Cc: Stephen Boyd <sboyd@codeaurora.org>
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Cc: Kevin Hilman <khilman@linaro.org>
>> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
>> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
>> ---
>>   arch/arm/include/asm/cpuidle_ops.h | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/cpuidle_ops.h b/arch/arm/include/asm/cpuidle_ops.h
>> index be0a612..40cb262 100644
>> --- a/arch/arm/include/asm/cpuidle_ops.h
>> +++ b/arch/arm/include/asm/cpuidle_ops.h
>> @@ -1,3 +1,8 @@
>>   /*
>>    * List of cpuidle operations
>>    */
>> +
>> +#if IS_ENABLED(CONFIG_QCOM_PM)
>
> Why not #ifdef CONFIG_QCOM_PM? I thought IS_ENABLED was for C code where
> you want to put it in an if () statement.

This is right. But the IS_ENABLED is also valid.

It seems the current trend is to replace #ifdef with #if IS_ENABLED. It 
is supposed to prevent to create or'ed conditional with the module support.

eg:

#if defined(CONFIG_FOO) || defined(CONFIG_FOO_MODULE)

is replaced by:

#if IS_ENABLED(CONFIG_FOO)

Lina: By the way, it would be preferable to use the 
CONFIG_ARM_QCOM_CPUIDLE where IS_ENABLED makes more sense even the 
drivers are not modules (who knows if they are converted as module again 
hence #ifdef will be invalid).



>> +CPUIDLE_OPS(qcom_kpss_v1)
>> +CPUIDLE_OPS(qcom_kpss_v2)
>> +#endif
>
>


-- 
  <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

[RFC PATCH v15 04/11] ARM: cpuidle: Register cpuidle_ops for QCOM cpus

[Daniel Lezcano]

On 03/11/2015 07:16 PM, Stephen Boyd wrote:
> On 03/09/15 08:16, Lina Iyer wrote:
>> Register cpuidle ops for Krait Processor Sub-System.
>> Supports v1 and v2 versions of KPSS.
>>
>> Cc: Stephen Boyd <sboyd@codeaurora.org>
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Cc: Kevin Hilman <khilman@linaro.org>
>> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
>> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
>> ---
>>   arch/arm/include/asm/cpuidle_ops.h | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/cpuidle_ops.h b/arch/arm/include/asm/cpuidle_ops.h
>> index be0a612..40cb262 100644
>> --- a/arch/arm/include/asm/cpuidle_ops.h
>> +++ b/arch/arm/include/asm/cpuidle_ops.h
>> @@ -1,3 +1,8 @@
>>   /*
>>    * List of cpuidle operations
>>    */
>> +
>> +#if IS_ENABLED(CONFIG_QCOM_PM)
>
> Why not #ifdef CONFIG_QCOM_PM? I thought IS_ENABLED was for C code where
> you want to put it in an if () statement.

This is right. But the IS_ENABLED is also valid.

It seems the current trend is to replace #ifdef with #if IS_ENABLED. It 
is supposed to prevent to create or'ed conditional with the module support.

eg:

#if defined(CONFIG_FOO) || defined(CONFIG_FOO_MODULE)

is replaced by:

#if IS_ENABLED(CONFIG_FOO)

Lina: By the way, it would be preferable to use the 
CONFIG_ARM_QCOM_CPUIDLE where IS_ENABLED makes more sense even the 
drivers are not modules (who knows if they are converted as module again 
hence #ifdef will be invalid).



>> +CPUIDLE_OPS(qcom_kpss_v1)
>> +CPUIDLE_OPS(qcom_kpss_v2)
>> +#endif
>
>


-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

Re: [RFC PATCH v15 04/11] ARM: cpuidle: Register cpuidle_ops for QCOM cpus

[Lina Iyer]

On Thu, Mar 12 2015 at 06:34 -0600, Daniel Lezcano wrote:
>On 03/11/2015 07:16 PM, Stephen Boyd wrote:
>>On 03/09/15 08:16, Lina Iyer wrote:

[...]

>>>+#if IS_ENABLED(CONFIG_QCOM_PM)
>>
>>Why not #ifdef CONFIG_QCOM_PM? I thought IS_ENABLED was for C code where
>>you want to put it in an if () statement.
>
>This is right. But the IS_ENABLED is also valid.
>
>It seems the current trend is to replace #ifdef with #if IS_ENABLED. 
>It is supposed to prevent to create or'ed conditional with the module 
>support.
>
>eg:
>
>#if defined(CONFIG_FOO) || defined(CONFIG_FOO_MODULE)
>
>is replaced by:
>
>#if IS_ENABLED(CONFIG_FOO)
>
>Lina: By the way, it would be preferable to use the 
>CONFIG_ARM_QCOM_CPUIDLE where IS_ENABLED makes more sense even the 

Daniel: I dont have CONFIG_ARM_QCOM_CPUIDLE defined anymore. By moving
to generic ARM cpuidle, i removed all changes to drivers/cpuidle/. So I
used the config item that defineds these items.

Also, having two indpendent CONFIG_ items provides a chance that the
declaration is not matched with the definition or vice versa.

>drivers are not modules (who knows if they are converted as module 
>again hence #ifdef will be invalid).
>
>
>
>>>+CPUIDLE_OPS(qcom_kpss_v1)
>>>+CPUIDLE_OPS(qcom_kpss_v2)
>>>+#endif

[RFC PATCH v15 04/11] ARM: cpuidle: Register cpuidle_ops for QCOM cpus

[Lina Iyer]

On Thu, Mar 12 2015 at 06:34 -0600, Daniel Lezcano wrote:
>On 03/11/2015 07:16 PM, Stephen Boyd wrote:
>>On 03/09/15 08:16, Lina Iyer wrote:

[...]

>>>+#if IS_ENABLED(CONFIG_QCOM_PM)
>>
>>Why not #ifdef CONFIG_QCOM_PM? I thought IS_ENABLED was for C code where
>>you want to put it in an if () statement.
>
>This is right. But the IS_ENABLED is also valid.
>
>It seems the current trend is to replace #ifdef with #if IS_ENABLED. 
>It is supposed to prevent to create or'ed conditional with the module 
>support.
>
>eg:
>
>#if defined(CONFIG_FOO) || defined(CONFIG_FOO_MODULE)
>
>is replaced by:
>
>#if IS_ENABLED(CONFIG_FOO)
>
>Lina: By the way, it would be preferable to use the 
>CONFIG_ARM_QCOM_CPUIDLE where IS_ENABLED makes more sense even the 

Daniel: I dont have CONFIG_ARM_QCOM_CPUIDLE defined anymore. By moving
to generic ARM cpuidle, i removed all changes to drivers/cpuidle/. So I
used the config item that defineds these items.

Also, having two indpendent CONFIG_ items provides a chance that the
declaration is not matched with the definition or vice versa.

>drivers are not modules (who knows if they are converted as module 
>again hence #ifdef will be invalid).
>
>
>
>>>+CPUIDLE_OPS(qcom_kpss_v1)
>>>+CPUIDLE_OPS(qcom_kpss_v2)
>>>+#endif

Re: [RFC PATCH v15 04/11] ARM: cpuidle: Register cpuidle_ops for QCOM cpus

[Daniel Lezcano]

On 03/12/2015 04:06 PM, Lina Iyer wrote:
> On Thu, Mar 12 2015 at 06:34 -0600, Daniel Lezcano wrote:
>> On 03/11/2015 07:16 PM, Stephen Boyd wrote:
>>> On 03/09/15 08:16, Lina Iyer wrote:
>
> [...]
>
>>>> +#if IS_ENABLED(CONFIG_QCOM_PM)
>>>
>>> Why not #ifdef CONFIG_QCOM_PM? I thought IS_ENABLED was for C code where
>>> you want to put it in an if () statement.
>>
>> This is right. But the IS_ENABLED is also valid.
>>
>> It seems the current trend is to replace #ifdef with #if IS_ENABLED.
>> It is supposed to prevent to create or'ed conditional with the module
>> support.
>>
>> eg:
>>
>> #if defined(CONFIG_FOO) || defined(CONFIG_FOO_MODULE)
>>
>> is replaced by:
>>
>> #if IS_ENABLED(CONFIG_FOO)
>>
>> Lina: By the way, it would be preferable to use the
>> CONFIG_ARM_QCOM_CPUIDLE where IS_ENABLED makes more sense even the
>
> Daniel: I dont have CONFIG_ARM_QCOM_CPUIDLE defined anymore. By moving
> to generic ARM cpuidle, i removed all changes to drivers/cpuidle/. So I
> used the config item that defineds these items.
>
> Also, having two indpendent CONFIG_ items provides a chance that the
> declaration is not matched with the definition or vice versa.

I think CONFIG_ARM_QCOM_CPUIDLE should be defined as a bool in the 
Kconfig.arm in drivers/cpuidle.

We may want to disable the different cpuidle drivers even if they rely 
on the generic cpuidle driver.

>> drivers are not modules (who knows if they are converted as module
>> again hence #ifdef will be invalid).
>>
>>
>>
>>>> +CPUIDLE_OPS(qcom_kpss_v1)
>>>> +CPUIDLE_OPS(qcom_kpss_v2)
>>>> +#endif
>


-- 
  <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

[RFC PATCH v15 04/11] ARM: cpuidle: Register cpuidle_ops for QCOM cpus

[Daniel Lezcano]

On 03/12/2015 04:06 PM, Lina Iyer wrote:
> On Thu, Mar 12 2015 at 06:34 -0600, Daniel Lezcano wrote:
>> On 03/11/2015 07:16 PM, Stephen Boyd wrote:
>>> On 03/09/15 08:16, Lina Iyer wrote:
>
> [...]
>
>>>> +#if IS_ENABLED(CONFIG_QCOM_PM)
>>>
>>> Why not #ifdef CONFIG_QCOM_PM? I thought IS_ENABLED was for C code where
>>> you want to put it in an if () statement.
>>
>> This is right. But the IS_ENABLED is also valid.
>>
>> It seems the current trend is to replace #ifdef with #if IS_ENABLED.
>> It is supposed to prevent to create or'ed conditional with the module
>> support.
>>
>> eg:
>>
>> #if defined(CONFIG_FOO) || defined(CONFIG_FOO_MODULE)
>>
>> is replaced by:
>>
>> #if IS_ENABLED(CONFIG_FOO)
>>
>> Lina: By the way, it would be preferable to use the
>> CONFIG_ARM_QCOM_CPUIDLE where IS_ENABLED makes more sense even the
>
> Daniel: I dont have CONFIG_ARM_QCOM_CPUIDLE defined anymore. By moving
> to generic ARM cpuidle, i removed all changes to drivers/cpuidle/. So I
> used the config item that defineds these items.
>
> Also, having two indpendent CONFIG_ items provides a chance that the
> declaration is not matched with the definition or vice versa.

I think CONFIG_ARM_QCOM_CPUIDLE should be defined as a bool in the 
Kconfig.arm in drivers/cpuidle.

We may want to disable the different cpuidle drivers even if they rely 
on the generic cpuidle driver.

>> drivers are not modules (who knows if they are converted as module
>> again hence #ifdef will be invalid).
>>
>>
>>
>>>> +CPUIDLE_OPS(qcom_kpss_v1)
>>>> +CPUIDLE_OPS(qcom_kpss_v2)
>>>> +#endif
>


-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

[PATCH v15 05/11] ARM: dts: qcom: Add power-controller device node for 8074 Krait CPUs

[Lina Iyer]

Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.

Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/boot/dts/qcom-msm8974.dtsi | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index e265ec1..5a41f44 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -21,6 +21,7 @@
 			reg = <0>;
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc0>;
+			qcom,saw = <&saw0>;
 		};
 
 		cpu@1 {
@@ -30,6 +31,7 @@
 			reg = <1>;
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc1>;
+			qcom,saw = <&saw1>;
 		};
 
 		cpu@2 {
@@ -39,6 +41,7 @@
 			reg = <2>;
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc2>;
+			qcom,saw = <&saw2>;
 		};
 
 		cpu@3 {
@@ -48,6 +51,7 @@
 			reg = <3>;
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc3>;
+			qcom,saw = <&saw3>;
 		};
 
 		L2: l2-cache {
@@ -144,7 +148,27 @@
 			};
 		};
 
-		saw_l2: regulator@f9012000 {
+		saw0: power-controller@f9089000 {
+			compatible = "qcom,msm8974-saw2-v2.1-cpu";
+			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw1: power-controller@f9099000 {
+			compatible = "qcom,msm8974-saw2-v2.1-cpu";
+			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw2: power-controller@f90a9000 {
+			compatible = "qcom,msm8974-saw2-v2.1-cpu";
+			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw3: power-controller@f90b9000 {
+			compatible = "qcom,msm8974-saw2-v2.1-cpu";
+			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw_l2: power-controller@f9012000 {
 			compatible = "qcom,saw2";
 			reg = <0xf9012000 0x1000>;
 			regulator;
-- 
2.1.0

[PATCH v15 05/11] ARM: dts: qcom: Add power-controller device node for 8074 Krait CPUs

[Lina Iyer]

Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.

Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/boot/dts/qcom-msm8974.dtsi | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index e265ec1..5a41f44 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -21,6 +21,7 @@
 			reg = <0>;
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc0>;
+			qcom,saw = <&saw0>;
 		};
 
 		cpu at 1 {
@@ -30,6 +31,7 @@
 			reg = <1>;
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc1>;
+			qcom,saw = <&saw1>;
 		};
 
 		cpu at 2 {
@@ -39,6 +41,7 @@
 			reg = <2>;
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc2>;
+			qcom,saw = <&saw2>;
 		};
 
 		cpu at 3 {
@@ -48,6 +51,7 @@
 			reg = <3>;
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc3>;
+			qcom,saw = <&saw3>;
 		};
 
 		L2: l2-cache {
@@ -144,7 +148,27 @@
 			};
 		};
 
-		saw_l2: regulator at f9012000 {
+		saw0: power-controller at f9089000 {
+			compatible = "qcom,msm8974-saw2-v2.1-cpu";
+			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw1: power-controller at f9099000 {
+			compatible = "qcom,msm8974-saw2-v2.1-cpu";
+			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw2: power-controller at f90a9000 {
+			compatible = "qcom,msm8974-saw2-v2.1-cpu";
+			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw3: power-controller at f90b9000 {
+			compatible = "qcom,msm8974-saw2-v2.1-cpu";
+			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw_l2: power-controller at f9012000 {
 			compatible = "qcom,saw2";
 			reg = <0xf9012000 0x1000>;
 			regulator;
-- 
2.1.0

[PATCH v15 03/11] ARM: cpuidle: qcom: Add documentation for qcom cpuidle states.

[Lina Iyer]

Add documentation for cpuidle states of QCOM cpus. In addition to
arm-idle-state compatible string, the ARM idle state definition must
define one of the following compatible strings -
	"qcom,idle-state-stby",
	"qcom,idle-state-ret",
	"qcom,idle-state-spc",
	"qcom,idle-state-pc",

The compatibles helps the SPM platform driver to use the correct idle
function when the index to the idle state is passed to the platform
driver.

Signed-off-by: Lina Iyer <lina.iyer-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 .../bindings/arm/msm/qcom,idle-state.txt           | 81 ++++++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
new file mode 100644
index 0000000..ae1b07f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
@@ -0,0 +1,81 @@
+QCOM Idle States for cpuidle driver
+
+ARM provides idle-state node to define the cpuidle states, as defined in [1].
+cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
+states. Idle states have different enter/exit latency and residency values.
+The idle states supported by the QCOM SoC are defined as -
+
+    * Standby
+    * Retention
+    * Standalone Power Collapse (Standalone PC or SPC)
+    * Power Collapse (PC)
+
+Standby: Standby does a little more in addition to architectural clock gating.
+When the WFI instruction is executed the ARM core would gate its internal
+clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
+trigger to execute the SPM state machine. The SPM state machine waits for the
+interrupt to trigger the core back in to active. This triggers the cache
+hierarchy to enter standby states, when all cpus are idle. An interrupt brings
+the SPM state machine out of its wait, the next step is to ensure that the
+cache hierarchy is also out of standby, and then the cpu is allowed to resume
+execution.
+
+Retention: Retention is a low power state where the core is clock gated and
+the memory and the registers associated with the core are retained. The
+voltage may be reduced to the minimum value needed to keep the processor
+registers active. The SPM should be configured to execute the retention
+sequence and would wait for interrupt, before restoring the cpu to execution
+state. Retention may have a slightly higher latency than Standby.
+
+Standalone PC: A cpu can power down and warmboot if there is a sufficient time
+between the time it enters idle and the next known wake up. SPC mode is used
+to indicate a core entering a power down state without consulting any other
+cpu or the system resources. This helps save power only on that core.  The SPM
+sequence for this idle state is programmed to power down the supply to the
+core, wait for the interrupt, restore power to the core, and ensure the
+system state including cache hierarchy is ready before allowing core to
+resume. Applying power and resetting the core causes the core to warmboot
+back into Elevation Level (EL) which trampolines the control back to the
+kernel. Entering a power down state for the cpu, needs to be done by trapping
+into a EL. Failing to do so, would result in a crash enforced by the warm boot
+code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
+be flushed in s/w, before powering down the core.
+
+Power Collapse: This state is similar to the SPC mode, but distinguishes
+itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
+modes. In a hierarchical power domain SoC, this means L2 and other caches can
+be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
+voltages reduced, provided all cpus enter this state.  Since the span of low
+power modes possible at this state is vast, the exit latency and the residency
+of this low power mode would be considered high even though at a cpu level,
+this essentially is cpu power down. The SPM in this state also may handshake
+with the Resource power manager processor in the SoC to indicate a complete
+application processor subsystem shut down.
+
+The idle-state for QCOM SoCs are distinguished by the compatible property of
+the idle-states device node.
+The devicetree representation of the idle state should be -
+
+Required properties:
+
+- compatible: Must be one of -
+			"qcom,idle-state-stby",
+			"qcom,idle-state-ret",
+			"qcom,idle-state-spc",
+			"qcom,idle-state-pc",
+		and "arm,idle-state".
+
+Other required and optional properties are specified in [1].
+
+Example:
+
+	idle-states {
+		CPU_SPC: spc {
+			compatible = "qcom,idle-state-spc", "arm,idle-state";
+			entry-latency-us = <150>;
+			exit-latency-us = <200>;
+			min-residency-us = <2000>;
+		};
+	};
+
+[1]. Documentation/devicetree/bindings/arm/idle-states.txt
-- 
2.1.0

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v15 03/11] ARM: cpuidle: qcom: Add documentation for qcom cpuidle states.

[Lina Iyer]

Add documentation for cpuidle states of QCOM cpus. In addition to
arm-idle-state compatible string, the ARM idle state definition must
define one of the following compatible strings -
	"qcom,idle-state-stby",
	"qcom,idle-state-ret",
	"qcom,idle-state-spc",
	"qcom,idle-state-pc",

The compatibles helps the SPM platform driver to use the correct idle
function when the index to the idle state is passed to the platform
driver.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 .../bindings/arm/msm/qcom,idle-state.txt           | 81 ++++++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
new file mode 100644
index 0000000..ae1b07f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
@@ -0,0 +1,81 @@
+QCOM Idle States for cpuidle driver
+
+ARM provides idle-state node to define the cpuidle states, as defined in [1].
+cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
+states. Idle states have different enter/exit latency and residency values.
+The idle states supported by the QCOM SoC are defined as -
+
+    * Standby
+    * Retention
+    * Standalone Power Collapse (Standalone PC or SPC)
+    * Power Collapse (PC)
+
+Standby: Standby does a little more in addition to architectural clock gating.
+When the WFI instruction is executed the ARM core would gate its internal
+clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
+trigger to execute the SPM state machine. The SPM state machine waits for the
+interrupt to trigger the core back in to active. This triggers the cache
+hierarchy to enter standby states, when all cpus are idle. An interrupt brings
+the SPM state machine out of its wait, the next step is to ensure that the
+cache hierarchy is also out of standby, and then the cpu is allowed to resume
+execution.
+
+Retention: Retention is a low power state where the core is clock gated and
+the memory and the registers associated with the core are retained. The
+voltage may be reduced to the minimum value needed to keep the processor
+registers active. The SPM should be configured to execute the retention
+sequence and would wait for interrupt, before restoring the cpu to execution
+state. Retention may have a slightly higher latency than Standby.
+
+Standalone PC: A cpu can power down and warmboot if there is a sufficient time
+between the time it enters idle and the next known wake up. SPC mode is used
+to indicate a core entering a power down state without consulting any other
+cpu or the system resources. This helps save power only on that core.  The SPM
+sequence for this idle state is programmed to power down the supply to the
+core, wait for the interrupt, restore power to the core, and ensure the
+system state including cache hierarchy is ready before allowing core to
+resume. Applying power and resetting the core causes the core to warmboot
+back into Elevation Level (EL) which trampolines the control back to the
+kernel. Entering a power down state for the cpu, needs to be done by trapping
+into a EL. Failing to do so, would result in a crash enforced by the warm boot
+code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
+be flushed in s/w, before powering down the core.
+
+Power Collapse: This state is similar to the SPC mode, but distinguishes
+itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
+modes. In a hierarchical power domain SoC, this means L2 and other caches can
+be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
+voltages reduced, provided all cpus enter this state.  Since the span of low
+power modes possible at this state is vast, the exit latency and the residency
+of this low power mode would be considered high even though at a cpu level,
+this essentially is cpu power down. The SPM in this state also may handshake
+with the Resource power manager processor in the SoC to indicate a complete
+application processor subsystem shut down.
+
+The idle-state for QCOM SoCs are distinguished by the compatible property of
+the idle-states device node.
+The devicetree representation of the idle state should be -
+
+Required properties:
+
+- compatible: Must be one of -
+			"qcom,idle-state-stby",
+			"qcom,idle-state-ret",
+			"qcom,idle-state-spc",
+			"qcom,idle-state-pc",
+		and "arm,idle-state".
+
+Other required and optional properties are specified in [1].
+
+Example:
+
+	idle-states {
+		CPU_SPC: spc {
+			compatible = "qcom,idle-state-spc", "arm,idle-state";
+			entry-latency-us = <150>;
+			exit-latency-us = <200>;
+			min-residency-us = <2000>;
+		};
+	};
+
+[1]. Documentation/devicetree/bindings/arm/idle-states.txt
-- 
2.1.0

[PATCH v15 06/11] ARM: dts: qcom: Add power-controller device node for 8084 Krait CPUs

[Lina Iyer]

Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.

Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Signed-off-by: Lina Iyer <lina.iyer-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Reviewed-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 arch/arm/boot/dts/qcom-apq8084.dtsi | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 1f130bc..71182bf 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -21,6 +21,7 @@
 			enable-method = "qcom,kpss-acc-v2";
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc0>;
+			qcom,saw = <&saw0>;
 		};
 
 		cpu@1 {
@@ -30,6 +31,7 @@
 			enable-method = "qcom,kpss-acc-v2";
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc1>;
+			qcom,saw = <&saw1>;
 		};
 
 		cpu@2 {
@@ -39,6 +41,7 @@
 			enable-method = "qcom,kpss-acc-v2";
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc2>;
+			qcom,saw = <&saw2>;
 		};
 
 		cpu@3 {
@@ -48,6 +51,7 @@
 			enable-method = "qcom,kpss-acc-v2";
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc3>;
+			qcom,saw = <&saw3>;
 		};
 
 		L2: l2-cache {
@@ -144,7 +148,27 @@
 			};
 		};
 
-		saw_l2: regulator@f9012000 {
+		saw0: power-controller@f9089000 {
+			compatible = "qcom,apq8084-saw2-v2.1-cpu";
+			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw1: power-controller@f9099000 {
+			compatible = "qcom,apq8084-saw2-v2.1-cpu";
+			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw2: power-controller@f90a9000 {
+			compatible = "qcom,apq8084-saw2-v2.1-cpu";
+			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw3: power-controller@f90b9000 {
+			compatible = "qcom,apq8084-saw2-v2.1-cpu";
+			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw_l2: power-controller@f9012000 {
 			compatible = "qcom,saw2";
 			reg = <0xf9012000 0x1000>;
 			regulator;
-- 
2.1.0

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v15 06/11] ARM: dts: qcom: Add power-controller device node for 8084 Krait CPUs

[Lina Iyer]

Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.

Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/boot/dts/qcom-apq8084.dtsi | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 1f130bc..71182bf 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -21,6 +21,7 @@
 			enable-method = "qcom,kpss-acc-v2";
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc0>;
+			qcom,saw = <&saw0>;
 		};
 
 		cpu at 1 {
@@ -30,6 +31,7 @@
 			enable-method = "qcom,kpss-acc-v2";
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc1>;
+			qcom,saw = <&saw1>;
 		};
 
 		cpu at 2 {
@@ -39,6 +41,7 @@
 			enable-method = "qcom,kpss-acc-v2";
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc2>;
+			qcom,saw = <&saw2>;
 		};
 
 		cpu at 3 {
@@ -48,6 +51,7 @@
 			enable-method = "qcom,kpss-acc-v2";
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc3>;
+			qcom,saw = <&saw3>;
 		};
 
 		L2: l2-cache {
@@ -144,7 +148,27 @@
 			};
 		};
 
-		saw_l2: regulator at f9012000 {
+		saw0: power-controller at f9089000 {
+			compatible = "qcom,apq8084-saw2-v2.1-cpu";
+			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw1: power-controller at f9099000 {
+			compatible = "qcom,apq8084-saw2-v2.1-cpu";
+			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw2: power-controller at f90a9000 {
+			compatible = "qcom,apq8084-saw2-v2.1-cpu";
+			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw3: power-controller at f90b9000 {
+			compatible = "qcom,apq8084-saw2-v2.1-cpu";
+			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
+		};
+
+		saw_l2: power-controller at f9012000 {
 			compatible = "qcom,saw2";
 			reg = <0xf9012000 0x1000>;
 			regulator;
-- 
2.1.0

[PATCH v15 09/11] ARM: dts: qcom: Add idle states device nodes for 8084

[Lina Iyer]

Add ARM common idle states device bindings for cpuidle support for APQ
8084.

Support standby and standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.

Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Signed-off-by: Lina Iyer <lina.iyer-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Reviewed-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 arch/arm/boot/dts/qcom-apq8084.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 71182bf..a3c24ff 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -22,6 +22,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc0>;
 			qcom,saw = <&saw0>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu@1 {
@@ -32,6 +33,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc1>;
 			qcom,saw = <&saw1>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu@2 {
@@ -42,6 +44,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc2>;
 			qcom,saw = <&saw2>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu@3 {
@@ -52,6 +55,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc3>;
 			qcom,saw = <&saw3>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		L2: l2-cache {
@@ -59,6 +63,24 @@
 			cache-level = <2>;
 			qcom,saw = <&saw_l2>;
 		};
+
+		idle-states {
+			CPU_STBY: standby {
+				compatible = "qcom,idle-state-stby",
+						"arm,idle-state";
+				entry-latency-us = <1>;
+				exit-latency-us = <1>;
+				min-residency-us = <2>;
+			};
+
+			CPU_SPC: spc {
+				compatible = "qcom,idle-state-spc",
+						"arm,idle-state";
+				entry-latency-us = <150>;
+				exit-latency-us = <200>;
+				min-residency-us = <2000>;
+			};
+		};
 	};
 
 	cpu-pmu {
-- 
2.1.0

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v15 09/11] ARM: dts: qcom: Add idle states device nodes for 8084

[Lina Iyer]

Add ARM common idle states device bindings for cpuidle support for APQ
8084.

Support standby and standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.

Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/boot/dts/qcom-apq8084.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 71182bf..a3c24ff 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -22,6 +22,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc0>;
 			qcom,saw = <&saw0>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu at 1 {
@@ -32,6 +33,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc1>;
 			qcom,saw = <&saw1>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu at 2 {
@@ -42,6 +44,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc2>;
 			qcom,saw = <&saw2>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu at 3 {
@@ -52,6 +55,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc3>;
 			qcom,saw = <&saw3>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		L2: l2-cache {
@@ -59,6 +63,24 @@
 			cache-level = <2>;
 			qcom,saw = <&saw_l2>;
 		};
+
+		idle-states {
+			CPU_STBY: standby {
+				compatible = "qcom,idle-state-stby",
+						"arm,idle-state";
+				entry-latency-us = <1>;
+				exit-latency-us = <1>;
+				min-residency-us = <2>;
+			};
+
+			CPU_SPC: spc {
+				compatible = "qcom,idle-state-spc",
+						"arm,idle-state";
+				entry-latency-us = <150>;
+				exit-latency-us = <200>;
+				min-residency-us = <2000>;
+			};
+		};
 	};
 
 	cpu-pmu {
-- 
2.1.0

[PATCH v15 07/11] ARM: dts: qcom: Update power-controller device node for 8064 Krait CPUs

[Lina Iyer]

Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.

Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index b3154c0..9fd24bc 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -139,26 +139,26 @@
 			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 		};
 
-		saw0: regulator@2089000 {
-			compatible = "qcom,saw2";
+		saw0: power-controller@2089000 {
+			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 			regulator;
 		};
 
-		saw1: regulator@2099000 {
-			compatible = "qcom,saw2";
+		saw1: power-controller@2099000 {
+			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 			regulator;
 		};
 
-		saw2: regulator@20a9000 {
-			compatible = "qcom,saw2";
+		saw2: power-controller@20a9000 {
+			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 			regulator;
 		};
 
-		saw3: regulator@20b9000 {
-			compatible = "qcom,saw2";
+		saw3: power-controller@20b9000 {
+			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 			regulator;
 		};
-- 
2.1.0

[PATCH v15 07/11] ARM: dts: qcom: Update power-controller device node for 8064 Krait CPUs

[Lina Iyer]

Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.

Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index b3154c0..9fd24bc 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -139,26 +139,26 @@
 			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 		};
 
-		saw0: regulator at 2089000 {
-			compatible = "qcom,saw2";
+		saw0: power-controller at 2089000 {
+			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 			regulator;
 		};
 
-		saw1: regulator at 2099000 {
-			compatible = "qcom,saw2";
+		saw1: power-controller at 2099000 {
+			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 			regulator;
 		};
 
-		saw2: regulator at 20a9000 {
-			compatible = "qcom,saw2";
+		saw2: power-controller at 20a9000 {
+			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 			regulator;
 		};
 
-		saw3: regulator at 20b9000 {
-			compatible = "qcom,saw2";
+		saw3: power-controller at 20b9000 {
+			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 			regulator;
 		};
-- 
2.1.0

[PATCH v15 08/11] ARM: dts: qcom: Add idle states device nodes for 8074

[Lina Iyer]

Add ARM common idle states device bindings for cpuidle support for APQ
8074/8974.

Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.

Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/boot/dts/qcom-msm8974.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 5a41f44..ea31c3a 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -22,6 +22,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc0>;
 			qcom,saw = <&saw0>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu@1 {
@@ -32,6 +33,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc1>;
 			qcom,saw = <&saw1>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu@2 {
@@ -42,6 +44,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc2>;
 			qcom,saw = <&saw2>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu@3 {
@@ -52,6 +55,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc3>;
 			qcom,saw = <&saw3>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		L2: l2-cache {
@@ -59,6 +63,24 @@
 			cache-level = <2>;
 			qcom,saw = <&saw_l2>;
 		};
+
+		idle-states {
+			CPU_STBY: standby {
+				compatible = "qcom,idle-state-stby",
+						"arm,idle-state";
+				entry-latency-us = <1>;
+				exit-latency-us = <1>;
+				min-residency-us = <2>;
+			};
+
+			CPU_SPC: spc {
+				compatible = "qcom,idle-state-spc",
+						"arm,idle-state";
+				entry-latency-us = <150>;
+				exit-latency-us = <200>;
+				min-residency-us = <2000>;
+			};
+		};
 	};
 
 	cpu-pmu {
-- 
2.1.0

[PATCH v15 08/11] ARM: dts: qcom: Add idle states device nodes for 8074

[Lina Iyer]

Add ARM common idle states device bindings for cpuidle support for APQ
8074/8974.

Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.

Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/boot/dts/qcom-msm8974.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 5a41f44..ea31c3a 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -22,6 +22,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc0>;
 			qcom,saw = <&saw0>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu at 1 {
@@ -32,6 +33,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc1>;
 			qcom,saw = <&saw1>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu at 2 {
@@ -42,6 +44,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc2>;
 			qcom,saw = <&saw2>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu at 3 {
@@ -52,6 +55,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc3>;
 			qcom,saw = <&saw3>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		L2: l2-cache {
@@ -59,6 +63,24 @@
 			cache-level = <2>;
 			qcom,saw = <&saw_l2>;
 		};
+
+		idle-states {
+			CPU_STBY: standby {
+				compatible = "qcom,idle-state-stby",
+						"arm,idle-state";
+				entry-latency-us = <1>;
+				exit-latency-us = <1>;
+				min-residency-us = <2>;
+			};
+
+			CPU_SPC: spc {
+				compatible = "qcom,idle-state-spc",
+						"arm,idle-state";
+				entry-latency-us = <150>;
+				exit-latency-us = <200>;
+				min-residency-us = <2000>;
+			};
+		};
 	};
 
 	cpu-pmu {
-- 
2.1.0

[PATCH v15 10/11] ARM: dts: qcom: Add idle state device nodes for 8064

[Lina Iyer]

Add ARM common idle state device bindings for cpuidle support for APQ
8064.

Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.

Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 9fd24bc..08893fd 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -23,6 +23,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc0>;
 			qcom,saw = <&saw0>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu@1 {
@@ -33,6 +34,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc1>;
 			qcom,saw = <&saw1>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu@2 {
@@ -43,6 +45,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc2>;
 			qcom,saw = <&saw2>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu@3 {
@@ -53,12 +56,31 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc3>;
 			qcom,saw = <&saw3>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		L2: l2-cache {
 			compatible = "cache";
 			cache-level = <2>;
 		};
+
+		idle-states {
+			CPU_STBY: standby {
+				compatible = "qcom,idle-state-stby",
+						"arm,idle-state";
+				entry-latency-us = <1>;
+				exit-latency-us = <1>;
+				min-residency-us = <2>;
+			};
+
+			CPU_SPC: spc {
+				compatible = "qcom,idle-state-spc",
+						"arm,idle-state";
+				entry-latency-us = <400>;
+				exit-latency-us = <900>;
+				min-residency-us = <3000>;
+			};
+		};
 	};
 
 	cpu-pmu {
-- 
2.1.0

[PATCH v15 10/11] ARM: dts: qcom: Add idle state device nodes for 8064

[Lina Iyer]

Add ARM common idle state device bindings for cpuidle support for APQ
8064.

Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.

Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 9fd24bc..08893fd 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -23,6 +23,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc0>;
 			qcom,saw = <&saw0>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu at 1 {
@@ -33,6 +34,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc1>;
 			qcom,saw = <&saw1>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu at 2 {
@@ -43,6 +45,7 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc2>;
 			qcom,saw = <&saw2>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		cpu at 3 {
@@ -53,12 +56,31 @@
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc3>;
 			qcom,saw = <&saw3>;
+			cpu-idle-states = <&CPU_STBY &CPU_SPC>;
 		};
 
 		L2: l2-cache {
 			compatible = "cache";
 			cache-level = <2>;
 		};
+
+		idle-states {
+			CPU_STBY: standby {
+				compatible = "qcom,idle-state-stby",
+						"arm,idle-state";
+				entry-latency-us = <1>;
+				exit-latency-us = <1>;
+				min-residency-us = <2>;
+			};
+
+			CPU_SPC: spc {
+				compatible = "qcom,idle-state-spc",
+						"arm,idle-state";
+				entry-latency-us = <400>;
+				exit-latency-us = <900>;
+				min-residency-us = <3000>;
+			};
+		};
 	};
 
 	cpu-pmu {
-- 
2.1.0

[PATCH v15 11/11] ARM: qcom: Update defconfig

[Lina Iyer]

* Enable QCOM_PM
* Enable ARM_CPUIDLE

Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 arch/arm/configs/qcom_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 8c7da33..33a5339 100644
--- a/arch/arm/configs/qcom_defconfig
+++ b/arch/arm/configs/qcom_defconfig
@@ -30,6 +30,7 @@ CONFIG_CLEANCACHE=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CPU_IDLE=y
+CONFIG_ARM_CPUIDLE=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
@@ -135,6 +136,7 @@ CONFIG_DMADEVICES=y
 CONFIG_QCOM_BAM_DMA=y
 CONFIG_STAGING=y
 CONFIG_QCOM_GSBI=y
+CONFIG_QCOM_PM=y
 CONFIG_COMMON_CLK_QCOM=y
 CONFIG_APQ_MMCC_8084=y
 CONFIG_IPQ_GCC_806X=y
-- 
2.1.0

[PATCH v15 11/11] ARM: qcom: Update defconfig

[Lina Iyer]

* Enable QCOM_PM
* Enable ARM_CPUIDLE

Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 arch/arm/configs/qcom_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 8c7da33..33a5339 100644
--- a/arch/arm/configs/qcom_defconfig
+++ b/arch/arm/configs/qcom_defconfig
@@ -30,6 +30,7 @@ CONFIG_CLEANCACHE=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CPU_IDLE=y
+CONFIG_ARM_CPUIDLE=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
@@ -135,6 +136,7 @@ CONFIG_DMADEVICES=y
 CONFIG_QCOM_BAM_DMA=y
 CONFIG_STAGING=y
 CONFIG_QCOM_GSBI=y
+CONFIG_QCOM_PM=y
 CONFIG_COMMON_CLK_QCOM=y
 CONFIG_APQ_MMCC_8084=y
 CONFIG_IPQ_GCC_806X=y
-- 
2.1.0