All sort of cdclk stuff

All sort of cdclk stuff

[Mika Kahola]

This patch series rebases Ville's original cdclk patch series

http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html

The patches include modifications to

  drm/i915: Return more precise cdclk for gen2/3
  drm/i915: Fix i855_get_display_clock_speed()
  drm/i915: Fix 852GM/GMV cdclk
  drm/i915: Add cdclk extraction for g33, 965gm and g4x
  drm/i915: ILK cdclk seems to be 450MHz
  drm/i915: Assume 400 MHz cdclk for the rest of gen4-7
  drm/i915: Simplify ilk_get_aux_clock_divider()
  drm/i915: Convert the ddi cdclk code to .get_display_clock_speed()
  drm/i915: Warn when cdclk for the platforms is not known
  drm/i915: Cache the current cdclk frequency in dev_priv
  drm/i915: Use cached cdclk value
  drm/i915: Unify ilk and hsw .get_aux_clock_divider()
  drm/i915: Store max cdclk value in dev_priv
  drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk
  drm/i915: Fix chv cdclk support
  drm/i915: HSW cdclk change support
  drm/i915: Add IS_BDW_ULX()
  drm/i915: BDW cdclk change support
  drm/i915: Limit CHV max cdclk to 320 MHz
  drm/i915: Combined VLV, HSW, and BDW global pipe conf into single function
            'intel_modeset_global_pipes()'

-- 
Mika Kahola, Intel OTC
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[PATCH 01/19] drm/i915: Return more precise cdclk for gen2/3

[Mika Kahola]

Fill out the lower three digits for gen2 and gen3 cdclk frqeuncy. It's
not clear if these are accurate frquencies or just in the ballpark, but
without docs this is the best we can do.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a693129..2bf960f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5893,7 +5893,7 @@ static int i945_get_display_clock_speed(struct drm_device *dev)
 
 static int i915_get_display_clock_speed(struct drm_device *dev)
 {
-	return 333000;
+	return 333333;
 }
 
 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
@@ -5909,19 +5909,19 @@ static int pnv_get_display_clock_speed(struct drm_device *dev)
 
 	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
-		return 267000;
+		return 266667;
 	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
-		return 333000;
+		return 333333;
 	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
-		return 444000;
+		return 444444;
 	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 		return 200000;
 	default:
 		DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
 	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
-		return 133000;
+		return 133333;
 	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
-		return 167000;
+		return 166667;
 	}
 }
 
@@ -5932,11 +5932,11 @@ static int i915gm_get_display_clock_speed(struct drm_device *dev)
 	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
 
 	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
-		return 133000;
+		return 133333;
 	else {
 		switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 		case GC_DISPLAY_CLOCK_333_MHZ:
-			return 333000;
+			return 333333;
 		default:
 		case GC_DISPLAY_CLOCK_190_200_MHZ:
 			return 190000;
@@ -5946,7 +5946,7 @@ static int i915gm_get_display_clock_speed(struct drm_device *dev)
 
 static int i865_get_display_clock_speed(struct drm_device *dev)
 {
-	return 266000;
+	return 266667;
 }
 
 static int i855_get_display_clock_speed(struct drm_device *dev)
@@ -5962,7 +5962,7 @@ static int i855_get_display_clock_speed(struct drm_device *dev)
 	case GC_CLOCK_166_250:
 		return 250000;
 	case GC_CLOCK_100_133:
-		return 133000;
+		return 133333;
 	}
 
 	/* Shouldn't happen */
@@ -5971,7 +5971,7 @@ static int i855_get_display_clock_speed(struct drm_device *dev)
 
 static int i830_get_display_clock_speed(struct drm_device *dev)
 {
-	return 133000;
+	return 133333;
 }
 
 static void
-- 
1.9.1

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Re: [PATCH 01/19] drm/i915: Return more precise cdclk for gen2/3

[Damien Lespiau]

On Tue, Mar 31, 2015 at 02:09:47PM +0300, Mika Kahola wrote:
> Fill out the lower three digits for gen2 and gen3 cdclk frqeuncy. It's
> not clear if these are accurate frquencies or just in the ballpark, but
> without docs this is the best we can do.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 22 +++++++++++-----------
>  1 file changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a693129..2bf960f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5893,7 +5893,7 @@ static int i945_get_display_clock_speed(struct drm_device *dev)
>  
>  static int i915_get_display_clock_speed(struct drm_device *dev)
>  {
> -	return 333000;
> +	return 333333;
>  }
>  
>  static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
> @@ -5909,19 +5909,19 @@ static int pnv_get_display_clock_speed(struct drm_device *dev)
>  
>  	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
>  	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
> -		return 267000;
> +		return 266667;
>  	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
> -		return 333000;
> +		return 333333;
>  	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
> -		return 444000;
> +		return 444444;
>  	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
>  		return 200000;
>  	default:
>  		DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
>  	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
> -		return 133000;
> +		return 133333;
>  	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
> -		return 167000;
> +		return 166667;
>  	}
>  }
>  
> @@ -5932,11 +5932,11 @@ static int i915gm_get_display_clock_speed(struct drm_device *dev)
>  	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
>  
>  	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
> -		return 133000;
> +		return 133333;
>  	else {
>  		switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
>  		case GC_DISPLAY_CLOCK_333_MHZ:
> -			return 333000;
> +			return 333333;
>  		default:
>  		case GC_DISPLAY_CLOCK_190_200_MHZ:
>  			return 190000;
> @@ -5946,7 +5946,7 @@ static int i915gm_get_display_clock_speed(struct drm_device *dev)
>  
>  static int i865_get_display_clock_speed(struct drm_device *dev)
>  {
> -	return 266000;
> +	return 266667;
>  }
>  
>  static int i855_get_display_clock_speed(struct drm_device *dev)
> @@ -5962,7 +5962,7 @@ static int i855_get_display_clock_speed(struct drm_device *dev)
>  	case GC_CLOCK_166_250:
>  		return 250000;
>  	case GC_CLOCK_100_133:
> -		return 133000;
> +		return 133333;
>  	}
>  
>  	/* Shouldn't happen */
> @@ -5971,7 +5971,7 @@ static int i855_get_display_clock_speed(struct drm_device *dev)
>  
>  static int i830_get_display_clock_speed(struct drm_device *dev)
>  {
> -	return 133000;
> +	return 133333;
>  }
>  
>  static void
> -- 
> 1.9.1
> 
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH 02/19] drm/i915: Fix i855 get_display_clock_speed

[Mika Kahola]

Actually read the HPLLCC register insted of assuming it's 0. Fix the
HPLLCC bit definitions and all the missing ones from the 852GME spec.

852GME, 854 and 855 all seem to match the same HPLLC encoding even
though only some of the values are valid is some of the platforms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 11 ++++++++---
 drivers/gpu/drm/i915/intel_display.c | 15 ++++++++++++---
 2 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b522eb6..ee6b306 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -50,12 +50,17 @@
 
 /* PCI config space */
 
-#define HPLLCC	0xc0 /* 855 only */
-#define   GC_CLOCK_CONTROL_MASK		(0xf << 0)
+#define HPLLCC	0xc0 /* 85x only */
+#define   GC_CLOCK_CONTROL_MASK		(0x7 << 0)
 #define   GC_CLOCK_133_200		(0 << 0)
 #define   GC_CLOCK_100_200		(1 << 0)
 #define   GC_CLOCK_100_133		(2 << 0)
-#define   GC_CLOCK_166_250		(3 << 0)
+#define   GC_CLOCK_133_266		(3 << 0)
+#define   GC_CLOCK_133_200_2		(4 << 0)
+#define   GC_CLOCK_133_266_2		(5 << 0)
+#define   GC_CLOCK_166_266		(6 << 0)
+#define   GC_CLOCK_166_250		(7 << 0)
+
 #define GCFGC2	0xda
 #define GCFGC	0xf0 /* 915+ only */
 #define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2bf960f..10d3188 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5949,20 +5949,29 @@ static int i865_get_display_clock_speed(struct drm_device *dev)
 	return 266667;
 }
 
-static int i855_get_display_clock_speed(struct drm_device *dev)
+static int i85x_get_display_clock_speed(struct drm_device *dev)
 {
 	u16 hpllcc = 0;
+
+	pci_bus_read_config_word(dev->pdev->bus,
+				 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
+
 	/* Assume that the hardware is in the high speed state.  This
 	 * should be the default.
 	 */
 	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 	case GC_CLOCK_133_200:
+	case GC_CLOCK_133_200_2:
 	case GC_CLOCK_100_200:
 		return 200000;
 	case GC_CLOCK_166_250:
 		return 250000;
 	case GC_CLOCK_100_133:
 		return 133333;
+	case GC_CLOCK_133_266:
+	case GC_CLOCK_133_266_2:
+	case GC_CLOCK_166_266:
+		return 266667;
 	}
 
 	/* Shouldn't happen */
@@ -13519,8 +13528,8 @@ static void intel_init_display(struct drm_device *dev)
 			i865_get_display_clock_speed;
 	else if (IS_I85X(dev))
 		dev_priv->display.get_display_clock_speed =
-			i855_get_display_clock_speed;
-	else /* 852, 830 */
+			i85x_get_display_clock_speed;
+	else /* 830 */
 		dev_priv->display.get_display_clock_speed =
 			i830_get_display_clock_speed;
 
-- 
1.9.1

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[PATCH 04/19] drm/i915: Add cdclk extraction for g33, g965gm and g4x

[Mika Kahola]

Implement cdclk extraction for g33, 965gm and g4x platforms. The details
came from configdb. Sadly there isn't anything there for other gen3/gen4
chipsets.

So far I've tested this on one ELK where it gave me a HPLL VCO of 5333
MHz and cdclk of 444 MHz which seems perfectly sane for this machine.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |   3 +
 drivers/gpu/drm/i915/intel_display.c | 186 ++++++++++++++++++++++++++++++++++-
 2 files changed, 185 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ee6b306..f26ebd2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2223,6 +2223,9 @@ enum skl_disp_power_wells {
 #define CLKCFG_MEM_800					(3 << 4)
 #define CLKCFG_MEM_MASK					(7 << 4)
 
+#define HPLLVCO				(MCHBAR_MIRROR_BASE + 0xc38)
+#define HPLLVCO_MOBILE			(MCHBAR_MIRROR_BASE + 0xc0f)
+
 #define TSC1			0x11001
 #define   TSE			(1<<0)
 #define TR1			0x11006
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 774dc6e..bebbfd2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5991,6 +5991,175 @@ static int i830_get_display_clock_speed(struct drm_device *dev)
 	return 133333;
 }
 
+static unsigned int intel_hpll_vco(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	static const unsigned int blb_vco[8] = {
+		[0] = 3200000,
+		[1] = 4000000,
+		[2] = 5333333,
+		[3] = 4800000,
+		[4] = 6400000,
+	};
+	static const unsigned int pnv_vco[8] = {
+		[0] = 3200000,
+		[1] = 4000000,
+		[2] = 5333333,
+		[3] = 4800000,
+		[4] = 2666667,
+	};
+	static const unsigned int cl_vco[8] = {
+		[0] = 3200000,
+		[1] = 4000000,
+		[2] = 5333333,
+		[3] = 6400000,
+		[4] = 3333333,
+		[5] = 3566667,
+		[6] = 4266667,
+	};
+	static const unsigned int elk_vco[8] = {
+		[0] = 3200000,
+		[1] = 4000000,
+		[2] = 5333333,
+		[3] = 4800000,
+	};
+	static const unsigned int ctg_vco[8] = {
+		[0] = 3200000,
+		[1] = 4000000,
+		[2] = 5333333,
+		[3] = 6400000,
+		[4] = 2666667,
+		[5] = 4266667,
+	};
+	const unsigned int *vco_table;
+	unsigned int vco;
+	uint8_t tmp = 0;
+
+	/* FIXME other chipsets? */
+	if (IS_GM45(dev))
+		vco_table = ctg_vco;
+	else if (IS_G4X(dev))
+		vco_table = elk_vco;
+	else if (IS_CRESTLINE(dev))
+		vco_table = cl_vco;
+	else if (IS_PINEVIEW(dev))
+		vco_table = pnv_vco;
+	else if (IS_G33(dev))
+		vco_table = blb_vco;
+	else
+		return 0;
+
+	tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
+
+	vco = vco_table[tmp & 0x7];
+	if (vco == 0)
+		DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
+	else
+		DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
+
+	return vco;
+}
+
+static int gm45_get_display_clock_speed(struct drm_device *dev)
+{
+	unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
+	uint16_t tmp = 0;
+
+	pci_read_config_word(dev->pdev, GCFGC, &tmp);
+
+	cdclk_sel = (tmp >> 12) & 0x1;
+
+	switch (vco) {
+	case 2666667:
+	case 4000000:
+	case 5333333:
+		return cdclk_sel ? 333333 : 222222;
+	case 3200000:
+		return cdclk_sel ? 320000 : 228571;
+	default:
+		DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
+		return 222222;
+	}
+}
+
+static int i965gm_get_display_clock_speed(struct drm_device *dev)
+{
+	static const uint8_t div_3200[] = { 16, 10,  8 };
+	static const uint8_t div_4000[] = { 20, 12, 10 };
+	static const uint8_t div_5333[] = { 24, 16, 14 };
+	const uint8_t *div_table;
+	unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
+	uint16_t tmp = 0;
+
+	pci_read_config_word(dev->pdev, GCFGC, &tmp);
+
+	cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
+
+	if (cdclk_sel >= ARRAY_SIZE(div_3200))
+		goto fail;
+
+	switch (vco) {
+	case 3200000:
+		div_table = div_3200;
+		break;
+	case 4000000:
+		div_table = div_4000;
+		break;
+	case 5333333:
+		div_table = div_5333;
+		break;
+	default:
+		goto fail;
+	}
+
+	return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
+
+ fail:
+	DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
+	return 200000;
+}
+
+static int g33_get_display_clock_speed(struct drm_device *dev)
+{
+	static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
+	static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
+	static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
+	static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
+	const uint8_t *div_table;
+	unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
+	uint16_t tmp = 0;
+
+	pci_read_config_word(dev->pdev, GCFGC, &tmp);
+
+	cdclk_sel = (tmp >> 4) & 0x7;
+
+	if (cdclk_sel >= ARRAY_SIZE(div_3200))
+		goto fail;
+
+	switch (vco) {
+	case 3200000:
+		div_table = div_3200;
+		break;
+	case 4000000:
+		div_table = div_4000;
+		break;
+	case 4800000:
+		div_table = div_4800;
+		break;
+	case 5333333:
+		div_table = div_5333;
+		break;
+	default:
+		goto fail;
+	}
+
+	return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
+
+ fail:
+	DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
+	return 190476;
+}
+
 static void
 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
 {
@@ -13516,7 +13685,19 @@ static void intel_init_display(struct drm_device *dev)
 	if (IS_VALLEYVIEW(dev))
 		dev_priv->display.get_display_clock_speed =
 			valleyview_get_display_clock_speed;
-	else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
+	else if (IS_GM45(dev))
+		dev_priv->display.get_display_clock_speed =
+			gm45_get_display_clock_speed;
+	else if (IS_CRESTLINE(dev))
+		dev_priv->display.get_display_clock_speed =
+			i965gm_get_display_clock_speed;
+	else if (IS_PINEVIEW(dev))
+		dev_priv->display.get_display_clock_speed =
+			pnv_get_display_clock_speed;
+	else if (IS_G33(dev) || IS_G4X(dev))
+		dev_priv->display.get_display_clock_speed =
+			g33_get_display_clock_speed;
+	else if (IS_I945G(dev))
 		dev_priv->display.get_display_clock_speed =
 			i945_get_display_clock_speed;
 	else if (IS_I915G(dev))
@@ -13525,9 +13706,6 @@ static void intel_init_display(struct drm_device *dev)
 	else if (IS_I945GM(dev) || IS_845G(dev))
 		dev_priv->display.get_display_clock_speed =
 			i9xx_misc_get_display_clock_speed;
-	else if (IS_PINEVIEW(dev))
-		dev_priv->display.get_display_clock_speed =
-			pnv_get_display_clock_speed;
 	else if (IS_I915GM(dev))
 		dev_priv->display.get_display_clock_speed =
 			i915gm_get_display_clock_speed;
-- 
1.9.1

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[PATCH 05/19] drm/i915: ILK cdclk seems to be 450MHz

[Mika Kahola]

Based on the BIOS DP A AUX 2x clock divider the cdclk frequency
on ILK is 450Mhz. At least that holds on my ILK and it matches
how we program the divider.

Supposedly cdclk is 400MHz on SNB and IVB, again based on the AUX 2x
clock divider. Note that I don't have a SNB or IVB machine with
eDP so I couldn't verify what the BIOS used, so this notion is
purely based on our current code,

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bebbfd2..5df9c47 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5886,6 +5886,11 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev)
 	return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 }
 
+static int ilk_get_display_clock_speed(struct drm_device *dev)
+{
+	return 450000;
+}
+
 static int i945_get_display_clock_speed(struct drm_device *dev)
 {
 	return 400000;
@@ -13685,6 +13690,9 @@ static void intel_init_display(struct drm_device *dev)
 	if (IS_VALLEYVIEW(dev))
 		dev_priv->display.get_display_clock_speed =
 			valleyview_get_display_clock_speed;
+	else if (IS_GEN5(dev))
+		dev_priv->display.get_display_clock_speed =
+			ilk_get_display_clock_speed;
 	else if (IS_GM45(dev))
 		dev_priv->display.get_display_clock_speed =
 			gm45_get_display_clock_speed;
-- 
1.9.1

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Re: [PATCH 05/19] drm/i915: ILK cdclk seems to be 450MHz

[Damien Lespiau]

On Tue, Mar 31, 2015 at 02:11:54PM +0300, Mika Kahola wrote:
> Based on the BIOS DP A AUX 2x clock divider the cdclk frequency
> on ILK is 450Mhz. At least that holds on my ILK and it matches
> how we program the divider.
> 
> Supposedly cdclk is 400MHz on SNB and IVB, again based on the AUX 2x
> clock divider. Note that I don't have a SNB or IVB machine with
> eDP so I couldn't verify what the BIOS used, so this notion is
> purely based on our current code,
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bebbfd2..5df9c47 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5886,6 +5886,11 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev)
>  	return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
>  }
>  
> +static int ilk_get_display_clock_speed(struct drm_device *dev)
> +{
> +	return 450000;
> +}
> +
>  static int i945_get_display_clock_speed(struct drm_device *dev)
>  {
>  	return 400000;
> @@ -13685,6 +13690,9 @@ static void intel_init_display(struct drm_device *dev)
>  	if (IS_VALLEYVIEW(dev))
>  		dev_priv->display.get_display_clock_speed =
>  			valleyview_get_display_clock_speed;
> +	else if (IS_GEN5(dev))
> +		dev_priv->display.get_display_clock_speed =
> +			ilk_get_display_clock_speed;
>  	else if (IS_GM45(dev))
>  		dev_priv->display.get_display_clock_speed =
>  			gm45_get_display_clock_speed;
> -- 
> 1.9.1
> 
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH 06/19] drm/i915: Assume 400MHz cdclk for the rest of gen4-7

[Mika Kahola]

We don't currently have cdclk extraction code for 965g,snb,ivb.
Let's assume 400 MHz until we know better. That seems to match hints
in various vague documents. Whether that's good enough is not
entirely clear.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5df9c47..4a4fdb0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13705,7 +13705,8 @@ static void intel_init_display(struct drm_device *dev)
 	else if (IS_G33(dev) || IS_G4X(dev))
 		dev_priv->display.get_display_clock_speed =
 			g33_get_display_clock_speed;
-	else if (IS_I945G(dev))
+	else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
+		 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
 		dev_priv->display.get_display_clock_speed =
 			i945_get_display_clock_speed;
 	else if (IS_I915G(dev))
-- 
1.9.1

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Re: [PATCH 06/19] drm/i915: Assume 400MHz cdclk for the rest of gen4-7

[Damien Lespiau]

On Tue, Mar 31, 2015 at 02:11:56PM +0300, Mika Kahola wrote:
> We don't currently have cdclk extraction code for 965g,snb,ivb.
> Let's assume 400 MHz until we know better. That seems to match hints
> in various vague documents. Whether that's good enough is not
> entirely clear.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---

Acked-by: Damien Lespiau <damien.lespiau@intel.com>

>  drivers/gpu/drm/i915/intel_display.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5df9c47..4a4fdb0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13705,7 +13705,8 @@ static void intel_init_display(struct drm_device *dev)
>  	else if (IS_G33(dev) || IS_G4X(dev))
>  		dev_priv->display.get_display_clock_speed =
>  			g33_get_display_clock_speed;
> -	else if (IS_I945G(dev))
> +	else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
> +		 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
>  		dev_priv->display.get_display_clock_speed =
>  			i945_get_display_clock_speed;
>  	else if (IS_I915G(dev))
> -- 
> 1.9.1
> 
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[PATCH 07/19] drm/i915: Simplify ilk_get_aux_clock_divider

[Mika Kahola]

Now that we are "extracting" the cdclk frequency on ILK-IVB we
can also simplify ilk_get_aux_clock_divider() to calculate the
divider based on cdclk instead of hardcoding the values.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9b741b5..e38dbd5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -696,15 +696,13 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	if (index)
 		return 0;
 
 	if (intel_dig_port->port == PORT_A) {
-		if (IS_GEN6(dev) || IS_GEN7(dev))
-			return 200; /* SNB & IVB eDP input clock at 400Mhz */
-		else
-			return 225; /* eDP input clock at 450Mhz */
+		return DIV_ROUND_UP(dev_priv->display.get_display_clock_speed(dev), 2000);
 	} else {
 		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 	}
-- 
1.9.1

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Re: [PATCH 07/19] drm/i915: Simplify ilk_get_aux_clock_divider

[Damien Lespiau]

On Tue, Mar 31, 2015 at 02:11:59PM +0300, Mika Kahola wrote:
> Now that we are "extracting" the cdclk frequency on ILK-IVB we
> can also simplify ilk_get_aux_clock_divider() to calculate the
> divider based on cdclk instead of hardcoding the values.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

>  drivers/gpu/drm/i915/intel_dp.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9b741b5..e38dbd5 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -696,15 +696,13 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
>  {
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	if (index)
>  		return 0;
>  
>  	if (intel_dig_port->port == PORT_A) {
> -		if (IS_GEN6(dev) || IS_GEN7(dev))
> -			return 200; /* SNB & IVB eDP input clock at 400Mhz */
> -		else
> -			return 225; /* eDP input clock at 450Mhz */
> +		return DIV_ROUND_UP(dev_priv->display.get_display_clock_speed(dev), 2000);
>  	} else {
>  		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
>  	}
> -- 
> 1.9.1
> 
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[PATCH 08/19] drm/i915: Convert the ddi cdclk code to get_display_clock_speed

[Mika Kahola]

Unify the HSW/BDW/SKL cdclk extraction code to conform to the same
.get_display_clock_speed() mold that all the other platforms
use.

v2: Update due to SKL code getting added

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_audio.c   |   3 +-
 drivers/gpu/drm/i915/intel_ddi.c     | 101 +----------------------------------
 drivers/gpu/drm/i915/intel_display.c |  98 ++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_dp.c      |   2 +-
 drivers/gpu/drm/i915/intel_drv.h     |   1 -
 drivers/gpu/drm/i915/intel_pm.c      |   2 +-
 6 files changed, 102 insertions(+), 105 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 2396cc7..0d5b1ce 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -485,7 +485,8 @@ static int i915_audio_component_get_cdclk_freq(struct device *dev)
 		return -ENODEV;
 
 	intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
-	ret = intel_ddi_get_cdclk_freq(dev_priv);
+	ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
+
 	intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
 
 	return ret;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 47b9307..8c692d8 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1689,105 +1689,6 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
 	}
 }
 
-static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
-{
-	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
-	uint32_t cdctl = I915_READ(CDCLK_CTL);
-	uint32_t linkrate;
-
-	if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
-		WARN(1, "LCPLL1 not enabled\n");
-		return 24000; /* 24MHz is the cd freq with NSSC ref */
-	}
-
-	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
-		return 540000;
-
-	linkrate = (I915_READ(DPLL_CTRL1) &
-		    DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
-
-	if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
-	    linkrate == DPLL_CRTL1_LINK_RATE_1080) {
-		/* vco 8640 */
-		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
-		case CDCLK_FREQ_450_432:
-			return 432000;
-		case CDCLK_FREQ_337_308:
-			return 308570;
-		case CDCLK_FREQ_675_617:
-			return 617140;
-		default:
-			WARN(1, "Unknown cd freq selection\n");
-		}
-	} else {
-		/* vco 8100 */
-		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
-		case CDCLK_FREQ_450_432:
-			return 450000;
-		case CDCLK_FREQ_337_308:
-			return 337500;
-		case CDCLK_FREQ_675_617:
-			return 675000;
-		default:
-			WARN(1, "Unknown cd freq selection\n");
-		}
-	}
-
-	/* error case, do as if DPLL0 isn't enabled */
-	return 24000;
-}
-
-static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
-{
-	uint32_t lcpll = I915_READ(LCPLL_CTL);
-	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
-
-	if (lcpll & LCPLL_CD_SOURCE_FCLK)
-		return 800000;
-	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
-		return 450000;
-	else if (freq == LCPLL_CLK_FREQ_450)
-		return 450000;
-	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
-		return 540000;
-	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
-		return 337500;
-	else
-		return 675000;
-}
-
-static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
-{
-	struct drm_device *dev = dev_priv->dev;
-	uint32_t lcpll = I915_READ(LCPLL_CTL);
-	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
-
-	if (lcpll & LCPLL_CD_SOURCE_FCLK)
-		return 800000;
-	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
-		return 450000;
-	else if (freq == LCPLL_CLK_FREQ_450)
-		return 450000;
-	else if (IS_HSW_ULT(dev))
-		return 337500;
-	else
-		return 540000;
-}
-
-int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
-{
-	struct drm_device *dev = dev_priv->dev;
-
-	if (IS_SKYLAKE(dev))
-		return skl_get_cdclk_freq(dev_priv);
-
-	if (IS_BROADWELL(dev))
-		return bdw_get_cdclk_freq(dev_priv);
-
-	/* Haswell */
-	return hsw_get_cdclk_freq(dev_priv);
-}
-
 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
 			       struct intel_shared_dpll *pll)
 {
@@ -1974,7 +1875,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
 		hsw_shared_dplls_init(dev_priv);
 
 	DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
-		      intel_ddi_get_cdclk_freq(dev_priv));
+		      dev_priv->display.get_display_clock_speed(dev));
 
 	if (IS_SKYLAKE(dev)) {
 		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4a4fdb0..6e33258 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5864,6 +5864,93 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 	return 0;
 }
 
+static int skylake_get_display_clock_speed(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
+	uint32_t cdctl = I915_READ(CDCLK_CTL);
+	uint32_t linkrate;
+
+	if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
+		WARN(1, "LCPLL1 not enabled\n");
+		return 24000; /* 24MHz is the cd freq with NSSC ref */
+	}
+
+	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
+		return 540000;
+
+	linkrate = (I915_READ(DPLL_CTRL1) &
+		    DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
+
+	if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
+	    linkrate == DPLL_CRTL1_LINK_RATE_1080) {
+		/* vco 8640 */
+		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
+		case CDCLK_FREQ_450_432:
+			return 432000;
+		case CDCLK_FREQ_337_308:
+			return 308570;
+		case CDCLK_FREQ_675_617:
+			return 617140;
+		default:
+			WARN(1, "Unknown cd freq selection\n");
+		}
+	} else {
+		/* vco 8100 */
+		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
+		case CDCLK_FREQ_450_432:
+			return 450000;
+		case CDCLK_FREQ_337_308:
+			return 337500;
+		case CDCLK_FREQ_675_617:
+			return 675000;
+		default:
+			WARN(1, "Unknown cd freq selection\n");
+		}
+	}
+
+	/* error case, do as if DPLL0 isn't enabled */
+	return 24000;
+}
+
+static int broadwell_get_display_clock_speed(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t lcpll = I915_READ(LCPLL_CTL);
+	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
+
+	if (lcpll & LCPLL_CD_SOURCE_FCLK)
+		return 800000;
+	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
+		return 450000;
+	else if (freq == LCPLL_CLK_FREQ_450)
+		return 450000;
+	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
+		return 540000;
+	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
+		return 337500;
+	else
+		return 675000;
+}
+
+static int haswell_get_display_clock_speed(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t lcpll = I915_READ(LCPLL_CTL);
+	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
+
+	if (lcpll & LCPLL_CD_SOURCE_FCLK)
+		return 800000;
+	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
+		return 450000;
+	else if (freq == LCPLL_CLK_FREQ_450)
+		return 450000;
+	else if (IS_HSW_ULT(dev))
+		return 337500;
+	else
+		return 540000;
+}
+
 static int valleyview_get_display_clock_speed(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -13687,7 +13774,16 @@ static void intel_init_display(struct drm_device *dev)
 	}
 
 	/* Returns the core display clock speed */
-	if (IS_VALLEYVIEW(dev))
+	if (IS_SKYLAKE(dev))
+		dev_priv->display.get_display_clock_speed =
+			skylake_get_display_clock_speed;
+	else if (IS_BROADWELL(dev))
+		dev_priv->display.get_display_clock_speed =
+			broadwell_get_display_clock_speed;
+	else if (IS_HASWELL(dev))
+		dev_priv->display.get_display_clock_speed =
+			haswell_get_display_clock_speed;
+	else if (IS_VALLEYVIEW(dev))
 		dev_priv->display.get_display_clock_speed =
 			valleyview_get_display_clock_speed;
 	else if (IS_GEN5(dev))
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e38dbd5..047a52e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -717,7 +717,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 	if (intel_dig_port->port == PORT_A) {
 		if (index)
 			return 0;
-		return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
+		return DIV_ROUND_CLOSEST(dev_priv->display.get_display_clock_speed(dev), 2000);
 	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 		/* Workaround for non-ULT HSW */
 		switch (index) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index fca7b9f..4f2ed95 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -856,7 +856,6 @@ void hsw_fdi_link_train(struct drm_crtc *crtc);
 void intel_ddi_init(struct drm_device *dev, enum port port);
 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
-int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 void intel_ddi_pll_init(struct drm_device *dev);
 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fa4ccb3..e1392e7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1792,7 +1792,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
 	linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
 				     mode->crtc_clock);
 	ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
-					 intel_ddi_get_cdclk_freq(dev_priv));
+					 dev_priv->display.get_display_clock_speed(dev_priv->dev));
 
 	return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
 	       PIPE_WM_LINETIME_TIME(linetime);
-- 
1.9.1

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Re: [PATCH 08/19] drm/i915: Convert the ddi cdclk code to get_display_clock_speed

[Damien Lespiau]

On Tue, Mar 31, 2015 at 02:12:01PM +0300, Mika Kahola wrote:
> Unify the HSW/BDW/SKL cdclk extraction code to conform to the same
> .get_display_clock_speed() mold that all the other platforms
> use.
> 
> v2: Update due to SKL code getting added

Having done the same rebase last week, I'm fairly sure there were some
work needed (intel_audio.c didn't exist in the v2 of this patch).
Usually that's enough a v3 comment:

v3: Rebase on top of -nightly (introduction of intel_audio.c) (Mika Kahola)

or something.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_audio.c   |   3 +-
>  drivers/gpu/drm/i915/intel_ddi.c     | 101 +----------------------------------
>  drivers/gpu/drm/i915/intel_display.c |  98 ++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_dp.c      |   2 +-
>  drivers/gpu/drm/i915/intel_drv.h     |   1 -
>  drivers/gpu/drm/i915/intel_pm.c      |   2 +-
>  6 files changed, 102 insertions(+), 105 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 2396cc7..0d5b1ce 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -485,7 +485,8 @@ static int i915_audio_component_get_cdclk_freq(struct device *dev)
>  		return -ENODEV;
>  
>  	intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
> -	ret = intel_ddi_get_cdclk_freq(dev_priv);
> +	ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
> +
>  	intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
>  
>  	return ret;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 47b9307..8c692d8 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1689,105 +1689,6 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
>  	}
>  }
>  
> -static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
> -{
> -	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> -	uint32_t cdctl = I915_READ(CDCLK_CTL);
> -	uint32_t linkrate;
> -
> -	if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
> -		WARN(1, "LCPLL1 not enabled\n");
> -		return 24000; /* 24MHz is the cd freq with NSSC ref */
> -	}
> -
> -	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
> -		return 540000;
> -
> -	linkrate = (I915_READ(DPLL_CTRL1) &
> -		    DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
> -
> -	if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
> -	    linkrate == DPLL_CRTL1_LINK_RATE_1080) {
> -		/* vco 8640 */
> -		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> -		case CDCLK_FREQ_450_432:
> -			return 432000;
> -		case CDCLK_FREQ_337_308:
> -			return 308570;
> -		case CDCLK_FREQ_675_617:
> -			return 617140;
> -		default:
> -			WARN(1, "Unknown cd freq selection\n");
> -		}
> -	} else {
> -		/* vco 8100 */
> -		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> -		case CDCLK_FREQ_450_432:
> -			return 450000;
> -		case CDCLK_FREQ_337_308:
> -			return 337500;
> -		case CDCLK_FREQ_675_617:
> -			return 675000;
> -		default:
> -			WARN(1, "Unknown cd freq selection\n");
> -		}
> -	}
> -
> -	/* error case, do as if DPLL0 isn't enabled */
> -	return 24000;
> -}
> -
> -static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
> -{
> -	uint32_t lcpll = I915_READ(LCPLL_CTL);
> -	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
> -
> -	if (lcpll & LCPLL_CD_SOURCE_FCLK)
> -		return 800000;
> -	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
> -		return 450000;
> -	else if (freq == LCPLL_CLK_FREQ_450)
> -		return 450000;
> -	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
> -		return 540000;
> -	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
> -		return 337500;
> -	else
> -		return 675000;
> -}
> -
> -static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
> -{
> -	struct drm_device *dev = dev_priv->dev;
> -	uint32_t lcpll = I915_READ(LCPLL_CTL);
> -	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
> -
> -	if (lcpll & LCPLL_CD_SOURCE_FCLK)
> -		return 800000;
> -	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
> -		return 450000;
> -	else if (freq == LCPLL_CLK_FREQ_450)
> -		return 450000;
> -	else if (IS_HSW_ULT(dev))
> -		return 337500;
> -	else
> -		return 540000;
> -}
> -
> -int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
> -{
> -	struct drm_device *dev = dev_priv->dev;
> -
> -	if (IS_SKYLAKE(dev))
> -		return skl_get_cdclk_freq(dev_priv);
> -
> -	if (IS_BROADWELL(dev))
> -		return bdw_get_cdclk_freq(dev_priv);
> -
> -	/* Haswell */
> -	return hsw_get_cdclk_freq(dev_priv);
> -}
> -
>  static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  			       struct intel_shared_dpll *pll)
>  {
> @@ -1974,7 +1875,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
>  		hsw_shared_dplls_init(dev_priv);
>  
>  	DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
> -		      intel_ddi_get_cdclk_freq(dev_priv));
> +		      dev_priv->display.get_display_clock_speed(dev));
>  
>  	if (IS_SKYLAKE(dev)) {
>  		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4a4fdb0..6e33258 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5864,6 +5864,93 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>  	return 0;
>  }
>  
> +static int skylake_get_display_clock_speed(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> +	uint32_t cdctl = I915_READ(CDCLK_CTL);
> +	uint32_t linkrate;
> +
> +	if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
> +		WARN(1, "LCPLL1 not enabled\n");
> +		return 24000; /* 24MHz is the cd freq with NSSC ref */
> +	}
> +
> +	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
> +		return 540000;
> +
> +	linkrate = (I915_READ(DPLL_CTRL1) &
> +		    DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
> +
> +	if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
> +	    linkrate == DPLL_CRTL1_LINK_RATE_1080) {
> +		/* vco 8640 */
> +		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> +		case CDCLK_FREQ_450_432:
> +			return 432000;
> +		case CDCLK_FREQ_337_308:
> +			return 308570;
> +		case CDCLK_FREQ_675_617:
> +			return 617140;
> +		default:
> +			WARN(1, "Unknown cd freq selection\n");
> +		}
> +	} else {
> +		/* vco 8100 */
> +		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> +		case CDCLK_FREQ_450_432:
> +			return 450000;
> +		case CDCLK_FREQ_337_308:
> +			return 337500;
> +		case CDCLK_FREQ_675_617:
> +			return 675000;
> +		default:
> +			WARN(1, "Unknown cd freq selection\n");
> +		}
> +	}
> +
> +	/* error case, do as if DPLL0 isn't enabled */
> +	return 24000;
> +}
> +
> +static int broadwell_get_display_clock_speed(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	uint32_t lcpll = I915_READ(LCPLL_CTL);
> +	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
> +
> +	if (lcpll & LCPLL_CD_SOURCE_FCLK)
> +		return 800000;
> +	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
> +		return 450000;
> +	else if (freq == LCPLL_CLK_FREQ_450)
> +		return 450000;
> +	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
> +		return 540000;
> +	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
> +		return 337500;
> +	else
> +		return 675000;
> +}
> +
> +static int haswell_get_display_clock_speed(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	uint32_t lcpll = I915_READ(LCPLL_CTL);
> +	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
> +
> +	if (lcpll & LCPLL_CD_SOURCE_FCLK)
> +		return 800000;
> +	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
> +		return 450000;
> +	else if (freq == LCPLL_CLK_FREQ_450)
> +		return 450000;
> +	else if (IS_HSW_ULT(dev))
> +		return 337500;
> +	else
> +		return 540000;
> +}
> +
>  static int valleyview_get_display_clock_speed(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -13687,7 +13774,16 @@ static void intel_init_display(struct drm_device *dev)
>  	}
>  
>  	/* Returns the core display clock speed */
> -	if (IS_VALLEYVIEW(dev))
> +	if (IS_SKYLAKE(dev))
> +		dev_priv->display.get_display_clock_speed =
> +			skylake_get_display_clock_speed;
> +	else if (IS_BROADWELL(dev))
> +		dev_priv->display.get_display_clock_speed =
> +			broadwell_get_display_clock_speed;
> +	else if (IS_HASWELL(dev))
> +		dev_priv->display.get_display_clock_speed =
> +			haswell_get_display_clock_speed;
> +	else if (IS_VALLEYVIEW(dev))
>  		dev_priv->display.get_display_clock_speed =
>  			valleyview_get_display_clock_speed;
>  	else if (IS_GEN5(dev))
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e38dbd5..047a52e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -717,7 +717,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
>  	if (intel_dig_port->port == PORT_A) {
>  		if (index)
>  			return 0;
> -		return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
> +		return DIV_ROUND_CLOSEST(dev_priv->display.get_display_clock_speed(dev), 2000);
>  	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
>  		/* Workaround for non-ULT HSW */
>  		switch (index) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index fca7b9f..4f2ed95 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -856,7 +856,6 @@ void hsw_fdi_link_train(struct drm_crtc *crtc);
>  void intel_ddi_init(struct drm_device *dev, enum port port);
>  enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
>  bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
> -int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
>  void intel_ddi_pll_init(struct drm_device *dev);
>  void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
>  void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fa4ccb3..e1392e7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1792,7 +1792,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
>  	linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
>  				     mode->crtc_clock);
>  	ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
> -					 intel_ddi_get_cdclk_freq(dev_priv));
> +					 dev_priv->display.get_display_clock_speed(dev_priv->dev));
>  
>  	return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
>  	       PIPE_WM_LINETIME_TIME(linetime);
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 08/19] drm/i915: Convert the ddi cdclk code to get_display_clock_speed

[Daniel Vetter]

On Tue, Mar 31, 2015 at 02:15:56PM +0100, Damien Lespiau wrote:
> On Tue, Mar 31, 2015 at 02:12:01PM +0300, Mika Kahola wrote:
> > Unify the HSW/BDW/SKL cdclk extraction code to conform to the same
> > .get_display_clock_speed() mold that all the other platforms
> > use.
> > 
> > v2: Update due to SKL code getting added
> 
> Having done the same rebase last week, I'm fairly sure there were some
> work needed (intel_audio.c didn't exist in the v2 of this patch).
> Usually that's enough a v3 comment:
> 
> v3: Rebase on top of -nightly (introduction of intel_audio.c) (Mika Kahola)
> 
> or something.

Added and merged all the reviewed patches, thanks.
-Daniel

> 
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_audio.c   |   3 +-
> >  drivers/gpu/drm/i915/intel_ddi.c     | 101 +----------------------------------
> >  drivers/gpu/drm/i915/intel_display.c |  98 ++++++++++++++++++++++++++++++++-
> >  drivers/gpu/drm/i915/intel_dp.c      |   2 +-
> >  drivers/gpu/drm/i915/intel_drv.h     |   1 -
> >  drivers/gpu/drm/i915/intel_pm.c      |   2 +-
> >  6 files changed, 102 insertions(+), 105 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> > index 2396cc7..0d5b1ce 100644
> > --- a/drivers/gpu/drm/i915/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > @@ -485,7 +485,8 @@ static int i915_audio_component_get_cdclk_freq(struct device *dev)
> >  		return -ENODEV;
> >  
> >  	intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
> > -	ret = intel_ddi_get_cdclk_freq(dev_priv);
> > +	ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
> > +
> >  	intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
> >  
> >  	return ret;
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 47b9307..8c692d8 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1689,105 +1689,6 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
> >  	}
> >  }
> >  
> > -static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
> > -{
> > -	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> > -	uint32_t cdctl = I915_READ(CDCLK_CTL);
> > -	uint32_t linkrate;
> > -
> > -	if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
> > -		WARN(1, "LCPLL1 not enabled\n");
> > -		return 24000; /* 24MHz is the cd freq with NSSC ref */
> > -	}
> > -
> > -	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
> > -		return 540000;
> > -
> > -	linkrate = (I915_READ(DPLL_CTRL1) &
> > -		    DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
> > -
> > -	if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
> > -	    linkrate == DPLL_CRTL1_LINK_RATE_1080) {
> > -		/* vco 8640 */
> > -		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> > -		case CDCLK_FREQ_450_432:
> > -			return 432000;
> > -		case CDCLK_FREQ_337_308:
> > -			return 308570;
> > -		case CDCLK_FREQ_675_617:
> > -			return 617140;
> > -		default:
> > -			WARN(1, "Unknown cd freq selection\n");
> > -		}
> > -	} else {
> > -		/* vco 8100 */
> > -		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> > -		case CDCLK_FREQ_450_432:
> > -			return 450000;
> > -		case CDCLK_FREQ_337_308:
> > -			return 337500;
> > -		case CDCLK_FREQ_675_617:
> > -			return 675000;
> > -		default:
> > -			WARN(1, "Unknown cd freq selection\n");
> > -		}
> > -	}
> > -
> > -	/* error case, do as if DPLL0 isn't enabled */
> > -	return 24000;
> > -}
> > -
> > -static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
> > -{
> > -	uint32_t lcpll = I915_READ(LCPLL_CTL);
> > -	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
> > -
> > -	if (lcpll & LCPLL_CD_SOURCE_FCLK)
> > -		return 800000;
> > -	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
> > -		return 450000;
> > -	else if (freq == LCPLL_CLK_FREQ_450)
> > -		return 450000;
> > -	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
> > -		return 540000;
> > -	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
> > -		return 337500;
> > -	else
> > -		return 675000;
> > -}
> > -
> > -static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
> > -{
> > -	struct drm_device *dev = dev_priv->dev;
> > -	uint32_t lcpll = I915_READ(LCPLL_CTL);
> > -	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
> > -
> > -	if (lcpll & LCPLL_CD_SOURCE_FCLK)
> > -		return 800000;
> > -	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
> > -		return 450000;
> > -	else if (freq == LCPLL_CLK_FREQ_450)
> > -		return 450000;
> > -	else if (IS_HSW_ULT(dev))
> > -		return 337500;
> > -	else
> > -		return 540000;
> > -}
> > -
> > -int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
> > -{
> > -	struct drm_device *dev = dev_priv->dev;
> > -
> > -	if (IS_SKYLAKE(dev))
> > -		return skl_get_cdclk_freq(dev_priv);
> > -
> > -	if (IS_BROADWELL(dev))
> > -		return bdw_get_cdclk_freq(dev_priv);
> > -
> > -	/* Haswell */
> > -	return hsw_get_cdclk_freq(dev_priv);
> > -}
> > -
> >  static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
> >  			       struct intel_shared_dpll *pll)
> >  {
> > @@ -1974,7 +1875,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
> >  		hsw_shared_dplls_init(dev_priv);
> >  
> >  	DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
> > -		      intel_ddi_get_cdclk_freq(dev_priv));
> > +		      dev_priv->display.get_display_clock_speed(dev));
> >  
> >  	if (IS_SKYLAKE(dev)) {
> >  		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 4a4fdb0..6e33258 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5864,6 +5864,93 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> >  	return 0;
> >  }
> >  
> > +static int skylake_get_display_clock_speed(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> > +	uint32_t cdctl = I915_READ(CDCLK_CTL);
> > +	uint32_t linkrate;
> > +
> > +	if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
> > +		WARN(1, "LCPLL1 not enabled\n");
> > +		return 24000; /* 24MHz is the cd freq with NSSC ref */
> > +	}
> > +
> > +	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
> > +		return 540000;
> > +
> > +	linkrate = (I915_READ(DPLL_CTRL1) &
> > +		    DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
> > +
> > +	if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
> > +	    linkrate == DPLL_CRTL1_LINK_RATE_1080) {
> > +		/* vco 8640 */
> > +		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> > +		case CDCLK_FREQ_450_432:
> > +			return 432000;
> > +		case CDCLK_FREQ_337_308:
> > +			return 308570;
> > +		case CDCLK_FREQ_675_617:
> > +			return 617140;
> > +		default:
> > +			WARN(1, "Unknown cd freq selection\n");
> > +		}
> > +	} else {
> > +		/* vco 8100 */
> > +		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> > +		case CDCLK_FREQ_450_432:
> > +			return 450000;
> > +		case CDCLK_FREQ_337_308:
> > +			return 337500;
> > +		case CDCLK_FREQ_675_617:
> > +			return 675000;
> > +		default:
> > +			WARN(1, "Unknown cd freq selection\n");
> > +		}
> > +	}
> > +
> > +	/* error case, do as if DPLL0 isn't enabled */
> > +	return 24000;
> > +}
> > +
> > +static int broadwell_get_display_clock_speed(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	uint32_t lcpll = I915_READ(LCPLL_CTL);
> > +	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
> > +
> > +	if (lcpll & LCPLL_CD_SOURCE_FCLK)
> > +		return 800000;
> > +	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
> > +		return 450000;
> > +	else if (freq == LCPLL_CLK_FREQ_450)
> > +		return 450000;
> > +	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
> > +		return 540000;
> > +	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
> > +		return 337500;
> > +	else
> > +		return 675000;
> > +}
> > +
> > +static int haswell_get_display_clock_speed(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	uint32_t lcpll = I915_READ(LCPLL_CTL);
> > +	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
> > +
> > +	if (lcpll & LCPLL_CD_SOURCE_FCLK)
> > +		return 800000;
> > +	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
> > +		return 450000;
> > +	else if (freq == LCPLL_CLK_FREQ_450)
> > +		return 450000;
> > +	else if (IS_HSW_ULT(dev))
> > +		return 337500;
> > +	else
> > +		return 540000;
> > +}
> > +
> >  static int valleyview_get_display_clock_speed(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -13687,7 +13774,16 @@ static void intel_init_display(struct drm_device *dev)
> >  	}
> >  
> >  	/* Returns the core display clock speed */
> > -	if (IS_VALLEYVIEW(dev))
> > +	if (IS_SKYLAKE(dev))
> > +		dev_priv->display.get_display_clock_speed =
> > +			skylake_get_display_clock_speed;
> > +	else if (IS_BROADWELL(dev))
> > +		dev_priv->display.get_display_clock_speed =
> > +			broadwell_get_display_clock_speed;
> > +	else if (IS_HASWELL(dev))
> > +		dev_priv->display.get_display_clock_speed =
> > +			haswell_get_display_clock_speed;
> > +	else if (IS_VALLEYVIEW(dev))
> >  		dev_priv->display.get_display_clock_speed =
> >  			valleyview_get_display_clock_speed;
> >  	else if (IS_GEN5(dev))
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index e38dbd5..047a52e 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -717,7 +717,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> >  	if (intel_dig_port->port == PORT_A) {
> >  		if (index)
> >  			return 0;
> > -		return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
> > +		return DIV_ROUND_CLOSEST(dev_priv->display.get_display_clock_speed(dev), 2000);
> >  	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> >  		/* Workaround for non-ULT HSW */
> >  		switch (index) {
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index fca7b9f..4f2ed95 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -856,7 +856,6 @@ void hsw_fdi_link_train(struct drm_crtc *crtc);
> >  void intel_ddi_init(struct drm_device *dev, enum port port);
> >  enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
> >  bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
> > -int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
> >  void intel_ddi_pll_init(struct drm_device *dev);
> >  void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
> >  void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index fa4ccb3..e1392e7 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -1792,7 +1792,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
> >  	linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
> >  				     mode->crtc_clock);
> >  	ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
> > -					 intel_ddi_get_cdclk_freq(dev_priv));
> > +					 dev_priv->display.get_display_clock_speed(dev_priv->dev));
> >  
> >  	return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
> >  	       PIPE_WM_LINETIME_TIME(linetime);
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH 10/19] drm/i915: Cache current cdclk frequency in dev_priv

[Mika Kahola]

Rather that extracting the current cdclk freuqncy every time someone
wants to know it, cache the current value and use that. VLV/CHV already
stored a cached value there so just expand that to cover all platforms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 42 +++++++++++++++++++++++-------------
 2 files changed, 28 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4ef320c..38279f6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1660,7 +1660,7 @@ struct drm_i915_private {
 	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
 	unsigned int fsb_freq, mem_freq, is_ddr3;
-	unsigned int vlv_cdclk_freq;
+	unsigned int cdclk_freq;
 	unsigned int hpll_freq;
 
 	/**
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d436171..9e6c289 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5008,20 +5008,28 @@ static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 	return vco_freq[hpll_freq] * 1000;
 }
 
-static void vlv_update_cdclk(struct drm_device *dev)
+static void intel_update_cdclk(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
+	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
 	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
-			 dev_priv->vlv_cdclk_freq);
+			 dev_priv->cdclk_freq);
 
 	/*
 	 * Program the gmbus_freq based on the cdclk frequency.
 	 * BSpec erroneously claims we should aim for 4MHz, but
 	 * in fact 1MHz is the correct frequency.
 	 */
-	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
+	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
+	if (IS_VALLEYVIEW(dev)) {
+		/*
+		 * Program the gmbus_freq based on the cdclk frequency.
+		 * BSpec erroneously claims we should aim for 4MHz, but
+		 * in fact 1MHz is the correct frequency.
+		 */
+		I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
+	}
 }
 
 /* Adjust CDclk dividers to allow high res or save power if possible */
@@ -5030,7 +5038,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 val, cmd;
 
-	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
+	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->cdclk_freq);
 
 	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 		cmd = 2;
@@ -5086,7 +5094,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
 	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 	mutex_unlock(&dev_priv->dpio_lock);
 
-	vlv_update_cdclk(dev);
+	intel_update_cdclk(dev);
 }
 
 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
@@ -5094,7 +5102,7 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 val, cmd;
 
-	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
+	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->cdclk_freq);
 
 	switch (cdclk) {
 	case 333333:
@@ -5126,7 +5134,7 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
 	}
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
-	vlv_update_cdclk(dev);
+	intel_update_cdclk(dev);
 }
 
 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
@@ -5182,8 +5190,7 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
 	struct intel_crtc *intel_crtc;
 	int max_pixclk = intel_mode_max_pixclk(dev_priv);
 
-	if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
-	    dev_priv->vlv_cdclk_freq)
+	if (valleyview_calc_cdclk(dev_priv, max_pixclk) == dev_priv->cdclk_freq)
 		return;
 
 	/* disable/enable all currently active pipes while we change cdclk */
@@ -5201,7 +5208,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 	else
 		default_credits = PFI_CREDIT(8);
 
-	if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
+	if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
 		/* CHV suggested value is 31 or 63 */
 		if (IS_CHERRYVIEW(dev_priv))
 			credits = PFI_CREDIT_31;
@@ -5235,7 +5242,7 @@ static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
 	int max_pixclk = intel_mode_max_pixclk(dev_priv);
 	int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
 
-	if (req_cdclk != dev_priv->vlv_cdclk_freq) {
+	if (req_cdclk != dev_priv->cdclk_freq) {
 		/*
 		 * FIXME: We can end up here with all power domains off, yet
 		 * with a CDCLK frequency other than the minimum. To account
@@ -8625,6 +8632,8 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
 		I915_WRITE(LCPLL_CTL, val);
 		POSTING_READ(LCPLL_CTL);
 	}
+
+	intel_update_cdclk(dev_priv->dev);
 }
 
 /*
@@ -8676,6 +8685,8 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
 	}
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+	intel_update_cdclk(dev_priv->dev);
 }
 
 /*
@@ -12592,6 +12603,8 @@ static void intel_shared_dpll_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
+	intel_update_cdclk(dev);
+
 	if (HAS_DDI(dev))
 		intel_ddi_pll_init(dev);
 	else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
@@ -14059,10 +14072,9 @@ static void i915_disable_vga(struct drm_device *dev)
 
 void intel_modeset_init_hw(struct drm_device *dev)
 {
-	intel_prepare_ddi(dev);
+	intel_update_cdclk(dev);
 
-	if (IS_VALLEYVIEW(dev))
-		vlv_update_cdclk(dev);
+	intel_prepare_ddi(dev);
 
 	intel_init_clock_gating(dev);
 
-- 
1.9.1

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[PATCH 11/19] drm/i915: Use cached cdclk value

[Mika Kahola]

Rather than reading out the current cdclk value use the cached value we
have tucked away in dev_priv.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 +--
 drivers/gpu/drm/i915/intel_dp.c      | 5 +++--
 drivers/gpu/drm/i915/intel_pm.c      | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9e6c289..2ca3709 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5817,8 +5817,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 
 	/* FIXME should check pixel clock limits on all platforms */
 	if (INTEL_INFO(dev)->gen < 4) {
-		int clock_limit =
-			dev_priv->display.get_display_clock_speed(dev);
+		int clock_limit = dev_priv->cdclk_freq;
 
 		/*
 		 * Enable pixel doubling when the dot clock
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 047a52e..cab282f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -702,7 +702,8 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 		return 0;
 
 	if (intel_dig_port->port == PORT_A) {
-		return DIV_ROUND_UP(dev_priv->display.get_display_clock_speed(dev), 2000);
+		return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);
+
 	} else {
 		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 	}
@@ -717,7 +718,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 	if (intel_dig_port->port == PORT_A) {
 		if (index)
 			return 0;
-		return DIV_ROUND_CLOSEST(dev_priv->display.get_display_clock_speed(dev), 2000);
+		return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 		/* Workaround for non-ULT HSW */
 		switch (index) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e1392e7..45431f4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1792,7 +1792,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
 	linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
 				     mode->crtc_clock);
 	ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
-					 dev_priv->display.get_display_clock_speed(dev_priv->dev));
+					 dev_priv->cdclk_freq);
 
 	return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
 	       PIPE_WM_LINETIME_TIME(linetime);
-- 
1.9.1

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[PATCH 12/19] drm/i915: Unify ilk and hsw .get_aux_clock_divider

[Mika Kahola]

ilk_get_aux_clock_divider() is now a subset of
hsw_get_aux_clock_divider() so unify them.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 23 +++--------------------
 1 file changed, 3 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cab282f..45b976b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -698,23 +698,6 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (index)
-		return 0;
-
-	if (intel_dig_port->port == PORT_A) {
-		return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);
-
-	} else {
-		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
-	}
-}
-
-static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
-	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = intel_dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
 	if (intel_dig_port->port == PORT_A) {
 		if (index)
 			return 0;
@@ -727,7 +710,9 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 		default: return 0;
 		}
 	} else  {
-		return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
+		if (index)
+			return 0;
+		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 	}
 }
 
@@ -5450,8 +5435,6 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
 	else if (IS_VALLEYVIEW(dev))
 		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
-	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
-		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
 	else if (HAS_PCH_SPLIT(dev))
 		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
 	else
-- 
1.9.1

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[PATCH 13/19] drm/i915: Store max cdclk value in dev_priv

[Mika Kahola]

Keep the cdclk maximum supported frequency around in dev_priv so that we
can verify certain things against it before actually changing the cdclk
frequency.

For now only VLV/CHV have support changing cdclk frequency, so other
plarforms get to assume cdclk is fixed.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++++++-
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 38279f6..39b6042 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1660,7 +1660,7 @@ struct drm_i915_private {
 	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
 	unsigned int fsb_freq, mem_freq, is_ddr3;
-	unsigned int cdclk_freq;
+	unsigned int cdclk_freq, max_cdclk_freq;
 	unsigned int hpll_freq;
 
 	/**
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2ca3709..b16fa47 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5008,6 +5008,21 @@ static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 	return vco_freq[hpll_freq] * 1000;
 }
 
+static void intel_update_max_cdclk(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	if (IS_VALLEYVIEW(dev)) {
+		dev_priv->max_cdclk_freq = 400000;
+	} else {
+		/* otherwise assume cdclk is fixed */
+		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
+	}
+
+	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
+			 dev_priv->max_cdclk_freq);
+}
+
 static void intel_update_cdclk(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5030,6 +5045,9 @@ static void intel_update_cdclk(struct drm_device *dev)
 		 */
 		I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
 	}
+
+	if (dev_priv->max_cdclk_freq == 0)
+		intel_update_max_cdclk(dev);
 }
 
 /* Adjust CDclk dividers to allow high res or save power if possible */
@@ -5817,7 +5835,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 
 	/* FIXME should check pixel clock limits on all platforms */
 	if (INTEL_INFO(dev)->gen < 4) {
-		int clock_limit = dev_priv->cdclk_freq;
+		int clock_limit = dev_priv->max_cdclk_freq;
 
 		/*
 		 * Enable pixel doubling when the dot clock
-- 
1.9.1

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[PATCH 14/19] drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk

[Mika Kahola]

Bspec says we shouldn't enable IPS on BDW when the pipe pixel rate
exceeds 95% of the core display clock. Apparently this can cause
underruns.

There's no similar restriction listed for HSW, so leave that one alone
for now.

v2: Add pipe_config_supports_ips() (Chris)
v3: Compare against the max cdclk insted of the current cdclk

Tested-by: Timo Aaltonen <tjaalton@ubuntu.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83497
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 drivers/gpu/drm/i915/intel_pm.c      | 17 ++++++++---------
 3 files changed, 38 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b16fa47..3752d5e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5818,12 +5818,39 @@ retry:
 	return ret;
 }
 
+static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
+				     struct intel_crtc_state *pipe_config)
+{
+	if (pipe_config->pipe_bpp > 24)
+		return false;
+
+	/* HSW can handle pixel rate up to cdclk? */
+	if (IS_HASWELL(dev_priv->dev))
+		return true;
+
+	/*
+	 * FIXME if we compare against max we should then
+	 * increase the cdclk frequency when the current
+	 * value is too low. The other option is to compare
+	 * against the cdclk frequency we're going have post
+	 * modeset (ie. one we computed using other constraints).
+	 * Need to measure whether using a lower cdclk w/o IPS
+	 * is better or worse than a higher cdclk w/ IPS.
+	 */
+	return ilk_pipe_pixel_rate(pipe_config) <=
+		dev_priv->max_cdclk_freq * 95 / 100;
+}
+
 static void hsw_compute_ips_config(struct intel_crtc *crtc,
 				   struct intel_crtc_state *pipe_config)
 {
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
 	pipe_config->ips_enabled = i915.enable_ips &&
-				   hsw_crtc_supports_ips(crtc) &&
-				   pipe_config->pipe_bpp <= 24;
+		hsw_crtc_supports_ips(crtc) &&
+		pipe_config_supports_ips(dev_priv, pipe_config);
+
 }
 
 static int intel_crtc_compute_config(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4f2ed95..1bdbceb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1270,6 +1270,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev);
 void skl_wm_get_hw_state(struct drm_device *dev);
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 			  struct skl_ddb_allocation *ddb /* out */);
+uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
 
 
 /* intel_sdvo.c */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 45431f4..281d645 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1411,23 +1411,22 @@ static void i845_update_wm(struct drm_crtc *unused_crtc)
 	I915_WRITE(FW_BLC, fwater_lo);
 }
 
-static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
-				    struct drm_crtc *crtc)
+uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
 {
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	uint32_t pixel_rate;
 
-	pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
+	pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
 
 	/* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
 	 * adjust the pixel_rate here. */
 
-	if (intel_crtc->config->pch_pfit.enabled) {
+	if (pipe_config->pch_pfit.enabled) {
 		uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
-		uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
+		uint32_t pfit_size = pipe_config->pch_pfit.size;
+
+		pipe_w = pipe_config->pipe_src_w;
+		pipe_h = pipe_config->pipe_src_h;
 
-		pipe_w = intel_crtc->config->pipe_src_w;
-		pipe_h = intel_crtc->config->pipe_src_h;
 		pfit_w = (pfit_size >> 16) & 0xFFFF;
 		pfit_h = pfit_size & 0xFFFF;
 		if (pipe_w < pfit_w)
@@ -2043,7 +2042,7 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
 
 	p->active = true;
 	p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
-	p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
+	p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
 
 	if (crtc->primary->state->fb) {
 		p->pri.enabled = true;
-- 
1.9.1

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[PATCH 15/19] drm/i915: HSW cdclk support

[Mika Kahola]

Implement support for changing the cdclk frequency during runtime on
HSW. VLV/CHV already have support for this, so we can follow their
example for the most part. Only the actual hardware programming differs,
the rest is pretty much the same.

The pipe pixel rate stuff is handled a bit differently for now due to
the difference in pch vs. gmch pfit handling. Eventually we should unify
that part to eliminate what is essentially duplicated code.

v2: Grab rps.hw_lock around sandybridge_pcode_write()
v3: Rebase due to power well vs. .global_resources() reordering
v4: Rebase due to .global_resources() reordering for Haswell

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |   3 +
 drivers/gpu/drm/i915/intel_display.c | 161 ++++++++++++++++++++++++++++++++++-
 2 files changed, 161 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f26ebd2..b25f712 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6244,6 +6244,7 @@ enum skl_disp_power_wells {
 #define   GEN6_PCODE_WRITE_D_COMP		0x11
 #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
 #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
+#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
 #define   DISPLAY_IPS_CONTROL			0x19
 #define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
 #define GEN6_PCODE_DATA				0x138128
@@ -6698,10 +6699,12 @@ enum skl_disp_power_wells {
 #define  LCPLL_PLL_LOCK			(1<<30)
 #define  LCPLL_CLK_FREQ_MASK		(3<<26)
 #define  LCPLL_CLK_FREQ_450		(0<<26)
+#define  LCPLL_CLK_FREQ_ALT_HSW		(1<<26) /* 337.5 (ULX) or 540 */
 #define  LCPLL_CLK_FREQ_54O_BDW		(1<<26)
 #define  LCPLL_CLK_FREQ_337_5_BDW	(2<<26)
 #define  LCPLL_CLK_FREQ_675_BDW		(3<<26)
 #define  LCPLL_CD_CLOCK_DISABLE		(1<<25)
+#define  LCPLL_ROOT_CD_CLOCK_DISABLE	(1<<24)
 #define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
 #define  LCPLL_POWER_DOWN_ALLOW		(1<<22)
 #define  LCPLL_CD_SOURCE_FCLK		(1<<21)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3752d5e..cce7103 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5012,7 +5012,16 @@ static void intel_update_max_cdclk(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_HASWELL(dev)) {
+		if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
+			dev_priv->max_cdclk_freq = 450000;
+		else if (IS_HSW_ULX(dev))
+			dev_priv->max_cdclk_freq = 337500;
+		else if (IS_HSW_ULT(dev))
+			dev_priv->max_cdclk_freq = 450000;
+		else
+			dev_priv->max_cdclk_freq = 540000;
+	} else if (IS_VALLEYVIEW(dev)) {
 		dev_priv->max_cdclk_freq = 400000;
 	} else {
 		/* otherwise assume cdclk is fixed */
@@ -8773,6 +8782,144 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv)
 	hsw_disable_lcpll(dev_priv, true, true);
 }
 
+/* compute the max rate for new configuration */
+static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+	struct intel_crtc *crtc;
+	int max_pixel_rate = 0;
+
+	for_each_intel_crtc(dev, crtc) {
+		if (crtc->new_enabled)
+			max_pixel_rate = max(max_pixel_rate,
+					     ilk_pipe_pixel_rate(crtc->new_config));
+	}
+
+	return max_pixel_rate;
+}
+
+static int haswell_calc_cdclk(struct drm_i915_private *dev_priv,
+			      int max_pixel_rate)
+{
+	int cdclk;
+
+	/*
+	 * FIXME should also account for plane ratio
+	 * once 64bpp pixel formats are supported.
+	 */
+	if (max_pixel_rate > 450000)
+		cdclk = 540000;
+	else if (max_pixel_rate > 337500 || !IS_HSW_ULX(dev_priv))
+		cdclk = 450000;
+	else
+		cdclk = 337500;
+
+	/*
+	 * FIXME move the cdclk caclulation to
+	 * compute_config() so we can fail gracegully.
+	 */
+	if (cdclk > dev_priv->max_cdclk_freq) {
+		DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
+			  cdclk, dev_priv->max_cdclk_freq);
+		cdclk = dev_priv->max_cdclk_freq;
+	}
+
+	return cdclk;
+}
+
+static void haswell_set_cdclk(struct drm_device *dev, int cdclk)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t val;
+
+	if (WARN((I915_READ(LCPLL_CTL) &
+		  (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
+		   LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
+		   LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
+		   LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
+		 "trying to change cdclk frequency with cdclk not enabled\n"))
+		return;
+
+	val = I915_READ(LCPLL_CTL);
+	val &= ~LCPLL_CLK_FREQ_MASK;
+
+	switch (cdclk) {
+	case 450000:
+		val |= LCPLL_CLK_FREQ_450;
+		break;
+	case 337500:
+	case 540000:
+		val |= LCPLL_CLK_FREQ_ALT_HSW;
+		break;
+	default:
+		WARN(1, "invalid cdclk frequency\n");
+		return;
+	}
+
+	I915_WRITE(LCPLL_CTL, val);
+
+	if (IS_HSW_ULX(dev)) {
+		mutex_lock(&dev_priv->rps.hw_lock);
+		sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
+					cdclk == 337500);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+	}
+
+	intel_update_cdclk(dev);
+
+	WARN(cdclk != dev_priv->cdclk_freq,
+	     "cdclk requested %d kHz but got %d kHz\n",
+	     cdclk, dev_priv->cdclk_freq);
+}
+
+static void haswell_modeset_global_pipes(struct drm_device *dev,
+					 unsigned *prepare_pipes)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *crtc;
+	int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
+
+	if (haswell_calc_cdclk(dev_priv, max_pixel_rate) ==
+	    dev_priv->cdclk_freq)
+		return;
+
+	/* disable/enable all currently active pipes while we change cdclk */
+	for_each_intel_crtc(dev, crtc)
+		if (crtc->base.enabled)
+			*prepare_pipes |= 1 << crtc->pipe;
+}
+
+static void haswell_modeset_global_resources(struct drm_atomic_state *state)
+{
+	struct drm_device *dev = state->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
+	int req_cdclk = haswell_calc_cdclk(dev_priv, max_pixel_rate);
+
+	if (req_cdclk != dev_priv->cdclk_freq)
+		haswell_set_cdclk(dev, req_cdclk);
+
+	if (req_cdclk != dev_priv->cdclk_freq) {
+		/*
+		 * FIXME: We can end up here with all power domains off, yet
+		 * with a CDCLK frequency other than the minimum. To account
+		 * for this take the PIPE-A power domain, which covers the HW
+		 * blocks needed for the following programming. This can be
+		 * removed once it's guaranteed that we get here either with
+		 * the minimum CDCLK set, or the required power domains
+		 * enabled.
+		 */
+		intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
+
+		haswell_set_cdclk(dev, req_cdclk);
+
+		vlv_program_pfi_credits(dev_priv);
+
+		intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
+	}
+
+}
+
 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
 {
 	struct drm_device *dev = dev_priv->dev;
@@ -8792,6 +8939,8 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
 	intel_prepare_ddi(dev);
 }
 
+
+
 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
 				      struct intel_crtc_state *crtc_state)
 {
@@ -11866,8 +12015,11 @@ static int __intel_set_mode(struct drm_crtc *crtc,
 	 * mode set on this crtc.  For other crtcs we need to use the
 	 * adjusted_mode bits in the crtc directly.
 	 */
-	if (IS_VALLEYVIEW(dev)) {
-		valleyview_modeset_global_pipes(dev, &prepare_pipes);
+	if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev)) {
+		if (IS_VALLEYVIEW(dev))
+			valleyview_modeset_global_pipes(dev, &prepare_pipes);
+		else
+			haswell_modeset_global_pipes(dev, &prepare_pipes);
 
 		/* may have added more to prepare_pipes than we should */
 		prepare_pipes &= ~disable_pipes;
@@ -13892,6 +14044,9 @@ static void intel_init_display(struct drm_device *dev)
 		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
 	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
+		if (IS_HASWELL(dev))
+			dev_priv->display.modeset_global_resources =
+				haswell_modeset_global_resources;
 	} else if (IS_VALLEYVIEW(dev)) {
 		dev_priv->display.modeset_global_resources =
 			valleyview_modeset_global_resources;
-- 
1.9.1

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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Sivakumar Thulasimani]

On 3/31/2015 4:44 PM, Mika Kahola wrote:
> Implement support for changing the cdclk frequency during runtime on
> HSW. VLV/CHV already have support for this, so we can follow their
> example for the most part. Only the actual hardware programming differs,
> the rest is pretty much the same.
>
> The pipe pixel rate stuff is handled a bit differently for now due to
> the difference in pch vs. gmch pfit handling. Eventually we should unify
> that part to eliminate what is essentially duplicated code.
>
> v2: Grab rps.hw_lock around sandybridge_pcode_write()
> v3: Rebase due to power well vs. .global_resources() reordering
> v4: Rebase due to .global_resources() reordering for Haswell
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h      |   3 +
>   drivers/gpu/drm/i915/intel_display.c | 161 ++++++++++++++++++++++++++++++++++-
>   2 files changed, 161 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f26ebd2..b25f712 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6244,6 +6244,7 @@ enum skl_disp_power_wells {
>   #define   GEN6_PCODE_WRITE_D_COMP		0x11
>   #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
>   #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
> +#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
>   #define   DISPLAY_IPS_CONTROL			0x19
>   #define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
>   #define GEN6_PCODE_DATA				0x138128
> @@ -6698,10 +6699,12 @@ enum skl_disp_power_wells {
>   #define  LCPLL_PLL_LOCK			(1<<30)
>   #define  LCPLL_CLK_FREQ_MASK		(3<<26)
>   #define  LCPLL_CLK_FREQ_450		(0<<26)
> +#define  LCPLL_CLK_FREQ_ALT_HSW		(1<<26) /* 337.5 (ULX) or 540 */
>   #define  LCPLL_CLK_FREQ_54O_BDW		(1<<26)
>   #define  LCPLL_CLK_FREQ_337_5_BDW	(2<<26)
>   #define  LCPLL_CLK_FREQ_675_BDW		(3<<26)
>   #define  LCPLL_CD_CLOCK_DISABLE		(1<<25)
> +#define  LCPLL_ROOT_CD_CLOCK_DISABLE	(1<<24)
>   #define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
>   #define  LCPLL_POWER_DOWN_ALLOW		(1<<22)
>   #define  LCPLL_CD_SOURCE_FCLK		(1<<21)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3752d5e..cce7103 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5012,7 +5012,16 @@ static void intel_update_max_cdclk(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
>   
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_HASWELL(dev)) {
> +		if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
> +			dev_priv->max_cdclk_freq = 450000;
> +		else if (IS_HSW_ULX(dev))
> +			dev_priv->max_cdclk_freq = 337500;
> +		else if (IS_HSW_ULT(dev))
> +			dev_priv->max_cdclk_freq = 450000;
> +		else
> +			dev_priv->max_cdclk_freq = 540000;
> +	} else if (IS_VALLEYVIEW(dev)) {
>   		dev_priv->max_cdclk_freq = 400000;
>   	} else {
>   		/* otherwise assume cdclk is fixed */
> @@ -8773,6 +8782,144 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv)
>   	hsw_disable_lcpll(dev_priv, true, true);
>   }
>   
> +/* compute the max rate for new configuration */
> +static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
> +{
> +	struct drm_device *dev = dev_priv->dev;
> +	struct intel_crtc *crtc;
> +	int max_pixel_rate = 0;
> +
> +	for_each_intel_crtc(dev, crtc) {
> +		if (crtc->new_enabled)
> +			max_pixel_rate = max(max_pixel_rate,
> +					     ilk_pipe_pixel_rate(crtc->new_config));
> +	}
> +
> +	return max_pixel_rate;
> +}
> +
> +static int haswell_calc_cdclk(struct drm_i915_private *dev_priv,
> +			      int max_pixel_rate)
> +{
> +	int cdclk;
> +
> +	/*
> +	 * FIXME should also account for plane ratio
> +	 * once 64bpp pixel formats are supported.
> +	 */
> +	if (max_pixel_rate > 450000)
> +		cdclk = 540000;
> +	else if (max_pixel_rate > 337500 || !IS_HSW_ULX(dev_priv))
> +		cdclk = 450000;
> +	else
> +		cdclk = 337500;
> +
> +	/*
> +	 * FIXME move the cdclk caclulation to
> +	 * compute_config() so we can fail gracegully.
> +	 */
> +	if (cdclk > dev_priv->max_cdclk_freq) {
> +		DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> +			  cdclk, dev_priv->max_cdclk_freq);
> +		cdclk = dev_priv->max_cdclk_freq;
> +	}
> +
> +	return cdclk;
> +}
won't this return 337MHz even for platforms that have HSW_CDCLK_LIMIT is 
set ? this should return 450MHz if this fuse is set

> +
> +static void haswell_set_cdclk(struct drm_device *dev, int cdclk)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	uint32_t val;
> +
> +	if (WARN((I915_READ(LCPLL_CTL) &
> +		  (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
> +		   LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
> +		   LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
> +		   LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
> +		 "trying to change cdclk frequency with cdclk not enabled\n"))
> +		return;
> +
> +	val = I915_READ(LCPLL_CTL);
> +	val &= ~LCPLL_CLK_FREQ_MASK;
> +
> +	switch (cdclk) {
> +	case 450000:
> +		val |= LCPLL_CLK_FREQ_450;
> +		break;
> +	case 337500:
> +	case 540000:
> +		val |= LCPLL_CLK_FREQ_ALT_HSW;
> +		break;
> +	default:
> +		WARN(1, "invalid cdclk frequency\n");
> +		return;
> +	}
> +
> +	I915_WRITE(LCPLL_CTL, val);
> +
> +	if (IS_HSW_ULX(dev)) {
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
> +					cdclk == 337500);
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +	}
> +
> +	intel_update_cdclk(dev);
> +
> +	WARN(cdclk != dev_priv->cdclk_freq,
> +	     "cdclk requested %d kHz but got %d kHz\n",
> +	     cdclk, dev_priv->cdclk_freq);
> +}
> +
> +static void haswell_modeset_global_pipes(struct drm_device *dev,
> +					 unsigned *prepare_pipes)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *crtc;
> +	int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
> +
> +	if (haswell_calc_cdclk(dev_priv, max_pixel_rate) ==
> +	    dev_priv->cdclk_freq)
> +		return;
> +
> +	/* disable/enable all currently active pipes while we change cdclk */
> +	for_each_intel_crtc(dev, crtc)
> +		if (crtc->base.enabled)
> +			*prepare_pipes |= 1 << crtc->pipe;
> +}
> +
> +static void haswell_modeset_global_resources(struct drm_atomic_state *state)
> +{
> +	struct drm_device *dev = state->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
> +	int req_cdclk = haswell_calc_cdclk(dev_priv, max_pixel_rate);
> +
> +	if (req_cdclk != dev_priv->cdclk_freq)
> +		haswell_set_cdclk(dev, req_cdclk);
> +
> +	if (req_cdclk != dev_priv->cdclk_freq) {
> +		/*
> +		 * FIXME: We can end up here with all power domains off, yet
> +		 * with a CDCLK frequency other than the minimum. To account
> +		 * for this take the PIPE-A power domain, which covers the HW
> +		 * blocks needed for the following programming. This can be
> +		 * removed once it's guaranteed that we get here either with
> +		 * the minimum CDCLK set, or the required power domains
> +		 * enabled.
> +		 */
> +		intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
> +
> +		haswell_set_cdclk(dev, req_cdclk);
> +
> +		vlv_program_pfi_credits(dev_priv);
> +
> +		intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
> +	}
> +
> +}
> +
>   void hsw_disable_pc8(struct drm_i915_private *dev_priv)
>   {
>   	struct drm_device *dev = dev_priv->dev;
> @@ -8792,6 +8939,8 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
>   	intel_prepare_ddi(dev);
>   }
>   
> +
> +
>   static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>   				      struct intel_crtc_state *crtc_state)
>   {
> @@ -11866,8 +12015,11 @@ static int __intel_set_mode(struct drm_crtc *crtc,
>   	 * mode set on this crtc.  For other crtcs we need to use the
>   	 * adjusted_mode bits in the crtc directly.
>   	 */
> -	if (IS_VALLEYVIEW(dev)) {
> -		valleyview_modeset_global_pipes(dev, &prepare_pipes);
> +	if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev)) {
> +		if (IS_VALLEYVIEW(dev))
> +			valleyview_modeset_global_pipes(dev, &prepare_pipes);
> +		else
> +			haswell_modeset_global_pipes(dev, &prepare_pipes);
>   
>   		/* may have added more to prepare_pipes than we should */
>   		prepare_pipes &= ~disable_pipes;
> @@ -13892,6 +14044,9 @@ static void intel_init_display(struct drm_device *dev)
>   		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
>   	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
>   		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
> +		if (IS_HASWELL(dev))
> +			dev_priv->display.modeset_global_resources =
> +				haswell_modeset_global_resources;
>   	} else if (IS_VALLEYVIEW(dev)) {
>   		dev_priv->display.modeset_global_resources =
>   			valleyview_modeset_global_resources;

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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Sivakumar Thulasimani]

sorry if i am missing something, HSW and BDW requires display audio 
controller to be updated with new values once CD clock is modified. how 
is this accomplished here ?

regards,
Sivakumar
On 4/7/2015 11:57 AM, Sivakumar Thulasimani wrote:
>
>
> On 3/31/2015 4:44 PM, Mika Kahola wrote:
>> Implement support for changing the cdclk frequency during runtime on
>> HSW. VLV/CHV already have support for this, so we can follow their
>> example for the most part. Only the actual hardware programming differs,
>> the rest is pretty much the same.
>>
>> The pipe pixel rate stuff is handled a bit differently for now due to
>> the difference in pch vs. gmch pfit handling. Eventually we should unify
>> that part to eliminate what is essentially duplicated code.
>>
>> v2: Grab rps.hw_lock around sandybridge_pcode_write()
>> v3: Rebase due to power well vs. .global_resources() reordering
>> v4: Rebase due to .global_resources() reordering for Haswell
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h      |   3 +
>>   drivers/gpu/drm/i915/intel_display.c | 161 
>> ++++++++++++++++++++++++++++++++++-
>>   2 files changed, 161 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index f26ebd2..b25f712 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6244,6 +6244,7 @@ enum skl_disp_power_wells {
>>   #define   GEN6_PCODE_WRITE_D_COMP        0x11
>>   #define   GEN6_ENCODE_RC6_VID(mv)        (((mv) - 245) / 5)
>>   #define   GEN6_DECODE_RC6_VID(vids)        (((vids) * 5) + 245)
>> +#define   HSW_PCODE_DE_WRITE_FREQ_REQ        0x17
>>   #define   DISPLAY_IPS_CONTROL            0x19
>>   #define      HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL    0x1A
>>   #define GEN6_PCODE_DATA                0x138128
>> @@ -6698,10 +6699,12 @@ enum skl_disp_power_wells {
>>   #define  LCPLL_PLL_LOCK            (1<<30)
>>   #define  LCPLL_CLK_FREQ_MASK        (3<<26)
>>   #define  LCPLL_CLK_FREQ_450        (0<<26)
>> +#define  LCPLL_CLK_FREQ_ALT_HSW        (1<<26) /* 337.5 (ULX) or 540 */
>>   #define  LCPLL_CLK_FREQ_54O_BDW        (1<<26)
>>   #define  LCPLL_CLK_FREQ_337_5_BDW    (2<<26)
>>   #define  LCPLL_CLK_FREQ_675_BDW        (3<<26)
>>   #define  LCPLL_CD_CLOCK_DISABLE        (1<<25)
>> +#define  LCPLL_ROOT_CD_CLOCK_DISABLE    (1<<24)
>>   #define  LCPLL_CD2X_CLOCK_DISABLE    (1<<23)
>>   #define  LCPLL_POWER_DOWN_ALLOW        (1<<22)
>>   #define  LCPLL_CD_SOURCE_FCLK        (1<<21)
>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 3752d5e..cce7103 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5012,7 +5012,16 @@ static void intel_update_max_cdclk(struct 
>> drm_device *dev)
>>   {
>>       struct drm_i915_private *dev_priv = dev->dev_private;
>>   -    if (IS_VALLEYVIEW(dev)) {
>> +    if (IS_HASWELL(dev)) {
>> +        if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
>> +            dev_priv->max_cdclk_freq = 450000;
>> +        else if (IS_HSW_ULX(dev))
>> +            dev_priv->max_cdclk_freq = 337500;
>> +        else if (IS_HSW_ULT(dev))
>> +            dev_priv->max_cdclk_freq = 450000;
>> +        else
>> +            dev_priv->max_cdclk_freq = 540000;
>> +    } else if (IS_VALLEYVIEW(dev)) {
>>           dev_priv->max_cdclk_freq = 400000;
>>       } else {
>>           /* otherwise assume cdclk is fixed */
>> @@ -8773,6 +8782,144 @@ void hsw_enable_pc8(struct drm_i915_private 
>> *dev_priv)
>>       hsw_disable_lcpll(dev_priv, true, true);
>>   }
>>   +/* compute the max rate for new configuration */
>> +static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
>> +{
>> +    struct drm_device *dev = dev_priv->dev;
>> +    struct intel_crtc *crtc;
>> +    int max_pixel_rate = 0;
>> +
>> +    for_each_intel_crtc(dev, crtc) {
>> +        if (crtc->new_enabled)
>> +            max_pixel_rate = max(max_pixel_rate,
>> + ilk_pipe_pixel_rate(crtc->new_config));
>> +    }
>> +
>> +    return max_pixel_rate;
>> +}
>> +
>> +static int haswell_calc_cdclk(struct drm_i915_private *dev_priv,
>> +                  int max_pixel_rate)
>> +{
>> +    int cdclk;
>> +
>> +    /*
>> +     * FIXME should also account for plane ratio
>> +     * once 64bpp pixel formats are supported.
>> +     */
>> +    if (max_pixel_rate > 450000)
>> +        cdclk = 540000;
>> +    else if (max_pixel_rate > 337500 || !IS_HSW_ULX(dev_priv))
>> +        cdclk = 450000;
>> +    else
>> +        cdclk = 337500;
>> +
>> +    /*
>> +     * FIXME move the cdclk caclulation to
>> +     * compute_config() so we can fail gracegully.
>> +     */
>> +    if (cdclk > dev_priv->max_cdclk_freq) {
>> +        DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
>> +              cdclk, dev_priv->max_cdclk_freq);
>> +        cdclk = dev_priv->max_cdclk_freq;
>> +    }
>> +
>> +    return cdclk;
>> +}
> won't this return 337MHz even for platforms that have HSW_CDCLK_LIMIT 
> is set ? this should return 450MHz if this fuse is set
>
>> +
>> +static void haswell_set_cdclk(struct drm_device *dev, int cdclk)
>> +{
>> +    struct drm_i915_private *dev_priv = dev->dev_private;
>> +    uint32_t val;
>> +
>> +    if (WARN((I915_READ(LCPLL_CTL) &
>> +          (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
>> +           LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
>> +           LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
>> +           LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
>> +         "trying to change cdclk frequency with cdclk not enabled\n"))
>> +        return;
>> +
>> +    val = I915_READ(LCPLL_CTL);
>> +    val &= ~LCPLL_CLK_FREQ_MASK;
>> +
>> +    switch (cdclk) {
>> +    case 450000:
>> +        val |= LCPLL_CLK_FREQ_450;
>> +        break;
>> +    case 337500:
>> +    case 540000:
>> +        val |= LCPLL_CLK_FREQ_ALT_HSW;
>> +        break;
>> +    default:
>> +        WARN(1, "invalid cdclk frequency\n");
>> +        return;
>> +    }
>> +
>> +    I915_WRITE(LCPLL_CTL, val);
>> +
>> +    if (IS_HSW_ULX(dev)) {
>> +        mutex_lock(&dev_priv->rps.hw_lock);
>> +        sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
>> +                    cdclk == 337500);
>> +        mutex_unlock(&dev_priv->rps.hw_lock);
>> +    }
>> +
>> +    intel_update_cdclk(dev);
>> +
>> +    WARN(cdclk != dev_priv->cdclk_freq,
>> +         "cdclk requested %d kHz but got %d kHz\n",
>> +         cdclk, dev_priv->cdclk_freq);
>> +}
>> +
>> +static void haswell_modeset_global_pipes(struct drm_device *dev,
>> +                     unsigned *prepare_pipes)
>> +{
>> +    struct drm_i915_private *dev_priv = dev->dev_private;
>> +    struct intel_crtc *crtc;
>> +    int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
>> +
>> +    if (haswell_calc_cdclk(dev_priv, max_pixel_rate) ==
>> +        dev_priv->cdclk_freq)
>> +        return;
>> +
>> +    /* disable/enable all currently active pipes while we change 
>> cdclk */
>> +    for_each_intel_crtc(dev, crtc)
>> +        if (crtc->base.enabled)
>> +            *prepare_pipes |= 1 << crtc->pipe;
>> +}
>> +
>> +static void haswell_modeset_global_resources(struct drm_atomic_state 
>> *state)
>> +{
>> +    struct drm_device *dev = state->dev;
>> +    struct drm_i915_private *dev_priv = dev->dev_private;
>> +    int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
>> +    int req_cdclk = haswell_calc_cdclk(dev_priv, max_pixel_rate);
>> +
>> +    if (req_cdclk != dev_priv->cdclk_freq)
>> +        haswell_set_cdclk(dev, req_cdclk);
>> +
>> +    if (req_cdclk != dev_priv->cdclk_freq) {
>> +        /*
>> +         * FIXME: We can end up here with all power domains off, yet
>> +         * with a CDCLK frequency other than the minimum. To account
>> +         * for this take the PIPE-A power domain, which covers the HW
>> +         * blocks needed for the following programming. This can be
>> +         * removed once it's guaranteed that we get here either with
>> +         * the minimum CDCLK set, or the required power domains
>> +         * enabled.
>> +         */
>> +        intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
>> +
>> +        haswell_set_cdclk(dev, req_cdclk);
>> +
>> +        vlv_program_pfi_credits(dev_priv);
>> +
>> +        intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
>> +    }
>> +
>> +}
>> +
>>   void hsw_disable_pc8(struct drm_i915_private *dev_priv)
>>   {
>>       struct drm_device *dev = dev_priv->dev;
>> @@ -8792,6 +8939,8 @@ void hsw_disable_pc8(struct drm_i915_private 
>> *dev_priv)
>>       intel_prepare_ddi(dev);
>>   }
>>   +
>> +
>>   static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>>                         struct intel_crtc_state *crtc_state)
>>   {
>> @@ -11866,8 +12015,11 @@ static int __intel_set_mode(struct drm_crtc 
>> *crtc,
>>        * mode set on this crtc.  For other crtcs we need to use the
>>        * adjusted_mode bits in the crtc directly.
>>        */
>> -    if (IS_VALLEYVIEW(dev)) {
>> -        valleyview_modeset_global_pipes(dev, &prepare_pipes);
>> +    if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev)) {
>> +        if (IS_VALLEYVIEW(dev))
>> +            valleyview_modeset_global_pipes(dev, &prepare_pipes);
>> +        else
>> +            haswell_modeset_global_pipes(dev, &prepare_pipes);
>>             /* may have added more to prepare_pipes than we should */
>>           prepare_pipes &= ~disable_pipes;
>> @@ -13892,6 +14044,9 @@ static void intel_init_display(struct 
>> drm_device *dev)
>>           dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
>>       } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
>>           dev_priv->display.fdi_link_train = hsw_fdi_link_train;
>> +        if (IS_HASWELL(dev))
>> +            dev_priv->display.modeset_global_resources =
>> +                haswell_modeset_global_resources;
>>       } else if (IS_VALLEYVIEW(dev)) {
>>           dev_priv->display.modeset_global_resources =
>>               valleyview_modeset_global_resources;
>
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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Ville Syrjälä]

On Tue, Apr 07, 2015 at 12:33:40PM +0530, Sivakumar Thulasimani wrote:
> sorry if i am missing something, HSW and BDW requires display audio 
> controller to be updated with new values once CD clock is modified. how 
> is this accomplished here ?

I'm hoping the audio driver will query the cdclk frequency after every
modeset.

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Sivakumar Thulasimani]

where can i check this (audio driver) ? since there was no need for them 
to check CD clock value till now i don't think they will be doing it. 
also this needs to be changed in Display Audio controller, so not sure 
if audio driver has access to it in the first place. will be good to 
confirm this before merging as it will break display audio if it is not 
programmed.

if any one has setup this can be confirmed by just switching CD clock 
after boot and playing an audio file.

regards,
Sivakumar

On 4/7/2015 1:59 PM, Ville Syrjälä wrote:
> On Tue, Apr 07, 2015 at 12:33:40PM +0530, Sivakumar Thulasimani wrote:
>> sorry if i am missing something, HSW and BDW requires display audio
>> controller to be updated with new values once CD clock is modified. how
>> is this accomplished here ?
> I'm hoping the audio driver will query the cdclk frequency after every
> modeset.
>

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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Mika Kahola]

Definitely a good idea to check the audio part as well if there is
a doubt that by changing CD clock the audio would fail. I can check
this and I'll get back once I have the results.

Cheers,
Mika
  
On Tue, Apr 07, 2015 at 02:06:50PM +0530, Sivakumar Thulasimani wrote:
> where can i check this (audio driver) ? since there was no need for
> them to check CD clock value till now i don't think they will be
> doing it. also this needs to be changed in Display Audio controller,
> so not sure if audio driver has access to it in the first place.
> will be good to confirm this before merging as it will break display
> audio if it is not programmed.
> 
> if any one has setup this can be confirmed by just switching CD
> clock after boot and playing an audio file.
> 
> regards,
> Sivakumar
> 
> On 4/7/2015 1:59 PM, Ville Syrjälä wrote:
> >On Tue, Apr 07, 2015 at 12:33:40PM +0530, Sivakumar Thulasimani wrote:
> >>sorry if i am missing something, HSW and BDW requires display audio
> >>controller to be updated with new values once CD clock is modified. how
> >>is this accomplished here ?
> >I'm hoping the audio driver will query the cdclk frequency after every
> >modeset.
> >
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Daniel Vetter]

On Tue, Apr 07, 2015 at 12:29:25PM +0300, Mika Kahola wrote:
> Definitely a good idea to check the audio part as well if there is
> a doubt that by changing CD clock the audio would fail. I can check
> this and I'll get back once I have the results.

We force a full modeset, which should result in an interrupt on the audio
side, which should result in the audio driver re-reading the current
cdclk. If that's no the case it's buggy already.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Mika Kahola]

I did some testing on audio part with HDMI-HDMI and DP-HDMI cables
connected to my Haswell box. Before applying the patch I tested as a
reference with the latest -nightly (04-08-2015), 4.0-rc7. Unfortunately,
I failed to get any audio over HDMI cable. For a reference I tested with
the very same setup the vanillla kernel from Linus tree 4.0-rc7 and with
that kernel the audio worked ok. Then I did some GIT bisecting and it
turned out that the first commit that I failed to get audio working was
aa2fee4286e43b4784982b17669b02cc99c1ae55.

To test this patch audio functionality I checkout the -nightly version
that works for me and apply the patch and test it. I'll come back with
the results later on. 

I had the module option i915.disable_power_well=0

The test routine that I used for audio testing was
speaker-test -c 2 -r 48000 -f S16_LE -t pink --device=plughw:0,3

On Tue, 2015-04-07 at 15:52 +0200, Daniel Vetter wrote:
> On Tue, Apr 07, 2015 at 12:29:25PM +0300, Mika Kahola wrote:
> > Definitely a good idea to check the audio part as well if there is
> > a doubt that by changing CD clock the audio would fail. I can check
> > this and I'll get back once I have the results.
> 
> We force a full modeset, which should result in an interrupt on the audio
> side, which should result in the audio driver re-reading the current
> cdclk. If that's no the case it's buggy already.
> -Daniel

-- 
Mika Kahola, Intel OTC



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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Daniel Vetter]

On Thu, Apr 09, 2015 at 10:24:24AM +0300, Mika Kahola wrote:
> I did some testing on audio part with HDMI-HDMI and DP-HDMI cables
> connected to my Haswell box. Before applying the patch I tested as a
> reference with the latest -nightly (04-08-2015), 4.0-rc7. Unfortunately,
> I failed to get any audio over HDMI cable. For a reference I tested with
> the very same setup the vanillla kernel from Linus tree 4.0-rc7 and with
> that kernel the audio worked ok. Then I did some GIT bisecting and it
> turned out that the first commit that I failed to get audio working was
> aa2fee4286e43b4784982b17669b02cc99c1ae55.

I don't have this sha1 anywhere. Can you please double-check?

Also to avoid such issues please always add at least the commit subject
and author, so that I can find it if it's somehow rebased.
-Daniel

> 
> To test this patch audio functionality I checkout the -nightly version
> that works for me and apply the patch and test it. I'll come back with
> the results later on. 
> 
> I had the module option i915.disable_power_well=0
> 
> The test routine that I used for audio testing was
> speaker-test -c 2 -r 48000 -f S16_LE -t pink --device=plughw:0,3
> 
> On Tue, 2015-04-07 at 15:52 +0200, Daniel Vetter wrote:
> > On Tue, Apr 07, 2015 at 12:29:25PM +0300, Mika Kahola wrote:
> > > Definitely a good idea to check the audio part as well if there is
> > > a doubt that by changing CD clock the audio would fail. I can check
> > > this and I'll get back once I have the results.
> > 
> > We force a full modeset, which should result in an interrupt on the audio
> > side, which should result in the audio driver re-reading the current
> > cdclk. If that's no the case it's buggy already.
> > -Daniel
> 
> -- 
> Mika Kahola, Intel OTC
> 
> 
> 

-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Mika Kahola]

On Thu, 2015-04-09 at 11:32 +0200, Daniel Vetter wrote:
> On Thu, Apr 09, 2015 at 10:24:24AM +0300, Mika Kahola wrote:
> > I did some testing on audio part with HDMI-HDMI and DP-HDMI cables
> > connected to my Haswell box. Before applying the patch I tested as a
> > reference with the latest -nightly (04-08-2015), 4.0-rc7. Unfortunately,
> > I failed to get any audio over HDMI cable. For a reference I tested with
> > the very same setup the vanillla kernel from Linus tree 4.0-rc7 and with
> > that kernel the audio worked ok. Then I did some GIT bisecting and it
> > turned out that the first commit that I failed to get audio working was
> > aa2fee4286e43b4784982b17669b02cc99c1ae55.
> 
I rerun the bisecting and this time the result was

commit 0a599838737a2527c35e4d94f794aefe59df1781
Merge: 2d846c7 a59d719
Author: Takashi Iwai <tiwai@suse.de>
Date:   Wed Apr 8 11:29:56 2015 +0200

    Merge branch 'for-linus' into for-next
    
    Back merge HD-audio quirks to for-next branch, so that we can apply
    a couple of more quirks.
    
    Signed-off-by: Takashi Iwai <tiwai@suse.de>

> I don't have this sha1 anywhere. Can you please double-check?
> 
> Also to avoid such issues please always add at least the commit subject
> and author, so that I can find it if it's somehow rebased.
> -Daniel
> 
> > 
> > To test this patch audio functionality I checkout the -nightly version
> > that works for me and apply the patch and test it. I'll come back with
> > the results later on. 
> > 
> > I had the module option i915.disable_power_well=0
> > 
> > The test routine that I used for audio testing was
> > speaker-test -c 2 -r 48000 -f S16_LE -t pink --device=plughw:0,3
> > 
> > On Tue, 2015-04-07 at 15:52 +0200, Daniel Vetter wrote:
> > > On Tue, Apr 07, 2015 at 12:29:25PM +0300, Mika Kahola wrote:
> > > > Definitely a good idea to check the audio part as well if there is
> > > > a doubt that by changing CD clock the audio would fail. I can check
> > > > this and I'll get back once I have the results.
> > > 
> > > We force a full modeset, which should result in an interrupt on the audio
> > > side, which should result in the audio driver re-reading the current
> > > cdclk. If that's no the case it's buggy already.
> > > -Daniel
> > 
> > -- 
> > Mika Kahola, Intel OTC
> > 
> > 
> > 
> 

-- 
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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Daniel Vetter]

On Thu, Apr 09, 2015 at 04:41:26PM +0300, Mika Kahola wrote:
> On Thu, 2015-04-09 at 11:32 +0200, Daniel Vetter wrote:
> > On Thu, Apr 09, 2015 at 10:24:24AM +0300, Mika Kahola wrote:
> > > I did some testing on audio part with HDMI-HDMI and DP-HDMI cables
> > > connected to my Haswell box. Before applying the patch I tested as a
> > > reference with the latest -nightly (04-08-2015), 4.0-rc7. Unfortunately,
> > > I failed to get any audio over HDMI cable. For a reference I tested with
> > > the very same setup the vanillla kernel from Linus tree 4.0-rc7 and with
> > > that kernel the audio worked ok. Then I did some GIT bisecting and it
> > > turned out that the first commit that I failed to get audio working was
> > > aa2fee4286e43b4784982b17669b02cc99c1ae55.
> > 
> I rerun the bisecting and this time the result was
> 
> commit 0a599838737a2527c35e4d94f794aefe59df1781
> Merge: 2d846c7 a59d719
> Author: Takashi Iwai <tiwai@suse.de>
> Date:   Wed Apr 8 11:29:56 2015 +0200
> 
>     Merge branch 'for-linus' into for-next
>     
>     Back merge HD-audio quirks to for-next branch, so that we can apply
>     a couple of more quirks.
>     
>     Signed-off-by: Takashi Iwai <tiwai@suse.de>

Adding Takashi and intel audio folks.
-Daniel

> 
> > I don't have this sha1 anywhere. Can you please double-check?
> > 
> > Also to avoid such issues please always add at least the commit subject
> > and author, so that I can find it if it's somehow rebased.
> > -Daniel
> > 
> > > 
> > > To test this patch audio functionality I checkout the -nightly version
> > > that works for me and apply the patch and test it. I'll come back with
> > > the results later on. 
> > > 
> > > I had the module option i915.disable_power_well=0
> > > 
> > > The test routine that I used for audio testing was
> > > speaker-test -c 2 -r 48000 -f S16_LE -t pink --device=plughw:0,3
> > > 
> > > On Tue, 2015-04-07 at 15:52 +0200, Daniel Vetter wrote:
> > > > On Tue, Apr 07, 2015 at 12:29:25PM +0300, Mika Kahola wrote:
> > > > > Definitely a good idea to check the audio part as well if there is
> > > > > a doubt that by changing CD clock the audio would fail. I can check
> > > > > this and I'll get back once I have the results.
> > > > 
> > > > We force a full modeset, which should result in an interrupt on the audio
> > > > side, which should result in the audio driver re-reading the current
> > > > cdclk. If that's no the case it's buggy already.
> > > > -Daniel
> > > 
> > > -- 
> > > Mika Kahola, Intel OTC
> > > 
> > > 
> > > 
> > 
> 
> -- 
> Mika Kahola, Intel OTC
> 
> 
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Takashi Iwai]

At Thu, 9 Apr 2015 15:51:27 +0200,
Daniel Vetter wrote:
> 
> On Thu, Apr 09, 2015 at 04:41:26PM +0300, Mika Kahola wrote:
> > On Thu, 2015-04-09 at 11:32 +0200, Daniel Vetter wrote:
> > > On Thu, Apr 09, 2015 at 10:24:24AM +0300, Mika Kahola wrote:
> > > > I did some testing on audio part with HDMI-HDMI and DP-HDMI cables
> > > > connected to my Haswell box. Before applying the patch I tested as a
> > > > reference with the latest -nightly (04-08-2015), 4.0-rc7. Unfortunately,
> > > > I failed to get any audio over HDMI cable. For a reference I tested with
> > > > the very same setup the vanillla kernel from Linus tree 4.0-rc7 and with
> > > > that kernel the audio worked ok. Then I did some GIT bisecting and it
> > > > turned out that the first commit that I failed to get audio working was
> > > > aa2fee4286e43b4784982b17669b02cc99c1ae55.
> > > 
> > I rerun the bisecting and this time the result was
> > 
> > commit 0a599838737a2527c35e4d94f794aefe59df1781
> > Merge: 2d846c7 a59d719
> > Author: Takashi Iwai <tiwai@suse.de>
> > Date:   Wed Apr 8 11:29:56 2015 +0200
> > 
> >     Merge branch 'for-linus' into for-next
> >     
> >     Back merge HD-audio quirks to for-next branch, so that we can apply
> >     a couple of more quirks.
> >     
> >     Signed-off-by: Takashi Iwai <tiwai@suse.de>
> 
> Adding Takashi and intel audio folks.

The bisecting looks odd.  The commit you pointed is a back-merge from
4.0-rc to next branch, so this merge itself shouldn't bring so many
stuff -- at least about the sound part.

The diff in sound/* is found below.  As you can see, the only change
relevant with HDMI is the chunk in sound/pci/hda/hda_intel.c for
HD-audio controller, but it's specific to Skylake, thus this must be
irrelevant with your hardware.

Please double-check.


thanks,

Takashi

===
% git diff 0a599838737a2527c35e4d94f794aefe59df1781^..0a599838737a2527c35e4d94f794aefe59df1781 sound
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 9bcc5457a83e..e1c210515581 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -1967,7 +1967,7 @@ static const struct pci_device_id azx_ids[] = {
 	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
 	/* Sunrise Point */
 	{ PCI_DEVICE(0x8086, 0xa170),
-	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
+	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
 	/* Sunrise Point-LP */
 	{ PCI_DEVICE(0x8086, 0x9d70),
 	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index e0c06f9a0e80..7f46d063af57 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -396,7 +396,7 @@ static void alc_auto_setup_eapd(struct hda_codec *codec, bool on)
 {
 	/* We currently only handle front, HP */
 	static hda_nid_t pins[] = {
-		0x0f, 0x10, 0x14, 0x15, 0
+		0x0f, 0x10, 0x14, 0x15, 0x17, 0
 	};
 	hda_nid_t *p;
 	for (p = pins; *p; p++)
@@ -2870,6 +2870,8 @@ static void alc283_init(struct hda_codec *codec)
 
 	if (!hp_pin)
 		return;
+
+	msleep(30);
 	hp_pin_sense = snd_hda_jack_detect(codec, hp_pin);
 
 	/* Index 0x43 Direct Drive HP AMP LPM Control 1 */
@@ -3564,6 +3566,7 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec)
 
 	switch (codec->core.vendor_id) {
 	case 0x10ec0255:
+	case 0x10ec0256:
 		alc_process_coef_fw(codec, coef0255);
 		break;
 	case 0x10ec0233:
@@ -3619,6 +3622,7 @@ static void alc_headset_mode_mic_in(struct hda_codec *codec, hda_nid_t hp_pin,
 
 	switch (codec->core.vendor_id) {
 	case 0x10ec0255:
+	case 0x10ec0256:
 		alc_write_coef_idx(codec, 0x45, 0xc489);
 		snd_hda_set_pin_ctl_cache(codec, hp_pin, 0);
 		alc_process_coef_fw(codec, coef0255);
@@ -3688,6 +3692,7 @@ static void alc_headset_mode_default(struct hda_codec *codec)
 
 	switch (codec->core.vendor_id) {
 	case 0x10ec0255:
+	case 0x10ec0256:
 		alc_process_coef_fw(codec, coef0255);
 		break;
 	case 0x10ec0233:
@@ -3742,6 +3747,7 @@ static void alc_headset_mode_ctia(struct hda_codec *codec)
 
 	switch (codec->core.vendor_id) {
 	case 0x10ec0255:
+	case 0x10ec0256:
 		alc_process_coef_fw(codec, coef0255);
 		break;
 	case 0x10ec0233:
@@ -3796,6 +3802,7 @@ static void alc_headset_mode_omtp(struct hda_codec *codec)
 
 	switch (codec->core.vendor_id) {
 	case 0x10ec0255:
+	case 0x10ec0256:
 		alc_process_coef_fw(codec, coef0255);
 		break;
 	case 0x10ec0233:
@@ -3841,6 +3848,7 @@ static void alc_determine_headset_type(struct hda_codec *codec)
 
 	switch (codec->core.vendor_id) {
 	case 0x10ec0255:
+	case 0x10ec0256:
 		alc_process_coef_fw(codec, coef0255);
 		msleep(300);
 		val = alc_read_coef_idx(codec, 0x46);
@@ -4993,6 +5001,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
 	SND_PCI_QUIRK(0x17aa, 0x501a, "Thinkpad", ALC283_FIXUP_INT_MIC),
 	SND_PCI_QUIRK(0x17aa, 0x501e, "Thinkpad L440", ALC292_FIXUP_TPT440_DOCK),
 	SND_PCI_QUIRK(0x17aa, 0x5026, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
+	SND_PCI_QUIRK(0x17aa, 0x5036, "Thinkpad T450s", ALC292_FIXUP_TPT440_DOCK),
 	SND_PCI_QUIRK(0x17aa, 0x5109, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
 	SND_PCI_QUIRK(0x17aa, 0x3bf8, "Quanta FL1", ALC269_FIXUP_PCM_44K),
 	SND_PCI_QUIRK(0x17aa, 0x9e54, "LENOVO NB", ALC269_FIXUP_LENOVO_EAPD),
@@ -5173,6 +5182,16 @@ static const struct snd_hda_pin_quirk alc269_pin_fixup_tbl[] = {
 		{0x17, 0x40000000},
 		{0x1d, 0x40700001},
 		{0x21, 0x02211050}),
+	SND_HDA_PIN_QUIRK(0x10ec0256, 0x1028, "Dell", ALC255_FIXUP_DELL1_MIC_NO_PRESENCE,
+		{0x12, 0x90a60140},
+		{0x13, 0x40000000},
+		{0x14, 0x90170110},
+		{0x19, 0x411111f0},
+		{0x1a, 0x411111f0},
+		{0x1b, 0x411111f0},
+		{0x1d, 0x40700001},
+		{0x1e, 0x411111f0},
+		{0x21, 0x02211020}),
 	SND_HDA_PIN_QUIRK(0x10ec0280, 0x103c, "HP", ALC280_FIXUP_HP_GPIO4,
 		{0x12, 0x90a60130},
 		{0x13, 0x40000000},
diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
index 353532b8aee4..8f63e8c8b46c 100644
--- a/sound/usb/quirks.c
+++ b/sound/usb/quirks.c
@@ -1113,8 +1113,13 @@ void snd_usb_set_format_quirk(struct snd_usb_substream *subs,
 
 bool snd_usb_get_sample_rate_quirk(struct snd_usb_audio *chip)
 {
-	/* MS Lifecam HD-5000 doesn't support reading the sample rate. */
-	return chip->usb_id == USB_ID(0x045E, 0x076D);
+	/* devices which do not support reading the sample rate. */
+	switch (chip->usb_id) {
+	case USB_ID(0x045E, 0x076D): /* MS Lifecam HD-5000 */
+	case USB_ID(0x04D8, 0xFEEA): /* Benchmark DAC1 Pre */
+		return true;
+	}
+	return false;
 }
 
 /* Marantz/Denon USB DACs need a vendor cmd to switch

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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Mika Kahola]

On Thu, 2015-04-09 at 17:17 +0200, Takashi Iwai wrote:
> At Thu, 9 Apr 2015 15:51:27 +0200,
> Daniel Vetter wrote:
> > 
> > On Thu, Apr 09, 2015 at 04:41:26PM +0300, Mika Kahola wrote:
> > > On Thu, 2015-04-09 at 11:32 +0200, Daniel Vetter wrote:
> > > > On Thu, Apr 09, 2015 at 10:24:24AM +0300, Mika Kahola wrote:
> > > > > I did some testing on audio part with HDMI-HDMI and DP-HDMI cables
> > > > > connected to my Haswell box. Before applying the patch I tested as a
> > > > > reference with the latest -nightly (04-08-2015), 4.0-rc7. Unfortunately,
> > > > > I failed to get any audio over HDMI cable. For a reference I tested with
> > > > > the very same setup the vanillla kernel from Linus tree 4.0-rc7 and with
> > > > > that kernel the audio worked ok. Then I did some GIT bisecting and it
> > > > > turned out that the first commit that I failed to get audio working was
> > > > > aa2fee4286e43b4784982b17669b02cc99c1ae55.
> > > > 
> > > I rerun the bisecting and this time the result was
> > > 
> > > commit 0a599838737a2527c35e4d94f794aefe59df1781
> > > Merge: 2d846c7 a59d719
> > > Author: Takashi Iwai <tiwai@suse.de>
> > > Date:   Wed Apr 8 11:29:56 2015 +0200
> > > 
> > >     Merge branch 'for-linus' into for-next
> > >     
> > >     Back merge HD-audio quirks to for-next branch, so that we can apply
> > >     a couple of more quirks.
> > >     
> > >     Signed-off-by: Takashi Iwai <tiwai@suse.de>
> > 
> > Adding Takashi and intel audio folks.
> 
> The bisecting looks odd.  The commit you pointed is a back-merge from
> 4.0-rc to next branch, so this merge itself shouldn't bring so many
> stuff -- at least about the sound part.
> 
> The diff in sound/* is found below.  As you can see, the only change
> relevant with HDMI is the chunk in sound/pci/hda/hda_intel.c for
> HD-audio controller, but it's specific to Skylake, thus this must be
> irrelevant with your hardware.
> 
> Please double-check.

I double-checked the bisecting and I ended up with the same result. You're
right, it does seems odd why audio on my Haswell box stopped working.

Any ideas how to proceed from here?

Cheers,
Mika


> thanks,
> 
> Takashi
> 
> ===
> % git diff 0a599838737a2527c35e4d94f794aefe59df1781^..0a599838737a2527c35e4d94f794aefe59df1781 sound
> diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
> index 9bcc5457a83e..e1c210515581 100644
> --- a/sound/pci/hda/hda_intel.c
> +++ b/sound/pci/hda/hda_intel.c
> @@ -1967,7 +1967,7 @@ static const struct pci_device_id azx_ids[] = {
>  	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
>  	/* Sunrise Point */
>  	{ PCI_DEVICE(0x8086, 0xa170),
> -	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
> +	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
>  	/* Sunrise Point-LP */
>  	{ PCI_DEVICE(0x8086, 0x9d70),
>  	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
> diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
> index e0c06f9a0e80..7f46d063af57 100644
> --- a/sound/pci/hda/patch_realtek.c
> +++ b/sound/pci/hda/patch_realtek.c
> @@ -396,7 +396,7 @@ static void alc_auto_setup_eapd(struct hda_codec *codec, bool on)
>  {
>  	/* We currently only handle front, HP */
>  	static hda_nid_t pins[] = {
> -		0x0f, 0x10, 0x14, 0x15, 0
> +		0x0f, 0x10, 0x14, 0x15, 0x17, 0
>  	};
>  	hda_nid_t *p;
>  	for (p = pins; *p; p++)
> @@ -2870,6 +2870,8 @@ static void alc283_init(struct hda_codec *codec)
>  
>  	if (!hp_pin)
>  		return;
> +
> +	msleep(30);
>  	hp_pin_sense = snd_hda_jack_detect(codec, hp_pin);
>  
>  	/* Index 0x43 Direct Drive HP AMP LPM Control 1 */
> @@ -3564,6 +3566,7 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec)
>  
>  	switch (codec->core.vendor_id) {
>  	case 0x10ec0255:
> +	case 0x10ec0256:
>  		alc_process_coef_fw(codec, coef0255);
>  		break;
>  	case 0x10ec0233:
> @@ -3619,6 +3622,7 @@ static void alc_headset_mode_mic_in(struct hda_codec *codec, hda_nid_t hp_pin,
>  
>  	switch (codec->core.vendor_id) {
>  	case 0x10ec0255:
> +	case 0x10ec0256:
>  		alc_write_coef_idx(codec, 0x45, 0xc489);
>  		snd_hda_set_pin_ctl_cache(codec, hp_pin, 0);
>  		alc_process_coef_fw(codec, coef0255);
> @@ -3688,6 +3692,7 @@ static void alc_headset_mode_default(struct hda_codec *codec)
>  
>  	switch (codec->core.vendor_id) {
>  	case 0x10ec0255:
> +	case 0x10ec0256:
>  		alc_process_coef_fw(codec, coef0255);
>  		break;
>  	case 0x10ec0233:
> @@ -3742,6 +3747,7 @@ static void alc_headset_mode_ctia(struct hda_codec *codec)
>  
>  	switch (codec->core.vendor_id) {
>  	case 0x10ec0255:
> +	case 0x10ec0256:
>  		alc_process_coef_fw(codec, coef0255);
>  		break;
>  	case 0x10ec0233:
> @@ -3796,6 +3802,7 @@ static void alc_headset_mode_omtp(struct hda_codec *codec)
>  
>  	switch (codec->core.vendor_id) {
>  	case 0x10ec0255:
> +	case 0x10ec0256:
>  		alc_process_coef_fw(codec, coef0255);
>  		break;
>  	case 0x10ec0233:
> @@ -3841,6 +3848,7 @@ static void alc_determine_headset_type(struct hda_codec *codec)
>  
>  	switch (codec->core.vendor_id) {
>  	case 0x10ec0255:
> +	case 0x10ec0256:
>  		alc_process_coef_fw(codec, coef0255);
>  		msleep(300);
>  		val = alc_read_coef_idx(codec, 0x46);
> @@ -4993,6 +5001,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
>  	SND_PCI_QUIRK(0x17aa, 0x501a, "Thinkpad", ALC283_FIXUP_INT_MIC),
>  	SND_PCI_QUIRK(0x17aa, 0x501e, "Thinkpad L440", ALC292_FIXUP_TPT440_DOCK),
>  	SND_PCI_QUIRK(0x17aa, 0x5026, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
> +	SND_PCI_QUIRK(0x17aa, 0x5036, "Thinkpad T450s", ALC292_FIXUP_TPT440_DOCK),
>  	SND_PCI_QUIRK(0x17aa, 0x5109, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
>  	SND_PCI_QUIRK(0x17aa, 0x3bf8, "Quanta FL1", ALC269_FIXUP_PCM_44K),
>  	SND_PCI_QUIRK(0x17aa, 0x9e54, "LENOVO NB", ALC269_FIXUP_LENOVO_EAPD),
> @@ -5173,6 +5182,16 @@ static const struct snd_hda_pin_quirk alc269_pin_fixup_tbl[] = {
>  		{0x17, 0x40000000},
>  		{0x1d, 0x40700001},
>  		{0x21, 0x02211050}),
> +	SND_HDA_PIN_QUIRK(0x10ec0256, 0x1028, "Dell", ALC255_FIXUP_DELL1_MIC_NO_PRESENCE,
> +		{0x12, 0x90a60140},
> +		{0x13, 0x40000000},
> +		{0x14, 0x90170110},
> +		{0x19, 0x411111f0},
> +		{0x1a, 0x411111f0},
> +		{0x1b, 0x411111f0},
> +		{0x1d, 0x40700001},
> +		{0x1e, 0x411111f0},
> +		{0x21, 0x02211020}),
>  	SND_HDA_PIN_QUIRK(0x10ec0280, 0x103c, "HP", ALC280_FIXUP_HP_GPIO4,
>  		{0x12, 0x90a60130},
>  		{0x13, 0x40000000},
> diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
> index 353532b8aee4..8f63e8c8b46c 100644
> --- a/sound/usb/quirks.c
> +++ b/sound/usb/quirks.c
> @@ -1113,8 +1113,13 @@ void snd_usb_set_format_quirk(struct snd_usb_substream *subs,
>  
>  bool snd_usb_get_sample_rate_quirk(struct snd_usb_audio *chip)
>  {
> -	/* MS Lifecam HD-5000 doesn't support reading the sample rate. */
> -	return chip->usb_id == USB_ID(0x045E, 0x076D);
> +	/* devices which do not support reading the sample rate. */
> +	switch (chip->usb_id) {
> +	case USB_ID(0x045E, 0x076D): /* MS Lifecam HD-5000 */
> +	case USB_ID(0x04D8, 0xFEEA): /* Benchmark DAC1 Pre */
> +		return true;
> +	}
> +	return false;
>  }
>  
>  /* Marantz/Denon USB DACs need a vendor cmd to switch
> 


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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Takashi Iwai]

At Fri, 10 Apr 2015 16:27:39 +0300,
Mika Kahola wrote:
> 
> On Thu, 2015-04-09 at 17:17 +0200, Takashi Iwai wrote:
> > At Thu, 9 Apr 2015 15:51:27 +0200,
> > Daniel Vetter wrote:
> > > 
> > > On Thu, Apr 09, 2015 at 04:41:26PM +0300, Mika Kahola wrote:
> > > > On Thu, 2015-04-09 at 11:32 +0200, Daniel Vetter wrote:
> > > > > On Thu, Apr 09, 2015 at 10:24:24AM +0300, Mika Kahola wrote:
> > > > > > I did some testing on audio part with HDMI-HDMI and DP-HDMI cables
> > > > > > connected to my Haswell box. Before applying the patch I tested as a
> > > > > > reference with the latest -nightly (04-08-2015), 4.0-rc7. Unfortunately,
> > > > > > I failed to get any audio over HDMI cable. For a reference I tested with
> > > > > > the very same setup the vanillla kernel from Linus tree 4.0-rc7 and with
> > > > > > that kernel the audio worked ok. Then I did some GIT bisecting and it
> > > > > > turned out that the first commit that I failed to get audio working was
> > > > > > aa2fee4286e43b4784982b17669b02cc99c1ae55.
> > > > > 
> > > > I rerun the bisecting and this time the result was
> > > > 
> > > > commit 0a599838737a2527c35e4d94f794aefe59df1781
> > > > Merge: 2d846c7 a59d719
> > > > Author: Takashi Iwai <tiwai@suse.de>
> > > > Date:   Wed Apr 8 11:29:56 2015 +0200
> > > > 
> > > >     Merge branch 'for-linus' into for-next
> > > >     
> > > >     Back merge HD-audio quirks to for-next branch, so that we can apply
> > > >     a couple of more quirks.
> > > >     
> > > >     Signed-off-by: Takashi Iwai <tiwai@suse.de>
> > > 
> > > Adding Takashi and intel audio folks.
> > 
> > The bisecting looks odd.  The commit you pointed is a back-merge from
> > 4.0-rc to next branch, so this merge itself shouldn't bring so many
> > stuff -- at least about the sound part.
> > 
> > The diff in sound/* is found below.  As you can see, the only change
> > relevant with HDMI is the chunk in sound/pci/hda/hda_intel.c for
> > HD-audio controller, but it's specific to Skylake, thus this must be
> > irrelevant with your hardware.
> > 
> > Please double-check.
> 
> I double-checked the bisecting and I ended up with the same result. You're
> right, it does seems odd why audio on my Haswell box stopped working.
> 
> Any ideas how to proceed from here?

Try to check whether the reverting the diff of sound/* manually fixes
the problem.  (i.e. apply diff -R for the diff I showed in the
previous mail.)

If it doesn't fix but still reverting the whole commit does fix, it
means that something else got broken by the merge.


Takashi


> 
> Cheers,
> Mika
> 
> 
> > thanks,
> > 
> > Takashi
> > 
> > ===
> > % git diff 0a599838737a2527c35e4d94f794aefe59df1781^..0a599838737a2527c35e4d94f794aefe59df1781 sound
> > diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
> > index 9bcc5457a83e..e1c210515581 100644
> > --- a/sound/pci/hda/hda_intel.c
> > +++ b/sound/pci/hda/hda_intel.c
> > @@ -1967,7 +1967,7 @@ static const struct pci_device_id azx_ids[] = {
> >  	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
> >  	/* Sunrise Point */
> >  	{ PCI_DEVICE(0x8086, 0xa170),
> > -	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
> > +	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
> >  	/* Sunrise Point-LP */
> >  	{ PCI_DEVICE(0x8086, 0x9d70),
> >  	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
> > diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
> > index e0c06f9a0e80..7f46d063af57 100644
> > --- a/sound/pci/hda/patch_realtek.c
> > +++ b/sound/pci/hda/patch_realtek.c
> > @@ -396,7 +396,7 @@ static void alc_auto_setup_eapd(struct hda_codec *codec, bool on)
> >  {
> >  	/* We currently only handle front, HP */
> >  	static hda_nid_t pins[] = {
> > -		0x0f, 0x10, 0x14, 0x15, 0
> > +		0x0f, 0x10, 0x14, 0x15, 0x17, 0
> >  	};
> >  	hda_nid_t *p;
> >  	for (p = pins; *p; p++)
> > @@ -2870,6 +2870,8 @@ static void alc283_init(struct hda_codec *codec)
> >  
> >  	if (!hp_pin)
> >  		return;
> > +
> > +	msleep(30);
> >  	hp_pin_sense = snd_hda_jack_detect(codec, hp_pin);
> >  
> >  	/* Index 0x43 Direct Drive HP AMP LPM Control 1 */
> > @@ -3564,6 +3566,7 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec)
> >  
> >  	switch (codec->core.vendor_id) {
> >  	case 0x10ec0255:
> > +	case 0x10ec0256:
> >  		alc_process_coef_fw(codec, coef0255);
> >  		break;
> >  	case 0x10ec0233:
> > @@ -3619,6 +3622,7 @@ static void alc_headset_mode_mic_in(struct hda_codec *codec, hda_nid_t hp_pin,
> >  
> >  	switch (codec->core.vendor_id) {
> >  	case 0x10ec0255:
> > +	case 0x10ec0256:
> >  		alc_write_coef_idx(codec, 0x45, 0xc489);
> >  		snd_hda_set_pin_ctl_cache(codec, hp_pin, 0);
> >  		alc_process_coef_fw(codec, coef0255);
> > @@ -3688,6 +3692,7 @@ static void alc_headset_mode_default(struct hda_codec *codec)
> >  
> >  	switch (codec->core.vendor_id) {
> >  	case 0x10ec0255:
> > +	case 0x10ec0256:
> >  		alc_process_coef_fw(codec, coef0255);
> >  		break;
> >  	case 0x10ec0233:
> > @@ -3742,6 +3747,7 @@ static void alc_headset_mode_ctia(struct hda_codec *codec)
> >  
> >  	switch (codec->core.vendor_id) {
> >  	case 0x10ec0255:
> > +	case 0x10ec0256:
> >  		alc_process_coef_fw(codec, coef0255);
> >  		break;
> >  	case 0x10ec0233:
> > @@ -3796,6 +3802,7 @@ static void alc_headset_mode_omtp(struct hda_codec *codec)
> >  
> >  	switch (codec->core.vendor_id) {
> >  	case 0x10ec0255:
> > +	case 0x10ec0256:
> >  		alc_process_coef_fw(codec, coef0255);
> >  		break;
> >  	case 0x10ec0233:
> > @@ -3841,6 +3848,7 @@ static void alc_determine_headset_type(struct hda_codec *codec)
> >  
> >  	switch (codec->core.vendor_id) {
> >  	case 0x10ec0255:
> > +	case 0x10ec0256:
> >  		alc_process_coef_fw(codec, coef0255);
> >  		msleep(300);
> >  		val = alc_read_coef_idx(codec, 0x46);
> > @@ -4993,6 +5001,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
> >  	SND_PCI_QUIRK(0x17aa, 0x501a, "Thinkpad", ALC283_FIXUP_INT_MIC),
> >  	SND_PCI_QUIRK(0x17aa, 0x501e, "Thinkpad L440", ALC292_FIXUP_TPT440_DOCK),
> >  	SND_PCI_QUIRK(0x17aa, 0x5026, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
> > +	SND_PCI_QUIRK(0x17aa, 0x5036, "Thinkpad T450s", ALC292_FIXUP_TPT440_DOCK),
> >  	SND_PCI_QUIRK(0x17aa, 0x5109, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
> >  	SND_PCI_QUIRK(0x17aa, 0x3bf8, "Quanta FL1", ALC269_FIXUP_PCM_44K),
> >  	SND_PCI_QUIRK(0x17aa, 0x9e54, "LENOVO NB", ALC269_FIXUP_LENOVO_EAPD),
> > @@ -5173,6 +5182,16 @@ static const struct snd_hda_pin_quirk alc269_pin_fixup_tbl[] = {
> >  		{0x17, 0x40000000},
> >  		{0x1d, 0x40700001},
> >  		{0x21, 0x02211050}),
> > +	SND_HDA_PIN_QUIRK(0x10ec0256, 0x1028, "Dell", ALC255_FIXUP_DELL1_MIC_NO_PRESENCE,
> > +		{0x12, 0x90a60140},
> > +		{0x13, 0x40000000},
> > +		{0x14, 0x90170110},
> > +		{0x19, 0x411111f0},
> > +		{0x1a, 0x411111f0},
> > +		{0x1b, 0x411111f0},
> > +		{0x1d, 0x40700001},
> > +		{0x1e, 0x411111f0},
> > +		{0x21, 0x02211020}),
> >  	SND_HDA_PIN_QUIRK(0x10ec0280, 0x103c, "HP", ALC280_FIXUP_HP_GPIO4,
> >  		{0x12, 0x90a60130},
> >  		{0x13, 0x40000000},
> > diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
> > index 353532b8aee4..8f63e8c8b46c 100644
> > --- a/sound/usb/quirks.c
> > +++ b/sound/usb/quirks.c
> > @@ -1113,8 +1113,13 @@ void snd_usb_set_format_quirk(struct snd_usb_substream *subs,
> >  
> >  bool snd_usb_get_sample_rate_quirk(struct snd_usb_audio *chip)
> >  {
> > -	/* MS Lifecam HD-5000 doesn't support reading the sample rate. */
> > -	return chip->usb_id == USB_ID(0x045E, 0x076D);
> > +	/* devices which do not support reading the sample rate. */
> > +	switch (chip->usb_id) {
> > +	case USB_ID(0x045E, 0x076D): /* MS Lifecam HD-5000 */
> > +	case USB_ID(0x04D8, 0xFEEA): /* Benchmark DAC1 Pre */
> > +		return true;
> > +	}
> > +	return false;
> >  }
> >  
> >  /* Marantz/Denon USB DACs need a vendor cmd to switch
> > 
> 
> 
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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Mika Kahola]

On Fri, 2015-04-10 at 16:10 +0200, Takashi Iwai wrote:
> At Fri, 10 Apr 2015 16:27:39 +0300,
> Mika Kahola wrote:
> > 
> > On Thu, 2015-04-09 at 17:17 +0200, Takashi Iwai wrote:
> > > At Thu, 9 Apr 2015 15:51:27 +0200,
> > > Daniel Vetter wrote:
> > > > 
> > > > On Thu, Apr 09, 2015 at 04:41:26PM +0300, Mika Kahola wrote:
> > > > > On Thu, 2015-04-09 at 11:32 +0200, Daniel Vetter wrote:
> > > > > > On Thu, Apr 09, 2015 at 10:24:24AM +0300, Mika Kahola wrote:
> > > > > > > I did some testing on audio part with HDMI-HDMI and DP-HDMI cables
> > > > > > > connected to my Haswell box. Before applying the patch I tested as a
> > > > > > > reference with the latest -nightly (04-08-2015), 4.0-rc7. Unfortunately,
> > > > > > > I failed to get any audio over HDMI cable. For a reference I tested with
> > > > > > > the very same setup the vanillla kernel from Linus tree 4.0-rc7 and with
> > > > > > > that kernel the audio worked ok. Then I did some GIT bisecting and it
> > > > > > > turned out that the first commit that I failed to get audio working was
> > > > > > > aa2fee4286e43b4784982b17669b02cc99c1ae55.
> > > > > > 
> > > > > I rerun the bisecting and this time the result was
> > > > > 
> > > > > commit 0a599838737a2527c35e4d94f794aefe59df1781
> > > > > Merge: 2d846c7 a59d719
> > > > > Author: Takashi Iwai <tiwai@suse.de>
> > > > > Date:   Wed Apr 8 11:29:56 2015 +0200
> > > > > 
> > > > >     Merge branch 'for-linus' into for-next
> > > > >     
> > > > >     Back merge HD-audio quirks to for-next branch, so that we can apply
> > > > >     a couple of more quirks.
> > > > >     
> > > > >     Signed-off-by: Takashi Iwai <tiwai@suse.de>
> > > > 
> > > > Adding Takashi and intel audio folks.
> > > 
> > > The bisecting looks odd.  The commit you pointed is a back-merge from
> > > 4.0-rc to next branch, so this merge itself shouldn't bring so many
> > > stuff -- at least about the sound part.
> > > 
> > > The diff in sound/* is found below.  As you can see, the only change
> > > relevant with HDMI is the chunk in sound/pci/hda/hda_intel.c for
> > > HD-audio controller, but it's specific to Skylake, thus this must be
> > > irrelevant with your hardware.
> > > 
> > > Please double-check.
> > 
> > I double-checked the bisecting and I ended up with the same result. You're
> > right, it does seems odd why audio on my Haswell box stopped working.
> > 
> > Any ideas how to proceed from here?
> 
> Try to check whether the reverting the diff of sound/* manually fixes
> the problem.  (i.e. apply diff -R for the diff I showed in the
> previous mail.)
> 
> If it doesn't fix but still reverting the whole commit does fix, it
> means that something else got broken by the merge.
> 
> 
> Takashi
> 

I reverted the diff but unfortunately there were no difference. 

For curiosity, I tested the audio with the latest -nightly and I got
the audio working again. I wonder what has changed but it seems that
the problem is now solved.

-Mika-

> 
> > 
> > Cheers,
> > Mika
> > 
> > 
> > > thanks,
> > > 
> > > Takashi
> > > 
> > > ===
> > > % git diff 0a599838737a2527c35e4d94f794aefe59df1781^..0a599838737a2527c35e4d94f794aefe59df1781 sound
> > > diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
> > > index 9bcc5457a83e..e1c210515581 100644
> > > --- a/sound/pci/hda/hda_intel.c
> > > +++ b/sound/pci/hda/hda_intel.c
> > > @@ -1967,7 +1967,7 @@ static const struct pci_device_id azx_ids[] = {
> > >  	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
> > >  	/* Sunrise Point */
> > >  	{ PCI_DEVICE(0x8086, 0xa170),
> > > -	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
> > > +	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
> > >  	/* Sunrise Point-LP */
> > >  	{ PCI_DEVICE(0x8086, 0x9d70),
> > >  	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
> > > diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
> > > index e0c06f9a0e80..7f46d063af57 100644
> > > --- a/sound/pci/hda/patch_realtek.c
> > > +++ b/sound/pci/hda/patch_realtek.c
> > > @@ -396,7 +396,7 @@ static void alc_auto_setup_eapd(struct hda_codec *codec, bool on)
> > >  {
> > >  	/* We currently only handle front, HP */
> > >  	static hda_nid_t pins[] = {
> > > -		0x0f, 0x10, 0x14, 0x15, 0
> > > +		0x0f, 0x10, 0x14, 0x15, 0x17, 0
> > >  	};
> > >  	hda_nid_t *p;
> > >  	for (p = pins; *p; p++)
> > > @@ -2870,6 +2870,8 @@ static void alc283_init(struct hda_codec *codec)
> > >  
> > >  	if (!hp_pin)
> > >  		return;
> > > +
> > > +	msleep(30);
> > >  	hp_pin_sense = snd_hda_jack_detect(codec, hp_pin);
> > >  
> > >  	/* Index 0x43 Direct Drive HP AMP LPM Control 1 */
> > > @@ -3564,6 +3566,7 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec)
> > >  
> > >  	switch (codec->core.vendor_id) {
> > >  	case 0x10ec0255:
> > > +	case 0x10ec0256:
> > >  		alc_process_coef_fw(codec, coef0255);
> > >  		break;
> > >  	case 0x10ec0233:
> > > @@ -3619,6 +3622,7 @@ static void alc_headset_mode_mic_in(struct hda_codec *codec, hda_nid_t hp_pin,
> > >  
> > >  	switch (codec->core.vendor_id) {
> > >  	case 0x10ec0255:
> > > +	case 0x10ec0256:
> > >  		alc_write_coef_idx(codec, 0x45, 0xc489);
> > >  		snd_hda_set_pin_ctl_cache(codec, hp_pin, 0);
> > >  		alc_process_coef_fw(codec, coef0255);
> > > @@ -3688,6 +3692,7 @@ static void alc_headset_mode_default(struct hda_codec *codec)
> > >  
> > >  	switch (codec->core.vendor_id) {
> > >  	case 0x10ec0255:
> > > +	case 0x10ec0256:
> > >  		alc_process_coef_fw(codec, coef0255);
> > >  		break;
> > >  	case 0x10ec0233:
> > > @@ -3742,6 +3747,7 @@ static void alc_headset_mode_ctia(struct hda_codec *codec)
> > >  
> > >  	switch (codec->core.vendor_id) {
> > >  	case 0x10ec0255:
> > > +	case 0x10ec0256:
> > >  		alc_process_coef_fw(codec, coef0255);
> > >  		break;
> > >  	case 0x10ec0233:
> > > @@ -3796,6 +3802,7 @@ static void alc_headset_mode_omtp(struct hda_codec *codec)
> > >  
> > >  	switch (codec->core.vendor_id) {
> > >  	case 0x10ec0255:
> > > +	case 0x10ec0256:
> > >  		alc_process_coef_fw(codec, coef0255);
> > >  		break;
> > >  	case 0x10ec0233:
> > > @@ -3841,6 +3848,7 @@ static void alc_determine_headset_type(struct hda_codec *codec)
> > >  
> > >  	switch (codec->core.vendor_id) {
> > >  	case 0x10ec0255:
> > > +	case 0x10ec0256:
> > >  		alc_process_coef_fw(codec, coef0255);
> > >  		msleep(300);
> > >  		val = alc_read_coef_idx(codec, 0x46);
> > > @@ -4993,6 +5001,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
> > >  	SND_PCI_QUIRK(0x17aa, 0x501a, "Thinkpad", ALC283_FIXUP_INT_MIC),
> > >  	SND_PCI_QUIRK(0x17aa, 0x501e, "Thinkpad L440", ALC292_FIXUP_TPT440_DOCK),
> > >  	SND_PCI_QUIRK(0x17aa, 0x5026, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
> > > +	SND_PCI_QUIRK(0x17aa, 0x5036, "Thinkpad T450s", ALC292_FIXUP_TPT440_DOCK),
> > >  	SND_PCI_QUIRK(0x17aa, 0x5109, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
> > >  	SND_PCI_QUIRK(0x17aa, 0x3bf8, "Quanta FL1", ALC269_FIXUP_PCM_44K),
> > >  	SND_PCI_QUIRK(0x17aa, 0x9e54, "LENOVO NB", ALC269_FIXUP_LENOVO_EAPD),
> > > @@ -5173,6 +5182,16 @@ static const struct snd_hda_pin_quirk alc269_pin_fixup_tbl[] = {
> > >  		{0x17, 0x40000000},
> > >  		{0x1d, 0x40700001},
> > >  		{0x21, 0x02211050}),
> > > +	SND_HDA_PIN_QUIRK(0x10ec0256, 0x1028, "Dell", ALC255_FIXUP_DELL1_MIC_NO_PRESENCE,
> > > +		{0x12, 0x90a60140},
> > > +		{0x13, 0x40000000},
> > > +		{0x14, 0x90170110},
> > > +		{0x19, 0x411111f0},
> > > +		{0x1a, 0x411111f0},
> > > +		{0x1b, 0x411111f0},
> > > +		{0x1d, 0x40700001},
> > > +		{0x1e, 0x411111f0},
> > > +		{0x21, 0x02211020}),
> > >  	SND_HDA_PIN_QUIRK(0x10ec0280, 0x103c, "HP", ALC280_FIXUP_HP_GPIO4,
> > >  		{0x12, 0x90a60130},
> > >  		{0x13, 0x40000000},
> > > diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
> > > index 353532b8aee4..8f63e8c8b46c 100644
> > > --- a/sound/usb/quirks.c
> > > +++ b/sound/usb/quirks.c
> > > @@ -1113,8 +1113,13 @@ void snd_usb_set_format_quirk(struct snd_usb_substream *subs,
> > >  
> > >  bool snd_usb_get_sample_rate_quirk(struct snd_usb_audio *chip)
> > >  {
> > > -	/* MS Lifecam HD-5000 doesn't support reading the sample rate. */
> > > -	return chip->usb_id == USB_ID(0x045E, 0x076D);
> > > +	/* devices which do not support reading the sample rate. */
> > > +	switch (chip->usb_id) {
> > > +	case USB_ID(0x045E, 0x076D): /* MS Lifecam HD-5000 */
> > > +	case USB_ID(0x04D8, 0xFEEA): /* Benchmark DAC1 Pre */
> > > +		return true;
> > > +	}
> > > +	return false;
> > >  }
> > >  
> > >  /* Marantz/Denon USB DACs need a vendor cmd to switch
> > > 
> > 
> > 


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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Ville Syrjälä]

On Mon, Apr 13, 2015 at 12:43:14PM +0300, Mika Kahola wrote:
> On Fri, 2015-04-10 at 16:10 +0200, Takashi Iwai wrote:
> > At Fri, 10 Apr 2015 16:27:39 +0300,
> > Mika Kahola wrote:
> > > 
> > > On Thu, 2015-04-09 at 17:17 +0200, Takashi Iwai wrote:
> > > > At Thu, 9 Apr 2015 15:51:27 +0200,
> > > > Daniel Vetter wrote:
> > > > > 
> > > > > On Thu, Apr 09, 2015 at 04:41:26PM +0300, Mika Kahola wrote:
> > > > > > On Thu, 2015-04-09 at 11:32 +0200, Daniel Vetter wrote:
> > > > > > > On Thu, Apr 09, 2015 at 10:24:24AM +0300, Mika Kahola wrote:
> > > > > > > > I did some testing on audio part with HDMI-HDMI and DP-HDMI cables
> > > > > > > > connected to my Haswell box. Before applying the patch I tested as a
> > > > > > > > reference with the latest -nightly (04-08-2015), 4.0-rc7. Unfortunately,
> > > > > > > > I failed to get any audio over HDMI cable. For a reference I tested with
> > > > > > > > the very same setup the vanillla kernel from Linus tree 4.0-rc7 and with
> > > > > > > > that kernel the audio worked ok. Then I did some GIT bisecting and it
> > > > > > > > turned out that the first commit that I failed to get audio working was
> > > > > > > > aa2fee4286e43b4784982b17669b02cc99c1ae55.
> > > > > > > 
> > > > > > I rerun the bisecting and this time the result was
> > > > > > 
> > > > > > commit 0a599838737a2527c35e4d94f794aefe59df1781
> > > > > > Merge: 2d846c7 a59d719
> > > > > > Author: Takashi Iwai <tiwai@suse.de>
> > > > > > Date:   Wed Apr 8 11:29:56 2015 +0200
> > > > > > 
> > > > > >     Merge branch 'for-linus' into for-next
> > > > > >     
> > > > > >     Back merge HD-audio quirks to for-next branch, so that we can apply
> > > > > >     a couple of more quirks.
> > > > > >     
> > > > > >     Signed-off-by: Takashi Iwai <tiwai@suse.de>
> > > > > 
> > > > > Adding Takashi and intel audio folks.
> > > > 
> > > > The bisecting looks odd.  The commit you pointed is a back-merge from
> > > > 4.0-rc to next branch, so this merge itself shouldn't bring so many
> > > > stuff -- at least about the sound part.
> > > > 
> > > > The diff in sound/* is found below.  As you can see, the only change
> > > > relevant with HDMI is the chunk in sound/pci/hda/hda_intel.c for
> > > > HD-audio controller, but it's specific to Skylake, thus this must be
> > > > irrelevant with your hardware.
> > > > 
> > > > Please double-check.
> > > 
> > > I double-checked the bisecting and I ended up with the same result. You're
> > > right, it does seems odd why audio on my Haswell box stopped working.
> > > 
> > > Any ideas how to proceed from here?
> > 
> > Try to check whether the reverting the diff of sound/* manually fixes
> > the problem.  (i.e. apply diff -R for the diff I showed in the
> > previous mail.)
> > 
> > If it doesn't fix but still reverting the whole commit does fix, it
> > means that something else got broken by the merge.
> > 
> > 
> > Takashi
> > 
> 
> I reverted the diff but unfortunately there were no difference. 
> 
> For curiosity, I tested the audio with the latest -nightly and I got
> the audio working again. I wonder what has changed but it seems that
> the problem is now solved.

BTW we now have a WARN triggering on BSW due to hda trying to query
the current cdclk frequency.
https://bugs.freedesktop.org/show_bug.cgi?id=90012

I'm not sure if hda really needs to know the cdclk freq on BSW or not.
But in either case I think we should just kill the HAS_DDI check. Once
these patches land the code will anyway work on all platforms. Mika,
can you add that to your list of things to do on top of these patches?

> 
> -Mika-
> 
> > 
> > > 
> > > Cheers,
> > > Mika
> > > 
> > > 
> > > > thanks,
> > > > 
> > > > Takashi
> > > > 
> > > > ===
> > > > % git diff 0a599838737a2527c35e4d94f794aefe59df1781^..0a599838737a2527c35e4d94f794aefe59df1781 sound
> > > > diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
> > > > index 9bcc5457a83e..e1c210515581 100644
> > > > --- a/sound/pci/hda/hda_intel.c
> > > > +++ b/sound/pci/hda/hda_intel.c
> > > > @@ -1967,7 +1967,7 @@ static const struct pci_device_id azx_ids[] = {
> > > >  	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
> > > >  	/* Sunrise Point */
> > > >  	{ PCI_DEVICE(0x8086, 0xa170),
> > > > -	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
> > > > +	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
> > > >  	/* Sunrise Point-LP */
> > > >  	{ PCI_DEVICE(0x8086, 0x9d70),
> > > >  	  .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
> > > > diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
> > > > index e0c06f9a0e80..7f46d063af57 100644
> > > > --- a/sound/pci/hda/patch_realtek.c
> > > > +++ b/sound/pci/hda/patch_realtek.c
> > > > @@ -396,7 +396,7 @@ static void alc_auto_setup_eapd(struct hda_codec *codec, bool on)
> > > >  {
> > > >  	/* We currently only handle front, HP */
> > > >  	static hda_nid_t pins[] = {
> > > > -		0x0f, 0x10, 0x14, 0x15, 0
> > > > +		0x0f, 0x10, 0x14, 0x15, 0x17, 0
> > > >  	};
> > > >  	hda_nid_t *p;
> > > >  	for (p = pins; *p; p++)
> > > > @@ -2870,6 +2870,8 @@ static void alc283_init(struct hda_codec *codec)
> > > >  
> > > >  	if (!hp_pin)
> > > >  		return;
> > > > +
> > > > +	msleep(30);
> > > >  	hp_pin_sense = snd_hda_jack_detect(codec, hp_pin);
> > > >  
> > > >  	/* Index 0x43 Direct Drive HP AMP LPM Control 1 */
> > > > @@ -3564,6 +3566,7 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec)
> > > >  
> > > >  	switch (codec->core.vendor_id) {
> > > >  	case 0x10ec0255:
> > > > +	case 0x10ec0256:
> > > >  		alc_process_coef_fw(codec, coef0255);
> > > >  		break;
> > > >  	case 0x10ec0233:
> > > > @@ -3619,6 +3622,7 @@ static void alc_headset_mode_mic_in(struct hda_codec *codec, hda_nid_t hp_pin,
> > > >  
> > > >  	switch (codec->core.vendor_id) {
> > > >  	case 0x10ec0255:
> > > > +	case 0x10ec0256:
> > > >  		alc_write_coef_idx(codec, 0x45, 0xc489);
> > > >  		snd_hda_set_pin_ctl_cache(codec, hp_pin, 0);
> > > >  		alc_process_coef_fw(codec, coef0255);
> > > > @@ -3688,6 +3692,7 @@ static void alc_headset_mode_default(struct hda_codec *codec)
> > > >  
> > > >  	switch (codec->core.vendor_id) {
> > > >  	case 0x10ec0255:
> > > > +	case 0x10ec0256:
> > > >  		alc_process_coef_fw(codec, coef0255);
> > > >  		break;
> > > >  	case 0x10ec0233:
> > > > @@ -3742,6 +3747,7 @@ static void alc_headset_mode_ctia(struct hda_codec *codec)
> > > >  
> > > >  	switch (codec->core.vendor_id) {
> > > >  	case 0x10ec0255:
> > > > +	case 0x10ec0256:
> > > >  		alc_process_coef_fw(codec, coef0255);
> > > >  		break;
> > > >  	case 0x10ec0233:
> > > > @@ -3796,6 +3802,7 @@ static void alc_headset_mode_omtp(struct hda_codec *codec)
> > > >  
> > > >  	switch (codec->core.vendor_id) {
> > > >  	case 0x10ec0255:
> > > > +	case 0x10ec0256:
> > > >  		alc_process_coef_fw(codec, coef0255);
> > > >  		break;
> > > >  	case 0x10ec0233:
> > > > @@ -3841,6 +3848,7 @@ static void alc_determine_headset_type(struct hda_codec *codec)
> > > >  
> > > >  	switch (codec->core.vendor_id) {
> > > >  	case 0x10ec0255:
> > > > +	case 0x10ec0256:
> > > >  		alc_process_coef_fw(codec, coef0255);
> > > >  		msleep(300);
> > > >  		val = alc_read_coef_idx(codec, 0x46);
> > > > @@ -4993,6 +5001,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
> > > >  	SND_PCI_QUIRK(0x17aa, 0x501a, "Thinkpad", ALC283_FIXUP_INT_MIC),
> > > >  	SND_PCI_QUIRK(0x17aa, 0x501e, "Thinkpad L440", ALC292_FIXUP_TPT440_DOCK),
> > > >  	SND_PCI_QUIRK(0x17aa, 0x5026, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
> > > > +	SND_PCI_QUIRK(0x17aa, 0x5036, "Thinkpad T450s", ALC292_FIXUP_TPT440_DOCK),
> > > >  	SND_PCI_QUIRK(0x17aa, 0x5109, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
> > > >  	SND_PCI_QUIRK(0x17aa, 0x3bf8, "Quanta FL1", ALC269_FIXUP_PCM_44K),
> > > >  	SND_PCI_QUIRK(0x17aa, 0x9e54, "LENOVO NB", ALC269_FIXUP_LENOVO_EAPD),
> > > > @@ -5173,6 +5182,16 @@ static const struct snd_hda_pin_quirk alc269_pin_fixup_tbl[] = {
> > > >  		{0x17, 0x40000000},
> > > >  		{0x1d, 0x40700001},
> > > >  		{0x21, 0x02211050}),
> > > > +	SND_HDA_PIN_QUIRK(0x10ec0256, 0x1028, "Dell", ALC255_FIXUP_DELL1_MIC_NO_PRESENCE,
> > > > +		{0x12, 0x90a60140},
> > > > +		{0x13, 0x40000000},
> > > > +		{0x14, 0x90170110},
> > > > +		{0x19, 0x411111f0},
> > > > +		{0x1a, 0x411111f0},
> > > > +		{0x1b, 0x411111f0},
> > > > +		{0x1d, 0x40700001},
> > > > +		{0x1e, 0x411111f0},
> > > > +		{0x21, 0x02211020}),
> > > >  	SND_HDA_PIN_QUIRK(0x10ec0280, 0x103c, "HP", ALC280_FIXUP_HP_GPIO4,
> > > >  		{0x12, 0x90a60130},
> > > >  		{0x13, 0x40000000},
> > > > diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
> > > > index 353532b8aee4..8f63e8c8b46c 100644
> > > > --- a/sound/usb/quirks.c
> > > > +++ b/sound/usb/quirks.c
> > > > @@ -1113,8 +1113,13 @@ void snd_usb_set_format_quirk(struct snd_usb_substream *subs,
> > > >  
> > > >  bool snd_usb_get_sample_rate_quirk(struct snd_usb_audio *chip)
> > > >  {
> > > > -	/* MS Lifecam HD-5000 doesn't support reading the sample rate. */
> > > > -	return chip->usb_id == USB_ID(0x045E, 0x076D);
> > > > +	/* devices which do not support reading the sample rate. */
> > > > +	switch (chip->usb_id) {
> > > > +	case USB_ID(0x045E, 0x076D): /* MS Lifecam HD-5000 */
> > > > +	case USB_ID(0x04D8, 0xFEEA): /* Benchmark DAC1 Pre */
> > > > +		return true;
> > > > +	}
> > > > +	return false;
> > > >  }
> > > >  
> > > >  /* Marantz/Denon USB DACs need a vendor cmd to switch
> > > > 
> > > 
> > > 
> 
> 
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Mika Kahola]

I tested this patch with the audio in place. With this setup in my HSW
machine I can hear the pink noise played back with DP-HDMI cable
attatched.

speaker-test -c 2 -r 48000 -F S16_LE -t pink --device=plughw:0,7

Cheers,
Mika

On Tue, 2015-04-07 at 14:06 +0530, Sivakumar Thulasimani wrote:
> where can i check this (audio driver) ? since there was no need for them 
> to check CD clock value till now i don't think they will be doing it. 
> also this needs to be changed in Display Audio controller, so not sure 
> if audio driver has access to it in the first place. will be good to 
> confirm this before merging as it will break display audio if it is not 
> programmed.
> 
> if any one has setup this can be confirmed by just switching CD clock 
> after boot and playing an audio file.
> 
> regards,
> Sivakumar
> 
> On 4/7/2015 1:59 PM, Ville Syrjälä wrote:
> > On Tue, Apr 07, 2015 at 12:33:40PM +0530, Sivakumar Thulasimani wrote:
> >> sorry if i am missing something, HSW and BDW requires display audio
> >> controller to be updated with new values once CD clock is modified. how
> >> is this accomplished here ?
> > I'm hoping the audio driver will query the cdclk frequency after every
> > modeset.
> >
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx


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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Sivakumar Thulasimani]

Thanks for the update Mika. The issue will be that audio plays faster or 
slower than normal. i.e it will be < 1x or > 1x. can you confirm if 
audible sound plays after CD Clock change at 1x speed ?

regards,
Sivakumar
On 4/14/2015 12:06 PM, Mika Kahola wrote:
> I tested this patch with the audio in place. With this setup in my HSW
> machine I can hear the pink noise played back with DP-HDMI cable
> attatched.
>
> speaker-test -c 2 -r 48000 -F S16_LE -t pink --device=plughw:0,7
>
> Cheers,
> Mika
>
> On Tue, 2015-04-07 at 14:06 +0530, Sivakumar Thulasimani wrote:
>> where can i check this (audio driver) ? since there was no need for them
>> to check CD clock value till now i don't think they will be doing it.
>> also this needs to be changed in Display Audio controller, so not sure
>> if audio driver has access to it in the first place. will be good to
>> confirm this before merging as it will break display audio if it is not
>> programmed.
>>
>> if any one has setup this can be confirmed by just switching CD clock
>> after boot and playing an audio file.
>>
>> regards,
>> Sivakumar
>>
>> On 4/7/2015 1:59 PM, Ville Syrjälä wrote:
>>> On Tue, Apr 07, 2015 at 12:33:40PM +0530, Sivakumar Thulasimani wrote:
>>>> sorry if i am missing something, HSW and BDW requires display audio
>>>> controller to be updated with new values once CD clock is modified. how
>>>> is this accomplished here ?
>>> I'm hoping the audio driver will query the cdclk frequency after every
>>> modeset.
>>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>

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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Mika Kahola]

With pink noise you can't tell if the audio is played faster or slower.

I tested this by playing ITU speech codec test sample

aplay --device=plughw:0,7 male.wav

and audio played back on 1x speed.

Cheers,
Mika

On Tue, 2015-04-14 at 12:27 +0530, Sivakumar Thulasimani wrote:
> Thanks for the update Mika. The issue will be that audio plays faster or 
> slower than normal. i.e it will be < 1x or > 1x. can you confirm if 
> audible sound plays after CD Clock change at 1x speed ?
> 
> regards,
> Sivakumar
> On 4/14/2015 12:06 PM, Mika Kahola wrote:
> > I tested this patch with the audio in place. With this setup in my HSW
> > machine I can hear the pink noise played back with DP-HDMI cable
> > attatched.
> >
> > speaker-test -c 2 -r 48000 -F S16_LE -t pink --device=plughw:0,7
> >
> > Cheers,
> > Mika
> >
> > On Tue, 2015-04-07 at 14:06 +0530, Sivakumar Thulasimani wrote:
> >> where can i check this (audio driver) ? since there was no need for them
> >> to check CD clock value till now i don't think they will be doing it.
> >> also this needs to be changed in Display Audio controller, so not sure
> >> if audio driver has access to it in the first place. will be good to
> >> confirm this before merging as it will break display audio if it is not
> >> programmed.
> >>
> >> if any one has setup this can be confirmed by just switching CD clock
> >> after boot and playing an audio file.
> >>
> >> regards,
> >> Sivakumar
> >>
> >> On 4/7/2015 1:59 PM, Ville Syrjälä wrote:
> >>> On Tue, Apr 07, 2015 at 12:33:40PM +0530, Sivakumar Thulasimani wrote:
> >>>> sorry if i am missing something, HSW and BDW requires display audio
> >>>> controller to be updated with new values once CD clock is modified. how
> >>>> is this accomplished here ?
> >>> I'm hoping the audio driver will query the cdclk frequency after every
> >>> modeset.
> >>>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >
> >
> 


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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Sivakumar Thulasimani]

Thanks for the confirmation, Mika :). then this change is fine
not sure if it is still relevant but you can add rb if possible

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 4/14/2015 12:36 PM, Mika Kahola wrote:
> With pink noise you can't tell if the audio is played faster or slower.
>
> I tested this by playing ITU speech codec test sample
>
> aplay --device=plughw:0,7 male.wav
>
> and audio played back on 1x speed.
>
> Cheers,
> Mika
>
> On Tue, 2015-04-14 at 12:27 +0530, Sivakumar Thulasimani wrote:
>> Thanks for the update Mika. The issue will be that audio plays faster or
>> slower than normal. i.e it will be < 1x or > 1x. can you confirm if
>> audible sound plays after CD Clock change at 1x speed ?
>>
>> regards,
>> Sivakumar
>> On 4/14/2015 12:06 PM, Mika Kahola wrote:
>>> I tested this patch with the audio in place. With this setup in my HSW
>>> machine I can hear the pink noise played back with DP-HDMI cable
>>> attatched.
>>>
>>> speaker-test -c 2 -r 48000 -F S16_LE -t pink --device=plughw:0,7
>>>
>>> Cheers,
>>> Mika
>>>
>>> On Tue, 2015-04-07 at 14:06 +0530, Sivakumar Thulasimani wrote:
>>>> where can i check this (audio driver) ? since there was no need for them
>>>> to check CD clock value till now i don't think they will be doing it.
>>>> also this needs to be changed in Display Audio controller, so not sure
>>>> if audio driver has access to it in the first place. will be good to
>>>> confirm this before merging as it will break display audio if it is not
>>>> programmed.
>>>>
>>>> if any one has setup this can be confirmed by just switching CD clock
>>>> after boot and playing an audio file.
>>>>
>>>> regards,
>>>> Sivakumar
>>>>
>>>> On 4/7/2015 1:59 PM, Ville Syrjälä wrote:
>>>>> On Tue, Apr 07, 2015 at 12:33:40PM +0530, Sivakumar Thulasimani wrote:
>>>>>> sorry if i am missing something, HSW and BDW requires display audio
>>>>>> controller to be updated with new values once CD clock is modified. how
>>>>>> is this accomplished here ?
>>>>> I'm hoping the audio driver will query the cdclk frequency after every
>>>>> modeset.
>>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>
>>>
>
>
>

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Re: [PATCH 15/19] drm/i915: HSW cdclk support

[Ville Syrjälä]

On Tue, Apr 07, 2015 at 11:57:23AM +0530, Sivakumar Thulasimani wrote:
> 
> 
> On 3/31/2015 4:44 PM, Mika Kahola wrote:
> > Implement support for changing the cdclk frequency during runtime on
> > HSW. VLV/CHV already have support for this, so we can follow their
> > example for the most part. Only the actual hardware programming differs,
> > the rest is pretty much the same.
> >
> > The pipe pixel rate stuff is handled a bit differently for now due to
> > the difference in pch vs. gmch pfit handling. Eventually we should unify
> > that part to eliminate what is essentially duplicated code.
> >
> > v2: Grab rps.hw_lock around sandybridge_pcode_write()
> > v3: Rebase due to power well vs. .global_resources() reordering
> > v4: Rebase due to .global_resources() reordering for Haswell
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_reg.h      |   3 +
> >   drivers/gpu/drm/i915/intel_display.c | 161 ++++++++++++++++++++++++++++++++++-
> >   2 files changed, 161 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f26ebd2..b25f712 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6244,6 +6244,7 @@ enum skl_disp_power_wells {
> >   #define   GEN6_PCODE_WRITE_D_COMP		0x11
> >   #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
> >   #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
> > +#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
> >   #define   DISPLAY_IPS_CONTROL			0x19
> >   #define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
> >   #define GEN6_PCODE_DATA				0x138128
> > @@ -6698,10 +6699,12 @@ enum skl_disp_power_wells {
> >   #define  LCPLL_PLL_LOCK			(1<<30)
> >   #define  LCPLL_CLK_FREQ_MASK		(3<<26)
> >   #define  LCPLL_CLK_FREQ_450		(0<<26)
> > +#define  LCPLL_CLK_FREQ_ALT_HSW		(1<<26) /* 337.5 (ULX) or 540 */
> >   #define  LCPLL_CLK_FREQ_54O_BDW		(1<<26)
> >   #define  LCPLL_CLK_FREQ_337_5_BDW	(2<<26)
> >   #define  LCPLL_CLK_FREQ_675_BDW		(3<<26)
> >   #define  LCPLL_CD_CLOCK_DISABLE		(1<<25)
> > +#define  LCPLL_ROOT_CD_CLOCK_DISABLE	(1<<24)
> >   #define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
> >   #define  LCPLL_POWER_DOWN_ALLOW		(1<<22)
> >   #define  LCPLL_CD_SOURCE_FCLK		(1<<21)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 3752d5e..cce7103 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5012,7 +5012,16 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> >   {
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> >   
> > -	if (IS_VALLEYVIEW(dev)) {
> > +	if (IS_HASWELL(dev)) {
> > +		if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
> > +			dev_priv->max_cdclk_freq = 450000;
> > +		else if (IS_HSW_ULX(dev))
> > +			dev_priv->max_cdclk_freq = 337500;
> > +		else if (IS_HSW_ULT(dev))
> > +			dev_priv->max_cdclk_freq = 450000;
> > +		else
> > +			dev_priv->max_cdclk_freq = 540000;
> > +	} else if (IS_VALLEYVIEW(dev)) {
> >   		dev_priv->max_cdclk_freq = 400000;
> >   	} else {
> >   		/* otherwise assume cdclk is fixed */
> > @@ -8773,6 +8782,144 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv)
> >   	hsw_disable_lcpll(dev_priv, true, true);
> >   }
> >   
> > +/* compute the max rate for new configuration */
> > +static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
> > +{
> > +	struct drm_device *dev = dev_priv->dev;
> > +	struct intel_crtc *crtc;
> > +	int max_pixel_rate = 0;
> > +
> > +	for_each_intel_crtc(dev, crtc) {
> > +		if (crtc->new_enabled)
> > +			max_pixel_rate = max(max_pixel_rate,
> > +					     ilk_pipe_pixel_rate(crtc->new_config));
> > +	}
> > +
> > +	return max_pixel_rate;
> > +}
> > +
> > +static int haswell_calc_cdclk(struct drm_i915_private *dev_priv,
> > +			      int max_pixel_rate)
> > +{
> > +	int cdclk;
> > +
> > +	/*
> > +	 * FIXME should also account for plane ratio
> > +	 * once 64bpp pixel formats are supported.
> > +	 */
> > +	if (max_pixel_rate > 450000)
> > +		cdclk = 540000;
> > +	else if (max_pixel_rate > 337500 || !IS_HSW_ULX(dev_priv))
> > +		cdclk = 450000;
> > +	else
> > +		cdclk = 337500;
> > +
> > +	/*
> > +	 * FIXME move the cdclk caclulation to
> > +	 * compute_config() so we can fail gracegully.
> > +	 */
> > +	if (cdclk > dev_priv->max_cdclk_freq) {
> > +		DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> > +			  cdclk, dev_priv->max_cdclk_freq);
> > +		cdclk = dev_priv->max_cdclk_freq;
> > +	}
> > +
> > +	return cdclk;
> > +}
> won't this return 337MHz even for platforms that have HSW_CDCLK_LIMIT is 
> set ? this should return 450MHz if this fuse is set

I'm not sure ULX machines would ever have HSW_CDCLK_LIMIT set. But
having a check for it should do no harm so might as well I suppose.

-- 
Ville Syrjälä
Intel OTC
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[PATCH 16/19] drm/i915: Add IS_BDW_ULX

[Mika Kahola]

We need to tell BDW ULT and ULX apart.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 39b6042..c7f7808 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2326,6 +2326,9 @@ struct drm_i915_cmd_table {
 				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\
 				 (INTEL_DEVID(dev) & 0xf) == 0xb ||	\
 				 (INTEL_DEVID(dev) & 0xf) == 0xe))
+/* ULX machines are also considered ULT. */
+#define IS_BDW_ULX(dev)		(IS_BROADWELL(dev) && \
+				 (INTEL_DEVID(dev) & 0xf) == 0xe)
 #define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
 				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
 #define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \
-- 
1.9.1

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[PATCH 17/19] drm/i915: BDW clock change support

[Mika Kahola]

Add support for changing cdclk frequency during runtime on BDW. The
procedure is quite a bit different on BDW from the one on HSW, so
add a separate function for it.

Also with IPS enabled the actual pixel rate mustn't exceed 95% of cdclk,
so take that into account when computing the max pixel rate.

v2: Grab rps.hw_lock around sandybridge_pcode_write()
v3: Rebase due to power well vs. .global_resources() reordering
v4: Rebase due to .global_resources() reordering for BDW

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |   1 +
 drivers/gpu/drm/i915/intel_display.c | 140 ++++++++++++++++++++++++++++++-----
 2 files changed, 123 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b25f712..e8e6918 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6245,6 +6245,7 @@ enum skl_disp_power_wells {
 #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
 #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
 #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
+#define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
 #define   DISPLAY_IPS_CONTROL			0x19
 #define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
 #define GEN6_PCODE_DATA				0x138128
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cce7103..736df3e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5012,7 +5012,22 @@ static void intel_update_max_cdclk(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (IS_HASWELL(dev)) {
+	if (IS_BROADWELL(dev))  {
+		/*
+		 * FIXME with extra cooling we can allow
+		 * 540 MHz for ULX and 675 Mhz for ULT.
+		 * How can we know if extra cooling is
+		 * available? PCI ID, VTB, something else?
+		 */
+		if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
+			dev_priv->max_cdclk_freq = 450000;
+		else if (IS_BDW_ULX(dev))
+			dev_priv->max_cdclk_freq = 450000;
+		else if (IS_BDW_ULT(dev))
+			dev_priv->max_cdclk_freq = 540000;
+		else
+			dev_priv->max_cdclk_freq = 675000;
+	} else if (IS_HASWELL(dev)) {
 		if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 			dev_priv->max_cdclk_freq = 450000;
 		else if (IS_HSW_ULX(dev))
@@ -5838,13 +5853,11 @@ static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
 		return true;
 
 	/*
-	 * FIXME if we compare against max we should then
-	 * increase the cdclk frequency when the current
-	 * value is too low. The other option is to compare
-	 * against the cdclk frequency we're going have post
-	 * modeset (ie. one we computed using other constraints).
-	 * Need to measure whether using a lower cdclk w/o IPS
-	 * is better or worse than a higher cdclk w/ IPS.
+	 * We compare against max which means we must take
+	 * the increased cdclk requirement into account when
+	 * calculating the new cdclk.
+	 *
+	 * Should measure whether using a lower cdclk w/o IPS
 	 */
 	return ilk_pipe_pixel_rate(pipe_config) <=
 		dev_priv->max_cdclk_freq * 95 / 100;
@@ -8790,9 +8803,18 @@ static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
 	int max_pixel_rate = 0;
 
 	for_each_intel_crtc(dev, crtc) {
-		if (crtc->new_enabled)
-			max_pixel_rate = max(max_pixel_rate,
-					     ilk_pipe_pixel_rate(crtc->new_config));
+		int pixel_rate;
+
+		if (!crtc->new_enabled)
+			continue;
+
+		pixel_rate = ilk_pipe_pixel_rate(crtc->new_config);
+
+		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
+		if (IS_BROADWELL(dev) && crtc->new_config->ips_enabled)
+			pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
+
+		max_pixel_rate = max(max_pixel_rate, pixel_rate);
 	}
 
 	return max_pixel_rate;
@@ -8807,7 +8829,9 @@ static int haswell_calc_cdclk(struct drm_i915_private *dev_priv,
 	 * FIXME should also account for plane ratio
 	 * once 64bpp pixel formats are supported.
 	 */
-	if (max_pixel_rate > 450000)
+	if (max_pixel_rate > 540000)
+		cdclk = 675000;
+	else if (max_pixel_rate > 450000)
 		cdclk = 540000;
 	else if (max_pixel_rate > 337500 || !IS_HSW_ULX(dev_priv))
 		cdclk = 450000;
@@ -8872,6 +8896,83 @@ static void haswell_set_cdclk(struct drm_device *dev, int cdclk)
 	     cdclk, dev_priv->cdclk_freq);
 }
 
+static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t val, data;
+	int ret;
+
+	if (WARN((I915_READ(LCPLL_CTL) &
+		  (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
+		   LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
+		   LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
+		   LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
+		 "trying to change cdclk frequency with cdclk not enabled\n"))
+		return;
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+	ret = sandybridge_pcode_write(dev_priv,
+				      BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+	if (ret) {
+		DRM_ERROR("failed to inform pcode about cdclk change\n");
+		return;
+	}
+
+	val = I915_READ(LCPLL_CTL);
+	val |= LCPLL_CD_SOURCE_FCLK;
+	I915_WRITE(LCPLL_CTL, val);
+
+	if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
+			       LCPLL_CD_SOURCE_FCLK_DONE, 1))
+		DRM_ERROR("Switching to FCLK failed\n");
+
+	val = I915_READ(LCPLL_CTL);
+	val &= ~LCPLL_CLK_FREQ_MASK;
+
+	switch (cdclk) {
+	case 450000:
+		val |= LCPLL_CLK_FREQ_450;
+		data = 0;
+		break;
+	case 540000:
+		val |= LCPLL_CLK_FREQ_54O_BDW;
+		data = 1;
+		break;
+	case 337500:
+		val |= LCPLL_CLK_FREQ_337_5_BDW;
+		data = 2;
+		break;
+	case 675000:
+		val |= LCPLL_CLK_FREQ_675_BDW;
+		data = 3;
+		break;
+	default:
+	WARN(1, "invalid cdclk frequency\n");
+		return;
+	}
+
+	I915_WRITE(LCPLL_CTL, val);
+
+	val = I915_READ(LCPLL_CTL);
+	val &= ~LCPLL_CD_SOURCE_FCLK;
+	I915_WRITE(LCPLL_CTL, val);
+
+	if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
+				LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
+		DRM_ERROR("Switching back to LCPLL failed\n");
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+	sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+
+	intel_update_cdclk(dev);
+
+	WARN(cdclk != dev_priv->cdclk_freq,
+	     "cdclk requested %d kHz but got %d kHz\n",
+	     cdclk, dev_priv->cdclk_freq);
+}
+
 static void haswell_modeset_global_pipes(struct drm_device *dev,
 					 unsigned *prepare_pipes)
 {
@@ -8896,8 +8997,12 @@ static void haswell_modeset_global_resources(struct drm_atomic_state *state)
 	int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
 	int req_cdclk = haswell_calc_cdclk(dev_priv, max_pixel_rate);
 
-	if (req_cdclk != dev_priv->cdclk_freq)
-		haswell_set_cdclk(dev, req_cdclk);
+	if (req_cdclk != dev_priv->cdclk_freq) {
+		if (IS_BROADWELL(dev))
+			broadwell_set_cdclk(dev, req_cdclk);
+		else
+			haswell_set_cdclk(dev, req_cdclk);
+	}
 
 	if (req_cdclk != dev_priv->cdclk_freq) {
 		/*
@@ -12015,7 +12120,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
 	 * mode set on this crtc.  For other crtcs we need to use the
 	 * adjusted_mode bits in the crtc directly.
 	 */
-	if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev)) {
+	if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 		if (IS_VALLEYVIEW(dev))
 			valleyview_modeset_global_pipes(dev, &prepare_pipes);
 		else
@@ -14044,9 +14149,8 @@ static void intel_init_display(struct drm_device *dev)
 		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
 	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
-		if (IS_HASWELL(dev))
-			dev_priv->display.modeset_global_resources =
-				haswell_modeset_global_resources;
+		dev_priv->display.modeset_global_resources =
+			haswell_modeset_global_resources;
 	} else if (IS_VALLEYVIEW(dev)) {
 		dev_priv->display.modeset_global_resources =
 			valleyview_modeset_global_resources;
-- 
1.9.1

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[PATCH 18/19] drm/i915: Limit CHV max cdclk

[Mika Kahola]

Limit CHV maximum cdclk to 320MHz.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 736df3e..5ed40df 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5037,7 +5037,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
 		else
 			dev_priv->max_cdclk_freq = 540000;
 	} else if (IS_VALLEYVIEW(dev)) {
-		dev_priv->max_cdclk_freq = 400000;
+		dev_priv->max_cdclk_freq = IS_CHERRYVIEW(dev) ? 320000 : 400000;
 	} else {
 		/* otherwise assume cdclk is fixed */
 		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
-- 
1.9.1

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[PATCH 19/19] drm/i915: Modeset global_pipes() update

[Mika Kahola]

Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
into one function 'intel_modeset_global_pipes()'

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 89 +++++++++++++++++-------------------
 1 file changed, 41 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5ed40df..7180d2b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5209,38 +5209,6 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
 		return 200000;
 }
 
-/* compute the max pixel clock for new configuration */
-static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
-{
-	struct drm_device *dev = dev_priv->dev;
-	struct intel_crtc *intel_crtc;
-	int max_pixclk = 0;
-
-	for_each_intel_crtc(dev, intel_crtc) {
-		if (intel_crtc->new_enabled)
-			max_pixclk = max(max_pixclk,
-					 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
-	}
-
-	return max_pixclk;
-}
-
-static void valleyview_modeset_global_pipes(struct drm_device *dev,
-					    unsigned *prepare_pipes)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc;
-	int max_pixclk = intel_mode_max_pixclk(dev_priv);
-
-	if (valleyview_calc_cdclk(dev_priv, max_pixclk) == dev_priv->cdclk_freq)
-		return;
-
-	/* disable/enable all currently active pipes while we change cdclk */
-	for_each_intel_crtc(dev, intel_crtc)
-		if (intel_crtc->base.state->enable)
-			*prepare_pipes |= (1 << intel_crtc->pipe);
-}
-
 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 {
 	unsigned int credits, default_credits;
@@ -5277,6 +5245,22 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 	WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 }
 
+/* compute the max pixel clock for new configuration */
+static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+	struct intel_crtc *intel_crtc;
+	int max_pixclk = 0;
+
+	for_each_intel_crtc(dev, intel_crtc) {
+		if (intel_crtc->new_enabled)
+			max_pixclk = max(max_pixclk,
+					 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
+	}
+
+	return max_pixclk;
+}
+
 static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
 {
 	struct drm_device *dev = state->dev;
@@ -8973,21 +8957,38 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
 	     cdclk, dev_priv->cdclk_freq);
 }
 
-static void haswell_modeset_global_pipes(struct drm_device *dev,
-					 unsigned *prepare_pipes)
+static void intel_modeset_global_pipes(struct drm_device *dev,
+				       unsigned *prepare_pipes,
+				       unsigned *disable_pipes)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *crtc;
-	int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
+	int max_pixclk;
 
-	if (haswell_calc_cdclk(dev_priv, max_pixel_rate) ==
-	    dev_priv->cdclk_freq)
+	/* this modeset is valid only for VLV, HSW, and BDW */
+	if (!IS_VALLEYVIEW(dev) && !IS_HASWELL(dev) && !IS_BROADWELL(dev))
 		return;
 
+	if (IS_VALLEYVIEW(dev)) {
+		max_pixclk = intel_mode_max_pixclk(dev_priv);
+		if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
+		    dev_priv->cdclk_freq)
+			return;
+	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+		max_pixclk = ilk_max_pixel_rate(dev_priv);
+		if (haswell_calc_cdclk(dev_priv, max_pixclk) ==
+		    dev_priv->cdclk_freq)
+			return;
+
+	}
+
 	/* disable/enable all currently active pipes while we change cdclk */
 	for_each_intel_crtc(dev, crtc)
-		if (crtc->base.enabled)
-			*prepare_pipes |= 1 << crtc->pipe;
+		if (crtc->base.state->enable)
+			*prepare_pipes |= (1 << crtc->pipe);
+
+	/* may have added more to prepare_pipes than we should */
+	*prepare_pipes &= ~*disable_pipes;
 }
 
 static void haswell_modeset_global_resources(struct drm_atomic_state *state)
@@ -12120,15 +12121,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
 	 * mode set on this crtc.  For other crtcs we need to use the
 	 * adjusted_mode bits in the crtc directly.
 	 */
-	if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
-		if (IS_VALLEYVIEW(dev))
-			valleyview_modeset_global_pipes(dev, &prepare_pipes);
-		else
-			haswell_modeset_global_pipes(dev, &prepare_pipes);
-
-		/* may have added more to prepare_pipes than we should */
-		prepare_pipes &= ~disable_pipes;
-	}
+	intel_modeset_global_pipes(dev, &prepare_pipes, &disable_pipes);
 
 	ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
 	if (ret)
-- 
1.9.1

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Re: [PATCH 19/19] drm/i915: Modeset global_pipes() update

[Ville Syrjälä]

On Tue, Mar 31, 2015 at 02:14:23PM +0300, Mika Kahola wrote:
> Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
> into one function 'intel_modeset_global_pipes()'
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 89 +++++++++++++++++-------------------
>  1 file changed, 41 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5ed40df..7180d2b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5209,38 +5209,6 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>  		return 200000;
>  }
>  
> -/* compute the max pixel clock for new configuration */
> -static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
> -{
> -	struct drm_device *dev = dev_priv->dev;
> -	struct intel_crtc *intel_crtc;
> -	int max_pixclk = 0;
> -
> -	for_each_intel_crtc(dev, intel_crtc) {
> -		if (intel_crtc->new_enabled)
> -			max_pixclk = max(max_pixclk,
> -					 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
> -	}
> -
> -	return max_pixclk;
> -}
> -
> -static void valleyview_modeset_global_pipes(struct drm_device *dev,
> -					    unsigned *prepare_pipes)
> -{
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc;
> -	int max_pixclk = intel_mode_max_pixclk(dev_priv);
> -
> -	if (valleyview_calc_cdclk(dev_priv, max_pixclk) == dev_priv->cdclk_freq)
> -		return;
> -
> -	/* disable/enable all currently active pipes while we change cdclk */
> -	for_each_intel_crtc(dev, intel_crtc)
> -		if (intel_crtc->base.state->enable)
> -			*prepare_pipes |= (1 << intel_crtc->pipe);
> -}
> -
>  static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
>  {
>  	unsigned int credits, default_credits;
> @@ -5277,6 +5245,22 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
>  	WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
>  }
>  
> +/* compute the max pixel clock for new configuration */
> +static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
> +{
> +	struct drm_device *dev = dev_priv->dev;
> +	struct intel_crtc *intel_crtc;
> +	int max_pixclk = 0;
> +
> +	for_each_intel_crtc(dev, intel_crtc) {
> +		if (intel_crtc->new_enabled)
> +			max_pixclk = max(max_pixclk,
> +					 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
> +	}
> +
> +	return max_pixclk;
> +}
> +
>  static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
>  {
>  	struct drm_device *dev = state->dev;
> @@ -8973,21 +8957,38 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
>  	     cdclk, dev_priv->cdclk_freq);
>  }
>  
> -static void haswell_modeset_global_pipes(struct drm_device *dev,
> -					 unsigned *prepare_pipes)
> +static void intel_modeset_global_pipes(struct drm_device *dev,
> +				       unsigned *prepare_pipes,
> +				       unsigned *disable_pipes)

You don't modify disable_pipes, so no need to pass as pointer.

I do think passing disable_pipes into intel_modeset_global_pipes() does
make sense however, as it makes it clearer why we need to clear out the
disable_pipes when the code is all in one place like this.

>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *crtc;
> -	int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
> +	int max_pixclk;
>  
> -	if (haswell_calc_cdclk(dev_priv, max_pixel_rate) ==
> -	    dev_priv->cdclk_freq)
> +	/* this modeset is valid only for VLV, HSW, and BDW */
> +	if (!IS_VALLEYVIEW(dev) && !IS_HASWELL(dev) && !IS_BROADWELL(dev))
>  		return;
>  
> +	if (IS_VALLEYVIEW(dev)) {
> +		max_pixclk = intel_mode_max_pixclk(dev_priv);
> +		if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
> +		    dev_priv->cdclk_freq)
> +			return;
> +	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> +		max_pixclk = ilk_max_pixel_rate(dev_priv);
> +		if (haswell_calc_cdclk(dev_priv, max_pixclk) ==
> +		    dev_priv->cdclk_freq)
> +			return;
> +
> +	}

Maybe move the current vs. newly computed pixclk comparison out of
the if ladder, so we don't have to duplicate it for each platform?
It should also get rid of the ugly line length issue we have here.

Eventually we should get rid of the platform specifics here, but
that requires that we sort out the pfit pixel rate mess for all
platforms in the same way. Currently we just ignore the pfit
scaling ratio for gmch (and gen9 IIRC) platforms.

> +
>  	/* disable/enable all currently active pipes while we change cdclk */
>  	for_each_intel_crtc(dev, crtc)
> -		if (crtc->base.enabled)
> -			*prepare_pipes |= 1 << crtc->pipe;
> +		if (crtc->base.state->enable)
> +			*prepare_pipes |= (1 << crtc->pipe);
> +
> +	/* may have added more to prepare_pipes than we should */
> +	*prepare_pipes &= ~*disable_pipes;
>  }
>  
>  static void haswell_modeset_global_resources(struct drm_atomic_state *state)
> @@ -12120,15 +12121,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
>  	 * mode set on this crtc.  For other crtcs we need to use the
>  	 * adjusted_mode bits in the crtc directly.
>  	 */
> -	if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> -		if (IS_VALLEYVIEW(dev))
> -			valleyview_modeset_global_pipes(dev, &prepare_pipes);
> -		else
> -			haswell_modeset_global_pipes(dev, &prepare_pipes);
> -
> -		/* may have added more to prepare_pipes than we should */
> -		prepare_pipes &= ~disable_pipes;
> -	}
> +	intel_modeset_global_pipes(dev, &prepare_pipes, &disable_pipes);
>  
>  	ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
>  	if (ret)
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 19/19] drm/i915: Modeset global_pipes() update

[Mika Kahola]

On Tue, Mar 31, 2015 at 05:45:56PM +0300, Ville Syrjälä wrote:
> On Tue, Mar 31, 2015 at 02:14:23PM +0300, Mika Kahola wrote:
> > Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
> > into one function 'intel_modeset_global_pipes()'
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 89 +++++++++++++++++-------------------
> >  1 file changed, 41 insertions(+), 48 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 5ed40df..7180d2b 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5209,38 +5209,6 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> >  		return 200000;
> >  }
> >  
> > -/* compute the max pixel clock for new configuration */
> > -static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
> > -{
> > -	struct drm_device *dev = dev_priv->dev;
> > -	struct intel_crtc *intel_crtc;
> > -	int max_pixclk = 0;
> > -
> > -	for_each_intel_crtc(dev, intel_crtc) {
> > -		if (intel_crtc->new_enabled)
> > -			max_pixclk = max(max_pixclk,
> > -					 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
> > -	}
> > -
> > -	return max_pixclk;
> > -}
> > -
> > -static void valleyview_modeset_global_pipes(struct drm_device *dev,
> > -					    unsigned *prepare_pipes)
> > -{
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	struct intel_crtc *intel_crtc;
> > -	int max_pixclk = intel_mode_max_pixclk(dev_priv);
> > -
> > -	if (valleyview_calc_cdclk(dev_priv, max_pixclk) == dev_priv->cdclk_freq)
> > -		return;
> > -
> > -	/* disable/enable all currently active pipes while we change cdclk */
> > -	for_each_intel_crtc(dev, intel_crtc)
> > -		if (intel_crtc->base.state->enable)
> > -			*prepare_pipes |= (1 << intel_crtc->pipe);
> > -}
> > -
> >  static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
> >  {
> >  	unsigned int credits, default_credits;
> > @@ -5277,6 +5245,22 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
> >  	WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
> >  }
> >  
> > +/* compute the max pixel clock for new configuration */
> > +static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
> > +{
> > +	struct drm_device *dev = dev_priv->dev;
> > +	struct intel_crtc *intel_crtc;
> > +	int max_pixclk = 0;
> > +
> > +	for_each_intel_crtc(dev, intel_crtc) {
> > +		if (intel_crtc->new_enabled)
> > +			max_pixclk = max(max_pixclk,
> > +					 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
> > +	}
> > +
> > +	return max_pixclk;
> > +}
> > +
> >  static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
> >  {
> >  	struct drm_device *dev = state->dev;
> > @@ -8973,21 +8957,38 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
> >  	     cdclk, dev_priv->cdclk_freq);
> >  }
> >  
> > -static void haswell_modeset_global_pipes(struct drm_device *dev,
> > -					 unsigned *prepare_pipes)
> > +static void intel_modeset_global_pipes(struct drm_device *dev,
> > +				       unsigned *prepare_pipes,
> > +				       unsigned *disable_pipes)
> 
> You don't modify disable_pipes, so no need to pass as pointer.
> 
> I do think passing disable_pipes into intel_modeset_global_pipes() does
> make sense however, as it makes it clearer why we need to clear out the
> disable_pipes when the code is all in one place like this.
That's a good point.

> 
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct intel_crtc *crtc;
> > -	int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
> > +	int max_pixclk;
> >  
> > -	if (haswell_calc_cdclk(dev_priv, max_pixel_rate) ==
> > -	    dev_priv->cdclk_freq)
> > +	/* this modeset is valid only for VLV, HSW, and BDW */
> > +	if (!IS_VALLEYVIEW(dev) && !IS_HASWELL(dev) && !IS_BROADWELL(dev))
> >  		return;
> >  
> > +	if (IS_VALLEYVIEW(dev)) {
> > +		max_pixclk = intel_mode_max_pixclk(dev_priv);
> > +		if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
> > +		    dev_priv->cdclk_freq)
> > +			return;
> > +	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> > +		max_pixclk = ilk_max_pixel_rate(dev_priv);
> > +		if (haswell_calc_cdclk(dev_priv, max_pixclk) ==
> > +		    dev_priv->cdclk_freq)
> > +			return;
> > +
> > +	}
> 
> Maybe move the current vs. newly computed pixclk comparison out of
> the if ladder, so we don't have to duplicate it for each platform?
> It should also get rid of the ugly line length issue we have here.
> 
> Eventually we should get rid of the platform specifics here, but
> that requires that we sort out the pfit pixel rate mess for all
> platforms in the same way. Currently we just ignore the pfit
> scaling ratio for gmch (and gen9 IIRC) platforms.
Indeed, line break issue does look ugly. I throw a revised patch for this.

Thanks for the review!

> 
> > +
> >  	/* disable/enable all currently active pipes while we change cdclk */
> >  	for_each_intel_crtc(dev, crtc)
> > -		if (crtc->base.enabled)
> > -			*prepare_pipes |= 1 << crtc->pipe;
> > +		if (crtc->base.state->enable)
> > +			*prepare_pipes |= (1 << crtc->pipe);
> > +
> > +	/* may have added more to prepare_pipes than we should */
> > +	*prepare_pipes &= ~*disable_pipes;
> >  }
> >  
> >  static void haswell_modeset_global_resources(struct drm_atomic_state *state)
> > @@ -12120,15 +12121,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
> >  	 * mode set on this crtc.  For other crtcs we need to use the
> >  	 * adjusted_mode bits in the crtc directly.
> >  	 */
> > -	if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> > -		if (IS_VALLEYVIEW(dev))
> > -			valleyview_modeset_global_pipes(dev, &prepare_pipes);
> > -		else
> > -			haswell_modeset_global_pipes(dev, &prepare_pipes);
> > -
> > -		/* may have added more to prepare_pipes than we should */
> > -		prepare_pipes &= ~disable_pipes;
> > -	}
> > +	intel_modeset_global_pipes(dev, &prepare_pipes, &disable_pipes);
> >  
> >  	ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
> >  	if (ret)
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Mika Kahola, Intel OTC
_______________________________________________
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[PATCH 19/19] drm/i915: Modeset global_pipes() update

[Mika Kahola]

Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
into one function 'intel_modeset_global_pipes()'

v2:
- we don't modify 'disable_pipes', so passing this as a pointer
  is removed (based on Ville's comment)
- introduced a new function 'intel_calc_cdclk()' that combines
  routines from 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()'

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 191 ++++++++++++++++-------------------
 1 file changed, 88 insertions(+), 103 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7b97907..18a1262 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5179,66 +5179,62 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
 	intel_update_cdclk(dev);
 }
 
-static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
+static int intel_calc_cdclk(struct drm_i915_private *dev_priv,
 				 int max_pixclk)
 {
-	int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
-	int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
+	int cdclk = 200000;
 
-	/*
-	 * Really only a few cases to deal with, as only 4 CDclks are supported:
-	 *   200MHz
-	 *   267MHz
-	 *   320/333MHz (depends on HPLL freq)
-	 *   400MHz (VLV only)
-	 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
-	 * of the lower bin and adjust if needed.
-	 *
-	 * We seem to get an unstable or solid color picture at 200MHz.
-	 * Not sure what's wrong. For now use 200MHz only when all pipes
-	 * are off.
-	 */
-	if (!IS_CHERRYVIEW(dev_priv) &&
-	    max_pixclk > freq_320*limit/100)
-		return 400000;
-	else if (max_pixclk > 266667*limit/100)
-		return freq_320;
-	else if (max_pixclk > 0)
-		return 266667;
-	else
-		return 200000;
-}
-
-/* compute the max pixel clock for new configuration */
-static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
-{
-	struct drm_device *dev = dev_priv->dev;
-	struct intel_crtc *intel_crtc;
-	int max_pixclk = 0;
+	if (IS_VALLEYVIEW(dev_priv)) {
+		int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
+		int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
+		/*
+		 * Really only a few cases to deal with, as only 4 CDclks are supported:
+		 *   200MHz
+		 *   267MHz
+		 *   320/333MHz (depends on HPLL freq)
+		 *   400MHz (VLV only)
+		 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
+		 * of the lower bin and adjust if needed.
+		 *
+		 * We seem to get an unstable or solid color picture at 200MHz.
+		 * Not sure what's wrong. For now use 200MHz only when all pipes
+		 * are off.
+		 */
+		if (!IS_CHERRYVIEW(dev_priv) &&
+		    max_pixclk > freq_320*limit/100)
+			cdclk = 400000;
+		else if (max_pixclk > 266667*limit/100)
+			cdclk = freq_320;
+		else if (max_pixclk > 0)
+			cdclk = 266667;
+		else
+			cdclk = 200000;
+	} else if (IS_HASWELL(dev_priv)) {
+		/*
+		 * FIXME should also account for plane ratio
+		 * once 64bpp pixel formats are supported.
+		 */
+		if (max_pixclk > 540000)
+			cdclk = 675000;
+		else if (max_pixclk > 450000)
+			cdclk = 540000;
+		else if (max_pixclk > 337500 || !IS_HSW_ULX(dev_priv))
+			cdclk = 450000;
+		else
+			cdclk = 337500;
 
-	for_each_intel_crtc(dev, intel_crtc) {
-		if (intel_crtc->new_enabled)
-			max_pixclk = max(max_pixclk,
-					 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
+		/*
+		 * FIXME move the cdclk caclulation to
+		 * compute_config() so we can fail gracegully.
+		 */
+		if (cdclk > dev_priv->max_cdclk_freq) {
+			DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
+				  cdclk, dev_priv->max_cdclk_freq);
+			cdclk = dev_priv->max_cdclk_freq;
+		}
 	}
 
-	return max_pixclk;
-}
-
-static void valleyview_modeset_global_pipes(struct drm_device *dev,
-					    unsigned *prepare_pipes)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc;
-	int max_pixclk = intel_mode_max_pixclk(dev_priv);
-
-	if (valleyview_calc_cdclk(dev_priv, max_pixclk) == dev_priv->cdclk_freq)
-		return;
-
-	/* disable/enable all currently active pipes while we change cdclk */
-	for_each_intel_crtc(dev, intel_crtc)
-		if (intel_crtc->base.state->enable)
-			*prepare_pipes |= (1 << intel_crtc->pipe);
+	return cdclk;
 }
 
 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
@@ -5277,12 +5273,28 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 	WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 }
 
+/* compute the max pixel clock for new configuration */
+static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = dev_priv->dev;
+	struct intel_crtc *intel_crtc;
+	int max_pixclk = 0;
+
+	for_each_intel_crtc(dev, intel_crtc) {
+		if (intel_crtc->new_enabled)
+			max_pixclk = max(max_pixclk,
+					 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
+	}
+
+	return max_pixclk;
+}
+
 static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
 {
 	struct drm_device *dev = state->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int max_pixclk = intel_mode_max_pixclk(dev_priv);
-	int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
+	int req_cdclk = intel_calc_cdclk(dev_priv, max_pixclk);
 
 	if (req_cdclk != dev_priv->cdclk_freq) {
 		/*
@@ -8634,37 +8646,6 @@ static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
 	return max_pixel_rate;
 }
 
-static int haswell_calc_cdclk(struct drm_i915_private *dev_priv,
-			      int max_pixel_rate)
-{
-	int cdclk;
-
-	/*
-	 * FIXME should also account for plane ratio
-	 * once 64bpp pixel formats are supported.
-	 */
-	if (max_pixel_rate > 540000)
-		cdclk = 675000;
-	else if (max_pixel_rate > 450000)
-		cdclk = 540000;
-	else if (max_pixel_rate > 337500 || !IS_HSW_ULX(dev_priv))
-		cdclk = 450000;
-	else
-		cdclk = 337500;
-
-	/*
-	 * FIXME move the cdclk caclulation to
-	 * compute_config() so we can fail gracegully.
-	 */
-	if (cdclk > dev_priv->max_cdclk_freq) {
-		DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
-			  cdclk, dev_priv->max_cdclk_freq);
-		cdclk = dev_priv->max_cdclk_freq;
-	}
-
-	return cdclk;
-}
-
 static void haswell_set_cdclk(struct drm_device *dev, int cdclk)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8787,21 +8768,33 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
 	     cdclk, dev_priv->cdclk_freq);
 }
 
-static void haswell_modeset_global_pipes(struct drm_device *dev,
-					 unsigned *prepare_pipes)
+static void intel_modeset_global_pipes(struct drm_device *dev,
+				       unsigned *prepare_pipes,
+				       unsigned disable_pipes)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *crtc;
-	int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
+	int max_pixclk;
+
+	/* this modeset is valid only for VLV, HSW, and BDW */
+	if (!IS_VALLEYVIEW(dev) && !IS_HASWELL(dev) && !IS_BROADWELL(dev))
+		return;
+
+	if (IS_VALLEYVIEW(dev))
+		max_pixclk = intel_mode_max_pixclk(dev_priv);
+	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		max_pixclk = ilk_max_pixel_rate(dev_priv);
 
-	if (haswell_calc_cdclk(dev_priv, max_pixel_rate) ==
-	    dev_priv->cdclk_freq)
+	if (intel_calc_cdclk(dev_priv, max_pixclk) == dev_priv->cdclk_freq)
 		return;
 
 	/* disable/enable all currently active pipes while we change cdclk */
 	for_each_intel_crtc(dev, crtc)
-		if (crtc->base.enabled)
-			*prepare_pipes |= 1 << crtc->pipe;
+		if (crtc->base.state->enable)
+			*prepare_pipes |= (1 << crtc->pipe);
+
+	/* may have added more to prepare_pipes than we should */
+	*prepare_pipes &= ~disable_pipes;
 }
 
 static void haswell_modeset_global_resources(struct drm_atomic_state *state)
@@ -8809,7 +8802,7 @@ static void haswell_modeset_global_resources(struct drm_atomic_state *state)
 	struct drm_device *dev = state->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
-	int req_cdclk = haswell_calc_cdclk(dev_priv, max_pixel_rate);
+	int req_cdclk = intel_calc_cdclk(dev_priv, max_pixel_rate);
 
 	if (req_cdclk != dev_priv->cdclk_freq) {
 		if (IS_BROADWELL(dev))
@@ -11933,15 +11926,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
 	 * mode set on this crtc.  For other crtcs we need to use the
 	 * adjusted_mode bits in the crtc directly.
 	 */
-	if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
-		if (IS_VALLEYVIEW(dev))
-			valleyview_modeset_global_pipes(dev, &prepare_pipes);
-		else
-			haswell_modeset_global_pipes(dev, &prepare_pipes);
-
-		/* may have added more to prepare_pipes than we should */
-		prepare_pipes &= ~disable_pipes;
-	}
+	intel_modeset_global_pipes(dev, &prepare_pipes, disable_pipes);
 
 	ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
 	if (ret)
-- 
1.9.1

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Re: [PATCH 19/19] drm/i915: Modeset global_pipes() update

[Ville Syrjälä]

On Thu, Apr 02, 2015 at 01:05:31PM +0300, Mika Kahola wrote:
> Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
> into one function 'intel_modeset_global_pipes()'
> 
> v2:
> - we don't modify 'disable_pipes', so passing this as a pointer
>   is removed (based on Ville's comment)
> - introduced a new function 'intel_calc_cdclk()' that combines
>   routines from 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()'
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 191 ++++++++++++++++-------------------
>  1 file changed, 88 insertions(+), 103 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7b97907..18a1262 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5179,66 +5179,62 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
>  	intel_update_cdclk(dev);
>  }
>  
> -static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> +static int intel_calc_cdclk(struct drm_i915_private *dev_priv,
>  				 int max_pixclk)
>  {
> -	int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
> -	int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
> +	int cdclk = 200000;
>  
> -	/*
> -	 * Really only a few cases to deal with, as only 4 CDclks are supported:
> -	 *   200MHz
> -	 *   267MHz
> -	 *   320/333MHz (depends on HPLL freq)
> -	 *   400MHz (VLV only)
> -	 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
> -	 * of the lower bin and adjust if needed.
> -	 *
> -	 * We seem to get an unstable or solid color picture at 200MHz.
> -	 * Not sure what's wrong. For now use 200MHz only when all pipes
> -	 * are off.
> -	 */
> -	if (!IS_CHERRYVIEW(dev_priv) &&
> -	    max_pixclk > freq_320*limit/100)
> -		return 400000;
> -	else if (max_pixclk > 266667*limit/100)
> -		return freq_320;
> -	else if (max_pixclk > 0)
> -		return 266667;
> -	else
> -		return 200000;
> -}

I'd leave the valleyview_calc_cdclk() and haswell_calc_cdclk() alone.
Stuffing them into a single function makes the patch quite ugly. Also
I suppose we might want to turn it into a vfunc in the future and
having separate funcs for different platforms would make that easier.

> -
> -/* compute the max pixel clock for new configuration */
> -static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
> -{
> -	struct drm_device *dev = dev_priv->dev;
> -	struct intel_crtc *intel_crtc;
> -	int max_pixclk = 0;
> +	if (IS_VALLEYVIEW(dev_priv)) {
> +		int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
> +		int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
> +		/*
> +		 * Really only a few cases to deal with, as only 4 CDclks are supported:
> +		 *   200MHz
> +		 *   267MHz
> +		 *   320/333MHz (depends on HPLL freq)
> +		 *   400MHz (VLV only)
> +		 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
> +		 * of the lower bin and adjust if needed.
> +		 *
> +		 * We seem to get an unstable or solid color picture at 200MHz.
> +		 * Not sure what's wrong. For now use 200MHz only when all pipes
> +		 * are off.
> +		 */
> +		if (!IS_CHERRYVIEW(dev_priv) &&
> +		    max_pixclk > freq_320*limit/100)
> +			cdclk = 400000;
> +		else if (max_pixclk > 266667*limit/100)
> +			cdclk = freq_320;
> +		else if (max_pixclk > 0)
> +			cdclk = 266667;
> +		else
> +			cdclk = 200000;
> +	} else if (IS_HASWELL(dev_priv)) {
> +		/*
> +		 * FIXME should also account for plane ratio
> +		 * once 64bpp pixel formats are supported.
> +		 */
> +		if (max_pixclk > 540000)
> +			cdclk = 675000;
> +		else if (max_pixclk > 450000)
> +			cdclk = 540000;
> +		else if (max_pixclk > 337500 || !IS_HSW_ULX(dev_priv))
> +			cdclk = 450000;
> +		else
> +			cdclk = 337500;
>  
> -	for_each_intel_crtc(dev, intel_crtc) {
> -		if (intel_crtc->new_enabled)
> -			max_pixclk = max(max_pixclk,
> -					 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
> +		/*
> +		 * FIXME move the cdclk caclulation to
> +		 * compute_config() so we can fail gracegully.
> +		 */
> +		if (cdclk > dev_priv->max_cdclk_freq) {
> +			DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> +				  cdclk, dev_priv->max_cdclk_freq);
> +			cdclk = dev_priv->max_cdclk_freq;
> +		}
>  	}
>  
> -	return max_pixclk;
> -}
> -
> -static void valleyview_modeset_global_pipes(struct drm_device *dev,
> -					    unsigned *prepare_pipes)
> -{
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc;
> -	int max_pixclk = intel_mode_max_pixclk(dev_priv);
> -
> -	if (valleyview_calc_cdclk(dev_priv, max_pixclk) == dev_priv->cdclk_freq)
> -		return;
> -
> -	/* disable/enable all currently active pipes while we change cdclk */
> -	for_each_intel_crtc(dev, intel_crtc)
> -		if (intel_crtc->base.state->enable)
> -			*prepare_pipes |= (1 << intel_crtc->pipe);
> +	return cdclk;
>  }
>  
>  static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
> @@ -5277,12 +5273,28 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
>  	WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
>  }
>  
> +/* compute the max pixel clock for new configuration */
> +static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
> +{
> +	struct drm_device *dev = dev_priv->dev;
> +	struct intel_crtc *intel_crtc;
> +	int max_pixclk = 0;
> +
> +	for_each_intel_crtc(dev, intel_crtc) {
> +		if (intel_crtc->new_enabled)
> +			max_pixclk = max(max_pixclk,
> +					 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
> +	}
> +
> +	return max_pixclk;
> +}
> +
>  static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
>  {
>  	struct drm_device *dev = state->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int max_pixclk = intel_mode_max_pixclk(dev_priv);
> -	int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
> +	int req_cdclk = intel_calc_cdclk(dev_priv, max_pixclk);
>  
>  	if (req_cdclk != dev_priv->cdclk_freq) {
>  		/*
> @@ -8634,37 +8646,6 @@ static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
>  	return max_pixel_rate;
>  }
>  
> -static int haswell_calc_cdclk(struct drm_i915_private *dev_priv,
> -			      int max_pixel_rate)
> -{
> -	int cdclk;
> -
> -	/*
> -	 * FIXME should also account for plane ratio
> -	 * once 64bpp pixel formats are supported.
> -	 */
> -	if (max_pixel_rate > 540000)
> -		cdclk = 675000;
> -	else if (max_pixel_rate > 450000)
> -		cdclk = 540000;
> -	else if (max_pixel_rate > 337500 || !IS_HSW_ULX(dev_priv))
> -		cdclk = 450000;
> -	else
> -		cdclk = 337500;
> -
> -	/*
> -	 * FIXME move the cdclk caclulation to
> -	 * compute_config() so we can fail gracegully.
> -	 */
> -	if (cdclk > dev_priv->max_cdclk_freq) {
> -		DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> -			  cdclk, dev_priv->max_cdclk_freq);
> -		cdclk = dev_priv->max_cdclk_freq;
> -	}
> -
> -	return cdclk;
> -}
> -
>  static void haswell_set_cdclk(struct drm_device *dev, int cdclk)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -8787,21 +8768,33 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
>  	     cdclk, dev_priv->cdclk_freq);
>  }
>  
> -static void haswell_modeset_global_pipes(struct drm_device *dev,
> -					 unsigned *prepare_pipes)
> +static void intel_modeset_global_pipes(struct drm_device *dev,
> +				       unsigned *prepare_pipes,
> +				       unsigned disable_pipes)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *crtc;
> -	int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
> +	int max_pixclk;
> +
> +	/* this modeset is valid only for VLV, HSW, and BDW */
> +	if (!IS_VALLEYVIEW(dev) && !IS_HASWELL(dev) && !IS_BROADWELL(dev))
> +		return;
> +
> +	if (IS_VALLEYVIEW(dev))
> +		max_pixclk = intel_mode_max_pixclk(dev_priv);
> +	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> +		max_pixclk = ilk_max_pixel_rate(dev_priv);
>  
> -	if (haswell_calc_cdclk(dev_priv, max_pixel_rate) ==
> -	    dev_priv->cdclk_freq)
> +	if (intel_calc_cdclk(dev_priv, max_pixclk) == dev_priv->cdclk_freq)
>  		return;
>  
>  	/* disable/enable all currently active pipes while we change cdclk */
>  	for_each_intel_crtc(dev, crtc)
> -		if (crtc->base.enabled)
> -			*prepare_pipes |= 1 << crtc->pipe;
> +		if (crtc->base.state->enable)
> +			*prepare_pipes |= (1 << crtc->pipe);
> +
> +	/* may have added more to prepare_pipes than we should */
> +	*prepare_pipes &= ~disable_pipes;
>  }
>  
>  static void haswell_modeset_global_resources(struct drm_atomic_state *state)
> @@ -8809,7 +8802,7 @@ static void haswell_modeset_global_resources(struct drm_atomic_state *state)
>  	struct drm_device *dev = state->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
> -	int req_cdclk = haswell_calc_cdclk(dev_priv, max_pixel_rate);
> +	int req_cdclk = intel_calc_cdclk(dev_priv, max_pixel_rate);
>  
>  	if (req_cdclk != dev_priv->cdclk_freq) {
>  		if (IS_BROADWELL(dev))
> @@ -11933,15 +11926,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
>  	 * mode set on this crtc.  For other crtcs we need to use the
>  	 * adjusted_mode bits in the crtc directly.
>  	 */
> -	if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> -		if (IS_VALLEYVIEW(dev))
> -			valleyview_modeset_global_pipes(dev, &prepare_pipes);
> -		else
> -			haswell_modeset_global_pipes(dev, &prepare_pipes);
> -
> -		/* may have added more to prepare_pipes than we should */
> -		prepare_pipes &= ~disable_pipes;
> -	}
> +	intel_modeset_global_pipes(dev, &prepare_pipes, disable_pipes);
>  
>  	ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
>  	if (ret)
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[PATCH 19/19] drm/i915: Modeset global_pipes() update

[Mika Kahola]

Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
into one function 'intel_modeset_global_pipes()'

v2:
- we don't modify 'disable_pipes', so passing this as a pointer
  is removed (based on Ville's comment)
- introduced a new function 'intel_calc_cdclk()' that combines
  routines from 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()'

v3:
- Let's take a step back and not remove the routines 'valleyview_calc_cdclk()'
  and 'haswell_calc_cdclk()' from newly introduced routine
  'intel_calc_cdclk()' (based on Ville's comment)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 63 ++++++++++++++++++------------------
 1 file changed, 32 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7b97907..f05bd12 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5225,22 +5225,6 @@ static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
 	return max_pixclk;
 }
 
-static void valleyview_modeset_global_pipes(struct drm_device *dev,
-					    unsigned *prepare_pipes)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc;
-	int max_pixclk = intel_mode_max_pixclk(dev_priv);
-
-	if (valleyview_calc_cdclk(dev_priv, max_pixclk) == dev_priv->cdclk_freq)
-		return;
-
-	/* disable/enable all currently active pipes while we change cdclk */
-	for_each_intel_crtc(dev, intel_crtc)
-		if (intel_crtc->base.state->enable)
-			*prepare_pipes |= (1 << intel_crtc->pipe);
-}
-
 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 {
 	unsigned int credits, default_credits;
@@ -8787,21 +8771,46 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
 	     cdclk, dev_priv->cdclk_freq);
 }
 
-static void haswell_modeset_global_pipes(struct drm_device *dev,
-					 unsigned *prepare_pipes)
+static int intel_calc_cdclk(struct drm_device *dev, int max_pixclk)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int cdclk;
+
+	if (IS_VALLEYVIEW(dev))
+		cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
+	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		cdclk = haswell_calc_cdclk(dev_priv, max_pixclk);
+
+	return cdclk;
+}
+
+static void intel_modeset_global_pipes(struct drm_device *dev,
+				       unsigned *prepare_pipes,
+				       unsigned disable_pipes)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *crtc;
-	int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
+	int max_pixclk;
 
-	if (haswell_calc_cdclk(dev_priv, max_pixel_rate) ==
-	    dev_priv->cdclk_freq)
+       /* this modeset is valid only for VLV, HSW, and BDW */
+	if (!IS_VALLEYVIEW(dev) && !IS_HASWELL(dev) && !IS_BROADWELL(dev))
+		return;
+
+	if (IS_VALLEYVIEW(dev))
+		max_pixclk = intel_mode_max_pixclk(dev_priv);
+	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		max_pixclk = ilk_max_pixel_rate(dev_priv);
+
+	if (intel_calc_cdclk(dev, max_pixclk) == dev_priv->cdclk_freq)
 		return;
 
 	/* disable/enable all currently active pipes while we change cdclk */
 	for_each_intel_crtc(dev, crtc)
-		if (crtc->base.enabled)
+		if (crtc->base.state->enable)
 			*prepare_pipes |= 1 << crtc->pipe;
+
+       /* may have added more to prepare_pipes than we should */
+	*prepare_pipes &= ~disable_pipes;
 }
 
 static void haswell_modeset_global_resources(struct drm_atomic_state *state)
@@ -11933,15 +11942,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
 	 * mode set on this crtc.  For other crtcs we need to use the
 	 * adjusted_mode bits in the crtc directly.
 	 */
-	if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
-		if (IS_VALLEYVIEW(dev))
-			valleyview_modeset_global_pipes(dev, &prepare_pipes);
-		else
-			haswell_modeset_global_pipes(dev, &prepare_pipes);
-
-		/* may have added more to prepare_pipes than we should */
-		prepare_pipes &= ~disable_pipes;
-	}
+	intel_modeset_global_pipes(dev, &prepare_pipes, disable_pipes);
 
 	ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
 	if (ret)
-- 
1.9.1

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Re: All sort of cdclk stuff

[Damien Lespiau]

On Tue, Mar 31, 2015 at 02:05:35PM +0300, Mika Kahola wrote:
> This patch series rebases Ville's original cdclk patch series
> 
> http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html
> 
> The patches include modifications to

For some reason, I haven't received all the patches listed there... and
it seems I'm not the only one:

  http://patchwork.lespiau.name/series/1293/

Patches 03 and 09 and MIA.

-- 
Damien

> 
>   drm/i915: Return more precise cdclk for gen2/3
>   drm/i915: Fix i855_get_display_clock_speed()
>   drm/i915: Fix 852GM/GMV cdclk
>   drm/i915: Add cdclk extraction for g33, 965gm and g4x
>   drm/i915: ILK cdclk seems to be 450MHz
>   drm/i915: Assume 400 MHz cdclk for the rest of gen4-7
>   drm/i915: Simplify ilk_get_aux_clock_divider()
>   drm/i915: Convert the ddi cdclk code to .get_display_clock_speed()
>   drm/i915: Warn when cdclk for the platforms is not known
>   drm/i915: Cache the current cdclk frequency in dev_priv
>   drm/i915: Use cached cdclk value
>   drm/i915: Unify ilk and hsw .get_aux_clock_divider()
>   drm/i915: Store max cdclk value in dev_priv
>   drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk
>   drm/i915: Fix chv cdclk support
>   drm/i915: HSW cdclk change support
>   drm/i915: Add IS_BDW_ULX()
>   drm/i915: BDW cdclk change support
>   drm/i915: Limit CHV max cdclk to 320 MHz
>   drm/i915: Combined VLV, HSW, and BDW global pipe conf into single function
>             'intel_modeset_global_pipes()'
> 
> -- 
> Mika Kahola, Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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