From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: laurent.desnogues@gmail.com, serge.fdrv@gmail.com,
edgar.iglesias@xilinx.com, alex.bennee@linaro.org, agraf@suse.de
Subject: [Qemu-devel] [PATCH v3 7/9] target-arm: Add S2 translation to 32bit S1 PTWs
Date: Sat, 3 Oct 2015 15:38:57 -0700 [thread overview]
Message-ID: <1443911939-2825-8-git-send-email-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <1443911939-2825-1-git-send-email-edgar.iglesias@gmail.com>
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add support for applying S2 translation to 32bit S1
page-table walks.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target-arm/helper.c | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index fca2aef..c108248 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6182,11 +6182,19 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
* was being done for a CPU load/store or an address translation instruction
* (but not if it was for a debug access).
*/
-static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure)
+static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
+ ARMMMUIdx mmu_idx, uint32_t *fsr,
+ ARMMMUFaultInfo *fi)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
MemTxAttrs attrs = {};
attrs.secure = is_secure;
+ addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
+ if (fi->s1ptw) {
+ return 0;
+ }
return address_space_ldl(cs->as, addr, attrs, NULL);
}
@@ -6230,7 +6238,8 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
code = 5;
goto do_fault;
}
- desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
+ desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
+ mmu_idx, fsr, fi);
type = (desc & 3);
domain = (desc >> 5) & 0x0f;
if (regime_el(env, mmu_idx) == 1) {
@@ -6266,7 +6275,8 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
/* Fine pagetable. */
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
}
- desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
+ desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
+ mmu_idx, fsr, fi);
switch (desc & 3) {
case 0: /* Page translation fault. */
code = 7;
@@ -6347,7 +6357,8 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
code = 5;
goto do_fault;
}
- desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
+ desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
+ mmu_idx, fsr, fi);
type = (desc & 3);
if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
/* Section translation fault, or attempt to use the encoding
@@ -6398,7 +6409,8 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
ns = extract32(desc, 3, 1);
/* Lookup l2 entry. */
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
- desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
+ desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
+ mmu_idx, fsr, fi);
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
switch (desc & 3) {
case 0: /* Page translation fault. */
--
1.9.1
next prev parent reply other threads:[~2015-10-03 22:39 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-03 22:38 [Qemu-devel] [PATCH v3 0/9] arm: Steps towards EL2 support round 5 Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2 Edgar E. Iglesias
2015-10-07 11:51 ` Alex Bennée
2015-10-07 21:18 ` Peter Maydell
2015-10-08 7:52 ` Alex Bennée
2015-10-08 5:38 ` Laurent Desnogues
2015-10-08 8:18 ` Peter Maydell
2015-10-08 8:24 ` Alex Bennée
2015-10-08 9:40 ` Laurent Desnogues
2015-10-08 9:14 ` Alex Bennée
2015-10-08 19:16 ` Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 2/9] target-arm: Add computation of starting level for S2 PTW Edgar E. Iglesias
2015-10-07 12:24 ` Alex Bennée
2015-10-08 19:35 ` Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 3/9] target-arm: Add support for S2 page-table protection bits Edgar E. Iglesias
2015-10-07 16:19 ` Alex Bennée
2015-10-07 23:11 ` Peter Maydell
2015-10-14 12:45 ` Alex Bennée
2015-10-14 19:38 ` Peter Maydell
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 4/9] target-arm: Avoid inline for get_phys_addr Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 5/9] target-arm: Add ARMMMUFaultInfo Edgar E. Iglesias
2015-10-07 16:24 ` Alex Bennée
2015-10-08 19:25 ` Edgar E. Iglesias
2015-10-08 20:06 ` Edgar E. Iglesias
2015-10-08 21:15 ` Peter Maydell
2015-10-14 13:00 ` Alex Bennée
2015-10-14 20:47 ` Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 6/9] target-arm: Add S2 translation to 64bit S1 PTWs Edgar E. Iglesias
2015-10-03 22:38 ` Edgar E. Iglesias [this message]
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 8/9] target-arm: Route S2 MMU faults to EL2 Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 9/9] target-arm: Add support for S1 + S2 MMU translations Edgar E. Iglesias
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