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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org,
	qemu-devel@nongnu.org, agraf@suse.de,
	laurent.desnogues@gmail.com, serge.fdrv@gmail.com
Subject: Re: [Qemu-devel] [PATCH v3 2/9] target-arm: Add computation of starting level for S2 PTW
Date: Thu, 8 Oct 2015 12:35:11 -0700	[thread overview]
Message-ID: <20151008193511.GJ24839@toto> (raw)
In-Reply-To: <87a8ruyih0.fsf@linaro.org>

On Wed, Oct 07, 2015 at 01:24:27PM +0100, Alex Bennée wrote:
> 
> Edgar E. Iglesias <edgar.iglesias@gmail.com> writes:
> 
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > The starting level for S2 pagetable walks is computed
> > differently from the S1 starting level. Implement the S2
> > variant.
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> >  target-arm/helper.c | 39 +++++++++++++++++++++++++++------------
> >  1 file changed, 27 insertions(+), 12 deletions(-)
> >
> > diff --git a/target-arm/helper.c b/target-arm/helper.c
> > index 5a5e5f0..507324f 100644
> > --- a/target-arm/helper.c
> > +++ b/target-arm/helper.c
> > @@ -6549,18 +6549,33 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
> >          goto do_fault;
> >      }
> >  
> > -    /* The starting level depends on the virtual address size (which can be
> > -     * up to 48 bits) and the translation granule size. It indicates the number
> > -     * of strides (granule_sz bits at a time) needed to consume the bits
> > -     * of the input address. In the pseudocode this is:
> > -     *  level = 4 - RoundUp((inputsize - grainsize) / stride)
> > -     * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
> > -     * our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
> > -     * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
> > -     *     = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
> > -     *     = 4 - (va_size - tsz - 4) / granule_sz;
> > -     */
> > -    level = 4 - (va_size - tsz - 4) / granule_sz;
> > +    if (mmu_idx != ARMMMUIdx_S2NS) {
> > +        /* The starting level depends on the virtual address size (which can
> > +         * be up to 48 bits) and the translation granule size. It indicates
> > +         * the number of strides (granule_sz bits at a time) needed to
> > +         * consume the bits of the input address. In the pseudocode this is:
> > +         *  level = 4 - RoundUp((inputsize - grainsize) / stride)
> > +         * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
> > +         * our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
> > +         * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
> > +         * = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
> > +         * = 4 - (va_size - tsz - 4) / granule_sz;
> > +         */
> > +        level = 4 - (va_size - tsz - 4) / granule_sz;
> > +    } else {
> > +        unsigned int startlevel = extract32(tcr->raw_tcr, 6, 2);
> 
> Maybe an assert(startlevel<3) would be useful?

Good catch here. There is actually a trap for some of the bad startlevel cases.
I'll implement that for the next version.


> 
> > +
> > +        /* For stage 2 translations the starting level is specified by the
> > +         * VCTR_EL2.SL0 field (whose interpretation depends on the page size)
> > +         */
> > +        if (granule_sz == 9) {
> > +            /* 4K pages */
> > +            level = 2 - startlevel;
> > +        } else {
> > +            /* 16K or 64K pages */
> > +            level = 3 - startlevel;
> > +        }
> > +    }
> >  
> >      /* Clear the vaddr bits which aren't part of the within-region address,
> >       * so that we don't have to special case things when calculating the
> 
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Thanks, I'll hold the RB until you see the next version with the traps for bad
start-levels.

Cheers,
Edgar

  reply	other threads:[~2015-10-08 19:39 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-03 22:38 [Qemu-devel] [PATCH v3 0/9] arm: Steps towards EL2 support round 5 Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2 Edgar E. Iglesias
2015-10-07 11:51   ` Alex Bennée
2015-10-07 21:18     ` Peter Maydell
2015-10-08  7:52       ` Alex Bennée
2015-10-08  5:38   ` Laurent Desnogues
2015-10-08  8:18     ` Peter Maydell
2015-10-08  8:24     ` Alex Bennée
2015-10-08  9:40       ` Laurent Desnogues
2015-10-08  9:14   ` Alex Bennée
2015-10-08 19:16     ` Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 2/9] target-arm: Add computation of starting level for S2 PTW Edgar E. Iglesias
2015-10-07 12:24   ` Alex Bennée
2015-10-08 19:35     ` Edgar E. Iglesias [this message]
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 3/9] target-arm: Add support for S2 page-table protection bits Edgar E. Iglesias
2015-10-07 16:19   ` Alex Bennée
2015-10-07 23:11     ` Peter Maydell
2015-10-14 12:45       ` Alex Bennée
2015-10-14 19:38         ` Peter Maydell
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 4/9] target-arm: Avoid inline for get_phys_addr Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 5/9] target-arm: Add ARMMMUFaultInfo Edgar E. Iglesias
2015-10-07 16:24   ` Alex Bennée
2015-10-08 19:25     ` Edgar E. Iglesias
2015-10-08 20:06     ` Edgar E. Iglesias
2015-10-08 21:15       ` Peter Maydell
2015-10-14 13:00       ` Alex Bennée
2015-10-14 20:47         ` Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 6/9] target-arm: Add S2 translation to 64bit S1 PTWs Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 7/9] target-arm: Add S2 translation to 32bit " Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 8/9] target-arm: Route S2 MMU faults to EL2 Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 9/9] target-arm: Add support for S1 + S2 MMU translations Edgar E. Iglesias

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