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From: "Alex Bennée" <alex.bennee@linaro.org>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org,
	qemu-devel@nongnu.org, agraf@suse.de,
	laurent.desnogues@gmail.com, serge.fdrv@gmail.com
Subject: Re: [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2
Date: Thu, 08 Oct 2015 10:14:08 +0100	[thread overview]
Message-ID: <87ziztwwm7.fsf@linaro.org> (raw)
In-Reply-To: <1443911939-2825-2-git-send-email-edgar.iglesias@gmail.com>


Edgar E. Iglesias <edgar.iglesias@gmail.com> writes:

> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Now Peter has pointed out I can't read ;-)

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  target-arm/cpu.h    |  1 +
>  target-arm/helper.c | 12 ++++++++++++
>  2 files changed, 13 insertions(+)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index cc1578c..895f2c2 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -278,6 +278,7 @@ typedef struct CPUARMState {
>              };
>              uint64_t far_el[4];
>          };
> +        uint64_t hpfar_el2;
>          union { /* Translation result. */
>              struct {
>                  uint64_t _unused_par_0;
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 8367997..5a5e5f0 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>      { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> +    { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
> +      .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
> +      .type = ARM_CP_CONST, .resetvalue = 0 },
>      REGINFO_SENTINEL
>  };
>  
> @@ -3444,6 +3448,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
>        .resetvalue = 0,
>        .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
>  #endif
> +    { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
> +      .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
> +      .access = PL2_RW, .accessfn = access_el3_aa32ns,
> +      .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
> +    { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
> +      .access = PL2_RW,
> +      .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
>      REGINFO_SENTINEL
>  };

-- 
Alex Bennée

  parent reply	other threads:[~2015-10-08  9:15 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-03 22:38 [Qemu-devel] [PATCH v3 0/9] arm: Steps towards EL2 support round 5 Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2 Edgar E. Iglesias
2015-10-07 11:51   ` Alex Bennée
2015-10-07 21:18     ` Peter Maydell
2015-10-08  7:52       ` Alex Bennée
2015-10-08  5:38   ` Laurent Desnogues
2015-10-08  8:18     ` Peter Maydell
2015-10-08  8:24     ` Alex Bennée
2015-10-08  9:40       ` Laurent Desnogues
2015-10-08  9:14   ` Alex Bennée [this message]
2015-10-08 19:16     ` Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 2/9] target-arm: Add computation of starting level for S2 PTW Edgar E. Iglesias
2015-10-07 12:24   ` Alex Bennée
2015-10-08 19:35     ` Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 3/9] target-arm: Add support for S2 page-table protection bits Edgar E. Iglesias
2015-10-07 16:19   ` Alex Bennée
2015-10-07 23:11     ` Peter Maydell
2015-10-14 12:45       ` Alex Bennée
2015-10-14 19:38         ` Peter Maydell
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 4/9] target-arm: Avoid inline for get_phys_addr Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 5/9] target-arm: Add ARMMMUFaultInfo Edgar E. Iglesias
2015-10-07 16:24   ` Alex Bennée
2015-10-08 19:25     ` Edgar E. Iglesias
2015-10-08 20:06     ` Edgar E. Iglesias
2015-10-08 21:15       ` Peter Maydell
2015-10-14 13:00       ` Alex Bennée
2015-10-14 20:47         ` Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 6/9] target-arm: Add S2 translation to 64bit S1 PTWs Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 7/9] target-arm: Add S2 translation to 32bit " Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 8/9] target-arm: Route S2 MMU faults to EL2 Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 9/9] target-arm: Add support for S1 + S2 MMU translations Edgar E. Iglesias

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