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From: Peter Maydell <peter.maydell@linaro.org>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: "Edgar Iglesias" <edgar.iglesias@xilinx.com>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"Alexander Graf" <agraf@suse.de>,
	"Laurent Desnogues" <laurent.desnogues@gmail.com>,
	"Sergey Fedorov" <serge.fdrv@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v3 5/9] target-arm: Add ARMMMUFaultInfo
Date: Thu, 8 Oct 2015 22:15:02 +0100	[thread overview]
Message-ID: <CAFEAcA8mNmaV=GCH4-GfTo9tKVtF068ZQtt7N7_EKMwweFU=UQ@mail.gmail.com> (raw)
In-Reply-To: <20151008200647.GK24839@toto>

On 8 October 2015 at 21:06, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> On Wed, Oct 07, 2015 at 05:24:27PM +0100, Alex Bennée wrote:
>>
>> Edgar E. Iglesias <edgar.iglesias@gmail.com> writes:
>>
>> > +/**
>> > + * ARMMMUFaultInfo: Information describing an ARM MMU Fault
>> > + * @s2addr: Address that caused a fault at stage 2
>> > + * @stage2: True if we faulted at stage 2
>> > + * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
>> > + */
>> > +typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
>> > +struct ARMMMUFaultInfo {
>> > +    target_ulong s2addr;
>> > +    bool stage2;
>> > +    bool s1ptw;
>>
>> I guess the compiler packs the bools down pretty well but why not just
>> encode the faulting stage in a single variable? Perhaps I'm
>> misunderstanding the potential combinations here.
>>
>
> Do you mean using bitfields?
> e.g:
>
> struct ARMMMUFaultInfo {
>     target_ulong s2addr;
>     unsigned int stage2 : 1;
>     unsigned int s1ptw : 1;
> }
> If so, I guess we could. If others agree, I can change to that.
> We could also maybe structure things differently. I didn't consider
> the encodings very much here to be honest...

I'm not a great fan of bitfields personally; I think a pair
of bool fields expresses things more clearly.

-- PMM

  reply	other threads:[~2015-10-08 21:15 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-03 22:38 [Qemu-devel] [PATCH v3 0/9] arm: Steps towards EL2 support round 5 Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2 Edgar E. Iglesias
2015-10-07 11:51   ` Alex Bennée
2015-10-07 21:18     ` Peter Maydell
2015-10-08  7:52       ` Alex Bennée
2015-10-08  5:38   ` Laurent Desnogues
2015-10-08  8:18     ` Peter Maydell
2015-10-08  8:24     ` Alex Bennée
2015-10-08  9:40       ` Laurent Desnogues
2015-10-08  9:14   ` Alex Bennée
2015-10-08 19:16     ` Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 2/9] target-arm: Add computation of starting level for S2 PTW Edgar E. Iglesias
2015-10-07 12:24   ` Alex Bennée
2015-10-08 19:35     ` Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 3/9] target-arm: Add support for S2 page-table protection bits Edgar E. Iglesias
2015-10-07 16:19   ` Alex Bennée
2015-10-07 23:11     ` Peter Maydell
2015-10-14 12:45       ` Alex Bennée
2015-10-14 19:38         ` Peter Maydell
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 4/9] target-arm: Avoid inline for get_phys_addr Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 5/9] target-arm: Add ARMMMUFaultInfo Edgar E. Iglesias
2015-10-07 16:24   ` Alex Bennée
2015-10-08 19:25     ` Edgar E. Iglesias
2015-10-08 20:06     ` Edgar E. Iglesias
2015-10-08 21:15       ` Peter Maydell [this message]
2015-10-14 13:00       ` Alex Bennée
2015-10-14 20:47         ` Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 6/9] target-arm: Add S2 translation to 64bit S1 PTWs Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 7/9] target-arm: Add S2 translation to 32bit " Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 8/9] target-arm: Route S2 MMU faults to EL2 Edgar E. Iglesias
2015-10-03 22:38 ` [Qemu-devel] [PATCH v3 9/9] target-arm: Add support for S1 + S2 MMU translations Edgar E. Iglesias

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