* [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 14:48 ` Peter Maydell
2016-01-29 5:06 ` [Qemu-devel] [PULL 01/39] target-ppc: Use sensible POWER8/POWER8E versions David Gibson
` (38 subsequent siblings)
39 siblings, 1 reply; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
The following changes since commit 357e81c7e880f868833edf9f53cce1f3b09ea8ec:
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160128' into staging (2016-01-28 11:46:34 +0000)
are available in the git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.6-20160129
for you to fetch changes up to 1699679e699276c0538008f6ca74cd04e6c68b42:
target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro (2016-01-29 14:01:52 +1100)
----------------------------------------------------------------
ppc patch queue for 2016-01-29
Currently accumulated patches for target-ppc, pseries machine type and
related devices.
* Cleanup of error handling code in spapr
* A number of fixes for Macintosh devices for the benefit of MacOS 9 and X
* Remove some abuses of the RTAS memory access functions in spapr
* Fixes for the gdbstub (and monitor debug) for VMX and VSX extensions.
* Fix pseries machine hotplug memory under TCG
* Clean up and extend handling of multiple page sizes with 64-bit hash MMUs
----------------------------------------------------------------
Alyssa Milburn (1):
cuda.c: return error for unknown commands
Anton Blanchard (1):
target-ppc: gdbstub: Add VSX support
Benjamin Herrenschmidt (1):
target-ppc: Use sensible POWER8/POWER8E versions
Bharata B Rao (1):
spapr: Don't create ibm,dynamic-reconfiguration-memory w/o DR LMBs
David Gibson (22):
spapr: Small fixes to rtas_ibm_get_system_parameter, remove rtas_st_buffer
spapr: Remove rtas_st_buffer_direct()
spapr: Remove abuse of rtas_ld() in h_client_architecture_support
ppc: Clean up error handling in ppc_set_compat()
pseries: Clean up error handling of spapr_cpu_init()
pseries: Clean up error handling in spapr_validate_node_memory()
pseries: Clean up error handling in spapr_vga_init()
pseries: Clean up error handling in spapr_rtas_register()
pseries: Clean up error handling in xics_system_init()
pseries: Clean up error reporting in ppc_spapr_init()
pseries: Clean up error reporting in htab migration functions
pseries: Allow TCG h_enter to work with hotplugged memory
target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub
target-ppc: Convert mmu-hash{32,64}.[ch] from CPUPPCState to PowerPCCPU
target-ppc: Rework ppc_store_slb
target-ppc: Rework SLB page size lookup
target-ppc: Use actual page size encodings from HPTE
target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one
target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one()
target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs
target-ppc: Helper to determine page size information from hpte alone
target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG
Greg Kurz (6):
target-ppc: kvm: fix floating point registers sync on little-endian hosts
target-ppc: rename and export maybe_bswap_register()
target-ppc: gdbstub: fix float registers for little-endian guests
target-ppc: gdbstub: introduce avr_need_swap()
target-ppc: gdbstub: fix altivec registers for little-endian guests
target-ppc: gdbstub: fix spe registers for little-endian guests
James Clarke (1):
target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro
Mark Cave-Ayland (5):
target-ppc: use cpu_write_xer() helper in cpu_post_load
macio: use the existing IDEDMA aiocb to hold the active DMA aiocb
macio: add dma_active to VMStateDescription
mac_dbdma: add DBDMA controller state to VMStateDescription
cuda: add missing fields to VMStateDescription
Programmingkid (1):
uninorth.c: add support for UniNorth kMacRISCPCIAddressSelect (0x48) register
configure | 6 +-
gdb-xml/power-vsx.xml | 44 +++
hw/ide/macio.c | 23 +-
hw/ide/macio.c.orig | 634 ++++++++++++++++++++++++++++++++++++++++++++
hw/misc/macio/cuda.c | 12 +-
hw/misc/macio/mac_dbdma.c | 40 ++-
hw/pci-host/uninorth.c | 9 +
hw/ppc/mac.h | 1 -
hw/ppc/spapr.c | 112 ++++----
hw/ppc/spapr_hcall.c | 145 ++++------
hw/ppc/spapr_rtas.c | 50 ++--
include/hw/ppc/spapr.h | 36 +--
target-ppc/cpu-models.c | 12 +-
target-ppc/cpu-models.h | 4 +-
target-ppc/cpu.h | 35 ++-
target-ppc/gdbstub.c | 10 +-
target-ppc/helper.h | 1 +
target-ppc/kvm.c | 14 +-
target-ppc/kvm_ppc.h | 5 -
target-ppc/machine.c | 22 +-
target-ppc/mmu-hash32.c | 68 +++--
target-ppc/mmu-hash32.h | 30 ++-
target-ppc/mmu-hash64.c | 270 +++++++++++++------
target-ppc/mmu-hash64.h | 30 ++-
target-ppc/mmu_helper.c | 59 ++---
target-ppc/translate.c | 2 +-
target-ppc/translate_init.c | 129 +++++++--
27 files changed, 1382 insertions(+), 421 deletions(-)
create mode 100644 gdb-xml/power-vsx.xml
create mode 100644 hw/ide/macio.c.orig
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129
2016-01-29 5:06 ` David Gibson
@ 2016-01-29 14:48 ` Peter Maydell
2016-01-30 12:29 ` David Gibson
0 siblings, 1 reply; 47+ messages in thread
From: Peter Maydell @ 2016-01-29 14:48 UTC (permalink / raw)
To: David Gibson
Cc: Michael Roth, Alexey Kardashevskiy, QEMU Developers,
Alexander Graf, qemu-ppc
On 29 January 2016 at 05:06, David Gibson <david@gibson.dropbear.id.au> wrote:
> The following changes since commit 357e81c7e880f868833edf9f53cce1f3b09ea8ec:
>
> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160128' into staging (2016-01-28 11:46:34 +0000)
>
> are available in the git repository at:
>
> git://github.com/dgibson/qemu.git tags/ppc-for-2.6-20160129
>
> for you to fetch changes up to 1699679e699276c0538008f6ca74cd04e6c68b42:
>
> target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro (2016-01-29 14:01:52 +1100)
>
> ----------------------------------------------------------------
> ppc patch queue for 2016-01-29
>
> Currently accumulated patches for target-ppc, pseries machine type and
> related devices.
> * Cleanup of error handling code in spapr
> * A number of fixes for Macintosh devices for the benefit of MacOS 9 and X
> * Remove some abuses of the RTAS memory access functions in spapr
> * Fixes for the gdbstub (and monitor debug) for VMX and VSX extensions.
> * Fix pseries machine hotplug memory under TCG
> * Clean up and extend handling of multiple page sizes with 64-bit hash MMUs
>
Hi. Unfortunately this generates errors when built with clang:
/home/petmay01/linaro/qemu-for-merges/target-ppc/mmu_helper.c:660:20:
error: unused function 'ppc4xx_tlb_invalidate_virt'
[-Werror,-Wunused-function]
static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
^
1 error generated.
The function does appear from a quick grep to be entirely unused...
(GCC doesn't complain about this because it doesn't warn about unused
static inline functions in a .c file, but clang does.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 47+ messages in thread* Re: [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129
2016-01-29 14:48 ` Peter Maydell
@ 2016-01-30 12:29 ` David Gibson
2016-01-31 23:57 ` David Gibson
0 siblings, 1 reply; 47+ messages in thread
From: David Gibson @ 2016-01-30 12:29 UTC (permalink / raw)
To: Peter Maydell
Cc: Michael Roth, Alexey Kardashevskiy, QEMU Developers,
Alexander Graf, qemu-ppc
[-- Attachment #1: Type: text/plain, Size: 2113 bytes --]
On Fri, Jan 29, 2016 at 02:48:23PM +0000, Peter Maydell wrote:
> On 29 January 2016 at 05:06, David Gibson <david@gibson.dropbear.id.au> wrote:
> > The following changes since commit 357e81c7e880f868833edf9f53cce1f3b09ea8ec:
> >
> > Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160128' into staging (2016-01-28 11:46:34 +0000)
> >
> > are available in the git repository at:
> >
> > git://github.com/dgibson/qemu.git tags/ppc-for-2.6-20160129
> >
> > for you to fetch changes up to 1699679e699276c0538008f6ca74cd04e6c68b42:
> >
> > target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro (2016-01-29 14:01:52 +1100)
> >
> > ----------------------------------------------------------------
> > ppc patch queue for 2016-01-29
> >
> > Currently accumulated patches for target-ppc, pseries machine type and
> > related devices.
> > * Cleanup of error handling code in spapr
> > * A number of fixes for Macintosh devices for the benefit of MacOS 9 and X
> > * Remove some abuses of the RTAS memory access functions in spapr
> > * Fixes for the gdbstub (and monitor debug) for VMX and VSX extensions.
> > * Fix pseries machine hotplug memory under TCG
> > * Clean up and extend handling of multiple page sizes with 64-bit hash MMUs
> >
>
> Hi. Unfortunately this generates errors when built with clang:
>
> /home/petmay01/linaro/qemu-for-merges/target-ppc/mmu_helper.c:660:20:
> error: unused function 'ppc4xx_tlb_invalidate_virt'
> [-Werror,-Wunused-function]
> static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
> ^
> 1 error generated.
>
> The function does appear from a quick grep to be entirely unused...
>
> (GCC doesn't complain about this because it doesn't warn about unused
> static inline functions in a .c file, but clang does.)
Dammit. Sorry.
Now.. why didn't travis pick that up :/.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129
2016-01-30 12:29 ` David Gibson
@ 2016-01-31 23:57 ` David Gibson
2016-02-01 11:29 ` Peter Maydell
0 siblings, 1 reply; 47+ messages in thread
From: David Gibson @ 2016-01-31 23:57 UTC (permalink / raw)
To: Peter Maydell
Cc: Michael Roth, Alexey Kardashevskiy, QEMU Developers,
Alexander Graf, qemu-ppc
[-- Attachment #1: Type: text/plain, Size: 2473 bytes --]
On Sat, Jan 30, 2016 at 11:29:43PM +1100, David Gibson wrote:
> On Fri, Jan 29, 2016 at 02:48:23PM +0000, Peter Maydell wrote:
> > On 29 January 2016 at 05:06, David Gibson <david@gibson.dropbear.id.au> wrote:
> > > The following changes since commit 357e81c7e880f868833edf9f53cce1f3b09ea8ec:
> > >
> > > Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160128' into staging (2016-01-28 11:46:34 +0000)
> > >
> > > are available in the git repository at:
> > >
> > > git://github.com/dgibson/qemu.git tags/ppc-for-2.6-20160129
> > >
> > > for you to fetch changes up to 1699679e699276c0538008f6ca74cd04e6c68b42:
> > >
> > > target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro (2016-01-29 14:01:52 +1100)
> > >
> > > ----------------------------------------------------------------
> > > ppc patch queue for 2016-01-29
> > >
> > > Currently accumulated patches for target-ppc, pseries machine type and
> > > related devices.
> > > * Cleanup of error handling code in spapr
> > > * A number of fixes for Macintosh devices for the benefit of MacOS 9 and X
> > > * Remove some abuses of the RTAS memory access functions in spapr
> > > * Fixes for the gdbstub (and monitor debug) for VMX and VSX extensions.
> > > * Fix pseries machine hotplug memory under TCG
> > > * Clean up and extend handling of multiple page sizes with 64-bit hash MMUs
> > >
> >
> > Hi. Unfortunately this generates errors when built with clang:
> >
> > /home/petmay01/linaro/qemu-for-merges/target-ppc/mmu_helper.c:660:20:
> > error: unused function 'ppc4xx_tlb_invalidate_virt'
> > [-Werror,-Wunused-function]
> > static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
> > ^
> > 1 error generated.
> >
> > The function does appear from a quick grep to be entirely unused...
> >
> > (GCC doesn't complain about this because it doesn't warn about unused
> > static inline functions in a .c file, but clang does.)
>
> Dammit. Sorry.
>
> Now.. why didn't travis pick that up :/.
Turns out the answer is because the test for support of #pragma GCC
diagnostic turns off -Werror on clang builds for me. So I wonder
what's different about your setup that -Werror is working with clang.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129
2016-01-31 23:57 ` David Gibson
@ 2016-02-01 11:29 ` Peter Maydell
0 siblings, 0 replies; 47+ messages in thread
From: Peter Maydell @ 2016-02-01 11:29 UTC (permalink / raw)
To: David Gibson
Cc: Michael Roth, Alexey Kardashevskiy, QEMU Developers,
Alexander Graf, qemu-ppc
On 31 January 2016 at 23:57, David Gibson <david@gibson.dropbear.id.au> wrote:
> Turns out the answer is because the test for support of #pragma GCC
> diagnostic turns off -Werror on clang builds for me. So I wonder
> what's different about your setup that -Werror is working with clang.
On OSX warnings are just warnings but part of my test process involves
grepping the log output for 'warning'. On x86 clang I configure with
--extra-cflags=-Werror, to work around the pragma diagnostic check.
(None of the spurious diagnostics we use the pragma to suppress are in
practice a problem on my build.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Qemu-devel] [PULL 01/39] target-ppc: Use sensible POWER8/POWER8E versions
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
2016-01-29 5:06 ` David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 02/39] target-ppc: use cpu_write_xer() helper in cpu_post_load David Gibson
` (37 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
We never released anything older than POWER8 DD2.0 and POWER8E DD2.1,
so let's use these versions, without that some firmware or Linux code
might fail to use some HW features that were non functional in earlier
internal only spins of the chip.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/cpu-models.c | 12 ++++++------
target-ppc/cpu-models.h | 4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index 4d5ab4b..349783e 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -1138,10 +1138,10 @@
"POWER7 v2.3")
POWERPC_DEF("POWER7+_v2.1", CPU_POWERPC_POWER7P_v21, POWER7,
"POWER7+ v2.1")
- POWERPC_DEF("POWER8E_v1.0", CPU_POWERPC_POWER8E_v10, POWER8,
- "POWER8E v1.0")
- POWERPC_DEF("POWER8_v1.0", CPU_POWERPC_POWER8_v10, POWER8,
- "POWER8 v1.0")
+ POWERPC_DEF("POWER8E_v2.1", CPU_POWERPC_POWER8E_v21, POWER8,
+ "POWER8E v2.1")
+ POWERPC_DEF("POWER8_v2.0", CPU_POWERPC_POWER8_v20, POWER8,
+ "POWER8 v2.0")
POWERPC_DEF("970_v2.2", CPU_POWERPC_970_v22, 970,
"PowerPC 970 v2.2")
POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970,
@@ -1389,8 +1389,8 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
{ "POWER5gs", "POWER5+_v2.1" },
{ "POWER7", "POWER7_v2.3" },
{ "POWER7+", "POWER7+_v2.1" },
- { "POWER8E", "POWER8E_v1.0" },
- { "POWER8", "POWER8_v1.0" },
+ { "POWER8E", "POWER8E_v2.1" },
+ { "POWER8", "POWER8_v2.0" },
{ "970", "970_v2.2" },
{ "970fx", "970fx_v3.1" },
{ "970mp", "970mp_v1.1" },
diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
index 9d80e72..2992427 100644
--- a/target-ppc/cpu-models.h
+++ b/target-ppc/cpu-models.h
@@ -557,9 +557,9 @@ enum {
CPU_POWERPC_POWER7P_BASE = 0x004A0000,
CPU_POWERPC_POWER7P_v21 = 0x004A0201,
CPU_POWERPC_POWER8E_BASE = 0x004B0000,
- CPU_POWERPC_POWER8E_v10 = 0x004B0100,
+ CPU_POWERPC_POWER8E_v21 = 0x004B0201,
CPU_POWERPC_POWER8_BASE = 0x004D0000,
- CPU_POWERPC_POWER8_v10 = 0x004D0100,
+ CPU_POWERPC_POWER8_v20 = 0x004D0200,
CPU_POWERPC_970_v22 = 0x00390202,
CPU_POWERPC_970FX_v10 = 0x00391100,
CPU_POWERPC_970FX_v20 = 0x003C0200,
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 02/39] target-ppc: use cpu_write_xer() helper in cpu_post_load
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 01/39] target-ppc: Use sensible POWER8/POWER8E versions David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 03/39] macio: use the existing IDEDMA aiocb to hold the active DMA aiocb David Gibson
` (36 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, Mark Cave-Ayland, mdroth, qemu-devel, qemu-ppc, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Otherwise some internal xer variables fail to get set post-migration.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/machine.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index f4ac761..b61c060 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -168,7 +168,7 @@ static int cpu_post_load(void *opaque, int version_id)
env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
env->lr = env->spr[SPR_LR];
env->ctr = env->spr[SPR_CTR];
- env->xer = env->spr[SPR_XER];
+ cpu_write_xer(env, env->spr[SPR_XER]);
#if defined(TARGET_PPC64)
env->cfar = env->spr[SPR_CFAR];
#endif
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 03/39] macio: use the existing IDEDMA aiocb to hold the active DMA aiocb
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (2 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 02/39] target-ppc: use cpu_write_xer() helper in cpu_post_load David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 8:02 ` [Qemu-devel] [Qemu-ppc] " Aurelien Jarno
2016-01-29 5:06 ` [Qemu-devel] [PULL 04/39] macio: add dma_active to VMStateDescription David Gibson
` (35 subsequent siblings)
39 siblings, 1 reply; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, Mark Cave-Ayland, mdroth, qemu-devel, qemu-ppc, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Currently the aiocb is held within MACIOIDEState, however the IDE core code
assumes that the current actvie DMA aiocb is held in aiocb in a few places,
e.g. ide_bus_reset() and ide_reset().
Switch over to using IDEDMA aiocb to store the aiocb for the current active
DMA request so that bus resets and restarts are handled correctly. As a
consequence we can now use ide_set_inactive() rather than handling its
functionality ourselves.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: John Snow <jsnow@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ide/macio.c | 20 +-
hw/ide/macio.c.orig | 634 ++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/ppc/mac.h | 1 -
3 files changed, 646 insertions(+), 9 deletions(-)
create mode 100644 hw/ide/macio.c.orig
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index d4031b6..110af46 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -119,8 +119,8 @@ static void pmac_dma_read(BlockBackend *blk,
MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64 " "
"nsector: %x\n", (offset >> 9), (bytes >> 9));
- m->aiocb = blk_aio_readv(blk, (offset >> 9), &io->iov, (bytes >> 9),
- cb, io);
+ s->bus->dma->aiocb = blk_aio_readv(blk, (offset >> 9), &io->iov,
+ (bytes >> 9), cb, io);
}
static void pmac_dma_write(BlockBackend *blk,
@@ -204,8 +204,8 @@ static void pmac_dma_write(BlockBackend *blk,
MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64 " "
"nsector: %x\n", (offset >> 9), (bytes >> 9));
- m->aiocb = blk_aio_writev(blk, (offset >> 9), &io->iov, (bytes >> 9),
- cb, io);
+ s->bus->dma->aiocb = blk_aio_writev(blk, (offset >> 9), &io->iov,
+ (bytes >> 9), cb, io);
}
static void pmac_dma_trim(BlockBackend *blk,
@@ -231,8 +231,8 @@ static void pmac_dma_trim(BlockBackend *blk,
s->io_buffer_index += io->len;
io->len = 0;
- m->aiocb = ide_issue_trim(blk, (offset >> 9), &io->iov, (bytes >> 9),
- cb, io);
+ s->bus->dma->aiocb = ide_issue_trim(blk, (offset >> 9), &io->iov,
+ (bytes >> 9), cb, io);
}
static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
@@ -291,6 +291,8 @@ done:
} else {
block_acct_done(blk_get_stats(s->blk), &s->acct);
}
+
+ ide_set_inactive(s, false);
io->dma_end(opaque);
}
@@ -305,7 +307,6 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
if (ret < 0) {
MACIO_DPRINTF("DMA error: %d\n", ret);
- m->aiocb = NULL;
ide_dma_error(s);
goto done;
}
@@ -356,6 +357,8 @@ done:
block_acct_done(blk_get_stats(s->blk), &s->acct);
}
}
+
+ ide_set_inactive(s, false);
io->dma_end(opaque);
}
@@ -393,8 +396,9 @@ static void pmac_ide_transfer(DBDMA_io *io)
static void pmac_ide_flush(DBDMA_io *io)
{
MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
- if (m->aiocb) {
+ if (s->bus->dma->aiocb) {
blk_drain_all();
}
}
diff --git a/hw/ide/macio.c.orig b/hw/ide/macio.c.orig
new file mode 100644
index 0000000..d4031b6
--- /dev/null
+++ b/hw/ide/macio.c.orig
@@ -0,0 +1,634 @@
+/*
+ * QEMU IDE Emulation: MacIO support.
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2006 Openedhand Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw/hw.h"
+#include "hw/ppc/mac.h"
+#include "hw/ppc/mac_dbdma.h"
+#include "sysemu/block-backend.h"
+#include "sysemu/dma.h"
+
+#include <hw/ide/internal.h>
+
+/* debug MACIO */
+// #define DEBUG_MACIO
+
+#ifdef DEBUG_MACIO
+static const int debug_macio = 1;
+#else
+static const int debug_macio = 0;
+#endif
+
+#define MACIO_DPRINTF(fmt, ...) do { \
+ if (debug_macio) { \
+ printf(fmt , ## __VA_ARGS__); \
+ } \
+ } while (0)
+
+
+/***********************************************************/
+/* MacIO based PowerPC IDE */
+
+#define MACIO_PAGE_SIZE 4096
+
+/*
+ * Unaligned DMA read/write access functions required for OS X/Darwin which
+ * don't perform DMA transactions on sector boundaries. These functions are
+ * modelled on bdrv_co_do_preadv()/bdrv_co_do_pwritev() and so should be
+ * easy to remove if the unaligned block APIs are ever exposed.
+ */
+
+static void pmac_dma_read(BlockBackend *blk,
+ int64_t offset, unsigned int bytes,
+ void (*cb)(void *opaque, int ret), void *opaque)
+{
+ DBDMA_io *io = opaque;
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+ dma_addr_t dma_addr, dma_len;
+ void *mem;
+ int64_t sector_num;
+ int nsector;
+ uint64_t align = BDRV_SECTOR_SIZE;
+ size_t head_bytes, tail_bytes;
+
+ qemu_iovec_destroy(&io->iov);
+ qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
+
+ sector_num = (offset >> 9);
+ nsector = (io->len >> 9);
+
+ MACIO_DPRINTF("--- DMA read transfer (0x%" HWADDR_PRIx ",0x%x): "
+ "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
+ sector_num, nsector);
+
+ dma_addr = io->addr;
+ dma_len = io->len;
+ mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
+ DMA_DIRECTION_FROM_DEVICE);
+
+ if (offset & (align - 1)) {
+ head_bytes = offset & (align - 1);
+
+ MACIO_DPRINTF("--- DMA unaligned head: sector %" PRId64 ", "
+ "discarding %zu bytes\n", sector_num, head_bytes);
+
+ qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
+
+ bytes += offset & (align - 1);
+ offset = offset & ~(align - 1);
+ }
+
+ qemu_iovec_add(&io->iov, mem, io->len);
+
+ if ((offset + bytes) & (align - 1)) {
+ tail_bytes = (offset + bytes) & (align - 1);
+
+ MACIO_DPRINTF("--- DMA unaligned tail: sector %" PRId64 ", "
+ "discarding bytes %zu\n", sector_num, tail_bytes);
+
+ qemu_iovec_add(&io->iov, &io->tail_remainder, align - tail_bytes);
+ bytes = ROUND_UP(bytes, align);
+ }
+
+ s->io_buffer_size -= io->len;
+ s->io_buffer_index += io->len;
+
+ io->len = 0;
+
+ MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64 " "
+ "nsector: %x\n", (offset >> 9), (bytes >> 9));
+
+ m->aiocb = blk_aio_readv(blk, (offset >> 9), &io->iov, (bytes >> 9),
+ cb, io);
+}
+
+static void pmac_dma_write(BlockBackend *blk,
+ int64_t offset, int bytes,
+ void (*cb)(void *opaque, int ret), void *opaque)
+{
+ DBDMA_io *io = opaque;
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+ dma_addr_t dma_addr, dma_len;
+ void *mem;
+ int64_t sector_num;
+ int nsector;
+ uint64_t align = BDRV_SECTOR_SIZE;
+ size_t head_bytes, tail_bytes;
+ bool unaligned_head = false, unaligned_tail = false;
+
+ qemu_iovec_destroy(&io->iov);
+ qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
+
+ sector_num = (offset >> 9);
+ nsector = (io->len >> 9);
+
+ MACIO_DPRINTF("--- DMA write transfer (0x%" HWADDR_PRIx ",0x%x): "
+ "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
+ sector_num, nsector);
+
+ dma_addr = io->addr;
+ dma_len = io->len;
+ mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
+ DMA_DIRECTION_TO_DEVICE);
+
+ if (offset & (align - 1)) {
+ head_bytes = offset & (align - 1);
+ sector_num = ((offset & ~(align - 1)) >> 9);
+
+ MACIO_DPRINTF("--- DMA unaligned head: pre-reading head sector %"
+ PRId64 "\n", sector_num);
+
+ blk_pread(s->blk, (sector_num << 9), &io->head_remainder, align);
+
+ qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
+ qemu_iovec_add(&io->iov, mem, io->len);
+
+ bytes += offset & (align - 1);
+ offset = offset & ~(align - 1);
+
+ unaligned_head = true;
+ }
+
+ if ((offset + bytes) & (align - 1)) {
+ tail_bytes = (offset + bytes) & (align - 1);
+ sector_num = (((offset + bytes) & ~(align - 1)) >> 9);
+
+ MACIO_DPRINTF("--- DMA unaligned tail: pre-reading tail sector %"
+ PRId64 "\n", sector_num);
+
+ blk_pread(s->blk, (sector_num << 9), &io->tail_remainder, align);
+
+ if (!unaligned_head) {
+ qemu_iovec_add(&io->iov, mem, io->len);
+ }
+
+ qemu_iovec_add(&io->iov, &io->tail_remainder + tail_bytes,
+ align - tail_bytes);
+
+ bytes = ROUND_UP(bytes, align);
+
+ unaligned_tail = true;
+ }
+
+ if (!unaligned_head && !unaligned_tail) {
+ qemu_iovec_add(&io->iov, mem, io->len);
+ }
+
+ s->io_buffer_size -= io->len;
+ s->io_buffer_index += io->len;
+
+ io->len = 0;
+
+ MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64 " "
+ "nsector: %x\n", (offset >> 9), (bytes >> 9));
+
+ m->aiocb = blk_aio_writev(blk, (offset >> 9), &io->iov, (bytes >> 9),
+ cb, io);
+}
+
+static void pmac_dma_trim(BlockBackend *blk,
+ int64_t offset, int bytes,
+ void (*cb)(void *opaque, int ret), void *opaque)
+{
+ DBDMA_io *io = opaque;
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+ dma_addr_t dma_addr, dma_len;
+ void *mem;
+
+ qemu_iovec_destroy(&io->iov);
+ qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
+
+ dma_addr = io->addr;
+ dma_len = io->len;
+ mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
+ DMA_DIRECTION_TO_DEVICE);
+
+ qemu_iovec_add(&io->iov, mem, io->len);
+ s->io_buffer_size -= io->len;
+ s->io_buffer_index += io->len;
+ io->len = 0;
+
+ m->aiocb = ide_issue_trim(blk, (offset >> 9), &io->iov, (bytes >> 9),
+ cb, io);
+}
+
+static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
+{
+ DBDMA_io *io = opaque;
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+ int64_t offset;
+
+ MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
+
+ if (ret < 0) {
+ MACIO_DPRINTF("DMA error: %d\n", ret);
+ ide_atapi_io_error(s, ret);
+ goto done;
+ }
+
+ if (!m->dma_active) {
+ MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
+ s->nsector, io->len, s->status);
+ /* data not ready yet, wait for the channel to get restarted */
+ io->processing = false;
+ return;
+ }
+
+ if (s->io_buffer_size <= 0) {
+ MACIO_DPRINTF("End of IDE transfer\n");
+ ide_atapi_cmd_ok(s);
+ m->dma_active = false;
+ goto done;
+ }
+
+ if (io->len == 0) {
+ MACIO_DPRINTF("End of DMA transfer\n");
+ goto done;
+ }
+
+ if (s->lba == -1) {
+ /* Non-block ATAPI transfer - just copy to RAM */
+ s->io_buffer_size = MIN(s->io_buffer_size, io->len);
+ cpu_physical_memory_write(io->addr, s->io_buffer, s->io_buffer_size);
+ ide_atapi_cmd_ok(s);
+ m->dma_active = false;
+ goto done;
+ }
+
+ /* Calculate current offset */
+ offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
+
+ pmac_dma_read(s->blk, offset, io->len, pmac_ide_atapi_transfer_cb, io);
+ return;
+
+done:
+ if (ret < 0) {
+ block_acct_failed(blk_get_stats(s->blk), &s->acct);
+ } else {
+ block_acct_done(blk_get_stats(s->blk), &s->acct);
+ }
+ io->dma_end(opaque);
+}
+
+static void pmac_ide_transfer_cb(void *opaque, int ret)
+{
+ DBDMA_io *io = opaque;
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+ int64_t offset;
+
+ MACIO_DPRINTF("pmac_ide_transfer_cb\n");
+
+ if (ret < 0) {
+ MACIO_DPRINTF("DMA error: %d\n", ret);
+ m->aiocb = NULL;
+ ide_dma_error(s);
+ goto done;
+ }
+
+ if (!m->dma_active) {
+ MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
+ s->nsector, io->len, s->status);
+ /* data not ready yet, wait for the channel to get restarted */
+ io->processing = false;
+ return;
+ }
+
+ if (s->io_buffer_size <= 0) {
+ MACIO_DPRINTF("End of IDE transfer\n");
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s->bus);
+ m->dma_active = false;
+ goto done;
+ }
+
+ if (io->len == 0) {
+ MACIO_DPRINTF("End of DMA transfer\n");
+ goto done;
+ }
+
+ /* Calculate number of sectors */
+ offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
+
+ switch (s->dma_cmd) {
+ case IDE_DMA_READ:
+ pmac_dma_read(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
+ break;
+ case IDE_DMA_WRITE:
+ pmac_dma_write(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
+ break;
+ case IDE_DMA_TRIM:
+ pmac_dma_trim(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
+ break;
+ }
+
+ return;
+
+done:
+ if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
+ if (ret < 0) {
+ block_acct_failed(blk_get_stats(s->blk), &s->acct);
+ } else {
+ block_acct_done(blk_get_stats(s->blk), &s->acct);
+ }
+ }
+ io->dma_end(opaque);
+}
+
+static void pmac_ide_transfer(DBDMA_io *io)
+{
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+
+ MACIO_DPRINTF("\n");
+
+ if (s->drive_kind == IDE_CD) {
+ block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
+ BLOCK_ACCT_READ);
+
+ pmac_ide_atapi_transfer_cb(io, 0);
+ return;
+ }
+
+ switch (s->dma_cmd) {
+ case IDE_DMA_READ:
+ block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
+ BLOCK_ACCT_READ);
+ break;
+ case IDE_DMA_WRITE:
+ block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
+ BLOCK_ACCT_WRITE);
+ break;
+ default:
+ break;
+ }
+
+ pmac_ide_transfer_cb(io, 0);
+}
+
+static void pmac_ide_flush(DBDMA_io *io)
+{
+ MACIOIDEState *m = io->opaque;
+
+ if (m->aiocb) {
+ blk_drain_all();
+ }
+}
+
+/* PowerMac IDE memory IO */
+static void pmac_ide_writeb (void *opaque,
+ hwaddr addr, uint32_t val)
+{
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ switch (addr) {
+ case 1 ... 7:
+ ide_ioport_write(&d->bus, addr, val);
+ break;
+ case 8:
+ case 22:
+ ide_cmd_write(&d->bus, 0, val);
+ break;
+ default:
+ break;
+ }
+}
+
+static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
+{
+ uint8_t retval;
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ switch (addr) {
+ case 1 ... 7:
+ retval = ide_ioport_read(&d->bus, addr);
+ break;
+ case 8:
+ case 22:
+ retval = ide_status_read(&d->bus, 0);
+ break;
+ default:
+ retval = 0xFF;
+ break;
+ }
+ return retval;
+}
+
+static void pmac_ide_writew (void *opaque,
+ hwaddr addr, uint32_t val)
+{
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ val = bswap16(val);
+ if (addr == 0) {
+ ide_data_writew(&d->bus, 0, val);
+ }
+}
+
+static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
+{
+ uint16_t retval;
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ if (addr == 0) {
+ retval = ide_data_readw(&d->bus, 0);
+ } else {
+ retval = 0xFFFF;
+ }
+ retval = bswap16(retval);
+ return retval;
+}
+
+static void pmac_ide_writel (void *opaque,
+ hwaddr addr, uint32_t val)
+{
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ val = bswap32(val);
+ if (addr == 0) {
+ ide_data_writel(&d->bus, 0, val);
+ }
+}
+
+static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
+{
+ uint32_t retval;
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ if (addr == 0) {
+ retval = ide_data_readl(&d->bus, 0);
+ } else {
+ retval = 0xFFFFFFFF;
+ }
+ retval = bswap32(retval);
+ return retval;
+}
+
+static const MemoryRegionOps pmac_ide_ops = {
+ .old_mmio = {
+ .write = {
+ pmac_ide_writeb,
+ pmac_ide_writew,
+ pmac_ide_writel,
+ },
+ .read = {
+ pmac_ide_readb,
+ pmac_ide_readw,
+ pmac_ide_readl,
+ },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_pmac = {
+ .name = "ide",
+ .version_id = 3,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_IDE_BUS(bus, MACIOIDEState),
+ VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void macio_ide_reset(DeviceState *dev)
+{
+ MACIOIDEState *d = MACIO_IDE(dev);
+
+ ide_bus_reset(&d->bus);
+}
+
+static int ide_nop_int(IDEDMA *dma, int x)
+{
+ return 0;
+}
+
+static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
+{
+ return 0;
+}
+
+static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
+ BlockCompletionFunc *cb)
+{
+ MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
+
+ s->io_buffer_index = 0;
+ if (s->drive_kind == IDE_CD) {
+ s->io_buffer_size = s->packet_transfer_size;
+ } else {
+ s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
+ }
+
+ MACIO_DPRINTF("\n\n------------ IDE transfer\n");
+ MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
+ s->io_buffer_size, s->io_buffer_index);
+ MACIO_DPRINTF("lba: %x size: %x\n", s->lba, s->io_buffer_size);
+ MACIO_DPRINTF("-------------------------\n");
+
+ m->dma_active = true;
+ DBDMA_kick(m->dbdma);
+}
+
+static const IDEDMAOps dbdma_ops = {
+ .start_dma = ide_dbdma_start,
+ .prepare_buf = ide_nop_int32,
+ .rw_buf = ide_nop_int,
+};
+
+static void macio_ide_realizefn(DeviceState *dev, Error **errp)
+{
+ MACIOIDEState *s = MACIO_IDE(dev);
+
+ ide_init2(&s->bus, s->irq);
+
+ /* Register DMA callbacks */
+ s->dma.ops = &dbdma_ops;
+ s->bus.dma = &s->dma;
+}
+
+static void macio_ide_initfn(Object *obj)
+{
+ SysBusDevice *d = SYS_BUS_DEVICE(obj);
+ MACIOIDEState *s = MACIO_IDE(obj);
+
+ ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
+ memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
+ sysbus_init_mmio(d, &s->mem);
+ sysbus_init_irq(d, &s->irq);
+ sysbus_init_irq(d, &s->dma_irq);
+}
+
+static void macio_ide_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = macio_ide_realizefn;
+ dc->reset = macio_ide_reset;
+ dc->vmsd = &vmstate_pmac;
+ set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
+}
+
+static const TypeInfo macio_ide_type_info = {
+ .name = TYPE_MACIO_IDE,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MACIOIDEState),
+ .instance_init = macio_ide_initfn,
+ .class_init = macio_ide_class_init,
+};
+
+static void macio_ide_register_types(void)
+{
+ type_register_static(&macio_ide_type_info);
+}
+
+/* hd_table must contain 2 block drivers */
+void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
+{
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ if (hd_table[i]) {
+ ide_create_drive(&s->bus, i, hd_table[i]);
+ }
+ }
+}
+
+void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel)
+{
+ s->dbdma = dbdma;
+ DBDMA_register_channel(dbdma, channel, s->dma_irq,
+ pmac_ide_transfer, pmac_ide_flush, s);
+}
+
+type_init(macio_ide_register_types)
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index e375ed2..ecf7792 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -134,7 +134,6 @@ typedef struct MACIOIDEState {
MemoryRegion mem;
IDEBus bus;
- BlockAIOCB *aiocb;
IDEDMA dma;
void *dbdma;
bool dma_active;
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [PULL 03/39] macio: use the existing IDEDMA aiocb to hold the active DMA aiocb
2016-01-29 5:06 ` [Qemu-devel] [PULL 03/39] macio: use the existing IDEDMA aiocb to hold the active DMA aiocb David Gibson
@ 2016-01-29 8:02 ` Aurelien Jarno
2016-01-30 12:36 ` David Gibson
0 siblings, 1 reply; 47+ messages in thread
From: Aurelien Jarno @ 2016-01-29 8:02 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-devel, peter.maydell, qemu-ppc, agraf, mdroth
On 2016-01-29 16:06, David Gibson wrote:
> From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>
> Currently the aiocb is held within MACIOIDEState, however the IDE core code
> assumes that the current actvie DMA aiocb is held in aiocb in a few places,
> e.g. ide_bus_reset() and ide_reset().
>
> Switch over to using IDEDMA aiocb to store the aiocb for the current active
> DMA request so that bus resets and restarts are handled correctly. As a
> consequence we can now use ide_set_inactive() rather than handling its
> functionality ourselves.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Reviewed-by: John Snow <jsnow@redhat.com>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> hw/ide/macio.c | 20 +-
> hw/ide/macio.c.orig | 634 ++++++++++++++++++++++++++++++++++++++++++++++++++++
I don't think you want to add this file to the git.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PULL 03/39] macio: use the existing IDEDMA aiocb to hold the active DMA aiocb
2016-01-29 8:02 ` [Qemu-devel] [Qemu-ppc] " Aurelien Jarno
@ 2016-01-30 12:36 ` David Gibson
0 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-30 12:36 UTC (permalink / raw)
To: Aurelien Jarno; +Cc: qemu-devel, peter.maydell, qemu-ppc, agraf, mdroth
[-- Attachment #1: Type: text/plain, Size: 1281 bytes --]
On Fri, Jan 29, 2016 at 09:02:47AM +0100, Aurelien Jarno wrote:
> On 2016-01-29 16:06, David Gibson wrote:
> > From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> >
> > Currently the aiocb is held within MACIOIDEState, however the IDE core code
> > assumes that the current actvie DMA aiocb is held in aiocb in a few places,
> > e.g. ide_bus_reset() and ide_reset().
> >
> > Switch over to using IDEDMA aiocb to store the aiocb for the current active
> > DMA request so that bus resets and restarts are handled correctly. As a
> > consequence we can now use ide_set_inactive() rather than handling its
> > functionality ourselves.
> >
> > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> > Reviewed-by: John Snow <jsnow@redhat.com>
> > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> > ---
> > hw/ide/macio.c | 20 +-
> > hw/ide/macio.c.orig | 634 ++++++++++++++++++++++++++++++++++++++++++++++++++++
>
> I don't think you want to add this file to the git.
Sigh. Indeed. Not doing well with these pulls lately :(.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Qemu-devel] [PULL 04/39] macio: add dma_active to VMStateDescription
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (3 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 03/39] macio: use the existing IDEDMA aiocb to hold the active DMA aiocb David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 05/39] mac_dbdma: add DBDMA controller state " David Gibson
` (34 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, Mark Cave-Ayland, mdroth, qemu-devel, qemu-ppc, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Make sure that we include the value of dma_active in the migration stream.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: John Snow <jsnow@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ide/macio.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index 110af46..a39bdc0 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -516,11 +516,12 @@ static const MemoryRegionOps pmac_ide_ops = {
static const VMStateDescription vmstate_pmac = {
.name = "ide",
- .version_id = 3,
+ .version_id = 4,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_IDE_BUS(bus, MACIOIDEState),
VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
+ VMSTATE_BOOL(dma_active, MACIOIDEState),
VMSTATE_END_OF_LIST()
}
};
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 05/39] mac_dbdma: add DBDMA controller state to VMStateDescription
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (4 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 04/39] macio: add dma_active to VMStateDescription David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 06/39] cuda: add missing fields " David Gibson
` (33 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, Mark Cave-Ayland, mdroth, qemu-devel, qemu-ppc, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Make sure that we include the DBDMA controller state in the migration
stream.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/misc/macio/mac_dbdma.c | 40 ++++++++++++++++++++++++++++++++++++----
1 file changed, 36 insertions(+), 4 deletions(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index 5ee8f02..161f49e 100644
--- a/hw/misc/macio/mac_dbdma.c
+++ b/hw/misc/macio/mac_dbdma.c
@@ -712,20 +712,52 @@ static const MemoryRegionOps dbdma_ops = {
},
};
-static const VMStateDescription vmstate_dbdma_channel = {
- .name = "dbdma_channel",
+static const VMStateDescription vmstate_dbdma_io = {
+ .name = "dbdma_io",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(addr, struct DBDMA_io),
+ VMSTATE_INT32(len, struct DBDMA_io),
+ VMSTATE_INT32(is_last, struct DBDMA_io),
+ VMSTATE_INT32(is_dma_out, struct DBDMA_io),
+ VMSTATE_BOOL(processing, struct DBDMA_io),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_dbdma_cmd = {
+ .name = "dbdma_cmd",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
+ VMSTATE_UINT16(req_count, dbdma_cmd),
+ VMSTATE_UINT16(command, dbdma_cmd),
+ VMSTATE_UINT32(phy_addr, dbdma_cmd),
+ VMSTATE_UINT32(cmd_dep, dbdma_cmd),
+ VMSTATE_UINT16(res_count, dbdma_cmd),
+ VMSTATE_UINT16(xfer_status, dbdma_cmd),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_dbdma_channel = {
+ .name = "dbdma_channel",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, struct DBDMA_channel, DBDMA_REGS),
+ VMSTATE_STRUCT(io, struct DBDMA_channel, 0, vmstate_dbdma_io, DBDMA_io),
+ VMSTATE_STRUCT(current, struct DBDMA_channel, 0, vmstate_dbdma_cmd,
+ dbdma_cmd),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_dbdma = {
.name = "dbdma",
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
.fields = (VMStateField[]) {
VMSTATE_STRUCT_ARRAY(channels, DBDMAState, DBDMA_CHANNELS, 1,
vmstate_dbdma_channel, DBDMA_channel),
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 06/39] cuda: add missing fields to VMStateDescription
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (5 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 05/39] mac_dbdma: add DBDMA controller state " David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 07/39] spapr: Small fixes to rtas_ibm_get_system_parameter, remove rtas_st_buffer David Gibson
` (32 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, Mark Cave-Ayland, mdroth, qemu-devel, qemu-ppc, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Include some fields missed from the previous VMState conversion to the
migration stream, as well as the new SR_INT delay timer.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/misc/macio/cuda.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c
index 9db4c64..3556852 100644
--- a/hw/misc/macio/cuda.c
+++ b/hw/misc/macio/cuda.c
@@ -704,15 +704,17 @@ static const VMStateDescription vmstate_cuda_timer = {
static const VMStateDescription vmstate_cuda = {
.name = "cuda",
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
.fields = (VMStateField[]) {
VMSTATE_UINT8(a, CUDAState),
VMSTATE_UINT8(b, CUDAState),
+ VMSTATE_UINT8(last_b, CUDAState),
VMSTATE_UINT8(dira, CUDAState),
VMSTATE_UINT8(dirb, CUDAState),
VMSTATE_UINT8(sr, CUDAState),
VMSTATE_UINT8(acr, CUDAState),
+ VMSTATE_UINT8(last_acr, CUDAState),
VMSTATE_UINT8(pcr, CUDAState),
VMSTATE_UINT8(ifr, CUDAState),
VMSTATE_UINT8(ier, CUDAState),
@@ -727,6 +729,7 @@ static const VMStateDescription vmstate_cuda = {
VMSTATE_STRUCT_ARRAY(timers, CUDAState, 2, 1,
vmstate_cuda_timer, CUDATimer),
VMSTATE_TIMER_PTR(adb_poll_timer, CUDAState),
+ VMSTATE_TIMER_PTR(sr_delay_timer, CUDAState),
VMSTATE_END_OF_LIST()
}
};
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 07/39] spapr: Small fixes to rtas_ibm_get_system_parameter, remove rtas_st_buffer
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (6 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 06/39] cuda: add missing fields " David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 08/39] spapr: Remove rtas_st_buffer_direct() David Gibson
` (31 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
rtas_st_buffer() appears in spapr.h as though it were a widely used helper,
but in fact it is only used for saving data in a format used by
rtas_ibm_get_system_parameter(). This changes it to a local helper more
specifically for that function.
While we're there fix a couple of small defects in
rtas_ibm_get_system_parameter:
- For the string value SPLPAR_CHARACTERISTICS, it wasn't including the
terminating \0 in the length which it should according to LoPAPR
7.3.16.1
- It now checks that the supplied buffer has at least enough space for
the length of the returned data, and returns an error if it does not.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr_rtas.c | 21 +++++++++++++++++----
include/hw/ppc/spapr.h | 28 +++++++++-------------------
2 files changed, 26 insertions(+), 23 deletions(-)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 34b12a3..8b702b5 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -228,6 +228,19 @@ static void rtas_stop_self(PowerPCCPU *cpu, sPAPRMachineState *spapr,
env->msr = 0;
}
+static inline int sysparm_st(target_ulong addr, target_ulong len,
+ const void *val, uint16_t vallen)
+{
+ hwaddr phys = ppc64_phys_to_real(addr);
+
+ if (len < 2) {
+ return RTAS_OUT_SYSPARM_PARAM_ERROR;
+ }
+ stw_be_phys(&address_space_memory, phys, vallen);
+ cpu_physical_memory_write(phys + 2, val, MIN(len - 2, vallen));
+ return RTAS_OUT_SUCCESS;
+}
+
static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
sPAPRMachineState *spapr,
uint32_t token, uint32_t nargs,
@@ -237,7 +250,7 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
target_ulong parameter = rtas_ld(args, 0);
target_ulong buffer = rtas_ld(args, 1);
target_ulong length = rtas_ld(args, 2);
- target_ulong ret = RTAS_OUT_SUCCESS;
+ target_ulong ret;
switch (parameter) {
case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: {
@@ -249,18 +262,18 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
current_machine->ram_size / M_BYTE,
smp_cpus,
max_cpus);
- rtas_st_buffer(buffer, length, (uint8_t *)param_val, strlen(param_val));
+ ret = sysparm_st(buffer, length, param_val, strlen(param_val) + 1);
g_free(param_val);
break;
}
case RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE: {
uint8_t param_val = DIAGNOSTICS_RUN_MODE_DISABLED;
- rtas_st_buffer(buffer, length, ¶m_val, sizeof(param_val));
+ ret = sysparm_st(buffer, length, ¶m_val, sizeof(param_val));
break;
}
case RTAS_SYSPARM_UUID:
- rtas_st_buffer(buffer, length, qemu_uuid, (qemu_uuid_set ? 16 : 0));
+ ret = sysparm_st(buffer, length, qemu_uuid, (qemu_uuid_set ? 16 : 0));
break;
default:
ret = RTAS_OUT_NOT_SUPPORTED;
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 53af76a..1e10fc9 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -408,14 +408,15 @@ int spapr_allocate_irq_block(int num, bool lsi, bool msi);
#define RTAS_SLOT_PERM_ERR_LOG 2
/* RTAS return codes */
-#define RTAS_OUT_SUCCESS 0
-#define RTAS_OUT_NO_ERRORS_FOUND 1
-#define RTAS_OUT_HW_ERROR -1
-#define RTAS_OUT_BUSY -2
-#define RTAS_OUT_PARAM_ERROR -3
-#define RTAS_OUT_NOT_SUPPORTED -3
-#define RTAS_OUT_NO_SUCH_INDICATOR -3
-#define RTAS_OUT_NOT_AUTHORIZED -9002
+#define RTAS_OUT_SUCCESS 0
+#define RTAS_OUT_NO_ERRORS_FOUND 1
+#define RTAS_OUT_HW_ERROR -1
+#define RTAS_OUT_BUSY -2
+#define RTAS_OUT_PARAM_ERROR -3
+#define RTAS_OUT_NOT_SUPPORTED -3
+#define RTAS_OUT_NO_SUCH_INDICATOR -3
+#define RTAS_OUT_NOT_AUTHORIZED -9002
+#define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
/* RTAS tokens */
#define RTAS_TOKEN_BASE 0x2000
@@ -513,17 +514,6 @@ static inline void rtas_st_buffer_direct(target_ulong phys,
MIN(buffer_len, phys_len));
}
-static inline void rtas_st_buffer(target_ulong phys, target_ulong phys_len,
- uint8_t *buffer, uint16_t buffer_len)
-{
- if (phys_len < 2) {
- return;
- }
- stw_be_phys(&address_space_memory,
- ppc64_phys_to_real(phys), buffer_len);
- rtas_st_buffer_direct(phys + 2, phys_len - 2, buffer, buffer_len);
-}
-
typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
uint32_t token,
uint32_t nargs, target_ulong args,
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 08/39] spapr: Remove rtas_st_buffer_direct()
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (7 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 07/39] spapr: Small fixes to rtas_ibm_get_system_parameter, remove rtas_st_buffer David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 09/39] spapr: Remove abuse of rtas_ld() in h_client_architecture_support David Gibson
` (30 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
rtas_st_buffer_direct() is a not particularly useful wrapper around
cpu_physical_memory_write(). All the callers are in
rtas_ibm_configure_connector, where it's better handled by local helper.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr_rtas.c | 17 ++++++++++-------
include/hw/ppc/spapr.h | 8 --------
2 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 8b702b5..eac1556 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -505,6 +505,13 @@ out:
#define CC_VAL_DATA_OFFSET ((CC_IDX_PROP_DATA_OFFSET + 1) * 4)
#define CC_WA_LEN 4096
+static void configure_connector_st(target_ulong addr, target_ulong offset,
+ const void *buf, size_t len)
+{
+ cpu_physical_memory_write(ppc64_phys_to_real(addr + offset),
+ buf, MIN(len, CC_WA_LEN - offset));
+}
+
static void rtas_ibm_configure_connector(PowerPCCPU *cpu,
sPAPRMachineState *spapr,
uint32_t token, uint32_t nargs,
@@ -570,8 +577,7 @@ static void rtas_ibm_configure_connector(PowerPCCPU *cpu,
/* provide the name of the next OF node */
wa_offset = CC_VAL_DATA_OFFSET;
rtas_st(wa_addr, CC_IDX_NODE_NAME_OFFSET, wa_offset);
- rtas_st_buffer_direct(wa_addr + wa_offset, CC_WA_LEN - wa_offset,
- (uint8_t *)name, strlen(name) + 1);
+ configure_connector_st(wa_addr, wa_offset, name, strlen(name) + 1);
resp = SPAPR_DR_CC_RESPONSE_NEXT_CHILD;
break;
case FDT_END_NODE:
@@ -596,8 +602,7 @@ static void rtas_ibm_configure_connector(PowerPCCPU *cpu,
/* provide the name of the next OF property */
wa_offset = CC_VAL_DATA_OFFSET;
rtas_st(wa_addr, CC_IDX_PROP_NAME_OFFSET, wa_offset);
- rtas_st_buffer_direct(wa_addr + wa_offset, CC_WA_LEN - wa_offset,
- (uint8_t *)name, strlen(name) + 1);
+ configure_connector_st(wa_addr, wa_offset, name, strlen(name) + 1);
/* provide the length and value of the OF property. data gets
* placed immediately after NULL terminator of the OF property's
@@ -606,9 +611,7 @@ static void rtas_ibm_configure_connector(PowerPCCPU *cpu,
wa_offset += strlen(name) + 1,
rtas_st(wa_addr, CC_IDX_PROP_LEN, prop_len);
rtas_st(wa_addr, CC_IDX_PROP_DATA_OFFSET, wa_offset);
- rtas_st_buffer_direct(wa_addr + wa_offset, CC_WA_LEN - wa_offset,
- (uint8_t *)((struct fdt_property *)prop)->data,
- prop_len);
+ configure_connector_st(wa_addr, wa_offset, prop->data, prop_len);
resp = SPAPR_DR_CC_RESPONSE_NEXT_PROPERTY;
break;
case FDT_END:
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 1e10fc9..1f9e722 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -506,14 +506,6 @@ static inline void rtas_st(target_ulong phys, int n, uint32_t val)
stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
}
-static inline void rtas_st_buffer_direct(target_ulong phys,
- target_ulong phys_len,
- uint8_t *buffer, uint16_t buffer_len)
-{
- cpu_physical_memory_write(ppc64_phys_to_real(phys), buffer,
- MIN(buffer_len, phys_len));
-}
-
typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
uint32_t token,
uint32_t nargs, target_ulong args,
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 09/39] spapr: Remove abuse of rtas_ld() in h_client_architecture_support
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (8 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 08/39] spapr: Remove rtas_st_buffer_direct() David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 10/39] spapr: Don't create ibm, dynamic-reconfiguration-memory w/o DR LMBs David Gibson
` (29 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
h_client_architecture_support() uses rtas_ld() for general purpose memory
access, despite the fact that it's not an RTAS routine at all and rtas_ld
makes things more awkward.
Clean this up by replacing rtas_ld() calls with appropriate ldXX_phys()
calls.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr_hcall.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index cebceea..9dbdba9 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -861,7 +861,8 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
target_ulong opcode,
target_ulong *args)
{
- target_ulong list = args[0], ov_table;
+ target_ulong list = ppc64_phys_to_real(args[0]);
+ target_ulong ov_table, ov5;
PowerPCCPUClass *pcc_ = POWERPC_CPU_GET_CLASS(cpu_);
CPUState *cs;
bool cpu_match = false, cpu_update = true, memory_update = false;
@@ -875,9 +876,9 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
for (counter = 0; counter < 512; ++counter) {
uint32_t pvr, pvr_mask;
- pvr_mask = rtas_ld(list, 0);
+ pvr_mask = ldl_be_phys(&address_space_memory, list);
list += 4;
- pvr = rtas_ld(list, 0);
+ pvr = ldl_be_phys(&address_space_memory, list);
list += 4;
trace_spapr_cas_pvr_try(pvr);
@@ -948,14 +949,13 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
/* For the future use: here @ov_table points to the first option vector */
ov_table = list;
- list = cas_get_option_vector(5, ov_table);
- if (!list) {
+ ov5 = cas_get_option_vector(5, ov_table);
+ if (!ov5) {
return H_SUCCESS;
}
/* @list now points to OV 5 */
- list += 2;
- ov5_byte2 = rtas_ld(list, 0) >> 24;
+ ov5_byte2 = ldub_phys(&address_space_memory, ov5 + 2);
if (ov5_byte2 & OV5_DRCONF_MEMORY) {
memory_update = true;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 10/39] spapr: Don't create ibm, dynamic-reconfiguration-memory w/o DR LMBs
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (9 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 09/39] spapr: Remove abuse of rtas_ld() in h_client_architecture_support David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 11/39] ppc: Clean up error handling in ppc_set_compat() David Gibson
` (28 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, mdroth, qemu-devel, qemu-ppc, Bharata B Rao, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
If guest doesn't have any dynamically reconfigurable (DR) logical memory
blocks (LMB), then we shouldn't create ibm,dynamic-reconfiguration-memory
device tree node.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 50e5a26..86e5023 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -763,6 +763,13 @@ static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
/*
+ * Don't create the node if there are no DR LMBs.
+ */
+ if (!nr_lmbs) {
+ return 0;
+ }
+
+ /*
* Allocate enough buffer size to fit in ibm,dynamic-memory
* or ibm,associativity-lookup-arrays
*/
@@ -868,7 +875,7 @@ int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
_FDT((spapr_fixup_cpu_dt(fdt, spapr)));
}
- /* Generate memory nodes or ibm,dynamic-reconfiguration-memory node */
+ /* Generate ibm,dynamic-reconfiguration-memory node if required */
if (memory_update && smc->dr_lmb_enabled) {
_FDT((spapr_populate_drconf_memory(spapr, fdt)));
}
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 11/39] ppc: Clean up error handling in ppc_set_compat()
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (10 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 10/39] spapr: Don't create ibm, dynamic-reconfiguration-memory w/o DR LMBs David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 12/39] pseries: Clean up error handling of spapr_cpu_init() David Gibson
` (27 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
Current ppc_set_compat() returns -1 for errors, and also (unconditionally)
reports an error message. The caller in h_client_architecture_support()
may then report it again using an outdated fprintf().
Clean this up by using the modern error reporting mechanisms. Also add
strerror(errno) to the error message.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr.c | 4 +---
hw/ppc/spapr_hcall.c | 10 +++++-----
target-ppc/cpu.h | 2 +-
target-ppc/translate_init.c | 13 +++++++------
4 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 86e5023..672815f 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1642,9 +1642,7 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu)
}
if (cpu->max_compat) {
- if (ppc_set_compat(cpu, cpu->max_compat) < 0) {
- exit(1);
- }
+ ppc_set_compat(cpu, cpu->max_compat, &error_fatal);
}
xics_cpu_setup(spapr->icp, cpu);
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 9dbdba9..e9c057d 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -837,7 +837,7 @@ static target_ulong cas_get_option_vector(int vector, target_ulong table)
typedef struct {
PowerPCCPU *cpu;
uint32_t cpu_version;
- int ret;
+ Error *err;
} SetCompatState;
static void do_set_compat(void *arg)
@@ -845,7 +845,7 @@ static void do_set_compat(void *arg)
SetCompatState *s = arg;
cpu_synchronize_state(CPU(s->cpu));
- s->ret = ppc_set_compat(s->cpu, s->cpu_version);
+ ppc_set_compat(s->cpu, s->cpu_version, &s->err);
}
#define get_compat_level(cpuver) ( \
@@ -930,13 +930,13 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
SetCompatState s = {
.cpu = POWERPC_CPU(cs),
.cpu_version = cpu_version,
- .ret = 0
+ .err = NULL,
};
run_on_cpu(cs, do_set_compat, &s);
- if (s.ret < 0) {
- fprintf(stderr, "Unable to set compatibility mode\n");
+ if (s.err) {
+ error_report_err(s.err);
return H_HARDWARE;
}
}
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 9706000..b3b89e6 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1210,7 +1210,7 @@ void ppc_store_msr (CPUPPCState *env, target_ulong value);
void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
-int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version);
+void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp);
/* Time-base and decrementer management */
#ifndef NO_CPU_IO_DEFS
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d7e1a4e..4c61525 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -9186,7 +9186,7 @@ int ppc_get_compat_smt_threads(PowerPCCPU *cpu)
return ret;
}
-int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version)
+void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp)
{
int ret = 0;
CPUPPCState *env = &cpu->env;
@@ -9208,12 +9208,13 @@ int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version)
break;
}
- if (kvm_enabled() && kvmppc_set_compat(cpu, cpu->cpu_version) < 0) {
- error_report("Unable to set compatibility mode in KVM");
- ret = -1;
+ if (kvm_enabled()) {
+ ret = kvmppc_set_compat(cpu, cpu->cpu_version);
+ if (ret < 0) {
+ error_setg_errno(errp, -ret,
+ "Unable to set CPU compatibility mode in KVM");
+ }
}
-
- return ret;
}
static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 12/39] pseries: Clean up error handling of spapr_cpu_init()
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (11 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 11/39] ppc: Clean up error handling in ppc_set_compat() David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 13/39] pseries: Clean up error handling in spapr_validate_node_memory() David Gibson
` (26 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
Currently spapr_cpu_init() is hardcoded to handle any errors as fatal.
That works for now, since it's only called from initial setup where an
error here means we really can't proceed.
However, we'll want to handle this more flexibly for cpu hotplug in future
so generalize this using the error reporting infrastructure. While we're
at it make a small cleanup in a related part of ppc_spapr_init() to use
error_report() instead of an old-style explicit fprintf().
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 672815f..447fa5d 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1624,7 +1624,8 @@ static void spapr_boot_set(void *opaque, const char *boot_device,
machine->boot_order = g_strdup(boot_device);
}
-static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu)
+static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
+ Error **errp)
{
CPUPPCState *env = &cpu->env;
@@ -1642,7 +1643,13 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu)
}
if (cpu->max_compat) {
- ppc_set_compat(cpu, cpu->max_compat, &error_fatal);
+ Error *local_err = NULL;
+
+ ppc_set_compat(cpu, cpu->max_compat, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
}
xics_cpu_setup(spapr->icp, cpu);
@@ -1811,10 +1818,10 @@ static void ppc_spapr_init(MachineState *machine)
for (i = 0; i < smp_cpus; i++) {
cpu = cpu_ppc_init(machine->cpu_model);
if (cpu == NULL) {
- fprintf(stderr, "Unable to find PowerPC CPU definition\n");
+ error_report("Unable to find PowerPC CPU definition");
exit(1);
}
- spapr_cpu_init(spapr, cpu);
+ spapr_cpu_init(spapr, cpu, &error_fatal);
}
if (kvm_enabled()) {
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 13/39] pseries: Clean up error handling in spapr_validate_node_memory()
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (12 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 12/39] pseries: Clean up error handling of spapr_cpu_init() David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 14/39] pseries: Clean up error handling in spapr_vga_init() David Gibson
` (25 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
Use error_setg() and return an error, rather than using an explicit exit().
Also improve messages, and be more explicit about which constraint failed.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr.c | 37 ++++++++++++++++++++++---------------
1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 447fa5d..b20b109 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1698,27 +1698,34 @@ static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
* to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
* since we can't support such unaligned sizes with DRCONF_MEMORY.
*/
-static void spapr_validate_node_memory(MachineState *machine)
+static void spapr_validate_node_memory(MachineState *machine, Error **errp)
{
int i;
- if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE ||
- machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
- error_report("Can't support memory configuration where RAM size "
- "0x" RAM_ADDR_FMT " or maxmem size "
- "0x" RAM_ADDR_FMT " isn't aligned to %llu MB",
- machine->ram_size, machine->maxram_size,
- SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
- exit(EXIT_FAILURE);
+ if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
+ error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
+ " is not aligned to %llu MiB",
+ machine->ram_size,
+ SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
+ return;
+ }
+
+ if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
+ error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
+ " is not aligned to %llu MiB",
+ machine->ram_size,
+ SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
+ return;
}
for (i = 0; i < nb_numa_nodes; i++) {
if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
- error_report("Can't support memory configuration where memory size"
- " %" PRIx64 " of node %d isn't aligned to %llu MB",
- numa_info[i].node_mem, i,
- SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
- exit(EXIT_FAILURE);
+ error_setg(errp,
+ "Node %d memory size 0x%" PRIx64
+ " is not aligned to %llu MiB",
+ i, numa_info[i].node_mem,
+ SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
+ return;
}
}
}
@@ -1808,7 +1815,7 @@ static void ppc_spapr_init(MachineState *machine)
XICS_IRQS);
if (smc->dr_lmb_enabled) {
- spapr_validate_node_memory(machine);
+ spapr_validate_node_memory(machine, &error_fatal);
}
/* init CPUs */
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 14/39] pseries: Clean up error handling in spapr_vga_init()
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (13 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 13/39] pseries: Clean up error handling in spapr_validate_node_memory() David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 15/39] pseries: Clean up error handling in spapr_rtas_register() David Gibson
` (24 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
Use error_setg() to return an error rather than an explicit exit().
Previously it was an exit(0) instead of a non-zero exit code, which was
simply a bug. Also improve the error message.
While we're at it change the type of spapr_vga_init() to bool since that's
how we're using it anyway.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index b20b109..045c5a1 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1245,7 +1245,7 @@ static void spapr_rtc_create(sPAPRMachineState *spapr)
}
/* Returns whether we want to use VGA or not */
-static int spapr_vga_init(PCIBus *pci_bus)
+static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
{
switch (vga_interface_type) {
case VGA_NONE:
@@ -1256,9 +1256,9 @@ static int spapr_vga_init(PCIBus *pci_bus)
case VGA_VIRTIO:
return pci_vga_init(pci_bus) != NULL;
default:
- fprintf(stderr, "This vga model is not supported,"
- "currently it only supports -vga std\n");
- exit(0);
+ error_setg(errp,
+ "Unsupported VGA mode, only -vga std or -vga virtio is supported");
+ return false;
}
}
@@ -1933,7 +1933,7 @@ static void ppc_spapr_init(MachineState *machine)
}
/* Graphics */
- if (spapr_vga_init(phb->bus)) {
+ if (spapr_vga_init(phb->bus, &error_fatal)) {
spapr->has_graphics = true;
machine->usb |= defaults_enabled() && !machine->usb_disabled;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 15/39] pseries: Clean up error handling in spapr_rtas_register()
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (14 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 14/39] pseries: Clean up error handling in spapr_vga_init() David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 16/39] pseries: Clean up error handling in xics_system_init() David Gibson
` (23 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
The errors detected in this function necessarily indicate bugs in the rest
of the qemu code, rather than an external or configuration problem.
So, a simple assert() is more appropriate than any more complex error
reporting.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr_rtas.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index eac1556..130c917 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -664,17 +664,11 @@ target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *spapr,
void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn)
{
- if (!((token >= RTAS_TOKEN_BASE) && (token < RTAS_TOKEN_MAX))) {
- fprintf(stderr, "RTAS invalid token 0x%x\n", token);
- exit(1);
- }
+ assert((token >= RTAS_TOKEN_BASE) && (token < RTAS_TOKEN_MAX));
token -= RTAS_TOKEN_BASE;
- if (rtas_table[token].name) {
- fprintf(stderr, "RTAS call \"%s\" is registered already as 0x%x\n",
- rtas_table[token].name, token);
- exit(1);
- }
+
+ assert(!rtas_table[token].name);
rtas_table[token].name = name;
rtas_table[token].fn = fn;
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 16/39] pseries: Clean up error handling in xics_system_init()
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (15 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 15/39] pseries: Clean up error handling in spapr_rtas_register() David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 17/39] pseries: Clean up error reporting in ppc_spapr_init() David Gibson
` (22 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
Use the error handling infrastructure to pass an error out from
try_create_xics() instead of assuming &error_abort - the caller is in a
better position to decide on error handling policy.
Also change the error handling from an &error_abort to &error_fatal, since
this occurs during the initial machine construction and could be triggered
by bad configuration rather than a program error.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 045c5a1..59f0a16 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -111,7 +111,7 @@ static XICSState *try_create_xics(const char *type, int nr_servers,
}
static XICSState *xics_system_init(MachineState *machine,
- int nr_servers, int nr_irqs)
+ int nr_servers, int nr_irqs, Error **errp)
{
XICSState *icp = NULL;
@@ -130,7 +130,7 @@ static XICSState *xics_system_init(MachineState *machine,
}
if (!icp) {
- icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, &error_abort);
+ icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, errp);
}
return icp;
@@ -1812,7 +1812,7 @@ static void ppc_spapr_init(MachineState *machine)
spapr->icp = xics_system_init(machine,
DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(),
smp_threads),
- XICS_IRQS);
+ XICS_IRQS, &error_fatal);
if (smc->dr_lmb_enabled) {
spapr_validate_node_memory(machine, &error_fatal);
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 17/39] pseries: Clean up error reporting in ppc_spapr_init()
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (16 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 16/39] pseries: Clean up error handling in xics_system_init() David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 18/39] pseries: Clean up error reporting in htab migration functions David Gibson
` (21 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
This function includes a number of explicit fprintf()s for errors.
Change these to use error_report() instead.
Also replace the single exit(EXIT_FAILURE) with an explicit exit(1), since
the latter is the more usual idiom in qemu by a large margin.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 59f0a16..f8404d3 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1788,8 +1788,8 @@ static void ppc_spapr_init(MachineState *machine)
}
if (spapr->rma_size > node0_size) {
- fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n",
- spapr->rma_size);
+ error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
+ spapr->rma_size);
exit(1);
}
@@ -1855,10 +1855,10 @@ static void ppc_spapr_init(MachineState *machine)
ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
if (machine->ram_slots > SPAPR_MAX_RAM_SLOTS) {
- error_report("Specified number of memory slots %" PRIu64
- " exceeds max supported %d",
+ error_report("Specified number of memory slots %"
+ PRIu64" exceeds max supported %d",
machine->ram_slots, SPAPR_MAX_RAM_SLOTS);
- exit(EXIT_FAILURE);
+ exit(1);
}
spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
@@ -1954,8 +1954,9 @@ static void ppc_spapr_init(MachineState *machine)
}
if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
- fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
- "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
+ error_report(
+ "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
+ MIN_RMA_SLOF);
exit(1);
}
@@ -1971,8 +1972,8 @@ static void ppc_spapr_init(MachineState *machine)
kernel_le = kernel_size > 0;
}
if (kernel_size < 0) {
- fprintf(stderr, "qemu: error loading %s: %s\n",
- kernel_filename, load_elf_strerror(kernel_size));
+ error_report("error loading %s: %s",
+ kernel_filename, load_elf_strerror(kernel_size));
exit(1);
}
@@ -1985,8 +1986,8 @@ static void ppc_spapr_init(MachineState *machine)
initrd_size = load_image_targphys(initrd_filename, initrd_base,
load_limit - initrd_base);
if (initrd_size < 0) {
- fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
- initrd_filename);
+ error_report("could not load initial ram disk '%s'",
+ initrd_filename);
exit(1);
}
} else {
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 18/39] pseries: Clean up error reporting in htab migration functions
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (17 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 17/39] pseries: Clean up error reporting in ppc_spapr_init() David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 19/39] target-ppc: kvm: fix floating point registers sync on little-endian hosts David Gibson
` (20 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
The functions for migrating the hash page table on pseries machine type
(htab_save_setup() and htab_load()) can report some errors with an
explicit fprintf() before returning an appropriate error code. Change some
of these to use error_report() instead. htab_save_setup() is omitted for
now to avoid conflicts with some other in-progress work.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
---
hw/ppc/spapr.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index f8404d3..a9c9a95 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1533,7 +1533,7 @@ static int htab_load(QEMUFile *f, void *opaque, int version_id)
int fd = -1;
if (version_id < 1 || version_id > 1) {
- fprintf(stderr, "htab_load() bad version\n");
+ error_report("htab_load() bad version");
return -EINVAL;
}
@@ -1554,8 +1554,8 @@ static int htab_load(QEMUFile *f, void *opaque, int version_id)
fd = kvmppc_get_htab_fd(true);
if (fd < 0) {
- fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n",
- strerror(errno));
+ error_report("Unable to open fd to restore KVM hash table: %s",
+ strerror(errno));
}
}
@@ -1575,9 +1575,9 @@ static int htab_load(QEMUFile *f, void *opaque, int version_id)
if ((index + n_valid + n_invalid) >
(HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
/* Bad index in stream */
- fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) "
- "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid,
- spapr->htab_shift);
+ error_report(
+ "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
+ index, n_valid, n_invalid, spapr->htab_shift);
return -EINVAL;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 19/39] target-ppc: kvm: fix floating point registers sync on little-endian hosts
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (18 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 18/39] pseries: Clean up error reporting in htab migration functions David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 20/39] target-ppc: rename and export maybe_bswap_register() David Gibson
` (19 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson, Greg Kurz
From: Greg Kurz <gkurz@linux.vnet.ibm.com>
On VSX capable CPUs, the 32 FP registers are mapped to the high-bits
of the 32 first VSX registers. So if you have:
VSR31 = (uint128) 0x0102030405060708090a0b0c0d0e0f00
then
FPR31 = (uint64) 0x0102030405060708
The kernel stores the VSX registers in the fp_state struct following the
host endian element ordering.
On big-endian:
fp_state.fpr[31][0] = 0x0102030405060708
fp_state.fpr[31][1] = 0x090a0b0c0d0e0f00
On little-endian:
fp_state.fpr[31][0] = 0x090a0b0c0d0e0f00
fp_state.fpr[31][1] = 0x0102030405060708
The KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls preserve this ordering, but
QEMU considers it as big-endian and always copies element [0] to the
fpr[] array and element [1] to the vsr[] array. This does not work with
little-endian hosts, and you will get:
(qemu) p $f31
0x90a0b0c0d0e0f00
instead of:
(qemu) p $f31
0x102030405060708
This patch fixes the element ordering for little-endian hosts.
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/kvm.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 9940a90..4524999 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -650,8 +650,13 @@ static int kvm_put_fp(CPUState *cs)
for (i = 0; i < 32; i++) {
uint64_t vsr[2];
+#ifdef HOST_WORDS_BIGENDIAN
vsr[0] = float64_val(env->fpr[i]);
vsr[1] = env->vsr[i];
+#else
+ vsr[0] = env->vsr[i];
+ vsr[1] = float64_val(env->fpr[i]);
+#endif
reg.addr = (uintptr_t) &vsr;
reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
@@ -721,10 +726,17 @@ static int kvm_get_fp(CPUState *cs)
vsx ? "VSR" : "FPR", i, strerror(errno));
return ret;
} else {
+#ifdef HOST_WORDS_BIGENDIAN
env->fpr[i] = vsr[0];
if (vsx) {
env->vsr[i] = vsr[1];
}
+#else
+ env->fpr[i] = vsr[1];
+ if (vsx) {
+ env->vsr[i] = vsr[0];
+ }
+#endif
}
}
}
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 20/39] target-ppc: rename and export maybe_bswap_register()
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (19 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 19/39] target-ppc: kvm: fix floating point registers sync on little-endian hosts David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 21/39] target-ppc: gdbstub: fix float registers for little-endian guests David Gibson
` (18 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson, Greg Kurz
From: Greg Kurz <gkurz@linux.vnet.ibm.com>
This helper will be used to support FP, Altivec and VSX registers when
the guest is little-endian.
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/cpu.h | 1 +
target-ppc/gdbstub.c | 10 +++++-----
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index b3b89e6..2bc96b4 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2355,4 +2355,5 @@ int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
*/
PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
+void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
#endif /* !defined (__CPU_PPC_H__) */
diff --git a/target-ppc/gdbstub.c b/target-ppc/gdbstub.c
index 14675f4..b20bb0c 100644
--- a/target-ppc/gdbstub.c
+++ b/target-ppc/gdbstub.c
@@ -88,7 +88,7 @@ static int ppc_gdb_register_len(int n)
the proper ordering for the binary, and cannot be changed.
For system mode, TARGET_WORDS_BIGENDIAN is always set, and we must check
the current mode of the chip to see if we're running in little-endian. */
-static void maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
+void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
{
#ifndef CONFIG_USER_ONLY
if (!msr_le) {
@@ -158,7 +158,7 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
break;
}
}
- maybe_bswap_register(env, mem_buf, r);
+ ppc_maybe_bswap_register(env, mem_buf, r);
return r;
}
@@ -214,7 +214,7 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
break;
}
}
- maybe_bswap_register(env, mem_buf, r);
+ ppc_maybe_bswap_register(env, mem_buf, r);
return r;
}
@@ -227,7 +227,7 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
if (!r) {
return r;
}
- maybe_bswap_register(env, mem_buf, r);
+ ppc_maybe_bswap_register(env, mem_buf, r);
if (n < 32) {
/* gprs */
env->gpr[n] = ldtul_p(mem_buf);
@@ -277,7 +277,7 @@ int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
if (!r) {
return r;
}
- maybe_bswap_register(env, mem_buf, r);
+ ppc_maybe_bswap_register(env, mem_buf, r);
if (n < 32) {
/* gprs */
env->gpr[n] = ldq_p(mem_buf);
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 21/39] target-ppc: gdbstub: fix float registers for little-endian guests
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (20 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 20/39] target-ppc: rename and export maybe_bswap_register() David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 22/39] target-ppc: gdbstub: introduce avr_need_swap() David Gibson
` (17 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson, Greg Kurz
From: Greg Kurz <gkurz@linux.vnet.ibm.com>
Let's reuse the ppc_maybe_bswap_register() helper, like we already do
with the general registers.
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/translate_init.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4c61525..26b9b67 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8755,10 +8755,12 @@ static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
stfq_p(mem_buf, env->fpr[n]);
+ ppc_maybe_bswap_register(env, mem_buf, 8);
return 8;
}
if (n == 32) {
stl_p(mem_buf, env->fpscr);
+ ppc_maybe_bswap_register(env, mem_buf, 4);
return 4;
}
return 0;
@@ -8767,10 +8769,12 @@ static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 8);
env->fpr[n] = ldfq_p(mem_buf);
return 8;
}
if (n == 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 4);
helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
return 4;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 22/39] target-ppc: gdbstub: introduce avr_need_swap()
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (21 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 21/39] target-ppc: gdbstub: fix float registers for little-endian guests David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 23/39] target-ppc: gdbstub: fix altivec registers for little-endian guests David Gibson
` (16 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson, Greg Kurz
From: Greg Kurz <gkurz@linux.vnet.ibm.com>
This helper will be used to support Altivec registers in little-endian guests.
This patch does not change functionnality.
Note: I had to put the helper some lines away from the gdb_*_avr_reg()
routines to get a more readable patch.
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/translate_init.c | 37 +++++++++++++++++++++++--------------
1 file changed, 23 insertions(+), 14 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 26b9b67..41308c3 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8751,6 +8751,15 @@ static void dump_ppc_insns (CPUPPCState *env)
}
#endif
+static bool avr_need_swap(CPUPPCState *env)
+{
+#ifdef HOST_WORDS_BIGENDIAN
+ return false;
+#else
+ return true;
+#endif
+}
+
static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
@@ -8784,13 +8793,13 @@ static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
-#ifdef HOST_WORDS_BIGENDIAN
- stq_p(mem_buf, env->avr[n].u64[0]);
- stq_p(mem_buf+8, env->avr[n].u64[1]);
-#else
- stq_p(mem_buf, env->avr[n].u64[1]);
- stq_p(mem_buf+8, env->avr[n].u64[0]);
-#endif
+ if (!avr_need_swap(env)) {
+ stq_p(mem_buf, env->avr[n].u64[0]);
+ stq_p(mem_buf+8, env->avr[n].u64[1]);
+ } else {
+ stq_p(mem_buf, env->avr[n].u64[1]);
+ stq_p(mem_buf+8, env->avr[n].u64[0]);
+ }
return 16;
}
if (n == 32) {
@@ -8807,13 +8816,13 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
-#ifdef HOST_WORDS_BIGENDIAN
- env->avr[n].u64[0] = ldq_p(mem_buf);
- env->avr[n].u64[1] = ldq_p(mem_buf+8);
-#else
- env->avr[n].u64[1] = ldq_p(mem_buf);
- env->avr[n].u64[0] = ldq_p(mem_buf+8);
-#endif
+ if (!avr_need_swap(env)) {
+ env->avr[n].u64[0] = ldq_p(mem_buf);
+ env->avr[n].u64[1] = ldq_p(mem_buf+8);
+ } else {
+ env->avr[n].u64[1] = ldq_p(mem_buf);
+ env->avr[n].u64[0] = ldq_p(mem_buf+8);
+ }
return 16;
}
if (n == 32) {
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 23/39] target-ppc: gdbstub: fix altivec registers for little-endian guests
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (22 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 22/39] target-ppc: gdbstub: introduce avr_need_swap() David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 24/39] target-ppc: gdbstub: fix spe " David Gibson
` (15 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson, Greg Kurz
From: Greg Kurz <gkurz@linux.vnet.ibm.com>
Altivec registers are 128-bit wide. They are stored in memory as two
64-bit values that must be byteswapped when the guest is little-endian.
Let's reuse the ppc_maybe_bswap_register() helper for this.
We also need to fix the ordering of the 64-bit elements according to
the target endianness, for both system and user mode.
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/translate_init.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 41308c3..02734a2 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8754,9 +8754,9 @@ static void dump_ppc_insns (CPUPPCState *env)
static bool avr_need_swap(CPUPPCState *env)
{
#ifdef HOST_WORDS_BIGENDIAN
- return false;
+ return msr_le;
#else
- return true;
+ return !msr_le;
#endif
}
@@ -8800,14 +8800,18 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
stq_p(mem_buf, env->avr[n].u64[1]);
stq_p(mem_buf+8, env->avr[n].u64[0]);
}
+ ppc_maybe_bswap_register(env, mem_buf, 8);
+ ppc_maybe_bswap_register(env, mem_buf + 8, 8);
return 16;
}
if (n == 32) {
stl_p(mem_buf, env->vscr);
+ ppc_maybe_bswap_register(env, mem_buf, 4);
return 4;
}
if (n == 33) {
stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
+ ppc_maybe_bswap_register(env, mem_buf, 4);
return 4;
}
return 0;
@@ -8816,6 +8820,8 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 8);
+ ppc_maybe_bswap_register(env, mem_buf + 8, 8);
if (!avr_need_swap(env)) {
env->avr[n].u64[0] = ldq_p(mem_buf);
env->avr[n].u64[1] = ldq_p(mem_buf+8);
@@ -8826,10 +8832,12 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
return 16;
}
if (n == 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 4);
env->vscr = ldl_p(mem_buf);
return 4;
}
if (n == 33) {
+ ppc_maybe_bswap_register(env, mem_buf, 4);
env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
return 4;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 24/39] target-ppc: gdbstub: fix spe registers for little-endian guests
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (23 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 23/39] target-ppc: gdbstub: fix altivec registers for little-endian guests David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 25/39] target-ppc: gdbstub: Add VSX support David Gibson
` (14 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson, Greg Kurz
From: Greg Kurz <gkurz@linux.vnet.ibm.com>
Let's reuse the ppc_maybe_bswap_register() helper, like we already do
with the general registers.
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/translate_init.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 02734a2..83942fe 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8849,6 +8849,7 @@ static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
if (n < 32) {
#if defined(TARGET_PPC64)
stl_p(mem_buf, env->gpr[n] >> 32);
+ ppc_maybe_bswap_register(env, mem_buf, 4);
#else
stl_p(mem_buf, env->gprh[n]);
#endif
@@ -8856,10 +8857,12 @@ static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
}
if (n == 32) {
stq_p(mem_buf, env->spe_acc);
+ ppc_maybe_bswap_register(env, mem_buf, 8);
return 8;
}
if (n == 33) {
stl_p(mem_buf, env->spe_fscr);
+ ppc_maybe_bswap_register(env, mem_buf, 4);
return 4;
}
return 0;
@@ -8870,7 +8873,11 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
if (n < 32) {
#if defined(TARGET_PPC64)
target_ulong lo = (uint32_t)env->gpr[n];
- target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
+ target_ulong hi;
+
+ ppc_maybe_bswap_register(env, mem_buf, 4);
+
+ hi = (target_ulong)ldl_p(mem_buf) << 32;
env->gpr[n] = lo | hi;
#else
env->gprh[n] = ldl_p(mem_buf);
@@ -8878,10 +8885,12 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
return 4;
}
if (n == 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 8);
env->spe_acc = ldq_p(mem_buf);
return 8;
}
if (n == 33) {
+ ppc_maybe_bswap_register(env, mem_buf, 4);
env->spe_fscr = ldl_p(mem_buf);
return 4;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 25/39] target-ppc: gdbstub: Add VSX support
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (24 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 24/39] target-ppc: gdbstub: fix spe " David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 26/39] pseries: Allow TCG h_enter to work with hotplugged memory David Gibson
` (13 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, mdroth, qemu-devel, qemu-ppc, Anton Blanchard, David Gibson,
Greg Kurz
From: Anton Blanchard <anton@samba.org>
Add the XML and functions to get and set VSX registers.
Signed-off-by: Anton Blanchard <anton@samba.org>
(fixed little-endian guests)
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
configure | 6 +++---
gdb-xml/power-vsx.xml | 44 ++++++++++++++++++++++++++++++++++++++++++++
target-ppc/translate_init.c | 24 ++++++++++++++++++++++++
3 files changed, 71 insertions(+), 3 deletions(-)
create mode 100644 gdb-xml/power-vsx.xml
diff --git a/configure b/configure
index 3506e44..297bfc7 100755
--- a/configure
+++ b/configure
@@ -5702,20 +5702,20 @@ case "$target_name" in
ppc64)
TARGET_BASE_ARCH=ppc
TARGET_ABI_DIR=ppc
- gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml"
+ gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
;;
ppc64le)
TARGET_ARCH=ppc64
TARGET_BASE_ARCH=ppc
TARGET_ABI_DIR=ppc
- gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml"
+ gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
;;
ppc64abi32)
TARGET_ARCH=ppc64
TARGET_BASE_ARCH=ppc
TARGET_ABI_DIR=ppc
echo "TARGET_ABI32=y" >> $config_target_mak
- gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml"
+ gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
;;
sh4|sh4eb)
TARGET_ARCH=sh4
diff --git a/gdb-xml/power-vsx.xml b/gdb-xml/power-vsx.xml
new file mode 100644
index 0000000..fd290e9
--- /dev/null
+++ b/gdb-xml/power-vsx.xml
@@ -0,0 +1,44 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2008-2015 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- POWER7 VSX registers that do not overlap existing FP and VMX
+ registers. -->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.power.vsx">
+ <reg name="vs0h" bitsize="64" type="uint64"/>
+ <reg name="vs1h" bitsize="64" type="uint64"/>
+ <reg name="vs2h" bitsize="64" type="uint64"/>
+ <reg name="vs3h" bitsize="64" type="uint64"/>
+ <reg name="vs4h" bitsize="64" type="uint64"/>
+ <reg name="vs5h" bitsize="64" type="uint64"/>
+ <reg name="vs6h" bitsize="64" type="uint64"/>
+ <reg name="vs7h" bitsize="64" type="uint64"/>
+ <reg name="vs8h" bitsize="64" type="uint64"/>
+ <reg name="vs9h" bitsize="64" type="uint64"/>
+ <reg name="vs10h" bitsize="64" type="uint64"/>
+ <reg name="vs11h" bitsize="64" type="uint64"/>
+ <reg name="vs12h" bitsize="64" type="uint64"/>
+ <reg name="vs13h" bitsize="64" type="uint64"/>
+ <reg name="vs14h" bitsize="64" type="uint64"/>
+ <reg name="vs15h" bitsize="64" type="uint64"/>
+ <reg name="vs16h" bitsize="64" type="uint64"/>
+ <reg name="vs17h" bitsize="64" type="uint64"/>
+ <reg name="vs18h" bitsize="64" type="uint64"/>
+ <reg name="vs19h" bitsize="64" type="uint64"/>
+ <reg name="vs20h" bitsize="64" type="uint64"/>
+ <reg name="vs21h" bitsize="64" type="uint64"/>
+ <reg name="vs22h" bitsize="64" type="uint64"/>
+ <reg name="vs23h" bitsize="64" type="uint64"/>
+ <reg name="vs24h" bitsize="64" type="uint64"/>
+ <reg name="vs25h" bitsize="64" type="uint64"/>
+ <reg name="vs26h" bitsize="64" type="uint64"/>
+ <reg name="vs27h" bitsize="64" type="uint64"/>
+ <reg name="vs28h" bitsize="64" type="uint64"/>
+ <reg name="vs29h" bitsize="64" type="uint64"/>
+ <reg name="vs30h" bitsize="64" type="uint64"/>
+ <reg name="vs31h" bitsize="64" type="uint64"/>
+</feature>
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 83942fe..156d156 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8897,6 +8897,26 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
return 0;
}
+static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ stq_p(mem_buf, env->vsr[n]);
+ ppc_maybe_bswap_register(env, mem_buf, 8);
+ return 8;
+ }
+ return 0;
+}
+
+static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 8);
+ env->vsr[n] = ldq_p(mem_buf);
+ return 8;
+ }
+ return 0;
+}
+
static int ppc_fixup_cpu(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
@@ -9002,6 +9022,10 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
34, "power-spe.xml", 0);
}
+ if (pcc->insns_flags2 & PPC2_VSX) {
+ gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
+ 32, "power-vsx.xml", 0);
+ }
qemu_init_vcpu(cs);
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 26/39] pseries: Allow TCG h_enter to work with hotplugged memory
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (25 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 25/39] target-ppc: gdbstub: Add VSX support David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:06 ` [Qemu-devel] [PULL 27/39] cuda.c: return error for unknown commands David Gibson
` (12 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
The implementation of the H_ENTER hypercall for PAPR guests needs to
enforce correct access attributes on the inserted HPTE. This means
determining if the HPTE's real address is a regular RAM address (which
requires attributes for coherent access) or an IO address (which requires
attributes for cache-inhibited access).
At the moment this check is implemented with (raddr < machine->ram_size),
but that only handles addresses in the base RAM area, not any hotplugged
RAM.
This patch corrects the problem with a new helper.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr_hcall.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index e9c057d..c4ae255 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -84,10 +84,25 @@ static inline bool valid_pte_index(CPUPPCState *env, target_ulong pte_index)
return true;
}
+static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr)
+{
+ MachineState *machine = MACHINE(spapr);
+ MemoryHotplugState *hpms = &spapr->hotplug_memory;
+
+ if (addr < machine->ram_size) {
+ return true;
+ }
+ if ((addr >= hpms->base)
+ && ((addr - hpms->base) < memory_region_size(&hpms->mr))) {
+ return true;
+ }
+
+ return false;
+}
+
static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- MachineState *machine = MACHINE(spapr);
CPUPPCState *env = &cpu->env;
target_ulong flags = args[0];
target_ulong pte_index = args[1];
@@ -119,7 +134,7 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << page_shift) - 1);
- if (raddr < machine->ram_size) {
+ if (is_ram_address(spapr, raddr)) {
/* Regular RAM - should have WIMG=0010 */
if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) {
return H_PARAMETER;
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 27/39] cuda.c: return error for unknown commands
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (26 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 26/39] pseries: Allow TCG h_enter to work with hotplugged memory David Gibson
@ 2016-01-29 5:06 ` David Gibson
2016-01-29 5:07 ` [Qemu-devel] [PULL 28/39] uninorth.c: add support for UniNorth kMacRISCPCIAddressSelect (0x48) register David Gibson
` (11 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:06 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, mdroth, qemu-devel, Alyssa Milburn, qemu-ppc, David Gibson
From: Alyssa Milburn <fuzzie@fuzzie.org>
This avoids MacsBug hanging at startup in the absence of ADB mouse
input, by replying with an error (which is also what MOL does) when
it sends an unknown command (0x1c).
Signed-off-by: Alyssa Milburn <fuzzie@fuzzie.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/misc/macio/cuda.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c
index 3556852..5e4d5d5 100644
--- a/hw/misc/macio/cuda.c
+++ b/hw/misc/macio/cuda.c
@@ -605,6 +605,11 @@ static void cuda_receive_packet(CUDAState *s,
}
break;
default:
+ obuf[0] = ERROR_PACKET;
+ obuf[1] = 0x2;
+ obuf[2] = CUDA_PACKET;
+ obuf[3] = data[0];
+ cuda_send_packet_to_host(s, obuf, 4);
break;
}
}
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 28/39] uninorth.c: add support for UniNorth kMacRISCPCIAddressSelect (0x48) register
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (27 preceding siblings ...)
2016-01-29 5:06 ` [Qemu-devel] [PULL 27/39] cuda.c: return error for unknown commands David Gibson
@ 2016-01-29 5:07 ` David Gibson
2016-01-29 5:07 ` [Qemu-devel] [PULL 29/39] target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub David Gibson
` (10 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:07 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, mdroth, qemu-devel, Programmingkid, qemu-ppc, David Gibson
From: Programmingkid <programmingkidx@gmail.com>
Darwin/OS X use the undocumented kMacRISCPCIAddressSelect (0x48) to
configure PCI memory space size for mac99 machines. Without this
register, warnings similar to below are emitted to the console during boot:
AppleMacRiscPCI: bad range 2(80000000:01000000)
AppleMacRiscPCI: bad range 2(81000000:00001000)
AppleMacRiscPCI: bad range 2(81080000:00080000)
Based upon the algorithm in Darwin's AppleMacRiscPCI.cpp driver, set the
kMacRISCPCIAddressSelect register so that Darwin considers the PCI
memory space to be at 0x80000000 (size 0x10000000) which matches that
currently used by QEMU and OpenBIOS.
Signed-off-by: John Arbuckle <programmingkidx@gmail.com>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
[commit message and comment revised as suggested by Mark Cave-Ayland]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index 215b64f..d4aff84 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -330,6 +330,15 @@ static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
// d->config[0x34] = 0x80; // capabilities_pointer
+ /*
+ * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
+ * memory space with base 0x80000000, size 0x10000000 for Apple's
+ * AppleMacRiscPCI driver
+ */
+ d->config[0x48] = 0x0;
+ d->config[0x49] = 0x0;
+ d->config[0x4a] = 0x0;
+ d->config[0x4b] = 0x1;
}
static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 29/39] target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (28 preceding siblings ...)
2016-01-29 5:07 ` [Qemu-devel] [PULL 28/39] uninorth.c: add support for UniNorth kMacRISCPCIAddressSelect (0x48) register David Gibson
@ 2016-01-29 5:07 ` David Gibson
2016-01-29 5:07 ` [Qemu-devel] [PULL 30/39] target-ppc: Convert mmu-hash{32, 64}.[ch] from CPUPPCState to PowerPCCPU David Gibson
` (9 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:07 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
This stub function is in the !KVM ifdef in target-ppc/kvm_ppc.h. However
no such function exists on the KVM side, or is ever used.
I think this originally referenced a function which read host page size
information from /proc, for we we now use the KVM GET_SMMU_INFO extension
instead.
In any case, it has no function now, so remove it.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
---
target-ppc/kvm_ppc.h | 5 -----
1 file changed, 5 deletions(-)
diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h
index 5e1333d..62406ce 100644
--- a/target-ppc/kvm_ppc.h
+++ b/target-ppc/kvm_ppc.h
@@ -98,11 +98,6 @@ static inline int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_l
return -1;
}
-static inline int kvmppc_read_segment_page_sizes(uint32_t *prop, int maxcells)
-{
- return -1;
-}
-
static inline int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
{
return -1;
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 30/39] target-ppc: Convert mmu-hash{32, 64}.[ch] from CPUPPCState to PowerPCCPU
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (29 preceding siblings ...)
2016-01-29 5:07 ` [Qemu-devel] [PULL 29/39] target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub David Gibson
@ 2016-01-29 5:07 ` David Gibson
2016-01-29 5:07 ` [Qemu-devel] [PULL 31/39] target-ppc: Rework ppc_store_slb David Gibson
` (8 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:07 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
Like a lot of places these files include a mixture of functions taking
both the older CPUPPCState *env and newer PowerPCCPU *cpu. Move a step
closer to cleaning this up by standardizing on PowerPCCPU, except for the
helper_* functions which are called with the CPUPPCState * from tcg.
Callers and some related functions are updated as well, the boundaries of
what's changed here are a bit arbitrary.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/spapr_hcall.c | 31 ++++++++++---------
target-ppc/kvm.c | 2 +-
target-ppc/mmu-hash32.c | 68 +++++++++++++++++++++++------------------
target-ppc/mmu-hash32.h | 30 ++++++++++---------
target-ppc/mmu-hash64.c | 80 +++++++++++++++++++++++++++++--------------------
target-ppc/mmu-hash64.h | 21 ++++++-------
target-ppc/mmu_helper.c | 13 ++++----
7 files changed, 136 insertions(+), 109 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index c4ae255..4707196 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -160,7 +160,7 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
pte_index &= ~7ULL;
token = ppc_hash64_start_access(cpu, pte_index);
for (; index < 8; index++) {
- if ((ppc_hash64_load_hpte0(env, token, index) & HPTE64_V_VALID) == 0) {
+ if (!(ppc_hash64_load_hpte0(cpu, token, index) & HPTE64_V_VALID)) {
break;
}
}
@@ -170,14 +170,14 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
}
} else {
token = ppc_hash64_start_access(cpu, pte_index);
- if (ppc_hash64_load_hpte0(env, token, 0) & HPTE64_V_VALID) {
+ if (ppc_hash64_load_hpte0(cpu, token, 0) & HPTE64_V_VALID) {
ppc_hash64_stop_access(token);
return H_PTEG_FULL;
}
ppc_hash64_stop_access(token);
}
- ppc_hash64_store_hpte(env, pte_index + index,
+ ppc_hash64_store_hpte(cpu, pte_index + index,
pteh | HPTE64_V_HPTE_DIRTY, ptel);
args[0] = pte_index + index;
@@ -191,11 +191,12 @@ typedef enum {
REMOVE_HW = 3,
} RemoveResult;
-static RemoveResult remove_hpte(CPUPPCState *env, target_ulong ptex,
+static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex,
target_ulong avpn,
target_ulong flags,
target_ulong *vp, target_ulong *rp)
{
+ CPUPPCState *env = &cpu->env;
uint64_t token;
target_ulong v, r, rb;
@@ -203,9 +204,9 @@ static RemoveResult remove_hpte(CPUPPCState *env, target_ulong ptex,
return REMOVE_PARM;
}
- token = ppc_hash64_start_access(ppc_env_get_cpu(env), ptex);
- v = ppc_hash64_load_hpte0(env, token, 0);
- r = ppc_hash64_load_hpte1(env, token, 0);
+ token = ppc_hash64_start_access(cpu, ptex);
+ v = ppc_hash64_load_hpte0(cpu, token, 0);
+ r = ppc_hash64_load_hpte1(cpu, token, 0);
ppc_hash64_stop_access(token);
if ((v & HPTE64_V_VALID) == 0 ||
@@ -215,7 +216,7 @@ static RemoveResult remove_hpte(CPUPPCState *env, target_ulong ptex,
}
*vp = v;
*rp = r;
- ppc_hash64_store_hpte(env, ptex, HPTE64_V_HPTE_DIRTY, 0);
+ ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0);
rb = compute_tlbie_rb(v, r, ptex);
ppc_tlb_invalidate_one(env, rb);
return REMOVE_SUCCESS;
@@ -224,13 +225,12 @@ static RemoveResult remove_hpte(CPUPPCState *env, target_ulong ptex,
static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- CPUPPCState *env = &cpu->env;
target_ulong flags = args[0];
target_ulong pte_index = args[1];
target_ulong avpn = args[2];
RemoveResult ret;
- ret = remove_hpte(env, pte_index, avpn, flags,
+ ret = remove_hpte(cpu, pte_index, avpn, flags,
&args[0], &args[1]);
switch (ret) {
@@ -271,7 +271,6 @@ static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,
static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- CPUPPCState *env = &cpu->env;
int i;
for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {
@@ -293,7 +292,7 @@ static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,
return H_PARAMETER;
}
- ret = remove_hpte(env, *tsh & H_BULK_REMOVE_PTEX, tsl,
+ ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl,
(*tsh & H_BULK_REMOVE_FLAGS) >> 26,
&v, &r);
@@ -330,8 +329,8 @@ static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr,
}
token = ppc_hash64_start_access(cpu, pte_index);
- v = ppc_hash64_load_hpte0(env, token, 0);
- r = ppc_hash64_load_hpte1(env, token, 0);
+ v = ppc_hash64_load_hpte0(cpu, token, 0);
+ r = ppc_hash64_load_hpte1(cpu, token, 0);
ppc_hash64_stop_access(token);
if ((v & HPTE64_V_VALID) == 0 ||
@@ -345,11 +344,11 @@ static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr,
r |= (flags << 48) & HPTE64_R_KEY_HI;
r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
rb = compute_tlbie_rb(v, r, pte_index);
- ppc_hash64_store_hpte(env, pte_index,
+ ppc_hash64_store_hpte(cpu, pte_index,
(v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0);
ppc_tlb_invalidate_one(env, rb);
/* Don't need a memory barrier, due to qemu's global lock */
- ppc_hash64_store_hpte(env, pte_index, v | HPTE64_V_HPTE_DIRTY, r);
+ ppc_hash64_store_hpte(cpu, pte_index, v | HPTE64_V_HPTE_DIRTY, r);
return H_SUCCESS;
}
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 4524999..98d7ba6 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -1205,7 +1205,7 @@ int kvm_arch_get_registers(CPUState *cs)
* Only restore valid entries
*/
if (rb & SLB_ESID_V) {
- ppc_store_slb(env, rb, rs);
+ ppc_store_slb(cpu, rb, rs);
}
}
#endif
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index a00ae3c..4497480 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -83,9 +83,10 @@ static int ppc_hash32_pp_prot(int key, int pp, int nx)
return prot;
}
-static int ppc_hash32_pte_prot(CPUPPCState *env,
+static int ppc_hash32_pte_prot(PowerPCCPU *cpu,
target_ulong sr, ppc_hash_pte32_t pte)
{
+ CPUPPCState *env = &cpu->env;
unsigned pp, key;
key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
@@ -94,9 +95,11 @@ static int ppc_hash32_pte_prot(CPUPPCState *env,
return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
}
-static target_ulong hash32_bat_size(CPUPPCState *env,
+static target_ulong hash32_bat_size(PowerPCCPU *cpu,
target_ulong batu, target_ulong batl)
{
+ CPUPPCState *env = &cpu->env;
+
if ((msr_pr && !(batu & BATU32_VP))
|| (!msr_pr && !(batu & BATU32_VS))) {
return 0;
@@ -105,7 +108,7 @@ static target_ulong hash32_bat_size(CPUPPCState *env,
return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
}
-static int hash32_bat_prot(CPUPPCState *env,
+static int hash32_bat_prot(PowerPCCPU *cpu,
target_ulong batu, target_ulong batl)
{
int pp, prot;
@@ -121,7 +124,7 @@ static int hash32_bat_prot(CPUPPCState *env,
return prot;
}
-static target_ulong hash32_bat_601_size(CPUPPCState *env,
+static target_ulong hash32_bat_601_size(PowerPCCPU *cpu,
target_ulong batu, target_ulong batl)
{
if (!(batl & BATL32_601_V)) {
@@ -131,9 +134,10 @@ static target_ulong hash32_bat_601_size(CPUPPCState *env,
return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17);
}
-static int hash32_bat_601_prot(CPUPPCState *env,
+static int hash32_bat_601_prot(PowerPCCPU *cpu,
target_ulong batu, target_ulong batl)
{
+ CPUPPCState *env = &cpu->env;
int key, pp;
pp = batu & BATU32_601_PP;
@@ -145,9 +149,10 @@ static int hash32_bat_601_prot(CPUPPCState *env,
return ppc_hash32_pp_prot(key, pp, 0);
}
-static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
+static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, target_ulong ea, int rwx,
int *prot)
{
+ CPUPPCState *env = &cpu->env;
target_ulong *BATlt, *BATut;
int i;
@@ -166,9 +171,9 @@ static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
target_ulong mask;
if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
- mask = hash32_bat_601_size(env, batu, batl);
+ mask = hash32_bat_601_size(cpu, batu, batl);
} else {
- mask = hash32_bat_size(env, batu, batl);
+ mask = hash32_bat_size(cpu, batu, batl);
}
LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
" BATl " TARGET_FMT_lx "\n", __func__,
@@ -178,9 +183,9 @@ static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
hwaddr raddr = (batl & mask) | (ea & ~mask);
if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
- *prot = hash32_bat_601_prot(env, batu, batl);
+ *prot = hash32_bat_601_prot(cpu, batu, batl);
} else {
- *prot = hash32_bat_prot(env, batu, batl);
+ *prot = hash32_bat_prot(cpu, batu, batl);
}
return raddr & TARGET_PAGE_MASK;
@@ -209,11 +214,12 @@ static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
return -1;
}
-static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
+static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr,
target_ulong eaddr, int rwx,
hwaddr *raddr, int *prot)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
qemu_log_mask(CPU_LOG_MMU, "direct store...\n");
@@ -293,12 +299,14 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
}
}
-hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash)
+hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash)
{
+ CPUPPCState *env = &cpu->env;
+
return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
}
-static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
+static hwaddr ppc_hash32_pteg_search(PowerPCCPU *cpu, hwaddr pteg_off,
bool secondary, target_ulong ptem,
ppc_hash_pte32_t *pte)
{
@@ -307,8 +315,8 @@ static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
int i;
for (i = 0; i < HPTES_PER_GROUP; i++) {
- pte0 = ppc_hash32_load_hpte0(env, pte_offset);
- pte1 = ppc_hash32_load_hpte1(env, pte_offset);
+ pte0 = ppc_hash32_load_hpte0(cpu, pte_offset);
+ pte1 = ppc_hash32_load_hpte1(cpu, pte_offset);
if ((pte0 & HPTE32_V_VALID)
&& (secondary == !!(pte0 & HPTE32_V_SECONDARY))
@@ -324,10 +332,11 @@ static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
return -1;
}
-static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
+static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu,
target_ulong sr, target_ulong eaddr,
ppc_hash_pte32_t *pte)
{
+ CPUPPCState *env = &cpu->env;
hwaddr pteg_off, pte_offset;
hwaddr hash;
uint32_t vsid, pgidx, ptem;
@@ -348,16 +357,16 @@ static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
" vsid=%" PRIx32 " ptem=%" PRIx32
" hash=" TARGET_FMT_plx "\n",
env->htab_base, env->htab_mask, vsid, ptem, hash);
- pteg_off = get_pteg_offset32(env, hash);
- pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
+ pteg_off = get_pteg_offset32(cpu, hash);
+ pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 0, ptem, pte);
if (pte_offset == -1) {
/* Secondary PTEG lookup */
qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
" vsid=%" PRIx32 " api=%" PRIx32
" hash=" TARGET_FMT_plx "\n", env->htab_base,
env->htab_mask, vsid, ptem, ~hash);
- pteg_off = get_pteg_offset32(env, ~hash);
- pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, pte);
+ pteg_off = get_pteg_offset32(cpu, ~hash);
+ pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 1, ptem, pte);
}
return pte_offset;
@@ -399,7 +408,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
/* 2. Check Block Address Translation entries (BATs) */
if (env->nb_BATs != 0) {
- raddr = ppc_hash32_bat_lookup(env, eaddr, rwx, &prot);
+ raddr = ppc_hash32_bat_lookup(cpu, eaddr, rwx, &prot);
if (raddr != -1) {
if (need_prot[rwx] & ~prot) {
if (rwx == 2) {
@@ -430,7 +439,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
/* 4. Handle direct store segments */
if (sr & SR32_T) {
- if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
+ if (ppc_hash32_direct_store(cpu, sr, eaddr, rwx,
&raddr, &prot) == 0) {
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
raddr & TARGET_PAGE_MASK, prot, mmu_idx,
@@ -449,7 +458,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
}
/* 6. Locate the PTE in the hash table */
- pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
+ pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte);
if (pte_offset == -1) {
if (rwx == 2) {
cs->exception_index = POWERPC_EXCP_ISI;
@@ -472,7 +481,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
/* 7. Check access permissions */
- prot = ppc_hash32_pte_prot(env, sr, pte);
+ prot = ppc_hash32_pte_prot(cpu, sr, pte);
if (need_prot[rwx] & ~prot) {
/* Access right violation */
@@ -507,7 +516,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
}
if (new_pte1 != pte.pte1) {
- ppc_hash32_store_hpte1(env, pte_offset, new_pte1);
+ ppc_hash32_store_hpte1(cpu, pte_offset, new_pte1);
}
/* 9. Determine the real address from the PTE */
@@ -520,8 +529,9 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
return 0;
}
-hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong eaddr)
+hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
{
+ CPUPPCState *env = &cpu->env;
target_ulong sr;
hwaddr pte_offset;
ppc_hash_pte32_t pte;
@@ -533,7 +543,7 @@ hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong eaddr)
}
if (env->nb_BATs != 0) {
- hwaddr raddr = ppc_hash32_bat_lookup(env, eaddr, 0, &prot);
+ hwaddr raddr = ppc_hash32_bat_lookup(cpu, eaddr, 0, &prot);
if (raddr != -1) {
return raddr;
}
@@ -546,7 +556,7 @@ hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong eaddr)
return -1;
}
- pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
+ pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte);
if (pte_offset == -1) {
return -1;
}
diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h
index d515d4f..afbb9dd 100644
--- a/target-ppc/mmu-hash32.h
+++ b/target-ppc/mmu-hash32.h
@@ -3,8 +3,8 @@
#ifndef CONFIG_USER_ONLY
-hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash);
-hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr);
+hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash);
+hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw,
int mmu_idx);
@@ -65,40 +65,42 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw,
#define HPTE32_R_WIMG 0x00000078
#define HPTE32_R_PP 0x00000003
-static inline target_ulong ppc_hash32_load_hpte0(CPUPPCState *env,
+static inline target_ulong ppc_hash32_load_hpte0(PowerPCCPU *cpu,
hwaddr pte_offset)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUPPCState *env = &cpu->env;
assert(!env->external_htab); /* Not supported on 32-bit for now */
- return ldl_phys(cs->as, env->htab_base + pte_offset);
+ return ldl_phys(CPU(cpu)->as, env->htab_base + pte_offset);
}
-static inline target_ulong ppc_hash32_load_hpte1(CPUPPCState *env,
+static inline target_ulong ppc_hash32_load_hpte1(PowerPCCPU *cpu,
hwaddr pte_offset)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUPPCState *env = &cpu->env;
assert(!env->external_htab); /* Not supported on 32-bit for now */
- return ldl_phys(cs->as, env->htab_base + pte_offset + HASH_PTE_SIZE_32/2);
+ return ldl_phys(CPU(cpu)->as,
+ env->htab_base + pte_offset + HASH_PTE_SIZE_32 / 2);
}
-static inline void ppc_hash32_store_hpte0(CPUPPCState *env,
+static inline void ppc_hash32_store_hpte0(PowerPCCPU *cpu,
hwaddr pte_offset, target_ulong pte0)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUPPCState *env = &cpu->env;
assert(!env->external_htab); /* Not supported on 32-bit for now */
- stl_phys(cs->as, env->htab_base + pte_offset, pte0);
+ stl_phys(CPU(cpu)->as, env->htab_base + pte_offset, pte0);
}
-static inline void ppc_hash32_store_hpte1(CPUPPCState *env,
+static inline void ppc_hash32_store_hpte1(PowerPCCPU *cpu,
hwaddr pte_offset, target_ulong pte1)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUPPCState *env = &cpu->env;
assert(!env->external_htab); /* Not supported on 32-bit for now */
- stl_phys(cs->as, env->htab_base + pte_offset + HASH_PTE_SIZE_32/2, pte1);
+ stl_phys(CPU(cpu)->as,
+ env->htab_base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1);
}
typedef struct {
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 34e20fa..03e25fd 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -40,8 +40,9 @@ bool kvmppc_kern_htab;
* SLB handling
*/
-static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
+static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr)
{
+ CPUPPCState *env = &cpu->env;
uint64_t esid_256M, esid_1T;
int n;
@@ -69,12 +70,13 @@ static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
return NULL;
}
-void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
+void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu)
{
+ CPUPPCState *env = &cpu->env;
int i;
uint64_t slbe, slbv;
- cpu_synchronize_state(CPU(ppc_env_get_cpu(env)));
+ cpu_synchronize_state(CPU(cpu));
cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
for (i = 0; i < env->slb_nr; i++) {
@@ -117,7 +119,7 @@ void helper_slbie(CPUPPCState *env, target_ulong addr)
PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppc_slb_t *slb;
- slb = slb_lookup(env, addr);
+ slb = slb_lookup(cpu, addr);
if (!slb) {
return;
}
@@ -133,8 +135,9 @@ void helper_slbie(CPUPPCState *env, target_ulong addr)
}
}
-int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
+int ppc_store_slb(PowerPCCPU *cpu, target_ulong rb, target_ulong rs)
{
+ CPUPPCState *env = &cpu->env;
int slot = rb & 0xfff;
ppc_slb_t *slb = &env->slb[slot];
@@ -159,9 +162,10 @@ int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
return 0;
}
-static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
+static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb,
target_ulong *rt)
{
+ CPUPPCState *env = &cpu->env;
int slot = rb & 0xfff;
ppc_slb_t *slb = &env->slb[slot];
@@ -173,9 +177,10 @@ static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
return 0;
}
-static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
+static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
target_ulong *rt)
{
+ CPUPPCState *env = &cpu->env;
int slot = rb & 0xfff;
ppc_slb_t *slb = &env->slb[slot];
@@ -189,7 +194,9 @@ static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
{
- if (ppc_store_slb(env, rb, rs) < 0) {
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
+ if (ppc_store_slb(cpu, rb, rs) < 0) {
helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL);
}
@@ -197,9 +204,10 @@ void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
target_ulong rt = 0;
- if (ppc_load_slb_esid(env, rb, &rt) < 0) {
+ if (ppc_load_slb_esid(cpu, rb, &rt) < 0) {
helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL);
}
@@ -208,9 +216,10 @@ target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
target_ulong rt = 0;
- if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
+ if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) {
helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL);
}
@@ -221,9 +230,10 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
* 64-bit hash table MMU handling
*/
-static int ppc_hash64_pte_prot(CPUPPCState *env,
+static int ppc_hash64_pte_prot(PowerPCCPU *cpu,
ppc_slb_t *slb, ppc_hash_pte64_t pte)
{
+ CPUPPCState *env = &cpu->env;
unsigned pp, key;
/* Some pp bit combinations have undefined behaviour, so default
* to no access in those cases */
@@ -273,12 +283,12 @@ static int ppc_hash64_pte_prot(CPUPPCState *env,
return prot;
}
-static int ppc_hash64_amr_prot(CPUPPCState *env, ppc_hash_pte64_t pte)
+static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
{
+ CPUPPCState *env = &cpu->env;
int key, amrbits;
int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
-
/* Only recent MMUs implement Virtual Page Class Key Protection */
if (!(env->mmu_model & POWERPC_MMU_AMR)) {
return prot;
@@ -347,23 +357,24 @@ void ppc_hash64_stop_access(uint64_t token)
}
}
-static hwaddr ppc_hash64_pteg_search(CPUPPCState *env, hwaddr hash,
+static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
bool secondary, target_ulong ptem,
ppc_hash_pte64_t *pte)
{
+ CPUPPCState *env = &cpu->env;
int i;
uint64_t token;
target_ulong pte0, pte1;
target_ulong pte_index;
pte_index = (hash & env->htab_mask) * HPTES_PER_GROUP;
- token = ppc_hash64_start_access(ppc_env_get_cpu(env), pte_index);
+ token = ppc_hash64_start_access(cpu, pte_index);
if (!token) {
return -1;
}
for (i = 0; i < HPTES_PER_GROUP; i++) {
- pte0 = ppc_hash64_load_hpte0(env, token, i);
- pte1 = ppc_hash64_load_hpte1(env, token, i);
+ pte0 = ppc_hash64_load_hpte0(cpu, token, i);
+ pte1 = ppc_hash64_load_hpte1(cpu, token, i);
if ((pte0 & HPTE64_V_VALID)
&& (secondary == !!(pte0 & HPTE64_V_SECONDARY))
@@ -399,10 +410,11 @@ static uint64_t ppc_hash64_page_shift(ppc_slb_t *slb)
return epnshift;
}
-static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
+static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
ppc_slb_t *slb, target_ulong eaddr,
ppc_hash_pte64_t *pte)
{
+ CPUPPCState *env = &cpu->env;
hwaddr pte_offset;
hwaddr hash;
uint64_t vsid, epnshift, epnmask, epn, ptem;
@@ -435,7 +447,7 @@ static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
" hash=" TARGET_FMT_plx "\n",
env->htab_base, env->htab_mask, vsid, ptem, hash);
- pte_offset = ppc_hash64_pteg_search(env, hash, 0, ptem, pte);
+ pte_offset = ppc_hash64_pteg_search(cpu, hash, 0, ptem, pte);
if (pte_offset == -1) {
/* Secondary PTEG lookup */
@@ -445,7 +457,7 @@ static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
" hash=" TARGET_FMT_plx "\n", env->htab_base,
env->htab_mask, vsid, ptem, ~hash);
- pte_offset = ppc_hash64_pteg_search(env, ~hash, 1, ptem, pte);
+ pte_offset = ppc_hash64_pteg_search(cpu, ~hash, 1, ptem, pte);
}
return pte_offset;
@@ -492,7 +504,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
}
/* 2. Translation is on, so look up the SLB */
- slb = slb_lookup(env, eaddr);
+ slb = slb_lookup(cpu, eaddr);
if (!slb) {
if (rwx == 2) {
@@ -514,7 +526,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
}
/* 4. Locate the PTE in the hash table */
- pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte);
+ pte_offset = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte);
if (pte_offset == -1) {
if (rwx == 2) {
cs->exception_index = POWERPC_EXCP_ISI;
@@ -536,8 +548,8 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
/* 5. Check access permissions */
- pp_prot = ppc_hash64_pte_prot(env, slb, pte);
- amr_prot = ppc_hash64_amr_prot(env, pte);
+ pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
+ amr_prot = ppc_hash64_amr_prot(cpu, pte);
prot = pp_prot & amr_prot;
if ((need_prot[rwx] & ~prot) != 0) {
@@ -580,7 +592,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
}
if (new_pte1 != pte.pte1) {
- ppc_hash64_store_hpte(env, pte_offset / HASH_PTE_SIZE_64,
+ ppc_hash64_store_hpte(cpu, pte_offset / HASH_PTE_SIZE_64,
pte.pte0, new_pte1);
}
@@ -594,8 +606,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
return 0;
}
-hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
+hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
{
+ CPUPPCState *env = &cpu->env;
ppc_slb_t *slb;
hwaddr pte_offset;
ppc_hash_pte64_t pte;
@@ -605,12 +618,12 @@ hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
return addr & 0x0FFFFFFFFFFFFFFFULL;
}
- slb = slb_lookup(env, addr);
+ slb = slb_lookup(cpu, addr);
if (!slb) {
return -1;
}
- pte_offset = ppc_hash64_htab_lookup(env, slb, addr, &pte);
+ pte_offset = ppc_hash64_htab_lookup(cpu, slb, addr, &pte);
if (pte_offset == -1) {
return -1;
}
@@ -618,11 +631,11 @@ hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
return ppc_hash64_pte_raddr(slb, pte, addr) & TARGET_PAGE_MASK;
}
-void ppc_hash64_store_hpte(CPUPPCState *env,
+void ppc_hash64_store_hpte(PowerPCCPU *cpu,
target_ulong pte_index,
target_ulong pte0, target_ulong pte1)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUPPCState *env = &cpu->env;
if (kvmppc_kern_htab) {
kvmppc_hash64_write_pte(env, pte_index, pte0, pte1);
@@ -632,9 +645,10 @@ void ppc_hash64_store_hpte(CPUPPCState *env,
pte_index *= HASH_PTE_SIZE_64;
if (env->external_htab) {
stq_p(env->external_htab + pte_index, pte0);
- stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64/2, pte1);
+ stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
} else {
- stq_phys(cs->as, env->htab_base + pte_index, pte0);
- stq_phys(cs->as, env->htab_base + pte_index + HASH_PTE_SIZE_64/2, pte1);
+ stq_phys(CPU(cpu)->as, env->htab_base + pte_index, pte0);
+ stq_phys(CPU(cpu)->as,
+ env->htab_base + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
}
}
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 291750f..6e3de7e 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -4,12 +4,13 @@
#ifndef CONFIG_USER_ONLY
#ifdef TARGET_PPC64
-void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
-int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
-hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr);
+void ppc_hash64_check_page_sizes(PowerPCCPU *cpu, Error **errp);
+void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu);
+int ppc_store_slb(PowerPCCPU *cpu, target_ulong rb, target_ulong rs);
+hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw,
int mmu_idx);
-void ppc_hash64_store_hpte(CPUPPCState *env, target_ulong index,
+void ppc_hash64_store_hpte(PowerPCCPU *cpu, target_ulong index,
target_ulong pte0, target_ulong pte1);
#endif
@@ -85,31 +86,31 @@ extern bool kvmppc_kern_htab;
uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index);
void ppc_hash64_stop_access(uint64_t token);
-static inline target_ulong ppc_hash64_load_hpte0(CPUPPCState *env,
+static inline target_ulong ppc_hash64_load_hpte0(PowerPCCPU *cpu,
uint64_t token, int index)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUPPCState *env = &cpu->env;
uint64_t addr;
addr = token + (index * HASH_PTE_SIZE_64);
if (env->external_htab) {
return ldq_p((const void *)(uintptr_t)addr);
} else {
- return ldq_phys(cs->as, addr);
+ return ldq_phys(CPU(cpu)->as, addr);
}
}
-static inline target_ulong ppc_hash64_load_hpte1(CPUPPCState *env,
+static inline target_ulong ppc_hash64_load_hpte1(PowerPCCPU *cpu,
uint64_t token, int index)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUPPCState *env = &cpu->env;
uint64_t addr;
addr = token + (index * HASH_PTE_SIZE_64) + HASH_PTE_SIZE_64/2;
if (env->external_htab) {
return ldq_p((const void *)(uintptr_t)addr);
} else {
- return ldq_phys(cs->as, addr);
+ return ldq_phys(CPU(cpu)->as, addr);
}
}
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 5217691..0ab73bc 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1297,7 +1297,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
case POWERPC_MMU_2_06a:
case POWERPC_MMU_2_07:
case POWERPC_MMU_2_07a:
- dump_slb(f, cpu_fprintf, env);
+ dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
break;
#endif
default:
@@ -1439,12 +1439,12 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
case POWERPC_MMU_2_06a:
case POWERPC_MMU_2_07:
case POWERPC_MMU_2_07a:
- return ppc_hash64_get_phys_page_debug(env, addr);
+ return ppc_hash64_get_phys_page_debug(cpu, addr);
#endif
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
- return ppc_hash32_get_phys_page_debug(env, addr);
+ return ppc_hash32_get_phys_page_debug(cpu, addr);
default:
;
@@ -1510,6 +1510,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
int rw, int mmu_idx)
{
CPUState *cs = CPU(ppc_env_get_cpu(env));
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
mmu_ctx_t ctx;
int access_type;
int ret = 0;
@@ -1611,9 +1612,9 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
tlb_miss:
env->error_code |= ctx.key << 19;
env->spr[SPR_HASH1] = env->htab_base +
- get_pteg_offset32(env, ctx.hash[0]);
+ get_pteg_offset32(cpu, ctx.hash[0]);
env->spr[SPR_HASH2] = env->htab_base +
- get_pteg_offset32(env, ctx.hash[1]);
+ get_pteg_offset32(cpu, ctx.hash[1]);
break;
case POWERPC_MMU_SOFT_74xx:
if (rw == 1) {
@@ -2101,7 +2102,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
/* flags = flags */
rs |= ((value >> 27) & 0xf) << 8;
- ppc_store_slb(env, rb, rs);
+ ppc_store_slb(cpu, rb, rs);
} else
#endif
if (env->sr[srnum] != value) {
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 31/39] target-ppc: Rework ppc_store_slb
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (30 preceding siblings ...)
2016-01-29 5:07 ` [Qemu-devel] [PULL 30/39] target-ppc: Convert mmu-hash{32, 64}.[ch] from CPUPPCState to PowerPCCPU David Gibson
@ 2016-01-29 5:07 ` David Gibson
2016-01-29 5:07 ` [Qemu-devel] [PULL 32/39] target-ppc: Rework SLB page size lookup David Gibson
` (7 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:07 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
ppc_store_slb updates the SLB for PPC cpus with 64-bit hash MMUs.
Currently it takes two parameters, which contain values encoded as the
register arguments to the slbmte instruction, one register contains the
ESID portion of the SLBE and also the slot number, the other contains the
VSID portion of the SLBE.
We're shortly going to want to do some SLB updates from other code where
it is more convenient to supply the slot number and ESID separately, so
rework this function and its callers to work this way.
As a bonus, this slightly simplifies the emulation of segment registers for
when running a 32-bit OS on a 64-bit CPU.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alexander Graf <agraf@suse.de>
---
target-ppc/kvm.c | 2 +-
target-ppc/mmu-hash64.c | 24 +++++++++++++-----------
target-ppc/mmu-hash64.h | 3 ++-
target-ppc/mmu_helper.c | 14 +++++---------
4 files changed, 21 insertions(+), 22 deletions(-)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 98d7ba6..0f45380 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -1205,7 +1205,7 @@ int kvm_arch_get_registers(CPUState *cs)
* Only restore valid entries
*/
if (rb & SLB_ESID_V) {
- ppc_store_slb(cpu, rb, rs);
+ ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
}
}
#endif
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 03e25fd..6e05643 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -135,28 +135,30 @@ void helper_slbie(CPUPPCState *env, target_ulong addr)
}
}
-int ppc_store_slb(PowerPCCPU *cpu, target_ulong rb, target_ulong rs)
+int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
+ target_ulong esid, target_ulong vsid)
{
CPUPPCState *env = &cpu->env;
- int slot = rb & 0xfff;
ppc_slb_t *slb = &env->slb[slot];
- if (rb & (0x1000 - env->slb_nr)) {
- return -1; /* Reserved bits set or slot too high */
+ if (slot >= env->slb_nr) {
+ return -1; /* Bad slot number */
+ }
+ if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) {
+ return -1; /* Reserved bits set */
}
- if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
+ if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
return -1; /* Bad segment size */
}
- if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
+ if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
return -1; /* 1T segment on MMU that doesn't support it */
}
- /* Mask out the slot number as we store the entry */
- slb->esid = rb & (SLB_ESID_ESID | SLB_ESID_V);
- slb->vsid = rs;
+ slb->esid = esid;
+ slb->vsid = vsid;
LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
- " %016" PRIx64 "\n", __func__, slot, rb, rs,
+ " %016" PRIx64 "\n", __func__, slot, esid, vsid,
slb->esid, slb->vsid);
return 0;
@@ -196,7 +198,7 @@ void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
- if (ppc_store_slb(cpu, rb, rs) < 0) {
+ if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) {
helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL);
}
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 6e3de7e..24fd2c4 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -6,7 +6,8 @@
#ifdef TARGET_PPC64
void ppc_hash64_check_page_sizes(PowerPCCPU *cpu, Error **errp);
void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu);
-int ppc_store_slb(PowerPCCPU *cpu, target_ulong rb, target_ulong rs);
+int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
+ target_ulong esid, target_ulong vsid);
hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw,
int mmu_idx);
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 0ab73bc..c040b17 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -2088,21 +2088,17 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
(int)srnum, value, env->sr[srnum]);
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
- uint64_t rb = 0, rs = 0;
+ uint64_t esid, vsid;
/* ESID = srnum */
- rb |= ((uint32_t)srnum & 0xf) << 28;
- /* Set the valid bit */
- rb |= SLB_ESID_V;
- /* Index = ESID */
- rb |= (uint32_t)srnum;
+ esid = ((uint64_t)(srnum & 0xf) << 28) | SLB_ESID_V;
/* VSID = VSID */
- rs |= (value & 0xfffffff) << 12;
+ vsid = (value & 0xfffffff) << 12;
/* flags = flags */
- rs |= ((value >> 27) & 0xf) << 8;
+ vsid |= ((value >> 27) & 0xf) << 8;
- ppc_store_slb(cpu, rb, rs);
+ ppc_store_slb(cpu, srnum, esid, vsid);
} else
#endif
if (env->sr[srnum] != value) {
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 32/39] target-ppc: Rework SLB page size lookup
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (31 preceding siblings ...)
2016-01-29 5:07 ` [Qemu-devel] [PULL 31/39] target-ppc: Rework ppc_store_slb David Gibson
@ 2016-01-29 5:07 ` David Gibson
2016-01-29 5:07 ` [Qemu-devel] [PULL 33/39] target-ppc: Use actual page size encodings from HPTE David Gibson
` (6 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:07 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
Currently, the ppc_hash64_page_shift() function looks up a page size based
on information in an SLB entry. It open codes the bit translation for
existing CPUs, however different CPU models can have different SLB
encodings. We already store those in the 'sps' table in CPUPPCState, but
we don't currently enforce that that actually matches the logic in
ppc_hash64_page_shift.
This patch reworks lookup of page size from SLB in several ways:
* ppc_store_slb() will now fail (triggering an illegal instruction
exception) if given a bad SLB page size encoding
* On success ppc_store_slb() stores a pointer to the relevant entry in
the page size table in the SLB entry. This is looked up directly from
the published table of page size encodings, so can't get out ot sync.
* ppc_hash64_htab_lookup() and others now use this precached page size
information rather than decoding the SLB values
* Now that callers have easy access to the page_shift,
ppc_hash64_pte_raddr() amounts to just a deposit64(), so remove it and
have the callers use deposit64() directly.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alexander Graf <agraf@suse.de>
---
target-ppc/cpu.h | 1 +
target-ppc/machine.c | 20 +++++++++++++
target-ppc/mmu-hash64.c | 74 +++++++++++++++++++++++--------------------------
3 files changed, 56 insertions(+), 39 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 2bc96b4..0820390 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -419,6 +419,7 @@ typedef struct ppc_slb_t ppc_slb_t;
struct ppc_slb_t {
uint64_t esid;
uint64_t vsid;
+ const struct ppc_one_seg_page_size *sps;
};
#define MAX_SLB_ENTRIES 64
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index b61c060..ca62d3e 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -2,6 +2,7 @@
#include "hw/boards.h"
#include "sysemu/kvm.h"
#include "helper_regs.h"
+#include "mmu-hash64.h"
static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
{
@@ -352,11 +353,30 @@ static bool slb_needed(void *opaque)
return (cpu->env.mmu_model & POWERPC_MMU_64);
}
+static int slb_post_load(void *opaque, int version_id)
+{
+ PowerPCCPU *cpu = opaque;
+ CPUPPCState *env = &cpu->env;
+ int i;
+
+ /* We've pulled in the raw esid and vsid values from the migration
+ * stream, but we need to recompute the page size pointers */
+ for (i = 0; i < env->slb_nr; i++) {
+ if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
+ /* Migration source had bad values in its SLB */
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
static const VMStateDescription vmstate_slb = {
.name = "cpu/slb",
.version_id = 1,
.minimum_version_id = 1,
.needed = slb_needed,
+ .post_load = slb_post_load,
.fields = (VMStateField[]) {
VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 6e05643..b784791 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -19,6 +19,7 @@
*/
#include "cpu.h"
#include "exec/helper-proto.h"
+#include "qemu/error-report.h"
#include "sysemu/kvm.h"
#include "kvm_ppc.h"
#include "mmu-hash64.h"
@@ -140,6 +141,8 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
{
CPUPPCState *env = &cpu->env;
ppc_slb_t *slb = &env->slb[slot];
+ const struct ppc_one_seg_page_size *sps = NULL;
+ int i;
if (slot >= env->slb_nr) {
return -1; /* Bad slot number */
@@ -154,8 +157,29 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
return -1; /* 1T segment on MMU that doesn't support it */
}
+ for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
+ const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
+
+ if (!sps1->page_shift) {
+ break;
+ }
+
+ if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
+ sps = sps1;
+ break;
+ }
+ }
+
+ if (!sps) {
+ error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu
+ " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx,
+ slot, esid, vsid);
+ return -1;
+ }
+
slb->esid = esid;
slb->vsid = vsid;
+ slb->sps = sps;
LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
" %016" PRIx64 "\n", __func__, slot, esid, vsid,
@@ -394,24 +418,6 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
return -1;
}
-static uint64_t ppc_hash64_page_shift(ppc_slb_t *slb)
-{
- uint64_t epnshift;
-
- /* Page size according to the SLB, which we use to generate the
- * EPN for hash table lookup.. When we implement more recent MMU
- * extensions this might be different from the actual page size
- * encoded in the PTE */
- if ((slb->vsid & SLB_VSID_LLP_MASK) == SLB_VSID_4K) {
- epnshift = TARGET_PAGE_BITS;
- } else if ((slb->vsid & SLB_VSID_LLP_MASK) == SLB_VSID_64K) {
- epnshift = TARGET_PAGE_BITS_64K;
- } else {
- epnshift = TARGET_PAGE_BITS_16M;
- }
- return epnshift;
-}
-
static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
ppc_slb_t *slb, target_ulong eaddr,
ppc_hash_pte64_t *pte)
@@ -419,21 +425,24 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
CPUPPCState *env = &cpu->env;
hwaddr pte_offset;
hwaddr hash;
- uint64_t vsid, epnshift, epnmask, epn, ptem;
+ uint64_t vsid, epnmask, epn, ptem;
+
+ /* The SLB store path should prevent any bad page size encodings
+ * getting in there, so: */
+ assert(slb->sps);
- epnshift = ppc_hash64_page_shift(slb);
- epnmask = ~((1ULL << epnshift) - 1);
+ epnmask = ~((1ULL << slb->sps->page_shift) - 1);
if (slb->vsid & SLB_VSID_B) {
/* 1TB segment */
vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
- hash = vsid ^ (vsid << 25) ^ (epn >> epnshift);
+ hash = vsid ^ (vsid << 25) ^ (epn >> slb->sps->page_shift);
} else {
/* 256M segment */
vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
- hash = vsid ^ (epn >> epnshift);
+ hash = vsid ^ (epn >> slb->sps->page_shift);
}
ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
@@ -465,20 +474,6 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
return pte_offset;
}
-static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte,
- target_ulong eaddr)
-{
- hwaddr mask;
- int target_page_bits;
- hwaddr rpn = pte.pte1 & HPTE64_R_RPN;
- /*
- * We support 4K, 64K and 16M now
- */
- target_page_bits = ppc_hash64_page_shift(slb);
- mask = (1ULL << target_page_bits) - 1;
- return (rpn & ~mask) | (eaddr & mask);
-}
-
int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
int rwx, int mmu_idx)
{
@@ -600,7 +595,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
/* 7. Determine the real address from the PTE */
- raddr = ppc_hash64_pte_raddr(slb, pte, eaddr);
+ raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, slb->sps->page_shift, eaddr);
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
@@ -630,7 +625,8 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
return -1;
}
- return ppc_hash64_pte_raddr(slb, pte, addr) & TARGET_PAGE_MASK;
+ return deposit64(pte.pte1 & HPTE64_R_RPN, 0, slb->sps->page_shift, addr)
+ & TARGET_PAGE_MASK;
}
void ppc_hash64_store_hpte(PowerPCCPU *cpu,
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 33/39] target-ppc: Use actual page size encodings from HPTE
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (32 preceding siblings ...)
2016-01-29 5:07 ` [Qemu-devel] [PULL 32/39] target-ppc: Rework SLB page size lookup David Gibson
@ 2016-01-29 5:07 ` David Gibson
2016-01-29 5:07 ` [Qemu-devel] [PULL 34/39] target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one David Gibson
` (5 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:07 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
At present the 64-bit hash MMU code uses information from the SLB to
determine the page size of a translation. We do need that information to
correctly look up the hash table. However the MMU also allows a
possibly larger page size to be encoded into the HPTE itself, which is used
to populate the TLB. At present qemu doesn't check that, and so doesn't
support the MPSS "Multiple Page Size per Segment" feature.
This makes a start on allowing this, by adding an hpte_page_shift()
function which looks up the page size of an HPTE. We use this to validate
page sizes encodings on faults, and populate the qemu TLB with larger
page sizes when appropriate.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alexander Graf <agraf@suse.de>
---
target-ppc/mmu-hash64.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 60 insertions(+), 3 deletions(-)
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index b784791..ee1e8bf 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -21,6 +21,7 @@
#include "exec/helper-proto.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
+#include "qemu/error-report.h"
#include "kvm_ppc.h"
#include "mmu-hash64.h"
@@ -474,12 +475,50 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
return pte_offset;
}
+static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
+ uint64_t pte0, uint64_t pte1)
+{
+ int i;
+
+ if (!(pte0 & HPTE64_V_LARGE)) {
+ if (sps->page_shift != 12) {
+ /* 4kiB page in a non 4kiB segment */
+ return 0;
+ }
+ /* Normal 4kiB page */
+ return 12;
+ }
+
+ for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
+ const struct ppc_one_page_size *ps = &sps->enc[i];
+ uint64_t mask;
+
+ if (!ps->page_shift) {
+ break;
+ }
+
+ if (ps->page_shift == 12) {
+ /* L bit is set so this can't be a 4kiB page */
+ continue;
+ }
+
+ mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
+
+ if ((pte1 & mask) == (ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
+ return ps->page_shift;
+ }
+ }
+
+ return 0; /* Bad page size encoding */
+}
+
int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
int rwx, int mmu_idx)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
ppc_slb_t *slb;
+ unsigned apshift;
hwaddr pte_offset;
ppc_hash_pte64_t pte;
int pp_prot, amr_prot, prot;
@@ -543,6 +582,18 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
qemu_log_mask(CPU_LOG_MMU,
"found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
+ /* Validate page size encoding */
+ apshift = hpte_page_shift(slb->sps, pte.pte0, pte.pte1);
+ if (!apshift) {
+ error_report("Bad page size encoding in HPTE 0x%"PRIx64" - 0x%"PRIx64
+ " @ 0x%"HWADDR_PRIx, pte.pte0, pte.pte1, pte_offset);
+ /* Not entirely sure what the right action here, but machine
+ * check seems reasonable */
+ cs->exception_index = POWERPC_EXCP_MCHECK;
+ env->error_code = 0;
+ return 1;
+ }
+
/* 5. Check access permissions */
pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
@@ -595,10 +646,10 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
/* 7. Determine the real address from the PTE */
- raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, slb->sps->page_shift, eaddr);
+ raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
- prot, mmu_idx, TARGET_PAGE_SIZE);
+ prot, mmu_idx, 1ULL << apshift);
return 0;
}
@@ -609,6 +660,7 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
ppc_slb_t *slb;
hwaddr pte_offset;
ppc_hash_pte64_t pte;
+ unsigned apshift;
if (msr_dr == 0) {
/* In real mode the top 4 effective address bits are ignored */
@@ -625,7 +677,12 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
return -1;
}
- return deposit64(pte.pte1 & HPTE64_R_RPN, 0, slb->sps->page_shift, addr)
+ apshift = hpte_page_shift(slb->sps, pte.pte0, pte.pte1);
+ if (!apshift) {
+ return -1;
+ }
+
+ return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
& TARGET_PAGE_MASK;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 34/39] target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (33 preceding siblings ...)
2016-01-29 5:07 ` [Qemu-devel] [PULL 33/39] target-ppc: Use actual page size encodings from HPTE David Gibson
@ 2016-01-29 5:07 ` David Gibson
2016-01-29 5:07 ` [Qemu-devel] [PULL 35/39] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one() David Gibson
` (4 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:07 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
ppc_tlb_invalidate_one() has a big switch handling many different MMU
types. However, most of those branches can never be reached:
It is called from 3 places: from remove_hpte() and h_protect() in
spapr_hcall.c (which always has a 64-bit hash MMU type), and from
helper_tlbie() in mmu_helper.c.
Calls to helper_tlbie() are generated from gen_tlbiel, gen_tlbiel and
gen_tlbiva. The first two are only used with the PPC_MEM_TLBIE flag,
set only with 32-bit or 64-bit hash MMU models, and gen_tlbiva() is
used only on 440 and 460 models with the BookE mmu model.
These means the exhaustive list of MMU types which may call
ppc_tlb_invalidate_one() is: POWERPC_MMU_SOFT_6xx, POWERPC_MMU_601,
POWERPC_MMU_32B, POWERPC_MMU_SOFT_74xx, POWERPC_MMU_64B, POWERPC_MMU_2_03,
POWERPC_MMU_2_06, POWERPC_MMU_2_07 and POWERPC_MMU_BOOKE.
Clean up by removing logic for all other MMU types from
ppc_tlb_invalidate_one().
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alexander Graf <agraf@suse.de>
---
target-ppc/mmu_helper.c | 20 ++------------------
1 file changed, 2 insertions(+), 18 deletions(-)
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index c040b17..82ebe5d 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1971,25 +1971,10 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
ppc6xx_tlb_invalidate_virt(env, addr, 1);
}
break;
- case POWERPC_MMU_SOFT_4xx:
- case POWERPC_MMU_SOFT_4xx_Z:
- ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
- break;
- case POWERPC_MMU_REAL:
- cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n");
- break;
- case POWERPC_MMU_MPC8xx:
- /* XXX: TODO */
- cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
- break;
case POWERPC_MMU_BOOKE:
/* XXX: TODO */
cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n");
break;
- case POWERPC_MMU_BOOKE206:
- /* XXX: TODO */
- cpu_abort(CPU(cpu), "BookE 2.06 MMU model is not implemented\n");
- break;
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
/* tlbie invalidate TLBs for all segments */
@@ -2031,9 +2016,8 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
break;
#endif /* defined(TARGET_PPC64) */
default:
- /* XXX: TODO */
- cpu_abort(CPU(cpu), "Unknown MMU model\n");
- break;
+ /* Should never reach here with other MMU models */
+ assert(0);
}
#else
ppc_tlb_invalidate_all(env);
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 35/39] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one()
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (34 preceding siblings ...)
2016-01-29 5:07 ` [Qemu-devel] [PULL 34/39] target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one David Gibson
@ 2016-01-29 5:07 ` David Gibson
2016-01-29 5:07 ` [Qemu-devel] [PULL 36/39] target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs David Gibson
` (3 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:07 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
Currently both the tlbiva instruction (used on 44x chips) and the tlbie
instruction (used on hash MMU chips) are both handled via
ppc_tlb_invalidate_one(). This is silly, because they're invoked from
different places, and do different things.
Clean this up by separating out the tlbiva instruction into its own
handling. In fact the implementation is only a stub anyway.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alexander Graf <agraf@suse.de>
---
target-ppc/helper.h | 1 +
target-ppc/mmu_helper.c | 14 ++++++++++----
target-ppc/translate.c | 2 +-
3 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 869be15..e5a8f7b 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -544,6 +544,7 @@ DEF_HELPER_2(74xx_tlbd, void, env, tl)
DEF_HELPER_2(74xx_tlbi, void, env, tl)
DEF_HELPER_FLAGS_1(tlbia, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(tlbie, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 82ebe5d..04b1fe1 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1971,10 +1971,6 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
ppc6xx_tlb_invalidate_virt(env, addr, 1);
}
break;
- case POWERPC_MMU_BOOKE:
- /* XXX: TODO */
- cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n");
- break;
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
/* tlbie invalidate TLBs for all segments */
@@ -2116,6 +2112,16 @@ void helper_tlbie(CPUPPCState *env, target_ulong addr)
ppc_tlb_invalidate_one(env, addr);
}
+void helper_tlbiva(CPUPPCState *env, target_ulong addr)
+{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
+ /* tlbiva instruction only exists on BookE */
+ assert(env->mmu_model == POWERPC_MMU_BOOKE);
+ /* XXX: TODO */
+ cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n");
+}
+
/* Software driven TLBs management */
/* PowerPC 602/603 software TLB load instructions helpers */
static void do_6xx_tlb(CPUPPCState *env, target_ulong new_EPN, int is_code)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4be7eaa..a05a169 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -5904,7 +5904,7 @@ static void gen_tlbiva(DisasContext *ctx)
}
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
+ gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
tcg_temp_free(t0);
#endif
}
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 36/39] target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (35 preceding siblings ...)
2016-01-29 5:07 ` [Qemu-devel] [PULL 35/39] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one() David Gibson
@ 2016-01-29 5:07 ` David Gibson
2016-01-29 5:07 ` [Qemu-devel] [PULL 37/39] target-ppc: Helper to determine page size information from hpte alone David Gibson
` (2 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:07 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
When HPTEs are removed or modified by hypercalls on spapr, we need to
invalidate the relevant pages in the qemu TLB.
Currently we do that by doing some complicated calculations to work out the
right encoding for the tlbie instruction, then passing that to
ppc_tlb_invalidate_one()... which totally ignores the argument and flushes
the whole tlb.
Avoid that by adding a new flush-by-hpte helper in mmu-hash64.c.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/spapr_hcall.c | 46 ++++------------------------------------------
target-ppc/mmu-hash64.c | 12 ++++++++++++
target-ppc/mmu-hash64.h | 3 +++
3 files changed, 19 insertions(+), 42 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 4707196..dedc7e0 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -37,42 +37,6 @@ static void set_spr(CPUState *cs, int spr, target_ulong value,
run_on_cpu(cs, do_spr_sync, &s);
}
-static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
- target_ulong pte_index)
-{
- target_ulong rb, va_low;
-
- rb = (v & ~0x7fULL) << 16; /* AVA field */
- va_low = pte_index >> 3;
- if (v & HPTE64_V_SECONDARY) {
- va_low = ~va_low;
- }
- /* xor vsid from AVA */
- if (!(v & HPTE64_V_1TB_SEG)) {
- va_low ^= v >> 12;
- } else {
- va_low ^= v >> 24;
- }
- va_low &= 0x7ff;
- if (v & HPTE64_V_LARGE) {
- rb |= 1; /* L field */
-#if 0 /* Disable that P7 specific bit for now */
- if (r & 0xff000) {
- /* non-16MB large page, must be 64k */
- /* (masks depend on page size) */
- rb |= 0x1000; /* page encoding in LP field */
- rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
- rb |= (va_low & 0xfe); /* AVAL field */
- }
-#endif
- } else {
- /* 4kB page */
- rb |= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */
- }
- rb |= (v >> 54) & 0x300; /* B field */
- return rb;
-}
-
static inline bool valid_pte_index(CPUPPCState *env, target_ulong pte_index)
{
/*
@@ -198,7 +162,7 @@ static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex,
{
CPUPPCState *env = &cpu->env;
uint64_t token;
- target_ulong v, r, rb;
+ target_ulong v, r;
if (!valid_pte_index(env, ptex)) {
return REMOVE_PARM;
@@ -217,8 +181,7 @@ static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex,
*vp = v;
*rp = r;
ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0);
- rb = compute_tlbie_rb(v, r, ptex);
- ppc_tlb_invalidate_one(env, rb);
+ ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
return REMOVE_SUCCESS;
}
@@ -322,7 +285,7 @@ static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong pte_index = args[1];
target_ulong avpn = args[2];
uint64_t token;
- target_ulong v, r, rb;
+ target_ulong v, r;
if (!valid_pte_index(env, pte_index)) {
return H_PARAMETER;
@@ -343,10 +306,9 @@ static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr,
r |= (flags << 55) & HPTE64_R_PP0;
r |= (flags << 48) & HPTE64_R_KEY_HI;
r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
- rb = compute_tlbie_rb(v, r, pte_index);
ppc_hash64_store_hpte(cpu, pte_index,
(v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0);
- ppc_tlb_invalidate_one(env, rb);
+ ppc_hash64_tlb_flush_hpte(cpu, pte_index, v, r);
/* Don't need a memory barrier, due to qemu's global lock */
ppc_hash64_store_hpte(cpu, pte_index, v | HPTE64_V_HPTE_DIRTY, r);
return H_SUCCESS;
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index ee1e8bf..3284776 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -707,3 +707,15 @@ void ppc_hash64_store_hpte(PowerPCCPU *cpu,
env->htab_base + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
}
}
+
+void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
+ target_ulong pte_index,
+ target_ulong pte0, target_ulong pte1)
+{
+ /*
+ * XXX: given the fact that there are too many segments to
+ * invalidate, and we still don't have a tlb_flush_mask(env, n,
+ * mask) in QEMU, we just invalidate all TLBs
+ */
+ tlb_flush(CPU(cpu), 1);
+}
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 24fd2c4..293a951 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -13,6 +13,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw,
int mmu_idx);
void ppc_hash64_store_hpte(PowerPCCPU *cpu, target_ulong index,
target_ulong pte0, target_ulong pte1);
+void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
+ target_ulong pte_index,
+ target_ulong pte0, target_ulong pte1);
#endif
/*
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 37/39] target-ppc: Helper to determine page size information from hpte alone
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (36 preceding siblings ...)
2016-01-29 5:07 ` [Qemu-devel] [PULL 36/39] target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs David Gibson
@ 2016-01-29 5:07 ` David Gibson
2016-01-29 5:07 ` [Qemu-devel] [PULL 38/39] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG David Gibson
2016-01-29 5:07 ` [Qemu-devel] [PULL 39/39] target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro David Gibson
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:07 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
h_enter() in the spapr code needs to know the page size of the HPTE it's
about to insert. Unlike other paths that do this, it doesn't have access
to the SLB, so at the moment it determines this with some open-coded
tests which assume POWER7 or POWER8 page size encodings.
To make this more flexible add ppc_hash64_hpte_page_shift_noslb() to
determine both the "base" page size per segment, and the individual
effective page size from an HPTE alone.
This means that the spapr code should now be able to handle any page size
listed in the env->sps table.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/spapr_hcall.c | 25 ++++++-------------------
target-ppc/mmu-hash64.c | 35 +++++++++++++++++++++++++++++++++++
target-ppc/mmu-hash64.h | 3 +++
3 files changed, 44 insertions(+), 19 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index dedc7e0..a535c73 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -72,31 +72,18 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong pte_index = args[1];
target_ulong pteh = args[2];
target_ulong ptel = args[3];
- target_ulong page_shift = 12;
+ unsigned apshift, spshift;
target_ulong raddr;
target_ulong index;
uint64_t token;
- /* only handle 4k and 16M pages for now */
- if (pteh & HPTE64_V_LARGE) {
-#if 0 /* We don't support 64k pages yet */
- if ((ptel & 0xf000) == 0x1000) {
- /* 64k page */
- } else
-#endif
- if ((ptel & 0xff000) == 0) {
- /* 16M page */
- page_shift = 24;
- /* lowest AVA bit must be 0 for 16M pages */
- if (pteh & 0x80) {
- return H_PARAMETER;
- }
- } else {
- return H_PARAMETER;
- }
+ apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel, &spshift);
+ if (!apshift) {
+ /* Bad page size encoding */
+ return H_PARAMETER;
}
- raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << page_shift) - 1);
+ raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
if (is_ram_address(spapr, raddr)) {
/* Regular RAM - should have WIMG=0010 */
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 3284776..19ee942 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -512,6 +512,41 @@ static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
return 0; /* Bad page size encoding */
}
+unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
+ uint64_t pte0, uint64_t pte1,
+ unsigned *seg_page_shift)
+{
+ CPUPPCState *env = &cpu->env;
+ int i;
+
+ if (!(pte0 & HPTE64_V_LARGE)) {
+ *seg_page_shift = 12;
+ return 12;
+ }
+
+ /*
+ * The encodings in env->sps need to be carefully chosen so that
+ * this gives an unambiguous result.
+ */
+ for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
+ const struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
+ unsigned shift;
+
+ if (!sps->page_shift) {
+ break;
+ }
+
+ shift = hpte_page_shift(sps, pte0, pte1);
+ if (shift) {
+ *seg_page_shift = sps->page_shift;
+ return shift;
+ }
+ }
+
+ *seg_page_shift = 0;
+ return 0;
+}
+
int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
int rwx, int mmu_idx)
{
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 293a951..34cf975 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -16,6 +16,9 @@ void ppc_hash64_store_hpte(PowerPCCPU *cpu, target_ulong index,
void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
target_ulong pte_index,
target_ulong pte0, target_ulong pte1);
+unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
+ uint64_t pte0, uint64_t pte1,
+ unsigned *seg_page_shift);
#endif
/*
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 38/39] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (37 preceding siblings ...)
2016-01-29 5:07 ` [Qemu-devel] [PULL 37/39] target-ppc: Helper to determine page size information from hpte alone David Gibson
@ 2016-01-29 5:07 ` David Gibson
2016-01-29 5:07 ` [Qemu-devel] [PULL 39/39] target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro David Gibson
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:07 UTC (permalink / raw)
To: peter.maydell, agraf; +Cc: aik, mdroth, qemu-devel, qemu-ppc, David Gibson
Now that the TCG and spapr code has been extended to allow (semi-)
arbitrary page encodings in the CPU's 'sps' table, we can add the many
page sizes supported by real POWER7 and POWER8 hardware that we previously
didn't support in TCG.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alexander Graf <agraf@suse.de>
---
target-ppc/mmu-hash64.h | 2 ++
target-ppc/translate_init.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 34cf975..ab0f86b 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -48,6 +48,8 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
#define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP)
#define SLB_VSID_4K 0x0000000000000000ULL
#define SLB_VSID_64K 0x0000000000000110ULL
+#define SLB_VSID_16M 0x0000000000000100ULL
+#define SLB_VSID_16G 0x0000000000000120ULL
/*
* Hash page table definitions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 156d156..d557043 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8104,6 +8104,36 @@ static Property powerpc_servercpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifdef CONFIG_SOFTMMU
+static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
+ .sps = {
+ {
+ .page_shift = 12, /* 4K */
+ .slb_enc = 0,
+ .enc = { { .page_shift = 12, .pte_enc = 0 },
+ { .page_shift = 16, .pte_enc = 0x7 },
+ { .page_shift = 24, .pte_enc = 0x38 }, },
+ },
+ {
+ .page_shift = 16, /* 64K */
+ .slb_enc = SLB_VSID_64K,
+ .enc = { { .page_shift = 16, .pte_enc = 0x1 },
+ { .page_shift = 24, .pte_enc = 0x8 }, },
+ },
+ {
+ .page_shift = 24, /* 16M */
+ .slb_enc = SLB_VSID_16M,
+ .enc = { { .page_shift = 24, .pte_enc = 0 }, },
+ },
+ {
+ .page_shift = 34, /* 16G */
+ .slb_enc = SLB_VSID_16G,
+ .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
+ },
+ }
+};
+#endif /* CONFIG_SOFTMMU */
+
static void init_proc_POWER7 (CPUPPCState *env)
{
init_proc_book3s_64(env, BOOK3S_CPU_POWER7);
@@ -8167,6 +8197,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+ pcc->sps = &POWER7_POWER8_sps;
#endif
pcc->excp_model = POWERPC_EXCP_POWER7;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
@@ -8247,6 +8278,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->mmu_model = POWERPC_MMU_2_07;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+ pcc->sps = &POWER7_POWER8_sps;
#endif
pcc->excp_model = POWERPC_EXCP_POWER7;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread* [Qemu-devel] [PULL 39/39] target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro
2016-01-29 5:06 [Qemu-devel] [PULL 00/39] ppc-for-2.6 queue 20160129 David Gibson
` (38 preceding siblings ...)
2016-01-29 5:07 ` [Qemu-devel] [PULL 38/39] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG David Gibson
@ 2016-01-29 5:07 ` David Gibson
39 siblings, 0 replies; 47+ messages in thread
From: David Gibson @ 2016-01-29 5:07 UTC (permalink / raw)
To: peter.maydell, agraf
Cc: aik, mdroth, qemu-devel, qemu-ppc, James Clarke, David Gibson
From: James Clarke <jrtc27@jrtc27.com>
Signed-off-by: James Clarke <jrtc27@jrtc27.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/cpu.h | 31 ++++++++++++++++++++++---------
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 0820390..f300c86 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -687,24 +687,37 @@ enum {
#define FP_FX (1ull << FPSCR_FX)
#define FP_FEX (1ull << FPSCR_FEX)
+#define FP_VX (1ull << FPSCR_VX)
#define FP_OX (1ull << FPSCR_OX)
-#define FP_OE (1ull << FPSCR_OE)
#define FP_UX (1ull << FPSCR_UX)
-#define FP_UE (1ull << FPSCR_UE)
-#define FP_XX (1ull << FPSCR_XX)
-#define FP_XE (1ull << FPSCR_XE)
#define FP_ZX (1ull << FPSCR_ZX)
-#define FP_ZE (1ull << FPSCR_ZE)
-#define FP_VX (1ull << FPSCR_VX)
+#define FP_XX (1ull << FPSCR_XX)
#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
#define FP_VXISI (1ull << FPSCR_VXISI)
-#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
-#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
#define FP_VXIDI (1ull << FPSCR_VXIDI)
+#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
+#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
#define FP_VXVC (1ull << FPSCR_VXVC)
+#define FP_FR (1ull << FSPCR_FR)
+#define FP_FI (1ull << FPSCR_FI)
+#define FP_C (1ull << FPSCR_C)
+#define FP_FL (1ull << FPSCR_FL)
+#define FP_FG (1ull << FPSCR_FG)
+#define FP_FE (1ull << FPSCR_FE)
+#define FP_FU (1ull << FPSCR_FU)
+#define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
+#define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
+#define FP_VXSOFT (1ull << FPSCR_VXSOFT)
+#define FP_VXSQRT (1ull << FPSCR_VXSQRT)
#define FP_VXCVI (1ull << FPSCR_VXCVI)
#define FP_VE (1ull << FPSCR_VE)
-#define FP_FI (1ull << FPSCR_FI)
+#define FP_OE (1ull << FPSCR_OE)
+#define FP_UE (1ull << FPSCR_UE)
+#define FP_ZE (1ull << FPSCR_ZE)
+#define FP_XE (1ull << FPSCR_XE)
+#define FP_NI (1ull << FPSCR_NI)
+#define FP_RN1 (1ull << FPSCR_RN1)
+#define FP_RN (1ull << FPSCR_RN)
/*****************************************************************************/
/* Vector status and control register */
--
2.5.0
^ permalink raw reply related [flat|nested] 47+ messages in thread