[PATCH 00/11] ARM: DTS/clk: DRA7 family: enable eDMA and audio updates

[PATCH 00/11] ARM: DTS/clk: DRA7 family: enable eDMA and audio updates

[Peter Ujfalusi]

Hi,

On dra7 family we have two DMA engine available: sDMA (omap-dma) and eDMA.
For some peripherals the use of eDMA is better due to L3 interconnect limitation
when using sDMA. Such peripherals are McASP1/2/3. By switching to eDMA we can
enable the AFIFO which will help to avoid under or overruns in audio.

This set will:
- add the hwmod data for eDMA TPCC and TPTCs
- add the needed DT nodes for eDMA and the crossbar
- we will enable the AFIFO use for audio
- add hwmod data and DT nodes for all McASP ports
- Fix the beagle-x15's clkout2 parent setting for the codec

The patch set has been tested on top of linux-next.

Regards,
Peter
---
Misael Lopez Cruz (1):
  ARM: DTS: dra7: Use eDMA and add DAT port address for McASP3

Peter Ujfalusi (10):
  ARM: DTS: dra7: Move the sDMA crossbar node under l4_cfg/scm
  ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1
  ARM: DTS: dra7: Enable eDMA
  ARM: DTS: dra7-evm: Enable AFIFO use for McASP3
  ARM: DTS: dra72-evm: Enable AFIFO use for McASP3
  ARM: DTS: am57xx-beagle-x15: Move clkout2 source selection to codec
    node
  ARM: DTS: am57xx-beagle-x15: Enable AFIFO use for McASP3
  ARM: clk: dra7xx: Correct mcasp8_ahclkx_mux name
  ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8
  ARM: DTS: dra7: Add nodes for McASP1/2/4/5/6/7/8

 arch/arm/boot/dts/am57xx-beagle-x15.dts   |   7 +-
 arch/arm/boot/dts/dra7-evm.dts            |   2 +
 arch/arm/boot/dts/dra7.dtsi               | 181 ++++++++++++++++-
 arch/arm/boot/dts/dra72-evm.dts           |   2 +
 arch/arm/boot/dts/dra7xx-clocks.dtsi      |   2 +-
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 323 ++++++++++++++++++++++++++++++
 drivers/clk/ti/clk-7xx.c                  |   2 +-
 7 files changed, 505 insertions(+), 14 deletions(-)

-- 
2.7.1

[PATCH 00/11] ARM: DTS/clk: DRA7 family: enable eDMA and audio updates

[Peter Ujfalusi]

Hi,

On dra7 family we have two DMA engine available: sDMA (omap-dma) and eDMA.
For some peripherals the use of eDMA is better due to L3 interconnect limitation
when using sDMA. Such peripherals are McASP1/2/3. By switching to eDMA we can
enable the AFIFO which will help to avoid under or overruns in audio.

This set will:
- add the hwmod data for eDMA TPCC and TPTCs
- add the needed DT nodes for eDMA and the crossbar
- we will enable the AFIFO use for audio
- add hwmod data and DT nodes for all McASP ports
- Fix the beagle-x15's clkout2 parent setting for the codec

The patch set has been tested on top of linux-next.

Regards,
Peter
---
Misael Lopez Cruz (1):
  ARM: DTS: dra7: Use eDMA and add DAT port address for McASP3

Peter Ujfalusi (10):
  ARM: DTS: dra7: Move the sDMA crossbar node under l4_cfg/scm
  ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1
  ARM: DTS: dra7: Enable eDMA
  ARM: DTS: dra7-evm: Enable AFIFO use for McASP3
  ARM: DTS: dra72-evm: Enable AFIFO use for McASP3
  ARM: DTS: am57xx-beagle-x15: Move clkout2 source selection to codec
    node
  ARM: DTS: am57xx-beagle-x15: Enable AFIFO use for McASP3
  ARM: clk: dra7xx: Correct mcasp8_ahclkx_mux name
  ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8
  ARM: DTS: dra7: Add nodes for McASP1/2/4/5/6/7/8

 arch/arm/boot/dts/am57xx-beagle-x15.dts   |   7 +-
 arch/arm/boot/dts/dra7-evm.dts            |   2 +
 arch/arm/boot/dts/dra7.dtsi               | 181 ++++++++++++++++-
 arch/arm/boot/dts/dra72-evm.dts           |   2 +
 arch/arm/boot/dts/dra7xx-clocks.dtsi      |   2 +-
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 323 ++++++++++++++++++++++++++++++
 drivers/clk/ti/clk-7xx.c                  |   2 +-
 7 files changed, 505 insertions(+), 14 deletions(-)

-- 
2.7.1

[PATCH 00/11] ARM: DTS/clk: DRA7 family: enable eDMA and audio updates

[Peter Ujfalusi]

Hi,

On dra7 family we have two DMA engine available: sDMA (omap-dma) and eDMA.
For some peripherals the use of eDMA is better due to L3 interconnect limitation
when using sDMA. Such peripherals are McASP1/2/3. By switching to eDMA we can
enable the AFIFO which will help to avoid under or overruns in audio.

This set will:
- add the hwmod data for eDMA TPCC and TPTCs
- add the needed DT nodes for eDMA and the crossbar
- we will enable the AFIFO use for audio
- add hwmod data and DT nodes for all McASP ports
- Fix the beagle-x15's clkout2 parent setting for the codec

The patch set has been tested on top of linux-next.

Regards,
Peter
---
Misael Lopez Cruz (1):
  ARM: DTS: dra7: Use eDMA and add DAT port address for McASP3

Peter Ujfalusi (10):
  ARM: DTS: dra7: Move the sDMA crossbar node under l4_cfg/scm
  ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1
  ARM: DTS: dra7: Enable eDMA
  ARM: DTS: dra7-evm: Enable AFIFO use for McASP3
  ARM: DTS: dra72-evm: Enable AFIFO use for McASP3
  ARM: DTS: am57xx-beagle-x15: Move clkout2 source selection to codec
    node
  ARM: DTS: am57xx-beagle-x15: Enable AFIFO use for McASP3
  ARM: clk: dra7xx: Correct mcasp8_ahclkx_mux name
  ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8
  ARM: DTS: dra7: Add nodes for McASP1/2/4/5/6/7/8

 arch/arm/boot/dts/am57xx-beagle-x15.dts   |   7 +-
 arch/arm/boot/dts/dra7-evm.dts            |   2 +
 arch/arm/boot/dts/dra7.dtsi               | 181 ++++++++++++++++-
 arch/arm/boot/dts/dra72-evm.dts           |   2 +
 arch/arm/boot/dts/dra7xx-clocks.dtsi      |   2 +-
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 323 ++++++++++++++++++++++++++++++
 drivers/clk/ti/clk-7xx.c                  |   2 +-
 7 files changed, 505 insertions(+), 14 deletions(-)

-- 
2.7.1

[PATCH 01/11] ARM: DTS: dra7: Move the sDMA crossbar node under l4_cfg/scm

[Peter Ujfalusi]

Move the sDMA xbar nodes under the L4 interconnect node.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 8ea153aa46f6..114286dbee25 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -161,6 +161,15 @@
 					compatible = "syscon";
 					reg = <0x1c24 0x0024>;
 				};
+
+				sdma_xbar: dma-router@b78 {
+					compatible = "ti,dra7-dma-crossbar";
+					reg = <0xb78 0xfc>;
+					#dma-cells = <1>;
+					dma-requests = <205>;
+					ti,dma-safe-map = <0>;
+					dma-masters = <&sdma>;
+				};
 			};
 
 			cm_core_aon: cm_core_aon@5000 {
@@ -315,15 +324,6 @@
 			dma-requests = <127>;
 		};
 
-		sdma_xbar: dma-router@4a002b78 {
-			compatible = "ti,dra7-dma-crossbar";
-			reg = <0x4a002b78 0xfc>;
-			#dma-cells = <1>;
-			dma-requests = <205>;
-			ti,dma-safe-map = <0>;
-			dma-masters = <&sdma>;
-		};
-
 		gpio1: gpio@4ae10000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4ae10000 0x200>;
-- 
2.7.1

[PATCH 01/11] ARM: DTS: dra7: Move the sDMA crossbar node under l4_cfg/scm

[Peter Ujfalusi]

Move the sDMA xbar nodes under the L4 interconnect node.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/dra7.dtsi | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 8ea153aa46f6..114286dbee25 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -161,6 +161,15 @@
 					compatible = "syscon";
 					reg = <0x1c24 0x0024>;
 				};
+
+				sdma_xbar: dma-router@b78 {
+					compatible = "ti,dra7-dma-crossbar";
+					reg = <0xb78 0xfc>;
+					#dma-cells = <1>;
+					dma-requests = <205>;
+					ti,dma-safe-map = <0>;
+					dma-masters = <&sdma>;
+				};
 			};
 
 			cm_core_aon: cm_core_aon@5000 {
@@ -315,15 +324,6 @@
 			dma-requests = <127>;
 		};
 
-		sdma_xbar: dma-router@4a002b78 {
-			compatible = "ti,dra7-dma-crossbar";
-			reg = <0x4a002b78 0xfc>;
-			#dma-cells = <1>;
-			dma-requests = <205>;
-			ti,dma-safe-map = <0>;
-			dma-masters = <&sdma>;
-		};
-
 		gpio1: gpio@4ae10000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4ae10000 0x200>;
-- 
2.7.1

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[PATCH 01/11] ARM: DTS: dra7: Move the sDMA crossbar node under l4_cfg/scm

[Peter Ujfalusi]

Move the sDMA xbar nodes under the L4 interconnect node.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 8ea153aa46f6..114286dbee25 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -161,6 +161,15 @@
 					compatible = "syscon";
 					reg = <0x1c24 0x0024>;
 				};
+
+				sdma_xbar: dma-router at b78 {
+					compatible = "ti,dra7-dma-crossbar";
+					reg = <0xb78 0xfc>;
+					#dma-cells = <1>;
+					dma-requests = <205>;
+					ti,dma-safe-map = <0>;
+					dma-masters = <&sdma>;
+				};
 			};
 
 			cm_core_aon: cm_core_aon at 5000 {
@@ -315,15 +324,6 @@
 			dma-requests = <127>;
 		};
 
-		sdma_xbar: dma-router at 4a002b78 {
-			compatible = "ti,dra7-dma-crossbar";
-			reg = <0x4a002b78 0xfc>;
-			#dma-cells = <1>;
-			dma-requests = <205>;
-			ti,dma-safe-map = <0>;
-			dma-masters = <&sdma>;
-		};
-
 		gpio1: gpio at 4ae10000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4ae10000 0x200>;
-- 
2.7.1

[PATCH 02/11] ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1

[Peter Ujfalusi]

Add hwmod data for the eDMA blocks:
 - TPCC: Third-party channel controller
 - TPTC0: Third-party transfer controller 0
 - TPTC1: Third-party transfer controller 1

The TPCC is following it's clock and power domain. This means that
the hwmod can not control it's status.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 88 +++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index b61355e2a771..3953ad031c43 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -430,6 +430,67 @@ static struct omap_hwmod dra7xx_dma_system_hwmod = {
 };
 
 /*
+ * 'tpcc' class
+ *
+ */
+static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
+	.name		= "tpcc",
+};
+
+static struct omap_hwmod dra7xx_tpcc_hwmod = {
+	.name		= "tpcc",
+	.class		= &dra7xx_tpcc_hwmod_class,
+	.clkdm_name	= "l3main1_clkdm",
+	.main_clk	= "l3_iclk_div",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/*
+ * 'tptc' class
+ *
+ */
+static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
+	.name		= "tptc",
+};
+
+/* tptc0 */
+static struct omap_hwmod dra7xx_tptc0_hwmod = {
+	.name		= "tptc0",
+	.class		= &dra7xx_tptc_hwmod_class,
+	.clkdm_name	= "l3main1_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+	.main_clk	= "l3_iclk_div",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/* tptc1 */
+static struct omap_hwmod dra7xx_tptc1_hwmod = {
+	.name		= "tptc1",
+	.class		= &dra7xx_tptc_hwmod_class,
+	.clkdm_name	= "l3main1_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+	.main_clk	= "l3_iclk_div",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/*
  * 'dss' class
  *
  */
@@ -2563,6 +2624,30 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l3_main_1 -> tpcc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_tpcc_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU,
+};
+
+/* l3_main_1 -> tptc0 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_tptc0_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU,
+};
+
+/* l3_main_1 -> tptc1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_tptc1_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU,
+};
+
 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
 	{
 		.name		= "family",
@@ -3380,6 +3465,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 	&dra7xx_l3_main_1__mcasp3,
 	&dra7xx_gmac__mdio,
 	&dra7xx_l4_cfg__dma_system,
+	&dra7xx_l3_main_1__tpcc,
+	&dra7xx_l3_main_1__tptc0,
+	&dra7xx_l3_main_1__tptc1,
 	&dra7xx_l3_main_1__dss,
 	&dra7xx_l3_main_1__dispc,
 	&dra7xx_l3_main_1__hdmi,
-- 
2.7.1

[PATCH 02/11] ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1

[Peter Ujfalusi]

Add hwmod data for the eDMA blocks:
 - TPCC: Third-party channel controller
 - TPTC0: Third-party transfer controller 0
 - TPTC1: Third-party transfer controller 1

The TPCC is following it's clock and power domain. This means that
the hwmod can not control it's status.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 88 +++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index b61355e2a771..3953ad031c43 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -430,6 +430,67 @@ static struct omap_hwmod dra7xx_dma_system_hwmod = {
 };
 
 /*
+ * 'tpcc' class
+ *
+ */
+static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
+	.name		= "tpcc",
+};
+
+static struct omap_hwmod dra7xx_tpcc_hwmod = {
+	.name		= "tpcc",
+	.class		= &dra7xx_tpcc_hwmod_class,
+	.clkdm_name	= "l3main1_clkdm",
+	.main_clk	= "l3_iclk_div",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/*
+ * 'tptc' class
+ *
+ */
+static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
+	.name		= "tptc",
+};
+
+/* tptc0 */
+static struct omap_hwmod dra7xx_tptc0_hwmod = {
+	.name		= "tptc0",
+	.class		= &dra7xx_tptc_hwmod_class,
+	.clkdm_name	= "l3main1_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+	.main_clk	= "l3_iclk_div",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/* tptc1 */
+static struct omap_hwmod dra7xx_tptc1_hwmod = {
+	.name		= "tptc1",
+	.class		= &dra7xx_tptc_hwmod_class,
+	.clkdm_name	= "l3main1_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+	.main_clk	= "l3_iclk_div",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/*
  * 'dss' class
  *
  */
@@ -2563,6 +2624,30 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l3_main_1 -> tpcc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_tpcc_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU,
+};
+
+/* l3_main_1 -> tptc0 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_tptc0_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU,
+};
+
+/* l3_main_1 -> tptc1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_tptc1_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU,
+};
+
 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
 	{
 		.name		= "family",
@@ -3380,6 +3465,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 	&dra7xx_l3_main_1__mcasp3,
 	&dra7xx_gmac__mdio,
 	&dra7xx_l4_cfg__dma_system,
+	&dra7xx_l3_main_1__tpcc,
+	&dra7xx_l3_main_1__tptc0,
+	&dra7xx_l3_main_1__tptc1,
 	&dra7xx_l3_main_1__dss,
 	&dra7xx_l3_main_1__dispc,
 	&dra7xx_l3_main_1__hdmi,
-- 
2.7.1

[PATCH 02/11] ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1

[Peter Ujfalusi]

Add hwmod data for the eDMA blocks:
 - TPCC: Third-party channel controller
 - TPTC0: Third-party transfer controller 0
 - TPTC1: Third-party transfer controller 1

The TPCC is following it's clock and power domain. This means that
the hwmod can not control it's status.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 88 +++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index b61355e2a771..3953ad031c43 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -430,6 +430,67 @@ static struct omap_hwmod dra7xx_dma_system_hwmod = {
 };
 
 /*
+ * 'tpcc' class
+ *
+ */
+static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
+	.name		= "tpcc",
+};
+
+static struct omap_hwmod dra7xx_tpcc_hwmod = {
+	.name		= "tpcc",
+	.class		= &dra7xx_tpcc_hwmod_class,
+	.clkdm_name	= "l3main1_clkdm",
+	.main_clk	= "l3_iclk_div",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/*
+ * 'tptc' class
+ *
+ */
+static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
+	.name		= "tptc",
+};
+
+/* tptc0 */
+static struct omap_hwmod dra7xx_tptc0_hwmod = {
+	.name		= "tptc0",
+	.class		= &dra7xx_tptc_hwmod_class,
+	.clkdm_name	= "l3main1_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+	.main_clk	= "l3_iclk_div",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/* tptc1 */
+static struct omap_hwmod dra7xx_tptc1_hwmod = {
+	.name		= "tptc1",
+	.class		= &dra7xx_tptc_hwmod_class,
+	.clkdm_name	= "l3main1_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+	.main_clk	= "l3_iclk_div",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/*
  * 'dss' class
  *
  */
@@ -2563,6 +2624,30 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l3_main_1 -> tpcc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_tpcc_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU,
+};
+
+/* l3_main_1 -> tptc0 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_tptc0_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU,
+};
+
+/* l3_main_1 -> tptc1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_tptc1_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU,
+};
+
 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
 	{
 		.name		= "family",
@@ -3380,6 +3465,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 	&dra7xx_l3_main_1__mcasp3,
 	&dra7xx_gmac__mdio,
 	&dra7xx_l4_cfg__dma_system,
+	&dra7xx_l3_main_1__tpcc,
+	&dra7xx_l3_main_1__tptc0,
+	&dra7xx_l3_main_1__tptc1,
 	&dra7xx_l3_main_1__dss,
 	&dra7xx_l3_main_1__dispc,
 	&dra7xx_l3_main_1__hdmi,
-- 
2.7.1

[PATCH 03/11] ARM: DTS: dra7: Enable eDMA

[Peter Ujfalusi]

DRA7 family has eDMA available along with the sDMA and in some cases it is
better suited for servicing peripherals.

Add the needed nodes for eDMA to be usable:
edma-tpcc, edma-tptc0/1 and the edma-xbar.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 48 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 114286dbee25..d2d2568b5695 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -170,6 +170,15 @@
 					ti,dma-safe-map = <0>;
 					dma-masters = <&sdma>;
 				};
+
+				edma_xbar: dma-router@c78 {
+					compatible = "ti,dra7-dma-crossbar";
+					reg = <0xc78 0x7c>;
+					#dma-cells = <2>;
+					dma-requests = <204>;
+					ti,dma-safe-map = <0>;
+					dma-masters = <&edma>;
+				};
 			};
 
 			cm_core_aon: cm_core_aon@5000 {
@@ -324,6 +333,45 @@
 			dma-requests = <127>;
 		};
 
+		edma: edma@43300000 {
+			compatible = "ti,edma3-tpcc";
+			ti,hwmods = "tpcc";
+			reg = <0x43300000 0x100000>;
+			reg-names = "edma3_cc";
+			interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma3_ccint", "emda3_mperr",
+					  "edma3_ccerrint";
+			dma-requests = <64>;
+			#dma-cells = <2>;
+
+			ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
+
+			/*
+			 * memcpy is disabled, can be enabled with:
+			 * ti,edma-memcpy-channels = <20 21>;
+			 * for example. Note that these channels need to be
+			 * masked in the xbar as well.
+			 */
+		};
+
+		edma_tptc0: tptc@43400000 {
+			compatible = "ti,edma3-tptc";
+			ti,hwmods = "tptc0";
+			reg =	<0x43400000 0x100000>;
+			interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma3_tcerrint";
+		};
+
+		edma_tptc1: tptc@43500000 {
+			compatible = "ti,edma3-tptc";
+			ti,hwmods = "tptc1";
+			reg =	<0x43500000 0x100000>;
+			interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma3_tcerrint";
+		};
+
 		gpio1: gpio@4ae10000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4ae10000 0x200>;
-- 
2.7.1

[PATCH 03/11] ARM: DTS: dra7: Enable eDMA

[Peter Ujfalusi]

DRA7 family has eDMA available along with the sDMA and in some cases it is
better suited for servicing peripherals.

Add the needed nodes for eDMA to be usable:
edma-tpcc, edma-tptc0/1 and the edma-xbar.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 48 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 114286dbee25..d2d2568b5695 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -170,6 +170,15 @@
 					ti,dma-safe-map = <0>;
 					dma-masters = <&sdma>;
 				};
+
+				edma_xbar: dma-router@c78 {
+					compatible = "ti,dra7-dma-crossbar";
+					reg = <0xc78 0x7c>;
+					#dma-cells = <2>;
+					dma-requests = <204>;
+					ti,dma-safe-map = <0>;
+					dma-masters = <&edma>;
+				};
 			};
 
 			cm_core_aon: cm_core_aon@5000 {
@@ -324,6 +333,45 @@
 			dma-requests = <127>;
 		};
 
+		edma: edma@43300000 {
+			compatible = "ti,edma3-tpcc";
+			ti,hwmods = "tpcc";
+			reg = <0x43300000 0x100000>;
+			reg-names = "edma3_cc";
+			interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma3_ccint", "emda3_mperr",
+					  "edma3_ccerrint";
+			dma-requests = <64>;
+			#dma-cells = <2>;
+
+			ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
+
+			/*
+			 * memcpy is disabled, can be enabled with:
+			 * ti,edma-memcpy-channels = <20 21>;
+			 * for example. Note that these channels need to be
+			 * masked in the xbar as well.
+			 */
+		};
+
+		edma_tptc0: tptc@43400000 {
+			compatible = "ti,edma3-tptc";
+			ti,hwmods = "tptc0";
+			reg =	<0x43400000 0x100000>;
+			interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma3_tcerrint";
+		};
+
+		edma_tptc1: tptc@43500000 {
+			compatible = "ti,edma3-tptc";
+			ti,hwmods = "tptc1";
+			reg =	<0x43500000 0x100000>;
+			interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma3_tcerrint";
+		};
+
 		gpio1: gpio@4ae10000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4ae10000 0x200>;
-- 
2.7.1

[PATCH 03/11] ARM: DTS: dra7: Enable eDMA

[Peter Ujfalusi]

DRA7 family has eDMA available along with the sDMA and in some cases it is
better suited for servicing peripherals.

Add the needed nodes for eDMA to be usable:
edma-tpcc, edma-tptc0/1 and the edma-xbar.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 48 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 114286dbee25..d2d2568b5695 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -170,6 +170,15 @@
 					ti,dma-safe-map = <0>;
 					dma-masters = <&sdma>;
 				};
+
+				edma_xbar: dma-router at c78 {
+					compatible = "ti,dra7-dma-crossbar";
+					reg = <0xc78 0x7c>;
+					#dma-cells = <2>;
+					dma-requests = <204>;
+					ti,dma-safe-map = <0>;
+					dma-masters = <&edma>;
+				};
 			};
 
 			cm_core_aon: cm_core_aon at 5000 {
@@ -324,6 +333,45 @@
 			dma-requests = <127>;
 		};
 
+		edma: edma at 43300000 {
+			compatible = "ti,edma3-tpcc";
+			ti,hwmods = "tpcc";
+			reg = <0x43300000 0x100000>;
+			reg-names = "edma3_cc";
+			interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma3_ccint", "emda3_mperr",
+					  "edma3_ccerrint";
+			dma-requests = <64>;
+			#dma-cells = <2>;
+
+			ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
+
+			/*
+			 * memcpy is disabled, can be enabled with:
+			 * ti,edma-memcpy-channels = <20 21>;
+			 * for example. Note that these channels need to be
+			 * masked in the xbar as well.
+			 */
+		};
+
+		edma_tptc0: tptc at 43400000 {
+			compatible = "ti,edma3-tptc";
+			ti,hwmods = "tptc0";
+			reg =	<0x43400000 0x100000>;
+			interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma3_tcerrint";
+		};
+
+		edma_tptc1: tptc at 43500000 {
+			compatible = "ti,edma3-tptc";
+			ti,hwmods = "tptc1";
+			reg =	<0x43500000 0x100000>;
+			interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma3_tcerrint";
+		};
+
 		gpio1: gpio at 4ae10000 {
 			compatible = "ti,omap4-gpio";
 			reg = <0x4ae10000 0x200>;
-- 
2.7.1

[PATCH 04/11] ARM: DTS: dra7: Use eDMA and add DAT port address for McASP3

[Peter Ujfalusi]

From: Misael Lopez Cruz <misael.lopez@ti.com>

McASP3 does not support constant addressing mode on the DAT
port, so increment transfers must be used instead.  This
restriction is also applicable for McASP1 and McASP2.

This DMA addressing constraint poses a major problem for sDMA
where constant addressing mode is used on the peripheral side.
Unfortunately, using increment transfers in sDMA comes with
important side effects.

The addressing mode used in eDMA is INC, so the silicon limitation
described above has no impact and the McASP3 DAT port can be
safely added by switching to eDMA instead of sDMA.

Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d2d2568b5695..258e6712a76b 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1467,12 +1467,13 @@
 		mcasp3: mcasp@48468000 {
 			compatible = "ti,dra7-mcasp-audio";
 			ti,hwmods = "mcasp3";
-			reg = <0x48468000 0x2000>;
-			reg-names = "mpu";
+			reg = <0x48468000 0x2000>,
+			      <0x46000000 0x1000>;
+			reg-names = "mpu","dat";
 			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "tx", "rx";
-			dmas = <&sdma_xbar 133>, <&sdma_xbar 132>;
+			dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
 			dma-names = "tx", "rx";
 			clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
 			clock-names = "fck", "ahclkx";
-- 
2.7.1

[PATCH 04/11] ARM: DTS: dra7: Use eDMA and add DAT port address for McASP3

[Peter Ujfalusi]

From: Misael Lopez Cruz <misael.lopez@ti.com>

McASP3 does not support constant addressing mode on the DAT
port, so increment transfers must be used instead.  This
restriction is also applicable for McASP1 and McASP2.

This DMA addressing constraint poses a major problem for sDMA
where constant addressing mode is used on the peripheral side.
Unfortunately, using increment transfers in sDMA comes with
important side effects.

The addressing mode used in eDMA is INC, so the silicon limitation
described above has no impact and the McASP3 DAT port can be
safely added by switching to eDMA instead of sDMA.

Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d2d2568b5695..258e6712a76b 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1467,12 +1467,13 @@
 		mcasp3: mcasp@48468000 {
 			compatible = "ti,dra7-mcasp-audio";
 			ti,hwmods = "mcasp3";
-			reg = <0x48468000 0x2000>;
-			reg-names = "mpu";
+			reg = <0x48468000 0x2000>,
+			      <0x46000000 0x1000>;
+			reg-names = "mpu","dat";
 			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "tx", "rx";
-			dmas = <&sdma_xbar 133>, <&sdma_xbar 132>;
+			dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
 			dma-names = "tx", "rx";
 			clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
 			clock-names = "fck", "ahclkx";
-- 
2.7.1

[PATCH 04/11] ARM: DTS: dra7: Use eDMA and add DAT port address for McASP3

[Peter Ujfalusi]

From: Misael Lopez Cruz <misael.lopez@ti.com>

McASP3 does not support constant addressing mode on the DAT
port, so increment transfers must be used instead.  This
restriction is also applicable for McASP1 and McASP2.

This DMA addressing constraint poses a major problem for sDMA
where constant addressing mode is used on the peripheral side.
Unfortunately, using increment transfers in sDMA comes with
important side effects.

The addressing mode used in eDMA is INC, so the silicon limitation
described above has no impact and the McASP3 DAT port can be
safely added by switching to eDMA instead of sDMA.

Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d2d2568b5695..258e6712a76b 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1467,12 +1467,13 @@
 		mcasp3: mcasp at 48468000 {
 			compatible = "ti,dra7-mcasp-audio";
 			ti,hwmods = "mcasp3";
-			reg = <0x48468000 0x2000>;
-			reg-names = "mpu";
+			reg = <0x48468000 0x2000>,
+			      <0x46000000 0x1000>;
+			reg-names = "mpu","dat";
 			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "tx", "rx";
-			dmas = <&sdma_xbar 133>, <&sdma_xbar 132>;
+			dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
 			dma-names = "tx", "rx";
 			clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
 			clock-names = "fck", "ahclkx";
-- 
2.7.1

[PATCH 05/11] ARM: DTS: dra7-evm: Enable AFIFO use for McASP3

[Peter Ujfalusi]

Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7-evm.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index cfc24e52244e..ebdbfcc96a6f 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -901,6 +901,8 @@
 	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 		1 2 0 0
 	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
 };
 
 &mailbox5 {
-- 
2.7.1

[PATCH 05/11] ARM: DTS: dra7-evm: Enable AFIFO use for McASP3

[Peter Ujfalusi]

Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7-evm.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index cfc24e52244e..ebdbfcc96a6f 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -901,6 +901,8 @@
 	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 		1 2 0 0
 	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
 };
 
 &mailbox5 {
-- 
2.7.1

[PATCH 05/11] ARM: DTS: dra7-evm: Enable AFIFO use for McASP3

[Peter Ujfalusi]

Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7-evm.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index cfc24e52244e..ebdbfcc96a6f 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -901,6 +901,8 @@
 	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 		1 2 0 0
 	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
 };
 
 &mailbox5 {
-- 
2.7.1

[PATCH 06/11] ARM: DTS: dra72-evm: Enable AFIFO use for McASP3

[Peter Ujfalusi]

Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra72-evm.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 00b12002c07c..18711124616a 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -831,6 +831,8 @@
 	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 		1 2 0 0
 	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
 };
 
 &mailbox5 {
-- 
2.7.1

[PATCH 06/11] ARM: DTS: dra72-evm: Enable AFIFO use for McASP3

[Peter Ujfalusi]

Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra72-evm.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 00b12002c07c..18711124616a 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -831,6 +831,8 @@
 	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 		1 2 0 0
 	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
 };
 
 &mailbox5 {
-- 
2.7.1

[PATCH 06/11] ARM: DTS: dra72-evm: Enable AFIFO use for McASP3

[Peter Ujfalusi]

Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra72-evm.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 00b12002c07c..18711124616a 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -831,6 +831,8 @@
 	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 		1 2 0 0
 	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
 };
 
 &mailbox5 {
-- 
2.7.1

[PATCH 07/11] ARM: DTS: am57xx-beagle-x15: Move clkout2 source selection to codec node

[Peter Ujfalusi]

The assigned-clock* needs to be in the root of the device's node. If it is
in the sub-node the CCF will ignore it.
Since the clkout2 is used by the codec as MCLK, move the clock parent
selection to that node.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/am57xx-beagle-x15.dts | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index b25d68496c7d..86351372174f 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -173,8 +173,6 @@
 
 		sound0_master: simple-audio-card,codec {
 			sound-dai = <&tlv320aic3104>;
-			assigned-clocks = <&clkoutmux2_clk_mux>;
-			assigned-clock-parents = <&sys_clk2_dclk_div>;
 			clocks = <&clkout2_clk>;
 		};
 	};
@@ -584,6 +582,9 @@
 		pinctrl-names = "default", "sleep";
 		pinctrl-0 = <&clkout2_pins_default>;
 		pinctrl-1 = <&clkout2_pins_sleep>;
+		assigned-clocks = <&clkoutmux2_clk_mux>;
+		assigned-clock-parents = <&sys_clk2_dclk_div>;
+
 		status = "okay";
 		adc-settle-ms = <40>;
 
-- 
2.7.1

[PATCH 07/11] ARM: DTS: am57xx-beagle-x15: Move clkout2 source selection to codec node

[Peter Ujfalusi]

The assigned-clock* needs to be in the root of the device's node. If it is
in the sub-node the CCF will ignore it.
Since the clkout2 is used by the codec as MCLK, move the clock parent
selection to that node.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/am57xx-beagle-x15.dts | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index b25d68496c7d..86351372174f 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -173,8 +173,6 @@
 
 		sound0_master: simple-audio-card,codec {
 			sound-dai = <&tlv320aic3104>;
-			assigned-clocks = <&clkoutmux2_clk_mux>;
-			assigned-clock-parents = <&sys_clk2_dclk_div>;
 			clocks = <&clkout2_clk>;
 		};
 	};
@@ -584,6 +582,9 @@
 		pinctrl-names = "default", "sleep";
 		pinctrl-0 = <&clkout2_pins_default>;
 		pinctrl-1 = <&clkout2_pins_sleep>;
+		assigned-clocks = <&clkoutmux2_clk_mux>;
+		assigned-clock-parents = <&sys_clk2_dclk_div>;
+
 		status = "okay";
 		adc-settle-ms = <40>;
 
-- 
2.7.1

[PATCH 07/11] ARM: DTS: am57xx-beagle-x15: Move clkout2 source selection to codec node

[Peter Ujfalusi]

The assigned-clock* needs to be in the root of the device's node. If it is
in the sub-node the CCF will ignore it.
Since the clkout2 is used by the codec as MCLK, move the clock parent
selection to that node.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/am57xx-beagle-x15.dts | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index b25d68496c7d..86351372174f 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -173,8 +173,6 @@
 
 		sound0_master: simple-audio-card,codec {
 			sound-dai = <&tlv320aic3104>;
-			assigned-clocks = <&clkoutmux2_clk_mux>;
-			assigned-clock-parents = <&sys_clk2_dclk_div>;
 			clocks = <&clkout2_clk>;
 		};
 	};
@@ -584,6 +582,9 @@
 		pinctrl-names = "default", "sleep";
 		pinctrl-0 = <&clkout2_pins_default>;
 		pinctrl-1 = <&clkout2_pins_sleep>;
+		assigned-clocks = <&clkoutmux2_clk_mux>;
+		assigned-clock-parents = <&sys_clk2_dclk_div>;
+
 		status = "okay";
 		adc-settle-ms = <40>;
 
-- 
2.7.1

[PATCH 08/11] ARM: DTS: am57xx-beagle-x15: Enable AFIFO use for McASP3

[Peter Ujfalusi]

Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/am57xx-beagle-x15.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 86351372174f..7e1d11177732 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -813,6 +813,8 @@
 	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
 		1 2 0 0
 	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
 };
 
 &mailbox5 {
-- 
2.7.1

[PATCH 08/11] ARM: DTS: am57xx-beagle-x15: Enable AFIFO use for McASP3

[Peter Ujfalusi]

Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/am57xx-beagle-x15.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 86351372174f..7e1d11177732 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -813,6 +813,8 @@
 	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
 		1 2 0 0
 	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
 };
 
 &mailbox5 {
-- 
2.7.1

[PATCH 08/11] ARM: DTS: am57xx-beagle-x15: Enable AFIFO use for McASP3

[Peter Ujfalusi]

Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/am57xx-beagle-x15.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 86351372174f..7e1d11177732 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -813,6 +813,8 @@
 	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
 		1 2 0 0
 	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
 };
 
 &mailbox5 {
-- 
2.7.1

[PATCH 09/11] ARM: clk: dra7xx: Correct mcasp8_ahclkx_mux name

[Peter Ujfalusi]

rename the mcasp8_ahclk_mux to mcasp8_ahclkx_mux.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +-
 drivers/clk/ti/clk-7xx.c             | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 357bedeebfac..8be2cbe0e7e4 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1856,7 +1856,7 @@
 		reg = <0x1908>;
 	};
 
-	mcasp8_ahclk_mux: mcasp8_ahclk_mux {
+	mcasp8_ahclkx_mux: mcasp8_ahclkx_mux {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index a911d7de3377..6b5a309d9939 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -223,7 +223,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
 	DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"),
 	DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"),
 	DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"),
-	DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"),
+	DT_CLK(NULL, "mcasp8_ahclkx_mux", "mcasp8_ahclkx_mux"),
 	DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"),
 	DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
 	DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"),
-- 
2.7.1

[PATCH 09/11] ARM: clk: dra7xx: Correct mcasp8_ahclkx_mux name

[Peter Ujfalusi]

rename the mcasp8_ahclk_mux to mcasp8_ahclkx_mux.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +-
 drivers/clk/ti/clk-7xx.c             | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 357bedeebfac..8be2cbe0e7e4 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1856,7 +1856,7 @@
 		reg = <0x1908>;
 	};
 
-	mcasp8_ahclk_mux: mcasp8_ahclk_mux {
+	mcasp8_ahclkx_mux: mcasp8_ahclkx_mux {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index a911d7de3377..6b5a309d9939 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -223,7 +223,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
 	DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"),
 	DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"),
 	DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"),
-	DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"),
+	DT_CLK(NULL, "mcasp8_ahclkx_mux", "mcasp8_ahclkx_mux"),
 	DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"),
 	DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
 	DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"),
-- 
2.7.1

[PATCH 09/11] ARM: clk: dra7xx: Correct mcasp8_ahclkx_mux name

[Peter Ujfalusi]

rename the mcasp8_ahclk_mux to mcasp8_ahclkx_mux.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +-
 drivers/clk/ti/clk-7xx.c             | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 357bedeebfac..8be2cbe0e7e4 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1856,7 +1856,7 @@
 		reg = <0x1908>;
 	};
 
-	mcasp8_ahclk_mux: mcasp8_ahclk_mux {
+	mcasp8_ahclkx_mux: mcasp8_ahclkx_mux {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index a911d7de3377..6b5a309d9939 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -223,7 +223,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
 	DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"),
 	DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"),
 	DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"),
-	DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"),
+	DT_CLK(NULL, "mcasp8_ahclkx_mux", "mcasp8_ahclkx_mux"),
 	DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"),
 	DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
 	DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"),
-- 
2.7.1

[PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Peter Ujfalusi]

Add missing data for all McASP ports for the dra7 family

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 235 ++++++++++++++++++++++++++++++
 1 file changed, 235 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 3953ad031c43..3bd067afa702 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1374,6 +1374,50 @@ static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
 	.sysc	= &dra7xx_mcasp_sysc,
 };
 
+/* mcasp1 */
+static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp1_hwmod = {
+	.name		= "mcasp1",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "ipu_clkdm",
+	.main_clk	= "mcasp1_aux_gfclk_mux",
+	.flags		= HWMOD_SWSUP_SIDLE,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp1_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp1_opt_clks),
+};
+
+/* mcasp2 */
+static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp2_hwmod = {
+	.name		= "mcasp2",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp2_aux_gfclk_mux",
+	.flags		= HWMOD_SWSUP_SIDLE,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp2_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp2_opt_clks),
+};
+
 /* mcasp3 */
 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
 	{ .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
@@ -1396,6 +1440,116 @@ static struct omap_hwmod dra7xx_mcasp3_hwmod = {
 	.opt_clks_cnt	= ARRAY_SIZE(mcasp3_opt_clks),
 };
 
+/* mcasp4 */
+static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp4_hwmod = {
+	.name		= "mcasp4",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp4_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp4_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp4_opt_clks),
+};
+
+/* mcasp5 */
+static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp5_hwmod = {
+	.name		= "mcasp5",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp5_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp5_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp5_opt_clks),
+};
+
+/* mcasp6 */
+static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp6_hwmod = {
+	.name		= "mcasp6",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp6_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp6_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp6_opt_clks),
+};
+
+/* mcasp7 */
+static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp7_hwmod = {
+	.name		= "mcasp7",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp7_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp7_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp7_opt_clks),
+};
+
+/* mcasp8 */
+static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp8_hwmod = {
+	.name		= "mcasp8",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp8_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp8_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp8_opt_clks),
+};
+
 /*
  * 'mmc' class
  *
@@ -2703,6 +2857,38 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_per2 -> mcasp1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp1_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> mcasp1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_mcasp1_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp2_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> mcasp2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_mcasp2_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l4_per2 -> mcasp3 */
 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
 	.master		= &dra7xx_l4_per2_hwmod,
@@ -2719,6 +2905,46 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_per2 -> mcasp4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp4_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp5_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp6_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp7_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp8_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l4_per1 -> elm */
 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
 	.master		= &dra7xx_l4_per1_hwmod,
@@ -3461,8 +3687,17 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 	&dra7xx_l4_wkup__dcan1,
 	&dra7xx_l4_per2__dcan2,
 	&dra7xx_l4_per2__cpgmac0,
+	&dra7xx_l4_per2__mcasp1,
+	&dra7xx_l3_main_1__mcasp1,
+	&dra7xx_l4_per2__mcasp2,
+	&dra7xx_l3_main_1__mcasp2,
 	&dra7xx_l4_per2__mcasp3,
 	&dra7xx_l3_main_1__mcasp3,
+	&dra7xx_l4_per2__mcasp4,
+	&dra7xx_l4_per2__mcasp5,
+	&dra7xx_l4_per2__mcasp6,
+	&dra7xx_l4_per2__mcasp7,
+	&dra7xx_l4_per2__mcasp8,
 	&dra7xx_gmac__mdio,
 	&dra7xx_l4_cfg__dma_system,
 	&dra7xx_l3_main_1__tpcc,
-- 
2.7.1

[PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Peter Ujfalusi]

Add missing data for all McASP ports for the dra7 family

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 235 ++++++++++++++++++++++++++++++
 1 file changed, 235 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 3953ad031c43..3bd067afa702 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1374,6 +1374,50 @@ static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
 	.sysc	= &dra7xx_mcasp_sysc,
 };
 
+/* mcasp1 */
+static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp1_hwmod = {
+	.name		= "mcasp1",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "ipu_clkdm",
+	.main_clk	= "mcasp1_aux_gfclk_mux",
+	.flags		= HWMOD_SWSUP_SIDLE,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp1_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp1_opt_clks),
+};
+
+/* mcasp2 */
+static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp2_hwmod = {
+	.name		= "mcasp2",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp2_aux_gfclk_mux",
+	.flags		= HWMOD_SWSUP_SIDLE,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp2_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp2_opt_clks),
+};
+
 /* mcasp3 */
 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
 	{ .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
@@ -1396,6 +1440,116 @@ static struct omap_hwmod dra7xx_mcasp3_hwmod = {
 	.opt_clks_cnt	= ARRAY_SIZE(mcasp3_opt_clks),
 };
 
+/* mcasp4 */
+static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp4_hwmod = {
+	.name		= "mcasp4",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp4_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp4_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp4_opt_clks),
+};
+
+/* mcasp5 */
+static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp5_hwmod = {
+	.name		= "mcasp5",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp5_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp5_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp5_opt_clks),
+};
+
+/* mcasp6 */
+static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp6_hwmod = {
+	.name		= "mcasp6",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp6_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp6_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp6_opt_clks),
+};
+
+/* mcasp7 */
+static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp7_hwmod = {
+	.name		= "mcasp7",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp7_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp7_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp7_opt_clks),
+};
+
+/* mcasp8 */
+static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp8_hwmod = {
+	.name		= "mcasp8",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp8_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp8_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp8_opt_clks),
+};
+
 /*
  * 'mmc' class
  *
@@ -2703,6 +2857,38 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_per2 -> mcasp1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp1_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> mcasp1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_mcasp1_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp2_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> mcasp2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_mcasp2_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l4_per2 -> mcasp3 */
 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
 	.master		= &dra7xx_l4_per2_hwmod,
@@ -2719,6 +2905,46 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_per2 -> mcasp4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp4_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp5_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp6_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp7_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp8_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l4_per1 -> elm */
 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
 	.master		= &dra7xx_l4_per1_hwmod,
@@ -3461,8 +3687,17 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 	&dra7xx_l4_wkup__dcan1,
 	&dra7xx_l4_per2__dcan2,
 	&dra7xx_l4_per2__cpgmac0,
+	&dra7xx_l4_per2__mcasp1,
+	&dra7xx_l3_main_1__mcasp1,
+	&dra7xx_l4_per2__mcasp2,
+	&dra7xx_l3_main_1__mcasp2,
 	&dra7xx_l4_per2__mcasp3,
 	&dra7xx_l3_main_1__mcasp3,
+	&dra7xx_l4_per2__mcasp4,
+	&dra7xx_l4_per2__mcasp5,
+	&dra7xx_l4_per2__mcasp6,
+	&dra7xx_l4_per2__mcasp7,
+	&dra7xx_l4_per2__mcasp8,
 	&dra7xx_gmac__mdio,
 	&dra7xx_l4_cfg__dma_system,
 	&dra7xx_l3_main_1__tpcc,
-- 
2.7.1

[PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Peter Ujfalusi]

Add missing data for all McASP ports for the dra7 family

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 235 ++++++++++++++++++++++++++++++
 1 file changed, 235 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 3953ad031c43..3bd067afa702 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1374,6 +1374,50 @@ static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
 	.sysc	= &dra7xx_mcasp_sysc,
 };
 
+/* mcasp1 */
+static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp1_hwmod = {
+	.name		= "mcasp1",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "ipu_clkdm",
+	.main_clk	= "mcasp1_aux_gfclk_mux",
+	.flags		= HWMOD_SWSUP_SIDLE,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp1_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp1_opt_clks),
+};
+
+/* mcasp2 */
+static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp2_hwmod = {
+	.name		= "mcasp2",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp2_aux_gfclk_mux",
+	.flags		= HWMOD_SWSUP_SIDLE,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp2_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp2_opt_clks),
+};
+
 /* mcasp3 */
 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
 	{ .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
@@ -1396,6 +1440,116 @@ static struct omap_hwmod dra7xx_mcasp3_hwmod = {
 	.opt_clks_cnt	= ARRAY_SIZE(mcasp3_opt_clks),
 };
 
+/* mcasp4 */
+static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp4_hwmod = {
+	.name		= "mcasp4",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp4_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp4_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp4_opt_clks),
+};
+
+/* mcasp5 */
+static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp5_hwmod = {
+	.name		= "mcasp5",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp5_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp5_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp5_opt_clks),
+};
+
+/* mcasp6 */
+static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp6_hwmod = {
+	.name		= "mcasp6",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp6_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp6_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp6_opt_clks),
+};
+
+/* mcasp7 */
+static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp7_hwmod = {
+	.name		= "mcasp7",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp7_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp7_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp7_opt_clks),
+};
+
+/* mcasp8 */
+static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
+	{ .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
+};
+
+static struct omap_hwmod dra7xx_mcasp8_hwmod = {
+	.name		= "mcasp8",
+	.class		= &dra7xx_mcasp_hwmod_class,
+	.clkdm_name	= "l4per2_clkdm",
+	.main_clk	= "mcasp8_aux_gfclk_mux",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= mcasp8_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcasp8_opt_clks),
+};
+
 /*
  * 'mmc' class
  *
@@ -2703,6 +2857,38 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_per2 -> mcasp1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp1_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> mcasp1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_mcasp1_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp2_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> mcasp2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_mcasp2_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l4_per2 -> mcasp3 */
 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
 	.master		= &dra7xx_l4_per2_hwmod,
@@ -2719,6 +2905,46 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_per2 -> mcasp4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp4_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp5_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp6_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp7_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> mcasp8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
+	.master		= &dra7xx_l4_per2_hwmod,
+	.slave		= &dra7xx_mcasp8_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l4_per1 -> elm */
 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
 	.master		= &dra7xx_l4_per1_hwmod,
@@ -3461,8 +3687,17 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 	&dra7xx_l4_wkup__dcan1,
 	&dra7xx_l4_per2__dcan2,
 	&dra7xx_l4_per2__cpgmac0,
+	&dra7xx_l4_per2__mcasp1,
+	&dra7xx_l3_main_1__mcasp1,
+	&dra7xx_l4_per2__mcasp2,
+	&dra7xx_l3_main_1__mcasp2,
 	&dra7xx_l4_per2__mcasp3,
 	&dra7xx_l3_main_1__mcasp3,
+	&dra7xx_l4_per2__mcasp4,
+	&dra7xx_l4_per2__mcasp5,
+	&dra7xx_l4_per2__mcasp6,
+	&dra7xx_l4_per2__mcasp7,
+	&dra7xx_l4_per2__mcasp8,
 	&dra7xx_gmac__mdio,
 	&dra7xx_l4_cfg__dma_system,
 	&dra7xx_l3_main_1__tpcc,
-- 
2.7.1

[PATCH 11/11] ARM: DTS: dra7: Add nodes for McASP1/2/4/5/6/7/8

[Peter Ujfalusi]

Add nodes to represent all McASP ports in the dra7 family.
For system consistency use the eDMA for audio operations. sDMA would be
fine for 4/5/6/7/8 since their DAT port is not through L3 interconnect.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 112 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 112 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 258e6712a76b..700382093922 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1464,6 +1464,38 @@
 			status = "disabled";
 		};
 
+		mcasp1: mcasp@48460000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp1";
+			reg = <0x48460000 0x2000>,
+			      <0x45800000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp2: mcasp@48464000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp2";
+			reg = <0x48464000 0x2000>,
+			      <0x45c00000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
 		mcasp3: mcasp@48468000 {
 			compatible = "ti,dra7-mcasp-audio";
 			ti,hwmods = "mcasp3";
@@ -1480,6 +1512,86 @@
 			status = "disabled";
 		};
 
+		mcasp4: mcasp@4846c000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp4";
+			reg = <0x4846c000 0x2000>,
+			      <0x48436000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp5: mcasp@48470000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp5";
+			reg = <0x48470000 0x2000>,
+			      <0x4843a000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp6: mcasp@48474000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp6";
+			reg = <0x48474000 0x2000>,
+			      <0x4844c000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp7: mcasp@48478000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp7";
+			reg = <0x48478000 0x2000>,
+			      <0x48450000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp8: mcasp@4847c000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp8";
+			reg = <0x4847c000 0x2000>,
+			      <0x48454000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
 		crossbar_mpu: crossbar@4a002a48 {
 			compatible = "ti,irq-crossbar";
 			reg = <0x4a002a48 0x130>;
-- 
2.7.1

[PATCH 11/11] ARM: DTS: dra7: Add nodes for McASP1/2/4/5/6/7/8

[Peter Ujfalusi]

Add nodes to represent all McASP ports in the dra7 family.
For system consistency use the eDMA for audio operations. sDMA would be
fine for 4/5/6/7/8 since their DAT port is not through L3 interconnect.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 112 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 112 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 258e6712a76b..700382093922 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1464,6 +1464,38 @@
 			status = "disabled";
 		};
 
+		mcasp1: mcasp@48460000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp1";
+			reg = <0x48460000 0x2000>,
+			      <0x45800000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp2: mcasp@48464000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp2";
+			reg = <0x48464000 0x2000>,
+			      <0x45c00000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
 		mcasp3: mcasp@48468000 {
 			compatible = "ti,dra7-mcasp-audio";
 			ti,hwmods = "mcasp3";
@@ -1480,6 +1512,86 @@
 			status = "disabled";
 		};
 
+		mcasp4: mcasp@4846c000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp4";
+			reg = <0x4846c000 0x2000>,
+			      <0x48436000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp5: mcasp@48470000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp5";
+			reg = <0x48470000 0x2000>,
+			      <0x4843a000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp6: mcasp@48474000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp6";
+			reg = <0x48474000 0x2000>,
+			      <0x4844c000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp7: mcasp@48478000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp7";
+			reg = <0x48478000 0x2000>,
+			      <0x48450000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp8: mcasp@4847c000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp8";
+			reg = <0x4847c000 0x2000>,
+			      <0x48454000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
 		crossbar_mpu: crossbar@4a002a48 {
 			compatible = "ti,irq-crossbar";
 			reg = <0x4a002a48 0x130>;
-- 
2.7.1

[PATCH 11/11] ARM: DTS: dra7: Add nodes for McASP1/2/4/5/6/7/8

[Peter Ujfalusi]

Add nodes to represent all McASP ports in the dra7 family.
For system consistency use the eDMA for audio operations. sDMA would be
fine for 4/5/6/7/8 since their DAT port is not through L3 interconnect.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 112 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 112 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 258e6712a76b..700382093922 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1464,6 +1464,38 @@
 			status = "disabled";
 		};
 
+		mcasp1: mcasp at 48460000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp1";
+			reg = <0x48460000 0x2000>,
+			      <0x45800000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp2: mcasp at 48464000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp2";
+			reg = <0x48464000 0x2000>,
+			      <0x45c00000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
 		mcasp3: mcasp at 48468000 {
 			compatible = "ti,dra7-mcasp-audio";
 			ti,hwmods = "mcasp3";
@@ -1480,6 +1512,86 @@
 			status = "disabled";
 		};
 
+		mcasp4: mcasp at 4846c000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp4";
+			reg = <0x4846c000 0x2000>,
+			      <0x48436000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp5: mcasp at 48470000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp5";
+			reg = <0x48470000 0x2000>,
+			      <0x4843a000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp6: mcasp at 48474000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp6";
+			reg = <0x48474000 0x2000>,
+			      <0x4844c000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp7: mcasp at 48478000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp7";
+			reg = <0x48478000 0x2000>,
+			      <0x48450000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp8: mcasp at 4847c000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp8";
+			reg = <0x4847c000 0x2000>,
+			      <0x48454000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
 		crossbar_mpu: crossbar at 4a002a48 {
 			compatible = "ti,irq-crossbar";
 			reg = <0x4a002a48 0x130>;
-- 
2.7.1

Re: [PATCH 02/11] ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1

[Paul Walmsley]

On Thu, 25 Feb 2016, Peter Ujfalusi wrote:

> Add hwmod data for the eDMA blocks:
>  - TPCC: Third-party channel controller
>  - TPTC0: Third-party transfer controller 0
>  - TPTC1: Third-party transfer controller 1
> 
> The TPCC is following it's clock and power domain. This means that
> the hwmod can not control it's status.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>

Thanks, queued.


- Paul

Re: [PATCH 02/11] ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1

[Paul Walmsley]

On Thu, 25 Feb 2016, Peter Ujfalusi wrote:

> Add hwmod data for the eDMA blocks:
>  - TPCC: Third-party channel controller
>  - TPTC0: Third-party transfer controller 0
>  - TPTC1: Third-party transfer controller 1
> 
> The TPCC is following it's clock and power domain. This means that
> the hwmod can not control it's status.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi-l0cyMroinI0@public.gmane.org>

Thanks, queued.


- Paul
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[PATCH 02/11] ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1

[Paul Walmsley]

On Thu, 25 Feb 2016, Peter Ujfalusi wrote:

> Add hwmod data for the eDMA blocks:
>  - TPCC: Third-party channel controller
>  - TPTC0: Third-party transfer controller 0
>  - TPTC1: Third-party transfer controller 1
> 
> The TPCC is following it's clock and power domain. This means that
> the hwmod can not control it's status.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>

Thanks, queued.


- Paul

Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Paul Walmsley]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 9854 bytes --]

Hi Péter

A few questions:

On Thu, 25 Feb 2016, Peter Ujfalusi wrote:

> Add missing data for all McASP ports for the dra7 family
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>

1. The patch doesn't set the HWMOD_OPT_CLKS_NEEDED flag for McASP1 and 2, 
but does set it for McASP4-8.  Could you please confirm that this is 
intentional, and if so, why?

2. The patch sets HWMOD_SWSUP_SIDLE for McASP1 and 2, but doesn't set it 
for McASP4-8.  Could you please confirm that this is intentional, and if 
so, why?  The descriptions of the MODULEMODE fields in SPRUHZ6 look 
identical.

3. Can McASP1,2,3 bus-master onto the L3?  If so, then there should be 
"dra7xx_mcasp1__l3_main_1"-style links to indicate this.


- Paul

> ---
>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 235 ++++++++++++++++++++++++++++++
>  1 file changed, 235 insertions(+)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 3953ad031c43..3bd067afa702 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1374,6 +1374,50 @@ static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
>  	.sysc	= &dra7xx_mcasp_sysc,
>  };
>  
> +/* mcasp1 */
> +static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
> +	{ .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
> +};
> +
> +static struct omap_hwmod dra7xx_mcasp1_hwmod = {
> +	.name		= "mcasp1",
> +	.class		= &dra7xx_mcasp_hwmod_class,
> +	.clkdm_name	= "ipu_clkdm",
> +	.main_clk	= "mcasp1_aux_gfclk_mux",
> +	.flags		= HWMOD_SWSUP_SIDLE,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +	.opt_clks	= mcasp1_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp1_opt_clks),
> +};
> +
> +/* mcasp2 */
> +static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
> +	{ .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
> +};
> +
> +static struct omap_hwmod dra7xx_mcasp2_hwmod = {
> +	.name		= "mcasp2",
> +	.class		= &dra7xx_mcasp_hwmod_class,
> +	.clkdm_name	= "l4per2_clkdm",
> +	.main_clk	= "mcasp2_aux_gfclk_mux",
> +	.flags		= HWMOD_SWSUP_SIDLE,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +	.opt_clks	= mcasp2_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp2_opt_clks),
> +};
> +
>  /* mcasp3 */
>  static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
>  	{ .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
> @@ -1396,6 +1440,116 @@ static struct omap_hwmod dra7xx_mcasp3_hwmod = {
>  	.opt_clks_cnt	= ARRAY_SIZE(mcasp3_opt_clks),
>  };
>  
> +/* mcasp4 */
> +static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
> +	{ .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
> +};
> +
> +static struct omap_hwmod dra7xx_mcasp4_hwmod = {
> +	.name		= "mcasp4",
> +	.class		= &dra7xx_mcasp_hwmod_class,
> +	.clkdm_name	= "l4per2_clkdm",
> +	.main_clk	= "mcasp4_aux_gfclk_mux",
> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +	.opt_clks	= mcasp4_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp4_opt_clks),
> +};
> +
> +/* mcasp5 */
> +static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
> +	{ .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
> +};
> +
> +static struct omap_hwmod dra7xx_mcasp5_hwmod = {
> +	.name		= "mcasp5",
> +	.class		= &dra7xx_mcasp_hwmod_class,
> +	.clkdm_name	= "l4per2_clkdm",
> +	.main_clk	= "mcasp5_aux_gfclk_mux",
> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +	.opt_clks	= mcasp5_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp5_opt_clks),
> +};
> +
> +/* mcasp6 */
> +static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
> +	{ .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
> +};
> +
> +static struct omap_hwmod dra7xx_mcasp6_hwmod = {
> +	.name		= "mcasp6",
> +	.class		= &dra7xx_mcasp_hwmod_class,
> +	.clkdm_name	= "l4per2_clkdm",
> +	.main_clk	= "mcasp6_aux_gfclk_mux",
> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +	.opt_clks	= mcasp6_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp6_opt_clks),
> +};
> +
> +/* mcasp7 */
> +static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
> +	{ .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
> +};
> +
> +static struct omap_hwmod dra7xx_mcasp7_hwmod = {
> +	.name		= "mcasp7",
> +	.class		= &dra7xx_mcasp_hwmod_class,
> +	.clkdm_name	= "l4per2_clkdm",
> +	.main_clk	= "mcasp7_aux_gfclk_mux",
> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +	.opt_clks	= mcasp7_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp7_opt_clks),
> +};
> +
> +/* mcasp8 */
> +static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
> +	{ .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
> +};
> +
> +static struct omap_hwmod dra7xx_mcasp8_hwmod = {
> +	.name		= "mcasp8",
> +	.class		= &dra7xx_mcasp_hwmod_class,
> +	.clkdm_name	= "l4per2_clkdm",
> +	.main_clk	= "mcasp8_aux_gfclk_mux",
> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +	.opt_clks	= mcasp8_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp8_opt_clks),
> +};
> +
>  /*
>   * 'mmc' class
>   *
> @@ -2703,6 +2857,38 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
>  	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>  };
>  
> +/* l4_per2 -> mcasp1 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
> +	.master		= &dra7xx_l4_per2_hwmod,
> +	.slave		= &dra7xx_mcasp1_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3_main_1 -> mcasp1 */
> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
> +	.master		= &dra7xx_l3_main_1_hwmod,
> +	.slave		= &dra7xx_mcasp1_hwmod,
> +	.clk		= "l3_iclk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_per2 -> mcasp2 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
> +	.master		= &dra7xx_l4_per2_hwmod,
> +	.slave		= &dra7xx_mcasp2_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3_main_1 -> mcasp2 */
> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
> +	.master		= &dra7xx_l3_main_1_hwmod,
> +	.slave		= &dra7xx_mcasp2_hwmod,
> +	.clk		= "l3_iclk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
>  /* l4_per2 -> mcasp3 */
>  static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
>  	.master		= &dra7xx_l4_per2_hwmod,
> @@ -2719,6 +2905,46 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
>  	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>  };
>  
> +/* l4_per2 -> mcasp4 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
> +	.master		= &dra7xx_l4_per2_hwmod,
> +	.slave		= &dra7xx_mcasp4_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_per2 -> mcasp5 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
> +	.master		= &dra7xx_l4_per2_hwmod,
> +	.slave		= &dra7xx_mcasp5_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_per2 -> mcasp6 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
> +	.master		= &dra7xx_l4_per2_hwmod,
> +	.slave		= &dra7xx_mcasp6_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_per2 -> mcasp7 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
> +	.master		= &dra7xx_l4_per2_hwmod,
> +	.slave		= &dra7xx_mcasp7_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_per2 -> mcasp8 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
> +	.master		= &dra7xx_l4_per2_hwmod,
> +	.slave		= &dra7xx_mcasp8_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
>  /* l4_per1 -> elm */
>  static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
>  	.master		= &dra7xx_l4_per1_hwmod,
> @@ -3461,8 +3687,17 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>  	&dra7xx_l4_wkup__dcan1,
>  	&dra7xx_l4_per2__dcan2,
>  	&dra7xx_l4_per2__cpgmac0,
> +	&dra7xx_l4_per2__mcasp1,
> +	&dra7xx_l3_main_1__mcasp1,
> +	&dra7xx_l4_per2__mcasp2,
> +	&dra7xx_l3_main_1__mcasp2,
>  	&dra7xx_l4_per2__mcasp3,
>  	&dra7xx_l3_main_1__mcasp3,
> +	&dra7xx_l4_per2__mcasp4,
> +	&dra7xx_l4_per2__mcasp5,
> +	&dra7xx_l4_per2__mcasp6,
> +	&dra7xx_l4_per2__mcasp7,
> +	&dra7xx_l4_per2__mcasp8,
>  	&dra7xx_gmac__mdio,
>  	&dra7xx_l4_cfg__dma_system,
>  	&dra7xx_l3_main_1__tpcc,
> -- 
> 2.7.1
> 


- Paul

[PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Paul Walmsley]

Hi P?ter

A few questions:

On Thu, 25 Feb 2016, Peter Ujfalusi wrote:

> Add missing data for all McASP ports for the dra7 family
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>

1. The patch doesn't set the HWMOD_OPT_CLKS_NEEDED flag for McASP1 and 2, 
but does set it for McASP4-8.  Could you please confirm that this is 
intentional, and if so, why?

2. The patch sets HWMOD_SWSUP_SIDLE for McASP1 and 2, but doesn't set it 
for McASP4-8.  Could you please confirm that this is intentional, and if 
so, why?  The descriptions of the MODULEMODE fields in SPRUHZ6 look 
identical.

3. Can McASP1,2,3 bus-master onto the L3?  If so, then there should be 
"dra7xx_mcasp1__l3_main_1"-style links to indicate this.


- Paul

> ---
>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 235 ++++++++++++++++++++++++++++++
>  1 file changed, 235 insertions(+)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 3953ad031c43..3bd067afa702 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1374,6 +1374,50 @@ static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
>  	.sysc	= &dra7xx_mcasp_sysc,
>  };
>  
> +/* mcasp1 */
> +static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
> +	{ .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
> +};
> +
> +static struct omap_hwmod dra7xx_mcasp1_hwmod = {
> +	.name		= "mcasp1",
> +	.class		= &dra7xx_mcasp_hwmod_class,
> +	.clkdm_name	= "ipu_clkdm",
> +	.main_clk	= "mcasp1_aux_gfclk_mux",
> +	.flags		= HWMOD_SWSUP_SIDLE,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +	.opt_clks	= mcasp1_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp1_opt_clks),
> +};
> +
> +/* mcasp2 */
> +static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
> +	{ .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
> +};
> +
> +static struct omap_hwmod dra7xx_mcasp2_hwmod = {
> +	.name		= "mcasp2",
> +	.class		= &dra7xx_mcasp_hwmod_class,
> +	.clkdm_name	= "l4per2_clkdm",
> +	.main_clk	= "mcasp2_aux_gfclk_mux",
> +	.flags		= HWMOD_SWSUP_SIDLE,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +	.opt_clks	= mcasp2_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp2_opt_clks),
> +};
> +
>  /* mcasp3 */
>  static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
>  	{ .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
> @@ -1396,6 +1440,116 @@ static struct omap_hwmod dra7xx_mcasp3_hwmod = {
>  	.opt_clks_cnt	= ARRAY_SIZE(mcasp3_opt_clks),
>  };
>  
> +/* mcasp4 */
> +static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
> +	{ .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
> +};
> +
> +static struct omap_hwmod dra7xx_mcasp4_hwmod = {
> +	.name		= "mcasp4",
> +	.class		= &dra7xx_mcasp_hwmod_class,
> +	.clkdm_name	= "l4per2_clkdm",
> +	.main_clk	= "mcasp4_aux_gfclk_mux",
> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +	.opt_clks	= mcasp4_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp4_opt_clks),
> +};
> +
> +/* mcasp5 */
> +static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
> +	{ .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
> +};
> +
> +static struct omap_hwmod dra7xx_mcasp5_hwmod = {
> +	.name		= "mcasp5",
> +	.class		= &dra7xx_mcasp_hwmod_class,
> +	.clkdm_name	= "l4per2_clkdm",
> +	.main_clk	= "mcasp5_aux_gfclk_mux",
> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +	.opt_clks	= mcasp5_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp5_opt_clks),
> +};
> +
> +/* mcasp6 */
> +static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
> +	{ .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
> +};
> +
> +static struct omap_hwmod dra7xx_mcasp6_hwmod = {
> +	.name		= "mcasp6",
> +	.class		= &dra7xx_mcasp_hwmod_class,
> +	.clkdm_name	= "l4per2_clkdm",
> +	.main_clk	= "mcasp6_aux_gfclk_mux",
> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +	.opt_clks	= mcasp6_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp6_opt_clks),
> +};
> +
> +/* mcasp7 */
> +static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
> +	{ .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
> +};
> +
> +static struct omap_hwmod dra7xx_mcasp7_hwmod = {
> +	.name		= "mcasp7",
> +	.class		= &dra7xx_mcasp_hwmod_class,
> +	.clkdm_name	= "l4per2_clkdm",
> +	.main_clk	= "mcasp7_aux_gfclk_mux",
> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +	.opt_clks	= mcasp7_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp7_opt_clks),
> +};
> +
> +/* mcasp8 */
> +static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
> +	{ .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
> +};
> +
> +static struct omap_hwmod dra7xx_mcasp8_hwmod = {
> +	.name		= "mcasp8",
> +	.class		= &dra7xx_mcasp_hwmod_class,
> +	.clkdm_name	= "l4per2_clkdm",
> +	.main_clk	= "mcasp8_aux_gfclk_mux",
> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +	.opt_clks	= mcasp8_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp8_opt_clks),
> +};
> +
>  /*
>   * 'mmc' class
>   *
> @@ -2703,6 +2857,38 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
>  	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>  };
>  
> +/* l4_per2 -> mcasp1 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
> +	.master		= &dra7xx_l4_per2_hwmod,
> +	.slave		= &dra7xx_mcasp1_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3_main_1 -> mcasp1 */
> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
> +	.master		= &dra7xx_l3_main_1_hwmod,
> +	.slave		= &dra7xx_mcasp1_hwmod,
> +	.clk		= "l3_iclk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_per2 -> mcasp2 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
> +	.master		= &dra7xx_l4_per2_hwmod,
> +	.slave		= &dra7xx_mcasp2_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3_main_1 -> mcasp2 */
> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
> +	.master		= &dra7xx_l3_main_1_hwmod,
> +	.slave		= &dra7xx_mcasp2_hwmod,
> +	.clk		= "l3_iclk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
>  /* l4_per2 -> mcasp3 */
>  static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
>  	.master		= &dra7xx_l4_per2_hwmod,
> @@ -2719,6 +2905,46 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
>  	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>  };
>  
> +/* l4_per2 -> mcasp4 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
> +	.master		= &dra7xx_l4_per2_hwmod,
> +	.slave		= &dra7xx_mcasp4_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_per2 -> mcasp5 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
> +	.master		= &dra7xx_l4_per2_hwmod,
> +	.slave		= &dra7xx_mcasp5_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_per2 -> mcasp6 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
> +	.master		= &dra7xx_l4_per2_hwmod,
> +	.slave		= &dra7xx_mcasp6_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_per2 -> mcasp7 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
> +	.master		= &dra7xx_l4_per2_hwmod,
> +	.slave		= &dra7xx_mcasp7_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_per2 -> mcasp8 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
> +	.master		= &dra7xx_l4_per2_hwmod,
> +	.slave		= &dra7xx_mcasp8_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
>  /* l4_per1 -> elm */
>  static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
>  	.master		= &dra7xx_l4_per1_hwmod,
> @@ -3461,8 +3687,17 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>  	&dra7xx_l4_wkup__dcan1,
>  	&dra7xx_l4_per2__dcan2,
>  	&dra7xx_l4_per2__cpgmac0,
> +	&dra7xx_l4_per2__mcasp1,
> +	&dra7xx_l3_main_1__mcasp1,
> +	&dra7xx_l4_per2__mcasp2,
> +	&dra7xx_l3_main_1__mcasp2,
>  	&dra7xx_l4_per2__mcasp3,
>  	&dra7xx_l3_main_1__mcasp3,
> +	&dra7xx_l4_per2__mcasp4,
> +	&dra7xx_l4_per2__mcasp5,
> +	&dra7xx_l4_per2__mcasp6,
> +	&dra7xx_l4_per2__mcasp7,
> +	&dra7xx_l4_per2__mcasp8,
>  	&dra7xx_gmac__mdio,
>  	&dra7xx_l4_cfg__dma_system,
>  	&dra7xx_l3_main_1__tpcc,
> -- 
> 2.7.1
> 


- Paul

Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Peter Ujfalusi]

Hi Paul,

On 03/01/2016 11:11 AM, Paul Walmsley wrote:
> Hi Péter
> 
> A few questions:
> 
> On Thu, 25 Feb 2016, Peter Ujfalusi wrote:
> 
>> Add missing data for all McASP ports for the dra7 family
>>
>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> 
> 1. The patch doesn't set the HWMOD_OPT_CLKS_NEEDED flag for McASP1 and 2, 
> but does set it for McASP4-8.  Could you please confirm that this is 
> intentional, and if so, why?

All should have the HWMOD_OPT_CLKS_NEEDED as both fclk and ahclkx is treated
as functional clock and needs to be available in order to be able to access
McASP registers.
Sorry, I can only test McASP3 and somehow I overlooked this when copy-pasting
the data.

> 2. The patch sets HWMOD_SWSUP_SIDLE for McASP1 and 2, but doesn't set it 
> for McASP4-8.  Could you please confirm that this is intentional, and if 
> so, why?  The descriptions of the MODULEMODE fields in SPRUHZ6 look 
> identical.

I need to confirm this, but all McASP should have the same set of flags.

> 
> 3. Can McASP1,2,3 bus-master onto the L3?  If so, then there should be 
> "dra7xx_mcasp1__l3_main_1"-style links to indicate this.

I need to check this, but I don't think McASP1,2,3 can be bus-master onto L3.

> 
> 
> - Paul

I can resend the series next week as I'm out of office this week.

-- 
Péter

> 
>> ---
>>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 235 ++++++++++++++++++++++++++++++
>>  1 file changed, 235 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> index 3953ad031c43..3bd067afa702 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> @@ -1374,6 +1374,50 @@ static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
>>  	.sysc	= &dra7xx_mcasp_sysc,
>>  };
>>  
>> +/* mcasp1 */
>> +static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp1_hwmod = {
>> +	.name		= "mcasp1",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "ipu_clkdm",
>> +	.main_clk	= "mcasp1_aux_gfclk_mux",
>> +	.flags		= HWMOD_SWSUP_SIDLE,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp1_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp1_opt_clks),
>> +};
>> +
>> +/* mcasp2 */
>> +static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp2_hwmod = {
>> +	.name		= "mcasp2",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp2_aux_gfclk_mux",
>> +	.flags		= HWMOD_SWSUP_SIDLE,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp2_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp2_opt_clks),
>> +};
>> +
>>  /* mcasp3 */
>>  static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
>>  	{ .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
>> @@ -1396,6 +1440,116 @@ static struct omap_hwmod dra7xx_mcasp3_hwmod = {
>>  	.opt_clks_cnt	= ARRAY_SIZE(mcasp3_opt_clks),
>>  };
>>  
>> +/* mcasp4 */
>> +static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp4_hwmod = {
>> +	.name		= "mcasp4",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp4_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp4_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp4_opt_clks),
>> +};
>> +
>> +/* mcasp5 */
>> +static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp5_hwmod = {
>> +	.name		= "mcasp5",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp5_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp5_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp5_opt_clks),
>> +};
>> +
>> +/* mcasp6 */
>> +static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp6_hwmod = {
>> +	.name		= "mcasp6",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp6_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp6_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp6_opt_clks),
>> +};
>> +
>> +/* mcasp7 */
>> +static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp7_hwmod = {
>> +	.name		= "mcasp7",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp7_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp7_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp7_opt_clks),
>> +};
>> +
>> +/* mcasp8 */
>> +static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp8_hwmod = {
>> +	.name		= "mcasp8",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp8_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp8_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp8_opt_clks),
>> +};
>> +
>>  /*
>>   * 'mmc' class
>>   *
>> @@ -2703,6 +2857,38 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
>>  	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>>  };
>>  
>> +/* l4_per2 -> mcasp1 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp1_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l3_main_1 -> mcasp1 */
>> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
>> +	.master		= &dra7xx_l3_main_1_hwmod,
>> +	.slave		= &dra7xx_mcasp1_hwmod,
>> +	.clk		= "l3_iclk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp2 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp2_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l3_main_1 -> mcasp2 */
>> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
>> +	.master		= &dra7xx_l3_main_1_hwmod,
>> +	.slave		= &dra7xx_mcasp2_hwmod,
>> +	.clk		= "l3_iclk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>>  /* l4_per2 -> mcasp3 */
>>  static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
>>  	.master		= &dra7xx_l4_per2_hwmod,
>> @@ -2719,6 +2905,46 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
>>  	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>>  };
>>  
>> +/* l4_per2 -> mcasp4 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp4_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp5 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp5_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp6 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp6_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp7 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp7_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp8 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp8_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>>  /* l4_per1 -> elm */
>>  static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
>>  	.master		= &dra7xx_l4_per1_hwmod,
>> @@ -3461,8 +3687,17 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>>  	&dra7xx_l4_wkup__dcan1,
>>  	&dra7xx_l4_per2__dcan2,
>>  	&dra7xx_l4_per2__cpgmac0,
>> +	&dra7xx_l4_per2__mcasp1,
>> +	&dra7xx_l3_main_1__mcasp1,
>> +	&dra7xx_l4_per2__mcasp2,
>> +	&dra7xx_l3_main_1__mcasp2,
>>  	&dra7xx_l4_per2__mcasp3,
>>  	&dra7xx_l3_main_1__mcasp3,
>> +	&dra7xx_l4_per2__mcasp4,
>> +	&dra7xx_l4_per2__mcasp5,
>> +	&dra7xx_l4_per2__mcasp6,
>> +	&dra7xx_l4_per2__mcasp7,
>> +	&dra7xx_l4_per2__mcasp8,
>>  	&dra7xx_gmac__mdio,
>>  	&dra7xx_l4_cfg__dma_system,
>>  	&dra7xx_l3_main_1__tpcc,
>> -- 
>> 2.7.1
>>
> 
> 
> - Paul
> 

Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Peter Ujfalusi]

Hi Paul,

On 03/01/2016 11:11 AM, Paul Walmsley wrote:
> Hi Péter
> 
> A few questions:
> 
> On Thu, 25 Feb 2016, Peter Ujfalusi wrote:
> 
>> Add missing data for all McASP ports for the dra7 family
>>
>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> 
> 1. The patch doesn't set the HWMOD_OPT_CLKS_NEEDED flag for McASP1 and 2, 
> but does set it for McASP4-8.  Could you please confirm that this is 
> intentional, and if so, why?

All should have the HWMOD_OPT_CLKS_NEEDED as both fclk and ahclkx is treated
as functional clock and needs to be available in order to be able to access
McASP registers.
Sorry, I can only test McASP3 and somehow I overlooked this when copy-pasting
the data.

> 2. The patch sets HWMOD_SWSUP_SIDLE for McASP1 and 2, but doesn't set it 
> for McASP4-8.  Could you please confirm that this is intentional, and if 
> so, why?  The descriptions of the MODULEMODE fields in SPRUHZ6 look 
> identical.

I need to confirm this, but all McASP should have the same set of flags.

> 
> 3. Can McASP1,2,3 bus-master onto the L3?  If so, then there should be 
> "dra7xx_mcasp1__l3_main_1"-style links to indicate this.

I need to check this, but I don't think McASP1,2,3 can be bus-master onto L3.

> 
> 
> - Paul

I can resend the series next week as I'm out of office this week.

-- 
Péter

> 
>> ---
>>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 235 ++++++++++++++++++++++++++++++
>>  1 file changed, 235 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> index 3953ad031c43..3bd067afa702 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> @@ -1374,6 +1374,50 @@ static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
>>  	.sysc	= &dra7xx_mcasp_sysc,
>>  };
>>  
>> +/* mcasp1 */
>> +static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp1_hwmod = {
>> +	.name		= "mcasp1",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "ipu_clkdm",
>> +	.main_clk	= "mcasp1_aux_gfclk_mux",
>> +	.flags		= HWMOD_SWSUP_SIDLE,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp1_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp1_opt_clks),
>> +};
>> +
>> +/* mcasp2 */
>> +static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp2_hwmod = {
>> +	.name		= "mcasp2",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp2_aux_gfclk_mux",
>> +	.flags		= HWMOD_SWSUP_SIDLE,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp2_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp2_opt_clks),
>> +};
>> +
>>  /* mcasp3 */
>>  static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
>>  	{ .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
>> @@ -1396,6 +1440,116 @@ static struct omap_hwmod dra7xx_mcasp3_hwmod = {
>>  	.opt_clks_cnt	= ARRAY_SIZE(mcasp3_opt_clks),
>>  };
>>  
>> +/* mcasp4 */
>> +static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp4_hwmod = {
>> +	.name		= "mcasp4",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp4_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp4_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp4_opt_clks),
>> +};
>> +
>> +/* mcasp5 */
>> +static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp5_hwmod = {
>> +	.name		= "mcasp5",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp5_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp5_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp5_opt_clks),
>> +};
>> +
>> +/* mcasp6 */
>> +static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp6_hwmod = {
>> +	.name		= "mcasp6",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp6_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp6_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp6_opt_clks),
>> +};
>> +
>> +/* mcasp7 */
>> +static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp7_hwmod = {
>> +	.name		= "mcasp7",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp7_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp7_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp7_opt_clks),
>> +};
>> +
>> +/* mcasp8 */
>> +static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp8_hwmod = {
>> +	.name		= "mcasp8",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp8_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp8_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp8_opt_clks),
>> +};
>> +
>>  /*
>>   * 'mmc' class
>>   *
>> @@ -2703,6 +2857,38 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
>>  	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>>  };
>>  
>> +/* l4_per2 -> mcasp1 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp1_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l3_main_1 -> mcasp1 */
>> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
>> +	.master		= &dra7xx_l3_main_1_hwmod,
>> +	.slave		= &dra7xx_mcasp1_hwmod,
>> +	.clk		= "l3_iclk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp2 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp2_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l3_main_1 -> mcasp2 */
>> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
>> +	.master		= &dra7xx_l3_main_1_hwmod,
>> +	.slave		= &dra7xx_mcasp2_hwmod,
>> +	.clk		= "l3_iclk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>>  /* l4_per2 -> mcasp3 */
>>  static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
>>  	.master		= &dra7xx_l4_per2_hwmod,
>> @@ -2719,6 +2905,46 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
>>  	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>>  };
>>  
>> +/* l4_per2 -> mcasp4 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp4_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp5 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp5_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp6 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp6_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp7 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp7_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp8 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp8_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>>  /* l4_per1 -> elm */
>>  static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
>>  	.master		= &dra7xx_l4_per1_hwmod,
>> @@ -3461,8 +3687,17 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>>  	&dra7xx_l4_wkup__dcan1,
>>  	&dra7xx_l4_per2__dcan2,
>>  	&dra7xx_l4_per2__cpgmac0,
>> +	&dra7xx_l4_per2__mcasp1,
>> +	&dra7xx_l3_main_1__mcasp1,
>> +	&dra7xx_l4_per2__mcasp2,
>> +	&dra7xx_l3_main_1__mcasp2,
>>  	&dra7xx_l4_per2__mcasp3,
>>  	&dra7xx_l3_main_1__mcasp3,
>> +	&dra7xx_l4_per2__mcasp4,
>> +	&dra7xx_l4_per2__mcasp5,
>> +	&dra7xx_l4_per2__mcasp6,
>> +	&dra7xx_l4_per2__mcasp7,
>> +	&dra7xx_l4_per2__mcasp8,
>>  	&dra7xx_gmac__mdio,
>>  	&dra7xx_l4_cfg__dma_system,
>>  	&dra7xx_l3_main_1__tpcc,
>> -- 
>> 2.7.1
>>
> 
> 
> - Paul
> 

[PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Peter Ujfalusi]

Hi Paul,

On 03/01/2016 11:11 AM, Paul Walmsley wrote:
> Hi P?ter
> 
> A few questions:
> 
> On Thu, 25 Feb 2016, Peter Ujfalusi wrote:
> 
>> Add missing data for all McASP ports for the dra7 family
>>
>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> 
> 1. The patch doesn't set the HWMOD_OPT_CLKS_NEEDED flag for McASP1 and 2, 
> but does set it for McASP4-8.  Could you please confirm that this is 
> intentional, and if so, why?

All should have the HWMOD_OPT_CLKS_NEEDED as both fclk and ahclkx is treated
as functional clock and needs to be available in order to be able to access
McASP registers.
Sorry, I can only test McASP3 and somehow I overlooked this when copy-pasting
the data.

> 2. The patch sets HWMOD_SWSUP_SIDLE for McASP1 and 2, but doesn't set it 
> for McASP4-8.  Could you please confirm that this is intentional, and if 
> so, why?  The descriptions of the MODULEMODE fields in SPRUHZ6 look 
> identical.

I need to confirm this, but all McASP should have the same set of flags.

> 
> 3. Can McASP1,2,3 bus-master onto the L3?  If so, then there should be 
> "dra7xx_mcasp1__l3_main_1"-style links to indicate this.

I need to check this, but I don't think McASP1,2,3 can be bus-master onto L3.

> 
> 
> - Paul

I can resend the series next week as I'm out of office this week.

-- 
P?ter

> 
>> ---
>>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 235 ++++++++++++++++++++++++++++++
>>  1 file changed, 235 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> index 3953ad031c43..3bd067afa702 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> @@ -1374,6 +1374,50 @@ static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
>>  	.sysc	= &dra7xx_mcasp_sysc,
>>  };
>>  
>> +/* mcasp1 */
>> +static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp1_hwmod = {
>> +	.name		= "mcasp1",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "ipu_clkdm",
>> +	.main_clk	= "mcasp1_aux_gfclk_mux",
>> +	.flags		= HWMOD_SWSUP_SIDLE,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp1_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp1_opt_clks),
>> +};
>> +
>> +/* mcasp2 */
>> +static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp2_hwmod = {
>> +	.name		= "mcasp2",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp2_aux_gfclk_mux",
>> +	.flags		= HWMOD_SWSUP_SIDLE,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp2_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp2_opt_clks),
>> +};
>> +
>>  /* mcasp3 */
>>  static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
>>  	{ .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
>> @@ -1396,6 +1440,116 @@ static struct omap_hwmod dra7xx_mcasp3_hwmod = {
>>  	.opt_clks_cnt	= ARRAY_SIZE(mcasp3_opt_clks),
>>  };
>>  
>> +/* mcasp4 */
>> +static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp4_hwmod = {
>> +	.name		= "mcasp4",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp4_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp4_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp4_opt_clks),
>> +};
>> +
>> +/* mcasp5 */
>> +static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp5_hwmod = {
>> +	.name		= "mcasp5",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp5_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp5_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp5_opt_clks),
>> +};
>> +
>> +/* mcasp6 */
>> +static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp6_hwmod = {
>> +	.name		= "mcasp6",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp6_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp6_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp6_opt_clks),
>> +};
>> +
>> +/* mcasp7 */
>> +static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp7_hwmod = {
>> +	.name		= "mcasp7",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp7_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp7_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp7_opt_clks),
>> +};
>> +
>> +/* mcasp8 */
>> +static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
>> +	{ .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
>> +};
>> +
>> +static struct omap_hwmod dra7xx_mcasp8_hwmod = {
>> +	.name		= "mcasp8",
>> +	.class		= &dra7xx_mcasp_hwmod_class,
>> +	.clkdm_name	= "l4per2_clkdm",
>> +	.main_clk	= "mcasp8_aux_gfclk_mux",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_SWCTRL,
>> +		},
>> +	},
>> +	.opt_clks	= mcasp8_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(mcasp8_opt_clks),
>> +};
>> +
>>  /*
>>   * 'mmc' class
>>   *
>> @@ -2703,6 +2857,38 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
>>  	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>>  };
>>  
>> +/* l4_per2 -> mcasp1 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp1_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l3_main_1 -> mcasp1 */
>> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
>> +	.master		= &dra7xx_l3_main_1_hwmod,
>> +	.slave		= &dra7xx_mcasp1_hwmod,
>> +	.clk		= "l3_iclk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp2 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp2_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l3_main_1 -> mcasp2 */
>> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
>> +	.master		= &dra7xx_l3_main_1_hwmod,
>> +	.slave		= &dra7xx_mcasp2_hwmod,
>> +	.clk		= "l3_iclk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>>  /* l4_per2 -> mcasp3 */
>>  static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
>>  	.master		= &dra7xx_l4_per2_hwmod,
>> @@ -2719,6 +2905,46 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
>>  	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>>  };
>>  
>> +/* l4_per2 -> mcasp4 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp4_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp5 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp5_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp6 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp6_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp7 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp7_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_per2 -> mcasp8 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
>> +	.master		= &dra7xx_l4_per2_hwmod,
>> +	.slave		= &dra7xx_mcasp8_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>>  /* l4_per1 -> elm */
>>  static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
>>  	.master		= &dra7xx_l4_per1_hwmod,
>> @@ -3461,8 +3687,17 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>>  	&dra7xx_l4_wkup__dcan1,
>>  	&dra7xx_l4_per2__dcan2,
>>  	&dra7xx_l4_per2__cpgmac0,
>> +	&dra7xx_l4_per2__mcasp1,
>> +	&dra7xx_l3_main_1__mcasp1,
>> +	&dra7xx_l4_per2__mcasp2,
>> +	&dra7xx_l3_main_1__mcasp2,
>>  	&dra7xx_l4_per2__mcasp3,
>>  	&dra7xx_l3_main_1__mcasp3,
>> +	&dra7xx_l4_per2__mcasp4,
>> +	&dra7xx_l4_per2__mcasp5,
>> +	&dra7xx_l4_per2__mcasp6,
>> +	&dra7xx_l4_per2__mcasp7,
>> +	&dra7xx_l4_per2__mcasp8,
>>  	&dra7xx_gmac__mdio,
>>  	&dra7xx_l4_cfg__dma_system,
>>  	&dra7xx_l3_main_1__tpcc,
>> -- 
>> 2.7.1
>>
> 
> 
> - Paul
> 

Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Paul Walmsley]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 1838 bytes --]

Hi Péter,

On Tue, 1 Mar 2016, Peter Ujfalusi wrote:

> Hi Paul,
> 
> On 03/01/2016 11:11 AM, Paul Walmsley wrote:
> > Hi Péter
> > 
> > A few questions:
> > 
> > On Thu, 25 Feb 2016, Peter Ujfalusi wrote:
> > 
> >> Add missing data for all McASP ports for the dra7 family
> >>
> >> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> > 
> > 1. The patch doesn't set the HWMOD_OPT_CLKS_NEEDED flag for McASP1 and 2, 
> > but does set it for McASP4-8.  Could you please confirm that this is 
> > intentional, and if so, why?
> 
> All should have the HWMOD_OPT_CLKS_NEEDED as both fclk and ahclkx is treated
> as functional clock and needs to be available in order to be able to access
> McASP registers.
> Sorry, I can only test McASP3 and somehow I overlooked this when copy-pasting
> the data.

OK

> > 2. The patch sets HWMOD_SWSUP_SIDLE for McASP1 and 2, but doesn't set it 
> > for McASP4-8.  Could you please confirm that this is intentional, and if 
> > so, why?  The descriptions of the MODULEMODE fields in SPRUHZ6 look 
> > identical.
> 
> I need to confirm this, but all McASP should have the same set of flags.

OK.  Looking at McASP3 data this morning, they probably shouldn't need 
HWMOD_SWSUP_SIDLE, but probably all need 

                        .modulemode   = MODULEMODE_SWCTRL,

> > 3. Can McASP1,2,3 bus-master onto the L3?  If so, then there should be 
> > "dra7xx_mcasp1__l3_main_1"-style links to indicate this.
> 
> I need to check this, but I don't think McASP1,2,3 can be bus-master onto L3.

OK.  When you get back, maybe doublecheck this - it looks to me from 
SPRUHZ6 that McASP1-3 have built-in DMA controllers.

> I can resend the series next week as I'm out of office this week.

That's fine.  It's most likely v4.7 material at this point.


- Paul

[PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Paul Walmsley]

Hi P?ter,

On Tue, 1 Mar 2016, Peter Ujfalusi wrote:

> Hi Paul,
> 
> On 03/01/2016 11:11 AM, Paul Walmsley wrote:
> > Hi P?ter
> > 
> > A few questions:
> > 
> > On Thu, 25 Feb 2016, Peter Ujfalusi wrote:
> > 
> >> Add missing data for all McASP ports for the dra7 family
> >>
> >> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> > 
> > 1. The patch doesn't set the HWMOD_OPT_CLKS_NEEDED flag for McASP1 and 2, 
> > but does set it for McASP4-8.  Could you please confirm that this is 
> > intentional, and if so, why?
> 
> All should have the HWMOD_OPT_CLKS_NEEDED as both fclk and ahclkx is treated
> as functional clock and needs to be available in order to be able to access
> McASP registers.
> Sorry, I can only test McASP3 and somehow I overlooked this when copy-pasting
> the data.

OK

> > 2. The patch sets HWMOD_SWSUP_SIDLE for McASP1 and 2, but doesn't set it 
> > for McASP4-8.  Could you please confirm that this is intentional, and if 
> > so, why?  The descriptions of the MODULEMODE fields in SPRUHZ6 look 
> > identical.
> 
> I need to confirm this, but all McASP should have the same set of flags.

OK.  Looking at McASP3 data this morning, they probably shouldn't need 
HWMOD_SWSUP_SIDLE, but probably all need 

                        .modulemode   = MODULEMODE_SWCTRL,

> > 3. Can McASP1,2,3 bus-master onto the L3?  If so, then there should be 
> > "dra7xx_mcasp1__l3_main_1"-style links to indicate this.
> 
> I need to check this, but I don't think McASP1,2,3 can be bus-master onto L3.

OK.  When you get back, maybe doublecheck this - it looks to me from 
SPRUHZ6 that McASP1-3 have built-in DMA controllers.

> I can resend the series next week as I'm out of office this week.

That's fine.  It's most likely v4.7 material at this point.


- Paul

Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Peter Ujfalusi]

Hi Paul,

On 03/01/2016 07:01 PM, Paul Walmsley wrote:
>>> 2. The patch sets HWMOD_SWSUP_SIDLE for McASP1 and 2, but doesn't set it 
>>> for McASP4-8.  Could you please confirm that this is intentional, and if 
>>> so, why?  The descriptions of the MODULEMODE fields in SPRUHZ6 look 
>>> identical.
>>
>> I need to confirm this, but all McASP should have the same set of flags.
> 
> OK.  Looking at McASP3 data this morning, they probably shouldn't need 
> HWMOD_SWSUP_SIDLE, but probably all need 
> 
>                         .modulemode   = MODULEMODE_SWCTRL,
> 
>>> 3. Can McASP1,2,3 bus-master onto the L3?  If so, then there should be 
>>> "dra7xx_mcasp1__l3_main_1"-style links to indicate this.
>>
>> I need to check this, but I don't think McASP1,2,3 can be bus-master onto L3.
> 
> OK.  When you get back, maybe doublecheck this - it looks to me from 
> SPRUHZ6 that McASP1-3 have built-in DMA controllers.

They are only targets on L3. Not sure about the built-in DMA controller

> 
>> I can resend the series next week as I'm out of office this week.
> 
> That's fine.  It's most likely v4.7 material at this point.
> 
> 
> - Paul
> 


-- 
Péter

Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Peter Ujfalusi]

Hi Paul,

On 03/01/2016 07:01 PM, Paul Walmsley wrote:
>>> 2. The patch sets HWMOD_SWSUP_SIDLE for McASP1 and 2, but doesn't set it 
>>> for McASP4-8.  Could you please confirm that this is intentional, and if 
>>> so, why?  The descriptions of the MODULEMODE fields in SPRUHZ6 look 
>>> identical.
>>
>> I need to confirm this, but all McASP should have the same set of flags.
> 
> OK.  Looking at McASP3 data this morning, they probably shouldn't need 
> HWMOD_SWSUP_SIDLE, but probably all need 
> 
>                         .modulemode   = MODULEMODE_SWCTRL,
> 
>>> 3. Can McASP1,2,3 bus-master onto the L3?  If so, then there should be 
>>> "dra7xx_mcasp1__l3_main_1"-style links to indicate this.
>>
>> I need to check this, but I don't think McASP1,2,3 can be bus-master onto L3.
> 
> OK.  When you get back, maybe doublecheck this - it looks to me from 
> SPRUHZ6 that McASP1-3 have built-in DMA controllers.

They are only targets on L3. Not sure about the built-in DMA controller

> 
>> I can resend the series next week as I'm out of office this week.
> 
> That's fine.  It's most likely v4.7 material at this point.
> 
> 
> - Paul
> 


-- 
Péter

[PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Peter Ujfalusi]

Hi Paul,

On 03/01/2016 07:01 PM, Paul Walmsley wrote:
>>> 2. The patch sets HWMOD_SWSUP_SIDLE for McASP1 and 2, but doesn't set it 
>>> for McASP4-8.  Could you please confirm that this is intentional, and if 
>>> so, why?  The descriptions of the MODULEMODE fields in SPRUHZ6 look 
>>> identical.
>>
>> I need to confirm this, but all McASP should have the same set of flags.
> 
> OK.  Looking at McASP3 data this morning, they probably shouldn't need 
> HWMOD_SWSUP_SIDLE, but probably all need 
> 
>                         .modulemode   = MODULEMODE_SWCTRL,
> 
>>> 3. Can McASP1,2,3 bus-master onto the L3?  If so, then there should be 
>>> "dra7xx_mcasp1__l3_main_1"-style links to indicate this.
>>
>> I need to check this, but I don't think McASP1,2,3 can be bus-master onto L3.
> 
> OK.  When you get back, maybe doublecheck this - it looks to me from 
> SPRUHZ6 that McASP1-3 have built-in DMA controllers.

They are only targets on L3. Not sure about the built-in DMA controller

> 
>> I can resend the series next week as I'm out of office this week.
> 
> That's fine.  It's most likely v4.7 material at this point.
> 
> 
> - Paul
> 


-- 
P?ter

Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Paul Walmsley]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 735 bytes --]

Hi Péter,

On Thu, 3 Mar 2016, Peter Ujfalusi wrote:

> On 03/01/2016 07:01 PM, Paul Walmsley wrote:
> >>> 3. Can McASP1,2,3 bus-master onto the L3?  If so, then there should be 
> >>> "dra7xx_mcasp1__l3_main_1"-style links to indicate this.
> >>
> >> I need to check this, but I don't think McASP1,2,3 can be bus-master onto L3.
> > 
> > OK.  When you get back, maybe doublecheck this - it looks to me from 
> > SPRUHZ6 that McASP1-3 have built-in DMA controllers.
> 
> They are only targets on L3. Not sure about the built-in DMA controller

OK thanks.  I took a closer look at SPRUHZ6E and I think I was mistaken 
about those blocks having DMA controllers.  So you can ignore this part
of my comments :-)

- Paul

Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Paul Walmsley]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 735 bytes --]

Hi Péter,

On Thu, 3 Mar 2016, Peter Ujfalusi wrote:

> On 03/01/2016 07:01 PM, Paul Walmsley wrote:
> >>> 3. Can McASP1,2,3 bus-master onto the L3?  If so, then there should be 
> >>> "dra7xx_mcasp1__l3_main_1"-style links to indicate this.
> >>
> >> I need to check this, but I don't think McASP1,2,3 can be bus-master onto L3.
> > 
> > OK.  When you get back, maybe doublecheck this - it looks to me from 
> > SPRUHZ6 that McASP1-3 have built-in DMA controllers.
> 
> They are only targets on L3. Not sure about the built-in DMA controller

OK thanks.  I took a closer look at SPRUHZ6E and I think I was mistaken 
about those blocks having DMA controllers.  So you can ignore this part
of my comments :-)

- Paul

[PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8

[Paul Walmsley]

Hi P?ter,

On Thu, 3 Mar 2016, Peter Ujfalusi wrote:

> On 03/01/2016 07:01 PM, Paul Walmsley wrote:
> >>> 3. Can McASP1,2,3 bus-master onto the L3?  If so, then there should be 
> >>> "dra7xx_mcasp1__l3_main_1"-style links to indicate this.
> >>
> >> I need to check this, but I don't think McASP1,2,3 can be bus-master onto L3.
> > 
> > OK.  When you get back, maybe doublecheck this - it looks to me from 
> > SPRUHZ6 that McASP1-3 have built-in DMA controllers.
> 
> They are only targets on L3. Not sure about the built-in DMA controller

OK thanks.  I took a closer look at SPRUHZ6E and I think I was mistaken 
about those blocks having DMA controllers.  So you can ignore this part
of my comments :-)

- Paul