* [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly
@ 2016-03-15 14:39 ville.syrjala
2016-03-15 14:39 ` [PATCH 01/16] drm/i915: Throw out BUGs from DPLL/PCH functions ville.syrjala
` (17 more replies)
0 siblings, 18 replies; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Here's a pile of pending VLV/CHV DSI and DPLL patches I had lying around.
Most of these have been posted before. Would be nice to finally get them
in.
I've tried to rebase things to account for BXT as well, but obviously
that part is not tested. I have tested this on a BYT FFRD8 which has
a DSI panel.
Apart from the VLV/CHV specific stuff, the main thing here is moving
the DSI PLL calculations to the .compute_config() phase. Another neat
thing is hooking up the panel fitter for DSI.
Ville Syrjälä (16):
drm/i915: Throw out BUGs from DPLL/PCH functions
drm/i915: Make {vlv,chv}_{disable,update}_pll() more similar
drm/i915: Implement WaPixelRepeatModeFixForC0:chv
drm/i915: Add a local pipe variable to vlv_enable_pll()
drm/i915: assert_panel_unlocked() in chv_enable_pll()
drm/i915: Remove the "three times for luck" trick from
vlv_enable_pll()
drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV
drm/i915: Don't read out port_clock on CHV when DPLL is disabled
drm/i915: Change lfsr_converts[] to u16
drm/i915: Power down the DSI PLL before reconfiguring it
drm/i915: Compute DSI PLL parameters during .compute_config()
drm/i915: Fix CHV DSI PLL refclk during state readout
drm/i915: Eliminate {vlv,bxt}_configure_dsi_pll()
drm/i915: Dump pfit PGM_RATIOS as hex
drm/i915: Hook up pfit for DSI
drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms
drivers/gpu/drm/i915/i915_drv.h | 7 +
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_display.c | 244 +++++++++++++++++++----------------
drivers/gpu/drm/i915/intel_dp.c | 5 +
drivers/gpu/drm/i915/intel_drv.h | 5 +
drivers/gpu/drm/i915/intel_dsi.c | 120 +++++++++++++----
drivers/gpu/drm/i915/intel_dsi.h | 14 +-
drivers/gpu/drm/i915/intel_dsi_pll.c | 155 +++++++++++-----------
8 files changed, 332 insertions(+), 222 deletions(-)
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 01/16] drm/i915: Throw out BUGs from DPLL/PCH functions
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
@ 2016-03-15 14:39 ` ville.syrjala
2016-03-16 9:02 ` Jani Nikula
2016-03-15 14:39 ` [PATCH 02/16] drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar ville.syrjala
` (16 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
These BUGs don't serve any purpose IMO. Throw them out.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ce55f0b683c6..22930f05457c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1661,9 +1661,6 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
assert_pipe_disabled(dev_priv, crtc->pipe);
- /* No really, not for ILK+ */
- BUG_ON(INTEL_INFO(dev)->gen >= 5);
-
/* PLL is protected by panel, make sure we can write it */
if (IS_MOBILE(dev) && !IS_I830(dev))
assert_panel_unlocked(dev_priv, crtc->pipe);
@@ -1839,9 +1836,6 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
i915_reg_t reg;
uint32_t val, pipeconf_val;
- /* PCH only available on ILK+ */
- BUG_ON(!HAS_PCH_SPLIT(dev));
-
/* Make sure PCH DPLL is enabled */
assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
@@ -1895,9 +1889,6 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
{
u32 val, pipeconf_val;
- /* PCH only available on ILK+ */
- BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
-
/* FDI must be feeding us bits for PCH ports */
assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 02/16] drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
2016-03-15 14:39 ` [PATCH 01/16] drm/i915: Throw out BUGs from DPLL/PCH functions ville.syrjala
@ 2016-03-15 14:39 ` ville.syrjala
2016-03-30 13:31 ` Jani Nikula
2016-03-15 14:39 ` [PATCH 03/16] drm/i915: Implement WaPixelRepeatModeFixForC0:chv ville.syrjala
` (15 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The VLV and CHV DPLL disable and update are almost identical in
how the DPLL/DPLL_MD registers need to be set up. But the code
looks more different than it really is. Try to bring them into
line.
v2: s/chv_update_pll/chv_compute_dpll/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 63 ++++++++++++++----------------------
1 file changed, 25 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 22930f05457c..414ed5007e60 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1759,16 +1759,13 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
/* Make sure the pipe isn't still relying on us */
assert_pipe_disabled(dev_priv, pipe);
- /*
- * Leave integrated clock source and reference clock enabled for pipe B.
- * The latter is needed for VGA hotplug / manual detection.
- */
- val = DPLL_VGA_MODE_DIS;
- if (pipe == PIPE_B)
- val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
+ val = DPLL_INTEGRATED_REF_CLK_VLV |
+ DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
+ if (pipe != PIPE_A)
+ val |= DPLL_INTEGRATED_CRI_CLK_VLV;
+
I915_WRITE(DPLL(pipe), val);
POSTING_READ(DPLL(pipe));
-
}
static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
@@ -1779,11 +1776,11 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
/* Make sure the pipe isn't still relying on us */
assert_pipe_disabled(dev_priv, pipe);
- /* Set PLL en = 0 */
val = DPLL_SSC_REF_CLK_CHV |
DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
if (pipe != PIPE_A)
val |= DPLL_INTEGRATED_CRI_CLK_VLV;
+
I915_WRITE(DPLL(pipe), val);
POSTING_READ(DPLL(pipe));
@@ -7240,24 +7237,27 @@ void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
static void vlv_compute_dpll(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
- u32 dpll, dpll_md;
+ pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
+ DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
+ DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
+ if (crtc->pipe != PIPE_A)
+ pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
- /*
- * Enable DPIO clock input. We should never disable the reference
- * clock for pipe B, since VGA hotplug / manual detection depends
- * on it.
- */
- dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
- DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
- /* We should never disable this, set it here for state tracking */
- if (crtc->pipe == PIPE_B)
- dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
- dpll |= DPLL_VCO_ENABLE;
- pipe_config->dpll_hw_state.dpll = dpll;
+ pipe_config->dpll_hw_state.dpll_md =
+ (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
+}
+
+static void chv_compute_dpll(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
+{
+ pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
+ DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
+ DPLL_VCO_ENABLE;
+ if (crtc->pipe != PIPE_A)
+ pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
- dpll_md = (pipe_config->pixel_multiplier - 1)
- << DPLL_MD_UDI_MULTIPLIER_SHIFT;
- pipe_config->dpll_hw_state.dpll_md = dpll_md;
+ pipe_config->dpll_hw_state.dpll_md =
+ (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
}
static void vlv_prepare_pll(struct intel_crtc *crtc,
@@ -7351,19 +7351,6 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
mutex_unlock(&dev_priv->sb_lock);
}
-static void chv_compute_dpll(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
-{
- pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
- DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
- DPLL_VCO_ENABLE;
- if (crtc->pipe != PIPE_A)
- pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
-
- pipe_config->dpll_hw_state.dpll_md =
- (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
-}
-
static void chv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config)
{
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 03/16] drm/i915: Implement WaPixelRepeatModeFixForC0:chv
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
2016-03-15 14:39 ` [PATCH 01/16] drm/i915: Throw out BUGs from DPLL/PCH functions ville.syrjala
2016-03-15 14:39 ` [PATCH 02/16] drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar ville.syrjala
@ 2016-03-15 14:39 ` ville.syrjala
2016-03-16 9:27 ` Jani Nikula
2016-03-15 14:39 ` [PATCH 04/16] drm/i915: Add a local pipe variable to vlv_enable_pll() ville.syrjala
` (14 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
DPLL_MD(PIPE_C) is AWOL on CHV. Instead of fixing it someone added
chicken bits to propagate the pixel multiplier from DPLL_MD(PIPE_B)
to either pipe B or C. So do that to make pixel repeat work on pipes
B and C. Pipe A is fine without any tricks.
Fortunately the pixel repeat propagation appears to be a oneshot
operation, so once the value has been written we can clear the
chicken bits. So it is still possible to drive pipe B and C with
different pixel multipliers simultaneosly.
Looks like DPLL_VGA_MODE_DIS must also be set in DPLL(PIPE_B)
for this to work. But since we keep that bit always set in all
DPLLs there's no problem.
This of course means we can't reliably read out the pixel multiplier
for pipes B and C. That would make the state checker unhappy, so I
added shadow copies of those registers in to dev_priv. The other
option would have been to skip pixel multiplier, dpll_md an dotclock
checks entirely on CHV, but that feels like a serious loss of cross
checking, so just pretending that we have working DPLL MD registers
seemed better. Obviously with the shadow copies we can't detect if
the pixel multiplier was properly configured, nor can we take over
its state from the BIOS, but hopefully people won't have displays
that would be limitd to such crappy modes.
There is one strange flicker still remaining. It's visible on
pipe C/HDMID when HDMIB is enabled while driven by pipe B.
It doesn't occur if pipe A drives HDMIB, nor is there any glitch
on pipe B/HDMIB when port C/HDMID starts up. I don't have a board
with HDMIC so not sure if it happens there too. So I'm not sure
if it's somehow tied in with this strange linkage between pipe B
and C. Sadly I was unable to find an enable sequence that would
avoid the glitch, but at least it's not fatal ie. the output
recovers afterwards.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++++++
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++++++++++----
3 files changed, 37 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 80b14f1ba302..31689e1b19e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1871,7 +1871,14 @@ struct drm_i915_private {
u32 fdi_rx_config;
+ /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
u32 chv_phy_control;
+ /*
+ * Shadows for CHV DPLL_MD regs to keep the state
+ * checker somewhat working in the presence hardware
+ * crappiness (can't read out DPLL_MD for pipes B & C).
+ */
+ u32 chv_dpll_md[I915_MAX_PIPES];
u32 suspend_count;
bool suspended_to_idle;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7dfc4007f3fa..f138588a88cd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4778,6 +4778,10 @@ enum skl_disp_power_wells {
#define CBR_PND_DEADLINE_DISABLE (1<<31)
#define CBR_PWM_CLOCK_MUX_SELECT (1<<30)
+#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
+#define CBR_DPLLBMD_PIPE_C (1<<29)
+#define CBR_DPLLBMD_PIPE_B (1<<18)
+
/* FIFO watermark sizes etc */
#define G4X_FIFO_LINE_SIZE 64
#define I915_FIFO_LINE_SIZE 64
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 414ed5007e60..18158b0324ed 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1635,9 +1635,27 @@ static void chv_enable_pll(struct intel_crtc *crtc,
if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
DRM_ERROR("PLL %d failed to lock\n", pipe);
- /* not sure when this should be written */
- I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
- POSTING_READ(DPLL_MD(pipe));
+ if (pipe != PIPE_A) {
+ /*
+ * WaPixelRepeatModeFixForC0:chv
+ *
+ * DPLLCMD is AWOL. Use chicken bits to propagate
+ * the value from DPLLBMD to either pipe B or C.
+ */
+ I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
+ I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
+ I915_WRITE(CBR4_VLV, 0);
+ dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
+
+ /*
+ * DPLLB VGA mode also seems to cause problems.
+ * We should always have it disabled.
+ */
+ WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
+ } else {
+ I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
+ POSTING_READ(DPLL_MD(pipe));
+ }
}
static int intel_num_dvo_pipes(struct drm_device *dev)
@@ -8096,7 +8114,11 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
i9xx_get_pfit_config(crtc, pipe_config);
if (INTEL_INFO(dev)->gen >= 4) {
- tmp = I915_READ(DPLL_MD(crtc->pipe));
+ /* No way to read it out on pipes B and C */
+ if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
+ tmp = dev_priv->chv_dpll_md[crtc->pipe];
+ else
+ tmp = I915_READ(DPLL_MD(crtc->pipe));
pipe_config->pixel_multiplier =
((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
>> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 04/16] drm/i915: Add a local pipe variable to vlv_enable_pll()
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (2 preceding siblings ...)
2016-03-15 14:39 ` [PATCH 03/16] drm/i915: Implement WaPixelRepeatModeFixForC0:chv ville.syrjala
@ 2016-03-15 14:39 ` ville.syrjala
2016-03-16 9:03 ` Jani Nikula
2016-03-15 14:39 ` [PATCH 05/16] drm/i915: assert_panel_unlocked() in chv_enable_pll() ville.syrjala
` (13 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Avoid redundant crtc->pipe lookups by giving vlv_enable_pll() a local
pipe variable. Also makes it look more like the corresponding CHV code.
While at is change the CHV code to enum pipe from int,
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 18158b0324ed..638ce97777de 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1572,24 +1572,25 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- i915_reg_t reg = DPLL(crtc->pipe);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t reg = DPLL(pipe);
u32 dpll = pipe_config->dpll_hw_state.dpll;
- assert_pipe_disabled(dev_priv, crtc->pipe);
+ assert_pipe_disabled(dev_priv, pipe);
/* PLL is protected by panel, make sure we can write it */
if (IS_MOBILE(dev_priv->dev))
- assert_panel_unlocked(dev_priv, crtc->pipe);
+ assert_panel_unlocked(dev_priv, pipe);
I915_WRITE(reg, dpll);
POSTING_READ(reg);
udelay(150);
if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
- DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
+ DRM_ERROR("DPLL %d failed to lock\n", pipe);
- I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
- POSTING_READ(DPLL_MD(crtc->pipe));
+ I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
+ POSTING_READ(DPLL_MD(pipe));
/* We do this three times for luck */
I915_WRITE(reg, dpll);
@@ -1608,11 +1609,11 @@ static void chv_enable_pll(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- int pipe = crtc->pipe;
+ enum pipe pipe = crtc->pipe;
enum dpio_channel port = vlv_pipe_to_channel(pipe);
u32 tmp;
- assert_pipe_disabled(dev_priv, crtc->pipe);
+ assert_pipe_disabled(dev_priv, pipe);
mutex_lock(&dev_priv->sb_lock);
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 05/16] drm/i915: assert_panel_unlocked() in chv_enable_pll()
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (3 preceding siblings ...)
2016-03-15 14:39 ` [PATCH 04/16] drm/i915: Add a local pipe variable to vlv_enable_pll() ville.syrjala
@ 2016-03-15 14:39 ` ville.syrjala
2016-03-16 9:04 ` Jani Nikula
2016-03-15 14:39 ` [PATCH 06/16] drm/i915: Remove the "three times for luck" trick from vlv_enable_pll() ville.syrjala
` (12 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Supposedly the power sequencer still locks out the DPLL registers on
CHV, so let's issue a warning if it's still locked when enabling the
DPLL.
Also drop the redundant IS_MOBILE() check for VLV when we check the same
thing.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 638ce97777de..d3332a33f8a7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1579,8 +1579,7 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
assert_pipe_disabled(dev_priv, pipe);
/* PLL is protected by panel, make sure we can write it */
- if (IS_MOBILE(dev_priv->dev))
- assert_panel_unlocked(dev_priv, pipe);
+ assert_panel_unlocked(dev_priv, pipe);
I915_WRITE(reg, dpll);
POSTING_READ(reg);
@@ -1615,6 +1614,9 @@ static void chv_enable_pll(struct intel_crtc *crtc,
assert_pipe_disabled(dev_priv, pipe);
+ /* PLL is protected by panel, make sure we can write it */
+ assert_panel_unlocked(dev_priv, pipe);
+
mutex_lock(&dev_priv->sb_lock);
/* Enable back the 10bit clock to display controller */
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 06/16] drm/i915: Remove the "three times for luck" trick from vlv_enable_pll()
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (4 preceding siblings ...)
2016-03-15 14:39 ` [PATCH 05/16] drm/i915: assert_panel_unlocked() in chv_enable_pll() ville.syrjala
@ 2016-03-15 14:39 ` ville.syrjala
2016-03-16 9:05 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 07/16] drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV ville.syrjala
` (11 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
VLV DPLL is somewhat sane and doesn't run on luck.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 11 -----------
1 file changed, 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d3332a33f8a7..c85b77c1188d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1590,17 +1590,6 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
POSTING_READ(DPLL_MD(pipe));
-
- /* We do this three times for luck */
- I915_WRITE(reg, dpll);
- POSTING_READ(reg);
- udelay(150); /* wait for warmup */
- I915_WRITE(reg, dpll);
- POSTING_READ(reg);
- udelay(150); /* wait for warmup */
- I915_WRITE(reg, dpll);
- POSTING_READ(reg);
- udelay(150); /* wait for warmup */
}
static void chv_enable_pll(struct intel_crtc *crtc,
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 07/16] drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (5 preceding siblings ...)
2016-03-15 14:39 ` [PATCH 06/16] drm/i915: Remove the "three times for luck" trick from vlv_enable_pll() ville.syrjala
@ 2016-03-15 14:40 ` ville.syrjala
2016-03-15 14:40 ` [PATCH 08/16] drm/i915: Don't read out port_clock on CHV when DPLL is disabled ville.syrjala
` (10 subsequent siblings)
17 siblings, 0 replies; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Set up DPLL and DPLL_MD even when driving DSI output on VLV/CHV. While
the DPLL isn't used to provide the clock we still need the refclock, and
it appears that the pixel repeat factor also has an effect on DSI
output. So set up eveyrhing in DPLL and DPLL_MD as we would do for
DP/HDMI/VGA, but don't actually enable the DPLL or configure the
dividers via DPIO.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 117 ++++++++++++++++++++++-------------
drivers/gpu/drm/i915/intel_dsi.c | 28 +++------
2 files changed, 80 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c85b77c1188d..98aae3914e9e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1567,45 +1567,47 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
}
+static void _vlv_enable_pll(struct intel_crtc *crtc,
+ const struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
+ POSTING_READ(DPLL(pipe));
+ udelay(150);
+
+ if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
+ DRM_ERROR("DPLL %d failed to lock\n", pipe);
+}
+
static void vlv_enable_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- i915_reg_t reg = DPLL(pipe);
- u32 dpll = pipe_config->dpll_hw_state.dpll;
assert_pipe_disabled(dev_priv, pipe);
/* PLL is protected by panel, make sure we can write it */
assert_panel_unlocked(dev_priv, pipe);
- I915_WRITE(reg, dpll);
- POSTING_READ(reg);
- udelay(150);
-
- if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
- DRM_ERROR("DPLL %d failed to lock\n", pipe);
+ if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
+ _vlv_enable_pll(crtc, pipe_config);
I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
POSTING_READ(DPLL_MD(pipe));
}
-static void chv_enable_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config)
+
+static void _chv_enable_pll(struct intel_crtc *crtc,
+ const struct intel_crtc_state *pipe_config)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
enum dpio_channel port = vlv_pipe_to_channel(pipe);
u32 tmp;
- assert_pipe_disabled(dev_priv, pipe);
-
- /* PLL is protected by panel, make sure we can write it */
- assert_panel_unlocked(dev_priv, pipe);
-
mutex_lock(&dev_priv->sb_lock);
/* Enable back the 10bit clock to display controller */
@@ -1626,6 +1628,21 @@ static void chv_enable_pll(struct intel_crtc *crtc,
/* Check PLL is locked */
if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
DRM_ERROR("PLL %d failed to lock\n", pipe);
+}
+
+static void chv_enable_pll(struct intel_crtc *crtc,
+ const struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ assert_pipe_disabled(dev_priv, pipe);
+
+ /* PLL is protected by panel, make sure we can write it */
+ assert_panel_unlocked(dev_priv, pipe);
+
+ if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
+ _chv_enable_pll(crtc, pipe_config);
if (pipe != PIPE_A) {
/*
@@ -6125,14 +6142,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
if (encoder->pre_pll_enable)
encoder->pre_pll_enable(encoder);
- if (!intel_crtc->config->has_dsi_encoder) {
- if (IS_CHERRYVIEW(dev)) {
- chv_prepare_pll(intel_crtc, intel_crtc->config);
- chv_enable_pll(intel_crtc, intel_crtc->config);
- } else {
- vlv_prepare_pll(intel_crtc, intel_crtc->config);
- vlv_enable_pll(intel_crtc, intel_crtc->config);
- }
+ if (IS_CHERRYVIEW(dev)) {
+ chv_prepare_pll(intel_crtc, intel_crtc->config);
+ chv_enable_pll(intel_crtc, intel_crtc->config);
+ } else {
+ vlv_prepare_pll(intel_crtc, intel_crtc->config);
+ vlv_enable_pll(intel_crtc, intel_crtc->config);
}
for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -6168,7 +6183,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
- int pipe = intel_crtc->pipe;
+ enum pipe pipe = intel_crtc->pipe;
if (WARN_ON(intel_crtc->active))
return;
@@ -7248,11 +7263,15 @@ static void vlv_compute_dpll(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
- DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
- DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
+ DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
if (crtc->pipe != PIPE_A)
pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
+ /* DPLL not used with DSI, but still need the rest set up */
+ if (!intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_DSI))
+ pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
+ DPLL_EXT_BUFFER_ENABLE_VLV;
+
pipe_config->dpll_hw_state.dpll_md =
(pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
}
@@ -7261,11 +7280,14 @@ static void chv_compute_dpll(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
- DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
- DPLL_VCO_ENABLE;
+ DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
if (crtc->pipe != PIPE_A)
pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
+ /* DPLL not used with DSI, but still need the rest set up */
+ if (!intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_DSI))
+ pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
+
pipe_config->dpll_hw_state.dpll_md =
(pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
}
@@ -7275,11 +7297,20 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- int pipe = crtc->pipe;
+ enum pipe pipe = crtc->pipe;
u32 mdiv;
u32 bestn, bestm1, bestm2, bestp1, bestp2;
u32 coreclk, reg_val;
+ /* Enable Refclk */
+ I915_WRITE(DPLL(pipe),
+ pipe_config->dpll_hw_state.dpll &
+ ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
+
+ /* No need to actually set up the DPLL with DSI */
+ if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
+ return;
+
mutex_lock(&dev_priv->sb_lock);
bestn = pipe_config->dpll.n;
@@ -7366,14 +7397,21 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- int pipe = crtc->pipe;
- i915_reg_t dpll_reg = DPLL(crtc->pipe);
+ enum pipe pipe = crtc->pipe;
enum dpio_channel port = vlv_pipe_to_channel(pipe);
u32 loopfilter, tribuf_calcntr;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
u32 dpio_val;
int vco;
+ /* Enable Refclk and SSC */
+ I915_WRITE(DPLL(pipe),
+ pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
+
+ /* No need to actually set up the DPLL with DSI */
+ if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
+ return;
+
bestn = pipe_config->dpll.n;
bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
bestm1 = pipe_config->dpll.m1;
@@ -7384,12 +7422,6 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
dpio_val = 0;
loopfilter = 0;
- /*
- * Enable Refclk and SSC
- */
- I915_WRITE(dpll_reg,
- pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
-
mutex_lock(&dev_priv->sb_lock);
/* p1 and p2 divider */
@@ -7851,9 +7883,6 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
memset(&crtc_state->dpll_hw_state, 0,
sizeof(crtc_state->dpll_hw_state));
- if (crtc_state->has_dsi_encoder)
- return 0;
-
for_each_connector_in_state(state, connector, connector_state, i) {
if (connector_state->crtc == &crtc->base)
num_connectors++;
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 01b8e9f4c272..4023b6bffa47 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -284,6 +284,12 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
/* DSI uses short packets for sync events, so clear mode flags for DSI */
adjusted_mode->flags = 0;
+ /*
+ * FIXME move the DSI PLL calc from vlv_enable_dsi_pll()
+ * to .compute_config().
+ */
+ pipe_config->clock_set = true;
+
return true;
}
@@ -471,8 +477,6 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
- struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
- enum pipe pipe = intel_crtc->pipe;
enum port port;
u32 tmp;
@@ -488,19 +492,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
msleep(intel_dsi->panel_on_delay);
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
- /*
- * Disable DPOunit clock gating, can stall pipe
- * and we need DPLL REFA always enabled
- */
- tmp = I915_READ(DPLL(pipe));
- tmp |= DPLL_REF_CLK_ENABLE_VLV;
- I915_WRITE(DPLL(pipe), tmp);
-
- /* update the hw state for DPLL */
- intel_crtc->config->dpll_hw_state.dpll =
- DPLL_INTEGRATED_REF_CLK_VLV |
- DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
-
+ /* Disable DPOunit clock gating, can stall pipe */
tmp = I915_READ(DSPCLK_GATE_D);
tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
I915_WRITE(DSPCLK_GATE_D, tmp);
@@ -717,12 +709,6 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
pipe_config->has_dsi_encoder = true;
- /*
- * DPLL_MD is not used in case of DSI, reading will get some default value
- * set dpll_md = 0
- */
- pipe_config->dpll_hw_state.dpll_md = 0;
-
pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp);
if (!pclk)
return;
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 08/16] drm/i915: Don't read out port_clock on CHV when DPLL is disabled
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (6 preceding siblings ...)
2016-03-15 14:40 ` [PATCH 07/16] drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV ville.syrjala
@ 2016-03-15 14:40 ` ville.syrjala
2016-03-16 9:06 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 09/16] drm/i915: Change lfsr_converts[] to u16 ville.syrjala
` (9 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Check whether the DPLL is even enabled before readoing out the dividers
and trying to derive port_clock on CHV. We already did this on VLV.
Also remove the comment "MIPI" comment from the VLV code since we call
this function whenever the pipe is enabled.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 98aae3914e9e..3e6b5fb140ad 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7969,8 +7969,8 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
u32 mdiv;
int refclk = 100000;
- /* In case of MIPI DPLL will not even be used */
- if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
+ /* In case of DSI, DPLL will not be used */
+ if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
return;
mutex_lock(&dev_priv->sb_lock);
@@ -8066,6 +8066,10 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
int refclk = 100000;
+ /* In case of DSI, DPLL will not be used */
+ if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
+ return;
+
mutex_lock(&dev_priv->sb_lock);
cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 09/16] drm/i915: Change lfsr_converts[] to u16
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (7 preceding siblings ...)
2016-03-15 14:40 ` [PATCH 08/16] drm/i915: Don't read out port_clock on CHV when DPLL is disabled ville.syrjala
@ 2016-03-15 14:40 ` ville.syrjala
2016-03-16 8:42 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 10/16] drm/i915: Power down the DSI PLL before reconfiguring it ville.syrjala
` (8 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
All the values in the DSI PLL LFSR seed table fit into 9bits, so change
the type to u16 from u32 to save a bit of space.
drivers/gpu/drm/i915/i915.ko:
-.rodata 90824
+.rodata 90760
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 2451c84949bd..916cc92c1400 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -56,7 +56,7 @@ struct dsi_mnp {
u32 dsi_pll_div;
};
-static const u32 lfsr_converts[] = {
+static const u16 lfsr_converts[] = {
426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 10/16] drm/i915: Power down the DSI PLL before reconfiguring it
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (8 preceding siblings ...)
2016-03-15 14:40 ` [PATCH 09/16] drm/i915: Change lfsr_converts[] to u16 ville.syrjala
@ 2016-03-15 14:40 ` ville.syrjala
2016-03-16 8:45 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 11/16] drm/i915: Compute DSI PLL parameters during .compute_config() ville.syrjala
` (7 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On VLV at least, the BIOS may leave the DSI PLL enabled in some wonky
state where it just refuses to lock. Simply disabling the PLL before
reconfiguring it is not enough to fix it, but power gating the PLL
prior to reconfiguring does work.
This happens on BYT FFRD8 when booting with HDMI connected so the DSI
display will not be lit up by the BIOS.
Also we can remove the code for BXT that disables the PLL before
enabling it again.
v2: s/vlv/intel/ since BXT made thing generic
v3: Remove the BXT disable PLL before enable trick
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++
drivers/gpu/drm/i915/intel_dsi_pll.c | 8 --------
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4023b6bffa47..787411e1c36f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -482,7 +482,13 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
+ /*
+ * The BIOS may leave the PLL in a wonky state where it doesn't
+ * lock. It needs to be fully powered down to fix it.
+ */
+ intel_disable_dsi_pll(encoder);
intel_enable_dsi_pll(encoder);
+
intel_dsi_prepare(encoder);
/* Panel Enable over CRC PMIC */
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 916cc92c1400..978cc2668a3d 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -474,14 +474,6 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
- val = I915_READ(BXT_DSI_PLL_ENABLE);
-
- if (val & BXT_DSI_PLL_DO_ENABLE) {
- WARN(1, "DSI PLL already enabled. Disabling it.\n");
- val &= ~BXT_DSI_PLL_DO_ENABLE;
- I915_WRITE(BXT_DSI_PLL_ENABLE, val);
- }
-
/* Configure PLL vales */
if (!bxt_configure_dsi_pll(encoder)) {
DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 11/16] drm/i915: Compute DSI PLL parameters during .compute_config()
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (9 preceding siblings ...)
2016-03-15 14:40 ` [PATCH 10/16] drm/i915: Power down the DSI PLL before reconfiguring it ville.syrjala
@ 2016-03-15 14:40 ` ville.syrjala
2016-03-16 8:56 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 12/16] drm/i915: Fix CHV DSI PLL refclk during state readout ville.syrjala
` (6 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Compute the DSI PLL parameters during .compute_config() rather than
.pre_pll_enable() so that we can fail gracefully if we can't find
suitable parameters.
In order to do that we need to store the DSI PLL parameters in
pipe_config.
v2: Handle BXT too
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 3 +
drivers/gpu/drm/i915/intel_drv.h | 5 ++
drivers/gpu/drm/i915/intel_dsi.c | 15 ++--
drivers/gpu/drm/i915/intel_dsi.h | 14 ++--
drivers/gpu/drm/i915/intel_dsi_pll.c | 155 +++++++++++++++++++----------------
5 files changed, 112 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3e6b5fb140ad..d0b7fc85bc3a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12757,6 +12757,9 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
+ PIPE_CONF_CHECK_X(dsi_pll.ctrl);
+ PIPE_CONF_CHECK_X(dsi_pll.div);
+
if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 02b3d22862a1..89229037436d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -495,6 +495,11 @@ struct intel_crtc_state {
/* Actual register state of the dpll, for shared dpll cross-checking. */
struct intel_dpll_hw_state dpll_hw_state;
+ /* DSI PLL registers */
+ struct {
+ u32 ctrl, div;
+ } dsi_pll;
+
int pipe_bpp;
struct intel_link_m_n dp_m_n;
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 787411e1c36f..1b4e83df4560 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -273,6 +273,7 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
struct intel_connector *intel_connector = intel_dsi->attached_connector;
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ int ret;
DRM_DEBUG_KMS("\n");
@@ -284,10 +285,10 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
/* DSI uses short packets for sync events, so clear mode flags for DSI */
adjusted_mode->flags = 0;
- /*
- * FIXME move the DSI PLL calc from vlv_enable_dsi_pll()
- * to .compute_config().
- */
+ ret = intel_compute_dsi_pll(encoder, pipe_config);
+ if (ret)
+ return false;
+
pipe_config->clock_set = true;
return true;
@@ -477,6 +478,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
enum port port;
u32 tmp;
@@ -487,7 +489,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
* lock. It needs to be fully powered down to fix it.
*/
intel_disable_dsi_pll(encoder);
- intel_enable_dsi_pll(encoder);
+ intel_enable_dsi_pll(encoder, crtc->config);
intel_dsi_prepare(encoder);
@@ -715,7 +717,8 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
pipe_config->has_dsi_encoder = true;
- pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp);
+ pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
+ pipe_config);
if (!pclk)
return;
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 92f39227b361..e94c07170bf6 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -126,11 +126,15 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
return container_of(encoder, struct intel_dsi, base.base);
}
-extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
-extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
-extern u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp);
-extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
- enum port port);
+int intel_compute_dsi_pll(struct intel_encoder *encoder,
+ struct intel_crtc_state *config);
+void intel_enable_dsi_pll(struct intel_encoder *encoder,
+ const struct intel_crtc_state *config);
+void intel_disable_dsi_pll(struct intel_encoder *encoder);
+u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
+ struct intel_crtc_state *config);
+void intel_dsi_reset_clocks(struct intel_encoder *encoder,
+ enum port port);
struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 978cc2668a3d..d35c8dc28fb6 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -51,10 +51,6 @@ int dsi_pixel_format_bpp(int pixel_format)
return bpp;
}
-struct dsi_mnp {
- u32 dsi_pll_ctrl;
- u32 dsi_pll_div;
-};
static const u16 lfsr_converts[] = {
426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
@@ -77,7 +73,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
}
static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
- struct dsi_mnp *dsi_mnp, int target_dsi_clk)
+ struct intel_crtc_state *config,
+ int target_dsi_clk)
{
unsigned int calc_m = 0, calc_p = 0;
unsigned int m_min, m_max, p_min = 2, p_max = 6;
@@ -123,8 +120,8 @@ static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
/* register has log2(N1), this works fine for powers of two */
n = ffs(n) - 1;
m_seed = lfsr_converts[calc_m - 62];
- dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
- dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT |
+ config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
+ config->dsi_pll.div = n << DSI_PLL_N1_DIV_SHIFT |
m_seed << DSI_PLL_M1_DIV_SHIFT;
return 0;
@@ -134,54 +131,63 @@ static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
* XXX: The muxing and gating is hard coded for now. Need to add support for
* sharing PLLs with two DSI outputs.
*/
-static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
+static int vlv_compute_dsi_pll(struct intel_encoder *encoder,
+ struct intel_crtc_state *config)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int ret;
- struct dsi_mnp dsi_mnp;
u32 dsi_clk;
dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
intel_dsi->lane_count);
- ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk);
+ ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
if (ret) {
DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
- return;
+ return ret;
}
if (intel_dsi->ports & (1 << PORT_A))
- dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
+ config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
if (intel_dsi->ports & (1 << PORT_C))
- dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
+ config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
+
+ config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
- dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
+ config->dsi_pll.div, config->dsi_pll.ctrl);
+
+ return 0;
+}
+
+static void vlv_configure_dsi_pll(struct intel_encoder *encoder,
+ const struct intel_crtc_state *config)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
- vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div);
- vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
+ vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
+ vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
+ config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
}
-static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
+static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
+ const struct intel_crtc_state *config)
{
- struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
- u32 tmp;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
DRM_DEBUG_KMS("\n");
mutex_lock(&dev_priv->sb_lock);
- vlv_configure_dsi_pll(encoder);
+ vlv_configure_dsi_pll(encoder, config);
/* wait at least 0.5 us after ungating before enabling VCO */
usleep_range(1, 10);
- tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
- tmp |= DSI_PLL_VCO_EN;
- vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
+ vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
DSI_PLL_LOCK, 20)) {
@@ -197,7 +203,7 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 tmp;
DRM_DEBUG_KMS("\n");
@@ -214,7 +220,7 @@ static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 val;
DRM_DEBUG_KMS("\n");
@@ -241,9 +247,10 @@ static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
bpp, pipe_bpp);
}
-static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
+static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
+ struct intel_crtc_state *config)
{
- struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u32 dsi_clock, pclk;
u32 pll_ctl, pll_div;
@@ -258,6 +265,9 @@ static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
mutex_unlock(&dev_priv->sb_lock);
+ config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
+ config->dsi_pll.div = pll_div;
+
/* mask out other bits and extract the P1 divisor */
pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
@@ -303,7 +313,8 @@ static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
return pclk;
}
-static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
+static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
+ struct intel_crtc_state *config)
{
u32 pclk;
u32 dsi_clk;
@@ -317,15 +328,9 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
return 0;
}
- dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) &
- BXT_DSI_PLL_RATIO_MASK;
+ config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
- /* Invalid DSI ratio ? */
- if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
- dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
- DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);
- return 0;
- }
+ dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
@@ -338,12 +343,13 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
return pclk;
}
-u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
+u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
+ struct intel_crtc_state *config)
{
if (IS_BROXTON(encoder->base.dev))
- return bxt_dsi_get_pclk(encoder, pipe_bpp);
+ return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
else
- return vlv_dsi_get_pclk(encoder, pipe_bpp);
+ return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
}
static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
@@ -360,7 +366,8 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
}
/* Program BXT Mipi clocks and dividers */
-static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
+static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
+ const struct intel_crtc_state *config)
{
struct drm_i915_private *dev_priv = dev->dev_private;
u32 tmp;
@@ -380,8 +387,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
/* Get the current DSI rate(actual) */
- pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
- BXT_DSI_PLL_RATIO_MASK;
+ pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
/*
@@ -417,16 +423,15 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
}
-static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
+static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
+ struct intel_crtc_state *config)
{
- struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u8 dsi_ratio;
u32 dsi_clk;
- u32 val;
dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
- intel_dsi->lane_count);
+ intel_dsi->lane_count);
/*
* From clock diagram, to get PLL ratio divider, divide double of DSI
@@ -435,9 +440,9 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
*/
dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
- dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
+ dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
- return false;
+ return -ECHRNG;
}
/*
@@ -445,27 +450,28 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
* Spec says both have to be programmed, even if one is not getting
* used. Configure MIPI_CLOCK_CTL dividers in modeset
*/
- val = I915_READ(BXT_DSI_PLL_CTL);
- val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
- val &= ~BXT_DSI_FREQ_SEL_MASK;
- val &= ~BXT_DSI_PLL_RATIO_MASK;
- val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2);
+ config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
/* As per recommendation from hardware team,
* Prog PVD ratio =1 if dsi ratio <= 50
*/
- if (dsi_ratio <= 50) {
- val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
- val |= BXT_DSI_PLL_PVD_RATIO_1;
- }
+ if (dsi_ratio <= 50)
+ config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
- I915_WRITE(BXT_DSI_PLL_CTL, val);
- POSTING_READ(BXT_DSI_PLL_CTL);
+ return 0;
+}
- return true;
+static void bxt_configure_dsi_pll(struct intel_encoder *encoder,
+ const struct intel_crtc_state *config)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
+ POSTING_READ(BXT_DSI_PLL_CTL);
}
-static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
+static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
+ const struct intel_crtc_state *config)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -475,14 +481,11 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
/* Configure PLL vales */
- if (!bxt_configure_dsi_pll(encoder)) {
- DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
- return;
- }
+ bxt_configure_dsi_pll(encoder, config);
/* Program TX, RX, Dphy clocks */
for_each_dsi_port(port, intel_dsi->ports)
- bxt_dsi_program_clocks(encoder->base.dev, port);
+ bxt_dsi_program_clocks(encoder->base.dev, port, config);
/* Enable DSI PLL */
val = I915_READ(BXT_DSI_PLL_ENABLE);
@@ -498,14 +501,28 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
DRM_DEBUG_KMS("DSI PLL locked\n");
}
-void intel_enable_dsi_pll(struct intel_encoder *encoder)
+int intel_compute_dsi_pll(struct intel_encoder *encoder,
+ struct intel_crtc_state *config)
+{
+ struct drm_device *dev = encoder->base.dev;
+
+ if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ return vlv_compute_dsi_pll(encoder, config);
+ else if (IS_BROXTON(dev))
+ return bxt_compute_dsi_pll(encoder, config);
+
+ return -ENODEV;
+}
+
+void intel_enable_dsi_pll(struct intel_encoder *encoder,
+ const struct intel_crtc_state *config)
{
struct drm_device *dev = encoder->base.dev;
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
- vlv_enable_dsi_pll(encoder);
+ vlv_enable_dsi_pll(encoder, config);
else if (IS_BROXTON(dev))
- bxt_enable_dsi_pll(encoder);
+ bxt_enable_dsi_pll(encoder, config);
}
void intel_disable_dsi_pll(struct intel_encoder *encoder)
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 12/16] drm/i915: Fix CHV DSI PLL refclk during state readout
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (10 preceding siblings ...)
2016-03-15 14:40 ` [PATCH 11/16] drm/i915: Compute DSI PLL parameters during .compute_config() ville.syrjala
@ 2016-03-15 14:40 ` ville.syrjala
2016-03-16 8:58 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 13/16] drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll() ville.syrjala
` (5 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use the proper refclock frequency (100MHz) when reading out the
current DSI clock on CHV.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index d35c8dc28fb6..99236baa946b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -255,7 +255,7 @@ static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
u32 dsi_clock, pclk;
u32 pll_ctl, pll_div;
u32 m = 0, p = 0, n;
- int refclk = 25000;
+ int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
int i;
DRM_DEBUG_KMS("\n");
--
2.4.10
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^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 13/16] drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll()
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (11 preceding siblings ...)
2016-03-15 14:40 ` [PATCH 12/16] drm/i915: Fix CHV DSI PLL refclk during state readout ville.syrjala
@ 2016-03-15 14:40 ` ville.syrjala
2016-03-16 8:59 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 14/16] drm/i915: Dump pfit PGM_RATIOS as hex ville.syrjala
` (4 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fold the DSI PLL configuration functions into the DSI PLL
enable functions since they are small and not called from anywhere else.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 28 ++++++----------------------
1 file changed, 6 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 99236baa946b..3d3132c12edb 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -162,17 +162,6 @@ static int vlv_compute_dsi_pll(struct intel_encoder *encoder,
return 0;
}
-static void vlv_configure_dsi_pll(struct intel_encoder *encoder,
- const struct intel_crtc_state *config)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-
- vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
- vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
- vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
- config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
-}
-
static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
const struct intel_crtc_state *config)
{
@@ -182,7 +171,10 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
mutex_lock(&dev_priv->sb_lock);
- vlv_configure_dsi_pll(encoder, config);
+ vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
+ vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
+ vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
+ config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
/* wait at least 0.5 us after ungating before enabling VCO */
usleep_range(1, 10);
@@ -461,15 +453,6 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
return 0;
}
-static void bxt_configure_dsi_pll(struct intel_encoder *encoder,
- const struct intel_crtc_state *config)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-
- I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
- POSTING_READ(BXT_DSI_PLL_CTL);
-}
-
static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
const struct intel_crtc_state *config)
{
@@ -481,7 +464,8 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
DRM_DEBUG_KMS("\n");
/* Configure PLL vales */
- bxt_configure_dsi_pll(encoder, config);
+ I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
+ POSTING_READ(BXT_DSI_PLL_CTL);
/* Program TX, RX, Dphy clocks */
for_each_dsi_port(port, intel_dsi->ports)
--
2.4.10
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 14/16] drm/i915: Dump pfit PGM_RATIOS as hex
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (12 preceding siblings ...)
2016-03-15 14:40 ` [PATCH 13/16] drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll() ville.syrjala
@ 2016-03-15 14:40 ` ville.syrjala
2016-03-16 9:00 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 15/16] drm/i915: Hook up pfit for DSI ville.syrjala
` (3 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
pgm_ratios in stored as a register value in pipe config, so let's dump
this one as hex as well.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d0b7fc85bc3a..ecda7e28ab9a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12722,7 +12722,7 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_X(gmch_pfit.control);
/* pfit ratios are autocomputed by the hw on gen4+ */
if (INTEL_INFO(dev)->gen < 4)
- PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
+ PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
if (!adjust) {
--
2.4.10
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 15/16] drm/i915: Hook up pfit for DSI
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (13 preceding siblings ...)
2016-03-15 14:40 ` [PATCH 14/16] drm/i915: Dump pfit PGM_RATIOS as hex ville.syrjala
@ 2016-03-15 14:40 ` ville.syrjala
2016-03-30 13:35 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 16/16] drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms ville.syrjala
` (2 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add the scaling mode property to DSI connectors, handle changes in the
property value, and compute the panel fitter state during
.compute_config().
v2: Handle BXT as well
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 74 +++++++++++++++++++++++++++++++++++++---
1 file changed, 69 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 1b4e83df4560..3823425a3e36 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -268,10 +268,12 @@ static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
static bool intel_dsi_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
base);
struct intel_connector *intel_connector = intel_dsi->attached_connector;
- struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+ const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
int ret;
@@ -279,9 +281,17 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
pipe_config->has_dsi_encoder = true;
- if (fixed_mode)
+ if (fixed_mode) {
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
+ if (HAS_GMCH_DISPLAY(dev_priv))
+ intel_gmch_panel_fitting(crtc, pipe_config,
+ intel_connector->panel.fitting_mode);
+ else
+ intel_pch_panel_fitting(crtc, pipe_config,
+ intel_connector->panel.fitting_mode);
+ }
+
/* DSI uses short packets for sync events, so clear mode flags for DSI */
adjusted_mode->flags = 0;
@@ -731,7 +741,7 @@ intel_dsi_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
struct intel_connector *intel_connector = to_intel_connector(connector);
- struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+ const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
DRM_DEBUG_KMS("\n");
@@ -1054,6 +1064,43 @@ static int intel_dsi_get_modes(struct drm_connector *connector)
return 1;
}
+static int intel_dsi_set_property(struct drm_connector *connector,
+ struct drm_property *property,
+ uint64_t val)
+{
+ struct drm_device *dev = connector->dev;
+ struct intel_connector *intel_connector = to_intel_connector(connector);
+ struct drm_crtc *crtc;
+ int ret;
+
+ ret = drm_object_property_set_value(&connector->base, property, val);
+ if (ret)
+ return ret;
+
+ if (property == dev->mode_config.scaling_mode_property) {
+ if (val == DRM_MODE_SCALE_NONE) {
+ DRM_DEBUG_KMS("no scaling not supported\n");
+ return -EINVAL;
+ }
+
+ if (intel_connector->panel.fitting_mode == val)
+ return 0;
+
+ intel_connector->panel.fitting_mode = val;
+ }
+
+ crtc = intel_attached_encoder(connector)->base.crtc;
+ if (crtc && crtc->state->enable) {
+ /*
+ * If the CRTC is enabled, the display will be changed
+ * according to the new panel fitting mode.
+ */
+ intel_crtc_restore_mode(crtc);
+ }
+
+ return 0;
+}
+
static void intel_dsi_connector_destroy(struct drm_connector *connector)
{
struct intel_connector *intel_connector = to_intel_connector(connector);
@@ -1096,11 +1143,25 @@ static const struct drm_connector_funcs intel_dsi_connector_funcs = {
.detect = intel_dsi_detect,
.destroy = intel_dsi_connector_destroy,
.fill_modes = drm_helper_probe_single_connector_modes,
+ .set_property = intel_dsi_set_property,
.atomic_get_property = intel_connector_atomic_get_property,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
};
+static void intel_dsi_add_properties(struct intel_connector *connector)
+{
+ struct drm_device *dev = connector->base.dev;
+
+ if (connector->panel.fixed_mode) {
+ drm_mode_create_scaling_mode_property(dev);
+ drm_object_attach_property(&connector->base.base,
+ dev->mode_config.scaling_mode_property,
+ DRM_MODE_SCALE_ASPECT);
+ connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
+ }
+}
+
void intel_dsi_init(struct drm_device *dev)
{
struct intel_dsi *intel_dsi;
@@ -1218,8 +1279,6 @@ void intel_dsi_init(struct drm_device *dev)
intel_connector_attach_encoder(intel_connector, intel_encoder);
- drm_connector_register(connector);
-
drm_panel_attach(intel_dsi->panel, connector);
mutex_lock(&dev->mode_config.mutex);
@@ -1238,6 +1297,11 @@ void intel_dsi_init(struct drm_device *dev)
}
intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
+
+ intel_dsi_add_properties(intel_connector);
+
+ drm_connector_register(connector);
+
intel_panel_setup_backlight(connector, INVALID_PIPE);
return;
--
2.4.10
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH 16/16] drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (14 preceding siblings ...)
2016-03-15 14:40 ` [PATCH 15/16] drm/i915: Hook up pfit for DSI ville.syrjala
@ 2016-03-15 14:40 ` ville.syrjala
2016-03-30 13:36 ` Jani Nikula
2016-03-15 15:27 ` ✗ Fi.CI.BAT: failure for drm/i915: DSI and DPLL stuff for VLV/CHV mostly Patchwork
2016-04-12 18:39 ` [PATCH 00/16] " Ville Syrjälä
17 siblings, 1 reply; 42+ messages in thread
From: ville.syrjala @ 2016-03-15 14:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We don't have a LVDS_BORDER_ENABLE type of bit for either eDP or DSI,
and just trying to frob the display timings to include borders results
in a corrupted picture. So reject the 'Center' scaling mode on GMCH
platforms for eDP and DSI.
TODO: Should really filter out the unsupported modes from the prop,
but that would be fairly invasive since the prop is now created and
stored by drm core. So leave it for a rainy day.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 5 +++++
drivers/gpu/drm/i915/intel_dsi.c | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0e326e776e8f..f268bda6d55e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4754,6 +4754,11 @@ intel_dp_set_property(struct drm_connector *connector,
DRM_DEBUG_KMS("no scaling not supported\n");
return -EINVAL;
}
+ if (HAS_GMCH_DISPLAY(dev_priv) &&
+ val == DRM_MODE_SCALE_CENTER) {
+ DRM_DEBUG_KMS("centering not supported\n");
+ return -EINVAL;
+ }
if (intel_connector->panel.fitting_mode == val) {
/* the eDP scaling property is not changed */
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 3823425a3e36..0ffa125a83e7 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1082,6 +1082,11 @@ static int intel_dsi_set_property(struct drm_connector *connector,
DRM_DEBUG_KMS("no scaling not supported\n");
return -EINVAL;
}
+ if (HAS_GMCH_DISPLAY(dev) &&
+ val == DRM_MODE_SCALE_CENTER) {
+ DRM_DEBUG_KMS("centering not supported\n");
+ return -EINVAL;
+ }
if (intel_connector->panel.fitting_mode == val)
return 0;
--
2.4.10
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 42+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: DSI and DPLL stuff for VLV/CHV mostly
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (15 preceding siblings ...)
2016-03-15 14:40 ` [PATCH 16/16] drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms ville.syrjala
@ 2016-03-15 15:27 ` Patchwork
2016-04-01 19:12 ` Ville Syrjälä
2016-04-12 18:39 ` [PATCH 00/16] " Ville Syrjälä
17 siblings, 1 reply; 42+ messages in thread
From: Patchwork @ 2016-03-15 15:27 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: DSI and DPLL stuff for VLV/CHV mostly
URL : https://patchwork.freedesktop.org/series/4472/
State : failure
== Summary ==
Series 4472v1 drm/i915: DSI and DPLL stuff for VLV/CHV mostly
http://patchwork.freedesktop.org/api/1.0/series/4472/revisions/1/mbox/
Test gem_ringfill:
Subgroup basic-default-s3:
pass -> DMESG-WARN (bsw-nuc-2)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass -> DMESG-WARN (bdw-ultra)
Subgroup basic-flip-vs-wf_vblank:
dmesg-warn -> PASS (hsw-brixbox)
Subgroup basic-plain-flip:
pass -> DMESG-WARN (hsw-brixbox)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b:
pass -> DMESG-WARN (hsw-brixbox)
Subgroup read-crc-pipe-c:
fail -> PASS (hsw-brixbox)
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS (skl-nuci5)
bdw-nuci7 total:194 pass:181 dwarn:0 dfail:0 fail:0 skip:13
bdw-ultra total:194 pass:172 dwarn:1 dfail:0 fail:0 skip:21
bsw-nuc-2 total:194 pass:156 dwarn:1 dfail:0 fail:0 skip:37
byt-nuc total:194 pass:155 dwarn:4 dfail:0 fail:0 skip:35
hsw-brixbox total:194 pass:170 dwarn:2 dfail:0 fail:0 skip:22
hsw-gt2 total:194 pass:177 dwarn:0 dfail:0 fail:0 skip:17
ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25
skl-i5k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
skl-nuci5 total:194 pass:183 dwarn:0 dfail:0 fail:0 skip:11
snb-dellxps total:194 pass:159 dwarn:1 dfail:0 fail:0 skip:34
Results at /archive/results/CI_IGT_test/Patchwork_1603/
fc881ebd9c3c26919c7d1113f8bf7014e1a05563 drm-intel-nightly: 2016y-03m-15d-13h-10m-41s UTC integration manifest
5efddb67a1588b732ac2ba0c89e258e6e3f72002 drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms
51623533abb03a96a2bedd56666577fee9bea750 drm/i915: Hook up pfit for DSI
3e4440df66c6bc0baa57caeb590c8af1593cc471 drm/i915: Dump pfit PGM_RATIOS as hex
6879ed09b83ff3930c87404d65c43fb4e2828c12 drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll()
6241adc4210412cef902b68e5fa39856beee86b9 drm/i915: Fix CHV DSI PLL refclk during state readout
7342e732e9304757e934440cfa5898c5c5c355b8 drm/i915: Compute DSI PLL parameters during .compute_config()
02cf9fe74efea1129b67c4f28e6b43f7f08b614a drm/i915: Power down the DSI PLL before reconfiguring it
fbd316324fb7b13e22ae14e815fdab5fca660cb1 drm/i915: Change lfsr_converts[] to u16
4a5fab6b1d66564ade2b5cc4eba6c0ec010f3e28 drm/i915: Don't read out port_clock on CHV when DPLL is disabled
bd993168e7a30cb208f1100906a4bf65363dd220 drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV
268fdd323dbe09d74cb575309f17b3a860ceaf1f drm/i915: Remove the "three times for luck" trick from vlv_enable_pll()
61a6befc33acbea46128efc806cfcc11214a5b72 drm/i915: assert_panel_unlocked() in chv_enable_pll()
6e59870b7c5559c18a0786b60af03df714e3a3bf drm/i915: Add a local pipe variable to vlv_enable_pll()
4c55229a544f6e165b54fc82c30758a6d775c1ee drm/i915: Implement WaPixelRepeatModeFixForC0:chv
9c162eb9644a4676365ba5e5e30aec6f157eb367 drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar
b67e0e51444022117f76de04947ffffbb2df1a31 drm/i915: Throw out BUGs from DPLL/PCH functions
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 09/16] drm/i915: Change lfsr_converts[] to u16
2016-03-15 14:40 ` [PATCH 09/16] drm/i915: Change lfsr_converts[] to u16 ville.syrjala
@ 2016-03-16 8:42 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2016-03-16 8:42 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> [ text/plain ]
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> All the values in the DSI PLL LFSR seed table fit into 9bits, so change
> the type to u16 from u32 to save a bit of space.
>
> drivers/gpu/drm/i915/i915.ko:
> -.rodata 90824
> +.rodata 90760
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 2451c84949bd..916cc92c1400 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -56,7 +56,7 @@ struct dsi_mnp {
> u32 dsi_pll_div;
> };
>
> -static const u32 lfsr_converts[] = {
> +static const u16 lfsr_converts[] = {
> 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
> 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
> 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 10/16] drm/i915: Power down the DSI PLL before reconfiguring it
2016-03-15 14:40 ` [PATCH 10/16] drm/i915: Power down the DSI PLL before reconfiguring it ville.syrjala
@ 2016-03-16 8:45 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2016-03-16 8:45 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> [ text/plain ]
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On VLV at least, the BIOS may leave the DSI PLL enabled in some wonky
> state where it just refuses to lock. Simply disabling the PLL before
> reconfiguring it is not enough to fix it, but power gating the PLL
> prior to reconfiguring does work.
>
> This happens on BYT FFRD8 when booting with HDMI connected so the DSI
> display will not be lit up by the BIOS.
>
> Also we can remove the code for BXT that disables the PLL before
> enabling it again.
>
> v2: s/vlv/intel/ since BXT made thing generic
> v3: Remove the BXT disable PLL before enable trick
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++
> drivers/gpu/drm/i915/intel_dsi_pll.c | 8 --------
> 2 files changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 4023b6bffa47..787411e1c36f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -482,7 +482,13 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
>
> DRM_DEBUG_KMS("\n");
>
> + /*
> + * The BIOS may leave the PLL in a wonky state where it doesn't
> + * lock. It needs to be fully powered down to fix it.
> + */
> + intel_disable_dsi_pll(encoder);
> intel_enable_dsi_pll(encoder);
> +
> intel_dsi_prepare(encoder);
>
> /* Panel Enable over CRC PMIC */
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 916cc92c1400..978cc2668a3d 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -474,14 +474,6 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
>
> DRM_DEBUG_KMS("\n");
>
> - val = I915_READ(BXT_DSI_PLL_ENABLE);
> -
> - if (val & BXT_DSI_PLL_DO_ENABLE) {
> - WARN(1, "DSI PLL already enabled. Disabling it.\n");
> - val &= ~BXT_DSI_PLL_DO_ENABLE;
> - I915_WRITE(BXT_DSI_PLL_ENABLE, val);
> - }
> -
> /* Configure PLL vales */
> if (!bxt_configure_dsi_pll(encoder)) {
> DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 11/16] drm/i915: Compute DSI PLL parameters during .compute_config()
2016-03-15 14:40 ` [PATCH 11/16] drm/i915: Compute DSI PLL parameters during .compute_config() ville.syrjala
@ 2016-03-16 8:56 ` Jani Nikula
2016-03-16 12:59 ` Ville Syrjälä
0 siblings, 1 reply; 42+ messages in thread
From: Jani Nikula @ 2016-03-16 8:56 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Compute the DSI PLL parameters during .compute_config() rather than
> .pre_pll_enable() so that we can fail gracefully if we can't find
> suitable parameters.
>
> In order to do that we need to store the DSI PLL parameters in
> pipe_config.
>
> v2: Handle BXT too
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[snip]
> @@ -317,15 +328,9 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
> return 0;
> }
>
> - dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) &
> - BXT_DSI_PLL_RATIO_MASK;
> + config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
>
> - /* Invalid DSI ratio ? */
> - if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
> - dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
> - DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);
> - return 0;
> - }
So you expect this to show up in the state checker instead now?
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 12/16] drm/i915: Fix CHV DSI PLL refclk during state readout
2016-03-15 14:40 ` [PATCH 12/16] drm/i915: Fix CHV DSI PLL refclk during state readout ville.syrjala
@ 2016-03-16 8:58 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2016-03-16 8:58 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use the proper refclock frequency (100MHz) when reading out the
> current DSI clock on CHV.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index d35c8dc28fb6..99236baa946b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -255,7 +255,7 @@ static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> u32 dsi_clock, pclk;
> u32 pll_ctl, pll_div;
> u32 m = 0, p = 0, n;
> - int refclk = 25000;
> + int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
> int i;
>
> DRM_DEBUG_KMS("\n");
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 13/16] drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll()
2016-03-15 14:40 ` [PATCH 13/16] drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll() ville.syrjala
@ 2016-03-16 8:59 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2016-03-16 8:59 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> [ text/plain ]
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Fold the DSI PLL configuration functions into the DSI PLL
> enable functions since they are small and not called from anywhere else.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_pll.c | 28 ++++++----------------------
> 1 file changed, 6 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 99236baa946b..3d3132c12edb 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -162,17 +162,6 @@ static int vlv_compute_dsi_pll(struct intel_encoder *encoder,
> return 0;
> }
>
> -static void vlv_configure_dsi_pll(struct intel_encoder *encoder,
> - const struct intel_crtc_state *config)
> -{
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -
> - vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
> - vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
> - vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
> - config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
> -}
> -
> static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
> const struct intel_crtc_state *config)
> {
> @@ -182,7 +171,10 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
>
> mutex_lock(&dev_priv->sb_lock);
>
> - vlv_configure_dsi_pll(encoder, config);
> + vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
> + vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
> + vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
> + config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
>
> /* wait at least 0.5 us after ungating before enabling VCO */
> usleep_range(1, 10);
> @@ -461,15 +453,6 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
> return 0;
> }
>
> -static void bxt_configure_dsi_pll(struct intel_encoder *encoder,
> - const struct intel_crtc_state *config)
> -{
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -
> - I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
> - POSTING_READ(BXT_DSI_PLL_CTL);
> -}
> -
> static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
> const struct intel_crtc_state *config)
> {
> @@ -481,7 +464,8 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
> DRM_DEBUG_KMS("\n");
>
> /* Configure PLL vales */
> - bxt_configure_dsi_pll(encoder, config);
> + I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
> + POSTING_READ(BXT_DSI_PLL_CTL);
>
> /* Program TX, RX, Dphy clocks */
> for_each_dsi_port(port, intel_dsi->ports)
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 14/16] drm/i915: Dump pfit PGM_RATIOS as hex
2016-03-15 14:40 ` [PATCH 14/16] drm/i915: Dump pfit PGM_RATIOS as hex ville.syrjala
@ 2016-03-16 9:00 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2016-03-16 9:00 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> pgm_ratios in stored as a register value in pipe config, so let's dump
> this one as hex as well.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d0b7fc85bc3a..ecda7e28ab9a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12722,7 +12722,7 @@ intel_pipe_config_compare(struct drm_device *dev,
> PIPE_CONF_CHECK_X(gmch_pfit.control);
> /* pfit ratios are autocomputed by the hw on gen4+ */
> if (INTEL_INFO(dev)->gen < 4)
> - PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
> + PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
> PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
>
> if (!adjust) {
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 01/16] drm/i915: Throw out BUGs from DPLL/PCH functions
2016-03-15 14:39 ` [PATCH 01/16] drm/i915: Throw out BUGs from DPLL/PCH functions ville.syrjala
@ 2016-03-16 9:02 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2016-03-16 9:02 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> These BUGs don't serve any purpose IMO. Throw them out.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
For some other things I might insist on replacing them with warns, but I
don't think these ones warrant that.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 ---------
> 1 file changed, 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ce55f0b683c6..22930f05457c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1661,9 +1661,6 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
>
> assert_pipe_disabled(dev_priv, crtc->pipe);
>
> - /* No really, not for ILK+ */
> - BUG_ON(INTEL_INFO(dev)->gen >= 5);
> -
> /* PLL is protected by panel, make sure we can write it */
> if (IS_MOBILE(dev) && !IS_I830(dev))
> assert_panel_unlocked(dev_priv, crtc->pipe);
> @@ -1839,9 +1836,6 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> i915_reg_t reg;
> uint32_t val, pipeconf_val;
>
> - /* PCH only available on ILK+ */
> - BUG_ON(!HAS_PCH_SPLIT(dev));
> -
> /* Make sure PCH DPLL is enabled */
> assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
>
> @@ -1895,9 +1889,6 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> {
> u32 val, pipeconf_val;
>
> - /* PCH only available on ILK+ */
> - BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
> -
> /* FDI must be feeding us bits for PCH ports */
> assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
> assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 04/16] drm/i915: Add a local pipe variable to vlv_enable_pll()
2016-03-15 14:39 ` [PATCH 04/16] drm/i915: Add a local pipe variable to vlv_enable_pll() ville.syrjala
@ 2016-03-16 9:03 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2016-03-16 9:03 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Avoid redundant crtc->pipe lookups by giving vlv_enable_pll() a local
> pipe variable. Also makes it look more like the corresponding CHV code.
>
> While at is change the CHV code to enum pipe from int,
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 17 +++++++++--------
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 18158b0324ed..638ce97777de 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1572,24 +1572,25 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - i915_reg_t reg = DPLL(crtc->pipe);
> + enum pipe pipe = crtc->pipe;
> + i915_reg_t reg = DPLL(pipe);
> u32 dpll = pipe_config->dpll_hw_state.dpll;
>
> - assert_pipe_disabled(dev_priv, crtc->pipe);
> + assert_pipe_disabled(dev_priv, pipe);
>
> /* PLL is protected by panel, make sure we can write it */
> if (IS_MOBILE(dev_priv->dev))
> - assert_panel_unlocked(dev_priv, crtc->pipe);
> + assert_panel_unlocked(dev_priv, pipe);
>
> I915_WRITE(reg, dpll);
> POSTING_READ(reg);
> udelay(150);
>
> if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> - DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
> + DRM_ERROR("DPLL %d failed to lock\n", pipe);
>
> - I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
> - POSTING_READ(DPLL_MD(crtc->pipe));
> + I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
> + POSTING_READ(DPLL_MD(pipe));
>
> /* We do this three times for luck */
> I915_WRITE(reg, dpll);
> @@ -1608,11 +1609,11 @@ static void chv_enable_pll(struct intel_crtc *crtc,
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - int pipe = crtc->pipe;
> + enum pipe pipe = crtc->pipe;
> enum dpio_channel port = vlv_pipe_to_channel(pipe);
> u32 tmp;
>
> - assert_pipe_disabled(dev_priv, crtc->pipe);
> + assert_pipe_disabled(dev_priv, pipe);
>
> mutex_lock(&dev_priv->sb_lock);
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 05/16] drm/i915: assert_panel_unlocked() in chv_enable_pll()
2016-03-15 14:39 ` [PATCH 05/16] drm/i915: assert_panel_unlocked() in chv_enable_pll() ville.syrjala
@ 2016-03-16 9:04 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2016-03-16 9:04 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Supposedly the power sequencer still locks out the DPLL registers on
> CHV, so let's issue a warning if it's still locked when enabling the
> DPLL.
>
> Also drop the redundant IS_MOBILE() check for VLV when we check the same
> thing.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 638ce97777de..d3332a33f8a7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1579,8 +1579,7 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
> assert_pipe_disabled(dev_priv, pipe);
>
> /* PLL is protected by panel, make sure we can write it */
> - if (IS_MOBILE(dev_priv->dev))
> - assert_panel_unlocked(dev_priv, pipe);
> + assert_panel_unlocked(dev_priv, pipe);
>
> I915_WRITE(reg, dpll);
> POSTING_READ(reg);
> @@ -1615,6 +1614,9 @@ static void chv_enable_pll(struct intel_crtc *crtc,
>
> assert_pipe_disabled(dev_priv, pipe);
>
> + /* PLL is protected by panel, make sure we can write it */
> + assert_panel_unlocked(dev_priv, pipe);
> +
> mutex_lock(&dev_priv->sb_lock);
>
> /* Enable back the 10bit clock to display controller */
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 06/16] drm/i915: Remove the "three times for luck" trick from vlv_enable_pll()
2016-03-15 14:39 ` [PATCH 06/16] drm/i915: Remove the "three times for luck" trick from vlv_enable_pll() ville.syrjala
@ 2016-03-16 9:05 ` Jani Nikula
2016-04-01 19:58 ` Ville Syrjälä
0 siblings, 1 reply; 42+ messages in thread
From: Jani Nikula @ 2016-03-16 9:05 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> VLV DPLL is somewhat sane and doesn't run on luck.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 11 -----------
> 1 file changed, 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d3332a33f8a7..c85b77c1188d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1590,17 +1590,6 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
>
> I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
> POSTING_READ(DPLL_MD(pipe));
> -
> - /* We do this three times for luck */
> - I915_WRITE(reg, dpll);
> - POSTING_READ(reg);
> - udelay(150); /* wait for warmup */
> - I915_WRITE(reg, dpll);
> - POSTING_READ(reg);
> - udelay(150); /* wait for warmup */
> - I915_WRITE(reg, dpll);
> - POSTING_READ(reg);
> - udelay(150); /* wait for warmup */
> }
>
> static void chv_enable_pll(struct intel_crtc *crtc,
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 08/16] drm/i915: Don't read out port_clock on CHV when DPLL is disabled
2016-03-15 14:40 ` [PATCH 08/16] drm/i915: Don't read out port_clock on CHV when DPLL is disabled ville.syrjala
@ 2016-03-16 9:06 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2016-03-16 9:06 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Check whether the DPLL is even enabled before readoing out the dividers
> and trying to derive port_clock on CHV. We already did this on VLV.
>
> Also remove the comment "MIPI" comment from the VLV code since we call
> this function whenever the pipe is enabled.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 98aae3914e9e..3e6b5fb140ad 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7969,8 +7969,8 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
> u32 mdiv;
> int refclk = 100000;
>
> - /* In case of MIPI DPLL will not even be used */
> - if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
> + /* In case of DSI, DPLL will not be used */
> + if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
> return;
>
> mutex_lock(&dev_priv->sb_lock);
> @@ -8066,6 +8066,10 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
> u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
> int refclk = 100000;
>
> + /* In case of DSI, DPLL will not be used */
> + if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
> + return;
> +
> mutex_lock(&dev_priv->sb_lock);
> cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
> pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 03/16] drm/i915: Implement WaPixelRepeatModeFixForC0:chv
2016-03-15 14:39 ` [PATCH 03/16] drm/i915: Implement WaPixelRepeatModeFixForC0:chv ville.syrjala
@ 2016-03-16 9:27 ` Jani Nikula
2016-03-16 13:07 ` Ville Syrjälä
0 siblings, 1 reply; 42+ messages in thread
From: Jani Nikula @ 2016-03-16 9:27 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> [ text/plain ]
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> DPLL_MD(PIPE_C) is AWOL on CHV. Instead of fixing it someone added
> chicken bits to propagate the pixel multiplier from DPLL_MD(PIPE_B)
> to either pipe B or C. So do that to make pixel repeat work on pipes
> B and C. Pipe A is fine without any tricks.
>
> Fortunately the pixel repeat propagation appears to be a oneshot
> operation, so once the value has been written we can clear the
> chicken bits. So it is still possible to drive pipe B and C with
> different pixel multipliers simultaneosly.
>
> Looks like DPLL_VGA_MODE_DIS must also be set in DPLL(PIPE_B)
> for this to work. But since we keep that bit always set in all
> DPLLs there's no problem.
>
> This of course means we can't reliably read out the pixel multiplier
> for pipes B and C. That would make the state checker unhappy, so I
> added shadow copies of those registers in to dev_priv. The other
> option would have been to skip pixel multiplier, dpll_md an dotclock
> checks entirely on CHV, but that feels like a serious loss of cross
> checking, so just pretending that we have working DPLL MD registers
> seemed better. Obviously with the shadow copies we can't detect if
> the pixel multiplier was properly configured, nor can we take over
> its state from the BIOS, but hopefully people won't have displays
> that would be limitd to such crappy modes.
>
> There is one strange flicker still remaining. It's visible on
> pipe C/HDMID when HDMIB is enabled while driven by pipe B.
> It doesn't occur if pipe A drives HDMIB, nor is there any glitch
> on pipe B/HDMIB when port C/HDMID starts up. I don't have a board
> with HDMIC so not sure if it happens there too. So I'm not sure
> if it's somehow tied in with this strange linkage between pipe B
> and C. Sadly I was unable to find an enable sequence that would
> avoid the glitch, but at least it's not fatal ie. the output
> recovers afterwards.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
I didn't dig up the specs, but the code seems to do what the commit
message says.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 7 +++++++
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++++++++++----
> 3 files changed, 37 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 80b14f1ba302..31689e1b19e6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1871,7 +1871,14 @@ struct drm_i915_private {
>
> u32 fdi_rx_config;
>
> + /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
> u32 chv_phy_control;
> + /*
> + * Shadows for CHV DPLL_MD regs to keep the state
> + * checker somewhat working in the presence hardware
> + * crappiness (can't read out DPLL_MD for pipes B & C).
> + */
> + u32 chv_dpll_md[I915_MAX_PIPES];
>
> u32 suspend_count;
> bool suspended_to_idle;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7dfc4007f3fa..f138588a88cd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4778,6 +4778,10 @@ enum skl_disp_power_wells {
> #define CBR_PND_DEADLINE_DISABLE (1<<31)
> #define CBR_PWM_CLOCK_MUX_SELECT (1<<30)
>
> +#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
> +#define CBR_DPLLBMD_PIPE_C (1<<29)
> +#define CBR_DPLLBMD_PIPE_B (1<<18)
> +
> /* FIFO watermark sizes etc */
> #define G4X_FIFO_LINE_SIZE 64
> #define I915_FIFO_LINE_SIZE 64
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 414ed5007e60..18158b0324ed 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1635,9 +1635,27 @@ static void chv_enable_pll(struct intel_crtc *crtc,
> if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> DRM_ERROR("PLL %d failed to lock\n", pipe);
>
> - /* not sure when this should be written */
> - I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
> - POSTING_READ(DPLL_MD(pipe));
> + if (pipe != PIPE_A) {
> + /*
> + * WaPixelRepeatModeFixForC0:chv
> + *
> + * DPLLCMD is AWOL. Use chicken bits to propagate
> + * the value from DPLLBMD to either pipe B or C.
> + */
> + I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
> + I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
> + I915_WRITE(CBR4_VLV, 0);
> + dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
> +
> + /*
> + * DPLLB VGA mode also seems to cause problems.
> + * We should always have it disabled.
> + */
> + WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
> + } else {
> + I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
> + POSTING_READ(DPLL_MD(pipe));
> + }
> }
>
> static int intel_num_dvo_pipes(struct drm_device *dev)
> @@ -8096,7 +8114,11 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> i9xx_get_pfit_config(crtc, pipe_config);
>
> if (INTEL_INFO(dev)->gen >= 4) {
> - tmp = I915_READ(DPLL_MD(crtc->pipe));
> + /* No way to read it out on pipes B and C */
> + if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
> + tmp = dev_priv->chv_dpll_md[crtc->pipe];
> + else
> + tmp = I915_READ(DPLL_MD(crtc->pipe));
> pipe_config->pixel_multiplier =
> ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
> >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 11/16] drm/i915: Compute DSI PLL parameters during .compute_config()
2016-03-16 8:56 ` Jani Nikula
@ 2016-03-16 12:59 ` Ville Syrjälä
0 siblings, 0 replies; 42+ messages in thread
From: Ville Syrjälä @ 2016-03-16 12:59 UTC (permalink / raw)
To: Jani Nikula; +Cc: Deepak M, intel-gfx
On Wed, Mar 16, 2016 at 10:56:33AM +0200, Jani Nikula wrote:
> On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Compute the DSI PLL parameters during .compute_config() rather than
> > .pre_pll_enable() so that we can fail gracefully if we can't find
> > suitable parameters.
> >
> > In order to do that we need to store the DSI PLL parameters in
> > pipe_config.
> >
> > v2: Handle BXT too
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> [snip]
>
> > @@ -317,15 +328,9 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
> > return 0;
> > }
> >
> > - dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) &
> > - BXT_DSI_PLL_RATIO_MASK;
> > + config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
> >
> > - /* Invalid DSI ratio ? */
> > - if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
> > - dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
> > - DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);
> > - return 0;
> > - }
>
> So you expect this to show up in the state checker instead now?
Frankly I'm not expecting it to show up at all. If the BIOS does program
an invalid value, well, then we should sanitize it somewhere without
spewing errors. If we misprogram it, then the state checker could catch
it (unless we have a bug in the compute phase already and somehow
compute the correct clock w/ an incorrect ratio).
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 03/16] drm/i915: Implement WaPixelRepeatModeFixForC0:chv
2016-03-16 9:27 ` Jani Nikula
@ 2016-03-16 13:07 ` Ville Syrjälä
0 siblings, 0 replies; 42+ messages in thread
From: Ville Syrjälä @ 2016-03-16 13:07 UTC (permalink / raw)
To: Jani Nikula; +Cc: Deepak M, intel-gfx
On Wed, Mar 16, 2016 at 11:27:05AM +0200, Jani Nikula wrote:
> On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> > [ text/plain ]
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > DPLL_MD(PIPE_C) is AWOL on CHV. Instead of fixing it someone added
> > chicken bits to propagate the pixel multiplier from DPLL_MD(PIPE_B)
> > to either pipe B or C. So do that to make pixel repeat work on pipes
> > B and C. Pipe A is fine without any tricks.
> >
> > Fortunately the pixel repeat propagation appears to be a oneshot
> > operation, so once the value has been written we can clear the
> > chicken bits. So it is still possible to drive pipe B and C with
> > different pixel multipliers simultaneosly.
> >
> > Looks like DPLL_VGA_MODE_DIS must also be set in DPLL(PIPE_B)
> > for this to work. But since we keep that bit always set in all
> > DPLLs there's no problem.
> >
> > This of course means we can't reliably read out the pixel multiplier
> > for pipes B and C. That would make the state checker unhappy, so I
> > added shadow copies of those registers in to dev_priv. The other
> > option would have been to skip pixel multiplier, dpll_md an dotclock
> > checks entirely on CHV, but that feels like a serious loss of cross
> > checking, so just pretending that we have working DPLL MD registers
> > seemed better. Obviously with the shadow copies we can't detect if
> > the pixel multiplier was properly configured, nor can we take over
> > its state from the BIOS, but hopefully people won't have displays
> > that would be limitd to such crappy modes.
> >
> > There is one strange flicker still remaining. It's visible on
> > pipe C/HDMID when HDMIB is enabled while driven by pipe B.
> > It doesn't occur if pipe A drives HDMIB, nor is there any glitch
> > on pipe B/HDMIB when port C/HDMID starts up. I don't have a board
> > with HDMIC so not sure if it happens there too. So I'm not sure
> > if it's somehow tied in with this strange linkage between pipe B
> > and C. Sadly I was unable to find an enable sequence that would
> > avoid the glitch, but at least it's not fatal ie. the output
> > recovers afterwards.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I didn't dig up the specs, but the code seems to do what the commit
> message says.
The "spec" wouldn't help much either, apart from showing where
the chicken bits live. I might have a powerpoint somewhere about
this, but it IIRC it didn't really tell you how to do things in
practice. As far as I can remember, I just used the standard
trial and error method to implement this.
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 7 +++++++
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++++++++++----
> > 3 files changed, 37 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 80b14f1ba302..31689e1b19e6 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1871,7 +1871,14 @@ struct drm_i915_private {
> >
> > u32 fdi_rx_config;
> >
> > + /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
> > u32 chv_phy_control;
> > + /*
> > + * Shadows for CHV DPLL_MD regs to keep the state
> > + * checker somewhat working in the presence hardware
> > + * crappiness (can't read out DPLL_MD for pipes B & C).
> > + */
> > + u32 chv_dpll_md[I915_MAX_PIPES];
> >
> > u32 suspend_count;
> > bool suspended_to_idle;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7dfc4007f3fa..f138588a88cd 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4778,6 +4778,10 @@ enum skl_disp_power_wells {
> > #define CBR_PND_DEADLINE_DISABLE (1<<31)
> > #define CBR_PWM_CLOCK_MUX_SELECT (1<<30)
> >
> > +#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
> > +#define CBR_DPLLBMD_PIPE_C (1<<29)
> > +#define CBR_DPLLBMD_PIPE_B (1<<18)
> > +
> > /* FIFO watermark sizes etc */
> > #define G4X_FIFO_LINE_SIZE 64
> > #define I915_FIFO_LINE_SIZE 64
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 414ed5007e60..18158b0324ed 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1635,9 +1635,27 @@ static void chv_enable_pll(struct intel_crtc *crtc,
> > if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> > DRM_ERROR("PLL %d failed to lock\n", pipe);
> >
> > - /* not sure when this should be written */
> > - I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
> > - POSTING_READ(DPLL_MD(pipe));
> > + if (pipe != PIPE_A) {
> > + /*
> > + * WaPixelRepeatModeFixForC0:chv
> > + *
> > + * DPLLCMD is AWOL. Use chicken bits to propagate
> > + * the value from DPLLBMD to either pipe B or C.
> > + */
> > + I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
> > + I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
> > + I915_WRITE(CBR4_VLV, 0);
> > + dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
> > +
> > + /*
> > + * DPLLB VGA mode also seems to cause problems.
> > + * We should always have it disabled.
> > + */
> > + WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
> > + } else {
> > + I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
> > + POSTING_READ(DPLL_MD(pipe));
> > + }
> > }
> >
> > static int intel_num_dvo_pipes(struct drm_device *dev)
> > @@ -8096,7 +8114,11 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> > i9xx_get_pfit_config(crtc, pipe_config);
> >
> > if (INTEL_INFO(dev)->gen >= 4) {
> > - tmp = I915_READ(DPLL_MD(crtc->pipe));
> > + /* No way to read it out on pipes B and C */
> > + if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
> > + tmp = dev_priv->chv_dpll_md[crtc->pipe];
> > + else
> > + tmp = I915_READ(DPLL_MD(crtc->pipe));
> > pipe_config->pixel_multiplier =
> > ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
> > >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
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^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 02/16] drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar
2016-03-15 14:39 ` [PATCH 02/16] drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar ville.syrjala
@ 2016-03-30 13:31 ` Jani Nikula
2016-04-01 19:59 ` Ville Syrjälä
0 siblings, 1 reply; 42+ messages in thread
From: Jani Nikula @ 2016-03-30 13:31 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The VLV and CHV DPLL disable and update are almost identical in
> how the DPLL/DPLL_MD registers need to be set up. But the code
> looks more different than it really is. Try to bring them into
> line.
>
> v2: s/chv_update_pll/chv_compute_dpll/
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 63 ++++++++++++++----------------------
> 1 file changed, 25 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 22930f05457c..414ed5007e60 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1759,16 +1759,13 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> /* Make sure the pipe isn't still relying on us */
> assert_pipe_disabled(dev_priv, pipe);
>
> - /*
> - * Leave integrated clock source and reference clock enabled for pipe B.
> - * The latter is needed for VGA hotplug / manual detection.
> - */
So, you change this to keep the reference clock enabled for both
pipes. Deserves a mention in the commit message. AFAICT it's the only
functional change in the patch.
Other than that,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> - val = DPLL_VGA_MODE_DIS;
> - if (pipe == PIPE_B)
> - val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
> + val = DPLL_INTEGRATED_REF_CLK_VLV |
> + DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> + if (pipe != PIPE_A)
> + val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> +
> I915_WRITE(DPLL(pipe), val);
> POSTING_READ(DPLL(pipe));
> -
> }
>
> static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> @@ -1779,11 +1776,11 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> /* Make sure the pipe isn't still relying on us */
> assert_pipe_disabled(dev_priv, pipe);
>
> - /* Set PLL en = 0 */
> val = DPLL_SSC_REF_CLK_CHV |
> DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> if (pipe != PIPE_A)
> val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> +
> I915_WRITE(DPLL(pipe), val);
> POSTING_READ(DPLL(pipe));
>
> @@ -7240,24 +7237,27 @@ void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
> static void vlv_compute_dpll(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> - u32 dpll, dpll_md;
> + pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
> + DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> + DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
> + if (crtc->pipe != PIPE_A)
> + pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
>
> - /*
> - * Enable DPIO clock input. We should never disable the reference
> - * clock for pipe B, since VGA hotplug / manual detection depends
> - * on it.
> - */
> - dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
> - DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
> - /* We should never disable this, set it here for state tracking */
> - if (crtc->pipe == PIPE_B)
> - dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> - dpll |= DPLL_VCO_ENABLE;
> - pipe_config->dpll_hw_state.dpll = dpll;
> + pipe_config->dpll_hw_state.dpll_md =
> + (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> +}
> +
> +static void chv_compute_dpll(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config)
> +{
> + pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
> + DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> + DPLL_VCO_ENABLE;
> + if (crtc->pipe != PIPE_A)
> + pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
>
> - dpll_md = (pipe_config->pixel_multiplier - 1)
> - << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> - pipe_config->dpll_hw_state.dpll_md = dpll_md;
> + pipe_config->dpll_hw_state.dpll_md =
> + (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> }
>
> static void vlv_prepare_pll(struct intel_crtc *crtc,
> @@ -7351,19 +7351,6 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
> mutex_unlock(&dev_priv->sb_lock);
> }
>
> -static void chv_compute_dpll(struct intel_crtc *crtc,
> - struct intel_crtc_state *pipe_config)
> -{
> - pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
> - DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> - DPLL_VCO_ENABLE;
> - if (crtc->pipe != PIPE_A)
> - pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> -
> - pipe_config->dpll_hw_state.dpll_md =
> - (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> -}
> -
> static void chv_prepare_pll(struct intel_crtc *crtc,
> const struct intel_crtc_state *pipe_config)
> {
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 15/16] drm/i915: Hook up pfit for DSI
2016-03-15 14:40 ` [PATCH 15/16] drm/i915: Hook up pfit for DSI ville.syrjala
@ 2016-03-30 13:35 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2016-03-30 13:35 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add the scaling mode property to DSI connectors, handle changes in the
> property value, and compute the panel fitter state during
> .compute_config().
>
> v2: Handle BXT as well
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 74 +++++++++++++++++++++++++++++++++++++---
> 1 file changed, 69 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 1b4e83df4560..3823425a3e36 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -268,10 +268,12 @@ static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
> static bool intel_dsi_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
> base);
> struct intel_connector *intel_connector = intel_dsi->attached_connector;
> - struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> int ret;
>
> @@ -279,9 +281,17 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
>
> pipe_config->has_dsi_encoder = true;
>
> - if (fixed_mode)
> + if (fixed_mode) {
> intel_fixed_panel_mode(fixed_mode, adjusted_mode);
>
> + if (HAS_GMCH_DISPLAY(dev_priv))
> + intel_gmch_panel_fitting(crtc, pipe_config,
> + intel_connector->panel.fitting_mode);
> + else
> + intel_pch_panel_fitting(crtc, pipe_config,
> + intel_connector->panel.fitting_mode);
> + }
> +
> /* DSI uses short packets for sync events, so clear mode flags for DSI */
> adjusted_mode->flags = 0;
>
> @@ -731,7 +741,7 @@ intel_dsi_mode_valid(struct drm_connector *connector,
> struct drm_display_mode *mode)
> {
> struct intel_connector *intel_connector = to_intel_connector(connector);
> - struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> + const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
>
> DRM_DEBUG_KMS("\n");
> @@ -1054,6 +1064,43 @@ static int intel_dsi_get_modes(struct drm_connector *connector)
> return 1;
> }
>
> +static int intel_dsi_set_property(struct drm_connector *connector,
> + struct drm_property *property,
> + uint64_t val)
> +{
> + struct drm_device *dev = connector->dev;
> + struct intel_connector *intel_connector = to_intel_connector(connector);
> + struct drm_crtc *crtc;
> + int ret;
> +
> + ret = drm_object_property_set_value(&connector->base, property, val);
> + if (ret)
> + return ret;
> +
> + if (property == dev->mode_config.scaling_mode_property) {
> + if (val == DRM_MODE_SCALE_NONE) {
> + DRM_DEBUG_KMS("no scaling not supported\n");
> + return -EINVAL;
> + }
> +
> + if (intel_connector->panel.fitting_mode == val)
> + return 0;
> +
> + intel_connector->panel.fitting_mode = val;
> + }
> +
> + crtc = intel_attached_encoder(connector)->base.crtc;
> + if (crtc && crtc->state->enable) {
> + /*
> + * If the CRTC is enabled, the display will be changed
> + * according to the new panel fitting mode.
> + */
> + intel_crtc_restore_mode(crtc);
> + }
> +
> + return 0;
> +}
> +
> static void intel_dsi_connector_destroy(struct drm_connector *connector)
> {
> struct intel_connector *intel_connector = to_intel_connector(connector);
> @@ -1096,11 +1143,25 @@ static const struct drm_connector_funcs intel_dsi_connector_funcs = {
> .detect = intel_dsi_detect,
> .destroy = intel_dsi_connector_destroy,
> .fill_modes = drm_helper_probe_single_connector_modes,
> + .set_property = intel_dsi_set_property,
> .atomic_get_property = intel_connector_atomic_get_property,
> .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> };
>
> +static void intel_dsi_add_properties(struct intel_connector *connector)
> +{
> + struct drm_device *dev = connector->base.dev;
> +
> + if (connector->panel.fixed_mode) {
> + drm_mode_create_scaling_mode_property(dev);
> + drm_object_attach_property(&connector->base.base,
> + dev->mode_config.scaling_mode_property,
> + DRM_MODE_SCALE_ASPECT);
> + connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
> + }
> +}
> +
> void intel_dsi_init(struct drm_device *dev)
> {
> struct intel_dsi *intel_dsi;
> @@ -1218,8 +1279,6 @@ void intel_dsi_init(struct drm_device *dev)
>
> intel_connector_attach_encoder(intel_connector, intel_encoder);
>
> - drm_connector_register(connector);
> -
> drm_panel_attach(intel_dsi->panel, connector);
>
> mutex_lock(&dev->mode_config.mutex);
> @@ -1238,6 +1297,11 @@ void intel_dsi_init(struct drm_device *dev)
> }
>
> intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
> +
> + intel_dsi_add_properties(intel_connector);
> +
> + drm_connector_register(connector);
> +
> intel_panel_setup_backlight(connector, INVALID_PIPE);
>
> return;
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 16/16] drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms
2016-03-15 14:40 ` [PATCH 16/16] drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms ville.syrjala
@ 2016-03-30 13:36 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2016-03-30 13:36 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Deepak M
On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We don't have a LVDS_BORDER_ENABLE type of bit for either eDP or DSI,
> and just trying to frob the display timings to include borders results
> in a corrupted picture. So reject the 'Center' scaling mode on GMCH
> platforms for eDP and DSI.
>
> TODO: Should really filter out the unsupported modes from the prop,
> but that would be fairly invasive since the prop is now created and
> stored by drm core. So leave it for a rainy day.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 5 +++++
> drivers/gpu/drm/i915/intel_dsi.c | 5 +++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 0e326e776e8f..f268bda6d55e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4754,6 +4754,11 @@ intel_dp_set_property(struct drm_connector *connector,
> DRM_DEBUG_KMS("no scaling not supported\n");
> return -EINVAL;
> }
> + if (HAS_GMCH_DISPLAY(dev_priv) &&
> + val == DRM_MODE_SCALE_CENTER) {
> + DRM_DEBUG_KMS("centering not supported\n");
> + return -EINVAL;
> + }
>
> if (intel_connector->panel.fitting_mode == val) {
> /* the eDP scaling property is not changed */
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 3823425a3e36..0ffa125a83e7 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -1082,6 +1082,11 @@ static int intel_dsi_set_property(struct drm_connector *connector,
> DRM_DEBUG_KMS("no scaling not supported\n");
> return -EINVAL;
> }
> + if (HAS_GMCH_DISPLAY(dev) &&
> + val == DRM_MODE_SCALE_CENTER) {
> + DRM_DEBUG_KMS("centering not supported\n");
> + return -EINVAL;
> + }
>
> if (intel_connector->panel.fitting_mode == val)
> return 0;
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915: DSI and DPLL stuff for VLV/CHV mostly
2016-03-15 15:27 ` ✗ Fi.CI.BAT: failure for drm/i915: DSI and DPLL stuff for VLV/CHV mostly Patchwork
@ 2016-04-01 19:12 ` Ville Syrjälä
2016-04-01 19:39 ` Chris Wilson
0 siblings, 1 reply; 42+ messages in thread
From: Ville Syrjälä @ 2016-04-01 19:12 UTC (permalink / raw)
To: intel-gfx
On Tue, Mar 15, 2016 at 03:27:30PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: DSI and DPLL stuff for VLV/CHV mostly
> URL : https://patchwork.freedesktop.org/series/4472/
> State : failure
>
> == Summary ==
>
> Series 4472v1 drm/i915: DSI and DPLL stuff for VLV/CHV mostly
> http://patchwork.freedesktop.org/api/1.0/series/4472/revisions/1/mbox/
>
> Test gem_ringfill:
> Subgroup basic-default-s3:
> pass -> DMESG-WARN (bsw-nuc-2)
lockdep splat
https://bugs.freedesktop.org/show_bug.cgi?id=94350
already fixed it seems.
> Test kms_flip:
> Subgroup basic-flip-vs-dpms:
> pass -> DMESG-WARN (bdw-ultra)
[ 481.430003] WARNING: CPU: 2 PID: 6638 at drivers/gpu/drm/i915/intel_drv.h:1497 gen8_write32+0x2b3/0x310 [i915]()
[ 481.430005] Device suspended during HW access
[ 481.430122] [<ffffffffa03bf723>] gen8_write32+0x2b3/0x310 [i915]
[ 481.430148] [<ffffffffa036dba8>] _ilk_disable_lp_wm+0x98/0xd0 [i915]
https://bugs.freedesktop.org/show_bug.cgi?id=94349
also fixed already.
> Subgroup basic-flip-vs-wf_vblank:
> dmesg-warn -> PASS (hsw-brixbox)
> Subgroup basic-plain-flip:
> pass -> DMESG-WARN (hsw-brixbox)
same
> Test kms_pipe_crc_basic:
> Subgroup read-crc-pipe-b:
> pass -> DMESG-WARN (hsw-brixbox)
same
> Subgroup read-crc-pipe-c:
> fail -> PASS (hsw-brixbox)
> Subgroup suspend-read-crc-pipe-b:
> dmesg-warn -> PASS (skl-nuci5)
>
> bdw-nuci7 total:194 pass:181 dwarn:0 dfail:0 fail:0 skip:13
> bdw-ultra total:194 pass:172 dwarn:1 dfail:0 fail:0 skip:21
> bsw-nuc-2 total:194 pass:156 dwarn:1 dfail:0 fail:0 skip:37
> byt-nuc total:194 pass:155 dwarn:4 dfail:0 fail:0 skip:35
> hsw-brixbox total:194 pass:170 dwarn:2 dfail:0 fail:0 skip:22
> hsw-gt2 total:194 pass:177 dwarn:0 dfail:0 fail:0 skip:17
> ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25
> skl-i5k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
> skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
> skl-nuci5 total:194 pass:183 dwarn:0 dfail:0 fail:0 skip:11
> snb-dellxps total:194 pass:159 dwarn:1 dfail:0 fail:0 skip:34
>
> Results at /archive/results/CI_IGT_test/Patchwork_1603/
>
> fc881ebd9c3c26919c7d1113f8bf7014e1a05563 drm-intel-nightly: 2016y-03m-15d-13h-10m-41s UTC integration manifest
> 5efddb67a1588b732ac2ba0c89e258e6e3f72002 drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms
> 51623533abb03a96a2bedd56666577fee9bea750 drm/i915: Hook up pfit for DSI
> 3e4440df66c6bc0baa57caeb590c8af1593cc471 drm/i915: Dump pfit PGM_RATIOS as hex
> 6879ed09b83ff3930c87404d65c43fb4e2828c12 drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll()
> 6241adc4210412cef902b68e5fa39856beee86b9 drm/i915: Fix CHV DSI PLL refclk during state readout
> 7342e732e9304757e934440cfa5898c5c5c355b8 drm/i915: Compute DSI PLL parameters during .compute_config()
> 02cf9fe74efea1129b67c4f28e6b43f7f08b614a drm/i915: Power down the DSI PLL before reconfiguring it
> fbd316324fb7b13e22ae14e815fdab5fca660cb1 drm/i915: Change lfsr_converts[] to u16
> 4a5fab6b1d66564ade2b5cc4eba6c0ec010f3e28 drm/i915: Don't read out port_clock on CHV when DPLL is disabled
> bd993168e7a30cb208f1100906a4bf65363dd220 drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV
> 268fdd323dbe09d74cb575309f17b3a860ceaf1f drm/i915: Remove the "three times for luck" trick from vlv_enable_pll()
> 61a6befc33acbea46128efc806cfcc11214a5b72 drm/i915: assert_panel_unlocked() in chv_enable_pll()
> 6e59870b7c5559c18a0786b60af03df714e3a3bf drm/i915: Add a local pipe variable to vlv_enable_pll()
> 4c55229a544f6e165b54fc82c30758a6d775c1ee drm/i915: Implement WaPixelRepeatModeFixForC0:chv
> 9c162eb9644a4676365ba5e5e30aec6f157eb367 drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar
> b67e0e51444022117f76de04947ffffbb2df1a31 drm/i915: Throw out BUGs from DPLL/PCH functions
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915: DSI and DPLL stuff for VLV/CHV mostly
2016-04-01 19:12 ` Ville Syrjälä
@ 2016-04-01 19:39 ` Chris Wilson
2016-04-01 19:47 ` Ville Syrjälä
0 siblings, 1 reply; 42+ messages in thread
From: Chris Wilson @ 2016-04-01 19:39 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Apr 01, 2016 at 10:12:09PM +0300, Ville Syrjälä wrote:
> On Tue, Mar 15, 2016 at 03:27:30PM -0000, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915: DSI and DPLL stuff for VLV/CHV mostly
> > URL : https://patchwork.freedesktop.org/series/4472/
> > State : failure
> >
> > == Summary ==
> >
> > Series 4472v1 drm/i915: DSI and DPLL stuff for VLV/CHV mostly
> > http://patchwork.freedesktop.org/api/1.0/series/4472/revisions/1/mbox/
> >
> > Test gem_ringfill:
> > Subgroup basic-default-s3:
> > pass -> DMESG-WARN (bsw-nuc-2)
>
> lockdep splat
> https://bugs.freedesktop.org/show_bug.cgi?id=94350
>
> already fixed it seems.
Absolutely sure it is the same one? The GEM busy suspend tests are meant
to be provoking a very similar lockdep splat!
Can you paste it here?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915: DSI and DPLL stuff for VLV/CHV mostly
2016-04-01 19:39 ` Chris Wilson
@ 2016-04-01 19:47 ` Ville Syrjälä
2016-04-01 19:53 ` Chris Wilson
0 siblings, 1 reply; 42+ messages in thread
From: Ville Syrjälä @ 2016-04-01 19:47 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On Fri, Apr 01, 2016 at 08:39:22PM +0100, Chris Wilson wrote:
> On Fri, Apr 01, 2016 at 10:12:09PM +0300, Ville Syrjälä wrote:
> > On Tue, Mar 15, 2016 at 03:27:30PM -0000, Patchwork wrote:
> > > == Series Details ==
> > >
> > > Series: drm/i915: DSI and DPLL stuff for VLV/CHV mostly
> > > URL : https://patchwork.freedesktop.org/series/4472/
> > > State : failure
> > >
> > > == Summary ==
> > >
> > > Series 4472v1 drm/i915: DSI and DPLL stuff for VLV/CHV mostly
> > > http://patchwork.freedesktop.org/api/1.0/series/4472/revisions/1/mbox/
> > >
> > > Test gem_ringfill:
> > > Subgroup basic-default-s3:
> > > pass -> DMESG-WARN (bsw-nuc-2)
> >
> > lockdep splat
> > https://bugs.freedesktop.org/show_bug.cgi?id=94350
> >
> > already fixed it seems.
>
> Absolutely sure it is the same one? The GEM busy suspend tests are meant
> to be provoking a very similar lockdep splat!
>
> Can you paste it here?
I thought I had, but apparently not.
[ 517.449665] ======================================================
[ 517.449667] [ INFO: possible circular locking dependency detected ]
[ 517.449671] 4.5.0-gfxbench+ #1 Not tainted
[ 517.449672] -------------------------------------------------------
[ 517.449675] rtcwake/7020 is trying to acquire lock:
[ 517.449692] (s_active#43){++++.+}, at: [<ffffffff81250740>] kernfs_remove_by_name_ns+0x40/0xa0
[ 517.449693]
but task is already holding lock:
[ 517.449703] (cpu_hotplug.lock){+.+.+.}, at: [<ffffffff81078f5d>] cpu_hotplug_begin+0x6d/0xc0
[ 517.449704]
which lock already depends on the new lock.
[ 517.449705]
the existing dependency chain (in reverse order) is:
[ 517.449711]
-> #3 (cpu_hotplug.lock){+.+.+.}:
[ 517.449717] [<ffffffff810cd7e1>] lock_acquire+0xb1/0x200
[ 517.449724] [<ffffffff817c1412>] mutex_lock_nested+0x62/0x3b0
[ 517.449729] [<ffffffff81078c21>] get_online_cpus+0x61/0x80
[ 517.449736] [<ffffffff81118d0b>] stop_machine+0x1b/0xe0
[ 517.449742] [<ffffffffa015975d>] 0xffffffffa015975d
[ 517.449746] [<ffffffffa015ddc6>] 0xffffffffa015ddc6
[ 517.449749] [<ffffffffa015f5af>] 0xffffffffa015f5af
[ 517.449752] [<ffffffffa0167031>] 0xffffffffa0167031
[ 517.449755] [<ffffffffa01672e8>] 0xffffffffa01672e8
[ 517.449758] [<ffffffffa017b03e>] 0xffffffffa017b03e
[ 517.449761] [<ffffffffa0178052>] 0xffffffffa0178052
[ 517.449764] [<ffffffffa0167db3>] 0xffffffffa0167db3
[ 517.449767] [<ffffffffa01ec5c1>] 0xffffffffa01ec5c1
[ 517.449773] [<ffffffff815199b4>] drm_dev_register+0xa4/0xb0
[ 517.449779] [<ffffffff8151bbce>] drm_get_pci_dev+0xce/0x1e0
[ 517.449782] [<ffffffffa01272ff>] 0xffffffffa01272ff
[ 517.449789] [<ffffffff81446657>] pci_device_probe+0x87/0xf0
[ 517.449794] [<ffffffff8153d729>] driver_probe_device+0x229/0x450
[ 517.449798] [<ffffffff8153d9d3>] __driver_attach+0x83/0x90
[ 517.449804] [<ffffffff8153b401>] bus_for_each_dev+0x61/0xa0
[ 517.449808] [<ffffffff8153d019>] driver_attach+0x19/0x20
[ 517.449812] [<ffffffff8153caff>] bus_add_driver+0x1ef/0x290
[ 517.449816] [<ffffffff8153e6fb>] driver_register+0x5b/0xe0
[ 517.449822] [<ffffffff8144558b>] __pci_register_driver+0x5b/0x60
[ 517.449827] [<ffffffff8151bdb6>] drm_pci_init+0xd6/0x100
[ 517.449830] [<ffffffffa0260094>] 0xffffffffa0260094
[ 517.449837] [<ffffffff810003de>] do_one_initcall+0xae/0x1d0
[ 517.449844] [<ffffffff8115b415>] do_init_module+0x5b/0x1c6
[ 517.449850] [<ffffffff81107d3a>] load_module+0x1c0a/0x24b0
[ 517.449853] [<ffffffff811087ce>] SyS_finit_module+0x7e/0xa0
[ 517.449859] [<ffffffff817c5cdb>] entry_SYSCALL_64_fastpath+0x16/0x73
[ 517.449864]
-> #2 (&dev->struct_mutex){+.+.+.}:
[ 517.449869] [<ffffffff810cd7e1>] lock_acquire+0xb1/0x200
[ 517.449875] [<ffffffff81514ec7>] drm_gem_mmap+0x1c7/0x270
[ 517.449882] [<ffffffff81199354>] mmap_region+0x334/0x580
[ 517.449886] [<ffffffff81199904>] do_mmap+0x364/0x410
[ 517.449891] [<ffffffff8117d8ed>] vm_mmap_pgoff+0x6d/0xa0
[ 517.449895] [<ffffffff81197a34>] SyS_mmap_pgoff+0x184/0x220
[ 517.449900] [<ffffffff8100a28d>] SyS_mmap+0x1d/0x20
[ 517.449905] [<ffffffff817c5cdb>] entry_SYSCALL_64_fastpath+0x16/0x73
[ 517.449910]
-> #1 (&mm->mmap_sem){++++++}:
[ 517.449914] [<ffffffff810cd7e1>] lock_acquire+0xb1/0x200
[ 517.449919] [<ffffffff8118e575>] __might_fault+0x75/0xa0
[ 517.449923] [<ffffffff8125114a>] kernfs_fop_write+0x8a/0x180
[ 517.449928] [<ffffffff811d3ce3>] __vfs_write+0x23/0xe0
[ 517.449933] [<ffffffff811d4a44>] vfs_write+0xa4/0x190
[ 517.449937] [<ffffffff811d58e4>] SyS_write+0x44/0xb0
[ 517.449941] [<ffffffff817c5cdb>] entry_SYSCALL_64_fastpath+0x16/0x73
[ 517.449947]
-> #0 (s_active#43){++++.+}:
[ 517.449951] [<ffffffff810ccdc9>] __lock_acquire+0x1fc9/0x20f0
[ 517.449954] [<ffffffff810cd7e1>] lock_acquire+0xb1/0x200
[ 517.449958] [<ffffffff8124f770>] __kernfs_remove+0x210/0x2f0
[ 517.449962] [<ffffffff81250740>] kernfs_remove_by_name_ns+0x40/0xa0
[ 517.449968] [<ffffffff81252aed>] sysfs_unmerge_group+0x3d/0x60
[ 517.449974] [<ffffffff81545524>] dpm_sysfs_remove+0x34/0x60
[ 517.449980] [<ffffffff81538f94>] device_del+0x44/0x250
[ 517.449983] [<ffffffff815391b9>] device_unregister+0x19/0x60
[ 517.449989] [<ffffffff815438e1>] cpu_cache_sysfs_exit+0x51/0xb0
[ 517.449993] [<ffffffff81543eb8>] cacheinfo_cpu_callback+0x38/0x70
[ 517.449999] [<ffffffff8109ba09>] notifier_call_chain+0x39/0xa0
[ 517.450003] [<ffffffff8109ba79>] __raw_notifier_call_chain+0x9/0x10
[ 517.450007] [<ffffffff81078e3e>] cpu_notify+0x1e/0x40
[ 517.450011] [<ffffffff81078ed9>] cpu_notify_nofail+0x9/0x20
[ 517.450014] [<ffffffff81079223>] _cpu_down+0x233/0x340
[ 517.450020] [<ffffffff81079763>] disable_nonboot_cpus+0xb3/0x3b0
[ 517.450027] [<ffffffff810d3f74>] suspend_devices_and_enter+0x5b4/0xc50
[ 517.450032] [<ffffffff810d4b41>] pm_suspend+0x531/0x9f0
[ 517.450036] [<ffffffff810d2c57>] state_store+0x77/0xe0
[ 517.450043] [<ffffffff8140109f>] kobj_attr_store+0xf/0x20
[ 517.450047] [<ffffffff81251e40>] sysfs_kf_write+0x40/0x50
[ 517.450051] [<ffffffff812511fc>] kernfs_fop_write+0x13c/0x180
[ 517.450055] [<ffffffff811d3ce3>] __vfs_write+0x23/0xe0
[ 517.450060] [<ffffffff811d4a44>] vfs_write+0xa4/0x190
[ 517.450063] [<ffffffff811d58e4>] SyS_write+0x44/0xb0
[ 517.450068] [<ffffffff817c5cdb>] entry_SYSCALL_64_fastpath+0x16/0x73
[ 517.450070]
other info that might help us debug this:
[ 517.450078] Chain exists of:
s_active#43 --> &dev->struct_mutex --> cpu_hotplug.lock
[ 517.450079] Possible unsafe locking scenario:
[ 517.450080] CPU0 CPU1
[ 517.450081] ---- ----
[ 517.450084] lock(cpu_hotplug.lock);
[ 517.450087] lock(&dev->struct_mutex);
[ 517.450089] lock(cpu_hotplug.lock);
[ 517.450093] lock(s_active#43);
[ 517.450094]
*** DEADLOCK ***
[ 517.450098] 8 locks held by rtcwake/7020:
[ 517.450108] #0: (sb_writers#6){.+.+.+}, at: [<ffffffff811d8074>] __sb_start_write+0xd4/0xf0
[ 517.450116] #1: (&of->mutex){+.+.+.}, at: [<ffffffff81251121>] kernfs_fop_write+0x61/0x180
[ 517.450125] #2: (s_active#221){.+.+.+}, at: [<ffffffff81251129>] kernfs_fop_write+0x69/0x180
[ 517.450133] #3: (pm_mutex){+.+...}, at: [<ffffffff810d4686>] pm_suspend+0x76/0x9f0
[ 517.450143] #4: (acpi_scan_lock){+.+.+.}, at: [<ffffffff814798d9>] acpi_scan_lock_acquire+0x12/0x14
[ 517.450151] #5: (cpu_add_remove_lock){+.+.+.}, at: [<ffffffff810796d4>] disable_nonboot_cpus+0x24/0x3b0
[ 517.450159] #6: (cpu_hotplug.dep_map){++++++}, at: [<ffffffff81078ef0>] cpu_hotplug_begin+0x0/0xc0
[ 517.450166] #7: (cpu_hotplug.lock){+.+.+.}, at: [<ffffffff81078f5d>] cpu_hotplug_begin+0x6d/0xc0
[ 517.450167]
stack backtrace:
[ 517.450173] CPU: 0 PID: 7020 Comm: rtcwake Not tainted 4.5.0-gfxbench+ #1
[ 517.450174] Hardware name: /NUC5CPYB, BIOS PYBSWCEL.86A.0040.2015.0814.1353 08/14/2015
[ 517.450181] 0000000000000000 ffff88016638f820 ffffffff813fef15 ffffffff825f70a0
[ 517.450187] ffffffff825a0220 ffff88016638f860 ffffffff810c941c ffff88016638f8c0
[ 517.450192] ffff88017a8b8940 ffff88017a8b8000 0000000000000008 ffff88017a8b8968
[ 517.450194] Call Trace:
[ 517.450198] [<ffffffff813fef15>] dump_stack+0x67/0x92
[ 517.450202] [<ffffffff810c941c>] print_circular_bug+0x1fc/0x310
[ 517.450206] [<ffffffff810ccdc9>] __lock_acquire+0x1fc9/0x20f0
[ 517.450210] [<ffffffff810cd7e1>] lock_acquire+0xb1/0x200
[ 517.450215] [<ffffffff81250740>] ? kernfs_remove_by_name_ns+0x40/0xa0
[ 517.450218] [<ffffffff8124f770>] __kernfs_remove+0x210/0x2f0
[ 517.450222] [<ffffffff81250740>] ? kernfs_remove_by_name_ns+0x40/0xa0
[ 517.450225] [<ffffffff8124f988>] ? kernfs_find_ns+0x78/0x130
[ 517.450228] [<ffffffff81250740>] kernfs_remove_by_name_ns+0x40/0xa0
[ 517.450232] [<ffffffff81252aed>] sysfs_unmerge_group+0x3d/0x60
[ 517.450236] [<ffffffff81545524>] dpm_sysfs_remove+0x34/0x60
[ 517.450239] [<ffffffff81538f94>] device_del+0x44/0x250
[ 517.450242] [<ffffffff815391b9>] device_unregister+0x19/0x60
[ 517.450246] [<ffffffff815438e1>] cpu_cache_sysfs_exit+0x51/0xb0
[ 517.450249] [<ffffffff81543eb8>] cacheinfo_cpu_callback+0x38/0x70
[ 517.450253] [<ffffffff8109ba09>] notifier_call_chain+0x39/0xa0
[ 517.450256] [<ffffffff8109ba79>] __raw_notifier_call_chain+0x9/0x10
[ 517.450259] [<ffffffff81078e3e>] cpu_notify+0x1e/0x40
[ 517.450262] [<ffffffff81078ed9>] cpu_notify_nofail+0x9/0x20
[ 517.450265] [<ffffffff81079223>] _cpu_down+0x233/0x340
[ 517.450271] [<ffffffff810e5310>] ? __call_rcu.constprop.61+0x2f0/0x2f0
[ 517.450274] [<ffffffff810e5370>] ? call_rcu_bh+0x20/0x20
[ 517.450280] [<ffffffff810e0e00>] ? trace_raw_output_rcu_utilization+0x60/0x60
[ 517.450285] [<ffffffff810e0e00>] ? trace_raw_output_rcu_utilization+0x60/0x60
[ 517.450289] [<ffffffff81079763>] disable_nonboot_cpus+0xb3/0x3b0
[ 517.450293] [<ffffffff810d3f74>] suspend_devices_and_enter+0x5b4/0xc50
[ 517.450298] [<ffffffff810c80a9>] ? __lock_is_held+0x49/0x70
[ 517.450302] [<ffffffff810d4b41>] pm_suspend+0x531/0x9f0
[ 517.450306] [<ffffffff810d2c57>] state_store+0x77/0xe0
[ 517.450309] [<ffffffff8140109f>] kobj_attr_store+0xf/0x20
[ 517.450313] [<ffffffff81251e40>] sysfs_kf_write+0x40/0x50
[ 517.450316] [<ffffffff812511fc>] kernfs_fop_write+0x13c/0x180
[ 517.450320] [<ffffffff811d3ce3>] __vfs_write+0x23/0xe0
[ 517.450325] [<ffffffff810c6aa2>] ? percpu_down_read+0x52/0x90
[ 517.450328] [<ffffffff811d8074>] ? __sb_start_write+0xd4/0xf0
[ 517.450331] [<ffffffff811d8074>] ? __sb_start_write+0xd4/0xf0
[ 517.450334] [<ffffffff811d4a44>] vfs_write+0xa4/0x190
[ 517.450340] [<ffffffff811f324a>] ? __fget_light+0x6a/0x90
[ 517.450343] [<ffffffff811d58e4>] SyS_write+0x44/0xb0
[ 517.450347] [<ffffffff817c5cdb>] entry_SYSCALL_64_fastpath+0x16/0x73
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915: DSI and DPLL stuff for VLV/CHV mostly
2016-04-01 19:47 ` Ville Syrjälä
@ 2016-04-01 19:53 ` Chris Wilson
0 siblings, 0 replies; 42+ messages in thread
From: Chris Wilson @ 2016-04-01 19:53 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Apr 01, 2016 at 10:47:13PM +0300, Ville Syrjälä wrote:
> On Fri, Apr 01, 2016 at 08:39:22PM +0100, Chris Wilson wrote:
> > On Fri, Apr 01, 2016 at 10:12:09PM +0300, Ville Syrjälä wrote:
> > > On Tue, Mar 15, 2016 at 03:27:30PM -0000, Patchwork wrote:
> > > > == Series Details ==
> > > >
> > > > Series: drm/i915: DSI and DPLL stuff for VLV/CHV mostly
> > > > URL : https://patchwork.freedesktop.org/series/4472/
> > > > State : failure
> > > >
> > > > == Summary ==
> > > >
> > > > Series 4472v1 drm/i915: DSI and DPLL stuff for VLV/CHV mostly
> > > > http://patchwork.freedesktop.org/api/1.0/series/4472/revisions/1/mbox/
> > > >
> > > > Test gem_ringfill:
> > > > Subgroup basic-default-s3:
> > > > pass -> DMESG-WARN (bsw-nuc-2)
> > >
> > > lockdep splat
> > > https://bugs.freedesktop.org/show_bug.cgi?id=94350
> > >
> > > already fixed it seems.
> >
> > Absolutely sure it is the same one? The GEM busy suspend tests are meant
> > to be provoking a very similar lockdep splat!
> >
> > Can you paste it here?
>
> I thought I had, but apparently not.
You probably had, I keep asking just in case I find the one I'm
interested in. Sadly this is the 4 step kernfs splat, so yes it should be
fixed in future CI runs.
Thanks,
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 06/16] drm/i915: Remove the "three times for luck" trick from vlv_enable_pll()
2016-03-16 9:05 ` Jani Nikula
@ 2016-04-01 19:58 ` Ville Syrjälä
0 siblings, 0 replies; 42+ messages in thread
From: Ville Syrjälä @ 2016-04-01 19:58 UTC (permalink / raw)
To: Jani Nikula; +Cc: Deepak M, intel-gfx
On Wed, Mar 16, 2016 at 11:05:30AM +0200, Jani Nikula wrote:
> On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > VLV DPLL is somewhat sane and doesn't run on luck.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Acked-by: Jani Nikula <jani.nikula@intel.com>
Pushed to dinq up to this patch. Thanks for the review.
>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 11 -----------
> > 1 file changed, 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index d3332a33f8a7..c85b77c1188d 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1590,17 +1590,6 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
> >
> > I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
> > POSTING_READ(DPLL_MD(pipe));
> > -
> > - /* We do this three times for luck */
> > - I915_WRITE(reg, dpll);
> > - POSTING_READ(reg);
> > - udelay(150); /* wait for warmup */
> > - I915_WRITE(reg, dpll);
> > - POSTING_READ(reg);
> > - udelay(150); /* wait for warmup */
> > - I915_WRITE(reg, dpll);
> > - POSTING_READ(reg);
> > - udelay(150); /* wait for warmup */
> > }
> >
> > static void chv_enable_pll(struct intel_crtc *crtc,
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 02/16] drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar
2016-03-30 13:31 ` Jani Nikula
@ 2016-04-01 19:59 ` Ville Syrjälä
0 siblings, 0 replies; 42+ messages in thread
From: Ville Syrjälä @ 2016-04-01 19:59 UTC (permalink / raw)
To: Jani Nikula; +Cc: Deepak M, intel-gfx
On Wed, Mar 30, 2016 at 04:31:04PM +0300, Jani Nikula wrote:
> On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The VLV and CHV DPLL disable and update are almost identical in
> > how the DPLL/DPLL_MD registers need to be set up. But the code
> > looks more different than it really is. Try to bring them into
> > line.
> >
> > v2: s/chv_update_pll/chv_compute_dpll/
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 63 ++++++++++++++----------------------
> > 1 file changed, 25 insertions(+), 38 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 22930f05457c..414ed5007e60 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1759,16 +1759,13 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> > /* Make sure the pipe isn't still relying on us */
> > assert_pipe_disabled(dev_priv, pipe);
> >
> > - /*
> > - * Leave integrated clock source and reference clock enabled for pipe B.
> > - * The latter is needed for VGA hotplug / manual detection.
> > - */
>
> So, you change this to keep the reference clock enabled for both
> pipes. Deserves a mention in the commit message. AFAICT it's the only
> functional change in the patch.
Added the following note while pushing:
"Note that we now leave the refclock always enabled for both
DPLLs in the dual channel PHY. But that's perfectly fine since
it's the same clock, and we anyway already do that when turning
the disp2d power well on."
>
> Other than that,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
> > - val = DPLL_VGA_MODE_DIS;
> > - if (pipe == PIPE_B)
> > - val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
> > + val = DPLL_INTEGRATED_REF_CLK_VLV |
> > + DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> > + if (pipe != PIPE_A)
> > + val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> > +
> > I915_WRITE(DPLL(pipe), val);
> > POSTING_READ(DPLL(pipe));
> > -
> > }
> >
> > static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> > @@ -1779,11 +1776,11 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> > /* Make sure the pipe isn't still relying on us */
> > assert_pipe_disabled(dev_priv, pipe);
> >
> > - /* Set PLL en = 0 */
> > val = DPLL_SSC_REF_CLK_CHV |
> > DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> > if (pipe != PIPE_A)
> > val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> > +
> > I915_WRITE(DPLL(pipe), val);
> > POSTING_READ(DPLL(pipe));
> >
> > @@ -7240,24 +7237,27 @@ void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
> > static void vlv_compute_dpll(struct intel_crtc *crtc,
> > struct intel_crtc_state *pipe_config)
> > {
> > - u32 dpll, dpll_md;
> > + pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
> > + DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> > + DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
> > + if (crtc->pipe != PIPE_A)
> > + pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> >
> > - /*
> > - * Enable DPIO clock input. We should never disable the reference
> > - * clock for pipe B, since VGA hotplug / manual detection depends
> > - * on it.
> > - */
> > - dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
> > - DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
> > - /* We should never disable this, set it here for state tracking */
> > - if (crtc->pipe == PIPE_B)
> > - dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> > - dpll |= DPLL_VCO_ENABLE;
> > - pipe_config->dpll_hw_state.dpll = dpll;
> > + pipe_config->dpll_hw_state.dpll_md =
> > + (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> > +}
> > +
> > +static void chv_compute_dpll(struct intel_crtc *crtc,
> > + struct intel_crtc_state *pipe_config)
> > +{
> > + pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
> > + DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> > + DPLL_VCO_ENABLE;
> > + if (crtc->pipe != PIPE_A)
> > + pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> >
> > - dpll_md = (pipe_config->pixel_multiplier - 1)
> > - << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> > - pipe_config->dpll_hw_state.dpll_md = dpll_md;
> > + pipe_config->dpll_hw_state.dpll_md =
> > + (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> > }
> >
> > static void vlv_prepare_pll(struct intel_crtc *crtc,
> > @@ -7351,19 +7351,6 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
> > mutex_unlock(&dev_priv->sb_lock);
> > }
> >
> > -static void chv_compute_dpll(struct intel_crtc *crtc,
> > - struct intel_crtc_state *pipe_config)
> > -{
> > - pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
> > - DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> > - DPLL_VCO_ENABLE;
> > - if (crtc->pipe != PIPE_A)
> > - pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> > -
> > - pipe_config->dpll_hw_state.dpll_md =
> > - (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> > -}
> > -
> > static void chv_prepare_pll(struct intel_crtc *crtc,
> > const struct intel_crtc_state *pipe_config)
> > {
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
` (16 preceding siblings ...)
2016-03-15 15:27 ` ✗ Fi.CI.BAT: failure for drm/i915: DSI and DPLL stuff for VLV/CHV mostly Patchwork
@ 2016-04-12 18:39 ` Ville Syrjälä
17 siblings, 0 replies; 42+ messages in thread
From: Ville Syrjälä @ 2016-04-12 18:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
On Tue, Mar 15, 2016 at 04:39:53PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Here's a pile of pending VLV/CHV DSI and DPLL patches I had lying around.
> Most of these have been posted before. Would be nice to finally get them
> in.
>
> I've tried to rebase things to account for BXT as well, but obviously
> that part is not tested. I have tested this on a BYT FFRD8 which has
> a DSI panel.
>
> Apart from the VLV/CHV specific stuff, the main thing here is moving
> the DSI PLL calculations to the .compute_config() phase. Another neat
> thing is hooking up the panel fitter for DSI.
>
> Ville Syrjälä (16):
> drm/i915: Throw out BUGs from DPLL/PCH functions
> drm/i915: Make {vlv,chv}_{disable,update}_pll() more similar
> drm/i915: Implement WaPixelRepeatModeFixForC0:chv
> drm/i915: Add a local pipe variable to vlv_enable_pll()
> drm/i915: assert_panel_unlocked() in chv_enable_pll()
> drm/i915: Remove the "three times for luck" trick from
> vlv_enable_pll()
These I have pushed earlier.
> drm/i915: Don't read out port_clock on CHV when DPLL is disabled
> drm/i915: Change lfsr_converts[] to u16
> drm/i915: Power down the DSI PLL before reconfiguring it
> drm/i915: Fix CHV DSI PLL refclk during state readout
> drm/i915: Dump pfit PGM_RATIOS as hex
These I just pushed now. Thanks for the reviews.
> drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV
> drm/i915: Compute DSI PLL parameters during .compute_config()
> drm/i915: Eliminate {vlv,bxt}_configure_dsi_pll()
> drm/i915: Hook up pfit for DSI
> drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms
These are still out in the cold. I'll rebase and repost them
as a new series.
>
> drivers/gpu/drm/i915/i915_drv.h | 7 +
> drivers/gpu/drm/i915/i915_reg.h | 4 +
> drivers/gpu/drm/i915/intel_display.c | 244 +++++++++++++++++++----------------
> drivers/gpu/drm/i915/intel_dp.c | 5 +
> drivers/gpu/drm/i915/intel_drv.h | 5 +
> drivers/gpu/drm/i915/intel_dsi.c | 120 +++++++++++++----
> drivers/gpu/drm/i915/intel_dsi.h | 14 +-
> drivers/gpu/drm/i915/intel_dsi_pll.c | 155 +++++++++++-----------
> 8 files changed, 332 insertions(+), 222 deletions(-)
>
> --
> 2.4.10
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 42+ messages in thread
end of thread, other threads:[~2016-04-12 18:39 UTC | newest]
Thread overview: 42+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
2016-03-15 14:39 ` [PATCH 01/16] drm/i915: Throw out BUGs from DPLL/PCH functions ville.syrjala
2016-03-16 9:02 ` Jani Nikula
2016-03-15 14:39 ` [PATCH 02/16] drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar ville.syrjala
2016-03-30 13:31 ` Jani Nikula
2016-04-01 19:59 ` Ville Syrjälä
2016-03-15 14:39 ` [PATCH 03/16] drm/i915: Implement WaPixelRepeatModeFixForC0:chv ville.syrjala
2016-03-16 9:27 ` Jani Nikula
2016-03-16 13:07 ` Ville Syrjälä
2016-03-15 14:39 ` [PATCH 04/16] drm/i915: Add a local pipe variable to vlv_enable_pll() ville.syrjala
2016-03-16 9:03 ` Jani Nikula
2016-03-15 14:39 ` [PATCH 05/16] drm/i915: assert_panel_unlocked() in chv_enable_pll() ville.syrjala
2016-03-16 9:04 ` Jani Nikula
2016-03-15 14:39 ` [PATCH 06/16] drm/i915: Remove the "three times for luck" trick from vlv_enable_pll() ville.syrjala
2016-03-16 9:05 ` Jani Nikula
2016-04-01 19:58 ` Ville Syrjälä
2016-03-15 14:40 ` [PATCH 07/16] drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV ville.syrjala
2016-03-15 14:40 ` [PATCH 08/16] drm/i915: Don't read out port_clock on CHV when DPLL is disabled ville.syrjala
2016-03-16 9:06 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 09/16] drm/i915: Change lfsr_converts[] to u16 ville.syrjala
2016-03-16 8:42 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 10/16] drm/i915: Power down the DSI PLL before reconfiguring it ville.syrjala
2016-03-16 8:45 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 11/16] drm/i915: Compute DSI PLL parameters during .compute_config() ville.syrjala
2016-03-16 8:56 ` Jani Nikula
2016-03-16 12:59 ` Ville Syrjälä
2016-03-15 14:40 ` [PATCH 12/16] drm/i915: Fix CHV DSI PLL refclk during state readout ville.syrjala
2016-03-16 8:58 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 13/16] drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll() ville.syrjala
2016-03-16 8:59 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 14/16] drm/i915: Dump pfit PGM_RATIOS as hex ville.syrjala
2016-03-16 9:00 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 15/16] drm/i915: Hook up pfit for DSI ville.syrjala
2016-03-30 13:35 ` Jani Nikula
2016-03-15 14:40 ` [PATCH 16/16] drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms ville.syrjala
2016-03-30 13:36 ` Jani Nikula
2016-03-15 15:27 ` ✗ Fi.CI.BAT: failure for drm/i915: DSI and DPLL stuff for VLV/CHV mostly Patchwork
2016-04-01 19:12 ` Ville Syrjälä
2016-04-01 19:39 ` Chris Wilson
2016-04-01 19:47 ` Ville Syrjälä
2016-04-01 19:53 ` Chris Wilson
2016-04-12 18:39 ` [PATCH 00/16] " Ville Syrjälä
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