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* [PATCH] reset: sunxi: fix for 64-bit compilation
@ 2017-03-06  1:35 ` Andre Przywara
  0 siblings, 0 replies; 8+ messages in thread
From: Andre Przywara @ 2017-03-06  1:35 UTC (permalink / raw)
  To: Maxime Ripard, Chen-Yu Tsai, Philipp Zabel; +Cc: linux-arm-kernel, linux-kernel

The Allwinner reset controller has 32-bit registers, so translating
the reset cell number into a register and bit offset should not use
any architecture dependent data size. Otherwise this breaks for 64-bit
architectures like arm64.
Fix this by making it clear that it's the hardware register width which
matters here in the calculation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/reset/reset-sunxi.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c
index b44f6b5..cd585cd 100644
--- a/drivers/reset/reset-sunxi.c
+++ b/drivers/reset/reset-sunxi.c
@@ -34,15 +34,16 @@ static int sunxi_reset_assert(struct reset_controller_dev *rcdev,
 	struct sunxi_reset_data *data = container_of(rcdev,
 						     struct sunxi_reset_data,
 						     rcdev);
-	int bank = id / BITS_PER_LONG;
-	int offset = id % BITS_PER_LONG;
+	int reg_width = sizeof(u32);
+	int bank = id / (reg_width * BITS_PER_BYTE);
+	int offset = id % (reg_width * BITS_PER_BYTE);
 	unsigned long flags;
 	u32 reg;
 
 	spin_lock_irqsave(&data->lock, flags);
 
-	reg = readl(data->membase + (bank * 4));
-	writel(reg & ~BIT(offset), data->membase + (bank * 4));
+	reg = readl(data->membase + (bank * reg_width));
+	writel(reg & ~BIT(offset), data->membase + (bank * reg_width));
 
 	spin_unlock_irqrestore(&data->lock, flags);
 
@@ -55,15 +56,16 @@ static int sunxi_reset_deassert(struct reset_controller_dev *rcdev,
 	struct sunxi_reset_data *data = container_of(rcdev,
 						     struct sunxi_reset_data,
 						     rcdev);
-	int bank = id / BITS_PER_LONG;
-	int offset = id % BITS_PER_LONG;
+	int reg_width = sizeof(u32);
+	int bank = id / (reg_width * BITS_PER_BYTE);
+	int offset = id % (reg_width * BITS_PER_BYTE);
 	unsigned long flags;
 	u32 reg;
 
 	spin_lock_irqsave(&data->lock, flags);
 
-	reg = readl(data->membase + (bank * 4));
-	writel(reg | BIT(offset), data->membase + (bank * 4));
+	reg = readl(data->membase + (bank * reg_width));
+	writel(reg | BIT(offset), data->membase + (bank * reg_width));
 
 	spin_unlock_irqrestore(&data->lock, flags);
 
-- 
2.8.2

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH] reset: sunxi: fix for 64-bit compilation
@ 2017-03-06  1:35 ` Andre Przywara
  0 siblings, 0 replies; 8+ messages in thread
From: Andre Przywara @ 2017-03-06  1:35 UTC (permalink / raw)
  To: linux-arm-kernel

The Allwinner reset controller has 32-bit registers, so translating
the reset cell number into a register and bit offset should not use
any architecture dependent data size. Otherwise this breaks for 64-bit
architectures like arm64.
Fix this by making it clear that it's the hardware register width which
matters here in the calculation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/reset/reset-sunxi.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c
index b44f6b5..cd585cd 100644
--- a/drivers/reset/reset-sunxi.c
+++ b/drivers/reset/reset-sunxi.c
@@ -34,15 +34,16 @@ static int sunxi_reset_assert(struct reset_controller_dev *rcdev,
 	struct sunxi_reset_data *data = container_of(rcdev,
 						     struct sunxi_reset_data,
 						     rcdev);
-	int bank = id / BITS_PER_LONG;
-	int offset = id % BITS_PER_LONG;
+	int reg_width = sizeof(u32);
+	int bank = id / (reg_width * BITS_PER_BYTE);
+	int offset = id % (reg_width * BITS_PER_BYTE);
 	unsigned long flags;
 	u32 reg;
 
 	spin_lock_irqsave(&data->lock, flags);
 
-	reg = readl(data->membase + (bank * 4));
-	writel(reg & ~BIT(offset), data->membase + (bank * 4));
+	reg = readl(data->membase + (bank * reg_width));
+	writel(reg & ~BIT(offset), data->membase + (bank * reg_width));
 
 	spin_unlock_irqrestore(&data->lock, flags);
 
@@ -55,15 +56,16 @@ static int sunxi_reset_deassert(struct reset_controller_dev *rcdev,
 	struct sunxi_reset_data *data = container_of(rcdev,
 						     struct sunxi_reset_data,
 						     rcdev);
-	int bank = id / BITS_PER_LONG;
-	int offset = id % BITS_PER_LONG;
+	int reg_width = sizeof(u32);
+	int bank = id / (reg_width * BITS_PER_BYTE);
+	int offset = id % (reg_width * BITS_PER_BYTE);
 	unsigned long flags;
 	u32 reg;
 
 	spin_lock_irqsave(&data->lock, flags);
 
-	reg = readl(data->membase + (bank * 4));
-	writel(reg | BIT(offset), data->membase + (bank * 4));
+	reg = readl(data->membase + (bank * reg_width));
+	writel(reg | BIT(offset), data->membase + (bank * reg_width));
 
 	spin_unlock_irqrestore(&data->lock, flags);
 
-- 
2.8.2

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* Re: [PATCH] reset: sunxi: fix for 64-bit compilation
  2017-03-06  1:35 ` Andre Przywara
@ 2017-03-08  4:28   ` Chen-Yu Tsai
  -1 siblings, 0 replies; 8+ messages in thread
From: Chen-Yu Tsai @ 2017-03-08  4:28 UTC (permalink / raw)
  To: Andre Przywara
  Cc: Maxime Ripard, Chen-Yu Tsai, Philipp Zabel, linux-arm-kernel,
	linux-kernel

On Mon, Mar 6, 2017 at 9:35 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> The Allwinner reset controller has 32-bit registers, so translating
> the reset cell number into a register and bit offset should not use
> any architecture dependent data size. Otherwise this breaks for 64-bit
> architectures like arm64.
> Fix this by making it clear that it's the hardware register width which
> matters here in the calculation.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

Though I don't expect this driver to be used with arm64 chips.

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH] reset: sunxi: fix for 64-bit compilation
@ 2017-03-08  4:28   ` Chen-Yu Tsai
  0 siblings, 0 replies; 8+ messages in thread
From: Chen-Yu Tsai @ 2017-03-08  4:28 UTC (permalink / raw)
  To: linux-arm-kernel

On Mon, Mar 6, 2017 at 9:35 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> The Allwinner reset controller has 32-bit registers, so translating
> the reset cell number into a register and bit offset should not use
> any architecture dependent data size. Otherwise this breaks for 64-bit
> architectures like arm64.
> Fix this by making it clear that it's the hardware register width which
> matters here in the calculation.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

Though I don't expect this driver to be used with arm64 chips.

^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH] reset: sunxi: fix for 64-bit compilation
  2017-03-08  4:28   ` Chen-Yu Tsai
@ 2017-03-08  9:26     ` Andre Przywara
  -1 siblings, 0 replies; 8+ messages in thread
From: Andre Przywara @ 2017-03-08  9:26 UTC (permalink / raw)
  To: Chen-Yu Tsai; +Cc: Maxime Ripard, Philipp Zabel, linux-arm-kernel, linux-kernel

Hi,

On 08/03/17 04:28, Chen-Yu Tsai wrote:
> On Mon, Mar 6, 2017 at 9:35 AM, Andre Przywara <andre.przywara@arm.com> wrote:
>> The Allwinner reset controller has 32-bit registers, so translating
>> the reset cell number into a register and bit offset should not use
>> any architecture dependent data size. Otherwise this breaks for 64-bit
>> architectures like arm64.
>> Fix this by making it clear that it's the hardware register width which
>> matters here in the calculation.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> 
> Acked-by: Chen-Yu Tsai <wens@csie.org>

Thanks a lot!

> Though I don't expect this driver to be used with arm64 chips.

Well, weren't we toying with the idea of using this for the A64 PRCM
support?

Also the driver is actually pretty generic, and I have (renaming)
patches lying around to make this obvious. This is partly driven by a
side project for some (arm64) SoC support, which can happily use that
driver to tackle its device reset support.

So as this is an obvious bug, I'd rather see this fixed now.

Cheers,
Andre.

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH] reset: sunxi: fix for 64-bit compilation
@ 2017-03-08  9:26     ` Andre Przywara
  0 siblings, 0 replies; 8+ messages in thread
From: Andre Przywara @ 2017-03-08  9:26 UTC (permalink / raw)
  To: linux-arm-kernel

Hi,

On 08/03/17 04:28, Chen-Yu Tsai wrote:
> On Mon, Mar 6, 2017 at 9:35 AM, Andre Przywara <andre.przywara@arm.com> wrote:
>> The Allwinner reset controller has 32-bit registers, so translating
>> the reset cell number into a register and bit offset should not use
>> any architecture dependent data size. Otherwise this breaks for 64-bit
>> architectures like arm64.
>> Fix this by making it clear that it's the hardware register width which
>> matters here in the calculation.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> 
> Acked-by: Chen-Yu Tsai <wens@csie.org>

Thanks a lot!

> Though I don't expect this driver to be used with arm64 chips.

Well, weren't we toying with the idea of using this for the A64 PRCM
support?

Also the driver is actually pretty generic, and I have (renaming)
patches lying around to make this obvious. This is partly driven by a
side project for some (arm64) SoC support, which can happily use that
driver to tackle its device reset support.

So as this is an obvious bug, I'd rather see this fixed now.

Cheers,
Andre.

^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH] reset: sunxi: fix for 64-bit compilation
  2017-03-08  9:26     ` Andre Przywara
@ 2017-03-08  9:52       ` Philipp Zabel
  -1 siblings, 0 replies; 8+ messages in thread
From: Philipp Zabel @ 2017-03-08  9:52 UTC (permalink / raw)
  To: Andre Przywara
  Cc: Chen-Yu Tsai, Maxime Ripard, linux-arm-kernel, linux-kernel

On Wed, 2017-03-08 at 09:26 +0000, Andre Przywara wrote:
> Hi,
> 
> On 08/03/17 04:28, Chen-Yu Tsai wrote:
> > On Mon, Mar 6, 2017 at 9:35 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> >> The Allwinner reset controller has 32-bit registers, so translating
> >> the reset cell number into a register and bit offset should not use
> >> any architecture dependent data size. Otherwise this breaks for 64-bit
> >> architectures like arm64.
> >> Fix this by making it clear that it's the hardware register width which
> >> matters here in the calculation.
> >>
> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > 
> > Acked-by: Chen-Yu Tsai <wens@csie.org>
> 
> Thanks a lot!

Applied, thanks.

> > Though I don't expect this driver to be used with arm64 chips.
> 
> Well, weren't we toying with the idea of using this for the A64 PRCM
> support?
> 
> Also the driver is actually pretty generic, and I have (renaming)
> patches lying around to make this obvious.

That is interesting, I have an untested patch that unifies sunxi,
socfpga, and stm32 floating around. I suppose this could be extended to
also cover ath79 and zx2967. I'll dust it off and send it out.

regards
Philipp

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH] reset: sunxi: fix for 64-bit compilation
@ 2017-03-08  9:52       ` Philipp Zabel
  0 siblings, 0 replies; 8+ messages in thread
From: Philipp Zabel @ 2017-03-08  9:52 UTC (permalink / raw)
  To: linux-arm-kernel

On Wed, 2017-03-08 at 09:26 +0000, Andre Przywara wrote:
> Hi,
> 
> On 08/03/17 04:28, Chen-Yu Tsai wrote:
> > On Mon, Mar 6, 2017 at 9:35 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> >> The Allwinner reset controller has 32-bit registers, so translating
> >> the reset cell number into a register and bit offset should not use
> >> any architecture dependent data size. Otherwise this breaks for 64-bit
> >> architectures like arm64.
> >> Fix this by making it clear that it's the hardware register width which
> >> matters here in the calculation.
> >>
> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > 
> > Acked-by: Chen-Yu Tsai <wens@csie.org>
> 
> Thanks a lot!

Applied, thanks.

> > Though I don't expect this driver to be used with arm64 chips.
> 
> Well, weren't we toying with the idea of using this for the A64 PRCM
> support?
> 
> Also the driver is actually pretty generic, and I have (renaming)
> patches lying around to make this obvious.

That is interesting, I have an untested patch that unifies sunxi,
socfpga, and stm32 floating around. I suppose this could be extended to
also cover ath79 and zx2967. I'll dust it off and send it out.

regards
Philipp

^ permalink raw reply	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-03-08 10:52 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-06  1:35 [PATCH] reset: sunxi: fix for 64-bit compilation Andre Przywara
2017-03-06  1:35 ` Andre Przywara
2017-03-08  4:28 ` Chen-Yu Tsai
2017-03-08  4:28   ` Chen-Yu Tsai
2017-03-08  9:26   ` Andre Przywara
2017-03-08  9:26     ` Andre Przywara
2017-03-08  9:52     ` Philipp Zabel
2017-03-08  9:52       ` Philipp Zabel

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