* [PATCH V3 00/10] clk: add imx7ulp clk support
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-arm-kernel, sboyd, mturquette, shawnguo,
Anson.Huang, ping.bai, linux-imx, fabio.estevam, Dong Aisheng
This patch series intends to add imx7ulp clk support.
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
Note: this series only adds A7 clock domain support as M4 clock
domain will be handled by M4 seperately.
Change Log:
v2->v3:
* Patch 1 changed on: 1) split normal and gate ops 2) fix the possible racy
Others no changes.
v1->v2:
* add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
* use clk_hw apis to register clocks
* use of_clk_add_hw_provider
* split the clocks register process into two parts: early part for possible
timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for
the left normal peripheral clocks registered by a platform driver.
Dong Aisheng (10):
clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
clk: imx: add pllv4 support
clk: imx: add pfdv2 support
clk: imx: add composite clk support
dt-bindings: clock: add imx7ulp clock binding doc
clk: imx: make mux parent strings const
clk: imx: implement new clk_hw based APIs
clk: imx: add imx7ulp clk driver
add imx7ulp support
.../devicetree/bindings/clock/imx7ulp-clock.txt | 62 ++++++
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/imx7ulp-evk.dts | 87 ++++++++
arch/arm/boot/dts/imx7ulp.dtsi | 202 ++++++++++++++++++
arch/arm/configs/imx_v6_v7_defconfig | 16 +-
arch/arm/mach-imx/Kconfig | 9 +
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/cpu.c | 3 +
arch/arm/mach-imx/mach-imx7ulp.c | 37 ++++
arch/arm/mach-imx/mxc.h | 1 +
arch/arm/mach-imx/pm-imx7ulp.c | 32 +++
drivers/clk/clk-divider.c | 152 ++++++++++++++
drivers/clk/clk-fractional-divider.c | 10 +
drivers/clk/imx/Makefile | 6 +-
drivers/clk/imx/clk-busy.c | 2 +-
drivers/clk/imx/clk-composite.c | 90 ++++++++
drivers/clk/imx/clk-fixup-mux.c | 2 +-
drivers/clk/imx/clk-imx7ulp.c | 232 +++++++++++++++++++++
drivers/clk/imx/clk-pfdv2.c | 207 ++++++++++++++++++
drivers/clk/imx/clk-pllv4.c | 188 +++++++++++++++++
drivers/clk/imx/clk.c | 22 ++
drivers/clk/imx/clk.h | 92 +++++++-
include/dt-bindings/clock/imx7ulp-clock.h | 108 ++++++++++
include/linux/clk-provider.h | 17 ++
25 files changed, 1561 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c
create mode 100644 drivers/clk/imx/clk-composite.c
create mode 100644 drivers/clk/imx/clk-imx7ulp.c
create mode 100644 drivers/clk/imx/clk-pfdv2.c
create mode 100644 drivers/clk/imx/clk-pllv4.c
create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h
--
2.7.4
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH V3 00/10] clk: add imx7ulp clk support
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: Dong Aisheng, ping.bai, Anson.Huang, mturquette, sboyd,
linux-kernel, linux-imx, fabio.estevam, shawnguo,
linux-arm-kernel
This patch series intends to add imx7ulp clk support.
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
Note: this series only adds A7 clock domain support as M4 clock
domain will be handled by M4 seperately.
Change Log:
v2->v3:
* Patch 1 changed on: 1) split normal and gate ops 2) fix the possible racy
Others no changes.
v1->v2:
* add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
* use clk_hw apis to register clocks
* use of_clk_add_hw_provider
* split the clocks register process into two parts: early part for possible
timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for
the left normal peripheral clocks registered by a platform driver.
Dong Aisheng (10):
clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
clk: imx: add pllv4 support
clk: imx: add pfdv2 support
clk: imx: add composite clk support
dt-bindings: clock: add imx7ulp clock binding doc
clk: imx: make mux parent strings const
clk: imx: implement new clk_hw based APIs
clk: imx: add imx7ulp clk driver
add imx7ulp support
.../devicetree/bindings/clock/imx7ulp-clock.txt | 62 ++++++
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/imx7ulp-evk.dts | 87 ++++++++
arch/arm/boot/dts/imx7ulp.dtsi | 202 ++++++++++++++++++
arch/arm/configs/imx_v6_v7_defconfig | 16 +-
arch/arm/mach-imx/Kconfig | 9 +
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/cpu.c | 3 +
arch/arm/mach-imx/mach-imx7ulp.c | 37 ++++
arch/arm/mach-imx/mxc.h | 1 +
arch/arm/mach-imx/pm-imx7ulp.c | 32 +++
drivers/clk/clk-divider.c | 152 ++++++++++++++
drivers/clk/clk-fractional-divider.c | 10 +
drivers/clk/imx/Makefile | 6 +-
drivers/clk/imx/clk-busy.c | 2 +-
drivers/clk/imx/clk-composite.c | 90 ++++++++
drivers/clk/imx/clk-fixup-mux.c | 2 +-
drivers/clk/imx/clk-imx7ulp.c | 232 +++++++++++++++++++++
drivers/clk/imx/clk-pfdv2.c | 207 ++++++++++++++++++
drivers/clk/imx/clk-pllv4.c | 188 +++++++++++++++++
drivers/clk/imx/clk.c | 22 ++
drivers/clk/imx/clk.h | 92 +++++++-
include/dt-bindings/clock/imx7ulp-clock.h | 108 ++++++++++
include/linux/clk-provider.h | 17 ++
25 files changed, 1561 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c
create mode 100644 drivers/clk/imx/clk-composite.c
create mode 100644 drivers/clk/imx/clk-imx7ulp.c
create mode 100644 drivers/clk/imx/clk-pfdv2.c
create mode 100644 drivers/clk/imx/clk-pllv4.c
create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH V3 00/10] clk: add imx7ulp clk support
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-arm-kernel
This patch series intends to add imx7ulp clk support.
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
Note: this series only adds A7 clock domain support as M4 clock
domain will be handled by M4 seperately.
Change Log:
v2->v3:
* Patch 1 changed on: 1) split normal and gate ops 2) fix the possible racy
Others no changes.
v1->v2:
* add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
* use clk_hw apis to register clocks
* use of_clk_add_hw_provider
* split the clocks register process into two parts: early part for possible
timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for
the left normal peripheral clocks registered by a platform driver.
Dong Aisheng (10):
clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
clk: imx: add pllv4 support
clk: imx: add pfdv2 support
clk: imx: add composite clk support
dt-bindings: clock: add imx7ulp clock binding doc
clk: imx: make mux parent strings const
clk: imx: implement new clk_hw based APIs
clk: imx: add imx7ulp clk driver
add imx7ulp support
.../devicetree/bindings/clock/imx7ulp-clock.txt | 62 ++++++
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/imx7ulp-evk.dts | 87 ++++++++
arch/arm/boot/dts/imx7ulp.dtsi | 202 ++++++++++++++++++
arch/arm/configs/imx_v6_v7_defconfig | 16 +-
arch/arm/mach-imx/Kconfig | 9 +
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/cpu.c | 3 +
arch/arm/mach-imx/mach-imx7ulp.c | 37 ++++
arch/arm/mach-imx/mxc.h | 1 +
arch/arm/mach-imx/pm-imx7ulp.c | 32 +++
drivers/clk/clk-divider.c | 152 ++++++++++++++
drivers/clk/clk-fractional-divider.c | 10 +
drivers/clk/imx/Makefile | 6 +-
drivers/clk/imx/clk-busy.c | 2 +-
drivers/clk/imx/clk-composite.c | 90 ++++++++
drivers/clk/imx/clk-fixup-mux.c | 2 +-
drivers/clk/imx/clk-imx7ulp.c | 232 +++++++++++++++++++++
drivers/clk/imx/clk-pfdv2.c | 207 ++++++++++++++++++
drivers/clk/imx/clk-pllv4.c | 188 +++++++++++++++++
drivers/clk/imx/clk.c | 22 ++
drivers/clk/imx/clk.h | 92 +++++++-
include/dt-bindings/clock/imx7ulp-clock.h | 108 ++++++++++
include/linux/clk-provider.h | 17 ++
25 files changed, 1561 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c
create mode 100644 drivers/clk/imx/clk-composite.c
create mode 100644 drivers/clk/imx/clk-imx7ulp.c
create mode 100644 drivers/clk/imx/clk-pfdv2.c
create mode 100644 drivers/clk/imx/clk-pllv4.c
create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h
--
2.7.4
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH V3 01/10] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
2018-01-19 13:11 ` Dong Aisheng
@ 2018-01-19 13:11 ` Dong Aisheng
-1 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-arm-kernel, sboyd, mturquette, shawnguo,
Anson.Huang, ping.bai, linux-imx, fabio.estevam, Dong Aisheng
For dividers with zero indicating clock is disabled, instead of giving a
warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not
set" in exist code, we'd like to introduce enable/disable function for it.
e.g.
000b - Clock disabled
001b - Divide by 1
010b - Divide by 2
...
Set rate when the clk is disabled will cache the rate request and only
when the clk is enabled will the driver actually program the hardware to
have the requested divider value. Similarly, when the clk is disabled we'll
write a 0 there, but when the clk is enabled we'll restore whatever rate
(divider) was chosen last.
It does mean that recalc rate will be sort of odd, because when the clk is
off it will return 0, and when the clk is on it will return the right rate.
So to make things work, we'll need to return the cached rate in recalc rate
when the clk is off and read the hardware when the clk is on.
NOTE for the default off divider, the recalc rate will still return 0 as
there's still no proper preset rate. Enable such divider will give user
a reminder error message.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* split normal and gate ops
* fix the possible racy
v1->v2:
* add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
---
drivers/clk/clk-divider.c | 152 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk-provider.h | 9 +++
2 files changed, 161 insertions(+)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index b49942b..6143895 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -124,6 +124,9 @@ unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
div = _get_div(table, val, flags, width);
if (!div) {
+ if (flags & CLK_DIVIDER_ZERO_GATE)
+ return 0;
+
WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
clk_hw_get_name(hw));
@@ -147,6 +150,34 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
divider->flags, divider->width);
}
+static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ unsigned int val;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ if (!clk_hw_is_enabled(hw)) {
+ val = divider->cached_val;
+ } else {
+ val = clk_readl(divider->reg) >> divider->shift;
+ val &= div_mask(divider->width);
+ }
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ return divider_recalc_rate(hw, parent_rate, val, divider->table,
+ divider->flags, divider->width);
+}
+
static bool _is_valid_table_div(const struct clk_div_table *table,
unsigned int div)
{
@@ -415,6 +446,108 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
+static int clk_divider_gate_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ int value;
+ u32 val;
+
+ value = divider_get_val(rate, parent_rate, divider->table,
+ divider->width, divider->flags);
+ if (value < 0)
+ return value;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ if (clk_hw_is_enabled(hw)) {
+ if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
+ val = div_mask(divider->width) << (divider->shift + 16);
+ } else {
+ val = clk_readl(divider->reg);
+ val &= ~(div_mask(divider->width) << divider->shift);
+ }
+ val |= (u32)value << divider->shift;
+ clk_writel(val, divider->reg);
+ } else {
+ divider->cached_val = value;
+ }
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ return 0;
+}
+
+static int clk_divider_enable(struct clk_hw *hw)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ u32 val;
+
+ if (!divider->cached_val) {
+ pr_err("%s: no valid preset rate\n", clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ /* restore div val */
+ val = clk_readl(divider->reg);
+ val |= divider->cached_val << divider->shift;
+ clk_writel(val, divider->reg);
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ return 0;
+}
+
+static void clk_divider_disable(struct clk_hw *hw)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ u32 val;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ /* store the current div val */
+ val = clk_readl(divider->reg) >> divider->shift;
+ val &= div_mask(divider->width);
+ divider->cached_val = val;
+ clk_writel(0, divider->reg);
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+}
+
+static int clk_divider_is_enabled(struct clk_hw *hw)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ u32 val;
+
+ val = clk_readl(divider->reg) >> divider->shift;
+ val &= div_mask(divider->width);
+
+ return val ? 1 : 0;
+}
+
const struct clk_ops clk_divider_ops = {
.recalc_rate = clk_divider_recalc_rate,
.round_rate = clk_divider_round_rate,
@@ -422,6 +555,16 @@ const struct clk_ops clk_divider_ops = {
};
EXPORT_SYMBOL_GPL(clk_divider_ops);
+const struct clk_ops clk_divider_gate_ops = {
+ .recalc_rate = clk_divider_gate_recalc_rate,
+ .round_rate = clk_divider_round_rate,
+ .set_rate = clk_divider_gate_set_rate,
+ .enable = clk_divider_enable,
+ .disable = clk_divider_disable,
+ .is_enabled = clk_divider_is_enabled,
+};
+EXPORT_SYMBOL_GPL(clk_divider_gate_ops);
+
const struct clk_ops clk_divider_ro_ops = {
.recalc_rate = clk_divider_recalc_rate,
.round_rate = clk_divider_round_rate,
@@ -437,6 +580,7 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name,
struct clk_divider *div;
struct clk_hw *hw;
struct clk_init_data init;
+ u32 val;
int ret;
if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
@@ -454,6 +598,8 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name,
init.name = name;
if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
init.ops = &clk_divider_ro_ops;
+ else if (clk_divider_flags & CLK_DIVIDER_ZERO_GATE)
+ init.ops = &clk_divider_gate_ops;
else
init.ops = &clk_divider_ops;
init.flags = flags | CLK_IS_BASIC;
@@ -469,6 +615,12 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name,
div->hw.init = &init;
div->table = table;
+ if (div->flags & CLK_DIVIDER_ZERO_GATE) {
+ val = clk_readl(reg) >> shift;
+ val &= div_mask(width);
+ div->cached_val = val;
+ }
+
/* register the clock */
hw = &div->hw;
ret = clk_hw_register(dev, hw);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index f711be6..68ccd36 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -360,6 +360,7 @@ struct clk_div_table {
* @shift: shift to the divider bit field
* @width: width of the divider bit field
* @table: array of value/divider pairs, last entry should have div = 0
+ * @cached_val: cached div hw value used for CLK_DIVIDER_ZERO_GATE
* @lock: register lock
*
* Clock with an adjustable divider affecting its output frequency. Implements
@@ -388,6 +389,12 @@ struct clk_div_table {
* CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
* except when the value read from the register is zero, the divisor is
* 2^width of the field.
+ * CLK_DIVIDER_ZERO_GATE - For dividers which are like CLK_DIVIDER_ONE_BASED
+ * when the value read from the register is zero, it means the divisor
+ * is gated. For this case, the cached_val will be used to store the
+ * intermediate div for the normal rate operation, like set_rate/get_rate/
+ * recalc_rate. When the divider is ungated, the driver will actually
+ * program the hardware to have the requested divider value.
*/
struct clk_divider {
struct clk_hw hw;
@@ -396,6 +403,7 @@ struct clk_divider {
u8 width;
u8 flags;
const struct clk_div_table *table;
+ u32 cached_val;
spinlock_t *lock;
};
@@ -408,6 +416,7 @@ struct clk_divider {
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
#define CLK_DIVIDER_READ_ONLY BIT(5)
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
+#define CLK_DIVIDER_ZERO_GATE BIT(7)
extern const struct clk_ops clk_divider_ops;
extern const struct clk_ops clk_divider_ro_ops;
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 01/10] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-arm-kernel
For dividers with zero indicating clock is disabled, instead of giving a
warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not
set" in exist code, we'd like to introduce enable/disable function for it.
e.g.
000b - Clock disabled
001b - Divide by 1
010b - Divide by 2
...
Set rate when the clk is disabled will cache the rate request and only
when the clk is enabled will the driver actually program the hardware to
have the requested divider value. Similarly, when the clk is disabled we'll
write a 0 there, but when the clk is enabled we'll restore whatever rate
(divider) was chosen last.
It does mean that recalc rate will be sort of odd, because when the clk is
off it will return 0, and when the clk is on it will return the right rate.
So to make things work, we'll need to return the cached rate in recalc rate
when the clk is off and read the hardware when the clk is on.
NOTE for the default off divider, the recalc rate will still return 0 as
there's still no proper preset rate. Enable such divider will give user
a reminder error message.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* split normal and gate ops
* fix the possible racy
v1->v2:
* add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
---
drivers/clk/clk-divider.c | 152 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk-provider.h | 9 +++
2 files changed, 161 insertions(+)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index b49942b..6143895 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -124,6 +124,9 @@ unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
div = _get_div(table, val, flags, width);
if (!div) {
+ if (flags & CLK_DIVIDER_ZERO_GATE)
+ return 0;
+
WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
clk_hw_get_name(hw));
@@ -147,6 +150,34 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
divider->flags, divider->width);
}
+static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ unsigned int val;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ if (!clk_hw_is_enabled(hw)) {
+ val = divider->cached_val;
+ } else {
+ val = clk_readl(divider->reg) >> divider->shift;
+ val &= div_mask(divider->width);
+ }
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ return divider_recalc_rate(hw, parent_rate, val, divider->table,
+ divider->flags, divider->width);
+}
+
static bool _is_valid_table_div(const struct clk_div_table *table,
unsigned int div)
{
@@ -415,6 +446,108 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
+static int clk_divider_gate_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ int value;
+ u32 val;
+
+ value = divider_get_val(rate, parent_rate, divider->table,
+ divider->width, divider->flags);
+ if (value < 0)
+ return value;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ if (clk_hw_is_enabled(hw)) {
+ if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
+ val = div_mask(divider->width) << (divider->shift + 16);
+ } else {
+ val = clk_readl(divider->reg);
+ val &= ~(div_mask(divider->width) << divider->shift);
+ }
+ val |= (u32)value << divider->shift;
+ clk_writel(val, divider->reg);
+ } else {
+ divider->cached_val = value;
+ }
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ return 0;
+}
+
+static int clk_divider_enable(struct clk_hw *hw)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ u32 val;
+
+ if (!divider->cached_val) {
+ pr_err("%s: no valid preset rate\n", clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ /* restore div val */
+ val = clk_readl(divider->reg);
+ val |= divider->cached_val << divider->shift;
+ clk_writel(val, divider->reg);
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ return 0;
+}
+
+static void clk_divider_disable(struct clk_hw *hw)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ u32 val;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ /* store the current div val */
+ val = clk_readl(divider->reg) >> divider->shift;
+ val &= div_mask(divider->width);
+ divider->cached_val = val;
+ clk_writel(0, divider->reg);
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+}
+
+static int clk_divider_is_enabled(struct clk_hw *hw)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ u32 val;
+
+ val = clk_readl(divider->reg) >> divider->shift;
+ val &= div_mask(divider->width);
+
+ return val ? 1 : 0;
+}
+
const struct clk_ops clk_divider_ops = {
.recalc_rate = clk_divider_recalc_rate,
.round_rate = clk_divider_round_rate,
@@ -422,6 +555,16 @@ const struct clk_ops clk_divider_ops = {
};
EXPORT_SYMBOL_GPL(clk_divider_ops);
+const struct clk_ops clk_divider_gate_ops = {
+ .recalc_rate = clk_divider_gate_recalc_rate,
+ .round_rate = clk_divider_round_rate,
+ .set_rate = clk_divider_gate_set_rate,
+ .enable = clk_divider_enable,
+ .disable = clk_divider_disable,
+ .is_enabled = clk_divider_is_enabled,
+};
+EXPORT_SYMBOL_GPL(clk_divider_gate_ops);
+
const struct clk_ops clk_divider_ro_ops = {
.recalc_rate = clk_divider_recalc_rate,
.round_rate = clk_divider_round_rate,
@@ -437,6 +580,7 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name,
struct clk_divider *div;
struct clk_hw *hw;
struct clk_init_data init;
+ u32 val;
int ret;
if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
@@ -454,6 +598,8 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name,
init.name = name;
if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
init.ops = &clk_divider_ro_ops;
+ else if (clk_divider_flags & CLK_DIVIDER_ZERO_GATE)
+ init.ops = &clk_divider_gate_ops;
else
init.ops = &clk_divider_ops;
init.flags = flags | CLK_IS_BASIC;
@@ -469,6 +615,12 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name,
div->hw.init = &init;
div->table = table;
+ if (div->flags & CLK_DIVIDER_ZERO_GATE) {
+ val = clk_readl(reg) >> shift;
+ val &= div_mask(width);
+ div->cached_val = val;
+ }
+
/* register the clock */
hw = &div->hw;
ret = clk_hw_register(dev, hw);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index f711be6..68ccd36 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -360,6 +360,7 @@ struct clk_div_table {
* @shift: shift to the divider bit field
* @width: width of the divider bit field
* @table: array of value/divider pairs, last entry should have div = 0
+ * @cached_val: cached div hw value used for CLK_DIVIDER_ZERO_GATE
* @lock: register lock
*
* Clock with an adjustable divider affecting its output frequency. Implements
@@ -388,6 +389,12 @@ struct clk_div_table {
* CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
* except when the value read from the register is zero, the divisor is
* 2^width of the field.
+ * CLK_DIVIDER_ZERO_GATE - For dividers which are like CLK_DIVIDER_ONE_BASED
+ * when the value read from the register is zero, it means the divisor
+ * is gated. For this case, the cached_val will be used to store the
+ * intermediate div for the normal rate operation, like set_rate/get_rate/
+ * recalc_rate. When the divider is ungated, the driver will actually
+ * program the hardware to have the requested divider value.
*/
struct clk_divider {
struct clk_hw hw;
@@ -396,6 +403,7 @@ struct clk_divider {
u8 width;
u8 flags;
const struct clk_div_table *table;
+ u32 cached_val;
spinlock_t *lock;
};
@@ -408,6 +416,7 @@ struct clk_divider {
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
#define CLK_DIVIDER_READ_ONLY BIT(5)
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
+#define CLK_DIVIDER_ZERO_GATE BIT(7)
extern const struct clk_ops clk_divider_ops;
extern const struct clk_ops clk_divider_ro_ops;
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 02/10] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
2018-01-19 13:11 ` Dong Aisheng
@ 2018-01-19 13:11 ` Dong Aisheng
-1 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-arm-kernel, sboyd, mturquette, shawnguo,
Anson.Huang, ping.bai, linux-imx, fabio.estevam, Dong Aisheng
Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and
denominator value in register are start from 0.
This can be used to support frac dividers like below:
Divider output clock = Divider input clock x [(frac +1) / (div +1)]
where frac/div in register is:
000b - Divide by 1.
001b - Divide by 2.
010b - Divide by 3.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* improve comments suggested by Stephen
---
drivers/clk/clk-fractional-divider.c | 10 ++++++++++
include/linux/clk-provider.h | 8 ++++++++
2 files changed, 18 insertions(+)
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index fdf625f..7ccde6b 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -40,6 +40,11 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
m = (val & fd->mmask) >> fd->mshift;
n = (val & fd->nmask) >> fd->nshift;
+ if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
+ m++;
+ n++;
+ }
+
if (!n || !m)
return parent_rate;
@@ -103,6 +108,11 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
&m, &n);
+ if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
+ m--;
+ n--;
+ }
+
if (fd->lock)
spin_lock_irqsave(fd->lock, flags);
else
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 68ccd36..cb55b67 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -566,6 +566,12 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
* @lock: register lock
*
* Clock with adjustable fractional divider affecting its output frequency.
+ *
+ * Flags:
+ * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
+ * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
+ * is set then the numerator and denominator are both the value read
+ * plus one.
*/
struct clk_fractional_divider {
struct clk_hw hw;
@@ -585,6 +591,8 @@ struct clk_fractional_divider {
#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
+#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
+
extern const struct clk_ops clk_fractional_divider_ops;
struct clk *clk_register_fractional_divider(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 02/10] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-arm-kernel
Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and
denominator value in register are start from 0.
This can be used to support frac dividers like below:
Divider output clock = Divider input clock x [(frac +1) / (div +1)]
where frac/div in register is:
000b - Divide by 1.
001b - Divide by 2.
010b - Divide by 3.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* improve comments suggested by Stephen
---
drivers/clk/clk-fractional-divider.c | 10 ++++++++++
include/linux/clk-provider.h | 8 ++++++++
2 files changed, 18 insertions(+)
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index fdf625f..7ccde6b 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -40,6 +40,11 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
m = (val & fd->mmask) >> fd->mshift;
n = (val & fd->nmask) >> fd->nshift;
+ if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
+ m++;
+ n++;
+ }
+
if (!n || !m)
return parent_rate;
@@ -103,6 +108,11 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
&m, &n);
+ if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
+ m--;
+ n--;
+ }
+
if (fd->lock)
spin_lock_irqsave(fd->lock, flags);
else
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 68ccd36..cb55b67 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -566,6 +566,12 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
* @lock: register lock
*
* Clock with adjustable fractional divider affecting its output frequency.
+ *
+ * Flags:
+ * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
+ * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
+ * is set then the numerator and denominator are both the value read
+ * plus one.
*/
struct clk_fractional_divider {
struct clk_hw hw;
@@ -585,6 +591,8 @@ struct clk_fractional_divider {
#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
+#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
+
extern const struct clk_ops clk_fractional_divider_ops;
struct clk *clk_register_fractional_divider(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 03/10] clk: imx: add pllv4 support
2018-01-19 13:11 ` Dong Aisheng
@ 2018-01-19 13:11 ` Dong Aisheng
-1 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-arm-kernel, sboyd, mturquette, shawnguo,
Anson.Huang, ping.bai, linux-imx, fabio.estevam, Dong Aisheng
pllv4 is designed for System Clock Generation (SCG) module observed
in IMX ULP SoC series. e.g. i.MX7ULP.
The SCG modules generates clock used to derive processor, system,
peripheral bus and external memory interface clocks while this patch
intends to support the PLL part.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* remove clk_pllv4_is_enabled() check in set_rate, instead it will
be handled by core later.
* use readl_poll_timeout
* use clk_hw_register instead of clk_register
* other minor changes
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-pllv4.c | 188 ++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk.h | 3 +
3 files changed, 192 insertions(+)
create mode 100644 drivers/clk/imx/clk-pllv4.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index f91f2b2..2f00b03 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -11,6 +11,7 @@ obj-y += \
clk-pllv1.o \
clk-pllv2.o \
clk-pllv3.o \
+ clk-pllv4.o \
clk-pfd.o
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c
new file mode 100644
index 0000000..47e4d1c
--- /dev/null
+++ b/drivers/clk/imx/clk-pllv4.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * Author: Dong Aisheng <aisheng.dong@nxp.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <linux/slab.h>
+
+/* PLL Control Status Register (xPLLCSR) */
+#define PLL_CSR_OFFSET 0x0
+#define PLL_VLD BIT(24)
+#define PLL_EN BIT(0)
+
+/* PLL Configuration Register (xPLLCFG) */
+#define PLL_CFG_OFFSET 0x08
+#define BP_PLL_MULT 16
+#define BM_PLL_MULT (0x7f << 16)
+
+/* PLL Numerator Register (xPLLNUM) */
+#define PLL_NUM_OFFSET 0x10
+
+/* PLL Denominator Register (xPLLDENOM) */
+#define PLL_DENOM_OFFSET 0x14
+
+struct clk_pllv4 {
+ struct clk_hw hw;
+ void __iomem *base;
+};
+
+/* Valid PLL MULT Table */
+static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16};
+
+#define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw)
+
+#define LOCK_TIMEOUT_US USEC_PER_MSEC
+
+static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll)
+{
+ u32 csr;
+
+ return readl_poll_timeout(pll->base + PLL_CSR_OFFSET,
+ csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US);
+}
+
+static int clk_pllv4_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ if (readl_relaxed(pll->base) & PLL_EN)
+ return 1;
+
+ return 0;
+}
+
+static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+ u32 div;
+
+ div = readl_relaxed(pll->base + PLL_CFG_OFFSET);
+ div &= BM_PLL_MULT;
+ div >>= BP_PLL_MULT;
+
+ return parent_rate * div;
+}
+
+static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long parent_rate = *prate;
+ unsigned long round_rate, i;
+
+ for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
+ round_rate = parent_rate * pllv4_mult_table[i];
+ if (rate >= round_rate)
+ return round_rate;
+ }
+
+ return round_rate;
+}
+
+static bool clk_pllv4_is_valid_mult(unsigned int mult)
+{
+ int i;
+
+ /* check if mult is in valid MULT table */
+ for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
+ if (pllv4_mult_table[i] == mult)
+ return true;
+ }
+
+ return false;
+}
+
+static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+ u32 val, mult;
+
+ mult = rate / parent_rate;
+
+ if (clk_pllv4_is_valid_mult(mult))
+ return -EINVAL;
+
+ val = readl_relaxed(pll->base + PLL_CFG_OFFSET);
+ val &= ~BM_PLL_MULT;
+ val |= mult << BP_PLL_MULT;
+ writel_relaxed(val, pll->base + PLL_CFG_OFFSET);
+
+ return 0;
+}
+
+static int clk_pllv4_enable(struct clk_hw *hw)
+{
+ u32 val;
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ val = readl_relaxed(pll->base);
+ val |= PLL_EN;
+ writel_relaxed(val, pll->base);
+
+ return clk_pllv4_wait_lock(pll);
+}
+
+static void clk_pllv4_disable(struct clk_hw *hw)
+{
+ u32 val;
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ val = readl_relaxed(pll->base);
+ val &= ~PLL_EN;
+ writel_relaxed(val, pll->base);
+}
+
+static const struct clk_ops clk_pllv4_ops = {
+ .recalc_rate = clk_pllv4_recalc_rate,
+ .round_rate = clk_pllv4_round_rate,
+ .set_rate = clk_pllv4_set_rate,
+ .enable = clk_pllv4_enable,
+ .disable = clk_pllv4_disable,
+ .is_enabled = clk_pllv4_is_enabled,
+};
+
+struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name,
+ void __iomem *base)
+{
+ struct clk_pllv4 *pll;
+ struct clk_hw *hw;
+ struct clk_init_data init;
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->base = base;
+
+ init.name = name;
+ init.ops = &clk_pllv4_ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ init.flags = CLK_SET_RATE_GATE;
+
+ pll->hw.init = &init;
+
+ hw = &pll->hw;
+ ret = clk_hw_register(NULL, hw);
+ if (ret) {
+ kfree(pll);
+ hw = ERR_PTR(ret);
+ }
+
+ return hw;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index d69c4bb..52f7c9d 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -42,6 +42,9 @@ enum imx_pllv3_type {
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent_name, void __iomem *base, u32 div_mask);
+struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name,
+ void __iomem *base);
+
struct clk *clk_register_gate2(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx, u8 cgr_val,
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 03/10] clk: imx: add pllv4 support
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-arm-kernel
pllv4 is designed for System Clock Generation (SCG) module observed
in IMX ULP SoC series. e.g. i.MX7ULP.
The SCG modules generates clock used to derive processor, system,
peripheral bus and external memory interface clocks while this patch
intends to support the PLL part.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* remove clk_pllv4_is_enabled() check in set_rate, instead it will
be handled by core later.
* use readl_poll_timeout
* use clk_hw_register instead of clk_register
* other minor changes
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-pllv4.c | 188 ++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk.h | 3 +
3 files changed, 192 insertions(+)
create mode 100644 drivers/clk/imx/clk-pllv4.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index f91f2b2..2f00b03 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -11,6 +11,7 @@ obj-y += \
clk-pllv1.o \
clk-pllv2.o \
clk-pllv3.o \
+ clk-pllv4.o \
clk-pfd.o
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c
new file mode 100644
index 0000000..47e4d1c
--- /dev/null
+++ b/drivers/clk/imx/clk-pllv4.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * Author: Dong Aisheng <aisheng.dong@nxp.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <linux/slab.h>
+
+/* PLL Control Status Register (xPLLCSR) */
+#define PLL_CSR_OFFSET 0x0
+#define PLL_VLD BIT(24)
+#define PLL_EN BIT(0)
+
+/* PLL Configuration Register (xPLLCFG) */
+#define PLL_CFG_OFFSET 0x08
+#define BP_PLL_MULT 16
+#define BM_PLL_MULT (0x7f << 16)
+
+/* PLL Numerator Register (xPLLNUM) */
+#define PLL_NUM_OFFSET 0x10
+
+/* PLL Denominator Register (xPLLDENOM) */
+#define PLL_DENOM_OFFSET 0x14
+
+struct clk_pllv4 {
+ struct clk_hw hw;
+ void __iomem *base;
+};
+
+/* Valid PLL MULT Table */
+static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16};
+
+#define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw)
+
+#define LOCK_TIMEOUT_US USEC_PER_MSEC
+
+static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll)
+{
+ u32 csr;
+
+ return readl_poll_timeout(pll->base + PLL_CSR_OFFSET,
+ csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US);
+}
+
+static int clk_pllv4_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ if (readl_relaxed(pll->base) & PLL_EN)
+ return 1;
+
+ return 0;
+}
+
+static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+ u32 div;
+
+ div = readl_relaxed(pll->base + PLL_CFG_OFFSET);
+ div &= BM_PLL_MULT;
+ div >>= BP_PLL_MULT;
+
+ return parent_rate * div;
+}
+
+static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long parent_rate = *prate;
+ unsigned long round_rate, i;
+
+ for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
+ round_rate = parent_rate * pllv4_mult_table[i];
+ if (rate >= round_rate)
+ return round_rate;
+ }
+
+ return round_rate;
+}
+
+static bool clk_pllv4_is_valid_mult(unsigned int mult)
+{
+ int i;
+
+ /* check if mult is in valid MULT table */
+ for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
+ if (pllv4_mult_table[i] == mult)
+ return true;
+ }
+
+ return false;
+}
+
+static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+ u32 val, mult;
+
+ mult = rate / parent_rate;
+
+ if (clk_pllv4_is_valid_mult(mult))
+ return -EINVAL;
+
+ val = readl_relaxed(pll->base + PLL_CFG_OFFSET);
+ val &= ~BM_PLL_MULT;
+ val |= mult << BP_PLL_MULT;
+ writel_relaxed(val, pll->base + PLL_CFG_OFFSET);
+
+ return 0;
+}
+
+static int clk_pllv4_enable(struct clk_hw *hw)
+{
+ u32 val;
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ val = readl_relaxed(pll->base);
+ val |= PLL_EN;
+ writel_relaxed(val, pll->base);
+
+ return clk_pllv4_wait_lock(pll);
+}
+
+static void clk_pllv4_disable(struct clk_hw *hw)
+{
+ u32 val;
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ val = readl_relaxed(pll->base);
+ val &= ~PLL_EN;
+ writel_relaxed(val, pll->base);
+}
+
+static const struct clk_ops clk_pllv4_ops = {
+ .recalc_rate = clk_pllv4_recalc_rate,
+ .round_rate = clk_pllv4_round_rate,
+ .set_rate = clk_pllv4_set_rate,
+ .enable = clk_pllv4_enable,
+ .disable = clk_pllv4_disable,
+ .is_enabled = clk_pllv4_is_enabled,
+};
+
+struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name,
+ void __iomem *base)
+{
+ struct clk_pllv4 *pll;
+ struct clk_hw *hw;
+ struct clk_init_data init;
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->base = base;
+
+ init.name = name;
+ init.ops = &clk_pllv4_ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ init.flags = CLK_SET_RATE_GATE;
+
+ pll->hw.init = &init;
+
+ hw = &pll->hw;
+ ret = clk_hw_register(NULL, hw);
+ if (ret) {
+ kfree(pll);
+ hw = ERR_PTR(ret);
+ }
+
+ return hw;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index d69c4bb..52f7c9d 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -42,6 +42,9 @@ enum imx_pllv3_type {
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent_name, void __iomem *base, u32 div_mask);
+struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name,
+ void __iomem *base);
+
struct clk *clk_register_gate2(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx, u8 cgr_val,
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 04/10] clk: imx: add pfdv2 support
2018-01-19 13:11 ` Dong Aisheng
@ 2018-01-19 13:11 ` Dong Aisheng
-1 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-arm-kernel, sboyd, mturquette, shawnguo,
Anson.Huang, ping.bai, linux-imx, fabio.estevam, Dong Aisheng
The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System
Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP.
NOTE pfdv2 can only be operated when clk is gated.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* change to readl_poll_timeout
* add pfd lock to protect share reg access between rate and enable/disable
operations and multiple pfd instances.
* use clk_hw_register
---
drivers/clk/imx/Makefile | 3 +-
drivers/clk/imx/clk-pfdv2.c | 207 ++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk.h | 3 +
3 files changed, 212 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/imx/clk-pfdv2.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 2f00b03..9c04ae4 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -12,7 +12,8 @@ obj-y += \
clk-pllv2.o \
clk-pllv3.o \
clk-pllv4.o \
- clk-pfd.o
+ clk-pfd.o \
+ clk-pfdv2.o
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
obj-$(CONFIG_SOC_IMX21) += clk-imx21.o
diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c
new file mode 100644
index 0000000..5421bdf
--- /dev/null
+++ b/drivers/clk/imx/clk-pfdv2.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * Author: Dong Aisheng <aisheng.dong@nxp.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <linux/slab.h>
+
+/**
+ * struct clk_pfdv2 - IMX PFD clock
+ * @clk_hw: clock source
+ * @reg: PFD register address
+ * @gate_bit: Gate bit offset
+ * @vld_bit: Valid bit offset
+ * @frac_off: PLL Fractional Divider offset
+ */
+
+struct clk_pfdv2 {
+ struct clk_hw hw;
+ void __iomem *reg;
+ u8 gate_bit;
+ u8 vld_bit;
+ u8 frac_off;
+};
+
+#define to_clk_pfdv2(_hw) container_of(_hw, struct clk_pfdv2, hw)
+
+#define CLK_PFDV2_FRAC_MASK 0x3f
+
+#define LOCK_TIMEOUT_US USEC_PER_MSEC
+
+static DEFINE_SPINLOCK(pfd_lock);
+
+static int clk_pfdv2_wait(struct clk_pfdv2 *pfd)
+{
+ u32 val;
+
+ return readl_poll_timeout(pfd->reg, val, val & pfd->vld_bit,
+ 0, LOCK_TIMEOUT_US);
+}
+
+static int clk_pfdv2_enable(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val &= ~pfd->gate_bit;
+ writel_relaxed(val, pfd->reg);
+ spin_unlock_irqrestore(&pfd_lock, flags);
+
+ return clk_pfdv2_wait(pfd);
+}
+
+static void clk_pfdv2_disable(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val |= pfd->gate_bit;
+ writel_relaxed(val, pfd->reg);
+ spin_unlock_irqrestore(&pfd_lock, flags);
+}
+
+static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ u64 tmp = parent_rate;
+ u8 frac;
+
+ frac = (readl_relaxed(pfd->reg) >> pfd->frac_off)
+ & CLK_PFDV2_FRAC_MASK;
+
+ if (!frac) {
+ pr_debug("clk_pfdv2: %s invalid pfd frac value 0\n",
+ clk_hw_get_name(hw));
+ return 0;
+ }
+
+ tmp *= 18;
+ do_div(tmp, frac);
+
+ return tmp;
+}
+
+static long clk_pfdv2_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ u64 tmp = *prate;
+ u8 frac;
+
+ tmp = tmp * 18 + rate / 2;
+ do_div(tmp, rate);
+ frac = tmp;
+
+ if (frac < 12)
+ frac = 12;
+ else if (frac > 35)
+ frac = 35;
+
+ tmp = *prate;
+ tmp *= 18;
+ do_div(tmp, frac);
+
+ return tmp;
+}
+
+static int clk_pfdv2_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+
+ if (readl_relaxed(pfd->reg) & pfd->gate_bit)
+ return 0;
+
+ return 1;
+}
+
+static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u64 tmp = parent_rate;
+ u32 val;
+ u8 frac;
+
+ tmp = tmp * 18 + rate / 2;
+ do_div(tmp, rate);
+ frac = tmp;
+ if (frac < 12)
+ frac = 12;
+ else if (frac > 35)
+ frac = 35;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val &= ~(CLK_PFDV2_FRAC_MASK << pfd->frac_off);
+ val |= frac << pfd->frac_off;
+ writel_relaxed(val, pfd->reg);
+ spin_unlock_irqrestore(&pfd_lock, flags);
+
+ return 0;
+}
+
+static const struct clk_ops clk_pfdv2_ops = {
+ .enable = clk_pfdv2_enable,
+ .disable = clk_pfdv2_disable,
+ .recalc_rate = clk_pfdv2_recalc_rate,
+ .round_rate = clk_pfdv2_round_rate,
+ .set_rate = clk_pfdv2_set_rate,
+ .is_enabled = clk_pfdv2_is_enabled,
+};
+
+struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
+ void __iomem *reg, u8 idx)
+{
+ struct clk_init_data init;
+ struct clk_pfdv2 *pfd;
+ struct clk_hw *hw;
+ int ret;
+
+ WARN_ON(idx > 3);
+
+ pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
+ if (!pfd)
+ return ERR_PTR(-ENOMEM);
+
+ pfd->reg = reg;
+ pfd->gate_bit = 1 << ((idx + 1) * 8 - 1);
+ pfd->vld_bit = pfd->gate_bit - 1;
+ pfd->frac_off = idx * 8;
+
+ init.name = name;
+ init.ops = &clk_pfdv2_ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ init.flags = CLK_SET_RATE_GATE;
+
+ pfd->hw.init = &init;
+
+ hw = &pfd->hw;
+ ret = clk_hw_register(NULL, hw);
+ if (ret) {
+ kfree(pfd);
+ hw = ERR_PTR(ret);
+ }
+
+ return hw;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 52f7c9d..ccd7181 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -60,6 +60,9 @@ struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
struct clk *imx_clk_pfd(const char *name, const char *parent_name,
void __iomem *reg, u8 idx);
+struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
+ void __iomem *reg, u8 idx);
+
struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
void __iomem *reg, u8 shift, u8 width,
void __iomem *busy_reg, u8 busy_shift);
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 04/10] clk: imx: add pfdv2 support
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-arm-kernel
The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System
Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP.
NOTE pfdv2 can only be operated when clk is gated.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* change to readl_poll_timeout
* add pfd lock to protect share reg access between rate and enable/disable
operations and multiple pfd instances.
* use clk_hw_register
---
drivers/clk/imx/Makefile | 3 +-
drivers/clk/imx/clk-pfdv2.c | 207 ++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk.h | 3 +
3 files changed, 212 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/imx/clk-pfdv2.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 2f00b03..9c04ae4 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -12,7 +12,8 @@ obj-y += \
clk-pllv2.o \
clk-pllv3.o \
clk-pllv4.o \
- clk-pfd.o
+ clk-pfd.o \
+ clk-pfdv2.o
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
obj-$(CONFIG_SOC_IMX21) += clk-imx21.o
diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c
new file mode 100644
index 0000000..5421bdf
--- /dev/null
+++ b/drivers/clk/imx/clk-pfdv2.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * Author: Dong Aisheng <aisheng.dong@nxp.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <linux/slab.h>
+
+/**
+ * struct clk_pfdv2 - IMX PFD clock
+ * @clk_hw: clock source
+ * @reg: PFD register address
+ * @gate_bit: Gate bit offset
+ * @vld_bit: Valid bit offset
+ * @frac_off: PLL Fractional Divider offset
+ */
+
+struct clk_pfdv2 {
+ struct clk_hw hw;
+ void __iomem *reg;
+ u8 gate_bit;
+ u8 vld_bit;
+ u8 frac_off;
+};
+
+#define to_clk_pfdv2(_hw) container_of(_hw, struct clk_pfdv2, hw)
+
+#define CLK_PFDV2_FRAC_MASK 0x3f
+
+#define LOCK_TIMEOUT_US USEC_PER_MSEC
+
+static DEFINE_SPINLOCK(pfd_lock);
+
+static int clk_pfdv2_wait(struct clk_pfdv2 *pfd)
+{
+ u32 val;
+
+ return readl_poll_timeout(pfd->reg, val, val & pfd->vld_bit,
+ 0, LOCK_TIMEOUT_US);
+}
+
+static int clk_pfdv2_enable(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val &= ~pfd->gate_bit;
+ writel_relaxed(val, pfd->reg);
+ spin_unlock_irqrestore(&pfd_lock, flags);
+
+ return clk_pfdv2_wait(pfd);
+}
+
+static void clk_pfdv2_disable(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val |= pfd->gate_bit;
+ writel_relaxed(val, pfd->reg);
+ spin_unlock_irqrestore(&pfd_lock, flags);
+}
+
+static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ u64 tmp = parent_rate;
+ u8 frac;
+
+ frac = (readl_relaxed(pfd->reg) >> pfd->frac_off)
+ & CLK_PFDV2_FRAC_MASK;
+
+ if (!frac) {
+ pr_debug("clk_pfdv2: %s invalid pfd frac value 0\n",
+ clk_hw_get_name(hw));
+ return 0;
+ }
+
+ tmp *= 18;
+ do_div(tmp, frac);
+
+ return tmp;
+}
+
+static long clk_pfdv2_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ u64 tmp = *prate;
+ u8 frac;
+
+ tmp = tmp * 18 + rate / 2;
+ do_div(tmp, rate);
+ frac = tmp;
+
+ if (frac < 12)
+ frac = 12;
+ else if (frac > 35)
+ frac = 35;
+
+ tmp = *prate;
+ tmp *= 18;
+ do_div(tmp, frac);
+
+ return tmp;
+}
+
+static int clk_pfdv2_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+
+ if (readl_relaxed(pfd->reg) & pfd->gate_bit)
+ return 0;
+
+ return 1;
+}
+
+static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u64 tmp = parent_rate;
+ u32 val;
+ u8 frac;
+
+ tmp = tmp * 18 + rate / 2;
+ do_div(tmp, rate);
+ frac = tmp;
+ if (frac < 12)
+ frac = 12;
+ else if (frac > 35)
+ frac = 35;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val &= ~(CLK_PFDV2_FRAC_MASK << pfd->frac_off);
+ val |= frac << pfd->frac_off;
+ writel_relaxed(val, pfd->reg);
+ spin_unlock_irqrestore(&pfd_lock, flags);
+
+ return 0;
+}
+
+static const struct clk_ops clk_pfdv2_ops = {
+ .enable = clk_pfdv2_enable,
+ .disable = clk_pfdv2_disable,
+ .recalc_rate = clk_pfdv2_recalc_rate,
+ .round_rate = clk_pfdv2_round_rate,
+ .set_rate = clk_pfdv2_set_rate,
+ .is_enabled = clk_pfdv2_is_enabled,
+};
+
+struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
+ void __iomem *reg, u8 idx)
+{
+ struct clk_init_data init;
+ struct clk_pfdv2 *pfd;
+ struct clk_hw *hw;
+ int ret;
+
+ WARN_ON(idx > 3);
+
+ pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
+ if (!pfd)
+ return ERR_PTR(-ENOMEM);
+
+ pfd->reg = reg;
+ pfd->gate_bit = 1 << ((idx + 1) * 8 - 1);
+ pfd->vld_bit = pfd->gate_bit - 1;
+ pfd->frac_off = idx * 8;
+
+ init.name = name;
+ init.ops = &clk_pfdv2_ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ init.flags = CLK_SET_RATE_GATE;
+
+ pfd->hw.init = &init;
+
+ hw = &pfd->hw;
+ ret = clk_hw_register(NULL, hw);
+ if (ret) {
+ kfree(pfd);
+ hw = ERR_PTR(ret);
+ }
+
+ return hw;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 52f7c9d..ccd7181 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -60,6 +60,9 @@ struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
struct clk *imx_clk_pfd(const char *name, const char *parent_name,
void __iomem *reg, u8 idx);
+struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
+ void __iomem *reg, u8 idx);
+
struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
void __iomem *reg, u8 shift, u8 width,
void __iomem *busy_reg, u8 busy_shift);
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 05/10] clk: imx: add composite clk support
2018-01-19 13:11 ` Dong Aisheng
@ 2018-01-19 13:11 ` Dong Aisheng
-1 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-arm-kernel, sboyd, mturquette, shawnguo,
Anson.Huang, ping.bai, linux-imx, fabio.estevam, Dong Aisheng
The imx composite clk is designed for Peripheral Clock Control (PCC)
module observed in IMX ULP SoC series. e.g. i.MX7ULP.
NOTE pcc can only be operated when clk is gated.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* remove an unneeded blank line change
* use clk_hw_register
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-composite.c | 90 +++++++++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk.h | 6 +++
3 files changed, 97 insertions(+)
create mode 100644 drivers/clk/imx/clk-composite.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 9c04ae4..eab606c 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -4,6 +4,7 @@ obj-y += \
clk.o \
clk-busy.o \
clk-cpu.o \
+ clk-composite.o \
clk-fixup-div.o \
clk-fixup-mux.o \
clk-gate-exclusive.o \
diff --git a/drivers/clk/imx/clk-composite.c b/drivers/clk/imx/clk-composite.c
new file mode 100644
index 0000000..78b891e
--- /dev/null
+++ b/drivers/clk/imx/clk-composite.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#define PCG_PCS_SHIFT 24
+#define PCG_PCS_MASK 0x7
+#define PCG_CGC_SHIFT 30
+#define PCG_FRAC_SHIFT 3
+#define PCG_FRAC_WIDTH 1
+#define PCG_FRAC_MASK BIT(3)
+#define PCG_PCD_SHIFT 0
+#define PCG_PCD_WIDTH 3
+#define PCG_PCD_MASK 0x7
+
+struct clk_hw *imx_clk_composite(const char *name,
+ const char * const *parent_names,
+ int num_parents, bool mux_present,
+ bool rate_present, bool gate_present,
+ void __iomem *reg)
+{
+ struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL;
+ struct clk_fractional_divider *fd = NULL;
+ struct clk_gate *gate = NULL;
+ struct clk_mux *mux = NULL;
+ struct clk_hw *hw;
+
+ if (mux_present) {
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+ mux_hw = &mux->hw;
+ mux->reg = reg;
+ mux->shift = PCG_PCS_SHIFT;
+ mux->mask = PCG_PCS_MASK;
+ }
+
+ if (rate_present) {
+ fd = kzalloc(sizeof(*fd), GFP_KERNEL);
+ if (!fd) {
+ kfree(mux);
+ return ERR_PTR(-ENOMEM);
+ }
+ fd_hw = &fd->hw;
+ fd->reg = reg;
+ fd->mshift = PCG_FRAC_SHIFT;
+ fd->mwidth = PCG_FRAC_WIDTH;
+ fd->mmask = PCG_FRAC_MASK;
+ fd->nshift = PCG_PCD_SHIFT;
+ fd->nwidth = PCG_PCD_WIDTH;
+ fd->nmask = PCG_PCD_MASK;
+ fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;
+ }
+
+ if (gate_present) {
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate) {
+ kfree(mux);
+ kfree(fd);
+ return ERR_PTR(-ENOMEM);
+ }
+ gate_hw = &gate->hw;
+ gate->reg = reg;
+ gate->bit_idx = PCG_CGC_SHIFT;
+ }
+
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux_hw, &clk_mux_ops, fd_hw,
+ &clk_fractional_divider_ops, gate_hw,
+ &clk_gate_ops, CLK_SET_RATE_GATE |
+ CLK_SET_PARENT_GATE);
+ if (IS_ERR(hw)) {
+ kfree(mux);
+ kfree(fd);
+ kfree(gate);
+ }
+
+ return hw;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index ccd7181..fed7660 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -71,6 +71,12 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
const char **parent_names, int num_parents);
+struct clk_hw *imx_clk_composite(const char *name,
+ const char * const *parent_names,
+ int num_parents, bool mux_present,
+ bool rate_present, bool gate_present,
+ void __iomem *reg);
+
struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
void __iomem *reg, u8 shift, u8 width,
void (*fixup)(u32 *val));
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 05/10] clk: imx: add composite clk support
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-arm-kernel
The imx composite clk is designed for Peripheral Clock Control (PCC)
module observed in IMX ULP SoC series. e.g. i.MX7ULP.
NOTE pcc can only be operated when clk is gated.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* remove an unneeded blank line change
* use clk_hw_register
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-composite.c | 90 +++++++++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk.h | 6 +++
3 files changed, 97 insertions(+)
create mode 100644 drivers/clk/imx/clk-composite.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 9c04ae4..eab606c 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -4,6 +4,7 @@ obj-y += \
clk.o \
clk-busy.o \
clk-cpu.o \
+ clk-composite.o \
clk-fixup-div.o \
clk-fixup-mux.o \
clk-gate-exclusive.o \
diff --git a/drivers/clk/imx/clk-composite.c b/drivers/clk/imx/clk-composite.c
new file mode 100644
index 0000000..78b891e
--- /dev/null
+++ b/drivers/clk/imx/clk-composite.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#define PCG_PCS_SHIFT 24
+#define PCG_PCS_MASK 0x7
+#define PCG_CGC_SHIFT 30
+#define PCG_FRAC_SHIFT 3
+#define PCG_FRAC_WIDTH 1
+#define PCG_FRAC_MASK BIT(3)
+#define PCG_PCD_SHIFT 0
+#define PCG_PCD_WIDTH 3
+#define PCG_PCD_MASK 0x7
+
+struct clk_hw *imx_clk_composite(const char *name,
+ const char * const *parent_names,
+ int num_parents, bool mux_present,
+ bool rate_present, bool gate_present,
+ void __iomem *reg)
+{
+ struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL;
+ struct clk_fractional_divider *fd = NULL;
+ struct clk_gate *gate = NULL;
+ struct clk_mux *mux = NULL;
+ struct clk_hw *hw;
+
+ if (mux_present) {
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+ mux_hw = &mux->hw;
+ mux->reg = reg;
+ mux->shift = PCG_PCS_SHIFT;
+ mux->mask = PCG_PCS_MASK;
+ }
+
+ if (rate_present) {
+ fd = kzalloc(sizeof(*fd), GFP_KERNEL);
+ if (!fd) {
+ kfree(mux);
+ return ERR_PTR(-ENOMEM);
+ }
+ fd_hw = &fd->hw;
+ fd->reg = reg;
+ fd->mshift = PCG_FRAC_SHIFT;
+ fd->mwidth = PCG_FRAC_WIDTH;
+ fd->mmask = PCG_FRAC_MASK;
+ fd->nshift = PCG_PCD_SHIFT;
+ fd->nwidth = PCG_PCD_WIDTH;
+ fd->nmask = PCG_PCD_MASK;
+ fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;
+ }
+
+ if (gate_present) {
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate) {
+ kfree(mux);
+ kfree(fd);
+ return ERR_PTR(-ENOMEM);
+ }
+ gate_hw = &gate->hw;
+ gate->reg = reg;
+ gate->bit_idx = PCG_CGC_SHIFT;
+ }
+
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux_hw, &clk_mux_ops, fd_hw,
+ &clk_fractional_divider_ops, gate_hw,
+ &clk_gate_ops, CLK_SET_RATE_GATE |
+ CLK_SET_PARENT_GATE);
+ if (IS_ERR(hw)) {
+ kfree(mux);
+ kfree(fd);
+ kfree(gate);
+ }
+
+ return hw;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index ccd7181..fed7660 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -71,6 +71,12 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
const char **parent_names, int num_parents);
+struct clk_hw *imx_clk_composite(const char *name,
+ const char * const *parent_names,
+ int num_parents, bool mux_present,
+ bool rate_present, bool gate_present,
+ void __iomem *reg);
+
struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
void __iomem *reg, u8 shift, u8 width,
void (*fixup)(u32 *val));
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 06/10] dt-bindings: clock: add imx7ulp clock binding doc
2018-01-19 13:11 ` Dong Aisheng
(?)
@ 2018-01-19 13:11 ` Dong Aisheng
-1 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-arm-kernel, sboyd, mturquette, shawnguo,
Anson.Huang, ping.bai, linux-imx, fabio.estevam, Dong Aisheng,
Rob Herring, Mark Rutland
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
Note IMX7ULP has two clock domains: M4 and A7. This binding doc
is only for A7 clock domain.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2: no changes
---
.../devicetree/bindings/clock/imx7ulp-clock.txt | 62 ++++++++++++
include/dt-bindings/clock/imx7ulp-clock.h | 108 +++++++++++++++++++++
2 files changed, 170 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h
diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
new file mode 100644
index 0000000..76ea3c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
@@ -0,0 +1,62 @@
+* Clock bindings for Freescale i.MX7ULP
+
+i.MX7ULP Clock functions are under joint control of the System
+Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
+modules, and Core Mode Controller (CMC)1 blocks
+
+The clocking scheme provides clear separation between M4 domain
+and A7 domain. Except for a few clock sources shared between two
+domains, such as the System Oscillator clock, the Slow IRC (SIRC),
+and and the Fast IRC clock (FIRCLK), clock sources and clock
+management are separated and contained within each domain.
+
+M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
+A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
+
+Note: this binding doc is only for A7 clock domain.
+
+Required properties:
+
+- compatible: Should be "fsl,imx7ulp-clock".
+- reg : Should contain registers location and length for scg1,
+ pcc2 and pcc3.
+- reg-names: Should contain the according reg names "scg1", "pcc2"
+ and "pcc3".
+- #clock-cells: Should be <1>.
+- clocks: Should contain the fixed input clocks.
+- clock-name: Should contain the following clock names:"rsoc", "sosc",
+ "sirc", "firc", "upll", "mpll".
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.
+See include/dt-bindings/clock/imx7ulp-clock.h
+for the full list of i.MX7ULP clock IDs.
+
+Examples:
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+
+clks: scg1@403e0000 {
+ compatible = "fsl,imx7ulp-clock";
+ reg = <0x403e0000 0x10000>
+ <0x403f0000 0x10000>
+ <0x40b30000 0x10000>;
+ reg-names = "scg1", "pcc2", "pcc3";
+ clocks = <&rsoc>, <&sosc>, <&sirc>,
+ <&firc>, <&upll>, <&mpll>;
+ clock-names = "rsoc", "sosc", "sirc",
+ "firc", "upll", "mpll";
+ #clock-cells = <1>;
+};
+
+usdhc1: usdhc@40380000 {
+ compatible = "fsl,imx7ulp-usdhc";
+ reg = <0x40380000 0x10000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&clks IMX7ULP_CLK_NIC1_DIV>,
+ <&clks IMX7ULP_CLK_USDHC1>;
+ clock-names ="ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+};
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
new file mode 100644
index 0000000..2556106
--- /dev/null
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
+#define __DT_BINDINGS_CLOCK_IMX7ULP_H
+
+#define IMX7ULP_CLK_DUMMY 0
+#define IMX7ULP_CLK_ROSC 1
+#define IMX7ULP_CLK_SOSC 2
+#define IMX7ULP_CLK_FIRC 3
+
+/* SCG1 */
+#define IMX7ULP_CLK_SPLL_PRE_SEL 4
+#define IMX7ULP_CLK_SPLL_PRE_DIV 5
+#define IMX7ULP_CLK_SPLL 6
+#define IMX7ULP_CLK_SPLL_POST_DIV1 7
+#define IMX7ULP_CLK_SPLL_POST_DIV2 8
+#define IMX7ULP_CLK_SPLL_PFD0 9
+#define IMX7ULP_CLK_SPLL_PFD1 10
+#define IMX7ULP_CLK_SPLL_PFD2 11
+#define IMX7ULP_CLK_SPLL_PFD3 12
+#define IMX7ULP_CLK_SPLL_PFD_SEL 13
+#define IMX7ULP_CLK_SPLL_SEL 14
+#define IMX7ULP_CLK_APLL_PRE_SEL 15
+#define IMX7ULP_CLK_APLL_PRE_DIV 16
+#define IMX7ULP_CLK_APLL 17
+#define IMX7ULP_CLK_APLL_POST_DIV1 18
+#define IMX7ULP_CLK_APLL_POST_DIV2 19
+#define IMX7ULP_CLK_APLL_PFD0 20
+#define IMX7ULP_CLK_APLL_PFD1 21
+#define IMX7ULP_CLK_APLL_PFD2 22
+#define IMX7ULP_CLK_APLL_PFD3 23
+#define IMX7ULP_CLK_APLL_PFD_SEL 24
+#define IMX7ULP_CLK_APLL_SEL 25
+#define IMX7ULP_CLK_UPLL 26
+#define IMX7ULP_CLK_SYS_SEL 27
+#define IMX7ULP_CLK_CORE_DIV 28
+#define IMX7ULP_CLK_BUS_DIV 29
+#define IMX7ULP_CLK_PLAT_DIV 30
+#define IMX7ULP_CLK_DDR_SEL 31
+#define IMX7ULP_CLK_DDR_DIV 32
+#define IMX7ULP_CLK_NIC_SEL 33
+#define IMX7ULP_CLK_NIC0_DIV 34
+#define IMX7ULP_CLK_GPU_DIV 35
+#define IMX7ULP_CLK_NIC1_DIV 36
+#define IMX7ULP_CLK_NIC1_BUS_DIV 37
+#define IMX7ULP_CLK_NIC1_EXT_DIV 38
+
+/* PCG2 */
+#define IMX7ULP_CLK_DMA1 39
+#define IMX7ULP_CLK_RGPIO2P1 40
+#define IMX7ULP_CLK_FLEXBUS 41
+#define IMX7ULP_CLK_SEMA42_1 42
+#define IMX7ULP_CLK_DMA_MUX1 43
+#define IMX7ULP_CLK_SNVS 44
+#define IMX7ULP_CLK_CAAM 45
+#define IMX7ULP_CLK_LPTPM4 46
+#define IMX7ULP_CLK_LPTPM5 47
+#define IMX7ULP_CLK_LPIT1 48
+#define IMX7ULP_CLK_LPSPI2 49
+#define IMX7ULP_CLK_LPSPI3 50
+#define IMX7ULP_CLK_LPI2C4 51
+#define IMX7ULP_CLK_LPI2C5 52
+#define IMX7ULP_CLK_LPUART4 53
+#define IMX7ULP_CLK_LPUART5 54
+#define IMX7ULP_CLK_FLEXIO1 55
+#define IMX7ULP_CLK_USB0 56
+#define IMX7ULP_CLK_USB1 57
+#define IMX7ULP_CLK_USB_PHY 58
+#define IMX7ULP_CLK_USB_PL301 59
+#define IMX7ULP_CLK_USDHC0 60
+#define IMX7ULP_CLK_USDHC1 61
+#define IMX7ULP_CLK_WDG1 62
+#define IMX7ULP_CLK_WDG2 63
+
+/* PCG3 */
+#define IMX7ULP_CLK_LPTPM6 64
+#define IMX7ULP_CLK_LPTPM7 65
+#define IMX7ULP_CLK_LPI2C6 66
+#define IMX7ULP_CLK_LPI2C7 67
+#define IMX7ULP_CLK_LPUART6 68
+#define IMX7ULP_CLK_LPUART7 69
+#define IMX7ULP_CLK_VIU 70
+#define IMX7ULP_CLK_DSI 71
+#define IMX7ULP_CLK_LCDIF 72
+#define IMX7ULP_CLK_MMDC 73
+#define IMX7ULP_CLK_PCTLC 74
+#define IMX7ULP_CLK_PCTLD 75
+#define IMX7ULP_CLK_PCTLE 76
+#define IMX7ULP_CLK_PCTLF 77
+#define IMX7ULP_CLK_GPU3D 78
+#define IMX7ULP_CLK_GPU2D 79
+#define IMX7ULP_CLK_MIPI_PLL 80
+#define IMX7ULP_CLK_SIRC 81
+#define IMX7ULP_CLK_SOSC_BUS_CLK 82
+#define IMX7ULP_CLK_FIRC_BUS_CLK 83
+#define IMX7ULP_CLK_SPLL_BUS_CLK 84
+
+#define IMX7ULP_CLK_END 85
+
+#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 06/10] dt-bindings: clock: add imx7ulp clock binding doc
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: Dong Aisheng, Mark Rutland, ping.bai, Anson.Huang, mturquette,
sboyd, linux-kernel, Rob Herring, linux-imx, fabio.estevam,
shawnguo, linux-arm-kernel
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
Note IMX7ULP has two clock domains: M4 and A7. This binding doc
is only for A7 clock domain.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2: no changes
---
.../devicetree/bindings/clock/imx7ulp-clock.txt | 62 ++++++++++++
include/dt-bindings/clock/imx7ulp-clock.h | 108 +++++++++++++++++++++
2 files changed, 170 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h
diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
new file mode 100644
index 0000000..76ea3c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
@@ -0,0 +1,62 @@
+* Clock bindings for Freescale i.MX7ULP
+
+i.MX7ULP Clock functions are under joint control of the System
+Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
+modules, and Core Mode Controller (CMC)1 blocks
+
+The clocking scheme provides clear separation between M4 domain
+and A7 domain. Except for a few clock sources shared between two
+domains, such as the System Oscillator clock, the Slow IRC (SIRC),
+and and the Fast IRC clock (FIRCLK), clock sources and clock
+management are separated and contained within each domain.
+
+M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
+A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
+
+Note: this binding doc is only for A7 clock domain.
+
+Required properties:
+
+- compatible: Should be "fsl,imx7ulp-clock".
+- reg : Should contain registers location and length for scg1,
+ pcc2 and pcc3.
+- reg-names: Should contain the according reg names "scg1", "pcc2"
+ and "pcc3".
+- #clock-cells: Should be <1>.
+- clocks: Should contain the fixed input clocks.
+- clock-name: Should contain the following clock names:"rsoc", "sosc",
+ "sirc", "firc", "upll", "mpll".
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.
+See include/dt-bindings/clock/imx7ulp-clock.h
+for the full list of i.MX7ULP clock IDs.
+
+Examples:
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+
+clks: scg1@403e0000 {
+ compatible = "fsl,imx7ulp-clock";
+ reg = <0x403e0000 0x10000>
+ <0x403f0000 0x10000>
+ <0x40b30000 0x10000>;
+ reg-names = "scg1", "pcc2", "pcc3";
+ clocks = <&rsoc>, <&sosc>, <&sirc>,
+ <&firc>, <&upll>, <&mpll>;
+ clock-names = "rsoc", "sosc", "sirc",
+ "firc", "upll", "mpll";
+ #clock-cells = <1>;
+};
+
+usdhc1: usdhc@40380000 {
+ compatible = "fsl,imx7ulp-usdhc";
+ reg = <0x40380000 0x10000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&clks IMX7ULP_CLK_NIC1_DIV>,
+ <&clks IMX7ULP_CLK_USDHC1>;
+ clock-names ="ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+};
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
new file mode 100644
index 0000000..2556106
--- /dev/null
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
+#define __DT_BINDINGS_CLOCK_IMX7ULP_H
+
+#define IMX7ULP_CLK_DUMMY 0
+#define IMX7ULP_CLK_ROSC 1
+#define IMX7ULP_CLK_SOSC 2
+#define IMX7ULP_CLK_FIRC 3
+
+/* SCG1 */
+#define IMX7ULP_CLK_SPLL_PRE_SEL 4
+#define IMX7ULP_CLK_SPLL_PRE_DIV 5
+#define IMX7ULP_CLK_SPLL 6
+#define IMX7ULP_CLK_SPLL_POST_DIV1 7
+#define IMX7ULP_CLK_SPLL_POST_DIV2 8
+#define IMX7ULP_CLK_SPLL_PFD0 9
+#define IMX7ULP_CLK_SPLL_PFD1 10
+#define IMX7ULP_CLK_SPLL_PFD2 11
+#define IMX7ULP_CLK_SPLL_PFD3 12
+#define IMX7ULP_CLK_SPLL_PFD_SEL 13
+#define IMX7ULP_CLK_SPLL_SEL 14
+#define IMX7ULP_CLK_APLL_PRE_SEL 15
+#define IMX7ULP_CLK_APLL_PRE_DIV 16
+#define IMX7ULP_CLK_APLL 17
+#define IMX7ULP_CLK_APLL_POST_DIV1 18
+#define IMX7ULP_CLK_APLL_POST_DIV2 19
+#define IMX7ULP_CLK_APLL_PFD0 20
+#define IMX7ULP_CLK_APLL_PFD1 21
+#define IMX7ULP_CLK_APLL_PFD2 22
+#define IMX7ULP_CLK_APLL_PFD3 23
+#define IMX7ULP_CLK_APLL_PFD_SEL 24
+#define IMX7ULP_CLK_APLL_SEL 25
+#define IMX7ULP_CLK_UPLL 26
+#define IMX7ULP_CLK_SYS_SEL 27
+#define IMX7ULP_CLK_CORE_DIV 28
+#define IMX7ULP_CLK_BUS_DIV 29
+#define IMX7ULP_CLK_PLAT_DIV 30
+#define IMX7ULP_CLK_DDR_SEL 31
+#define IMX7ULP_CLK_DDR_DIV 32
+#define IMX7ULP_CLK_NIC_SEL 33
+#define IMX7ULP_CLK_NIC0_DIV 34
+#define IMX7ULP_CLK_GPU_DIV 35
+#define IMX7ULP_CLK_NIC1_DIV 36
+#define IMX7ULP_CLK_NIC1_BUS_DIV 37
+#define IMX7ULP_CLK_NIC1_EXT_DIV 38
+
+/* PCG2 */
+#define IMX7ULP_CLK_DMA1 39
+#define IMX7ULP_CLK_RGPIO2P1 40
+#define IMX7ULP_CLK_FLEXBUS 41
+#define IMX7ULP_CLK_SEMA42_1 42
+#define IMX7ULP_CLK_DMA_MUX1 43
+#define IMX7ULP_CLK_SNVS 44
+#define IMX7ULP_CLK_CAAM 45
+#define IMX7ULP_CLK_LPTPM4 46
+#define IMX7ULP_CLK_LPTPM5 47
+#define IMX7ULP_CLK_LPIT1 48
+#define IMX7ULP_CLK_LPSPI2 49
+#define IMX7ULP_CLK_LPSPI3 50
+#define IMX7ULP_CLK_LPI2C4 51
+#define IMX7ULP_CLK_LPI2C5 52
+#define IMX7ULP_CLK_LPUART4 53
+#define IMX7ULP_CLK_LPUART5 54
+#define IMX7ULP_CLK_FLEXIO1 55
+#define IMX7ULP_CLK_USB0 56
+#define IMX7ULP_CLK_USB1 57
+#define IMX7ULP_CLK_USB_PHY 58
+#define IMX7ULP_CLK_USB_PL301 59
+#define IMX7ULP_CLK_USDHC0 60
+#define IMX7ULP_CLK_USDHC1 61
+#define IMX7ULP_CLK_WDG1 62
+#define IMX7ULP_CLK_WDG2 63
+
+/* PCG3 */
+#define IMX7ULP_CLK_LPTPM6 64
+#define IMX7ULP_CLK_LPTPM7 65
+#define IMX7ULP_CLK_LPI2C6 66
+#define IMX7ULP_CLK_LPI2C7 67
+#define IMX7ULP_CLK_LPUART6 68
+#define IMX7ULP_CLK_LPUART7 69
+#define IMX7ULP_CLK_VIU 70
+#define IMX7ULP_CLK_DSI 71
+#define IMX7ULP_CLK_LCDIF 72
+#define IMX7ULP_CLK_MMDC 73
+#define IMX7ULP_CLK_PCTLC 74
+#define IMX7ULP_CLK_PCTLD 75
+#define IMX7ULP_CLK_PCTLE 76
+#define IMX7ULP_CLK_PCTLF 77
+#define IMX7ULP_CLK_GPU3D 78
+#define IMX7ULP_CLK_GPU2D 79
+#define IMX7ULP_CLK_MIPI_PLL 80
+#define IMX7ULP_CLK_SIRC 81
+#define IMX7ULP_CLK_SOSC_BUS_CLK 82
+#define IMX7ULP_CLK_FIRC_BUS_CLK 83
+#define IMX7ULP_CLK_SPLL_BUS_CLK 84
+
+#define IMX7ULP_CLK_END 85
+
+#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 06/10] dt-bindings: clock: add imx7ulp clock binding doc
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-arm-kernel
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
Note IMX7ULP has two clock domains: M4 and A7. This binding doc
is only for A7 clock domain.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2: no changes
---
.../devicetree/bindings/clock/imx7ulp-clock.txt | 62 ++++++++++++
include/dt-bindings/clock/imx7ulp-clock.h | 108 +++++++++++++++++++++
2 files changed, 170 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h
diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
new file mode 100644
index 0000000..76ea3c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
@@ -0,0 +1,62 @@
+* Clock bindings for Freescale i.MX7ULP
+
+i.MX7ULP Clock functions are under joint control of the System
+Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
+modules, and Core Mode Controller (CMC)1 blocks
+
+The clocking scheme provides clear separation between M4 domain
+and A7 domain. Except for a few clock sources shared between two
+domains, such as the System Oscillator clock, the Slow IRC (SIRC),
+and and the Fast IRC clock (FIRCLK), clock sources and clock
+management are separated and contained within each domain.
+
+M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
+A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
+
+Note: this binding doc is only for A7 clock domain.
+
+Required properties:
+
+- compatible: Should be "fsl,imx7ulp-clock".
+- reg : Should contain registers location and length for scg1,
+ pcc2 and pcc3.
+- reg-names: Should contain the according reg names "scg1", "pcc2"
+ and "pcc3".
+- #clock-cells: Should be <1>.
+- clocks: Should contain the fixed input clocks.
+- clock-name: Should contain the following clock names:"rsoc", "sosc",
+ "sirc", "firc", "upll", "mpll".
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.
+See include/dt-bindings/clock/imx7ulp-clock.h
+for the full list of i.MX7ULP clock IDs.
+
+Examples:
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+
+clks: scg1 at 403e0000 {
+ compatible = "fsl,imx7ulp-clock";
+ reg = <0x403e0000 0x10000>
+ <0x403f0000 0x10000>
+ <0x40b30000 0x10000>;
+ reg-names = "scg1", "pcc2", "pcc3";
+ clocks = <&rsoc>, <&sosc>, <&sirc>,
+ <&firc>, <&upll>, <&mpll>;
+ clock-names = "rsoc", "sosc", "sirc",
+ "firc", "upll", "mpll";
+ #clock-cells = <1>;
+};
+
+usdhc1: usdhc at 40380000 {
+ compatible = "fsl,imx7ulp-usdhc";
+ reg = <0x40380000 0x10000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&clks IMX7ULP_CLK_NIC1_DIV>,
+ <&clks IMX7ULP_CLK_USDHC1>;
+ clock-names ="ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+};
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
new file mode 100644
index 0000000..2556106
--- /dev/null
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
+#define __DT_BINDINGS_CLOCK_IMX7ULP_H
+
+#define IMX7ULP_CLK_DUMMY 0
+#define IMX7ULP_CLK_ROSC 1
+#define IMX7ULP_CLK_SOSC 2
+#define IMX7ULP_CLK_FIRC 3
+
+/* SCG1 */
+#define IMX7ULP_CLK_SPLL_PRE_SEL 4
+#define IMX7ULP_CLK_SPLL_PRE_DIV 5
+#define IMX7ULP_CLK_SPLL 6
+#define IMX7ULP_CLK_SPLL_POST_DIV1 7
+#define IMX7ULP_CLK_SPLL_POST_DIV2 8
+#define IMX7ULP_CLK_SPLL_PFD0 9
+#define IMX7ULP_CLK_SPLL_PFD1 10
+#define IMX7ULP_CLK_SPLL_PFD2 11
+#define IMX7ULP_CLK_SPLL_PFD3 12
+#define IMX7ULP_CLK_SPLL_PFD_SEL 13
+#define IMX7ULP_CLK_SPLL_SEL 14
+#define IMX7ULP_CLK_APLL_PRE_SEL 15
+#define IMX7ULP_CLK_APLL_PRE_DIV 16
+#define IMX7ULP_CLK_APLL 17
+#define IMX7ULP_CLK_APLL_POST_DIV1 18
+#define IMX7ULP_CLK_APLL_POST_DIV2 19
+#define IMX7ULP_CLK_APLL_PFD0 20
+#define IMX7ULP_CLK_APLL_PFD1 21
+#define IMX7ULP_CLK_APLL_PFD2 22
+#define IMX7ULP_CLK_APLL_PFD3 23
+#define IMX7ULP_CLK_APLL_PFD_SEL 24
+#define IMX7ULP_CLK_APLL_SEL 25
+#define IMX7ULP_CLK_UPLL 26
+#define IMX7ULP_CLK_SYS_SEL 27
+#define IMX7ULP_CLK_CORE_DIV 28
+#define IMX7ULP_CLK_BUS_DIV 29
+#define IMX7ULP_CLK_PLAT_DIV 30
+#define IMX7ULP_CLK_DDR_SEL 31
+#define IMX7ULP_CLK_DDR_DIV 32
+#define IMX7ULP_CLK_NIC_SEL 33
+#define IMX7ULP_CLK_NIC0_DIV 34
+#define IMX7ULP_CLK_GPU_DIV 35
+#define IMX7ULP_CLK_NIC1_DIV 36
+#define IMX7ULP_CLK_NIC1_BUS_DIV 37
+#define IMX7ULP_CLK_NIC1_EXT_DIV 38
+
+/* PCG2 */
+#define IMX7ULP_CLK_DMA1 39
+#define IMX7ULP_CLK_RGPIO2P1 40
+#define IMX7ULP_CLK_FLEXBUS 41
+#define IMX7ULP_CLK_SEMA42_1 42
+#define IMX7ULP_CLK_DMA_MUX1 43
+#define IMX7ULP_CLK_SNVS 44
+#define IMX7ULP_CLK_CAAM 45
+#define IMX7ULP_CLK_LPTPM4 46
+#define IMX7ULP_CLK_LPTPM5 47
+#define IMX7ULP_CLK_LPIT1 48
+#define IMX7ULP_CLK_LPSPI2 49
+#define IMX7ULP_CLK_LPSPI3 50
+#define IMX7ULP_CLK_LPI2C4 51
+#define IMX7ULP_CLK_LPI2C5 52
+#define IMX7ULP_CLK_LPUART4 53
+#define IMX7ULP_CLK_LPUART5 54
+#define IMX7ULP_CLK_FLEXIO1 55
+#define IMX7ULP_CLK_USB0 56
+#define IMX7ULP_CLK_USB1 57
+#define IMX7ULP_CLK_USB_PHY 58
+#define IMX7ULP_CLK_USB_PL301 59
+#define IMX7ULP_CLK_USDHC0 60
+#define IMX7ULP_CLK_USDHC1 61
+#define IMX7ULP_CLK_WDG1 62
+#define IMX7ULP_CLK_WDG2 63
+
+/* PCG3 */
+#define IMX7ULP_CLK_LPTPM6 64
+#define IMX7ULP_CLK_LPTPM7 65
+#define IMX7ULP_CLK_LPI2C6 66
+#define IMX7ULP_CLK_LPI2C7 67
+#define IMX7ULP_CLK_LPUART6 68
+#define IMX7ULP_CLK_LPUART7 69
+#define IMX7ULP_CLK_VIU 70
+#define IMX7ULP_CLK_DSI 71
+#define IMX7ULP_CLK_LCDIF 72
+#define IMX7ULP_CLK_MMDC 73
+#define IMX7ULP_CLK_PCTLC 74
+#define IMX7ULP_CLK_PCTLD 75
+#define IMX7ULP_CLK_PCTLE 76
+#define IMX7ULP_CLK_PCTLF 77
+#define IMX7ULP_CLK_GPU3D 78
+#define IMX7ULP_CLK_GPU2D 79
+#define IMX7ULP_CLK_MIPI_PLL 80
+#define IMX7ULP_CLK_SIRC 81
+#define IMX7ULP_CLK_SOSC_BUS_CLK 82
+#define IMX7ULP_CLK_FIRC_BUS_CLK 83
+#define IMX7ULP_CLK_SPLL_BUS_CLK 84
+
+#define IMX7ULP_CLK_END 85
+
+#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 07/10] clk: imx: make mux parent strings const
2018-01-19 13:11 ` Dong Aisheng
@ 2018-01-19 13:11 ` Dong Aisheng
-1 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-arm-kernel, sboyd, mturquette, shawnguo,
Anson.Huang, ping.bai, linux-imx, fabio.estevam, Dong Aisheng
As the commit 2893c379461a ("clk: make strings in parent name arrays
const"), let's make the parent strings const, otherwise we may meet
the following warning when compiling:
drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init':
drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing argument 5 of
'imx_clk_mux_flags' discards 'const' qualifier from pointer target type
clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_mux_flags("apll_pre_sel", base + 0x508, 0,
1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
^
In file included from drivers/clk/imx/clk-imx7ulp.c:23:0:
drivers/clk/imx/clk.h:200:27: note: expected 'const char **' but argument is
of type 'const char * const*'
...
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v1->v3: no changes
---
drivers/clk/imx/clk-busy.c | 2 +-
drivers/clk/imx/clk-fixup-mux.c | 2 +-
drivers/clk/imx/clk.h | 18 +++++++++++-------
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/imx/clk-busy.c b/drivers/clk/imx/clk-busy.c
index 6df3389..ba1541f 100644
--- a/drivers/clk/imx/clk-busy.c
+++ b/drivers/clk/imx/clk-busy.c
@@ -154,7 +154,7 @@ static const struct clk_ops clk_busy_mux_ops = {
struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
- const char **parent_names, int num_parents)
+ const char * const *parent_names, int num_parents)
{
struct clk_busy_mux *busy;
struct clk *clk;
diff --git a/drivers/clk/imx/clk-fixup-mux.c b/drivers/clk/imx/clk-fixup-mux.c
index c9b327e..44817c1 100644
--- a/drivers/clk/imx/clk-fixup-mux.c
+++ b/drivers/clk/imx/clk-fixup-mux.c
@@ -70,7 +70,7 @@ static const struct clk_ops clk_fixup_mux_ops = {
};
struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents,
+ u8 shift, u8 width, const char * const *parents,
int num_parents, void (*fixup)(u32 *val))
{
struct clk_fixup_mux *fixup_mux;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index fed7660..956155c 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -69,7 +69,7 @@ struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
- const char **parent_names, int num_parents);
+ const char * const *parent_names, int num_parents);
struct clk_hw *imx_clk_composite(const char *name,
const char * const *parent_names,
@@ -82,7 +82,7 @@ struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
void (*fixup)(u32 *val));
struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents,
+ u8 shift, u8 width, const char * const *parents,
int num_parents, void (*fixup)(u32 *val));
static inline struct clk *imx_clk_fixed(const char *name, int rate)
@@ -91,7 +91,8 @@ static inline struct clk *imx_clk_fixed(const char *name, int rate)
}
static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
@@ -190,7 +191,8 @@ static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
}
static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT, reg, shift,
@@ -198,7 +200,8 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
}
static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
@@ -206,8 +209,9 @@ static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
}
static inline struct clk *imx_clk_mux_flags(const char *name,
- void __iomem *reg, u8 shift, u8 width, const char **parents,
- int num_parents, unsigned long flags)
+ void __iomem *reg, u8 shift, u8 width,
+ const char * const *parents, int num_parents,
+ unsigned long flags)
{
return clk_register_mux(NULL, name, parents, num_parents,
flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 07/10] clk: imx: make mux parent strings const
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-arm-kernel
As the commit 2893c379461a ("clk: make strings in parent name arrays
const"), let's make the parent strings const, otherwise we may meet
the following warning when compiling:
drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init':
drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing argument 5 of
'imx_clk_mux_flags' discards 'const' qualifier from pointer target type
clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_mux_flags("apll_pre_sel", base + 0x508, 0,
1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
^
In file included from drivers/clk/imx/clk-imx7ulp.c:23:0:
drivers/clk/imx/clk.h:200:27: note: expected 'const char **' but argument is
of type 'const char * const*'
...
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v1->v3: no changes
---
drivers/clk/imx/clk-busy.c | 2 +-
drivers/clk/imx/clk-fixup-mux.c | 2 +-
drivers/clk/imx/clk.h | 18 +++++++++++-------
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/imx/clk-busy.c b/drivers/clk/imx/clk-busy.c
index 6df3389..ba1541f 100644
--- a/drivers/clk/imx/clk-busy.c
+++ b/drivers/clk/imx/clk-busy.c
@@ -154,7 +154,7 @@ static const struct clk_ops clk_busy_mux_ops = {
struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
- const char **parent_names, int num_parents)
+ const char * const *parent_names, int num_parents)
{
struct clk_busy_mux *busy;
struct clk *clk;
diff --git a/drivers/clk/imx/clk-fixup-mux.c b/drivers/clk/imx/clk-fixup-mux.c
index c9b327e..44817c1 100644
--- a/drivers/clk/imx/clk-fixup-mux.c
+++ b/drivers/clk/imx/clk-fixup-mux.c
@@ -70,7 +70,7 @@ static const struct clk_ops clk_fixup_mux_ops = {
};
struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents,
+ u8 shift, u8 width, const char * const *parents,
int num_parents, void (*fixup)(u32 *val))
{
struct clk_fixup_mux *fixup_mux;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index fed7660..956155c 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -69,7 +69,7 @@ struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
- const char **parent_names, int num_parents);
+ const char * const *parent_names, int num_parents);
struct clk_hw *imx_clk_composite(const char *name,
const char * const *parent_names,
@@ -82,7 +82,7 @@ struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
void (*fixup)(u32 *val));
struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents,
+ u8 shift, u8 width, const char * const *parents,
int num_parents, void (*fixup)(u32 *val));
static inline struct clk *imx_clk_fixed(const char *name, int rate)
@@ -91,7 +91,8 @@ static inline struct clk *imx_clk_fixed(const char *name, int rate)
}
static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
@@ -190,7 +191,8 @@ static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
}
static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT, reg, shift,
@@ -198,7 +200,8 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
}
static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
@@ -206,8 +209,9 @@ static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
}
static inline struct clk *imx_clk_mux_flags(const char *name,
- void __iomem *reg, u8 shift, u8 width, const char **parents,
- int num_parents, unsigned long flags)
+ void __iomem *reg, u8 shift, u8 width,
+ const char * const *parents, int num_parents,
+ unsigned long flags)
{
return clk_register_mux(NULL, name, parents, num_parents,
flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 08/10] clk: imx: implement new clk_hw based APIs
2018-01-19 13:11 ` Dong Aisheng
(?)
@ 2018-01-19 13:11 ` Dong Aisheng
-1 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-arm-kernel, sboyd, mturquette, shawnguo,
Anson.Huang, ping.bai, linux-imx, fabio.estevam, Dong Aisheng
Clock providers are recommended to use the new struct clk_hw based API,
so implement IMX clk_hw based provider helpers functions to the new
approach.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2: new patches
---
drivers/clk/imx/clk.c | 22 ++++++++++++++++++
drivers/clk/imx/clk.h | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 84 insertions(+)
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index 9074e69..1efed86 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -18,6 +18,16 @@ void __init imx_check_clocks(struct clk *clks[], unsigned int count)
i, PTR_ERR(clks[i]));
}
+void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count)
+{
+ unsigned int i;
+
+ for (i = 0; i < count; i++)
+ if (IS_ERR(clks[i]))
+ pr_err("i.MX clk %u: register failed with %ld\n",
+ i, PTR_ERR(clks[i]));
+}
+
static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
{
struct of_phandle_args phandle;
@@ -49,6 +59,18 @@ struct clk * __init imx_obtain_fixed_clock(
return clk;
}
+struct clk_hw * __init imx_obtain_fixed_clk_hw(struct device_node *np,
+ const char *name)
+{
+ struct clk *clk;
+
+ clk = of_clk_get_by_name(np, name);
+ if (IS_ERR(clk))
+ return ERR_PTR(-ENOENT);
+
+ return __clk_get_hw(clk);
+}
+
/*
* This fixups the register CCM_CSCMR1 write value.
* The write/read/divider values of the aclk_podf field
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 956155c..3d58420 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -8,6 +8,7 @@
extern spinlock_t imx_ccm_lock;
void imx_check_clocks(struct clk *clks[], unsigned int count);
+void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
void imx_register_uart_clocks(struct clk ** const clks[]);
extern void imx_cscmr1_fixup(u32 *val);
@@ -54,6 +55,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
struct clk * imx_obtain_fixed_clock(
const char *name, unsigned long rate);
+struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
+ const char *name);
+
struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
void __iomem *reg, u8 shift, u32 exclusive_mask);
@@ -90,6 +94,16 @@ static inline struct clk *imx_clk_fixed(const char *name, int rate)
return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
}
+static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
+{
+ return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
+}
+
+static inline struct clk_hw *imx_get_clk_hw_fixed(const char *name, int rate)
+{
+ return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
+}
+
static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
u8 shift, u8 width, const char * const *parents,
int num_parents)
@@ -113,6 +127,15 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_divider(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift,
+ u8 width)
+{
+ return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_divider_flags(const char *name,
const char *parent, void __iomem *reg, u8 shift, u8 width,
unsigned long flags)
@@ -121,6 +144,15 @@ static inline struct clk *imx_clk_divider_flags(const char *name,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift,
+ u8 width, unsigned long flags)
+{
+ return clk_hw_register_divider(NULL, name, parent, flags,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
void __iomem *reg, u8 shift, u8 width)
{
@@ -136,6 +168,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
shift, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent,
+ void __iomem *reg, u8 shift)
+{
+ return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+ shift, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
void __iomem *reg, u8 shift)
{
@@ -208,6 +247,17 @@ static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg,
+ u8 shift, u8 width,
+ const char * const *parents,
+ int num_parents)
+{
+ return clk_hw_register_mux(NULL, name, parents, num_parents,
+ CLK_SET_RATE_NO_REPARENT |
+ CLK_OPS_PARENT_ENABLE,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_mux_flags(const char *name,
void __iomem *reg, u8 shift, u8 width,
const char * const *parents, int num_parents,
@@ -218,6 +268,18 @@ static inline struct clk *imx_clk_mux_flags(const char *name,
&imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name,
+ void __iomem *reg, u8 shift,
+ u8 width,
+ const char * const *parents,
+ int num_parents,
+ unsigned long flags)
+{
+ return clk_hw_register_mux(NULL, name, parents, num_parents,
+ flags | CLK_SET_RATE_NO_REPARENT,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
struct clk *imx_clk_cpu(const char *name, const char *parent_name,
struct clk *div, struct clk *mux, struct clk *pll,
struct clk *step);
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 08/10] clk: imx: implement new clk_hw based APIs
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: Dong Aisheng, ping.bai, Anson.Huang, mturquette, sboyd,
linux-kernel, linux-imx, fabio.estevam, shawnguo,
linux-arm-kernel
Clock providers are recommended to use the new struct clk_hw based API,
so implement IMX clk_hw based provider helpers functions to the new
approach.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2: new patches
---
drivers/clk/imx/clk.c | 22 ++++++++++++++++++
drivers/clk/imx/clk.h | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 84 insertions(+)
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index 9074e69..1efed86 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -18,6 +18,16 @@ void __init imx_check_clocks(struct clk *clks[], unsigned int count)
i, PTR_ERR(clks[i]));
}
+void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count)
+{
+ unsigned int i;
+
+ for (i = 0; i < count; i++)
+ if (IS_ERR(clks[i]))
+ pr_err("i.MX clk %u: register failed with %ld\n",
+ i, PTR_ERR(clks[i]));
+}
+
static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
{
struct of_phandle_args phandle;
@@ -49,6 +59,18 @@ struct clk * __init imx_obtain_fixed_clock(
return clk;
}
+struct clk_hw * __init imx_obtain_fixed_clk_hw(struct device_node *np,
+ const char *name)
+{
+ struct clk *clk;
+
+ clk = of_clk_get_by_name(np, name);
+ if (IS_ERR(clk))
+ return ERR_PTR(-ENOENT);
+
+ return __clk_get_hw(clk);
+}
+
/*
* This fixups the register CCM_CSCMR1 write value.
* The write/read/divider values of the aclk_podf field
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 956155c..3d58420 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -8,6 +8,7 @@
extern spinlock_t imx_ccm_lock;
void imx_check_clocks(struct clk *clks[], unsigned int count);
+void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
void imx_register_uart_clocks(struct clk ** const clks[]);
extern void imx_cscmr1_fixup(u32 *val);
@@ -54,6 +55,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
struct clk * imx_obtain_fixed_clock(
const char *name, unsigned long rate);
+struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
+ const char *name);
+
struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
void __iomem *reg, u8 shift, u32 exclusive_mask);
@@ -90,6 +94,16 @@ static inline struct clk *imx_clk_fixed(const char *name, int rate)
return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
}
+static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
+{
+ return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
+}
+
+static inline struct clk_hw *imx_get_clk_hw_fixed(const char *name, int rate)
+{
+ return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
+}
+
static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
u8 shift, u8 width, const char * const *parents,
int num_parents)
@@ -113,6 +127,15 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_divider(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift,
+ u8 width)
+{
+ return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_divider_flags(const char *name,
const char *parent, void __iomem *reg, u8 shift, u8 width,
unsigned long flags)
@@ -121,6 +144,15 @@ static inline struct clk *imx_clk_divider_flags(const char *name,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift,
+ u8 width, unsigned long flags)
+{
+ return clk_hw_register_divider(NULL, name, parent, flags,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
void __iomem *reg, u8 shift, u8 width)
{
@@ -136,6 +168,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
shift, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent,
+ void __iomem *reg, u8 shift)
+{
+ return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+ shift, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
void __iomem *reg, u8 shift)
{
@@ -208,6 +247,17 @@ static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg,
+ u8 shift, u8 width,
+ const char * const *parents,
+ int num_parents)
+{
+ return clk_hw_register_mux(NULL, name, parents, num_parents,
+ CLK_SET_RATE_NO_REPARENT |
+ CLK_OPS_PARENT_ENABLE,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_mux_flags(const char *name,
void __iomem *reg, u8 shift, u8 width,
const char * const *parents, int num_parents,
@@ -218,6 +268,18 @@ static inline struct clk *imx_clk_mux_flags(const char *name,
&imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name,
+ void __iomem *reg, u8 shift,
+ u8 width,
+ const char * const *parents,
+ int num_parents,
+ unsigned long flags)
+{
+ return clk_hw_register_mux(NULL, name, parents, num_parents,
+ flags | CLK_SET_RATE_NO_REPARENT,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
struct clk *imx_clk_cpu(const char *name, const char *parent_name,
struct clk *div, struct clk *mux, struct clk *pll,
struct clk *step);
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 08/10] clk: imx: implement new clk_hw based APIs
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-arm-kernel
Clock providers are recommended to use the new struct clk_hw based API,
so implement IMX clk_hw based provider helpers functions to the new
approach.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2: new patches
---
drivers/clk/imx/clk.c | 22 ++++++++++++++++++
drivers/clk/imx/clk.h | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 84 insertions(+)
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index 9074e69..1efed86 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -18,6 +18,16 @@ void __init imx_check_clocks(struct clk *clks[], unsigned int count)
i, PTR_ERR(clks[i]));
}
+void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count)
+{
+ unsigned int i;
+
+ for (i = 0; i < count; i++)
+ if (IS_ERR(clks[i]))
+ pr_err("i.MX clk %u: register failed with %ld\n",
+ i, PTR_ERR(clks[i]));
+}
+
static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
{
struct of_phandle_args phandle;
@@ -49,6 +59,18 @@ struct clk * __init imx_obtain_fixed_clock(
return clk;
}
+struct clk_hw * __init imx_obtain_fixed_clk_hw(struct device_node *np,
+ const char *name)
+{
+ struct clk *clk;
+
+ clk = of_clk_get_by_name(np, name);
+ if (IS_ERR(clk))
+ return ERR_PTR(-ENOENT);
+
+ return __clk_get_hw(clk);
+}
+
/*
* This fixups the register CCM_CSCMR1 write value.
* The write/read/divider values of the aclk_podf field
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 956155c..3d58420 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -8,6 +8,7 @@
extern spinlock_t imx_ccm_lock;
void imx_check_clocks(struct clk *clks[], unsigned int count);
+void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
void imx_register_uart_clocks(struct clk ** const clks[]);
extern void imx_cscmr1_fixup(u32 *val);
@@ -54,6 +55,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
struct clk * imx_obtain_fixed_clock(
const char *name, unsigned long rate);
+struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
+ const char *name);
+
struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
void __iomem *reg, u8 shift, u32 exclusive_mask);
@@ -90,6 +94,16 @@ static inline struct clk *imx_clk_fixed(const char *name, int rate)
return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
}
+static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
+{
+ return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
+}
+
+static inline struct clk_hw *imx_get_clk_hw_fixed(const char *name, int rate)
+{
+ return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
+}
+
static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
u8 shift, u8 width, const char * const *parents,
int num_parents)
@@ -113,6 +127,15 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_divider(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift,
+ u8 width)
+{
+ return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_divider_flags(const char *name,
const char *parent, void __iomem *reg, u8 shift, u8 width,
unsigned long flags)
@@ -121,6 +144,15 @@ static inline struct clk *imx_clk_divider_flags(const char *name,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift,
+ u8 width, unsigned long flags)
+{
+ return clk_hw_register_divider(NULL, name, parent, flags,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
void __iomem *reg, u8 shift, u8 width)
{
@@ -136,6 +168,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
shift, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent,
+ void __iomem *reg, u8 shift)
+{
+ return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+ shift, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
void __iomem *reg, u8 shift)
{
@@ -208,6 +247,17 @@ static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg,
+ u8 shift, u8 width,
+ const char * const *parents,
+ int num_parents)
+{
+ return clk_hw_register_mux(NULL, name, parents, num_parents,
+ CLK_SET_RATE_NO_REPARENT |
+ CLK_OPS_PARENT_ENABLE,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_mux_flags(const char *name,
void __iomem *reg, u8 shift, u8 width,
const char * const *parents, int num_parents,
@@ -218,6 +268,18 @@ static inline struct clk *imx_clk_mux_flags(const char *name,
&imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name,
+ void __iomem *reg, u8 shift,
+ u8 width,
+ const char * const *parents,
+ int num_parents,
+ unsigned long flags)
+{
+ return clk_hw_register_mux(NULL, name, parents, num_parents,
+ flags | CLK_SET_RATE_NO_REPARENT,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
struct clk *imx_clk_cpu(const char *name, const char *parent_name,
struct clk *div, struct clk *mux, struct clk *pll,
struct clk *step);
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 09/10] clk: imx: add imx7ulp clk driver
2018-01-19 13:11 ` Dong Aisheng
@ 2018-01-19 13:11 ` Dong Aisheng
-1 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-arm-kernel, sboyd, mturquette, shawnguo,
Anson.Huang, ping.bai, linux-imx, fabio.estevam, Dong Aisheng
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
This driver only adds clock support in A7 domain.
Note that most clocks required to be operated when gated, e.g. pll,
pfd, pcc. And more special cases that scs/ddr/nic mux selecting
different clock source requires that clock to be enabled first,
then we need set CLK_OPS_PARENT_ENABLE flag for them properly.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* use of_clk_add_hw_provider instead
* split the clocks register process into two parts: early part for possible
timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for
the left normal peripheral clocks registered by a platform driver.
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx7ulp.c | 232 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 233 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx7ulp.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index eab606c..f5ff925 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -28,4 +28,5 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o
obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
+obj-$(CONFIG_SOC_IMX7ULP) += clk-imx7ulp.o
obj-$(CONFIG_SOC_VF610) += clk-vf610.o
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
new file mode 100644
index 0000000..1245efc
--- /dev/null
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -0,0 +1,232 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * Author: Dong Aisheng <aisheng.dong@nxp.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "clk.h"
+
+static const char * const pll_pre_sels[] = { "sosc", "firc", };
+static const char * const spll_pfd_sels[] = { "spll_pfd0", "spll_pfd1", "spll_pfd2", "spll_pfd3", };
+static const char * const spll_sels[] = { "spll", "spll_pfd_sel", };
+static const char * const apll_pfd_sels[] = { "apll_pfd0", "apll_pfd1", "apll_pfd2", "apll_pfd3", };
+static const char * const apll_sels[] = { "apll", "apll_pfd_sel", };
+static const char * const scs_sels[] = { "dummy", "sosc", "sirc", "firc", "dummy", "apll_sel", "spll_sel", "upll", };
+static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
+static const char * const nic_sels[] = { "firc", "ddr_clk", };
+static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
+static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
+
+static struct clk_hw_onecell_data *clk_data;
+
+static void __init imx7ulp_clocks_early_init(struct device_node *scg_node)
+{
+ struct device_node *np = scg_node;
+ void __iomem *base;
+ struct clk_hw **clks;
+
+ clk_data = kzalloc(sizeof(*clk_data) +
+ sizeof(*clk_data->hws) * IMX7ULP_CLK_END,
+ GFP_KERNEL);
+ if (!clk_data)
+ return;
+
+ clk_data->num = IMX7ULP_CLK_END;
+ clks = clk_data->hws;
+
+ clks[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
+
+ clks[IMX7ULP_CLK_ROSC] = imx_obtain_fixed_clk_hw(np, "rosc");
+ clks[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc");
+ clks[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc");
+ clks[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc");
+ clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np, "mpll");
+ clks[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll");
+
+ /* SCG1 */
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+
+ /* NOTE: xPLL config can't be changed when xPLL is enabled */
+ clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
+ clks[IMX7ULP_CLK_SPLL_PRE_SEL] = imx_clk_hw_mux_flags("spll_pre_sel", base + 0x608, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
+
+ /* name parent_name reg shift width flags */
+ clks[IMX7ULP_CLK_APLL_PRE_DIV] = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0x508, 8, 3, CLK_SET_RATE_GATE);
+ clks[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x608, 8, 3, CLK_SET_RATE_GATE);
+
+ /* name parent_name base */
+ clks[IMX7ULP_CLK_APLL] = imx_clk_pllv4("apll", "apll_pre_div", base + 0x500);
+ clks[IMX7ULP_CLK_SPLL] = imx_clk_pllv4("spll", "spll_pre_div", base + 0x600);
+
+ /* APLL PFDs */
+ clks[IMX7ULP_CLK_APLL_PFD0] = imx_clk_pfdv2("apll_pfd0", "apll", base + 0x50c, 0);
+ clks[IMX7ULP_CLK_APLL_PFD1] = imx_clk_pfdv2("apll_pfd1", "apll", base + 0x50c, 1);
+ clks[IMX7ULP_CLK_APLL_PFD2] = imx_clk_pfdv2("apll_pfd2", "apll", base + 0x50c, 2);
+ clks[IMX7ULP_CLK_APLL_PFD3] = imx_clk_pfdv2("apll_pfd3", "apll", base + 0x50c, 3);
+
+ /* SPLL PFDs */
+ clks[IMX7ULP_CLK_SPLL_PFD0] = imx_clk_pfdv2("spll_pfd0", "spll", base + 0x60C, 0);
+ clks[IMX7ULP_CLK_SPLL_PFD1] = imx_clk_pfdv2("spll_pfd1", "spll", base + 0x60C, 1);
+ clks[IMX7ULP_CLK_SPLL_PFD2] = imx_clk_pfdv2("spll_pfd2", "spll", base + 0x60C, 2);
+ clks[IMX7ULP_CLK_SPLL_PFD3] = imx_clk_pfdv2("spll_pfd3", "spll", base + 0x60C, 3);
+
+ /* PLL Mux */
+ clks[IMX7ULP_CLK_APLL_PFD_SEL] = imx_clk_hw_mux_flags("apll_pfd_sel", base + 0x508, 14, 2, apll_pfd_sels, ARRAY_SIZE(apll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
+ clks[IMX7ULP_CLK_SPLL_PFD_SEL] = imx_clk_hw_mux_flags("spll_pfd_sel", base + 0x608, 14, 2, spll_pfd_sels, ARRAY_SIZE(spll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
+ clks[IMX7ULP_CLK_APLL_SEL] = imx_clk_hw_mux_flags("apll_sel", base + 0x508, 1, 1, apll_sels, ARRAY_SIZE(apll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
+ clks[IMX7ULP_CLK_SPLL_SEL] = imx_clk_hw_mux_flags("spll_sel", base + 0x608, 1, 1, spll_sels, ARRAY_SIZE(spll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
+
+ clks[IMX7ULP_CLK_SPLL_BUS_CLK] = clk_hw_register_divider(NULL, "spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ZERO_GATE, &imx_ccm_lock);
+
+ /* scs/ddr/nic select different clock source requires that clock to be enabled first */
+ clks[IMX7ULP_CLK_SYS_SEL] = imx_clk_hw_mux2("scs_sel", base + 0x14, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));
+ clks[IMX7ULP_CLK_NIC_SEL] = imx_clk_hw_mux2("nic_sel", base + 0x40, 28, 1, nic_sels, ARRAY_SIZE(nic_sels));
+ clks[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 1, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
+
+ clks[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
+
+ clks[IMX7ULP_CLK_DDR_DIV] = clk_hw_register_divider(NULL, "ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ZERO_GATE, &imx_ccm_lock);
+
+ clks[IMX7ULP_CLK_NIC0_DIV] = imx_clk_hw_divider_flags("nic0_clk", "nic_sel", base + 0x40, 24, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
+ clks[IMX7ULP_CLK_NIC1_DIV] = imx_clk_hw_divider_flags("nic1_clk", "nic0_clk", base + 0x40, 16, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
+ clks[IMX7ULP_CLK_NIC1_BUS_DIV] = imx_clk_hw_divider_flags("nic1_bus_clk", "nic1_clk", base + 0x40, 4, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
+
+ clks[IMX7ULP_CLK_SOSC_BUS_CLK] = clk_hw_register_divider(NULL, "sosc_bus_clk", "sosc", 0, base + 0x104, 8, 3,
+ CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ZERO_GATE, &imx_ccm_lock);
+ clks[IMX7ULP_CLK_FIRC_BUS_CLK] = clk_hw_register_divider(NULL, "firc_bus_clk", "firc", 0, base + 0x304, 8, 3,
+ CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ZERO_GATE, &imx_ccm_lock);
+
+ /* PCC2 */
+ base = of_iomap(np, 1);
+ WARN_ON(!base);
+
+ clks[IMX7ULP_CLK_LPTPM4] = imx_clk_composite("lptpm4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94);
+ clks[IMX7ULP_CLK_LPTPM5] = imx_clk_composite("lptpm5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98);
+ clks[IMX7ULP_CLK_LPIT1] = imx_clk_composite("lpit1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9c);
+
+ /* PCC3 */
+ base = of_iomap(np, 2);
+ WARN_ON(!base);
+
+ clks[IMX7ULP_CLK_LPTPM6] = imx_clk_composite("lptpm6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x84);
+ clks[IMX7ULP_CLK_LPTPM7] = imx_clk_composite("lptpm7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x88);
+
+ clks[IMX7ULP_CLK_MMDC] = clk_hw_register_gate(NULL, "mmdc", "nic1_clk", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ base + 0xac, 30, 0, &imx_ccm_lock);
+
+ imx_check_clk_hws(clks, clk_data->num);
+
+ of_clk_add_hw_provider(scg_node, of_clk_hw_onecell_get, clk_data);
+}
+CLK_OF_DECLARE_DRIVER(imx7ulp, "fsl,imx7ulp-clock", imx7ulp_clocks_early_init);
+
+static const struct of_device_id imx7ulp_clk_dt_ids[] = {
+ { .compatible = "fsl,imx7ulp-clock" },
+ { /* sentinel */ }
+};
+
+static int imx7ulp_clk_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct clk_hw **clks = clk_data->hws;
+ struct resource *res;
+ void __iomem *base;
+
+ /* PCC2 */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scg1");
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clks[IMX7ULP_CLK_GPU_DIV] = imx_clk_hw_divider("gpu_clk", "nic0_clk", base + 0x40, 20, 4);
+
+ /* PCC2 */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcc2");
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clks[IMX7ULP_CLK_DMA1] = imx_clk_hw_gate("dma1", "nic1_clk", base + 0x20, 30);
+ clks[IMX7ULP_CLK_RGPIO2P1] = imx_clk_hw_gate("rgpio2p1", "nic1_bus_clk", base + 0x3c, 30);
+ clks[IMX7ULP_CLK_DMA_MUX1] = imx_clk_hw_gate("dma_mux1", "nic1_bus_clk", base + 0x84, 30);
+ clks[IMX7ULP_CLK_SNVS] = imx_clk_hw_gate("snvs", "nic1_bus_clk", base + 0x8c, 30);
+ clks[IMX7ULP_CLK_CAAM] = imx_clk_hw_gate("caam", "nic1_clk", base + 0x90, 30);
+ clks[IMX7ULP_CLK_LPSPI2] = imx_clk_composite("lpspi2", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xa4);
+ clks[IMX7ULP_CLK_LPSPI3] = imx_clk_composite("lpspi3", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xa8);
+ clks[IMX7ULP_CLK_LPI2C4] = imx_clk_composite("lpi2c4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xac);
+ clks[IMX7ULP_CLK_LPI2C5] = imx_clk_composite("lpi2c5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb0);
+ clks[IMX7ULP_CLK_LPUART4] = imx_clk_composite("lpuart4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb4);
+ clks[IMX7ULP_CLK_LPUART5] = imx_clk_composite("lpuart5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb8);
+ clks[IMX7ULP_CLK_FLEXIO1] = imx_clk_composite("flexio1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xc4);
+ clks[IMX7ULP_CLK_USB0] = imx_clk_composite("usb0", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xcc);
+ clks[IMX7ULP_CLK_USB1] = imx_clk_composite("usb1", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xd0);
+ clks[IMX7ULP_CLK_USB_PHY] = imx_clk_hw_gate("usb_phy", "nic1_bus_clk", base + 0xD4, 30);
+ clks[IMX7ULP_CLK_USDHC0] = imx_clk_composite("usdhc0", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xdc);
+ clks[IMX7ULP_CLK_USDHC1] = imx_clk_composite("usdhc1", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xe0);
+ clks[IMX7ULP_CLK_WDG1] = imx_clk_composite("wdg1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0xf4);
+ clks[IMX7ULP_CLK_WDG2] = imx_clk_composite("sdg2", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0x10c);
+
+ /* PCC3 */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcc3");
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clks[IMX7ULP_CLK_LPI2C6] = imx_clk_composite("lpi2c6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x90);
+ clks[IMX7ULP_CLK_LPI2C7] = imx_clk_composite("lpi2c7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94);
+ clks[IMX7ULP_CLK_LPUART6] = imx_clk_composite("lpuart6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98);
+ clks[IMX7ULP_CLK_LPUART7] = imx_clk_composite("lpuart7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9c);
+ clks[IMX7ULP_CLK_DSI] = imx_clk_composite("dsi", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0xa4);
+ clks[IMX7ULP_CLK_LCDIF] = imx_clk_composite("lcdif", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xa8);
+
+ clks[IMX7ULP_CLK_VIU] = imx_clk_hw_gate("viu", "nic1_clk", base + 0xa0, 30);
+ clks[IMX7ULP_CLK_PCTLC] = imx_clk_hw_gate("pctlc", "nic1_bus_clk", base + 0xb8, 30);
+ clks[IMX7ULP_CLK_PCTLD] = imx_clk_hw_gate("pctld", "nic1_bus_clk", base + 0xbc, 30);
+ clks[IMX7ULP_CLK_PCTLE] = imx_clk_hw_gate("pctle", "nic1_bus_clk", base + 0xc0, 30);
+ clks[IMX7ULP_CLK_PCTLF] = imx_clk_hw_gate("pctlf", "nic1_bus_clk", base + 0xc4, 30);
+
+ clks[IMX7ULP_CLK_GPU3D] = imx_clk_composite("gpu3d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x140);
+ clks[IMX7ULP_CLK_GPU2D] = imx_clk_composite("gpu2d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x144);
+
+ imx_check_clk_hws(clks, clk_data->num);
+
+ of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
+
+ pr_debug("i.MX7ULP clock tree init done.\n");
+
+ return 0;
+}
+
+static struct platform_driver imx7ulp_clk_driver = {
+ .driver = {
+ .name = "imx7ulp-clock",
+ .of_match_table = imx7ulp_clk_dt_ids,
+ },
+ .probe = imx7ulp_clk_probe,
+};
+
+static int __init imx7ulp_clk_init(void)
+{
+ return platform_driver_register(&imx7ulp_clk_driver);
+}
+core_initcall(imx7ulp_clk_init);
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 09/10] clk: imx: add imx7ulp clk driver
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-arm-kernel
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
This driver only adds clock support in A7 domain.
Note that most clocks required to be operated when gated, e.g. pll,
pfd, pcc. And more special cases that scs/ddr/nic mux selecting
different clock source requires that clock to be enabled first,
then we need set CLK_OPS_PARENT_ENABLE flag for them properly.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* use of_clk_add_hw_provider instead
* split the clocks register process into two parts: early part for possible
timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for
the left normal peripheral clocks registered by a platform driver.
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx7ulp.c | 232 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 233 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx7ulp.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index eab606c..f5ff925 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -28,4 +28,5 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o
obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
+obj-$(CONFIG_SOC_IMX7ULP) += clk-imx7ulp.o
obj-$(CONFIG_SOC_VF610) += clk-vf610.o
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
new file mode 100644
index 0000000..1245efc
--- /dev/null
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -0,0 +1,232 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * Author: Dong Aisheng <aisheng.dong@nxp.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "clk.h"
+
+static const char * const pll_pre_sels[] = { "sosc", "firc", };
+static const char * const spll_pfd_sels[] = { "spll_pfd0", "spll_pfd1", "spll_pfd2", "spll_pfd3", };
+static const char * const spll_sels[] = { "spll", "spll_pfd_sel", };
+static const char * const apll_pfd_sels[] = { "apll_pfd0", "apll_pfd1", "apll_pfd2", "apll_pfd3", };
+static const char * const apll_sels[] = { "apll", "apll_pfd_sel", };
+static const char * const scs_sels[] = { "dummy", "sosc", "sirc", "firc", "dummy", "apll_sel", "spll_sel", "upll", };
+static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
+static const char * const nic_sels[] = { "firc", "ddr_clk", };
+static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
+static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
+
+static struct clk_hw_onecell_data *clk_data;
+
+static void __init imx7ulp_clocks_early_init(struct device_node *scg_node)
+{
+ struct device_node *np = scg_node;
+ void __iomem *base;
+ struct clk_hw **clks;
+
+ clk_data = kzalloc(sizeof(*clk_data) +
+ sizeof(*clk_data->hws) * IMX7ULP_CLK_END,
+ GFP_KERNEL);
+ if (!clk_data)
+ return;
+
+ clk_data->num = IMX7ULP_CLK_END;
+ clks = clk_data->hws;
+
+ clks[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
+
+ clks[IMX7ULP_CLK_ROSC] = imx_obtain_fixed_clk_hw(np, "rosc");
+ clks[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc");
+ clks[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc");
+ clks[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc");
+ clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np, "mpll");
+ clks[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll");
+
+ /* SCG1 */
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+
+ /* NOTE: xPLL config can't be changed when xPLL is enabled */
+ clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
+ clks[IMX7ULP_CLK_SPLL_PRE_SEL] = imx_clk_hw_mux_flags("spll_pre_sel", base + 0x608, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
+
+ /* name parent_name reg shift width flags */
+ clks[IMX7ULP_CLK_APLL_PRE_DIV] = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0x508, 8, 3, CLK_SET_RATE_GATE);
+ clks[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x608, 8, 3, CLK_SET_RATE_GATE);
+
+ /* name parent_name base */
+ clks[IMX7ULP_CLK_APLL] = imx_clk_pllv4("apll", "apll_pre_div", base + 0x500);
+ clks[IMX7ULP_CLK_SPLL] = imx_clk_pllv4("spll", "spll_pre_div", base + 0x600);
+
+ /* APLL PFDs */
+ clks[IMX7ULP_CLK_APLL_PFD0] = imx_clk_pfdv2("apll_pfd0", "apll", base + 0x50c, 0);
+ clks[IMX7ULP_CLK_APLL_PFD1] = imx_clk_pfdv2("apll_pfd1", "apll", base + 0x50c, 1);
+ clks[IMX7ULP_CLK_APLL_PFD2] = imx_clk_pfdv2("apll_pfd2", "apll", base + 0x50c, 2);
+ clks[IMX7ULP_CLK_APLL_PFD3] = imx_clk_pfdv2("apll_pfd3", "apll", base + 0x50c, 3);
+
+ /* SPLL PFDs */
+ clks[IMX7ULP_CLK_SPLL_PFD0] = imx_clk_pfdv2("spll_pfd0", "spll", base + 0x60C, 0);
+ clks[IMX7ULP_CLK_SPLL_PFD1] = imx_clk_pfdv2("spll_pfd1", "spll", base + 0x60C, 1);
+ clks[IMX7ULP_CLK_SPLL_PFD2] = imx_clk_pfdv2("spll_pfd2", "spll", base + 0x60C, 2);
+ clks[IMX7ULP_CLK_SPLL_PFD3] = imx_clk_pfdv2("spll_pfd3", "spll", base + 0x60C, 3);
+
+ /* PLL Mux */
+ clks[IMX7ULP_CLK_APLL_PFD_SEL] = imx_clk_hw_mux_flags("apll_pfd_sel", base + 0x508, 14, 2, apll_pfd_sels, ARRAY_SIZE(apll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
+ clks[IMX7ULP_CLK_SPLL_PFD_SEL] = imx_clk_hw_mux_flags("spll_pfd_sel", base + 0x608, 14, 2, spll_pfd_sels, ARRAY_SIZE(spll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
+ clks[IMX7ULP_CLK_APLL_SEL] = imx_clk_hw_mux_flags("apll_sel", base + 0x508, 1, 1, apll_sels, ARRAY_SIZE(apll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
+ clks[IMX7ULP_CLK_SPLL_SEL] = imx_clk_hw_mux_flags("spll_sel", base + 0x608, 1, 1, spll_sels, ARRAY_SIZE(spll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
+
+ clks[IMX7ULP_CLK_SPLL_BUS_CLK] = clk_hw_register_divider(NULL, "spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ZERO_GATE, &imx_ccm_lock);
+
+ /* scs/ddr/nic select different clock source requires that clock to be enabled first */
+ clks[IMX7ULP_CLK_SYS_SEL] = imx_clk_hw_mux2("scs_sel", base + 0x14, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));
+ clks[IMX7ULP_CLK_NIC_SEL] = imx_clk_hw_mux2("nic_sel", base + 0x40, 28, 1, nic_sels, ARRAY_SIZE(nic_sels));
+ clks[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 1, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
+
+ clks[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
+
+ clks[IMX7ULP_CLK_DDR_DIV] = clk_hw_register_divider(NULL, "ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ZERO_GATE, &imx_ccm_lock);
+
+ clks[IMX7ULP_CLK_NIC0_DIV] = imx_clk_hw_divider_flags("nic0_clk", "nic_sel", base + 0x40, 24, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
+ clks[IMX7ULP_CLK_NIC1_DIV] = imx_clk_hw_divider_flags("nic1_clk", "nic0_clk", base + 0x40, 16, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
+ clks[IMX7ULP_CLK_NIC1_BUS_DIV] = imx_clk_hw_divider_flags("nic1_bus_clk", "nic1_clk", base + 0x40, 4, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
+
+ clks[IMX7ULP_CLK_SOSC_BUS_CLK] = clk_hw_register_divider(NULL, "sosc_bus_clk", "sosc", 0, base + 0x104, 8, 3,
+ CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ZERO_GATE, &imx_ccm_lock);
+ clks[IMX7ULP_CLK_FIRC_BUS_CLK] = clk_hw_register_divider(NULL, "firc_bus_clk", "firc", 0, base + 0x304, 8, 3,
+ CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ZERO_GATE, &imx_ccm_lock);
+
+ /* PCC2 */
+ base = of_iomap(np, 1);
+ WARN_ON(!base);
+
+ clks[IMX7ULP_CLK_LPTPM4] = imx_clk_composite("lptpm4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94);
+ clks[IMX7ULP_CLK_LPTPM5] = imx_clk_composite("lptpm5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98);
+ clks[IMX7ULP_CLK_LPIT1] = imx_clk_composite("lpit1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9c);
+
+ /* PCC3 */
+ base = of_iomap(np, 2);
+ WARN_ON(!base);
+
+ clks[IMX7ULP_CLK_LPTPM6] = imx_clk_composite("lptpm6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x84);
+ clks[IMX7ULP_CLK_LPTPM7] = imx_clk_composite("lptpm7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x88);
+
+ clks[IMX7ULP_CLK_MMDC] = clk_hw_register_gate(NULL, "mmdc", "nic1_clk", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ base + 0xac, 30, 0, &imx_ccm_lock);
+
+ imx_check_clk_hws(clks, clk_data->num);
+
+ of_clk_add_hw_provider(scg_node, of_clk_hw_onecell_get, clk_data);
+}
+CLK_OF_DECLARE_DRIVER(imx7ulp, "fsl,imx7ulp-clock", imx7ulp_clocks_early_init);
+
+static const struct of_device_id imx7ulp_clk_dt_ids[] = {
+ { .compatible = "fsl,imx7ulp-clock" },
+ { /* sentinel */ }
+};
+
+static int imx7ulp_clk_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct clk_hw **clks = clk_data->hws;
+ struct resource *res;
+ void __iomem *base;
+
+ /* PCC2 */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scg1");
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clks[IMX7ULP_CLK_GPU_DIV] = imx_clk_hw_divider("gpu_clk", "nic0_clk", base + 0x40, 20, 4);
+
+ /* PCC2 */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcc2");
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clks[IMX7ULP_CLK_DMA1] = imx_clk_hw_gate("dma1", "nic1_clk", base + 0x20, 30);
+ clks[IMX7ULP_CLK_RGPIO2P1] = imx_clk_hw_gate("rgpio2p1", "nic1_bus_clk", base + 0x3c, 30);
+ clks[IMX7ULP_CLK_DMA_MUX1] = imx_clk_hw_gate("dma_mux1", "nic1_bus_clk", base + 0x84, 30);
+ clks[IMX7ULP_CLK_SNVS] = imx_clk_hw_gate("snvs", "nic1_bus_clk", base + 0x8c, 30);
+ clks[IMX7ULP_CLK_CAAM] = imx_clk_hw_gate("caam", "nic1_clk", base + 0x90, 30);
+ clks[IMX7ULP_CLK_LPSPI2] = imx_clk_composite("lpspi2", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xa4);
+ clks[IMX7ULP_CLK_LPSPI3] = imx_clk_composite("lpspi3", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xa8);
+ clks[IMX7ULP_CLK_LPI2C4] = imx_clk_composite("lpi2c4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xac);
+ clks[IMX7ULP_CLK_LPI2C5] = imx_clk_composite("lpi2c5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb0);
+ clks[IMX7ULP_CLK_LPUART4] = imx_clk_composite("lpuart4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb4);
+ clks[IMX7ULP_CLK_LPUART5] = imx_clk_composite("lpuart5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb8);
+ clks[IMX7ULP_CLK_FLEXIO1] = imx_clk_composite("flexio1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xc4);
+ clks[IMX7ULP_CLK_USB0] = imx_clk_composite("usb0", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xcc);
+ clks[IMX7ULP_CLK_USB1] = imx_clk_composite("usb1", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xd0);
+ clks[IMX7ULP_CLK_USB_PHY] = imx_clk_hw_gate("usb_phy", "nic1_bus_clk", base + 0xD4, 30);
+ clks[IMX7ULP_CLK_USDHC0] = imx_clk_composite("usdhc0", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xdc);
+ clks[IMX7ULP_CLK_USDHC1] = imx_clk_composite("usdhc1", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xe0);
+ clks[IMX7ULP_CLK_WDG1] = imx_clk_composite("wdg1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0xf4);
+ clks[IMX7ULP_CLK_WDG2] = imx_clk_composite("sdg2", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0x10c);
+
+ /* PCC3 */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcc3");
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clks[IMX7ULP_CLK_LPI2C6] = imx_clk_composite("lpi2c6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x90);
+ clks[IMX7ULP_CLK_LPI2C7] = imx_clk_composite("lpi2c7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94);
+ clks[IMX7ULP_CLK_LPUART6] = imx_clk_composite("lpuart6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98);
+ clks[IMX7ULP_CLK_LPUART7] = imx_clk_composite("lpuart7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9c);
+ clks[IMX7ULP_CLK_DSI] = imx_clk_composite("dsi", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0xa4);
+ clks[IMX7ULP_CLK_LCDIF] = imx_clk_composite("lcdif", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xa8);
+
+ clks[IMX7ULP_CLK_VIU] = imx_clk_hw_gate("viu", "nic1_clk", base + 0xa0, 30);
+ clks[IMX7ULP_CLK_PCTLC] = imx_clk_hw_gate("pctlc", "nic1_bus_clk", base + 0xb8, 30);
+ clks[IMX7ULP_CLK_PCTLD] = imx_clk_hw_gate("pctld", "nic1_bus_clk", base + 0xbc, 30);
+ clks[IMX7ULP_CLK_PCTLE] = imx_clk_hw_gate("pctle", "nic1_bus_clk", base + 0xc0, 30);
+ clks[IMX7ULP_CLK_PCTLF] = imx_clk_hw_gate("pctlf", "nic1_bus_clk", base + 0xc4, 30);
+
+ clks[IMX7ULP_CLK_GPU3D] = imx_clk_composite("gpu3d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x140);
+ clks[IMX7ULP_CLK_GPU2D] = imx_clk_composite("gpu2d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x144);
+
+ imx_check_clk_hws(clks, clk_data->num);
+
+ of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
+
+ pr_debug("i.MX7ULP clock tree init done.\n");
+
+ return 0;
+}
+
+static struct platform_driver imx7ulp_clk_driver = {
+ .driver = {
+ .name = "imx7ulp-clock",
+ .of_match_table = imx7ulp_clk_dt_ids,
+ },
+ .probe = imx7ulp_clk_probe,
+};
+
+static int __init imx7ulp_clk_init(void)
+{
+ return platform_driver_register(&imx7ulp_clk_driver);
+}
+core_initcall(imx7ulp_clk_init);
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 10/10] add imx7ulp support
2018-01-19 13:11 ` Dong Aisheng
(?)
@ 2018-01-19 13:11 ` Dong Aisheng
-1 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-arm-kernel, sboyd, mturquette, shawnguo,
Anson.Huang, ping.bai, linux-imx, fabio.estevam, Dong Aisheng
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/imx7ulp-evk.dts | 87 +++++++++++++++
arch/arm/boot/dts/imx7ulp.dtsi | 202 +++++++++++++++++++++++++++++++++++
arch/arm/configs/imx_v6_v7_defconfig | 16 ++-
arch/arm/mach-imx/Kconfig | 9 ++
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/cpu.c | 3 +
arch/arm/mach-imx/mach-imx7ulp.c | 37 +++++++
arch/arm/mach-imx/mxc.h | 1 +
arch/arm/mach-imx/pm-imx7ulp.c | 32 ++++++
11 files changed, 381 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0381e9..3257e71 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -519,6 +519,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-sdb-sht11.dtb \
imx7s-colibri-eval-v3.dtb \
imx7s-warp.dtb
+dtb-$(CONFIG_SOC_IMX7ULP) += \
+ imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-qds.dtb \
ls1021a-twr.dtb
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
new file mode 100644
index 0000000..cc4e6ef
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+ model = "NXP i.MX7ULP EVK";
+ compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
+
+ chosen {
+ bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
+ stdout-path = &lpuart4;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+};
+
+&lpuart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart4>;
+ status = "okay";
+};
+
+&usdhc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>;
+// <&pinctrl_usdhc0_cd>, <&pinctrl_usdhc0_rst>;
+ status = "okay";
+};
+
+&iomuxc1 {
+ pinctrl_lpuart4: lpuart4grp {
+ pins = <
+ IMX7ULP_PAD_PTC3__LPUART4_RX
+ IMX7ULP_PAD_PTC2__LPUART4_TX
+ >;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc0_cmd_data: usdhc0_cmd_data_0_3_grp {
+ pins = <
+ IMX7ULP_PAD_PTD1__SDHC0_CMD
+ IMX7ULP_PAD_PTD2__SDHC0_CLK
+ IMX7ULP_PAD_PTD7__SDHC0_D3
+ IMX7ULP_PAD_PTD8__SDHC0_D2
+ IMX7ULP_PAD_PTD9__SDHC0_D1
+ IMX7ULP_PAD_PTD10__SDHC0_D0
+ >;
+ drive-strength = <1>;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc0_clk: usdhc0_clk_grp {
+ pins = <
+ IMX7ULP_PAD_PTD2__SDHC0_CLK
+ >;
+ drive-strength = <1>;
+ bias-pull-down;
+ };
+
+ pinctrl_usdhc0_cd: usdhc0_gpios_cd_grp {
+ pins = <
+ IMX7ULP_PAD_PTC10__PTC10 /* USDHC0 CD */
+ >;
+ nxp,input-buffer-enable;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc0_rst: usdhc0_gpios_rst_grp {
+ pins = <
+ IMX7ULP_PAD_PTD0__PTD0 /* USDHC0 RST */
+ >;
+ nxp,output-buffer-enable;
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
new file mode 100644
index 0000000..05410ba
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -0,0 +1,202 @@
+/*
+ * Copyright NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+
+#include "imx7ulp-pinfunc.h"
+
+/ {
+ interrupt-parent = <&intc>;
+
+ aliases {
+ serial0 = &lpuart4;
+ serial1 = &lpuart6;
+ serial2 = &lpuart5;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ intc: interrupt-controller@40021000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x40021000 0x1000>,
+ <0x40022000 0x100>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rosc: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "rosc";
+ #clock-cells = <0>;
+ };
+
+ sosc: clock@1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ clock-frequency = <24000000>;
+ clock-output-names = "sosc";
+ #clock-cells = <0>;
+ };
+
+ sirc: clock@2 {
+ compatible = "fixed-clock";
+ reg = <2>;
+ clock-frequency = <16000000>;
+ clock-output-names = "sirc";
+ #clock-cells = <0>;
+ };
+
+ firc: clock@3 {
+ compatible = "fixed-clock";
+ reg = <3>;
+ clock-frequency = <48000000>;
+ clock-output-names = "firc";
+ #clock-cells = <0>;
+ };
+
+ upll: clock@4 {
+ compatible = "fixed-clock";
+ reg = <4>;
+ clock-frequency = <480000000>;
+ clock-output-names = "upll";
+ #clock-cells = <0>;
+ };
+
+ mpll: clock@5 {
+ compatible = "fixed-clock";
+ reg = <5>;
+ clock-frequency = <480000000>;
+ clock-output-names = "mpll";
+ #clock-cells = <0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ arm,cpu-registers-not-fw-configured;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&intc>;
+ clock-frequency = <1000000>;
+ status = "disabled";
+ };
+
+ sram: sram@20000000 {
+ compatible = "fsl,lpm-sram";
+ reg = <0x20008000 0x4000>;
+ };
+
+ ahbbridge0: ahb-bridge0@40000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40000000 0x800000>;
+ ranges;
+
+ lpuart4: serial@402D0000 {
+ compatible = "fsl,imx7ulp-lpuart";
+ reg = <0x402D0000 0x1000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_LPUART4>;
+ clock-names = "ipg";
+ assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>;
+ assigned-clock-rates = <24000000>;
+ status = "disabled";
+ };
+
+ lpuart5: serial@402E0000 {
+ compatible = "fsl,imx7ulp-lpuart";
+ reg = <0x402E0000 0x1000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clock-rates = <48000000>;
+ status = "disabled";
+ };
+
+ tpm5: tpm@40260000 {
+ compatible = "fsl,imx7ulp-tpm";
+ reg = <0x40260000 0x1000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&clks IMX7ULP_CLK_LPTPM5>;
+ clock-names = "ipg", "per";
+ };
+
+ usdhc0: usdhc@40370000 {
+ compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x40370000 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&clks IMX7ULP_CLK_NIC1_DIV>,
+ <&clks IMX7ULP_CLK_USDHC0>;
+ clock-names ="ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ clks: scg1@403e0000 {
+ compatible = "fsl,imx7ulp-clock";
+ reg = <0x403e0000 0x10000>,
+ <0x403f0000 0x10000>,
+ <0x40b30000 0x10000>;
+ reg-names = "scg1", "pcc2", "pcc3";
+ clocks = <&rosc>, <&sosc>, <&sirc>,
+ <&firc>, <&upll>, <&mpll>;
+ clock-names = "rosc", "sosc", "sirc",
+ "firc", "upll", "mpll";
+ assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
+ <&clks IMX7ULP_CLK_USDHC1>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>,
+ <&clks IMX7ULP_CLK_NIC1_DIV>;
+ #clock-cells = <1>;
+ };
+
+ smc1: smc1@40410000 {
+ compatible = "fsl,imx7ulp-smc1";
+ reg = <0x40410000 0x1000>;
+ };
+ };
+
+ ahbbridge1: ahb-bridge1@40800000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40800000 0x800000>;
+ ranges;
+
+ iomuxc1: iomuxc1@40ac0000 {
+ compatible = "fsl,imx7ulp-iomuxc1";
+ reg = <0x40ac0000 0x1000>;
+ };
+
+ lpuart6: serial@40A60000 {
+ compatible = "fsl,imx7ulp-lpuart";
+ reg = <0x40A60000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 0d44949..3ce8ff6 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -41,6 +41,7 @@ CONFIG_SOC_IMX6SL=y
CONFIG_SOC_IMX6SX=y
CONFIG_SOC_IMX6UL=y
CONFIG_SOC_IMX7D=y
+CONFIG_SOC_IMX7ULP=y
CONFIG_SOC_VF610=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
@@ -48,9 +49,7 @@ CONFIG_PCI_IMX6=y
CONFIG_SMP=y
CONFIG_ARM_PSCI=y
CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_AEABI=y
CONFIG_HIGHMEM=y
-CONFIG_CMA=y
CONFIG_FORCE_MAX_ZONEORDER=14
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
CONFIG_KEXEC=y
@@ -81,7 +80,6 @@ CONFIG_CAN_FLEXCAN=y
CONFIG_BT=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
CONFIG_CFG80211=y
CONFIG_CFG80211_WEXT=y
CONFIG_MAC80211=y
@@ -90,7 +88,6 @@ CONFIG_RFKILL_INPUT=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
-CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_IMX_WEIM=y
CONFIG_CONNECTOR=y
@@ -167,9 +164,9 @@ CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_TOUCHSCREEN_EGALAX=y
+CONFIG_TOUCHSCREEN_MAX11801=y
CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
CONFIG_TOUCHSCREEN_EDT_FT5X06=y
-CONFIG_TOUCHSCREEN_MAX11801=y
CONFIG_TOUCHSCREEN_MC13783=y
CONFIG_TOUCHSCREEN_TSC2004=y
CONFIG_TOUCHSCREEN_TSC2007=y
@@ -178,7 +175,6 @@ CONFIG_TOUCHSCREEN_SX8654=y
CONFIG_TOUCHSCREEN_COLIBRI_VF50=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_MMA8450=y
-CONFIG_HID_MULTITOUCH=y
CONFIG_SERIO_SERPORT=m
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_IMX=y
@@ -228,13 +224,13 @@ CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
CONFIG_REGULATOR_PFUZE100=y
+CONFIG_RC_CORE=y
+CONFIG_RC_DEVICES=y
+CONFIG_IR_GPIO_CIR=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_RC_CORE=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
-CONFIG_RC_DEVICES=y
-CONFIG_IR_GPIO_CIR=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
@@ -245,7 +241,6 @@ CONFIG_VIDEO_CODA=m
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_OV5640=m
-CONFIG_SOC_CAMERA_OV2640=y
CONFIG_IMX_IPUV3_CORE=y
CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
@@ -283,6 +278,7 @@ CONFIG_SND_SOC_CS42XX8_I2C=y
CONFIG_SND_SOC_TLV320AIC3X=y
CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SIMPLE_CARD=y
+CONFIG_HID_MULTITOUCH=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 782699e..54002c3 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -554,6 +554,15 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
+config SOC_IMX7ULP
+ bool "i.MX7ULP support"
+ select ARM_GIC
+ select CLKSRC_IMX_TPM
+ select HAVE_ARM_ARCH_TIMER
+ select PINCTRL_IMX7ULP
+ help
+ This enables support for Freescale i.MX7 Ultra Low Power processor.
+
config SOC_VF610
bool "Vybrid Family VF610 support"
select ARM_GIC if ARCH_MULTI_V7
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 8ff7105..69c2517 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -81,6 +81,7 @@ obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o
obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o
+obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
ifeq ($(CONFIG_SUSPEND),y)
AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index b09a2ec..b0e85df 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -128,6 +128,7 @@ void imx6dl_pm_init(void);
void imx6sl_pm_init(void);
void imx6sx_pm_init(void);
void imx6ul_pm_init(void);
+void imx7ulp_pm_init(void);
#ifdef CONFIG_PM
void imx51_pm_init(void);
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index d4e55f2..46f344f 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -138,6 +138,9 @@ struct device * __init imx_soc_device_init(void)
case MXC_CPU_IMX7D:
soc_id = "i.MX7D";
break;
+ case MXC_CPU_IMX7ULP:
+ soc_id = "i.MX7ULP";
+ break;
default:
soc_id = "Unknown";
}
diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c
new file mode 100644
index 0000000..9f7a25c
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx7ulp.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+#include "hardware.h"
+
+static void __init imx7ulp_init_machine(void)
+{
+ imx7ulp_pm_init();
+
+ mxc_set_cpu_type(MXC_CPU_IMX7ULP);
+ imx_print_silicon_rev("i.MX7ULP", IMX_CHIP_REVISION_1_0);
+ of_platform_default_populate(NULL, NULL, imx_soc_device_init());
+}
+
+static const char *const imx7ulp_dt_compat[] __initconst = {
+ "fsl,imx7ulp",
+ NULL,
+};
+
+DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
+ .init_machine = imx7ulp_init_machine,
+ .dt_compat = imx7ulp_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index e00d626..ac9677b 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -41,6 +41,7 @@
#define MXC_CPU_IMX6UL 0x64
#define MXC_CPU_IMX6ULL 0x65
#define MXC_CPU_IMX7D 0x72
+#define MXC_CPU_IMX7ULP 0xff
#define IMX_DDR_TYPE_LPDDR2 1
diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c
new file mode 100644
index 0000000..00401e0
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx7ulp.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define SMC_PMCTRL 0x10
+#define BP_PMCTRL_PSTOPO 16
+#define PSTOPO_PSTOP3 0x3
+
+void __init imx7ulp_pm_init(void)
+{
+ struct device_node *np;
+ void __iomem *smc1_base;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
+ smc1_base = of_iomap(np, 0);
+ WARN_ON(!smc1_base);
+
+ /* Partial Stop mode 3 with system/bus clock enabled */
+ writel_relaxed(PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO, smc1_base + SMC_PMCTRL);
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 10/10] add imx7ulp support
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-clk
Cc: Dong Aisheng, ping.bai, Anson.Huang, mturquette, sboyd,
linux-kernel, linux-imx, fabio.estevam, shawnguo,
linux-arm-kernel
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/imx7ulp-evk.dts | 87 +++++++++++++++
arch/arm/boot/dts/imx7ulp.dtsi | 202 +++++++++++++++++++++++++++++++++++
arch/arm/configs/imx_v6_v7_defconfig | 16 ++-
arch/arm/mach-imx/Kconfig | 9 ++
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/cpu.c | 3 +
arch/arm/mach-imx/mach-imx7ulp.c | 37 +++++++
arch/arm/mach-imx/mxc.h | 1 +
arch/arm/mach-imx/pm-imx7ulp.c | 32 ++++++
11 files changed, 381 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0381e9..3257e71 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -519,6 +519,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-sdb-sht11.dtb \
imx7s-colibri-eval-v3.dtb \
imx7s-warp.dtb
+dtb-$(CONFIG_SOC_IMX7ULP) += \
+ imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-qds.dtb \
ls1021a-twr.dtb
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
new file mode 100644
index 0000000..cc4e6ef
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+ model = "NXP i.MX7ULP EVK";
+ compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
+
+ chosen {
+ bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
+ stdout-path = &lpuart4;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+};
+
+&lpuart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart4>;
+ status = "okay";
+};
+
+&usdhc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>;
+// <&pinctrl_usdhc0_cd>, <&pinctrl_usdhc0_rst>;
+ status = "okay";
+};
+
+&iomuxc1 {
+ pinctrl_lpuart4: lpuart4grp {
+ pins = <
+ IMX7ULP_PAD_PTC3__LPUART4_RX
+ IMX7ULP_PAD_PTC2__LPUART4_TX
+ >;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc0_cmd_data: usdhc0_cmd_data_0_3_grp {
+ pins = <
+ IMX7ULP_PAD_PTD1__SDHC0_CMD
+ IMX7ULP_PAD_PTD2__SDHC0_CLK
+ IMX7ULP_PAD_PTD7__SDHC0_D3
+ IMX7ULP_PAD_PTD8__SDHC0_D2
+ IMX7ULP_PAD_PTD9__SDHC0_D1
+ IMX7ULP_PAD_PTD10__SDHC0_D0
+ >;
+ drive-strength = <1>;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc0_clk: usdhc0_clk_grp {
+ pins = <
+ IMX7ULP_PAD_PTD2__SDHC0_CLK
+ >;
+ drive-strength = <1>;
+ bias-pull-down;
+ };
+
+ pinctrl_usdhc0_cd: usdhc0_gpios_cd_grp {
+ pins = <
+ IMX7ULP_PAD_PTC10__PTC10 /* USDHC0 CD */
+ >;
+ nxp,input-buffer-enable;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc0_rst: usdhc0_gpios_rst_grp {
+ pins = <
+ IMX7ULP_PAD_PTD0__PTD0 /* USDHC0 RST */
+ >;
+ nxp,output-buffer-enable;
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
new file mode 100644
index 0000000..05410ba
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -0,0 +1,202 @@
+/*
+ * Copyright NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+
+#include "imx7ulp-pinfunc.h"
+
+/ {
+ interrupt-parent = <&intc>;
+
+ aliases {
+ serial0 = &lpuart4;
+ serial1 = &lpuart6;
+ serial2 = &lpuart5;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ intc: interrupt-controller@40021000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x40021000 0x1000>,
+ <0x40022000 0x100>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rosc: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "rosc";
+ #clock-cells = <0>;
+ };
+
+ sosc: clock@1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ clock-frequency = <24000000>;
+ clock-output-names = "sosc";
+ #clock-cells = <0>;
+ };
+
+ sirc: clock@2 {
+ compatible = "fixed-clock";
+ reg = <2>;
+ clock-frequency = <16000000>;
+ clock-output-names = "sirc";
+ #clock-cells = <0>;
+ };
+
+ firc: clock@3 {
+ compatible = "fixed-clock";
+ reg = <3>;
+ clock-frequency = <48000000>;
+ clock-output-names = "firc";
+ #clock-cells = <0>;
+ };
+
+ upll: clock@4 {
+ compatible = "fixed-clock";
+ reg = <4>;
+ clock-frequency = <480000000>;
+ clock-output-names = "upll";
+ #clock-cells = <0>;
+ };
+
+ mpll: clock@5 {
+ compatible = "fixed-clock";
+ reg = <5>;
+ clock-frequency = <480000000>;
+ clock-output-names = "mpll";
+ #clock-cells = <0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ arm,cpu-registers-not-fw-configured;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&intc>;
+ clock-frequency = <1000000>;
+ status = "disabled";
+ };
+
+ sram: sram@20000000 {
+ compatible = "fsl,lpm-sram";
+ reg = <0x20008000 0x4000>;
+ };
+
+ ahbbridge0: ahb-bridge0@40000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40000000 0x800000>;
+ ranges;
+
+ lpuart4: serial@402D0000 {
+ compatible = "fsl,imx7ulp-lpuart";
+ reg = <0x402D0000 0x1000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_LPUART4>;
+ clock-names = "ipg";
+ assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>;
+ assigned-clock-rates = <24000000>;
+ status = "disabled";
+ };
+
+ lpuart5: serial@402E0000 {
+ compatible = "fsl,imx7ulp-lpuart";
+ reg = <0x402E0000 0x1000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clock-rates = <48000000>;
+ status = "disabled";
+ };
+
+ tpm5: tpm@40260000 {
+ compatible = "fsl,imx7ulp-tpm";
+ reg = <0x40260000 0x1000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&clks IMX7ULP_CLK_LPTPM5>;
+ clock-names = "ipg", "per";
+ };
+
+ usdhc0: usdhc@40370000 {
+ compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x40370000 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&clks IMX7ULP_CLK_NIC1_DIV>,
+ <&clks IMX7ULP_CLK_USDHC0>;
+ clock-names ="ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ clks: scg1@403e0000 {
+ compatible = "fsl,imx7ulp-clock";
+ reg = <0x403e0000 0x10000>,
+ <0x403f0000 0x10000>,
+ <0x40b30000 0x10000>;
+ reg-names = "scg1", "pcc2", "pcc3";
+ clocks = <&rosc>, <&sosc>, <&sirc>,
+ <&firc>, <&upll>, <&mpll>;
+ clock-names = "rosc", "sosc", "sirc",
+ "firc", "upll", "mpll";
+ assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
+ <&clks IMX7ULP_CLK_USDHC1>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>,
+ <&clks IMX7ULP_CLK_NIC1_DIV>;
+ #clock-cells = <1>;
+ };
+
+ smc1: smc1@40410000 {
+ compatible = "fsl,imx7ulp-smc1";
+ reg = <0x40410000 0x1000>;
+ };
+ };
+
+ ahbbridge1: ahb-bridge1@40800000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40800000 0x800000>;
+ ranges;
+
+ iomuxc1: iomuxc1@40ac0000 {
+ compatible = "fsl,imx7ulp-iomuxc1";
+ reg = <0x40ac0000 0x1000>;
+ };
+
+ lpuart6: serial@40A60000 {
+ compatible = "fsl,imx7ulp-lpuart";
+ reg = <0x40A60000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 0d44949..3ce8ff6 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -41,6 +41,7 @@ CONFIG_SOC_IMX6SL=y
CONFIG_SOC_IMX6SX=y
CONFIG_SOC_IMX6UL=y
CONFIG_SOC_IMX7D=y
+CONFIG_SOC_IMX7ULP=y
CONFIG_SOC_VF610=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
@@ -48,9 +49,7 @@ CONFIG_PCI_IMX6=y
CONFIG_SMP=y
CONFIG_ARM_PSCI=y
CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_AEABI=y
CONFIG_HIGHMEM=y
-CONFIG_CMA=y
CONFIG_FORCE_MAX_ZONEORDER=14
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
CONFIG_KEXEC=y
@@ -81,7 +80,6 @@ CONFIG_CAN_FLEXCAN=y
CONFIG_BT=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
CONFIG_CFG80211=y
CONFIG_CFG80211_WEXT=y
CONFIG_MAC80211=y
@@ -90,7 +88,6 @@ CONFIG_RFKILL_INPUT=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
-CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_IMX_WEIM=y
CONFIG_CONNECTOR=y
@@ -167,9 +164,9 @@ CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_TOUCHSCREEN_EGALAX=y
+CONFIG_TOUCHSCREEN_MAX11801=y
CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
CONFIG_TOUCHSCREEN_EDT_FT5X06=y
-CONFIG_TOUCHSCREEN_MAX11801=y
CONFIG_TOUCHSCREEN_MC13783=y
CONFIG_TOUCHSCREEN_TSC2004=y
CONFIG_TOUCHSCREEN_TSC2007=y
@@ -178,7 +175,6 @@ CONFIG_TOUCHSCREEN_SX8654=y
CONFIG_TOUCHSCREEN_COLIBRI_VF50=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_MMA8450=y
-CONFIG_HID_MULTITOUCH=y
CONFIG_SERIO_SERPORT=m
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_IMX=y
@@ -228,13 +224,13 @@ CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
CONFIG_REGULATOR_PFUZE100=y
+CONFIG_RC_CORE=y
+CONFIG_RC_DEVICES=y
+CONFIG_IR_GPIO_CIR=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_RC_CORE=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
-CONFIG_RC_DEVICES=y
-CONFIG_IR_GPIO_CIR=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
@@ -245,7 +241,6 @@ CONFIG_VIDEO_CODA=m
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_OV5640=m
-CONFIG_SOC_CAMERA_OV2640=y
CONFIG_IMX_IPUV3_CORE=y
CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
@@ -283,6 +278,7 @@ CONFIG_SND_SOC_CS42XX8_I2C=y
CONFIG_SND_SOC_TLV320AIC3X=y
CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SIMPLE_CARD=y
+CONFIG_HID_MULTITOUCH=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 782699e..54002c3 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -554,6 +554,15 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
+config SOC_IMX7ULP
+ bool "i.MX7ULP support"
+ select ARM_GIC
+ select CLKSRC_IMX_TPM
+ select HAVE_ARM_ARCH_TIMER
+ select PINCTRL_IMX7ULP
+ help
+ This enables support for Freescale i.MX7 Ultra Low Power processor.
+
config SOC_VF610
bool "Vybrid Family VF610 support"
select ARM_GIC if ARCH_MULTI_V7
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 8ff7105..69c2517 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -81,6 +81,7 @@ obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o
obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o
+obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
ifeq ($(CONFIG_SUSPEND),y)
AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index b09a2ec..b0e85df 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -128,6 +128,7 @@ void imx6dl_pm_init(void);
void imx6sl_pm_init(void);
void imx6sx_pm_init(void);
void imx6ul_pm_init(void);
+void imx7ulp_pm_init(void);
#ifdef CONFIG_PM
void imx51_pm_init(void);
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index d4e55f2..46f344f 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -138,6 +138,9 @@ struct device * __init imx_soc_device_init(void)
case MXC_CPU_IMX7D:
soc_id = "i.MX7D";
break;
+ case MXC_CPU_IMX7ULP:
+ soc_id = "i.MX7ULP";
+ break;
default:
soc_id = "Unknown";
}
diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c
new file mode 100644
index 0000000..9f7a25c
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx7ulp.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+#include "hardware.h"
+
+static void __init imx7ulp_init_machine(void)
+{
+ imx7ulp_pm_init();
+
+ mxc_set_cpu_type(MXC_CPU_IMX7ULP);
+ imx_print_silicon_rev("i.MX7ULP", IMX_CHIP_REVISION_1_0);
+ of_platform_default_populate(NULL, NULL, imx_soc_device_init());
+}
+
+static const char *const imx7ulp_dt_compat[] __initconst = {
+ "fsl,imx7ulp",
+ NULL,
+};
+
+DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
+ .init_machine = imx7ulp_init_machine,
+ .dt_compat = imx7ulp_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index e00d626..ac9677b 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -41,6 +41,7 @@
#define MXC_CPU_IMX6UL 0x64
#define MXC_CPU_IMX6ULL 0x65
#define MXC_CPU_IMX7D 0x72
+#define MXC_CPU_IMX7ULP 0xff
#define IMX_DDR_TYPE_LPDDR2 1
diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c
new file mode 100644
index 0000000..00401e0
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx7ulp.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define SMC_PMCTRL 0x10
+#define BP_PMCTRL_PSTOPO 16
+#define PSTOPO_PSTOP3 0x3
+
+void __init imx7ulp_pm_init(void)
+{
+ struct device_node *np;
+ void __iomem *smc1_base;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
+ smc1_base = of_iomap(np, 0);
+ WARN_ON(!smc1_base);
+
+ /* Partial Stop mode 3 with system/bus clock enabled */
+ writel_relaxed(PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO, smc1_base + SMC_PMCTRL);
+}
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH V3 10/10] add imx7ulp support
@ 2018-01-19 13:11 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-19 13:11 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/imx7ulp-evk.dts | 87 +++++++++++++++
arch/arm/boot/dts/imx7ulp.dtsi | 202 +++++++++++++++++++++++++++++++++++
arch/arm/configs/imx_v6_v7_defconfig | 16 ++-
arch/arm/mach-imx/Kconfig | 9 ++
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/cpu.c | 3 +
arch/arm/mach-imx/mach-imx7ulp.c | 37 +++++++
arch/arm/mach-imx/mxc.h | 1 +
arch/arm/mach-imx/pm-imx7ulp.c | 32 ++++++
11 files changed, 381 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0381e9..3257e71 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -519,6 +519,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-sdb-sht11.dtb \
imx7s-colibri-eval-v3.dtb \
imx7s-warp.dtb
+dtb-$(CONFIG_SOC_IMX7ULP) += \
+ imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-qds.dtb \
ls1021a-twr.dtb
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
new file mode 100644
index 0000000..cc4e6ef
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+ model = "NXP i.MX7ULP EVK";
+ compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
+
+ chosen {
+ bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
+ stdout-path = &lpuart4;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+};
+
+&lpuart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart4>;
+ status = "okay";
+};
+
+&usdhc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>;
+// <&pinctrl_usdhc0_cd>, <&pinctrl_usdhc0_rst>;
+ status = "okay";
+};
+
+&iomuxc1 {
+ pinctrl_lpuart4: lpuart4grp {
+ pins = <
+ IMX7ULP_PAD_PTC3__LPUART4_RX
+ IMX7ULP_PAD_PTC2__LPUART4_TX
+ >;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc0_cmd_data: usdhc0_cmd_data_0_3_grp {
+ pins = <
+ IMX7ULP_PAD_PTD1__SDHC0_CMD
+ IMX7ULP_PAD_PTD2__SDHC0_CLK
+ IMX7ULP_PAD_PTD7__SDHC0_D3
+ IMX7ULP_PAD_PTD8__SDHC0_D2
+ IMX7ULP_PAD_PTD9__SDHC0_D1
+ IMX7ULP_PAD_PTD10__SDHC0_D0
+ >;
+ drive-strength = <1>;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc0_clk: usdhc0_clk_grp {
+ pins = <
+ IMX7ULP_PAD_PTD2__SDHC0_CLK
+ >;
+ drive-strength = <1>;
+ bias-pull-down;
+ };
+
+ pinctrl_usdhc0_cd: usdhc0_gpios_cd_grp {
+ pins = <
+ IMX7ULP_PAD_PTC10__PTC10 /* USDHC0 CD */
+ >;
+ nxp,input-buffer-enable;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc0_rst: usdhc0_gpios_rst_grp {
+ pins = <
+ IMX7ULP_PAD_PTD0__PTD0 /* USDHC0 RST */
+ >;
+ nxp,output-buffer-enable;
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
new file mode 100644
index 0000000..05410ba
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -0,0 +1,202 @@
+/*
+ * Copyright NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+
+#include "imx7ulp-pinfunc.h"
+
+/ {
+ interrupt-parent = <&intc>;
+
+ aliases {
+ serial0 = &lpuart4;
+ serial1 = &lpuart6;
+ serial2 = &lpuart5;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ intc: interrupt-controller at 40021000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x40021000 0x1000>,
+ <0x40022000 0x100>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rosc: clock at 0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "rosc";
+ #clock-cells = <0>;
+ };
+
+ sosc: clock at 1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ clock-frequency = <24000000>;
+ clock-output-names = "sosc";
+ #clock-cells = <0>;
+ };
+
+ sirc: clock at 2 {
+ compatible = "fixed-clock";
+ reg = <2>;
+ clock-frequency = <16000000>;
+ clock-output-names = "sirc";
+ #clock-cells = <0>;
+ };
+
+ firc: clock at 3 {
+ compatible = "fixed-clock";
+ reg = <3>;
+ clock-frequency = <48000000>;
+ clock-output-names = "firc";
+ #clock-cells = <0>;
+ };
+
+ upll: clock at 4 {
+ compatible = "fixed-clock";
+ reg = <4>;
+ clock-frequency = <480000000>;
+ clock-output-names = "upll";
+ #clock-cells = <0>;
+ };
+
+ mpll: clock at 5 {
+ compatible = "fixed-clock";
+ reg = <5>;
+ clock-frequency = <480000000>;
+ clock-output-names = "mpll";
+ #clock-cells = <0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ arm,cpu-registers-not-fw-configured;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&intc>;
+ clock-frequency = <1000000>;
+ status = "disabled";
+ };
+
+ sram: sram at 20000000 {
+ compatible = "fsl,lpm-sram";
+ reg = <0x20008000 0x4000>;
+ };
+
+ ahbbridge0: ahb-bridge0 at 40000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40000000 0x800000>;
+ ranges;
+
+ lpuart4: serial at 402D0000 {
+ compatible = "fsl,imx7ulp-lpuart";
+ reg = <0x402D0000 0x1000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_LPUART4>;
+ clock-names = "ipg";
+ assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>;
+ assigned-clock-rates = <24000000>;
+ status = "disabled";
+ };
+
+ lpuart5: serial at 402E0000 {
+ compatible = "fsl,imx7ulp-lpuart";
+ reg = <0x402E0000 0x1000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clock-rates = <48000000>;
+ status = "disabled";
+ };
+
+ tpm5: tpm at 40260000 {
+ compatible = "fsl,imx7ulp-tpm";
+ reg = <0x40260000 0x1000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&clks IMX7ULP_CLK_LPTPM5>;
+ clock-names = "ipg", "per";
+ };
+
+ usdhc0: usdhc at 40370000 {
+ compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x40370000 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&clks IMX7ULP_CLK_NIC1_DIV>,
+ <&clks IMX7ULP_CLK_USDHC0>;
+ clock-names ="ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ clks: scg1 at 403e0000 {
+ compatible = "fsl,imx7ulp-clock";
+ reg = <0x403e0000 0x10000>,
+ <0x403f0000 0x10000>,
+ <0x40b30000 0x10000>;
+ reg-names = "scg1", "pcc2", "pcc3";
+ clocks = <&rosc>, <&sosc>, <&sirc>,
+ <&firc>, <&upll>, <&mpll>;
+ clock-names = "rosc", "sosc", "sirc",
+ "firc", "upll", "mpll";
+ assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
+ <&clks IMX7ULP_CLK_USDHC1>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>,
+ <&clks IMX7ULP_CLK_NIC1_DIV>;
+ #clock-cells = <1>;
+ };
+
+ smc1: smc1 at 40410000 {
+ compatible = "fsl,imx7ulp-smc1";
+ reg = <0x40410000 0x1000>;
+ };
+ };
+
+ ahbbridge1: ahb-bridge1 at 40800000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40800000 0x800000>;
+ ranges;
+
+ iomuxc1: iomuxc1 at 40ac0000 {
+ compatible = "fsl,imx7ulp-iomuxc1";
+ reg = <0x40ac0000 0x1000>;
+ };
+
+ lpuart6: serial at 40A60000 {
+ compatible = "fsl,imx7ulp-lpuart";
+ reg = <0x40A60000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 0d44949..3ce8ff6 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -41,6 +41,7 @@ CONFIG_SOC_IMX6SL=y
CONFIG_SOC_IMX6SX=y
CONFIG_SOC_IMX6UL=y
CONFIG_SOC_IMX7D=y
+CONFIG_SOC_IMX7ULP=y
CONFIG_SOC_VF610=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
@@ -48,9 +49,7 @@ CONFIG_PCI_IMX6=y
CONFIG_SMP=y
CONFIG_ARM_PSCI=y
CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_AEABI=y
CONFIG_HIGHMEM=y
-CONFIG_CMA=y
CONFIG_FORCE_MAX_ZONEORDER=14
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
CONFIG_KEXEC=y
@@ -81,7 +80,6 @@ CONFIG_CAN_FLEXCAN=y
CONFIG_BT=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_LL=y
CONFIG_CFG80211=y
CONFIG_CFG80211_WEXT=y
CONFIG_MAC80211=y
@@ -90,7 +88,6 @@ CONFIG_RFKILL_INPUT=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
-CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_IMX_WEIM=y
CONFIG_CONNECTOR=y
@@ -167,9 +164,9 @@ CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_TOUCHSCREEN_EGALAX=y
+CONFIG_TOUCHSCREEN_MAX11801=y
CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
CONFIG_TOUCHSCREEN_EDT_FT5X06=y
-CONFIG_TOUCHSCREEN_MAX11801=y
CONFIG_TOUCHSCREEN_MC13783=y
CONFIG_TOUCHSCREEN_TSC2004=y
CONFIG_TOUCHSCREEN_TSC2007=y
@@ -178,7 +175,6 @@ CONFIG_TOUCHSCREEN_SX8654=y
CONFIG_TOUCHSCREEN_COLIBRI_VF50=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_MMA8450=y
-CONFIG_HID_MULTITOUCH=y
CONFIG_SERIO_SERPORT=m
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_IMX=y
@@ -228,13 +224,13 @@ CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
CONFIG_REGULATOR_PFUZE100=y
+CONFIG_RC_CORE=y
+CONFIG_RC_DEVICES=y
+CONFIG_IR_GPIO_CIR=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_RC_CORE=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
-CONFIG_RC_DEVICES=y
-CONFIG_IR_GPIO_CIR=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
@@ -245,7 +241,6 @@ CONFIG_VIDEO_CODA=m
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_OV5640=m
-CONFIG_SOC_CAMERA_OV2640=y
CONFIG_IMX_IPUV3_CORE=y
CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
@@ -283,6 +278,7 @@ CONFIG_SND_SOC_CS42XX8_I2C=y
CONFIG_SND_SOC_TLV320AIC3X=y
CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SIMPLE_CARD=y
+CONFIG_HID_MULTITOUCH=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 782699e..54002c3 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -554,6 +554,15 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
+config SOC_IMX7ULP
+ bool "i.MX7ULP support"
+ select ARM_GIC
+ select CLKSRC_IMX_TPM
+ select HAVE_ARM_ARCH_TIMER
+ select PINCTRL_IMX7ULP
+ help
+ This enables support for Freescale i.MX7 Ultra Low Power processor.
+
config SOC_VF610
bool "Vybrid Family VF610 support"
select ARM_GIC if ARCH_MULTI_V7
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 8ff7105..69c2517 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -81,6 +81,7 @@ obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o
obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o
+obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
ifeq ($(CONFIG_SUSPEND),y)
AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index b09a2ec..b0e85df 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -128,6 +128,7 @@ void imx6dl_pm_init(void);
void imx6sl_pm_init(void);
void imx6sx_pm_init(void);
void imx6ul_pm_init(void);
+void imx7ulp_pm_init(void);
#ifdef CONFIG_PM
void imx51_pm_init(void);
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index d4e55f2..46f344f 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -138,6 +138,9 @@ struct device * __init imx_soc_device_init(void)
case MXC_CPU_IMX7D:
soc_id = "i.MX7D";
break;
+ case MXC_CPU_IMX7ULP:
+ soc_id = "i.MX7ULP";
+ break;
default:
soc_id = "Unknown";
}
diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c
new file mode 100644
index 0000000..9f7a25c
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx7ulp.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+#include "hardware.h"
+
+static void __init imx7ulp_init_machine(void)
+{
+ imx7ulp_pm_init();
+
+ mxc_set_cpu_type(MXC_CPU_IMX7ULP);
+ imx_print_silicon_rev("i.MX7ULP", IMX_CHIP_REVISION_1_0);
+ of_platform_default_populate(NULL, NULL, imx_soc_device_init());
+}
+
+static const char *const imx7ulp_dt_compat[] __initconst = {
+ "fsl,imx7ulp",
+ NULL,
+};
+
+DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
+ .init_machine = imx7ulp_init_machine,
+ .dt_compat = imx7ulp_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index e00d626..ac9677b 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -41,6 +41,7 @@
#define MXC_CPU_IMX6UL 0x64
#define MXC_CPU_IMX6ULL 0x65
#define MXC_CPU_IMX7D 0x72
+#define MXC_CPU_IMX7ULP 0xff
#define IMX_DDR_TYPE_LPDDR2 1
diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c
new file mode 100644
index 0000000..00401e0
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx7ulp.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define SMC_PMCTRL 0x10
+#define BP_PMCTRL_PSTOPO 16
+#define PSTOPO_PSTOP3 0x3
+
+void __init imx7ulp_pm_init(void)
+{
+ struct device_node *np;
+ void __iomem *smc1_base;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
+ smc1_base = of_iomap(np, 0);
+ WARN_ON(!smc1_base);
+
+ /* Partial Stop mode 3 with system/bus clock enabled */
+ writel_relaxed(PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO, smc1_base + SMC_PMCTRL);
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 41+ messages in thread
* RE: [PATCH V3 10/10] add imx7ulp support
2018-01-19 13:11 ` Dong Aisheng
(?)
@ 2018-01-19 13:19 ` A.s. Dong
-1 siblings, 0 replies; 41+ messages in thread
From: A.s. Dong @ 2018-01-19 13:19 UTC (permalink / raw)
To: A.s. Dong, linux-clk
Cc: linux-kernel, linux-arm-kernel, sboyd, mturquette, shawnguo,
Anson Huang, Jacky Bai, dl-linux-imx, Fabio Estevam
Hi Stephen,
> -----Original Message-----
> From: Dong Aisheng [mailto:aisheng.dong@nxp.com]
> Sent: Friday, January 19, 2018 9:11 PM
> To: linux-clk@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> sboyd@codeaurora.org; mturquette@baylibre.com; shawnguo@kernel.org;
> Anson Huang <anson.huang@nxp.com>; Jacky Bai <ping.bai@nxp.com>; dl-
> linux-imx <linux-imx@nxp.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> A.s. Dong <aisheng.dong@nxp.com>
> Subject: [PATCH V3 10/10] add imx7ulp support
>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
>
I'm sorry that this one is for test and was sent out by accidently and should not belong
to the clk series. So you can ignore this one. Others, patch 1~9, are fine.
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 41+ messages in thread
* RE: [PATCH V3 10/10] add imx7ulp support
@ 2018-01-19 13:19 ` A.s. Dong
0 siblings, 0 replies; 41+ messages in thread
From: A.s. Dong @ 2018-01-19 13:19 UTC (permalink / raw)
To: A.s. Dong, linux-clk
Cc: linux-kernel, linux-arm-kernel, sboyd, mturquette, shawnguo,
Anson Huang, Jacky Bai, dl-linux-imx, Fabio Estevam
Hi Stephen,
> -----Original Message-----
> From: Dong Aisheng [mailto:aisheng.dong@nxp.com]
> Sent: Friday, January 19, 2018 9:11 PM
> To: linux-clk@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> sboyd@codeaurora.org; mturquette@baylibre.com; shawnguo@kernel.org;
> Anson Huang <anson.huang@nxp.com>; Jacky Bai <ping.bai@nxp.com>; dl-
> linux-imx <linux-imx@nxp.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> A.s. Dong <aisheng.dong@nxp.com>
> Subject: [PATCH V3 10/10] add imx7ulp support
>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
>
I'm sorry that this one is for test and was sent out by accidently and shou=
ld not belong
to the clk series. So you can ignore this one. Others, patch 1~9, are fine.
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH V3 10/10] add imx7ulp support
@ 2018-01-19 13:19 ` A.s. Dong
0 siblings, 0 replies; 41+ messages in thread
From: A.s. Dong @ 2018-01-19 13:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi Stephen,
> -----Original Message-----
> From: Dong Aisheng [mailto:aisheng.dong at nxp.com]
> Sent: Friday, January 19, 2018 9:11 PM
> To: linux-clk at vger.kernel.org
> Cc: linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> sboyd at codeaurora.org; mturquette at baylibre.com; shawnguo at kernel.org;
> Anson Huang <anson.huang@nxp.com>; Jacky Bai <ping.bai@nxp.com>; dl-
> linux-imx <linux-imx@nxp.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> A.s. Dong <aisheng.dong@nxp.com>
> Subject: [PATCH V3 10/10] add imx7ulp support
>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
>
I'm sorry that this one is for test and was sent out by accidently and should not belong
to the clk series. So you can ignore this one. Others, patch 1~9, are fine.
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH V3 01/10] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
2018-01-19 13:11 ` Dong Aisheng
@ 2018-01-23 11:03 ` Jerome Brunet
-1 siblings, 0 replies; 41+ messages in thread
From: Jerome Brunet @ 2018-01-23 11:03 UTC (permalink / raw)
To: Dong Aisheng, linux-clk, sboyd, mturquette
Cc: linux-kernel, linux-arm-kernel, shawnguo, Anson.Huang, ping.bai,
linux-imx, fabio.estevam
On Fri, 2018-01-19 at 21:11 +0800, Dong Aisheng wrote:
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index f711be6..68ccd36 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -360,6 +360,7 @@ struct clk_div_table {
> * @shift: shift to the divider bit field
> * @width: width of the divider bit field
> * @table: array of value/divider pairs, last entry should have div = 0
> + * @cached_val: cached div hw value used for CLK_DIVIDER_ZERO_GATE
> * @lock: register lock
> *
> * Clock with an adjustable divider affecting its output frequency. Implements
> @@ -388,6 +389,12 @@ struct clk_div_table {
> * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
> * except when the value read from the register is zero, the divisor is
> * 2^width of the field.
> + * CLK_DIVIDER_ZERO_GATE - For dividers which are like CLK_DIVIDER_ONE_BASED
Unless I missed something in your patch, this comment says that, like
CLK_DIVIDER_MAX_AT_ZERO, CLK_DIVIDER_ZERO_GATE behave as a CLK_DIVIDER_ONE_BASED
clock
However, I don't see anything special done in _get_val() around
CLK_DIVIDER_ZERO_GATE which means that calling _get_val() with div=2 would give
val=1. This is more like a regular divider (when CLK_DIVIDER_ONE_BASED is not
set)
Also, when looking for the best divider, CCF could find that the best div is 1.
On a non-CLK_DIVIDER_ONE_BASED, this would translate to value 0 and
(accidentally) gate the clock .
all the occurrences of CLK_DIVIDER_ZERO_GATE I have seen in patch 9 are combined
with CLK_DIVIDER_ONE_BASED, which is probably why this potential issue has gone
unnoticed.
I think CLK_DIVIDER_ZERO_GATE should just means that value 0 gate the clock, and
just that. It should not imply what the rest of values mean.
In a more general way, I'd love to see a feature such as CLK_DIVIDER_ZERO_GATE
added to the divider but I'm bit concerned of all the quirks we are slowly
adding to the generic divider. It seems we are all trying re-use the algorithm
of clk_divider_bestdiv() with different 'val-to-div' transfer function. Not too
sure what the best solution could be though.
> + * when the value read from the register is zero, it means the divisor
> + * is gated. For this case, the cached_val will be used to store the
> + * intermediate div for the normal rate operation, like set_rate/get_rate/
> + * recalc_rate. When the divider is ungated, the driver will actually
> + * program the hardware to have the requested divider value.
> */
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH V3 01/10] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
@ 2018-01-23 11:03 ` Jerome Brunet
0 siblings, 0 replies; 41+ messages in thread
From: Jerome Brunet @ 2018-01-23 11:03 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 2018-01-19 at 21:11 +0800, Dong Aisheng wrote:
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index f711be6..68ccd36 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -360,6 +360,7 @@ struct clk_div_table {
> * @shift: shift to the divider bit field
> * @width: width of the divider bit field
> * @table: array of value/divider pairs, last entry should have div = 0
> + * @cached_val: cached div hw value used for CLK_DIVIDER_ZERO_GATE
> * @lock: register lock
> *
> * Clock with an adjustable divider affecting its output frequency. Implements
> @@ -388,6 +389,12 @@ struct clk_div_table {
> * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
> * except when the value read from the register is zero, the divisor is
> * 2^width of the field.
> + * CLK_DIVIDER_ZERO_GATE - For dividers which are like CLK_DIVIDER_ONE_BASED
Unless I missed something in your patch, this comment says that, like
CLK_DIVIDER_MAX_AT_ZERO, CLK_DIVIDER_ZERO_GATE behave as a CLK_DIVIDER_ONE_BASED
clock
However, I don't see anything special done in _get_val() around
CLK_DIVIDER_ZERO_GATE which means that calling _get_val() with div=2 would give
val=1. This is more like a regular divider (when CLK_DIVIDER_ONE_BASED is not
set)
Also, when looking for the best divider, CCF could find that the best div is 1.
On a non-CLK_DIVIDER_ONE_BASED, this would translate to value 0 and
(accidentally) gate the clock .
all the occurrences of CLK_DIVIDER_ZERO_GATE I have seen in patch 9 are combined
with CLK_DIVIDER_ONE_BASED, which is probably why this potential issue has gone
unnoticed.
I think CLK_DIVIDER_ZERO_GATE should just means that value 0 gate the clock, and
just that. It should not imply what the rest of values mean.
In a more general way, I'd love to see a feature such as CLK_DIVIDER_ZERO_GATE
added to the divider but I'm bit concerned of all the quirks we are slowly
adding to the generic divider. It seems we are all trying re-use the algorithm
of clk_divider_bestdiv() with different 'val-to-div' transfer function. Not too
sure what the best solution could be though.
> + * when the value read from the register is zero, it means the divisor
> + * is gated. For this case, the cached_val will be used to store the
> + * intermediate div for the normal rate operation, like set_rate/get_rate/
> + * recalc_rate. When the divider is ungated, the driver will actually
> + * program the hardware to have the requested divider value.
> */
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH V3 01/10] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
2018-01-23 11:03 ` Jerome Brunet
@ 2018-01-23 12:21 ` Dong Aisheng
-1 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-23 12:21 UTC (permalink / raw)
To: Jerome Brunet
Cc: Dong Aisheng, linux-clk, sboyd, mturquette, linux-kernel,
linux-arm-kernel, shawnguo, Anson.Huang, ping.bai, linux-imx,
fabio.estevam
On Tue, Jan 23, 2018 at 12:03:46PM +0100, Jerome Brunet wrote:
> On Fri, 2018-01-19 at 21:11 +0800, Dong Aisheng wrote:
> > diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> > index f711be6..68ccd36 100644
> > --- a/include/linux/clk-provider.h
> > +++ b/include/linux/clk-provider.h
> > @@ -360,6 +360,7 @@ struct clk_div_table {
> > * @shift: shift to the divider bit field
> > * @width: width of the divider bit field
> > * @table: array of value/divider pairs, last entry should have div = 0
> > + * @cached_val: cached div hw value used for CLK_DIVIDER_ZERO_GATE
> > * @lock: register lock
> > *
> > * Clock with an adjustable divider affecting its output frequency. Implements
> > @@ -388,6 +389,12 @@ struct clk_div_table {
> > * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
> > * except when the value read from the register is zero, the divisor is
> > * 2^width of the field.
> > + * CLK_DIVIDER_ZERO_GATE - For dividers which are like CLK_DIVIDER_ONE_BASED
>
> Unless I missed something in your patch, this comment says that, like
> CLK_DIVIDER_MAX_AT_ZERO, CLK_DIVIDER_ZERO_GATE behave as a CLK_DIVIDER_ONE_BASED
> clock
>
> However, I don't see anything special done in _get_val() around
> CLK_DIVIDER_ZERO_GATE which means that calling _get_val() with div=2 would give
> val=1. This is more like a regular divider (when CLK_DIVIDER_ONE_BASED is not
> set)
>
> Also, when looking for the best divider, CCF could find that the best div is 1.
> On a non-CLK_DIVIDER_ONE_BASED, this would translate to value 0 and
> (accidentally) gate the clock .
>
> all the occurrences of CLK_DIVIDER_ZERO_GATE I have seen in patch 9 are combined
> with CLK_DIVIDER_ONE_BASED, which is probably why this potential issue has gone
> unnoticed.
>
Yes, this feature only works with CLK_DIVIDER_ONE_BASED in current design.
Probably we should state more clearly in the code comments?
> I think CLK_DIVIDER_ZERO_GATE should just means that value 0 gate the clock, and
> just that. It should not imply what the rest of values mean.
>
It did not imply what the reset of values mean. User needs to specify the
correct divider types. For current case, it should be CLK_DIVIDER_ONE_BASED
only.
e.g.
000b - Clock disabled
001b - Divide by 1
010b - Divide by 2
If anymore divider type want to use it, then we need extend the support
accordingly.
Theoretically any type of divider gets a 0 val (register value) is invalid for
ZERO_GATE feature. We should avoid it.
> In a more general way, I'd love to see a feature such as CLK_DIVIDER_ZERO_GATE
> added to the divider but I'm bit concerned of all the quirks we are slowly
> adding to the generic divider. It seems we are all trying re-use the algorithm
> of clk_divider_bestdiv() with different 'val-to-div' transfer function. Not too
> sure what the best solution could be though.
>
IMHO CLK_DIVIDER_ZERO_GATE only indicates the 0 val means clk gate.
It does not assume divider types. That looks like a generic way and is exactly
what this patch intends to do. Does it make sense?
Regards
Dong Aisheng
> > + * when the value read from the register is zero, it means the divisor
> > + * is gated. For this case, the cached_val will be used to store the
> > + * intermediate div for the normal rate operation, like set_rate/get_rate/
> > + * recalc_rate. When the divider is ungated, the driver will actually
> > + * program the hardware to have the requested divider value.
> > */
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-clk" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH V3 01/10] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
@ 2018-01-23 12:21 ` Dong Aisheng
0 siblings, 0 replies; 41+ messages in thread
From: Dong Aisheng @ 2018-01-23 12:21 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 23, 2018 at 12:03:46PM +0100, Jerome Brunet wrote:
> On Fri, 2018-01-19 at 21:11 +0800, Dong Aisheng wrote:
> > diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> > index f711be6..68ccd36 100644
> > --- a/include/linux/clk-provider.h
> > +++ b/include/linux/clk-provider.h
> > @@ -360,6 +360,7 @@ struct clk_div_table {
> > * @shift: shift to the divider bit field
> > * @width: width of the divider bit field
> > * @table: array of value/divider pairs, last entry should have div = 0
> > + * @cached_val: cached div hw value used for CLK_DIVIDER_ZERO_GATE
> > * @lock: register lock
> > *
> > * Clock with an adjustable divider affecting its output frequency. Implements
> > @@ -388,6 +389,12 @@ struct clk_div_table {
> > * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
> > * except when the value read from the register is zero, the divisor is
> > * 2^width of the field.
> > + * CLK_DIVIDER_ZERO_GATE - For dividers which are like CLK_DIVIDER_ONE_BASED
>
> Unless I missed something in your patch, this comment says that, like
> CLK_DIVIDER_MAX_AT_ZERO, CLK_DIVIDER_ZERO_GATE behave as a CLK_DIVIDER_ONE_BASED
> clock
>
> However, I don't see anything special done in _get_val() around
> CLK_DIVIDER_ZERO_GATE which means that calling _get_val() with div=2 would give
> val=1. This is more like a regular divider (when CLK_DIVIDER_ONE_BASED is not
> set)
>
> Also, when looking for the best divider, CCF could find that the best div is 1.
> On a non-CLK_DIVIDER_ONE_BASED, this would translate to value 0 and
> (accidentally) gate the clock .
>
> all the occurrences of CLK_DIVIDER_ZERO_GATE I have seen in patch 9 are combined
> with CLK_DIVIDER_ONE_BASED, which is probably why this potential issue has gone
> unnoticed.
>
Yes, this feature only works with CLK_DIVIDER_ONE_BASED in current design.
Probably we should state more clearly in the code comments?
> I think CLK_DIVIDER_ZERO_GATE should just means that value 0 gate the clock, and
> just that. It should not imply what the rest of values mean.
>
It did not imply what the reset of values mean. User needs to specify the
correct divider types. For current case, it should be CLK_DIVIDER_ONE_BASED
only.
e.g.
000b - Clock disabled
001b - Divide by 1
010b - Divide by 2
If anymore divider type want to use it, then we need extend the support
accordingly.
Theoretically any type of divider gets a 0 val (register value) is invalid for
ZERO_GATE feature. We should avoid it.
> In a more general way, I'd love to see a feature such as CLK_DIVIDER_ZERO_GATE
> added to the divider but I'm bit concerned of all the quirks we are slowly
> adding to the generic divider. It seems we are all trying re-use the algorithm
> of clk_divider_bestdiv() with different 'val-to-div' transfer function. Not too
> sure what the best solution could be though.
>
IMHO CLK_DIVIDER_ZERO_GATE only indicates the 0 val means clk gate.
It does not assume divider types. That looks like a generic way and is exactly
what this patch intends to do. Does it make sense?
Regards
Dong Aisheng
> > + * when the value read from the register is zero, it means the divisor
> > + * is gated. For this case, the cached_val will be used to store the
> > + * intermediate div for the normal rate operation, like set_rate/get_rate/
> > + * recalc_rate. When the divider is ungated, the driver will actually
> > + * program the hardware to have the requested divider value.
> > */
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-clk" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH V3 01/10] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
2018-01-23 12:21 ` Dong Aisheng
(?)
@ 2018-01-23 13:10 ` Jerome Brunet
-1 siblings, 0 replies; 41+ messages in thread
From: Jerome Brunet @ 2018-01-23 13:10 UTC (permalink / raw)
To: Dong Aisheng
Cc: Dong Aisheng, linux-clk, sboyd, mturquette, linux-kernel,
linux-arm-kernel, shawnguo, Anson.Huang, ping.bai, linux-imx,
fabio.estevam
On Tue, 2018-01-23 at 20:21 +0800, Dong Aisheng wrote:
> > In a more general way, I'd love to see a feature such as CLK_DIVIDER_ZERO_GATE
> > added to the divider but I'm bit concerned of all the quirks we are slowly
> > adding to the generic divider. It seems we are all trying re-use the algorithm
> > of clk_divider_bestdiv() with different 'val-to-div' transfer function. Not too
> > sure what the best solution could be though.
> >
>
> IMHO CLK_DIVIDER_ZERO_GATE only indicates the 0 val means clk gate.
> It does not assume divider types. That looks like a generic way and is exactly
> what this patch intends to do. Does it make sense?
It makes sense. That last comment was not about your patch specifically but
about the growing entropy in clk-divider.c in general.
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH V3 01/10] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
@ 2018-01-23 13:10 ` Jerome Brunet
0 siblings, 0 replies; 41+ messages in thread
From: Jerome Brunet @ 2018-01-23 13:10 UTC (permalink / raw)
To: Dong Aisheng
Cc: Dong Aisheng, linux-clk, sboyd, mturquette, linux-kernel,
linux-arm-kernel, shawnguo, Anson.Huang, ping.bai, linux-imx,
fabio.estevam
On Tue, 2018-01-23 at 20:21 +0800, Dong Aisheng wrote:
> > In a more general way, I'd love to see a feature such as CLK_DIVIDER_ZERO_GATE
> > added to the divider but I'm bit concerned of all the quirks we are slowly
> > adding to the generic divider. It seems we are all trying re-use the algorithm
> > of clk_divider_bestdiv() with different 'val-to-div' transfer function. Not too
> > sure what the best solution could be though.
> >
>
> IMHO CLK_DIVIDER_ZERO_GATE only indicates the 0 val means clk gate.
> It does not assume divider types. That looks like a generic way and is exactly
> what this patch intends to do. Does it make sense?
It makes sense. That last comment was not about your patch specifically but
about the growing entropy in clk-divider.c in general.
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH V3 01/10] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
@ 2018-01-23 13:10 ` Jerome Brunet
0 siblings, 0 replies; 41+ messages in thread
From: Jerome Brunet @ 2018-01-23 13:10 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, 2018-01-23 at 20:21 +0800, Dong Aisheng wrote:
> > In a more general way, I'd love to see a feature such as CLK_DIVIDER_ZERO_GATE
> > added to the divider but I'm bit concerned of all the quirks we are slowly
> > adding to the generic divider. It seems we are all trying re-use the algorithm
> > of clk_divider_bestdiv() with different 'val-to-div' transfer function. Not too
> > sure what the best solution could be though.
> >
>
> IMHO CLK_DIVIDER_ZERO_GATE only indicates the 0 val means clk gate.
> It does not assume divider types. That looks like a generic way and is exactly
> what this patch intends to do. Does it make sense?
It makes sense. That last comment was not about your patch specifically but
about the growing entropy in clk-divider.c in general.
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH V3 10/10] add imx7ulp support
2018-01-19 13:11 ` Dong Aisheng
@ 2018-01-25 13:22 ` Fabio Estevam
-1 siblings, 0 replies; 41+ messages in thread
From: Fabio Estevam @ 2018-01-25 13:22 UTC (permalink / raw)
To: Dong Aisheng
Cc: linux-clk, Ping Bai, Yongcai Huang, Michael Turquette,
Stephen Boyd, linux-kernel, linux-imx, Fabio Estevam, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Fri, Jan 19, 2018 at 11:11 AM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
Please always add a commit log.
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/imx7ulp-evk.dts | 87 +++++++++++++++
> arch/arm/boot/dts/imx7ulp.dtsi | 202 +++++++++++++++++++++++++++++++++++
> arch/arm/configs/imx_v6_v7_defconfig | 16 ++-
> arch/arm/mach-imx/Kconfig | 9 ++
> arch/arm/mach-imx/Makefile | 1 +
> arch/arm/mach-imx/common.h | 1 +
> arch/arm/mach-imx/cpu.c | 3 +
> arch/arm/mach-imx/mach-imx7ulp.c | 37 +++++++
> arch/arm/mach-imx/mxc.h | 1 +
> arch/arm/mach-imx/pm-imx7ulp.c | 32 ++++++
> 11 files changed, 381 insertions(+), 10 deletions(-)
> create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
> create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
> create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
> create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index d0381e9..3257e71 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -519,6 +519,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
> imx7d-sdb-sht11.dtb \
> imx7s-colibri-eval-v3.dtb \
> imx7s-warp.dtb
> +dtb-$(CONFIG_SOC_IMX7ULP) += \
> + imx7ulp-evk.dtb
> dtb-$(CONFIG_SOC_LS1021A) += \
> ls1021a-qds.dtb \
> ls1021a-twr.dtb
> diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
> new file mode 100644
> index 0000000..cc4e6ef
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx7ulp-evk.dts
> @@ -0,0 +1,87 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
Please use SPDX identifier.
> + */
> +
> +/dts-v1/;
> +
> +#include "imx7ulp.dtsi"
> +
> +/ {
> + model = "NXP i.MX7ULP EVK";
> + compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
Please remove the '"Generic DT based system" entry.
> +
> + chosen {
> + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
> + stdout-path = &lpuart4;
Better remove bootargs.
> + };
> +
> + memory {
memory@60000000 , otherwise building with W=1 will give you warning.
Please make sure that you don't get dtc warnings with W=1.
> + device_type = "memory";
> + reg = <0x60000000 0x40000000>;
> + };
> +};
> +
> +&lpuart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lpuart4>;
> + status = "okay";
> +};
> +
> +&usdhc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <>;
> + pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>;
> +// <&pinctrl_usdhc0_cd>, <&pinctrl_usdhc0_rst>;
Just remove the line instead of commenting it.
> diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
> new file mode 100644
> index 0000000..05410ba
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> @@ -0,0 +1,202 @@
> +/*
> + * Copyright NXP
No year information?
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
Please use SPDX identifier instead.
> diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> index 0d44949..3ce8ff6 100644
> --- a/arch/arm/configs/imx_v6_v7_defconfig
> +++ b/arch/arm/configs/imx_v6_v7_defconfig
> @@ -41,6 +41,7 @@ CONFIG_SOC_IMX6SL=y
> CONFIG_SOC_IMX6SX=y
> CONFIG_SOC_IMX6UL=y
> CONFIG_SOC_IMX7D=y
> +CONFIG_SOC_IMX7ULP=y
This should be part of a separate patch.
> CONFIG_SOC_VF610=y
> CONFIG_PCI=y
> CONFIG_PCI_MSI=y
> @@ -48,9 +49,7 @@ CONFIG_PCI_IMX6=y
> CONFIG_SMP=y
> CONFIG_ARM_PSCI=y
> CONFIG_PREEMPT_VOLUNTARY=y
> -CONFIG_AEABI=y
> CONFIG_HIGHMEM=y
> -CONFIG_CMA=y
> CONFIG_FORCE_MAX_ZONEORDER=14
> CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
> CONFIG_KEXEC=y
> @@ -81,7 +80,6 @@ CONFIG_CAN_FLEXCAN=y
> CONFIG_BT=y
> CONFIG_BT_HCIUART=y
> CONFIG_BT_HCIUART_H4=y
> -CONFIG_BT_HCIUART_LL=y
> CONFIG_CFG80211=y
> CONFIG_CFG80211_WEXT=y
> CONFIG_MAC80211=y
> @@ -90,7 +88,6 @@ CONFIG_RFKILL_INPUT=y
> CONFIG_DEVTMPFS=y
> CONFIG_DEVTMPFS_MOUNT=y
> # CONFIG_STANDALONE is not set
> -CONFIG_DMA_CMA=y
> CONFIG_CMA_SIZE_MBYTES=64
> CONFIG_IMX_WEIM=y
> CONFIG_CONNECTOR=y
> @@ -167,9 +164,9 @@ CONFIG_MOUSE_PS2_ELANTECH=y
> CONFIG_INPUT_TOUCHSCREEN=y
> CONFIG_TOUCHSCREEN_ADS7846=y
> CONFIG_TOUCHSCREEN_EGALAX=y
> +CONFIG_TOUCHSCREEN_MAX11801=y
> CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
> CONFIG_TOUCHSCREEN_EDT_FT5X06=y
> -CONFIG_TOUCHSCREEN_MAX11801=y
> CONFIG_TOUCHSCREEN_MC13783=y
> CONFIG_TOUCHSCREEN_TSC2004=y
> CONFIG_TOUCHSCREEN_TSC2007=y
> @@ -178,7 +175,6 @@ CONFIG_TOUCHSCREEN_SX8654=y
> CONFIG_TOUCHSCREEN_COLIBRI_VF50=y
> CONFIG_INPUT_MISC=y
> CONFIG_INPUT_MMA8450=y
> -CONFIG_HID_MULTITOUCH=y
> CONFIG_SERIO_SERPORT=m
> # CONFIG_LEGACY_PTYS is not set
> CONFIG_SERIAL_IMX=y
> @@ -228,13 +224,13 @@ CONFIG_REGULATOR_GPIO=y
> CONFIG_REGULATOR_MC13783=y
> CONFIG_REGULATOR_MC13892=y
> CONFIG_REGULATOR_PFUZE100=y
> +CONFIG_RC_CORE=y
> +CONFIG_RC_DEVICES=y
> +CONFIG_IR_GPIO_CIR=y
> CONFIG_MEDIA_SUPPORT=y
> CONFIG_MEDIA_CAMERA_SUPPORT=y
> -CONFIG_RC_CORE=y
> CONFIG_MEDIA_CONTROLLER=y
> CONFIG_VIDEO_V4L2_SUBDEV_API=y
> -CONFIG_RC_DEVICES=y
> -CONFIG_IR_GPIO_CIR=y
> CONFIG_MEDIA_USB_SUPPORT=y
> CONFIG_USB_VIDEO_CLASS=m
> CONFIG_V4L_PLATFORM_DRIVERS=y
> @@ -245,7 +241,6 @@ CONFIG_VIDEO_CODA=m
> # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
> CONFIG_VIDEO_ADV7180=m
> CONFIG_VIDEO_OV5640=m
> -CONFIG_SOC_CAMERA_OV2640=y
> CONFIG_IMX_IPUV3_CORE=y
> CONFIG_DRM=y
> CONFIG_DRM_PANEL_SIMPLE=y
> @@ -283,6 +278,7 @@ CONFIG_SND_SOC_CS42XX8_I2C=y
> CONFIG_SND_SOC_TLV320AIC3X=y
> CONFIG_SND_SOC_WM8960=y
> CONFIG_SND_SIMPLE_CARD=y
> +CONFIG_HID_MULTITOUCH=y
Don't do the defconfig cleanup in the same patch.
> CONFIG_USB=y
> CONFIG_USB_EHCI_HCD=y
> CONFIG_USB_EHCI_MXC=y
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 782699e..54002c3 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -554,6 +554,15 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
>
> if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
>
> +config SOC_IMX7ULP
> + bool "i.MX7ULP support"
> + select ARM_GIC
> + select CLKSRC_IMX_TPM
> + select HAVE_ARM_ARCH_TIMER
> + select PINCTRL_IMX7ULP
> + help
> + This enables support for Freescale i.MX7 Ultra Low Power processor.
> +
> config SOC_VF610
> bool "Vybrid Family VF610 support"
> select ARM_GIC if ARCH_MULTI_V7
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index 8ff7105..69c2517 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
arch/arm/mach-imx changes can also go in a different patch.
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH V3 10/10] add imx7ulp support
@ 2018-01-25 13:22 ` Fabio Estevam
0 siblings, 0 replies; 41+ messages in thread
From: Fabio Estevam @ 2018-01-25 13:22 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 19, 2018 at 11:11 AM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
Please always add a commit log.
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/imx7ulp-evk.dts | 87 +++++++++++++++
> arch/arm/boot/dts/imx7ulp.dtsi | 202 +++++++++++++++++++++++++++++++++++
> arch/arm/configs/imx_v6_v7_defconfig | 16 ++-
> arch/arm/mach-imx/Kconfig | 9 ++
> arch/arm/mach-imx/Makefile | 1 +
> arch/arm/mach-imx/common.h | 1 +
> arch/arm/mach-imx/cpu.c | 3 +
> arch/arm/mach-imx/mach-imx7ulp.c | 37 +++++++
> arch/arm/mach-imx/mxc.h | 1 +
> arch/arm/mach-imx/pm-imx7ulp.c | 32 ++++++
> 11 files changed, 381 insertions(+), 10 deletions(-)
> create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
> create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
> create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
> create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index d0381e9..3257e71 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -519,6 +519,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
> imx7d-sdb-sht11.dtb \
> imx7s-colibri-eval-v3.dtb \
> imx7s-warp.dtb
> +dtb-$(CONFIG_SOC_IMX7ULP) += \
> + imx7ulp-evk.dtb
> dtb-$(CONFIG_SOC_LS1021A) += \
> ls1021a-qds.dtb \
> ls1021a-twr.dtb
> diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
> new file mode 100644
> index 0000000..cc4e6ef
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx7ulp-evk.dts
> @@ -0,0 +1,87 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
Please use SPDX identifier.
> + */
> +
> +/dts-v1/;
> +
> +#include "imx7ulp.dtsi"
> +
> +/ {
> + model = "NXP i.MX7ULP EVK";
> + compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
Please remove the '"Generic DT based system" entry.
> +
> + chosen {
> + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
> + stdout-path = &lpuart4;
Better remove bootargs.
> + };
> +
> + memory {
memory at 60000000 , otherwise building with W=1 will give you warning.
Please make sure that you don't get dtc warnings with W=1.
> + device_type = "memory";
> + reg = <0x60000000 0x40000000>;
> + };
> +};
> +
> +&lpuart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lpuart4>;
> + status = "okay";
> +};
> +
> +&usdhc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <>;
> + pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>;
> +// <&pinctrl_usdhc0_cd>, <&pinctrl_usdhc0_rst>;
Just remove the line instead of commenting it.
> diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
> new file mode 100644
> index 0000000..05410ba
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> @@ -0,0 +1,202 @@
> +/*
> + * Copyright NXP
No year information?
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
Please use SPDX identifier instead.
> diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> index 0d44949..3ce8ff6 100644
> --- a/arch/arm/configs/imx_v6_v7_defconfig
> +++ b/arch/arm/configs/imx_v6_v7_defconfig
> @@ -41,6 +41,7 @@ CONFIG_SOC_IMX6SL=y
> CONFIG_SOC_IMX6SX=y
> CONFIG_SOC_IMX6UL=y
> CONFIG_SOC_IMX7D=y
> +CONFIG_SOC_IMX7ULP=y
This should be part of a separate patch.
> CONFIG_SOC_VF610=y
> CONFIG_PCI=y
> CONFIG_PCI_MSI=y
> @@ -48,9 +49,7 @@ CONFIG_PCI_IMX6=y
> CONFIG_SMP=y
> CONFIG_ARM_PSCI=y
> CONFIG_PREEMPT_VOLUNTARY=y
> -CONFIG_AEABI=y
> CONFIG_HIGHMEM=y
> -CONFIG_CMA=y
> CONFIG_FORCE_MAX_ZONEORDER=14
> CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
> CONFIG_KEXEC=y
> @@ -81,7 +80,6 @@ CONFIG_CAN_FLEXCAN=y
> CONFIG_BT=y
> CONFIG_BT_HCIUART=y
> CONFIG_BT_HCIUART_H4=y
> -CONFIG_BT_HCIUART_LL=y
> CONFIG_CFG80211=y
> CONFIG_CFG80211_WEXT=y
> CONFIG_MAC80211=y
> @@ -90,7 +88,6 @@ CONFIG_RFKILL_INPUT=y
> CONFIG_DEVTMPFS=y
> CONFIG_DEVTMPFS_MOUNT=y
> # CONFIG_STANDALONE is not set
> -CONFIG_DMA_CMA=y
> CONFIG_CMA_SIZE_MBYTES=64
> CONFIG_IMX_WEIM=y
> CONFIG_CONNECTOR=y
> @@ -167,9 +164,9 @@ CONFIG_MOUSE_PS2_ELANTECH=y
> CONFIG_INPUT_TOUCHSCREEN=y
> CONFIG_TOUCHSCREEN_ADS7846=y
> CONFIG_TOUCHSCREEN_EGALAX=y
> +CONFIG_TOUCHSCREEN_MAX11801=y
> CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
> CONFIG_TOUCHSCREEN_EDT_FT5X06=y
> -CONFIG_TOUCHSCREEN_MAX11801=y
> CONFIG_TOUCHSCREEN_MC13783=y
> CONFIG_TOUCHSCREEN_TSC2004=y
> CONFIG_TOUCHSCREEN_TSC2007=y
> @@ -178,7 +175,6 @@ CONFIG_TOUCHSCREEN_SX8654=y
> CONFIG_TOUCHSCREEN_COLIBRI_VF50=y
> CONFIG_INPUT_MISC=y
> CONFIG_INPUT_MMA8450=y
> -CONFIG_HID_MULTITOUCH=y
> CONFIG_SERIO_SERPORT=m
> # CONFIG_LEGACY_PTYS is not set
> CONFIG_SERIAL_IMX=y
> @@ -228,13 +224,13 @@ CONFIG_REGULATOR_GPIO=y
> CONFIG_REGULATOR_MC13783=y
> CONFIG_REGULATOR_MC13892=y
> CONFIG_REGULATOR_PFUZE100=y
> +CONFIG_RC_CORE=y
> +CONFIG_RC_DEVICES=y
> +CONFIG_IR_GPIO_CIR=y
> CONFIG_MEDIA_SUPPORT=y
> CONFIG_MEDIA_CAMERA_SUPPORT=y
> -CONFIG_RC_CORE=y
> CONFIG_MEDIA_CONTROLLER=y
> CONFIG_VIDEO_V4L2_SUBDEV_API=y
> -CONFIG_RC_DEVICES=y
> -CONFIG_IR_GPIO_CIR=y
> CONFIG_MEDIA_USB_SUPPORT=y
> CONFIG_USB_VIDEO_CLASS=m
> CONFIG_V4L_PLATFORM_DRIVERS=y
> @@ -245,7 +241,6 @@ CONFIG_VIDEO_CODA=m
> # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
> CONFIG_VIDEO_ADV7180=m
> CONFIG_VIDEO_OV5640=m
> -CONFIG_SOC_CAMERA_OV2640=y
> CONFIG_IMX_IPUV3_CORE=y
> CONFIG_DRM=y
> CONFIG_DRM_PANEL_SIMPLE=y
> @@ -283,6 +278,7 @@ CONFIG_SND_SOC_CS42XX8_I2C=y
> CONFIG_SND_SOC_TLV320AIC3X=y
> CONFIG_SND_SOC_WM8960=y
> CONFIG_SND_SIMPLE_CARD=y
> +CONFIG_HID_MULTITOUCH=y
Don't do the defconfig cleanup in the same patch.
> CONFIG_USB=y
> CONFIG_USB_EHCI_HCD=y
> CONFIG_USB_EHCI_MXC=y
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 782699e..54002c3 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -554,6 +554,15 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
>
> if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
>
> +config SOC_IMX7ULP
> + bool "i.MX7ULP support"
> + select ARM_GIC
> + select CLKSRC_IMX_TPM
> + select HAVE_ARM_ARCH_TIMER
> + select PINCTRL_IMX7ULP
> + help
> + This enables support for Freescale i.MX7 Ultra Low Power processor.
> +
> config SOC_VF610
> bool "Vybrid Family VF610 support"
> select ARM_GIC if ARCH_MULTI_V7
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index 8ff7105..69c2517 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
arch/arm/mach-imx changes can also go in a different patch.
^ permalink raw reply [flat|nested] 41+ messages in thread
* RE: [PATCH V3 10/10] add imx7ulp support
2018-01-25 13:22 ` Fabio Estevam
(?)
@ 2018-01-25 13:46 ` A.s. Dong
-1 siblings, 0 replies; 41+ messages in thread
From: A.s. Dong @ 2018-01-25 13:46 UTC (permalink / raw)
To: Fabio Estevam
Cc: linux-clk, Jacky Bai, Anson Huang, Michael Turquette,
Stephen Boyd, linux-kernel, dl-linux-imx, Fabio Estevam,
Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Fabio,
This patch (Patch 10) is used for test and was sent out by accidently, not formal one.
I also explained in another email. Guess you may not see it.
Really sorry for the inconvenience.
Regards
Dong Aisheng
> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: Thursday, January 25, 2018 9:22 PM
> To: A.s. Dong <aisheng.dong@nxp.com>
> Cc: linux-clk <linux-clk@vger.kernel.org>; Jacky Bai <ping.bai@nxp.com>;
> Anson Huang <anson.huang@nxp.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@codeaurora.org>; linux-
> kernel <linux-kernel@vger.kernel.org>; dl-linux-imx <linux-imx@nxp.com>;
> Fabio Estevam <fabio.estevam@nxp.com>; Shawn Guo
> <shawnguo@kernel.org>; moderated list:ARM/FREESCALE IMX / MXC ARM
> ARCHITECTURE <linux-arm-kernel@lists.infradead.org>
> Subject: Re: [PATCH V3 10/10] add imx7ulp support
>
> On Fri, Jan 19, 2018 at 11:11 AM, Dong Aisheng <aisheng.dong@nxp.com>
> wrote:
>
> Please always add a commit log.
>
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
>
> > ---
> > arch/arm/boot/dts/Makefile | 2 +
> > arch/arm/boot/dts/imx7ulp-evk.dts | 87 +++++++++++++++
> > arch/arm/boot/dts/imx7ulp.dtsi | 202
> +++++++++++++++++++++++++++++++++++
> > arch/arm/configs/imx_v6_v7_defconfig | 16 ++-
> > arch/arm/mach-imx/Kconfig | 9 ++
> > arch/arm/mach-imx/Makefile | 1 +
> > arch/arm/mach-imx/common.h | 1 +
> > arch/arm/mach-imx/cpu.c | 3 +
> > arch/arm/mach-imx/mach-imx7ulp.c | 37 +++++++
> > arch/arm/mach-imx/mxc.h | 1 +
> > arch/arm/mach-imx/pm-imx7ulp.c | 32 ++++++
> > 11 files changed, 381 insertions(+), 10 deletions(-) create mode
> > 100644 arch/arm/boot/dts/imx7ulp-evk.dts create mode 100644
> > arch/arm/boot/dts/imx7ulp.dtsi create mode 100644
> > arch/arm/mach-imx/mach-imx7ulp.c create mode 100644
> > arch/arm/mach-imx/pm-imx7ulp.c
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index d0381e9..3257e71 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -519,6 +519,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
> > imx7d-sdb-sht11.dtb \
> > imx7s-colibri-eval-v3.dtb \
> > imx7s-warp.dtb
> > +dtb-$(CONFIG_SOC_IMX7ULP) += \
> > + imx7ulp-evk.dtb
> > dtb-$(CONFIG_SOC_LS1021A) += \
> > ls1021a-qds.dtb \
> > ls1021a-twr.dtb
> > diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts
> > b/arch/arm/boot/dts/imx7ulp-evk.dts
> > new file mode 100644
> > index 0000000..cc4e6ef
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx7ulp-evk.dts
> > @@ -0,0 +1,87 @@
> > +/*
> > + * Copyright 2017 NXP
> > + *
> > + * This program is free software; you can redistribute it and/or
> > +modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
>
> Please use SPDX identifier.
>
>
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx7ulp.dtsi"
> > +
> > +/ {
> > + model = "NXP i.MX7ULP EVK";
> > + compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT
> > +based system";
>
> Please remove the '"Generic DT based system" entry.
>
>
> > +
> > + chosen {
> > + bootargs = "console=ttyLP0,115200
> earlycon=lpuart32,0x402D0010,115200";
> > + stdout-path = &lpuart4;
>
> Better remove bootargs.
>
>
> > + };
> > +
> > + memory {
>
> memory@60000000 , otherwise building with W=1 will give you warning.
>
> Please make sure that you don't get dtc warnings with W=1.
>
> > + device_type = "memory";
> > + reg = <0x60000000 0x40000000>;
> > + };
> > +};
> > +
> > +&lpuart4 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_lpuart4>;
> > + status = "okay";
> > +};
> > +
> > +&usdhc0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <>;
> > + pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>;
> > +// <&pinctrl_usdhc0_cd>, <&pinctrl_usdhc0_rst>;
>
> Just remove the line instead of commenting it.
>
> > diff --git a/arch/arm/boot/dts/imx7ulp.dtsi
> > b/arch/arm/boot/dts/imx7ulp.dtsi new file mode 100644 index
> > 0000000..05410ba
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> > @@ -0,0 +1,202 @@
> > +/*
> > + * Copyright NXP
>
> No year information?
>
>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
>
>
> Please use SPDX identifier instead.
>
> > diff --git a/arch/arm/configs/imx_v6_v7_defconfig
> > b/arch/arm/configs/imx_v6_v7_defconfig
> > index 0d44949..3ce8ff6 100644
> > --- a/arch/arm/configs/imx_v6_v7_defconfig
> > +++ b/arch/arm/configs/imx_v6_v7_defconfig
> > @@ -41,6 +41,7 @@ CONFIG_SOC_IMX6SL=y
> > CONFIG_SOC_IMX6SX=y
> > CONFIG_SOC_IMX6UL=y
> > CONFIG_SOC_IMX7D=y
> > +CONFIG_SOC_IMX7ULP=y
>
> This should be part of a separate patch.
>
>
> > CONFIG_SOC_VF610=y
> > CONFIG_PCI=y
> > CONFIG_PCI_MSI=y
> > @@ -48,9 +49,7 @@ CONFIG_PCI_IMX6=y
> > CONFIG_SMP=y
> > CONFIG_ARM_PSCI=y
> > CONFIG_PREEMPT_VOLUNTARY=y
> > -CONFIG_AEABI=y
> > CONFIG_HIGHMEM=y
> > -CONFIG_CMA=y
> > CONFIG_FORCE_MAX_ZONEORDER=14
> > CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
> > CONFIG_KEXEC=y
> > @@ -81,7 +80,6 @@ CONFIG_CAN_FLEXCAN=y CONFIG_BT=y
> > CONFIG_BT_HCIUART=y CONFIG_BT_HCIUART_H4=y -
> CONFIG_BT_HCIUART_LL=y
> > CONFIG_CFG80211=y CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=y
> @@ -90,7
> > +88,6 @@ CONFIG_RFKILL_INPUT=y CONFIG_DEVTMPFS=y
> > CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set
> > -CONFIG_DMA_CMA=y
> > CONFIG_CMA_SIZE_MBYTES=64
> > CONFIG_IMX_WEIM=y
> > CONFIG_CONNECTOR=y
> > @@ -167,9 +164,9 @@ CONFIG_MOUSE_PS2_ELANTECH=y
> > CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=y
> > CONFIG_TOUCHSCREEN_EGALAX=y
> > +CONFIG_TOUCHSCREEN_MAX11801=y
> > CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
> > CONFIG_TOUCHSCREEN_EDT_FT5X06=y
> > -CONFIG_TOUCHSCREEN_MAX11801=y
> > CONFIG_TOUCHSCREEN_MC13783=y
> > CONFIG_TOUCHSCREEN_TSC2004=y
> > CONFIG_TOUCHSCREEN_TSC2007=y
> > @@ -178,7 +175,6 @@ CONFIG_TOUCHSCREEN_SX8654=y
> > CONFIG_TOUCHSCREEN_COLIBRI_VF50=y CONFIG_INPUT_MISC=y
> > CONFIG_INPUT_MMA8450=y -CONFIG_HID_MULTITOUCH=y
> > CONFIG_SERIO_SERPORT=m # CONFIG_LEGACY_PTYS is not set
> > CONFIG_SERIAL_IMX=y @@ -228,13 +224,13 @@
> CONFIG_REGULATOR_GPIO=y
> > CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y
> > CONFIG_REGULATOR_PFUZE100=y
> > +CONFIG_RC_CORE=y
> > +CONFIG_RC_DEVICES=y
> > +CONFIG_IR_GPIO_CIR=y
> > CONFIG_MEDIA_SUPPORT=y
> > CONFIG_MEDIA_CAMERA_SUPPORT=y
> > -CONFIG_RC_CORE=y
> > CONFIG_MEDIA_CONTROLLER=y
> > CONFIG_VIDEO_V4L2_SUBDEV_API=y
> > -CONFIG_RC_DEVICES=y
> > -CONFIG_IR_GPIO_CIR=y
> > CONFIG_MEDIA_USB_SUPPORT=y
> > CONFIG_USB_VIDEO_CLASS=m
> > CONFIG_V4L_PLATFORM_DRIVERS=y
> > @@ -245,7 +241,6 @@ CONFIG_VIDEO_CODA=m #
> > CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
> CONFIG_VIDEO_ADV7180=m
> > CONFIG_VIDEO_OV5640=m -CONFIG_SOC_CAMERA_OV2640=y
> > CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y
> CONFIG_DRM_PANEL_SIMPLE=y @@
> > -283,6 +278,7 @@ CONFIG_SND_SOC_CS42XX8_I2C=y
> > CONFIG_SND_SOC_TLV320AIC3X=y CONFIG_SND_SOC_WM8960=y
> > CONFIG_SND_SIMPLE_CARD=y
> > +CONFIG_HID_MULTITOUCH=y
>
> Don't do the defconfig cleanup in the same patch.
>
> > CONFIG_USB=y
> > CONFIG_USB_EHCI_HCD=y
> > CONFIG_USB_EHCI_MXC=y
> > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> > index 782699e..54002c3 100644
> > --- a/arch/arm/mach-imx/Kconfig
> > +++ b/arch/arm/mach-imx/Kconfig
> > @@ -554,6 +554,15 @@ comment "Cortex-A/Cortex-M asymmetric
> multiprocessing platforms"
> >
> > if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
> >
> > +config SOC_IMX7ULP
> > + bool "i.MX7ULP support"
> > + select ARM_GIC
> > + select CLKSRC_IMX_TPM
> > + select HAVE_ARM_ARCH_TIMER
> > + select PINCTRL_IMX7ULP
> > + help
> > + This enables support for Freescale i.MX7 Ultra Low Power processor.
> > +
> > config SOC_VF610
> > bool "Vybrid Family VF610 support"
> > select ARM_GIC if ARCH_MULTI_V7 diff --git
> > a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index
> > 8ff7105..69c2517 100644
> > --- a/arch/arm/mach-imx/Makefile
> > +++ b/arch/arm/mach-imx/Makefile
>
> arch/arm/mach-imx changes can also go in a different patch.
^ permalink raw reply [flat|nested] 41+ messages in thread
* RE: [PATCH V3 10/10] add imx7ulp support
@ 2018-01-25 13:46 ` A.s. Dong
0 siblings, 0 replies; 41+ messages in thread
From: A.s. Dong @ 2018-01-25 13:46 UTC (permalink / raw)
To: Fabio Estevam
Cc: linux-clk, Jacky Bai, Anson Huang, Michael Turquette,
Stephen Boyd, linux-kernel, dl-linux-imx, Fabio Estevam,
Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
SGkgRmFiaW8sDQoNClRoaXMgcGF0Y2ggKFBhdGNoIDEwKSBpcyB1c2VkIGZvciB0ZXN0IGFuZCB3
YXMgc2VudCBvdXQgYnkgYWNjaWRlbnRseSwgbm90IGZvcm1hbCBvbmUuDQpJIGFsc28gZXhwbGFp
bmVkIGluIGFub3RoZXIgZW1haWwuIEd1ZXNzIHlvdSBtYXkgbm90IHNlZSBpdC4NCg0KUmVhbGx5
IHNvcnJ5IGZvciB0aGUgaW5jb252ZW5pZW5jZS4NCg0KUmVnYXJkcw0KRG9uZyBBaXNoZW5nDQoN
Cj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogRmFiaW8gRXN0ZXZhbSBbbWFp
bHRvOmZlc3RldmFtQGdtYWlsLmNvbV0NCj4gU2VudDogVGh1cnNkYXksIEphbnVhcnkgMjUsIDIw
MTggOToyMiBQTQ0KPiBUbzogQS5zLiBEb25nIDxhaXNoZW5nLmRvbmdAbnhwLmNvbT4NCj4gQ2M6
IGxpbnV4LWNsayA8bGludXgtY2xrQHZnZXIua2VybmVsLm9yZz47IEphY2t5IEJhaSA8cGluZy5i
YWlAbnhwLmNvbT47DQo+IEFuc29uIEh1YW5nIDxhbnNvbi5odWFuZ0BueHAuY29tPjsgTWljaGFl
bCBUdXJxdWV0dGUNCj4gPG10dXJxdWV0dGVAYmF5bGlicmUuY29tPjsgU3RlcGhlbiBCb3lkIDxz
Ym95ZEBjb2RlYXVyb3JhLm9yZz47IGxpbnV4LQ0KPiBrZXJuZWwgPGxpbnV4LWtlcm5lbEB2Z2Vy
Lmtlcm5lbC5vcmc+OyBkbC1saW51eC1pbXggPGxpbnV4LWlteEBueHAuY29tPjsNCj4gRmFiaW8g
RXN0ZXZhbSA8ZmFiaW8uZXN0ZXZhbUBueHAuY29tPjsgU2hhd24gR3VvDQo+IDxzaGF3bmd1b0Br
ZXJuZWwub3JnPjsgbW9kZXJhdGVkIGxpc3Q6QVJNL0ZSRUVTQ0FMRSBJTVggLyBNWEMgQVJNDQo+
IEFSQ0hJVEVDVFVSRSA8bGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnPg0KPiBT
dWJqZWN0OiBSZTogW1BBVENIIFYzIDEwLzEwXSBhZGQgaW14N3VscCBzdXBwb3J0DQo+IA0KPiBP
biBGcmksIEphbiAxOSwgMjAxOCBhdCAxMToxMSBBTSwgRG9uZyBBaXNoZW5nIDxhaXNoZW5nLmRv
bmdAbnhwLmNvbT4NCj4gd3JvdGU6DQo+IA0KPiBQbGVhc2UgYWx3YXlzIGFkZCBhIGNvbW1pdCBs
b2cuDQo+IA0KPiA+IFNpZ25lZC1vZmYtYnk6IERvbmcgQWlzaGVuZyA8YWlzaGVuZy5kb25nQG54
cC5jb20+DQo+IA0KPiA+IC0tLQ0KPiA+ICBhcmNoL2FybS9ib290L2R0cy9NYWtlZmlsZSAgICAg
ICAgICAgfCAgIDIgKw0KPiA+ICBhcmNoL2FybS9ib290L2R0cy9pbXg3dWxwLWV2ay5kdHMgICAg
fCAgODcgKysrKysrKysrKysrKysrDQo+ID4gIGFyY2gvYXJtL2Jvb3QvZHRzL2lteDd1bHAuZHRz
aSAgICAgICB8IDIwMg0KPiArKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKw0KPiA+
ICBhcmNoL2FybS9jb25maWdzL2lteF92Nl92N19kZWZjb25maWcgfCAgMTYgKystDQo+ID4gIGFy
Y2gvYXJtL21hY2gtaW14L0tjb25maWcgICAgICAgICAgICB8ICAgOSArKw0KPiA+ICBhcmNoL2Fy
bS9tYWNoLWlteC9NYWtlZmlsZSAgICAgICAgICAgfCAgIDEgKw0KPiA+ICBhcmNoL2FybS9tYWNo
LWlteC9jb21tb24uaCAgICAgICAgICAgfCAgIDEgKw0KPiA+ICBhcmNoL2FybS9tYWNoLWlteC9j
cHUuYyAgICAgICAgICAgICAgfCAgIDMgKw0KPiA+ICBhcmNoL2FybS9tYWNoLWlteC9tYWNoLWlt
eDd1bHAuYyAgICAgfCAgMzcgKysrKysrKw0KPiA+ICBhcmNoL2FybS9tYWNoLWlteC9teGMuaCAg
ICAgICAgICAgICAgfCAgIDEgKw0KPiA+ICBhcmNoL2FybS9tYWNoLWlteC9wbS1pbXg3dWxwLmMg
ICAgICAgfCAgMzIgKysrKysrDQo+ID4gIDExIGZpbGVzIGNoYW5nZWQsIDM4MSBpbnNlcnRpb25z
KCspLCAxMCBkZWxldGlvbnMoLSkgIGNyZWF0ZSBtb2RlDQo+ID4gMTAwNjQ0IGFyY2gvYXJtL2Jv
b3QvZHRzL2lteDd1bHAtZXZrLmR0cyAgY3JlYXRlIG1vZGUgMTAwNjQ0DQo+ID4gYXJjaC9hcm0v
Ym9vdC9kdHMvaW14N3VscC5kdHNpICBjcmVhdGUgbW9kZSAxMDA2NDQNCj4gPiBhcmNoL2FybS9t
YWNoLWlteC9tYWNoLWlteDd1bHAuYyAgY3JlYXRlIG1vZGUgMTAwNjQ0DQo+ID4gYXJjaC9hcm0v
bWFjaC1pbXgvcG0taW14N3VscC5jDQo+ID4NCj4gPiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm0vYm9v
dC9kdHMvTWFrZWZpbGUgYi9hcmNoL2FybS9ib290L2R0cy9NYWtlZmlsZQ0KPiA+IGluZGV4IGQw
MzgxZTkuLjMyNTdlNzEgMTAwNjQ0DQo+ID4gLS0tIGEvYXJjaC9hcm0vYm9vdC9kdHMvTWFrZWZp
bGUNCj4gPiArKysgYi9hcmNoL2FybS9ib290L2R0cy9NYWtlZmlsZQ0KPiA+IEBAIC01MTksNiAr
NTE5LDggQEAgZHRiLSQoQ09ORklHX1NPQ19JTVg3RCkgKz0gXA0KPiA+ICAgICAgICAgaW14N2Qt
c2RiLXNodDExLmR0YiBcDQo+ID4gICAgICAgICBpbXg3cy1jb2xpYnJpLWV2YWwtdjMuZHRiIFwN
Cj4gPiAgICAgICAgIGlteDdzLXdhcnAuZHRiDQo+ID4gK2R0Yi0kKENPTkZJR19TT0NfSU1YN1VM
UCkgKz0gXA0KPiA+ICsgICAgICAgaW14N3VscC1ldmsuZHRiDQo+ID4gIGR0Yi0kKENPTkZJR19T
T0NfTFMxMDIxQSkgKz0gXA0KPiA+ICAgICAgICAgbHMxMDIxYS1xZHMuZHRiIFwNCj4gPiAgICAg
ICAgIGxzMTAyMWEtdHdyLmR0Yg0KPiA+IGRpZmYgLS1naXQgYS9hcmNoL2FybS9ib290L2R0cy9p
bXg3dWxwLWV2ay5kdHMNCj4gPiBiL2FyY2gvYXJtL2Jvb3QvZHRzL2lteDd1bHAtZXZrLmR0cw0K
PiA+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0DQo+ID4gaW5kZXggMDAwMDAwMC4uY2M0ZTZlZg0KPiA+
IC0tLSAvZGV2L251bGwNCj4gPiArKysgYi9hcmNoL2FybS9ib290L2R0cy9pbXg3dWxwLWV2ay5k
dHMNCj4gPiBAQCAtMCwwICsxLDg3IEBADQo+ID4gKy8qDQo+ID4gKyAqIENvcHlyaWdodCAyMDE3
IE5YUA0KPiA+ICsgKg0KPiA+ICsgKiBUaGlzIHByb2dyYW0gaXMgZnJlZSBzb2Z0d2FyZTsgeW91
IGNhbiByZWRpc3RyaWJ1dGUgaXQgYW5kL29yDQo+ID4gK21vZGlmeQ0KPiA+ICsgKiBpdCB1bmRl
ciB0aGUgdGVybXMgb2YgdGhlIEdOVSBHZW5lcmFsIFB1YmxpYyBMaWNlbnNlIHZlcnNpb24gMiBh
cw0KPiA+ICsgKiBwdWJsaXNoZWQgYnkgdGhlIEZyZWUgU29mdHdhcmUgRm91bmRhdGlvbi4NCj4g
DQo+IFBsZWFzZSB1c2UgU1BEWCBpZGVudGlmaWVyLg0KPiANCj4gDQo+ID4gKyAqLw0KPiA+ICsN
Cj4gPiArL2R0cy12MS87DQo+ID4gKw0KPiA+ICsjaW5jbHVkZSAiaW14N3VscC5kdHNpIg0KPiA+
ICsNCj4gPiArLyB7DQo+ID4gKyAgICAgICBtb2RlbCA9ICJOWFAgaS5NWDdVTFAgRVZLIjsNCj4g
PiArICAgICAgIGNvbXBhdGlibGUgPSAiZnNsLGlteDd1bHAtZXZrIiwgImZzbCxpbXg3dWxwIiwg
IkdlbmVyaWMgRFQNCj4gPiArYmFzZWQgc3lzdGVtIjsNCj4gDQo+IFBsZWFzZSByZW1vdmUgdGhl
ICciR2VuZXJpYyBEVCBiYXNlZCBzeXN0ZW0iIGVudHJ5Lg0KPiANCj4gDQo+ID4gKw0KPiA+ICsg
ICAgICAgY2hvc2VuIHsNCj4gPiArICAgICAgICAgICAgICAgYm9vdGFyZ3MgPSAiY29uc29sZT10
dHlMUDAsMTE1MjAwDQo+IGVhcmx5Y29uPWxwdWFydDMyLDB4NDAyRDAwMTAsMTE1MjAwIjsNCj4g
PiArICAgICAgICAgICAgICAgc3Rkb3V0LXBhdGggPSAmbHB1YXJ0NDsNCj4gDQo+IEJldHRlciBy
ZW1vdmUgYm9vdGFyZ3MuDQo+IA0KPiANCj4gPiArICAgICAgIH07DQo+ID4gKw0KPiA+ICsgICAg
ICAgbWVtb3J5IHsNCj4gDQo+IG1lbW9yeUA2MDAwMDAwMCAsIG90aGVyd2lzZSBidWlsZGluZyB3
aXRoIFc9MSB3aWxsIGdpdmUgeW91IHdhcm5pbmcuDQo+IA0KPiBQbGVhc2UgbWFrZSBzdXJlIHRo
YXQgeW91IGRvbid0IGdldCBkdGMgd2FybmluZ3Mgd2l0aCBXPTEuDQo+IA0KPiA+ICsgICAgICAg
ICAgICAgICBkZXZpY2VfdHlwZSA9ICJtZW1vcnkiOw0KPiA+ICsgICAgICAgICAgICAgICByZWcg
PSA8MHg2MDAwMDAwMCAweDQwMDAwMDAwPjsNCj4gPiArICAgICAgIH07DQo+ID4gK307DQo+ID4g
Kw0KPiA+ICsmbHB1YXJ0NCB7DQo+ID4gKyAgICAgICBwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQi
Ow0KPiA+ICsgICAgICAgcGluY3RybC0wID0gPCZwaW5jdHJsX2xwdWFydDQ+Ow0KPiA+ICsgICAg
ICAgc3RhdHVzID0gIm9rYXkiOw0KPiA+ICt9Ow0KPiA+ICsNCj4gPiArJnVzZGhjMCB7DQo+ID4g
KyAgICAgICBwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOw0KPiA+ICsgICAgICAgcGluY3RybC0w
ID0gPD47DQo+ID4gKyAgICAgICBwaW5jdHJsLTAgPSA8JnBpbmN0cmxfdXNkaGMwX2NtZF9kYXRh
PiwgPCZwaW5jdHJsX3VzZGhjMF9jbGs+Ow0KPiA+ICsvLyAgICAgICAgICAgICAgICAgPCZwaW5j
dHJsX3VzZGhjMF9jZD4sIDwmcGluY3RybF91c2RoYzBfcnN0PjsNCj4gDQo+IEp1c3QgcmVtb3Zl
IHRoZSBsaW5lIGluc3RlYWQgb2YgY29tbWVudGluZyBpdC4NCj4gDQo+ID4gZGlmZiAtLWdpdCBh
L2FyY2gvYXJtL2Jvb3QvZHRzL2lteDd1bHAuZHRzaQ0KPiA+IGIvYXJjaC9hcm0vYm9vdC9kdHMv
aW14N3VscC5kdHNpIG5ldyBmaWxlIG1vZGUgMTAwNjQ0IGluZGV4DQo+ID4gMDAwMDAwMC4uMDU0
MTBiYQ0KPiA+IC0tLSAvZGV2L251bGwNCj4gPiArKysgYi9hcmNoL2FybS9ib290L2R0cy9pbXg3
dWxwLmR0c2kNCj4gPiBAQCAtMCwwICsxLDIwMiBAQA0KPiA+ICsvKg0KPiA+ICsgKiBDb3B5cmln
aHQgTlhQDQo+IA0KPiBObyB5ZWFyIGluZm9ybWF0aW9uPw0KPiANCj4gDQo+ID4gKyAqDQo+ID4g
KyAqIFRoaXMgcHJvZ3JhbSBpcyBmcmVlIHNvZnR3YXJlOyB5b3UgY2FuIHJlZGlzdHJpYnV0ZSBp
dCBhbmQvb3INCj4gPiArIG1vZGlmeQ0KPiA+ICsgKiBpdCB1bmRlciB0aGUgdGVybXMgb2YgdGhl
IEdOVSBHZW5lcmFsIFB1YmxpYyBMaWNlbnNlIHZlcnNpb24gMiBhcw0KPiA+ICsgKiBwdWJsaXNo
ZWQgYnkgdGhlIEZyZWUgU29mdHdhcmUgRm91bmRhdGlvbi4NCj4gDQo+IA0KPiBQbGVhc2UgdXNl
IFNQRFggaWRlbnRpZmllciBpbnN0ZWFkLg0KPiANCj4gPiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm0v
Y29uZmlncy9pbXhfdjZfdjdfZGVmY29uZmlnDQo+ID4gYi9hcmNoL2FybS9jb25maWdzL2lteF92
Nl92N19kZWZjb25maWcNCj4gPiBpbmRleCAwZDQ0OTQ5Li4zY2U4ZmY2IDEwMDY0NA0KPiA+IC0t
LSBhL2FyY2gvYXJtL2NvbmZpZ3MvaW14X3Y2X3Y3X2RlZmNvbmZpZw0KPiA+ICsrKyBiL2FyY2gv
YXJtL2NvbmZpZ3MvaW14X3Y2X3Y3X2RlZmNvbmZpZw0KPiA+IEBAIC00MSw2ICs0MSw3IEBAIENP
TkZJR19TT0NfSU1YNlNMPXkNCj4gPiAgQ09ORklHX1NPQ19JTVg2U1g9eQ0KPiA+ICBDT05GSUdf
U09DX0lNWDZVTD15DQo+ID4gIENPTkZJR19TT0NfSU1YN0Q9eQ0KPiA+ICtDT05GSUdfU09DX0lN
WDdVTFA9eQ0KPiANCj4gVGhpcyBzaG91bGQgYmUgcGFydCBvZiBhIHNlcGFyYXRlIHBhdGNoLg0K
PiANCj4gDQo+ID4gIENPTkZJR19TT0NfVkY2MTA9eQ0KPiA+ICBDT05GSUdfUENJPXkNCj4gPiAg
Q09ORklHX1BDSV9NU0k9eQ0KPiA+IEBAIC00OCw5ICs0OSw3IEBAIENPTkZJR19QQ0lfSU1YNj15
DQo+ID4gIENPTkZJR19TTVA9eQ0KPiA+ICBDT05GSUdfQVJNX1BTQ0k9eQ0KPiA+ICBDT05GSUdf
UFJFRU1QVF9WT0xVTlRBUlk9eQ0KPiA+IC1DT05GSUdfQUVBQkk9eQ0KPiA+ICBDT05GSUdfSElH
SE1FTT15DQo+ID4gLUNPTkZJR19DTUE9eQ0KPiA+ICBDT05GSUdfRk9SQ0VfTUFYX1pPTkVPUkRF
Uj0xNA0KPiA+ICBDT05GSUdfQ01ETElORT0ibm9pbml0cmQgY29uc29sZT10dHlteGMwLDExNTIw
MCINCj4gPiAgQ09ORklHX0tFWEVDPXkNCj4gPiBAQCAtODEsNyArODAsNiBAQCBDT05GSUdfQ0FO
X0ZMRVhDQU49eSAgQ09ORklHX0JUPXkNCj4gPiBDT05GSUdfQlRfSENJVUFSVD15ICBDT05GSUdf
QlRfSENJVUFSVF9IND15IC0NCj4gQ09ORklHX0JUX0hDSVVBUlRfTEw9eQ0KPiA+IENPTkZJR19D
Rkc4MDIxMT15ICBDT05GSUdfQ0ZHODAyMTFfV0VYVD15ICBDT05GSUdfTUFDODAyMTE9eQ0KPiBA
QCAtOTAsNw0KPiA+ICs4OCw2IEBAIENPTkZJR19SRktJTExfSU5QVVQ9eSAgQ09ORklHX0RFVlRN
UEZTPXkNCj4gPiBDT05GSUdfREVWVE1QRlNfTU9VTlQ9eSAgIyBDT05GSUdfU1RBTkRBTE9ORSBp
cyBub3Qgc2V0DQo+ID4gLUNPTkZJR19ETUFfQ01BPXkNCj4gPiAgQ09ORklHX0NNQV9TSVpFX01C
WVRFUz02NA0KPiA+ICBDT05GSUdfSU1YX1dFSU09eQ0KPiA+ICBDT05GSUdfQ09OTkVDVE9SPXkN
Cj4gPiBAQCAtMTY3LDkgKzE2NCw5IEBAIENPTkZJR19NT1VTRV9QUzJfRUxBTlRFQ0g9eQ0KPiA+
IENPTkZJR19JTlBVVF9UT1VDSFNDUkVFTj15ICBDT05GSUdfVE9VQ0hTQ1JFRU5fQURTNzg0Nj15
DQo+ID4gQ09ORklHX1RPVUNIU0NSRUVOX0VHQUxBWD15DQo+ID4gK0NPTkZJR19UT1VDSFNDUkVF
Tl9NQVgxMTgwMT15DQo+ID4gIENPTkZJR19UT1VDSFNDUkVFTl9JTVg2VUxfVFNDPXkNCj4gPiAg
Q09ORklHX1RPVUNIU0NSRUVOX0VEVF9GVDVYMDY9eQ0KPiA+IC1DT05GSUdfVE9VQ0hTQ1JFRU5f
TUFYMTE4MDE9eQ0KPiA+ICBDT05GSUdfVE9VQ0hTQ1JFRU5fTUMxMzc4Mz15DQo+ID4gIENPTkZJ
R19UT1VDSFNDUkVFTl9UU0MyMDA0PXkNCj4gPiAgQ09ORklHX1RPVUNIU0NSRUVOX1RTQzIwMDc9
eQ0KPiA+IEBAIC0xNzgsNyArMTc1LDYgQEAgQ09ORklHX1RPVUNIU0NSRUVOX1NYODY1ND15DQo+
ID4gQ09ORklHX1RPVUNIU0NSRUVOX0NPTElCUklfVkY1MD15ICBDT05GSUdfSU5QVVRfTUlTQz15
DQo+ID4gQ09ORklHX0lOUFVUX01NQTg0NTA9eSAtQ09ORklHX0hJRF9NVUxUSVRPVUNIPXkNCj4g
PiBDT05GSUdfU0VSSU9fU0VSUE9SVD1tICAjIENPTkZJR19MRUdBQ1lfUFRZUyBpcyBub3Qgc2V0
DQo+ID4gQ09ORklHX1NFUklBTF9JTVg9eSBAQCAtMjI4LDEzICsyMjQsMTMgQEANCj4gQ09ORklH
X1JFR1VMQVRPUl9HUElPPXkNCj4gPiBDT05GSUdfUkVHVUxBVE9SX01DMTM3ODM9eSAgQ09ORklH
X1JFR1VMQVRPUl9NQzEzODkyPXkNCj4gPiBDT05GSUdfUkVHVUxBVE9SX1BGVVpFMTAwPXkNCj4g
PiArQ09ORklHX1JDX0NPUkU9eQ0KPiA+ICtDT05GSUdfUkNfREVWSUNFUz15DQo+ID4gK0NPTkZJ
R19JUl9HUElPX0NJUj15DQo+ID4gIENPTkZJR19NRURJQV9TVVBQT1JUPXkNCj4gPiAgQ09ORklH
X01FRElBX0NBTUVSQV9TVVBQT1JUPXkNCj4gPiAtQ09ORklHX1JDX0NPUkU9eQ0KPiA+ICBDT05G
SUdfTUVESUFfQ09OVFJPTExFUj15DQo+ID4gIENPTkZJR19WSURFT19WNEwyX1NVQkRFVl9BUEk9
eQ0KPiA+IC1DT05GSUdfUkNfREVWSUNFUz15DQo+ID4gLUNPTkZJR19JUl9HUElPX0NJUj15DQo+
ID4gIENPTkZJR19NRURJQV9VU0JfU1VQUE9SVD15DQo+ID4gIENPTkZJR19VU0JfVklERU9fQ0xB
U1M9bQ0KPiA+ICBDT05GSUdfVjRMX1BMQVRGT1JNX0RSSVZFUlM9eQ0KPiA+IEBAIC0yNDUsNyAr
MjQxLDYgQEAgQ09ORklHX1ZJREVPX0NPREE9bSAgIw0KPiA+IENPTkZJR19NRURJQV9TVUJEUlZf
QVVUT1NFTEVDVCBpcyBub3Qgc2V0DQo+IENPTkZJR19WSURFT19BRFY3MTgwPW0NCj4gPiBDT05G
SUdfVklERU9fT1Y1NjQwPW0gLUNPTkZJR19TT0NfQ0FNRVJBX09WMjY0MD15DQo+ID4gQ09ORklH
X0lNWF9JUFVWM19DT1JFPXkgIENPTkZJR19EUk09eQ0KPiBDT05GSUdfRFJNX1BBTkVMX1NJTVBM
RT15IEBADQo+ID4gLTI4Myw2ICsyNzgsNyBAQCBDT05GSUdfU05EX1NPQ19DUzQyWFg4X0kyQz15
DQo+ID4gQ09ORklHX1NORF9TT0NfVExWMzIwQUlDM1g9eSAgQ09ORklHX1NORF9TT0NfV004OTYw
PXkNCj4gPiBDT05GSUdfU05EX1NJTVBMRV9DQVJEPXkNCj4gPiArQ09ORklHX0hJRF9NVUxUSVRP
VUNIPXkNCj4gDQo+IERvbid0IGRvIHRoZSBkZWZjb25maWcgY2xlYW51cCBpbiB0aGUgc2FtZSBw
YXRjaC4NCj4gDQo+ID4gIENPTkZJR19VU0I9eQ0KPiA+ICBDT05GSUdfVVNCX0VIQ0lfSENEPXkN
Cj4gPiAgQ09ORklHX1VTQl9FSENJX01YQz15DQo+ID4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtL21h
Y2gtaW14L0tjb25maWcgYi9hcmNoL2FybS9tYWNoLWlteC9LY29uZmlnDQo+ID4gaW5kZXggNzgy
Njk5ZS4uNTQwMDJjMyAxMDA2NDQNCj4gPiAtLS0gYS9hcmNoL2FybS9tYWNoLWlteC9LY29uZmln
DQo+ID4gKysrIGIvYXJjaC9hcm0vbWFjaC1pbXgvS2NvbmZpZw0KPiA+IEBAIC01NTQsNiArNTU0
LDE1IEBAIGNvbW1lbnQgIkNvcnRleC1BL0NvcnRleC1NIGFzeW1tZXRyaWMNCj4gbXVsdGlwcm9j
ZXNzaW5nIHBsYXRmb3JtcyINCj4gPg0KPiA+ICBpZiBBUkNIX01VTFRJX1Y3IHx8IEFSTV9TSU5H
TEVfQVJNVjdNDQo+ID4NCj4gPiArY29uZmlnIFNPQ19JTVg3VUxQDQo+ID4gKyAgICAgICBib29s
ICJpLk1YN1VMUCBzdXBwb3J0Ig0KPiA+ICsgICAgICAgc2VsZWN0IEFSTV9HSUMNCj4gPiArICAg
ICAgIHNlbGVjdCBDTEtTUkNfSU1YX1RQTQ0KPiA+ICsgICAgICAgc2VsZWN0IEhBVkVfQVJNX0FS
Q0hfVElNRVINCj4gPiArICAgICAgIHNlbGVjdCBQSU5DVFJMX0lNWDdVTFANCj4gPiArICAgICAg
IGhlbHANCj4gPiArICAgICAgICAgVGhpcyBlbmFibGVzIHN1cHBvcnQgZm9yIEZyZWVzY2FsZSBp
Lk1YNyBVbHRyYSBMb3cgUG93ZXIgcHJvY2Vzc29yLg0KPiA+ICsNCj4gPiAgY29uZmlnIFNPQ19W
RjYxMA0KPiA+ICAgICAgICAgYm9vbCAiVnlicmlkIEZhbWlseSBWRjYxMCBzdXBwb3J0Ig0KPiA+
ICAgICAgICAgc2VsZWN0IEFSTV9HSUMgaWYgQVJDSF9NVUxUSV9WNyBkaWZmIC0tZ2l0DQo+ID4g
YS9hcmNoL2FybS9tYWNoLWlteC9NYWtlZmlsZSBiL2FyY2gvYXJtL21hY2gtaW14L01ha2VmaWxl
IGluZGV4DQo+ID4gOGZmNzEwNS4uNjljMjUxNyAxMDA2NDQNCj4gPiAtLS0gYS9hcmNoL2FybS9t
YWNoLWlteC9NYWtlZmlsZQ0KPiA+ICsrKyBiL2FyY2gvYXJtL21hY2gtaW14L01ha2VmaWxlDQo+
IA0KPiBhcmNoL2FybS9tYWNoLWlteCBjaGFuZ2VzIGNhbiBhbHNvIGdvIGluIGEgZGlmZmVyZW50
IHBhdGNoLg0K
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH V3 10/10] add imx7ulp support
@ 2018-01-25 13:46 ` A.s. Dong
0 siblings, 0 replies; 41+ messages in thread
From: A.s. Dong @ 2018-01-25 13:46 UTC (permalink / raw)
To: linux-arm-kernel
Hi Fabio,
This patch (Patch 10) is used for test and was sent out by accidently, not formal one.
I also explained in another email. Guess you may not see it.
Really sorry for the inconvenience.
Regards
Dong Aisheng
> -----Original Message-----
> From: Fabio Estevam [mailto:festevam at gmail.com]
> Sent: Thursday, January 25, 2018 9:22 PM
> To: A.s. Dong <aisheng.dong@nxp.com>
> Cc: linux-clk <linux-clk@vger.kernel.org>; Jacky Bai <ping.bai@nxp.com>;
> Anson Huang <anson.huang@nxp.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@codeaurora.org>; linux-
> kernel <linux-kernel@vger.kernel.org>; dl-linux-imx <linux-imx@nxp.com>;
> Fabio Estevam <fabio.estevam@nxp.com>; Shawn Guo
> <shawnguo@kernel.org>; moderated list:ARM/FREESCALE IMX / MXC ARM
> ARCHITECTURE <linux-arm-kernel@lists.infradead.org>
> Subject: Re: [PATCH V3 10/10] add imx7ulp support
>
> On Fri, Jan 19, 2018 at 11:11 AM, Dong Aisheng <aisheng.dong@nxp.com>
> wrote:
>
> Please always add a commit log.
>
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
>
> > ---
> > arch/arm/boot/dts/Makefile | 2 +
> > arch/arm/boot/dts/imx7ulp-evk.dts | 87 +++++++++++++++
> > arch/arm/boot/dts/imx7ulp.dtsi | 202
> +++++++++++++++++++++++++++++++++++
> > arch/arm/configs/imx_v6_v7_defconfig | 16 ++-
> > arch/arm/mach-imx/Kconfig | 9 ++
> > arch/arm/mach-imx/Makefile | 1 +
> > arch/arm/mach-imx/common.h | 1 +
> > arch/arm/mach-imx/cpu.c | 3 +
> > arch/arm/mach-imx/mach-imx7ulp.c | 37 +++++++
> > arch/arm/mach-imx/mxc.h | 1 +
> > arch/arm/mach-imx/pm-imx7ulp.c | 32 ++++++
> > 11 files changed, 381 insertions(+), 10 deletions(-) create mode
> > 100644 arch/arm/boot/dts/imx7ulp-evk.dts create mode 100644
> > arch/arm/boot/dts/imx7ulp.dtsi create mode 100644
> > arch/arm/mach-imx/mach-imx7ulp.c create mode 100644
> > arch/arm/mach-imx/pm-imx7ulp.c
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index d0381e9..3257e71 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -519,6 +519,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
> > imx7d-sdb-sht11.dtb \
> > imx7s-colibri-eval-v3.dtb \
> > imx7s-warp.dtb
> > +dtb-$(CONFIG_SOC_IMX7ULP) += \
> > + imx7ulp-evk.dtb
> > dtb-$(CONFIG_SOC_LS1021A) += \
> > ls1021a-qds.dtb \
> > ls1021a-twr.dtb
> > diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts
> > b/arch/arm/boot/dts/imx7ulp-evk.dts
> > new file mode 100644
> > index 0000000..cc4e6ef
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx7ulp-evk.dts
> > @@ -0,0 +1,87 @@
> > +/*
> > + * Copyright 2017 NXP
> > + *
> > + * This program is free software; you can redistribute it and/or
> > +modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
>
> Please use SPDX identifier.
>
>
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx7ulp.dtsi"
> > +
> > +/ {
> > + model = "NXP i.MX7ULP EVK";
> > + compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT
> > +based system";
>
> Please remove the '"Generic DT based system" entry.
>
>
> > +
> > + chosen {
> > + bootargs = "console=ttyLP0,115200
> earlycon=lpuart32,0x402D0010,115200";
> > + stdout-path = &lpuart4;
>
> Better remove bootargs.
>
>
> > + };
> > +
> > + memory {
>
> memory at 60000000 , otherwise building with W=1 will give you warning.
>
> Please make sure that you don't get dtc warnings with W=1.
>
> > + device_type = "memory";
> > + reg = <0x60000000 0x40000000>;
> > + };
> > +};
> > +
> > +&lpuart4 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_lpuart4>;
> > + status = "okay";
> > +};
> > +
> > +&usdhc0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <>;
> > + pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>;
> > +// <&pinctrl_usdhc0_cd>, <&pinctrl_usdhc0_rst>;
>
> Just remove the line instead of commenting it.
>
> > diff --git a/arch/arm/boot/dts/imx7ulp.dtsi
> > b/arch/arm/boot/dts/imx7ulp.dtsi new file mode 100644 index
> > 0000000..05410ba
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> > @@ -0,0 +1,202 @@
> > +/*
> > + * Copyright NXP
>
> No year information?
>
>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
>
>
> Please use SPDX identifier instead.
>
> > diff --git a/arch/arm/configs/imx_v6_v7_defconfig
> > b/arch/arm/configs/imx_v6_v7_defconfig
> > index 0d44949..3ce8ff6 100644
> > --- a/arch/arm/configs/imx_v6_v7_defconfig
> > +++ b/arch/arm/configs/imx_v6_v7_defconfig
> > @@ -41,6 +41,7 @@ CONFIG_SOC_IMX6SL=y
> > CONFIG_SOC_IMX6SX=y
> > CONFIG_SOC_IMX6UL=y
> > CONFIG_SOC_IMX7D=y
> > +CONFIG_SOC_IMX7ULP=y
>
> This should be part of a separate patch.
>
>
> > CONFIG_SOC_VF610=y
> > CONFIG_PCI=y
> > CONFIG_PCI_MSI=y
> > @@ -48,9 +49,7 @@ CONFIG_PCI_IMX6=y
> > CONFIG_SMP=y
> > CONFIG_ARM_PSCI=y
> > CONFIG_PREEMPT_VOLUNTARY=y
> > -CONFIG_AEABI=y
> > CONFIG_HIGHMEM=y
> > -CONFIG_CMA=y
> > CONFIG_FORCE_MAX_ZONEORDER=14
> > CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
> > CONFIG_KEXEC=y
> > @@ -81,7 +80,6 @@ CONFIG_CAN_FLEXCAN=y CONFIG_BT=y
> > CONFIG_BT_HCIUART=y CONFIG_BT_HCIUART_H4=y -
> CONFIG_BT_HCIUART_LL=y
> > CONFIG_CFG80211=y CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=y
> @@ -90,7
> > +88,6 @@ CONFIG_RFKILL_INPUT=y CONFIG_DEVTMPFS=y
> > CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set
> > -CONFIG_DMA_CMA=y
> > CONFIG_CMA_SIZE_MBYTES=64
> > CONFIG_IMX_WEIM=y
> > CONFIG_CONNECTOR=y
> > @@ -167,9 +164,9 @@ CONFIG_MOUSE_PS2_ELANTECH=y
> > CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=y
> > CONFIG_TOUCHSCREEN_EGALAX=y
> > +CONFIG_TOUCHSCREEN_MAX11801=y
> > CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
> > CONFIG_TOUCHSCREEN_EDT_FT5X06=y
> > -CONFIG_TOUCHSCREEN_MAX11801=y
> > CONFIG_TOUCHSCREEN_MC13783=y
> > CONFIG_TOUCHSCREEN_TSC2004=y
> > CONFIG_TOUCHSCREEN_TSC2007=y
> > @@ -178,7 +175,6 @@ CONFIG_TOUCHSCREEN_SX8654=y
> > CONFIG_TOUCHSCREEN_COLIBRI_VF50=y CONFIG_INPUT_MISC=y
> > CONFIG_INPUT_MMA8450=y -CONFIG_HID_MULTITOUCH=y
> > CONFIG_SERIO_SERPORT=m # CONFIG_LEGACY_PTYS is not set
> > CONFIG_SERIAL_IMX=y @@ -228,13 +224,13 @@
> CONFIG_REGULATOR_GPIO=y
> > CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y
> > CONFIG_REGULATOR_PFUZE100=y
> > +CONFIG_RC_CORE=y
> > +CONFIG_RC_DEVICES=y
> > +CONFIG_IR_GPIO_CIR=y
> > CONFIG_MEDIA_SUPPORT=y
> > CONFIG_MEDIA_CAMERA_SUPPORT=y
> > -CONFIG_RC_CORE=y
> > CONFIG_MEDIA_CONTROLLER=y
> > CONFIG_VIDEO_V4L2_SUBDEV_API=y
> > -CONFIG_RC_DEVICES=y
> > -CONFIG_IR_GPIO_CIR=y
> > CONFIG_MEDIA_USB_SUPPORT=y
> > CONFIG_USB_VIDEO_CLASS=m
> > CONFIG_V4L_PLATFORM_DRIVERS=y
> > @@ -245,7 +241,6 @@ CONFIG_VIDEO_CODA=m #
> > CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
> CONFIG_VIDEO_ADV7180=m
> > CONFIG_VIDEO_OV5640=m -CONFIG_SOC_CAMERA_OV2640=y
> > CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y
> CONFIG_DRM_PANEL_SIMPLE=y @@
> > -283,6 +278,7 @@ CONFIG_SND_SOC_CS42XX8_I2C=y
> > CONFIG_SND_SOC_TLV320AIC3X=y CONFIG_SND_SOC_WM8960=y
> > CONFIG_SND_SIMPLE_CARD=y
> > +CONFIG_HID_MULTITOUCH=y
>
> Don't do the defconfig cleanup in the same patch.
>
> > CONFIG_USB=y
> > CONFIG_USB_EHCI_HCD=y
> > CONFIG_USB_EHCI_MXC=y
> > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> > index 782699e..54002c3 100644
> > --- a/arch/arm/mach-imx/Kconfig
> > +++ b/arch/arm/mach-imx/Kconfig
> > @@ -554,6 +554,15 @@ comment "Cortex-A/Cortex-M asymmetric
> multiprocessing platforms"
> >
> > if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
> >
> > +config SOC_IMX7ULP
> > + bool "i.MX7ULP support"
> > + select ARM_GIC
> > + select CLKSRC_IMX_TPM
> > + select HAVE_ARM_ARCH_TIMER
> > + select PINCTRL_IMX7ULP
> > + help
> > + This enables support for Freescale i.MX7 Ultra Low Power processor.
> > +
> > config SOC_VF610
> > bool "Vybrid Family VF610 support"
> > select ARM_GIC if ARCH_MULTI_V7 diff --git
> > a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index
> > 8ff7105..69c2517 100644
> > --- a/arch/arm/mach-imx/Makefile
> > +++ b/arch/arm/mach-imx/Makefile
>
> arch/arm/mach-imx changes can also go in a different patch.
^ permalink raw reply [flat|nested] 41+ messages in thread
end of thread, other threads:[~2018-01-25 13:46 UTC | newest]
Thread overview: 41+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-19 13:11 [PATCH V3 00/10] clk: add imx7ulp clk support Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-19 13:11 ` [PATCH V3 01/10] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE " Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-23 11:03 ` Jerome Brunet
2018-01-23 11:03 ` Jerome Brunet
2018-01-23 12:21 ` Dong Aisheng
2018-01-23 12:21 ` Dong Aisheng
2018-01-23 13:10 ` Jerome Brunet
2018-01-23 13:10 ` Jerome Brunet
2018-01-23 13:10 ` Jerome Brunet
2018-01-19 13:11 ` [PATCH V3 02/10] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-19 13:11 ` [PATCH V3 03/10] clk: imx: add pllv4 support Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-19 13:11 ` [PATCH V3 04/10] clk: imx: add pfdv2 support Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-19 13:11 ` [PATCH V3 05/10] clk: imx: add composite clk support Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-19 13:11 ` [PATCH V3 06/10] dt-bindings: clock: add imx7ulp clock binding doc Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-19 13:11 ` [PATCH V3 07/10] clk: imx: make mux parent strings const Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-19 13:11 ` [PATCH V3 08/10] clk: imx: implement new clk_hw based APIs Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-19 13:11 ` [PATCH V3 09/10] clk: imx: add imx7ulp clk driver Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-19 13:11 ` [PATCH V3 10/10] add imx7ulp support Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-19 13:11 ` Dong Aisheng
2018-01-19 13:19 ` A.s. Dong
2018-01-19 13:19 ` A.s. Dong
2018-01-19 13:19 ` A.s. Dong
2018-01-25 13:22 ` Fabio Estevam
2018-01-25 13:22 ` Fabio Estevam
2018-01-25 13:46 ` A.s. Dong
2018-01-25 13:46 ` A.s. Dong
2018-01-25 13:46 ` A.s. Dong
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.