From: Julien Thierry <julien.thierry@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Julien Thierry <julien.thierry@arm.com>, Ard Biesheuvel <ard.biesheuvel@linaro.org>, Oleg Nesterov <oleg@redhat.com> Subject: [PATCH v6 10/24] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Date: Mon, 12 Nov 2018 11:57:01 +0000 [thread overview] Message-ID: <1542023835-21446-11-git-send-email-julien.thierry@arm.com> (raw) In-Reply-To: <1542023835-21446-1-git-send-email-julien.thierry@arm.com> Instead disabling interrupts by setting the PSR.I bit, use a priority higher than the one used for interrupts to mask them via PMR. The value chosen for PMR to enable/disable interrupts encodes the status of interrupts on a single bit. This information is stored in the irqflags values used when saving/restoring IRQ status. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Suggested-by: Daniel Thompson <daniel.thompson@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Oleg Nesterov <oleg@redhat.com> --- arch/arm64/include/asm/efi.h | 3 +- arch/arm64/include/asm/irqflags.h | 132 +++++++++++++++++++++++++++++--------- 2 files changed, 105 insertions(+), 30 deletions(-) diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h index 7ed3208..3e06891 100644 --- a/arch/arm64/include/asm/efi.h +++ b/arch/arm64/include/asm/efi.h @@ -42,7 +42,8 @@ efi_status_t __efi_rt_asm_wrapper(void *, const char *, ...); -#define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT) +#define ARCH_EFI_IRQ_FLAGS_MASK \ + (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | ARCH_FLAG_PMR_EN) /* arch specific definitions used by the stub code */ diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h index 24692ed..e0a32e4 100644 --- a/arch/arm64/include/asm/irqflags.h +++ b/arch/arm64/include/asm/irqflags.h @@ -18,7 +18,27 @@ #ifdef __KERNEL__ +#include <asm/alternative.h> +#include <asm/cpufeature.h> #include <asm/ptrace.h> +#include <asm/sysreg.h> + + +/* + * When ICC_PMR_EL1 is used for interrupt masking, only the bit indicating + * whether the normal interrupts are masked is kept along with the daif + * flags. + */ +#define ARCH_FLAG_PMR_EN 0x1 + +#define MAKE_ARCH_FLAGS(daif, pmr) \ + ((daif) | (((pmr) >> GIC_PRIO_STATUS_SHIFT) & ARCH_FLAG_PMR_EN)) + +#define ARCH_FLAGS_GET_PMR(flags) \ + ((((flags) & ARCH_FLAG_PMR_EN) << GIC_PRIO_STATUS_SHIFT) \ + | GIC_PRIO_IRQOFF) + +#define ARCH_FLAGS_GET_DAIF(flags) ((flags) & ~ARCH_FLAG_PMR_EN) /* * Aarch64 has flags for masking: Debug, Asynchronous (serror), Interrupts and @@ -34,35 +54,62 @@ */ /* - * CPU interrupt mask handling. + * Local definitions to help us manage between PMR and daif */ -static inline unsigned long arch_local_irq_save(void) -{ - unsigned long flags; - asm volatile( - "mrs %0, daif // arch_local_irq_save\n" - "msr daifset, #2" - : "=r" (flags) - : - : "memory"); - return flags; -} +#define _save_daif(dest) \ + asm volatile("mrs %0, daif" : "=&r" (dest) : : "memory") + +#define _restore_daif(daif) \ + asm volatile("msr daif, %0" : : "r" (daif) : "memory") +#define _save_pmr(dest) \ + asm volatile(ALTERNATIVE( \ + "mov %0, #" __stringify(GIC_PRIO_IRQON), \ + "mrs_s %0, " __stringify(SYS_ICC_PMR_EL1), \ + ARM64_HAS_IRQ_PRIO_MASKING) \ + : "=&r" (dest) \ + : \ + : "memory") + +#define _restore_pmr(pmr) \ + asm volatile(ALTERNATIVE( \ + "nop\n" \ + "nop", \ + "msr_s " __stringify(SYS_ICC_PMR_EL1) ",%0\n" \ + "dsb sy", \ + ARM64_HAS_IRQ_PRIO_MASKING) \ + : \ + : "r" (pmr) \ + : "memory") + +/* + * CPU interrupt mask handling. + */ static inline void arch_local_irq_enable(void) { - asm volatile( - "msr daifclr, #2 // arch_local_irq_enable" - : + unsigned long unmasked = GIC_PRIO_IRQON; + + asm volatile(ALTERNATIVE( + "msr daifclr, #2 // arch_local_irq_enable\n" + "nop", + "msr_s " __stringify(SYS_ICC_PMR_EL1) ",%0\n" + "dsb sy", + ARM64_HAS_IRQ_PRIO_MASKING) : + : "r" (unmasked) : "memory"); } static inline void arch_local_irq_disable(void) { - asm volatile( - "msr daifset, #2 // arch_local_irq_disable" - : + unsigned long masked = GIC_PRIO_IRQOFF; + + asm volatile(ALTERNATIVE( + "msr daifset, #2 // arch_local_irq_disable", + "msr_s " __stringify(SYS_ICC_PMR_EL1) ",%0", + ARM64_HAS_IRQ_PRIO_MASKING) : + : "r" (masked) : "memory"); } @@ -71,12 +118,24 @@ static inline void arch_local_irq_disable(void) */ static inline unsigned long arch_local_save_flags(void) { + unsigned long daif_flags; + unsigned long pmr; + + _save_daif(daif_flags); + + _save_pmr(pmr); + + return MAKE_ARCH_FLAGS(daif_flags, pmr); +} + +static inline unsigned long arch_local_irq_save(void) +{ unsigned long flags; - asm volatile( - "mrs %0, daif // arch_local_save_flags" - : "=r" (flags) - : - : "memory"); + + flags = arch_local_save_flags(); + + arch_local_irq_disable(); + return flags; } @@ -85,16 +144,31 @@ static inline unsigned long arch_local_save_flags(void) */ static inline void arch_local_irq_restore(unsigned long flags) { - asm volatile( - "msr daif, %0 // arch_local_irq_restore" - : - : "r" (flags) - : "memory"); + unsigned long pmr = ARCH_FLAGS_GET_PMR(flags); + + flags = ARCH_FLAGS_GET_DAIF(flags); + + /* + * Code switching from PSR.I interrupt disabling to PMR masking + * should not lie between consecutive calls to local_irq_save() + * and local_irq_restore() in the same context. + * So restoring PMR and then the daif flags should be safe. + */ + _restore_pmr(pmr); + + _restore_daif(flags); } static inline int arch_irqs_disabled_flags(unsigned long flags) { - return flags & PSR_I_BIT; + return (ARCH_FLAGS_GET_DAIF(flags) & (PSR_I_BIT)) | + !(ARCH_FLAGS_GET_PMR(flags) & GIC_PRIO_STATUS_BIT); } + +#undef _save_daif +#undef _restore_daif +#undef _save_pmr +#undef _restore_pmr + #endif #endif -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: julien.thierry@arm.com (Julien Thierry) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 10/24] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Date: Mon, 12 Nov 2018 11:57:01 +0000 [thread overview] Message-ID: <1542023835-21446-11-git-send-email-julien.thierry@arm.com> (raw) In-Reply-To: <1542023835-21446-1-git-send-email-julien.thierry@arm.com> Instead disabling interrupts by setting the PSR.I bit, use a priority higher than the one used for interrupts to mask them via PMR. The value chosen for PMR to enable/disable interrupts encodes the status of interrupts on a single bit. This information is stored in the irqflags values used when saving/restoring IRQ status. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Suggested-by: Daniel Thompson <daniel.thompson@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Oleg Nesterov <oleg@redhat.com> --- arch/arm64/include/asm/efi.h | 3 +- arch/arm64/include/asm/irqflags.h | 132 +++++++++++++++++++++++++++++--------- 2 files changed, 105 insertions(+), 30 deletions(-) diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h index 7ed3208..3e06891 100644 --- a/arch/arm64/include/asm/efi.h +++ b/arch/arm64/include/asm/efi.h @@ -42,7 +42,8 @@ efi_status_t __efi_rt_asm_wrapper(void *, const char *, ...); -#define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT) +#define ARCH_EFI_IRQ_FLAGS_MASK \ + (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | ARCH_FLAG_PMR_EN) /* arch specific definitions used by the stub code */ diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h index 24692ed..e0a32e4 100644 --- a/arch/arm64/include/asm/irqflags.h +++ b/arch/arm64/include/asm/irqflags.h @@ -18,7 +18,27 @@ #ifdef __KERNEL__ +#include <asm/alternative.h> +#include <asm/cpufeature.h> #include <asm/ptrace.h> +#include <asm/sysreg.h> + + +/* + * When ICC_PMR_EL1 is used for interrupt masking, only the bit indicating + * whether the normal interrupts are masked is kept along with the daif + * flags. + */ +#define ARCH_FLAG_PMR_EN 0x1 + +#define MAKE_ARCH_FLAGS(daif, pmr) \ + ((daif) | (((pmr) >> GIC_PRIO_STATUS_SHIFT) & ARCH_FLAG_PMR_EN)) + +#define ARCH_FLAGS_GET_PMR(flags) \ + ((((flags) & ARCH_FLAG_PMR_EN) << GIC_PRIO_STATUS_SHIFT) \ + | GIC_PRIO_IRQOFF) + +#define ARCH_FLAGS_GET_DAIF(flags) ((flags) & ~ARCH_FLAG_PMR_EN) /* * Aarch64 has flags for masking: Debug, Asynchronous (serror), Interrupts and @@ -34,35 +54,62 @@ */ /* - * CPU interrupt mask handling. + * Local definitions to help us manage between PMR and daif */ -static inline unsigned long arch_local_irq_save(void) -{ - unsigned long flags; - asm volatile( - "mrs %0, daif // arch_local_irq_save\n" - "msr daifset, #2" - : "=r" (flags) - : - : "memory"); - return flags; -} +#define _save_daif(dest) \ + asm volatile("mrs %0, daif" : "=&r" (dest) : : "memory") + +#define _restore_daif(daif) \ + asm volatile("msr daif, %0" : : "r" (daif) : "memory") +#define _save_pmr(dest) \ + asm volatile(ALTERNATIVE( \ + "mov %0, #" __stringify(GIC_PRIO_IRQON), \ + "mrs_s %0, " __stringify(SYS_ICC_PMR_EL1), \ + ARM64_HAS_IRQ_PRIO_MASKING) \ + : "=&r" (dest) \ + : \ + : "memory") + +#define _restore_pmr(pmr) \ + asm volatile(ALTERNATIVE( \ + "nop\n" \ + "nop", \ + "msr_s " __stringify(SYS_ICC_PMR_EL1) ",%0\n" \ + "dsb sy", \ + ARM64_HAS_IRQ_PRIO_MASKING) \ + : \ + : "r" (pmr) \ + : "memory") + +/* + * CPU interrupt mask handling. + */ static inline void arch_local_irq_enable(void) { - asm volatile( - "msr daifclr, #2 // arch_local_irq_enable" - : + unsigned long unmasked = GIC_PRIO_IRQON; + + asm volatile(ALTERNATIVE( + "msr daifclr, #2 // arch_local_irq_enable\n" + "nop", + "msr_s " __stringify(SYS_ICC_PMR_EL1) ",%0\n" + "dsb sy", + ARM64_HAS_IRQ_PRIO_MASKING) : + : "r" (unmasked) : "memory"); } static inline void arch_local_irq_disable(void) { - asm volatile( - "msr daifset, #2 // arch_local_irq_disable" - : + unsigned long masked = GIC_PRIO_IRQOFF; + + asm volatile(ALTERNATIVE( + "msr daifset, #2 // arch_local_irq_disable", + "msr_s " __stringify(SYS_ICC_PMR_EL1) ",%0", + ARM64_HAS_IRQ_PRIO_MASKING) : + : "r" (masked) : "memory"); } @@ -71,12 +118,24 @@ static inline void arch_local_irq_disable(void) */ static inline unsigned long arch_local_save_flags(void) { + unsigned long daif_flags; + unsigned long pmr; + + _save_daif(daif_flags); + + _save_pmr(pmr); + + return MAKE_ARCH_FLAGS(daif_flags, pmr); +} + +static inline unsigned long arch_local_irq_save(void) +{ unsigned long flags; - asm volatile( - "mrs %0, daif // arch_local_save_flags" - : "=r" (flags) - : - : "memory"); + + flags = arch_local_save_flags(); + + arch_local_irq_disable(); + return flags; } @@ -85,16 +144,31 @@ static inline unsigned long arch_local_save_flags(void) */ static inline void arch_local_irq_restore(unsigned long flags) { - asm volatile( - "msr daif, %0 // arch_local_irq_restore" - : - : "r" (flags) - : "memory"); + unsigned long pmr = ARCH_FLAGS_GET_PMR(flags); + + flags = ARCH_FLAGS_GET_DAIF(flags); + + /* + * Code switching from PSR.I interrupt disabling to PMR masking + * should not lie between consecutive calls to local_irq_save() + * and local_irq_restore() in the same context. + * So restoring PMR and then the daif flags should be safe. + */ + _restore_pmr(pmr); + + _restore_daif(flags); } static inline int arch_irqs_disabled_flags(unsigned long flags) { - return flags & PSR_I_BIT; + return (ARCH_FLAGS_GET_DAIF(flags) & (PSR_I_BIT)) | + !(ARCH_FLAGS_GET_PMR(flags) & GIC_PRIO_STATUS_BIT); } + +#undef _save_daif +#undef _restore_daif +#undef _save_pmr +#undef _restore_pmr + #endif #endif -- 1.9.1
next prev parent reply other threads:[~2018-11-12 11:57 UTC|newest] Thread overview: 125+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-11-12 11:56 [PATCH v6 00/24] arm64: provide pseudo NMI with GICv3 Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-12 11:56 ` [PATCH v6 01/24] arm64: Remove unused daif related functions/macros Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-29 16:26 ` Mark Rutland 2018-11-29 16:26 ` Mark Rutland 2018-11-30 18:03 ` Catalin Marinas 2018-11-30 18:03 ` Catalin Marinas 2018-11-12 11:56 ` [PATCH v6 02/24] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-12 18:00 ` Suzuki K Poulose 2018-11-12 18:00 ` Suzuki K Poulose 2018-11-29 16:27 ` Mark Rutland 2018-11-29 16:27 ` Mark Rutland 2018-11-30 18:07 ` Catalin Marinas 2018-11-30 18:07 ` Catalin Marinas 2018-11-12 11:56 ` [PATCH v6 03/24] arm64: cpufeature: Add cpufeature for IRQ priority masking Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-12 18:02 ` Suzuki K Poulose 2018-11-12 18:02 ` Suzuki K Poulose 2018-11-29 17:12 ` Mark Rutland 2018-11-29 17:12 ` Mark Rutland 2018-12-03 10:33 ` Julien Thierry 2018-12-03 10:33 ` Julien Thierry 2018-11-30 18:07 ` Catalin Marinas 2018-11-30 18:07 ` Catalin Marinas 2018-11-12 11:56 ` [PATCH v6 04/24] arm/arm64: gic-v3: Add PMR and RPR accessors Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-29 16:32 ` Mark Rutland 2018-11-29 16:32 ` Mark Rutland 2018-11-30 18:07 ` Catalin Marinas 2018-11-30 18:07 ` Catalin Marinas 2018-11-12 11:56 ` [PATCH v6 05/24] irqchip/gic-v3: Switch to PMR masking before calling IRQ handler Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-29 18:12 ` Mark Rutland 2018-11-29 18:12 ` Mark Rutland 2018-11-30 9:18 ` Julien Thierry 2018-11-30 9:18 ` Julien Thierry 2018-12-04 16:21 ` Catalin Marinas 2018-12-04 16:21 ` Catalin Marinas 2018-11-12 11:56 ` [PATCH v6 06/24] arm64: ptrace: Provide definitions for PMR values Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-29 16:40 ` Mark Rutland 2018-11-29 16:40 ` Mark Rutland 2018-11-30 8:53 ` Julien Thierry 2018-11-30 8:53 ` Julien Thierry 2018-11-30 10:38 ` Daniel Thompson 2018-11-30 10:38 ` Daniel Thompson 2018-11-30 11:03 ` Julien Thierry 2018-11-30 11:03 ` Julien Thierry 2018-11-12 11:56 ` [PATCH v6 07/24] arm64: Make PMR part of task context Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-29 16:46 ` Mark Rutland 2018-11-29 16:46 ` Mark Rutland 2018-11-30 9:25 ` Julien Thierry 2018-11-30 9:25 ` Julien Thierry 2018-12-04 17:09 ` Catalin Marinas 2018-12-04 17:09 ` Catalin Marinas 2018-12-04 17:30 ` Julien Thierry 2018-12-04 17:30 ` Julien Thierry 2018-11-12 11:56 ` [PATCH v6 08/24] arm64: Unmask PMR before going idle Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-29 17:44 ` Mark Rutland 2018-11-29 17:44 ` Mark Rutland 2018-11-30 10:55 ` Julien Thierry 2018-11-30 10:55 ` Julien Thierry 2018-11-30 13:37 ` Mark Rutland 2018-11-30 13:37 ` Mark Rutland 2018-12-03 10:38 ` Julien Thierry 2018-12-03 10:38 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 09/24] arm64: kvm: Unmask PMR before entering guest Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` Julien Thierry [this message] 2018-11-12 11:57 ` [PATCH v6 10/24] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Julien Thierry 2018-12-04 17:36 ` Catalin Marinas 2018-12-04 17:36 ` Catalin Marinas 2018-12-05 16:55 ` Julien Thierry 2018-12-05 16:55 ` Julien Thierry 2018-12-05 18:26 ` Catalin Marinas 2018-12-05 18:26 ` Catalin Marinas 2018-12-06 9:50 ` Julien Thierry 2018-12-06 9:50 ` Julien Thierry 2018-12-10 14:39 ` Catalin Marinas 2018-12-10 14:39 ` Catalin Marinas 2018-11-12 11:57 ` [PATCH v6 11/24] arm64: daifflags: Include PMR in daifflags restore operations Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 12/24] arm64: alternative: Allow alternative status checking per cpufeature Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 13/24] arm64: alternative: Apply alternatives early in boot process Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 14/24] irqchip/gic-v3: Factor group0 detection into functions Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 15/24] arm64: Switch to PMR masking when starting CPUs Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-12-04 17:51 ` Catalin Marinas 2018-12-04 17:51 ` Catalin Marinas 2018-12-04 18:11 ` Julien Thierry 2018-12-04 18:11 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 16/24] arm64: gic-v3: Implement arch support for priority masking Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 17/24] irqchip/gic-v3: Detect if GIC can support pseudo-NMIs Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 18/24] irqchip/gic-v3: Handle pseudo-NMIs Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 19/24] irqchip/gic: Add functions to access irq priorities Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 20/24] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 21/24] arm64: Handle serror in NMI context Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-12-04 18:09 ` Catalin Marinas 2018-12-04 18:09 ` Catalin Marinas 2018-12-05 13:02 ` James Morse 2018-12-05 13:02 ` James Morse 2018-11-12 11:57 ` [PATCH v6 22/24] arm64: Skip preemption when exiting an NMI Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 23/24] arm64: Skip irqflags tracing for NMI in IRQs disabled context Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 24/24] arm64: Enable the support of pseudo-NMIs Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 12:00 ` [PATCH v6 00/24] arm64: provide pseudo NMI with GICv3 Julien Thierry 2018-11-12 12:00 ` Julien Thierry 2018-11-13 14:43 ` Julien Thierry 2018-11-13 14:43 ` Julien Thierry
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