From: Julien Thierry <julien.thierry@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Julien Thierry <julien.thierry@arm.com>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net> Subject: [PATCH v6 14/24] irqchip/gic-v3: Factor group0 detection into functions Date: Mon, 12 Nov 2018 11:57:05 +0000 [thread overview] Message-ID: <1542023835-21446-15-git-send-email-julien.thierry@arm.com> (raw) In-Reply-To: <1542023835-21446-1-git-send-email-julien.thierry@arm.com> The code to detect whether Linux has access to group0 interrupts can prove useful in other parts of the driver. Provide a separate function to do this. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> --- drivers/irqchip/irq-gic-v3.c | 55 +++++++++++++++++++++++++++++--------------- 1 file changed, 36 insertions(+), 19 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index e5d8c14..dbf5247 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -399,6 +399,39 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs } } +static u32 gic_get_pribits(void) +{ + u32 pribits; + + pribits = gic_read_ctlr(); + pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; + pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; + pribits++; + + return pribits; +} + +static bool gic_has_group0(void) +{ + u32 val; + + /* + * Let's find out if Group0 is under control of EL3 or not by + * setting the highest possible, non-zero priority in PMR. + * + * If SCR_EL3.FIQ is set, the priority gets shifted down in + * order for the CPU interface to set bit 7, and keep the + * actual priority in the non-secure range. In the process, it + * looses the least significant bit and the actual priority + * becomes 0x80. Reading it back returns 0, indicating that + * we're don't have access to Group0. + */ + gic_write_pmr(BIT(8 - gic_get_pribits())); + val = gic_read_pmr(); + + return val != 0; +} + static void __init gic_dist_init(void) { unsigned int i; @@ -540,7 +573,7 @@ static void gic_cpu_sys_reg_init(void) u64 mpidr = cpu_logical_map(cpu); u64 need_rss = MPIDR_RS(mpidr); bool group0; - u32 val, pribits; + u32 pribits; /* * Need to check that the SRE bit has actually been set. If @@ -552,25 +585,9 @@ static void gic_cpu_sys_reg_init(void) if (!gic_enable_sre()) pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); - pribits = gic_read_ctlr(); - pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; - pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; - pribits++; + pribits = gic_get_pribits(); - /* - * Let's find out if Group0 is under control of EL3 or not by - * setting the highest possible, non-zero priority in PMR. - * - * If SCR_EL3.FIQ is set, the priority gets shifted down in - * order for the CPU interface to set bit 7, and keep the - * actual priority in the non-secure range. In the process, it - * looses the least significant bit and the actual priority - * becomes 0x80. Reading it back returns 0, indicating that - * we're don't have access to Group0. - */ - write_gicreg(BIT(8 - pribits), ICC_PMR_EL1); - val = read_gicreg(ICC_PMR_EL1); - group0 = val != 0; + group0 = gic_has_group0(); /* Set priority mask register */ write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: julien.thierry@arm.com (Julien Thierry) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 14/24] irqchip/gic-v3: Factor group0 detection into functions Date: Mon, 12 Nov 2018 11:57:05 +0000 [thread overview] Message-ID: <1542023835-21446-15-git-send-email-julien.thierry@arm.com> (raw) In-Reply-To: <1542023835-21446-1-git-send-email-julien.thierry@arm.com> The code to detect whether Linux has access to group0 interrupts can prove useful in other parts of the driver. Provide a separate function to do this. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> --- drivers/irqchip/irq-gic-v3.c | 55 +++++++++++++++++++++++++++++--------------- 1 file changed, 36 insertions(+), 19 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index e5d8c14..dbf5247 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -399,6 +399,39 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs } } +static u32 gic_get_pribits(void) +{ + u32 pribits; + + pribits = gic_read_ctlr(); + pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; + pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; + pribits++; + + return pribits; +} + +static bool gic_has_group0(void) +{ + u32 val; + + /* + * Let's find out if Group0 is under control of EL3 or not by + * setting the highest possible, non-zero priority in PMR. + * + * If SCR_EL3.FIQ is set, the priority gets shifted down in + * order for the CPU interface to set bit 7, and keep the + * actual priority in the non-secure range. In the process, it + * looses the least significant bit and the actual priority + * becomes 0x80. Reading it back returns 0, indicating that + * we're don't have access to Group0. + */ + gic_write_pmr(BIT(8 - gic_get_pribits())); + val = gic_read_pmr(); + + return val != 0; +} + static void __init gic_dist_init(void) { unsigned int i; @@ -540,7 +573,7 @@ static void gic_cpu_sys_reg_init(void) u64 mpidr = cpu_logical_map(cpu); u64 need_rss = MPIDR_RS(mpidr); bool group0; - u32 val, pribits; + u32 pribits; /* * Need to check that the SRE bit has actually been set. If @@ -552,25 +585,9 @@ static void gic_cpu_sys_reg_init(void) if (!gic_enable_sre()) pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); - pribits = gic_read_ctlr(); - pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; - pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; - pribits++; + pribits = gic_get_pribits(); - /* - * Let's find out if Group0 is under control of EL3 or not by - * setting the highest possible, non-zero priority in PMR. - * - * If SCR_EL3.FIQ is set, the priority gets shifted down in - * order for the CPU interface to set bit 7, and keep the - * actual priority in the non-secure range. In the process, it - * looses the least significant bit and the actual priority - * becomes 0x80. Reading it back returns 0, indicating that - * we're don't have access to Group0. - */ - write_gicreg(BIT(8 - pribits), ICC_PMR_EL1); - val = read_gicreg(ICC_PMR_EL1); - group0 = val != 0; + group0 = gic_has_group0(); /* Set priority mask register */ write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); -- 1.9.1
next prev parent reply other threads:[~2018-11-12 11:58 UTC|newest] Thread overview: 125+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-11-12 11:56 [PATCH v6 00/24] arm64: provide pseudo NMI with GICv3 Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-12 11:56 ` [PATCH v6 01/24] arm64: Remove unused daif related functions/macros Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-29 16:26 ` Mark Rutland 2018-11-29 16:26 ` Mark Rutland 2018-11-30 18:03 ` Catalin Marinas 2018-11-30 18:03 ` Catalin Marinas 2018-11-12 11:56 ` [PATCH v6 02/24] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-12 18:00 ` Suzuki K Poulose 2018-11-12 18:00 ` Suzuki K Poulose 2018-11-29 16:27 ` Mark Rutland 2018-11-29 16:27 ` Mark Rutland 2018-11-30 18:07 ` Catalin Marinas 2018-11-30 18:07 ` Catalin Marinas 2018-11-12 11:56 ` [PATCH v6 03/24] arm64: cpufeature: Add cpufeature for IRQ priority masking Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-12 18:02 ` Suzuki K Poulose 2018-11-12 18:02 ` Suzuki K Poulose 2018-11-29 17:12 ` Mark Rutland 2018-11-29 17:12 ` Mark Rutland 2018-12-03 10:33 ` Julien Thierry 2018-12-03 10:33 ` Julien Thierry 2018-11-30 18:07 ` Catalin Marinas 2018-11-30 18:07 ` Catalin Marinas 2018-11-12 11:56 ` [PATCH v6 04/24] arm/arm64: gic-v3: Add PMR and RPR accessors Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-29 16:32 ` Mark Rutland 2018-11-29 16:32 ` Mark Rutland 2018-11-30 18:07 ` Catalin Marinas 2018-11-30 18:07 ` Catalin Marinas 2018-11-12 11:56 ` [PATCH v6 05/24] irqchip/gic-v3: Switch to PMR masking before calling IRQ handler Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-29 18:12 ` Mark Rutland 2018-11-29 18:12 ` Mark Rutland 2018-11-30 9:18 ` Julien Thierry 2018-11-30 9:18 ` Julien Thierry 2018-12-04 16:21 ` Catalin Marinas 2018-12-04 16:21 ` Catalin Marinas 2018-11-12 11:56 ` [PATCH v6 06/24] arm64: ptrace: Provide definitions for PMR values Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-29 16:40 ` Mark Rutland 2018-11-29 16:40 ` Mark Rutland 2018-11-30 8:53 ` Julien Thierry 2018-11-30 8:53 ` Julien Thierry 2018-11-30 10:38 ` Daniel Thompson 2018-11-30 10:38 ` Daniel Thompson 2018-11-30 11:03 ` Julien Thierry 2018-11-30 11:03 ` Julien Thierry 2018-11-12 11:56 ` [PATCH v6 07/24] arm64: Make PMR part of task context Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-29 16:46 ` Mark Rutland 2018-11-29 16:46 ` Mark Rutland 2018-11-30 9:25 ` Julien Thierry 2018-11-30 9:25 ` Julien Thierry 2018-12-04 17:09 ` Catalin Marinas 2018-12-04 17:09 ` Catalin Marinas 2018-12-04 17:30 ` Julien Thierry 2018-12-04 17:30 ` Julien Thierry 2018-11-12 11:56 ` [PATCH v6 08/24] arm64: Unmask PMR before going idle Julien Thierry 2018-11-12 11:56 ` Julien Thierry 2018-11-29 17:44 ` Mark Rutland 2018-11-29 17:44 ` Mark Rutland 2018-11-30 10:55 ` Julien Thierry 2018-11-30 10:55 ` Julien Thierry 2018-11-30 13:37 ` Mark Rutland 2018-11-30 13:37 ` Mark Rutland 2018-12-03 10:38 ` Julien Thierry 2018-12-03 10:38 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 09/24] arm64: kvm: Unmask PMR before entering guest Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 10/24] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-12-04 17:36 ` Catalin Marinas 2018-12-04 17:36 ` Catalin Marinas 2018-12-05 16:55 ` Julien Thierry 2018-12-05 16:55 ` Julien Thierry 2018-12-05 18:26 ` Catalin Marinas 2018-12-05 18:26 ` Catalin Marinas 2018-12-06 9:50 ` Julien Thierry 2018-12-06 9:50 ` Julien Thierry 2018-12-10 14:39 ` Catalin Marinas 2018-12-10 14:39 ` Catalin Marinas 2018-11-12 11:57 ` [PATCH v6 11/24] arm64: daifflags: Include PMR in daifflags restore operations Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 12/24] arm64: alternative: Allow alternative status checking per cpufeature Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 13/24] arm64: alternative: Apply alternatives early in boot process Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` Julien Thierry [this message] 2018-11-12 11:57 ` [PATCH v6 14/24] irqchip/gic-v3: Factor group0 detection into functions Julien Thierry 2018-11-12 11:57 ` [PATCH v6 15/24] arm64: Switch to PMR masking when starting CPUs Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-12-04 17:51 ` Catalin Marinas 2018-12-04 17:51 ` Catalin Marinas 2018-12-04 18:11 ` Julien Thierry 2018-12-04 18:11 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 16/24] arm64: gic-v3: Implement arch support for priority masking Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 17/24] irqchip/gic-v3: Detect if GIC can support pseudo-NMIs Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 18/24] irqchip/gic-v3: Handle pseudo-NMIs Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 19/24] irqchip/gic: Add functions to access irq priorities Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 20/24] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 21/24] arm64: Handle serror in NMI context Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-12-04 18:09 ` Catalin Marinas 2018-12-04 18:09 ` Catalin Marinas 2018-12-05 13:02 ` James Morse 2018-12-05 13:02 ` James Morse 2018-11-12 11:57 ` [PATCH v6 22/24] arm64: Skip preemption when exiting an NMI Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 23/24] arm64: Skip irqflags tracing for NMI in IRQs disabled context Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 11:57 ` [PATCH v6 24/24] arm64: Enable the support of pseudo-NMIs Julien Thierry 2018-11-12 11:57 ` Julien Thierry 2018-11-12 12:00 ` [PATCH v6 00/24] arm64: provide pseudo NMI with GICv3 Julien Thierry 2018-11-12 12:00 ` Julien Thierry 2018-11-13 14:43 ` Julien Thierry 2018-11-13 14:43 ` Julien Thierry
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