From: no-reply@patchew.org To: kbastian@mail.uni-paderborn.de Cc: fam@euphon.net, sagark@eecs.berkeley.edu, palmer@sifive.com, qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Subject: Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Date: Thu, 31 Jan 2019 10:06:54 -0800 (PST) [thread overview] Message-ID: <154895801314.23946.2260020723929273125@ebba9967afc0> (raw) In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Type: series Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de === TEST SCRIPT BEGIN === #!/bin/bash git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' 8fff3fc6a2 target/riscv: Remaining rvc insn reuse 32 bit translators c563ab1ecb target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64 e2d25e9d55 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 aa0f8ada63 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns c57a581714 target/riscv: Convert @cs_2 insns to share translation functions 0a0a43441c target/riscv: Remove decode_RV32_64G() 30f9d142a0 target/riscv: Remove gen_system() 5710f6d871 target/riscv: Rename trans_arith to gen_arith 3f07a91951 target/riscv: Remove manual decoding of RV32/64M insn 0fc287193b target/riscv: Remove shift and slt insn manual decoding 236a600baf target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists a4fde90aab target/riscv: Move gen_arith_imm() decoding into trans_* functions efebe9125f target/riscv: Remove manual decoding from gen_store() 30bef8034b target/riscv: Remove manual decoding from gen_load() ea82022814 target/riscv: Remove manual decoding from gen_branch() 047f3d2ee4 target/riscv: Remove gen_jalr() 7ea527626d target/riscv: Convert quadrant 2 of RVXC insns to decodetree 27b3303efa target/riscv: Convert quadrant 1 of RVXC insns to decodetree 6a90487077 target/riscv: Convert quadrant 0 of RVXC insns to decodetree 2d8731dad1 target/riscv: Convert RV priv insns to decodetree b78a5409c2 target/riscv: Convert RV64D insns to decodetree 7181a4f946 target/riscv: Convert RV32D insns to decodetree dbb77cd4df target/riscv: Convert RV64F insns to decodetree 6ff19f1f62 target/riscv: Convert RV32F insns to decodetree 101b3708d7 target/riscv: Convert RV64A insns to decodetree 18db9d7cbe target/riscv: Convert RV32A insns to decodetree c2032943b6 target/riscv: Convert RVXM insns to decodetree 80b7b0b6e0 target/riscv: Convert RVXI csr insns to decodetree 35ca21d90a target/riscv: Convert RVXI fence insns to decodetree a974405bbb target/riscv: Convert RVXI arithmetic insns to decodetree 3ea0060942 target/riscv: Convert RV64I load/store insns to decodetree c1b9e8b927 target/riscv: Convert RV32I load/store insns to decodetree 109a6de64b target/riscv: Convert RVXI branch insns to decodetree 492967f3a6 target/riscv: Activate decodetree and implemnt LUI & AUIPC 7f257b74de target/riscv: Move CPURISCVState pointer to DisasContext === OUTPUT BEGIN === 1/35 Checking commit 7f257b74decd (target/riscv: Move CPURISCVState pointer to DisasContext) 2/35 Checking commit 492967f3a6ae (target/riscv: Activate decodetree and implemnt LUI & AUIPC) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #34: new file mode 100644 ERROR: externs should be avoided in .c files #125: FILE: target/riscv/translate.c:1687: +bool decode_insn32(DisasContext *ctx, uint32_t insn); total: 1 errors, 1 warnings, 125 lines checked Patch 2/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 3/35 Checking commit 109a6de64b62 (target/riscv: Convert RVXI branch insns to decodetree) 4/35 Checking commit c1b9e8b927b1 (target/riscv: Convert RV32I load/store insns to decodetree) 5/35 Checking commit 3ea006094257 (target/riscv: Convert RV64I load/store insns to decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #39: new file mode 100644 total: 0 errors, 1 warnings, 76 lines checked Patch 5/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 6/35 Checking commit a974405bbbae (target/riscv: Convert RVXI arithmetic insns to decodetree) 7/35 Checking commit 35ca21d90a96 (target/riscv: Convert RVXI fence insns to decodetree) 8/35 Checking commit 80b7b0b6e041 (target/riscv: Convert RVXI csr insns to decodetree) 9/35 Checking commit c2032943b671 (target/riscv: Convert RVXM insns to decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #48: new file mode 100644 total: 0 errors, 1 warnings, 145 lines checked Patch 9/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 10/35 Checking commit 18db9d7cbe2a (target/riscv: Convert RV32A insns to decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #54: new file mode 100644 total: 0 errors, 1 warnings, 188 lines checked Patch 10/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 11/35 Checking commit 101b3708d75e (target/riscv: Convert RV64A insns to decodetree) 12/35 Checking commit 6ff19f1f6274 (target/riscv: Convert RV32F insns to decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #78: new file mode 100644 total: 0 errors, 1 warnings, 397 lines checked Patch 12/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 13/35 Checking commit dbb77cd4df54 (target/riscv: Convert RV64F insns to decodetree) 14/35 Checking commit 7181a4f9463b (target/riscv: Convert RV32D insns to decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #51: new file mode 100644 total: 0 errors, 1 warnings, 353 lines checked Patch 14/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 15/35 Checking commit b78a5409c29d (target/riscv: Convert RV64D insns to decodetree) 16/35 Checking commit 2d8731dad167 (target/riscv: Convert RV priv insns to decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #41: new file mode 100644 total: 0 errors, 1 warnings, 214 lines checked Patch 16/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 17/35 Checking commit 6a9048707730 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #31: new file mode 100644 ERROR: externs should be avoided in .c files #246: FILE: target/riscv/translate.c:983: +bool decode_insn16(DisasContext *ctx, uint16_t insn); total: 1 errors, 1 warnings, 227 lines checked Patch 17/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 18/35 Checking commit 27b3303efa77 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree) 19/35 Checking commit 7ea527626d72 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree) 20/35 Checking commit 047f3d2ee462 (target/riscv: Remove gen_jalr()) 21/35 Checking commit ea820228141b (target/riscv: Remove manual decoding from gen_branch()) 22/35 Checking commit 30bef8034bd6 (target/riscv: Remove manual decoding from gen_load()) 23/35 Checking commit efebe9125f0c (target/riscv: Remove manual decoding from gen_store()) 24/35 Checking commit a4fde90aab86 (target/riscv: Move gen_arith_imm() decoding into trans_* functions) 25/35 Checking commit 236a600baf26 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists) 26/35 Checking commit 0fc287193b96 (target/riscv: Remove shift and slt insn manual decoding) 27/35 Checking commit 3f07a91951e7 (target/riscv: Remove manual decoding of RV32/64M insn) 28/35 Checking commit 5710f6d87168 (target/riscv: Rename trans_arith to gen_arith) 29/35 Checking commit 30f9d142a0d7 (target/riscv: Remove gen_system()) 30/35 Checking commit 0a0a43441c43 (target/riscv: Remove decode_RV32_64G()) 31/35 Checking commit c57a58171416 (target/riscv: Convert @cs_2 insns to share translation functions) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #42: new file mode 100644 ERROR: externs should be avoided in .c files #182: FILE: target/riscv/translate.c:497: +bool decode_insn16(DisasContext *ctx, uint16_t insn); total: 1 errors, 1 warnings, 164 lines checked Patch 31/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 32/35 Checking commit aa0f8ada6393 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns) 33/35 Checking commit e2d25e9d5539 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #28: new file mode 100644 total: 0 errors, 1 warnings, 287 lines checked Patch 33/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 34/35 Checking commit c563ab1ecbf8 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64) 35/35 Checking commit 8fff3fc6a21e (target/riscv: Remaining rvc insn reuse 32 bit translators) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to patchew-devel@redhat.com
WARNING: multiple messages have this Message-ID (diff)
From: no-reply@patchew.org To: kbastian@mail.uni-paderborn.de Cc: fam@euphon.net, sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de, qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Date: Thu, 31 Jan 2019 10:06:54 -0800 (PST) [thread overview] Message-ID: <154895801314.23946.2260020723929273125@ebba9967afc0> (raw) In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Type: series Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de === TEST SCRIPT BEGIN === #!/bin/bash git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' 8fff3fc6a2 target/riscv: Remaining rvc insn reuse 32 bit translators c563ab1ecb target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64 e2d25e9d55 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 aa0f8ada63 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns c57a581714 target/riscv: Convert @cs_2 insns to share translation functions 0a0a43441c target/riscv: Remove decode_RV32_64G() 30f9d142a0 target/riscv: Remove gen_system() 5710f6d871 target/riscv: Rename trans_arith to gen_arith 3f07a91951 target/riscv: Remove manual decoding of RV32/64M insn 0fc287193b target/riscv: Remove shift and slt insn manual decoding 236a600baf target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists a4fde90aab target/riscv: Move gen_arith_imm() decoding into trans_* functions efebe9125f target/riscv: Remove manual decoding from gen_store() 30bef8034b target/riscv: Remove manual decoding from gen_load() ea82022814 target/riscv: Remove manual decoding from gen_branch() 047f3d2ee4 target/riscv: Remove gen_jalr() 7ea527626d target/riscv: Convert quadrant 2 of RVXC insns to decodetree 27b3303efa target/riscv: Convert quadrant 1 of RVXC insns to decodetree 6a90487077 target/riscv: Convert quadrant 0 of RVXC insns to decodetree 2d8731dad1 target/riscv: Convert RV priv insns to decodetree b78a5409c2 target/riscv: Convert RV64D insns to decodetree 7181a4f946 target/riscv: Convert RV32D insns to decodetree dbb77cd4df target/riscv: Convert RV64F insns to decodetree 6ff19f1f62 target/riscv: Convert RV32F insns to decodetree 101b3708d7 target/riscv: Convert RV64A insns to decodetree 18db9d7cbe target/riscv: Convert RV32A insns to decodetree c2032943b6 target/riscv: Convert RVXM insns to decodetree 80b7b0b6e0 target/riscv: Convert RVXI csr insns to decodetree 35ca21d90a target/riscv: Convert RVXI fence insns to decodetree a974405bbb target/riscv: Convert RVXI arithmetic insns to decodetree 3ea0060942 target/riscv: Convert RV64I load/store insns to decodetree c1b9e8b927 target/riscv: Convert RV32I load/store insns to decodetree 109a6de64b target/riscv: Convert RVXI branch insns to decodetree 492967f3a6 target/riscv: Activate decodetree and implemnt LUI & AUIPC 7f257b74de target/riscv: Move CPURISCVState pointer to DisasContext === OUTPUT BEGIN === 1/35 Checking commit 7f257b74decd (target/riscv: Move CPURISCVState pointer to DisasContext) 2/35 Checking commit 492967f3a6ae (target/riscv: Activate decodetree and implemnt LUI & AUIPC) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #34: new file mode 100644 ERROR: externs should be avoided in .c files #125: FILE: target/riscv/translate.c:1687: +bool decode_insn32(DisasContext *ctx, uint32_t insn); total: 1 errors, 1 warnings, 125 lines checked Patch 2/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 3/35 Checking commit 109a6de64b62 (target/riscv: Convert RVXI branch insns to decodetree) 4/35 Checking commit c1b9e8b927b1 (target/riscv: Convert RV32I load/store insns to decodetree) 5/35 Checking commit 3ea006094257 (target/riscv: Convert RV64I load/store insns to decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #39: new file mode 100644 total: 0 errors, 1 warnings, 76 lines checked Patch 5/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 6/35 Checking commit a974405bbbae (target/riscv: Convert RVXI arithmetic insns to decodetree) 7/35 Checking commit 35ca21d90a96 (target/riscv: Convert RVXI fence insns to decodetree) 8/35 Checking commit 80b7b0b6e041 (target/riscv: Convert RVXI csr insns to decodetree) 9/35 Checking commit c2032943b671 (target/riscv: Convert RVXM insns to decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #48: new file mode 100644 total: 0 errors, 1 warnings, 145 lines checked Patch 9/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 10/35 Checking commit 18db9d7cbe2a (target/riscv: Convert RV32A insns to decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #54: new file mode 100644 total: 0 errors, 1 warnings, 188 lines checked Patch 10/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 11/35 Checking commit 101b3708d75e (target/riscv: Convert RV64A insns to decodetree) 12/35 Checking commit 6ff19f1f6274 (target/riscv: Convert RV32F insns to decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #78: new file mode 100644 total: 0 errors, 1 warnings, 397 lines checked Patch 12/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 13/35 Checking commit dbb77cd4df54 (target/riscv: Convert RV64F insns to decodetree) 14/35 Checking commit 7181a4f9463b (target/riscv: Convert RV32D insns to decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #51: new file mode 100644 total: 0 errors, 1 warnings, 353 lines checked Patch 14/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 15/35 Checking commit b78a5409c29d (target/riscv: Convert RV64D insns to decodetree) 16/35 Checking commit 2d8731dad167 (target/riscv: Convert RV priv insns to decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #41: new file mode 100644 total: 0 errors, 1 warnings, 214 lines checked Patch 16/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 17/35 Checking commit 6a9048707730 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #31: new file mode 100644 ERROR: externs should be avoided in .c files #246: FILE: target/riscv/translate.c:983: +bool decode_insn16(DisasContext *ctx, uint16_t insn); total: 1 errors, 1 warnings, 227 lines checked Patch 17/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 18/35 Checking commit 27b3303efa77 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree) 19/35 Checking commit 7ea527626d72 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree) 20/35 Checking commit 047f3d2ee462 (target/riscv: Remove gen_jalr()) 21/35 Checking commit ea820228141b (target/riscv: Remove manual decoding from gen_branch()) 22/35 Checking commit 30bef8034bd6 (target/riscv: Remove manual decoding from gen_load()) 23/35 Checking commit efebe9125f0c (target/riscv: Remove manual decoding from gen_store()) 24/35 Checking commit a4fde90aab86 (target/riscv: Move gen_arith_imm() decoding into trans_* functions) 25/35 Checking commit 236a600baf26 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists) 26/35 Checking commit 0fc287193b96 (target/riscv: Remove shift and slt insn manual decoding) 27/35 Checking commit 3f07a91951e7 (target/riscv: Remove manual decoding of RV32/64M insn) 28/35 Checking commit 5710f6d87168 (target/riscv: Rename trans_arith to gen_arith) 29/35 Checking commit 30f9d142a0d7 (target/riscv: Remove gen_system()) 30/35 Checking commit 0a0a43441c43 (target/riscv: Remove decode_RV32_64G()) 31/35 Checking commit c57a58171416 (target/riscv: Convert @cs_2 insns to share translation functions) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #42: new file mode 100644 ERROR: externs should be avoided in .c files #182: FILE: target/riscv/translate.c:497: +bool decode_insn16(DisasContext *ctx, uint16_t insn); total: 1 errors, 1 warnings, 164 lines checked Patch 31/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 32/35 Checking commit aa0f8ada6393 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns) 33/35 Checking commit e2d25e9d5539 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #28: new file mode 100644 total: 0 errors, 1 warnings, 287 lines checked Patch 33/35 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 34/35 Checking commit c563ab1ecbf8 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64) 35/35 Checking commit 8fff3fc6a21e (target/riscv: Remaining rvc insn reuse 32 bit translators) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to patchew-devel@redhat.com
next prev parent reply other threads:[~2019-01-31 18:12 UTC|newest] Thread overview: 164+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-01-22 9:28 [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 23:03 ` [Qemu-devel] " Alistair Francis 2019-01-22 23:03 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 23:38 ` [Qemu-devel] " Alistair Francis 2019-01-22 23:38 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 05/35] target/riscv: Convert RV64I " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 09/35] target/riscv: Convert RVXM " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 10/35] target/riscv: Convert RV32A " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 23:43 ` [Qemu-devel] " Alistair Francis 2019-01-22 23:43 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 11/35] target/riscv: Convert RV64A " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 12/35] target/riscv: Convert RV32F " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 0:00 ` [Qemu-devel] " Alistair Francis 2019-01-23 0:00 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 0:08 ` [Qemu-devel] " Alistair Francis 2019-01-23 0:08 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 0:08 ` [Qemu-devel] " Alistair Francis 2019-01-23 0:08 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 15/35] target/riscv: Convert RV64D " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 0:10 ` [Qemu-devel] " Alistair Francis 2019-01-23 0:10 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 16/35] target/riscv: Convert RV priv " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 1:00 ` [Qemu-devel] " Alistair Francis 2019-01-23 1:00 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 21:32 ` [Qemu-devel] " Richard Henderson 2019-01-22 21:32 ` [Qemu-riscv] " Richard Henderson 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 21:36 ` [Qemu-devel] " Richard Henderson 2019-01-22 21:36 ` [Qemu-riscv] " Richard Henderson 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 29/35] target/riscv: Remove gen_system() Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 21:38 ` [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Richard Henderson 2019-01-22 21:38 ` [Qemu-riscv] " Richard Henderson 2019-01-23 9:15 ` [Qemu-devel] " Bastian Koppelmann 2019-01-23 9:15 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 21:22 ` Alistair Francis 2019-01-23 21:22 ` [Qemu-riscv] " Alistair Francis 2019-01-25 23:54 ` Palmer Dabbelt 2019-01-25 23:54 ` [Qemu-riscv] " Palmer Dabbelt 2019-01-26 8:51 ` [Qemu-devel] " Bastian Koppelmann 2019-01-26 8:51 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-29 19:22 ` Palmer Dabbelt 2019-01-29 19:22 ` [Qemu-riscv] " Palmer Dabbelt 2019-01-29 21:13 ` Alistair Francis 2019-01-29 21:13 ` [Qemu-riscv] " Alistair Francis 2019-01-30 9:08 ` Bastian Koppelmann 2019-01-30 9:08 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-30 18:47 ` Palmer Dabbelt 2019-01-30 18:47 ` [Qemu-riscv] " Palmer Dabbelt 2019-01-31 18:06 ` no-reply [this message] 2019-01-31 18:06 ` no-reply 2019-01-31 18:48 ` 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