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From: no-reply@patchew.org
To: kbastian@mail.uni-paderborn.de
Cc: fam@euphon.net, sagark@eecs.berkeley.edu, palmer@sifive.com,
	qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de,
	richard.henderson@linaro.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Date: Thu, 31 Jan 2019 13:38:43 -0800 (PST)	[thread overview]
Message-ID: <154897072252.23946.17941898366280095157@ebba9967afc0> (raw)
In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de>

Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
291fb33 target/riscv: Remaining rvc insn reuse 32 bit translators
f234c9a target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
16680b1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8c27631 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
d2bb2de target/riscv: Convert @cs_2 insns to share translation functions
24f0433 target/riscv: Remove decode_RV32_64G()
8e284b2 target/riscv: Remove gen_system()
7fdd5f1 target/riscv: Rename trans_arith to gen_arith
696cd56 target/riscv: Remove manual decoding of RV32/64M insn
81c0dbf target/riscv: Remove shift and slt insn manual decoding
69947ae target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
b162444 target/riscv: Move gen_arith_imm() decoding into trans_* functions
9d189f8 target/riscv: Remove manual decoding from gen_store()
b9e24ac target/riscv: Remove manual decoding from gen_load()
543c238 target/riscv: Remove manual decoding from gen_branch()
1ecefc4 target/riscv: Remove gen_jalr()
4251a01 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
3a0627a target/riscv: Convert quadrant 1 of RVXC insns to decodetree
135f107 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8833d53 target/riscv: Convert RV priv insns to decodetree
28b613a target/riscv: Convert RV64D insns to decodetree
02b797e target/riscv: Convert RV32D insns to decodetree
27cc348 target/riscv: Convert RV64F insns to decodetree
b0857e0 target/riscv: Convert RV32F insns to decodetree
b578a96 target/riscv: Convert RV64A insns to decodetree
26ca8f5 target/riscv: Convert RV32A insns to decodetree
0ef195f target/riscv: Convert RVXM insns to decodetree
d22f711 target/riscv: Convert RVXI csr insns to decodetree
34de7f7 target/riscv: Convert RVXI fence insns to decodetree
da5403e target/riscv: Convert RVXI arithmetic insns to decodetree
f8d0548 target/riscv: Convert RV64I load/store insns to decodetree
7f40538 target/riscv: Convert RV32I load/store insns to decodetree
d5b10e4 target/riscv: Convert RVXI branch insns to decodetree
26e2990 target/riscv: Activate decodetree and implemnt LUI & AUIPC
2d78010 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 2d78010a7d7b (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 26e2990adad9 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit d5b10e450153 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 7f40538802f9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit f8d0548e2da9 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit da5403e39dfc (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 34de7f750472 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit d22f711d7ddb (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit 0ef195feef49 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 26ca8f56316d (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54: 
new file mode 100644

total: 0 errors, 1 warnings, 188 lines checked

Patch 10/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit b578a9684221 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit b0857e0983f9 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78: 
new file mode 100644

total: 0 errors, 1 warnings, 397 lines checked

Patch 12/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 27cc348b3b41 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 02b797edd5e8 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51: 
new file mode 100644

total: 0 errors, 1 warnings, 353 lines checked

Patch 14/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 28b613a9323b (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 8833d537b599 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41: 
new file mode 100644

total: 0 errors, 1 warnings, 214 lines checked

Patch 16/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 135f10759377 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31: 
new file mode 100644

ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 227 lines checked

Patch 17/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

18/35 Checking commit 3a0627ae7139 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 4251a010bd40 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 1ecefc428332 (target/riscv: Remove gen_jalr())
21/35 Checking commit 543c238dc767 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit b9e24ac0d566 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 9d189f830c77 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit b162444c1849 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 69947ae04778 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 81c0dbfad9c7 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 696cd5696710 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 7fdd5f104c9d (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 8e284b2972e0 (target/riscv: Remove gen_system())
30/35 Checking commit 24f04339fe94 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit d2bb2de93587 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42: 
new file mode 100644

ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 164 lines checked

Patch 31/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

32/35 Checking commit 8c27631fd427 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 16680b13d8ee (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

total: 0 errors, 1 warnings, 287 lines checked

Patch 33/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit f234c9a30159 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 291fb3378aab (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

WARNING: multiple messages have this Message-ID (diff)
From: no-reply@patchew.org
To: kbastian@mail.uni-paderborn.de
Cc: fam@euphon.net, sagark@eecs.berkeley.edu, palmer@sifive.com,
	kbastian@mail.uni-paderborn.de, qemu-riscv@nongnu.org,
	peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org,
	qemu-devel@nongnu.org
Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Date: Thu, 31 Jan 2019 13:38:43 -0800 (PST)	[thread overview]
Message-ID: <154897072252.23946.17941898366280095157@ebba9967afc0> (raw)
In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de>

Patchew URL: https://patchew.org/QEMU/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de -> patchew/20190122092909.5341-1-kbastian@mail.uni-paderborn.de
Switched to a new branch 'test'
291fb33 target/riscv: Remaining rvc insn reuse 32 bit translators
f234c9a target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
16680b1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8c27631 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
d2bb2de target/riscv: Convert @cs_2 insns to share translation functions
24f0433 target/riscv: Remove decode_RV32_64G()
8e284b2 target/riscv: Remove gen_system()
7fdd5f1 target/riscv: Rename trans_arith to gen_arith
696cd56 target/riscv: Remove manual decoding of RV32/64M insn
81c0dbf target/riscv: Remove shift and slt insn manual decoding
69947ae target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
b162444 target/riscv: Move gen_arith_imm() decoding into trans_* functions
9d189f8 target/riscv: Remove manual decoding from gen_store()
b9e24ac target/riscv: Remove manual decoding from gen_load()
543c238 target/riscv: Remove manual decoding from gen_branch()
1ecefc4 target/riscv: Remove gen_jalr()
4251a01 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
3a0627a target/riscv: Convert quadrant 1 of RVXC insns to decodetree
135f107 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8833d53 target/riscv: Convert RV priv insns to decodetree
28b613a target/riscv: Convert RV64D insns to decodetree
02b797e target/riscv: Convert RV32D insns to decodetree
27cc348 target/riscv: Convert RV64F insns to decodetree
b0857e0 target/riscv: Convert RV32F insns to decodetree
b578a96 target/riscv: Convert RV64A insns to decodetree
26ca8f5 target/riscv: Convert RV32A insns to decodetree
0ef195f target/riscv: Convert RVXM insns to decodetree
d22f711 target/riscv: Convert RVXI csr insns to decodetree
34de7f7 target/riscv: Convert RVXI fence insns to decodetree
da5403e target/riscv: Convert RVXI arithmetic insns to decodetree
f8d0548 target/riscv: Convert RV64I load/store insns to decodetree
7f40538 target/riscv: Convert RV32I load/store insns to decodetree
d5b10e4 target/riscv: Convert RVXI branch insns to decodetree
26e2990 target/riscv: Activate decodetree and implemnt LUI & AUIPC
2d78010 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 2d78010a7d7b (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 26e2990adad9 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit d5b10e450153 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 7f40538802f9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit f8d0548e2da9 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit da5403e39dfc (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 34de7f750472 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit d22f711d7ddb (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit 0ef195feef49 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 26ca8f56316d (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54: 
new file mode 100644

total: 0 errors, 1 warnings, 188 lines checked

Patch 10/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit b578a9684221 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit b0857e0983f9 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78: 
new file mode 100644

total: 0 errors, 1 warnings, 397 lines checked

Patch 12/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 27cc348b3b41 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 02b797edd5e8 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51: 
new file mode 100644

total: 0 errors, 1 warnings, 353 lines checked

Patch 14/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 28b613a9323b (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 8833d537b599 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41: 
new file mode 100644

total: 0 errors, 1 warnings, 214 lines checked

Patch 16/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 135f10759377 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31: 
new file mode 100644

ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 227 lines checked

Patch 17/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

18/35 Checking commit 3a0627ae7139 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 4251a010bd40 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 1ecefc428332 (target/riscv: Remove gen_jalr())
21/35 Checking commit 543c238dc767 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit b9e24ac0d566 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit 9d189f830c77 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit b162444c1849 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 69947ae04778 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 81c0dbfad9c7 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 696cd5696710 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit 7fdd5f104c9d (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 8e284b2972e0 (target/riscv: Remove gen_system())
30/35 Checking commit 24f04339fe94 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit d2bb2de93587 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42: 
new file mode 100644

ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 164 lines checked

Patch 31/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

32/35 Checking commit 8c27631fd427 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 16680b13d8ee (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

total: 0 errors, 1 warnings, 287 lines checked

Patch 33/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit f234c9a30159 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 291fb3378aab (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190122092909.5341-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

  parent reply	other threads:[~2019-01-31 21:39 UTC|newest]

Thread overview: 164+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-22  9:28 [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 23:03   ` [Qemu-devel] " Alistair Francis
2019-01-22 23:03     ` [Qemu-riscv] " Alistair Francis
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 23:38   ` [Qemu-devel] " Alistair Francis
2019-01-22 23:38     ` [Qemu-riscv] " Alistair Francis
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 23:43   ` [Qemu-devel] " Alistair Francis
2019-01-22 23:43     ` [Qemu-riscv] " Alistair Francis
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  0:00   ` [Qemu-devel] " Alistair Francis
2019-01-23  0:00     ` [Qemu-riscv] " Alistair Francis
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  0:08   ` [Qemu-devel] " Alistair Francis
2019-01-23  0:08     ` [Qemu-riscv] " Alistair Francis
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  0:08   ` [Qemu-devel] " Alistair Francis
2019-01-23  0:08     ` [Qemu-riscv] " Alistair Francis
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  0:10   ` [Qemu-devel] " Alistair Francis
2019-01-23  0:10     ` [Qemu-riscv] " Alistair Francis
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23  1:00   ` [Qemu-devel] " Alistair Francis
2019-01-23  1:00     ` [Qemu-riscv] " Alistair Francis
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 21:32   ` [Qemu-devel] " Richard Henderson
2019-01-22 21:32     ` [Qemu-riscv] " Richard Henderson
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 21:36   ` [Qemu-devel] " Richard Henderson
2019-01-22 21:36     ` [Qemu-riscv] " Richard Henderson
2019-01-22  9:28 ` [Qemu-devel] [PATCH v5 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-01-22  9:28   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:29 ` [Qemu-devel] [PATCH v5 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2019-01-22  9:29   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:29 ` [Qemu-devel] [PATCH v5 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-01-22  9:29   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:29 ` [Qemu-devel] [PATCH v5 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-01-22  9:29   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:29 ` [Qemu-devel] [PATCH v5 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2019-01-22  9:29   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:29 ` [Qemu-devel] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-01-22  9:29   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:29 ` [Qemu-devel] [PATCH v5 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2019-01-22  9:29   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:29 ` [Qemu-devel] [PATCH v5 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-01-22  9:29   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:29 ` [Qemu-devel] [PATCH v5 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-01-22  9:29   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:29 ` [Qemu-devel] [PATCH v5 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-01-22  9:29   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22  9:29 ` [Qemu-devel] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-01-22  9:29   ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 21:38 ` [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Richard Henderson
2019-01-22 21:38   ` [Qemu-riscv] " Richard Henderson
2019-01-23  9:15   ` [Qemu-devel] " Bastian Koppelmann
2019-01-23  9:15     ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 21:22     ` Alistair Francis
2019-01-23 21:22       ` [Qemu-riscv] " Alistair Francis
2019-01-25 23:54   ` Palmer Dabbelt
2019-01-25 23:54     ` [Qemu-riscv] " Palmer Dabbelt
2019-01-26  8:51     ` [Qemu-devel] " Bastian Koppelmann
2019-01-26  8:51       ` [Qemu-riscv] " Bastian Koppelmann
2019-01-29 19:22       ` Palmer Dabbelt
2019-01-29 19:22         ` [Qemu-riscv] " Palmer Dabbelt
2019-01-29 21:13         ` Alistair Francis
2019-01-29 21:13           ` [Qemu-riscv] " Alistair Francis
2019-01-30  9:08         ` Bastian Koppelmann
2019-01-30  9:08           ` [Qemu-riscv] " Bastian Koppelmann
2019-01-30 18:47           ` Palmer Dabbelt
2019-01-30 18:47             ` [Qemu-riscv] " Palmer Dabbelt
2019-01-31 18:06 ` no-reply
2019-01-31 18:06   ` [Qemu-riscv] " no-reply
2019-01-31 18:48 ` no-reply
2019-01-31 18:48   ` [Qemu-riscv] " no-reply
2019-01-31 18:48 ` no-reply
2019-01-31 18:48   ` [Qemu-riscv] " no-reply
2019-01-31 18:51 ` no-reply
2019-01-31 18:51   ` [Qemu-riscv] " no-reply
2019-01-31 19:00 ` no-reply
2019-01-31 19:00   ` [Qemu-riscv] " no-reply
2019-01-31 19:08 ` no-reply
2019-01-31 19:08   ` [Qemu-riscv] " no-reply
2019-01-31 19:12 ` no-reply
2019-01-31 19:12   ` [Qemu-riscv] " no-reply
2019-01-31 21:00 ` no-reply
2019-01-31 21:00   ` [Qemu-riscv] " no-reply
2019-01-31 21:01 ` no-reply
2019-01-31 21:01   ` [Qemu-riscv] " no-reply
2019-01-31 21:04 ` no-reply
2019-01-31 21:04   ` [Qemu-riscv] " no-reply
2019-01-31 21:09 ` no-reply
2019-01-31 21:09   ` [Qemu-riscv] " no-reply
2019-01-31 21:10 ` no-reply
2019-01-31 21:10   ` [Qemu-riscv] " no-reply
2019-01-31 21:11 ` no-reply
2019-01-31 21:11   ` [Qemu-riscv] " no-reply
2019-01-31 21:12 ` no-reply
2019-01-31 21:12   ` [Qemu-riscv] " no-reply
2019-01-31 21:15 ` no-reply
2019-01-31 21:15   ` [Qemu-riscv] " no-reply
2019-01-31 21:15 ` no-reply
2019-01-31 21:15   ` [Qemu-riscv] " no-reply
2019-01-31 21:18 ` no-reply
2019-01-31 21:18   ` [Qemu-riscv] " no-reply
2019-01-31 21:19 ` no-reply
2019-01-31 21:19   ` [Qemu-riscv] " no-reply
2019-01-31 21:20 ` no-reply
2019-01-31 21:20   ` [Qemu-riscv] " no-reply
2019-01-31 21:22 ` no-reply
2019-01-31 21:22   ` [Qemu-riscv] " no-reply
2019-01-31 21:23 ` no-reply
2019-01-31 21:23   ` [Qemu-riscv] " no-reply
2019-01-31 21:25 ` no-reply
2019-01-31 21:25   ` [Qemu-riscv] " no-reply
2019-01-31 21:26 ` no-reply
2019-01-31 21:26   ` [Qemu-riscv] " no-reply
2019-01-31 21:27 ` no-reply
2019-01-31 21:27   ` [Qemu-riscv] " no-reply
2019-01-31 21:37 ` no-reply
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2019-01-31 21:38 ` no-reply [this message]
2019-01-31 21:38   ` no-reply
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