From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: sagark@eecs.berkeley.edu, palmer@sifive.com,
kbastian@mail.uni-paderborn.de
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>
Subject: [Qemu-devel] [PATCH v5 20/35] target/riscv: Remove gen_jalr()
Date: Tue, 22 Jan 2019 10:28:54 +0100 [thread overview]
Message-ID: <20190122092909.5341-21-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de>
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 28 +++++++++++++++++-
target/riscv/translate.c | 38 -------------------------
2 files changed, 27 insertions(+), 39 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index b0f35cef14..3b3aff4803 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -42,7 +42,33 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
{
- gen_jalr(ctx->env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+ /* no chaining with JALR */
+ TCGLabel *misaligned = NULL;
+ TCGv t0 = tcg_temp_new();
+
+
+ gen_get_gpr(cpu_pc, a->rs1);
+ tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+ tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+
+ if (!riscv_has_ext(ctx->env, RVC)) {
+ misaligned = gen_new_label();
+ tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+ }
+
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
+ }
+ tcg_gen_lookup_and_goto_ptr();
+
+ if (misaligned) {
+ gen_set_label(misaligned);
+ gen_exception_inst_addr_mis(ctx);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(t0);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 53febc60b0..1f59b02c84 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,44 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, target_long imm)
-{
- /* no chaining with JALR */
- TCGLabel *misaligned = NULL;
- TCGv t0 = tcg_temp_new();
-
- switch (opc) {
- case OPC_RISC_JALR:
- gen_get_gpr(cpu_pc, rs1);
- tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
- tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
-
- if (!riscv_has_ext(env, RVC)) {
- misaligned = gen_new_label();
- tcg_gen_andi_tl(t0, cpu_pc, 0x2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
- }
-
- if (rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
- }
- tcg_gen_lookup_and_goto_ptr();
-
- if (misaligned) {
- gen_set_label(misaligned);
- gen_exception_inst_addr_mis(ctx);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
-
- default:
- gen_exception_illegal(ctx);
- break;
- }
- tcg_temp_free(t0);
-}
-
static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rs1, int rs2, target_long bimm)
{
--
2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: sagark@eecs.berkeley.edu, palmer@sifive.com,
kbastian@mail.uni-paderborn.de
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>
Subject: [Qemu-riscv] [PATCH v5 20/35] target/riscv: Remove gen_jalr()
Date: Tue, 22 Jan 2019 10:28:54 +0100 [thread overview]
Message-ID: <20190122092909.5341-21-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de>
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 28 +++++++++++++++++-
target/riscv/translate.c | 38 -------------------------
2 files changed, 27 insertions(+), 39 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index b0f35cef14..3b3aff4803 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -42,7 +42,33 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
{
- gen_jalr(ctx->env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+ /* no chaining with JALR */
+ TCGLabel *misaligned = NULL;
+ TCGv t0 = tcg_temp_new();
+
+
+ gen_get_gpr(cpu_pc, a->rs1);
+ tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+ tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+
+ if (!riscv_has_ext(ctx->env, RVC)) {
+ misaligned = gen_new_label();
+ tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+ }
+
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
+ }
+ tcg_gen_lookup_and_goto_ptr();
+
+ if (misaligned) {
+ gen_set_label(misaligned);
+ gen_exception_inst_addr_mis(ctx);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(t0);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 53febc60b0..1f59b02c84 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -489,44 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, target_long imm)
-{
- /* no chaining with JALR */
- TCGLabel *misaligned = NULL;
- TCGv t0 = tcg_temp_new();
-
- switch (opc) {
- case OPC_RISC_JALR:
- gen_get_gpr(cpu_pc, rs1);
- tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
- tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
-
- if (!riscv_has_ext(env, RVC)) {
- misaligned = gen_new_label();
- tcg_gen_andi_tl(t0, cpu_pc, 0x2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
- }
-
- if (rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
- }
- tcg_gen_lookup_and_goto_ptr();
-
- if (misaligned) {
- gen_set_label(misaligned);
- gen_exception_inst_addr_mis(ctx);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
-
- default:
- gen_exception_illegal(ctx);
- break;
- }
- tcg_temp_free(t0);
-}
-
static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rs1, int rs2, target_long bimm)
{
--
2.20.1
next prev parent reply other threads:[~2019-01-22 9:38 UTC|newest]
Thread overview: 164+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-22 9:28 [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 23:03 ` [Qemu-devel] " Alistair Francis
2019-01-22 23:03 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 23:38 ` [Qemu-devel] " Alistair Francis
2019-01-22 23:38 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 23:43 ` [Qemu-devel] " Alistair Francis
2019-01-22 23:43 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 0:00 ` [Qemu-devel] " Alistair Francis
2019-01-23 0:00 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 0:08 ` [Qemu-devel] " Alistair Francis
2019-01-23 0:08 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 0:08 ` [Qemu-devel] " Alistair Francis
2019-01-23 0:08 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 0:10 ` [Qemu-devel] " Alistair Francis
2019-01-23 0:10 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 1:00 ` [Qemu-devel] " Alistair Francis
2019-01-23 1:00 ` [Qemu-riscv] " Alistair Francis
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 21:32 ` [Qemu-devel] " Richard Henderson
2019-01-22 21:32 ` [Qemu-riscv] " Richard Henderson
2019-01-22 9:28 ` Bastian Koppelmann [this message]
2019-01-22 9:28 ` [Qemu-riscv] [PATCH v5 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 21:36 ` [Qemu-devel] " Richard Henderson
2019-01-22 21:36 ` [Qemu-riscv] " Richard Henderson
2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-22 21:38 ` [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Richard Henderson
2019-01-22 21:38 ` [Qemu-riscv] " Richard Henderson
2019-01-23 9:15 ` [Qemu-devel] " Bastian Koppelmann
2019-01-23 9:15 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-23 21:22 ` Alistair Francis
2019-01-23 21:22 ` [Qemu-riscv] " Alistair Francis
2019-01-25 23:54 ` Palmer Dabbelt
2019-01-25 23:54 ` [Qemu-riscv] " Palmer Dabbelt
2019-01-26 8:51 ` [Qemu-devel] " Bastian Koppelmann
2019-01-26 8:51 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-29 19:22 ` Palmer Dabbelt
2019-01-29 19:22 ` [Qemu-riscv] " Palmer Dabbelt
2019-01-29 21:13 ` Alistair Francis
2019-01-29 21:13 ` [Qemu-riscv] " Alistair Francis
2019-01-30 9:08 ` Bastian Koppelmann
2019-01-30 9:08 ` [Qemu-riscv] " Bastian Koppelmann
2019-01-30 18:47 ` Palmer Dabbelt
2019-01-30 18:47 ` [Qemu-riscv] " Palmer Dabbelt
2019-01-31 18:06 ` no-reply
2019-01-31 18:06 ` [Qemu-riscv] " no-reply
2019-01-31 18:48 ` no-reply
2019-01-31 18:48 ` [Qemu-riscv] " no-reply
2019-01-31 18:48 ` no-reply
2019-01-31 18:48 ` [Qemu-riscv] " no-reply
2019-01-31 18:51 ` no-reply
2019-01-31 18:51 ` [Qemu-riscv] " no-reply
2019-01-31 19:00 ` no-reply
2019-01-31 19:00 ` [Qemu-riscv] " no-reply
2019-01-31 19:08 ` no-reply
2019-01-31 19:08 ` [Qemu-riscv] " no-reply
2019-01-31 19:12 ` no-reply
2019-01-31 19:12 ` [Qemu-riscv] " no-reply
2019-01-31 21:00 ` no-reply
2019-01-31 21:00 ` [Qemu-riscv] " no-reply
2019-01-31 21:01 ` no-reply
2019-01-31 21:01 ` [Qemu-riscv] " no-reply
2019-01-31 21:04 ` no-reply
2019-01-31 21:04 ` [Qemu-riscv] " no-reply
2019-01-31 21:09 ` no-reply
2019-01-31 21:09 ` [Qemu-riscv] " no-reply
2019-01-31 21:10 ` no-reply
2019-01-31 21:10 ` [Qemu-riscv] " no-reply
2019-01-31 21:11 ` no-reply
2019-01-31 21:11 ` [Qemu-riscv] " no-reply
2019-01-31 21:12 ` no-reply
2019-01-31 21:12 ` [Qemu-riscv] " no-reply
2019-01-31 21:15 ` no-reply
2019-01-31 21:15 ` [Qemu-riscv] " no-reply
2019-01-31 21:15 ` no-reply
2019-01-31 21:15 ` [Qemu-riscv] " no-reply
2019-01-31 21:18 ` no-reply
2019-01-31 21:18 ` [Qemu-riscv] " no-reply
2019-01-31 21:19 ` no-reply
2019-01-31 21:19 ` [Qemu-riscv] " no-reply
2019-01-31 21:20 ` no-reply
2019-01-31 21:20 ` [Qemu-riscv] " no-reply
2019-01-31 21:22 ` no-reply
2019-01-31 21:22 ` [Qemu-riscv] " no-reply
2019-01-31 21:23 ` no-reply
2019-01-31 21:23 ` [Qemu-riscv] " no-reply
2019-01-31 21:25 ` no-reply
2019-01-31 21:25 ` [Qemu-riscv] " no-reply
2019-01-31 21:26 ` no-reply
2019-01-31 21:26 ` [Qemu-riscv] " no-reply
2019-01-31 21:27 ` no-reply
2019-01-31 21:27 ` [Qemu-riscv] " no-reply
2019-01-31 21:37 ` no-reply
2019-01-31 21:37 ` [Qemu-riscv] " no-reply
2019-01-31 21:38 ` no-reply
2019-01-31 21:38 ` [Qemu-riscv] " no-reply
2019-01-31 21:41 ` no-reply
2019-01-31 21:41 ` [Qemu-riscv] " no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190122092909.5341-21-kbastian@mail.uni-paderborn.de \
--to=kbastian@mail.uni-paderborn.de \
--cc=alistair.francis@wdc.com \
--cc=palmer@sifive.com \
--cc=peer.adelt@hni.uni-paderborn.de \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=sagark@eecs.berkeley.edu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.