From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree Date: Tue, 22 Jan 2019 10:28:51 +0100 [thread overview] Message-ID: <20190122092909.5341-18-kbastian@mail.uni-paderborn.de> (raw) In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de> --- target/riscv/Makefile.objs | 9 ++- target/riscv/insn16.decode | 55 ++++++++++++++++++ target/riscv/insn_trans/trans_rvc.inc.c | 75 +++++++++++++++++++++++++ target/riscv/translate.c | 53 ++++++----------- 4 files changed, 154 insertions(+), 38 deletions(-) create mode 100644 target/riscv/insn16.decode create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index 05087a91bb..9c6c109327 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -10,4 +10,11 @@ target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \ "GEN", $(TARGET_DIR)$@) -target/riscv/translate.o: target/riscv/decode_insn32.inc.c +target/riscv/decode_insn16.inc.c: \ + $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE) + $(call quiet-command, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \ + "GEN", $(TARGET_DIR)$@) + +target/riscv/translate.o: target/riscv/decode_insn32.inc.c \ + target/riscv/decode_insn16.inc.c diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode new file mode 100644 index 0000000000..558c0c41f0 --- /dev/null +++ b/target/riscv/insn16.decode @@ -0,0 +1,55 @@ +# +# RISC-V translation routines for the RVXI Base Integer Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see <http://www.gnu.org/licenses/>. + +# Fields: +%rd 7:5 +%rs1_3 7:3 !function=ex_rvc_register +%rs2_3 2:3 !function=ex_rvc_register + +# Immediates: +%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2 +%uimm_cl_d 5:2 10:3 !function=ex_shift_3 +%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2 + + +# Argument sets: +&cl rs1 rd +&cl_dw uimm rs1 rd +&ciw nzuimm rd +&cs rs1 rs2 +&cs_dw uimm rs1 rs2 + + +# Formats 16: +@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3 +@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 +@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 +@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3 +@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3 +@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 +@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 + + +# *** RV64C Standard Extension (Quadrant 0) *** +c_addi4spn 000 ........ ... 00 @ciw +c_fld 001 ... ... .. ... 00 @cl_d +c_lw 010 ... ... .. ... 00 @cl_w +c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually +c_fsd 101 ... ... .. ... 00 @cs_d +c_sw 110 ... ... .. ... 00 @cs_w +c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c new file mode 100644 index 0000000000..93ec8aa30b --- /dev/null +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -0,0 +1,75 @@ +/* + * RISC-V translation routines for the RVC Compressed Instruction Set. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a) +{ + if (a->nzuimm == 0) { + /* Reserved in ISA */ + return false; + } + arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm }; + return trans_addi(ctx, &arg); +} + +static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a) +{ + arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm }; + return trans_fld(ctx, &arg); +} + +static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a) +{ + arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm }; + return trans_lw(ctx, &arg); +} + +static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) +{ +#ifdef TARGET_RISCV32 + /* C.FLW ( RV32FC-only ) */ + return false; +#else + /* C.LD ( RV64C/RV128C-only ) */ + return false; +#endif +} + +static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a) +{ + arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm }; + return trans_fsd(ctx, &arg); +} + +static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a) +{ + arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm }; + return trans_sw(ctx, &arg); +} + +static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) +{ +#ifdef TARGET_RISCV32 + /* C.FSW ( RV32FC-only ) */ + return false; +#else + /* C.SD ( RV64C/RV128C-only ) */ + return false; +#endif +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ff15e0f7ed..1ee13c1907 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -720,27 +720,6 @@ static void decode_RV32_64C0(DisasContext *ctx) uint8_t rs1s = GET_C_RS1S(ctx->opcode); switch (funct3) { - case 0: - /* illegal */ - if (ctx->opcode == 0) { - gen_exception_illegal(ctx); - } else { - /* C.ADDI4SPN -> addi rd', x2, zimm[9:2]*/ - gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs2, 2, - GET_C_ADDI4SPN_IMM(ctx->opcode)); - } - break; - case 1: - /* C.FLD -> fld rd', offset[7:3](rs1')*/ - gen_fp_load(ctx, OPC_RISC_FLD, rd_rs2, rs1s, - GET_C_LD_IMM(ctx->opcode)); - /* C.LQ(RV128) */ - break; - case 2: - /* C.LW -> lw rd', offset[6:2](rs1') */ - gen_load(ctx, OPC_RISC_LW, rd_rs2, rs1s, - GET_C_LW_IMM(ctx->opcode)); - break; case 3: #if defined(TARGET_RISCV64) /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ @@ -752,21 +731,6 @@ static void decode_RV32_64C0(DisasContext *ctx) GET_C_LW_IMM(ctx->opcode)); #endif break; - case 4: - /* reserved */ - gen_exception_illegal(ctx); - break; - case 5: - /* C.FSD(RV32/64) -> fsd rs2', offset[7:3](rs1') */ - gen_fp_store(ctx, OPC_RISC_FSD, rs1s, rd_rs2, - GET_C_LD_IMM(ctx->opcode)); - /* C.SQ (RV128) */ - break; - case 6: - /* C.SW -> sw rs2', offset[6:2](rs1')*/ - gen_store(ctx, OPC_RISC_SW, rs1s, rd_rs2, - GET_C_LW_IMM(ctx->opcode)); - break; case 7: #if defined(TARGET_RISCV64) /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ @@ -996,8 +960,15 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx) return imm << amount; \ } EX_SH(1) +EX_SH(2) +EX_SH(3) EX_SH(12) +static int ex_rvc_register(int reg) +{ + return 8 + reg; +} + bool decode_insn32(DisasContext *ctx, uint32_t insn); /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" @@ -1009,6 +980,11 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn); #include "insn_trans/trans_rvd.inc.c" #include "insn_trans/trans_privileged.inc.c" +bool decode_insn16(DisasContext *ctx, uint16_t insn); +/* auto-generated decoder*/ +#include "decode_insn16.inc.c" +#include "insn_trans/trans_rvc.inc.c" + static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { int rs1, rd; @@ -1042,7 +1018,10 @@ static void decode_opc(DisasContext *ctx) gen_exception_illegal(ctx); } else { ctx->pc_succ_insn = ctx->base.pc_next + 2; - decode_RV32_64C(ctx->env, ctx); + if (!decode_insn16(ctx, ctx->opcode)) { + /* fall back to old decoder */ + decode_RV32_64C(ctx->env, ctx); + } } } else { ctx->pc_succ_insn = ctx->base.pc_next + 4; -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [Qemu-riscv] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree Date: Tue, 22 Jan 2019 10:28:51 +0100 [thread overview] Message-ID: <20190122092909.5341-18-kbastian@mail.uni-paderborn.de> (raw) In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de> --- target/riscv/Makefile.objs | 9 ++- target/riscv/insn16.decode | 55 ++++++++++++++++++ target/riscv/insn_trans/trans_rvc.inc.c | 75 +++++++++++++++++++++++++ target/riscv/translate.c | 53 ++++++----------- 4 files changed, 154 insertions(+), 38 deletions(-) create mode 100644 target/riscv/insn16.decode create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index 05087a91bb..9c6c109327 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -10,4 +10,11 @@ target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \ "GEN", $(TARGET_DIR)$@) -target/riscv/translate.o: target/riscv/decode_insn32.inc.c +target/riscv/decode_insn16.inc.c: \ + $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE) + $(call quiet-command, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \ + "GEN", $(TARGET_DIR)$@) + +target/riscv/translate.o: target/riscv/decode_insn32.inc.c \ + target/riscv/decode_insn16.inc.c diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode new file mode 100644 index 0000000000..558c0c41f0 --- /dev/null +++ b/target/riscv/insn16.decode @@ -0,0 +1,55 @@ +# +# RISC-V translation routines for the RVXI Base Integer Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see <http://www.gnu.org/licenses/>. + +# Fields: +%rd 7:5 +%rs1_3 7:3 !function=ex_rvc_register +%rs2_3 2:3 !function=ex_rvc_register + +# Immediates: +%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2 +%uimm_cl_d 5:2 10:3 !function=ex_shift_3 +%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2 + + +# Argument sets: +&cl rs1 rd +&cl_dw uimm rs1 rd +&ciw nzuimm rd +&cs rs1 rs2 +&cs_dw uimm rs1 rs2 + + +# Formats 16: +@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3 +@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 +@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 +@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3 +@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3 +@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 +@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 + + +# *** RV64C Standard Extension (Quadrant 0) *** +c_addi4spn 000 ........ ... 00 @ciw +c_fld 001 ... ... .. ... 00 @cl_d +c_lw 010 ... ... .. ... 00 @cl_w +c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually +c_fsd 101 ... ... .. ... 00 @cs_d +c_sw 110 ... ... .. ... 00 @cs_w +c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c new file mode 100644 index 0000000000..93ec8aa30b --- /dev/null +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -0,0 +1,75 @@ +/* + * RISC-V translation routines for the RVC Compressed Instruction Set. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a) +{ + if (a->nzuimm == 0) { + /* Reserved in ISA */ + return false; + } + arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm }; + return trans_addi(ctx, &arg); +} + +static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a) +{ + arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm }; + return trans_fld(ctx, &arg); +} + +static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a) +{ + arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm }; + return trans_lw(ctx, &arg); +} + +static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) +{ +#ifdef TARGET_RISCV32 + /* C.FLW ( RV32FC-only ) */ + return false; +#else + /* C.LD ( RV64C/RV128C-only ) */ + return false; +#endif +} + +static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a) +{ + arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm }; + return trans_fsd(ctx, &arg); +} + +static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a) +{ + arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm }; + return trans_sw(ctx, &arg); +} + +static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) +{ +#ifdef TARGET_RISCV32 + /* C.FSW ( RV32FC-only ) */ + return false; +#else + /* C.SD ( RV64C/RV128C-only ) */ + return false; +#endif +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ff15e0f7ed..1ee13c1907 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -720,27 +720,6 @@ static void decode_RV32_64C0(DisasContext *ctx) uint8_t rs1s = GET_C_RS1S(ctx->opcode); switch (funct3) { - case 0: - /* illegal */ - if (ctx->opcode == 0) { - gen_exception_illegal(ctx); - } else { - /* C.ADDI4SPN -> addi rd', x2, zimm[9:2]*/ - gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs2, 2, - GET_C_ADDI4SPN_IMM(ctx->opcode)); - } - break; - case 1: - /* C.FLD -> fld rd', offset[7:3](rs1')*/ - gen_fp_load(ctx, OPC_RISC_FLD, rd_rs2, rs1s, - GET_C_LD_IMM(ctx->opcode)); - /* C.LQ(RV128) */ - break; - case 2: - /* C.LW -> lw rd', offset[6:2](rs1') */ - gen_load(ctx, OPC_RISC_LW, rd_rs2, rs1s, - GET_C_LW_IMM(ctx->opcode)); - break; case 3: #if defined(TARGET_RISCV64) /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ @@ -752,21 +731,6 @@ static void decode_RV32_64C0(DisasContext *ctx) GET_C_LW_IMM(ctx->opcode)); #endif break; - case 4: - /* reserved */ - gen_exception_illegal(ctx); - break; - case 5: - /* C.FSD(RV32/64) -> fsd rs2', offset[7:3](rs1') */ - gen_fp_store(ctx, OPC_RISC_FSD, rs1s, rd_rs2, - GET_C_LD_IMM(ctx->opcode)); - /* C.SQ (RV128) */ - break; - case 6: - /* C.SW -> sw rs2', offset[6:2](rs1')*/ - gen_store(ctx, OPC_RISC_SW, rs1s, rd_rs2, - GET_C_LW_IMM(ctx->opcode)); - break; case 7: #if defined(TARGET_RISCV64) /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ @@ -996,8 +960,15 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx) return imm << amount; \ } EX_SH(1) +EX_SH(2) +EX_SH(3) EX_SH(12) +static int ex_rvc_register(int reg) +{ + return 8 + reg; +} + bool decode_insn32(DisasContext *ctx, uint32_t insn); /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" @@ -1009,6 +980,11 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn); #include "insn_trans/trans_rvd.inc.c" #include "insn_trans/trans_privileged.inc.c" +bool decode_insn16(DisasContext *ctx, uint16_t insn); +/* auto-generated decoder*/ +#include "decode_insn16.inc.c" +#include "insn_trans/trans_rvc.inc.c" + static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { int rs1, rd; @@ -1042,7 +1018,10 @@ static void decode_opc(DisasContext *ctx) gen_exception_illegal(ctx); } else { ctx->pc_succ_insn = ctx->base.pc_next + 2; - decode_RV32_64C(ctx->env, ctx); + if (!decode_insn16(ctx, ctx->opcode)) { + /* fall back to old decoder */ + decode_RV32_64C(ctx->env, ctx); + } } } else { ctx->pc_succ_insn = ctx->base.pc_next + 4; -- 2.20.1
next prev parent reply other threads:[~2019-01-22 9:38 UTC|newest] Thread overview: 164+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-01-22 9:28 [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 23:03 ` [Qemu-devel] " Alistair Francis 2019-01-22 23:03 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 23:38 ` [Qemu-devel] " Alistair Francis 2019-01-22 23:38 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 05/35] target/riscv: Convert RV64I " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 09/35] target/riscv: Convert RVXM " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 10/35] target/riscv: Convert RV32A " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 23:43 ` [Qemu-devel] " Alistair Francis 2019-01-22 23:43 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 11/35] target/riscv: Convert RV64A " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 12/35] target/riscv: Convert RV32F " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 0:00 ` [Qemu-devel] " Alistair Francis 2019-01-23 0:00 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 0:08 ` [Qemu-devel] " Alistair Francis 2019-01-23 0:08 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 0:08 ` [Qemu-devel] " Alistair Francis 2019-01-23 0:08 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 15/35] target/riscv: Convert RV64D " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 0:10 ` [Qemu-devel] " Alistair Francis 2019-01-23 0:10 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 16/35] target/riscv: Convert RV priv " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 1:00 ` [Qemu-devel] " Alistair Francis 2019-01-23 1:00 ` [Qemu-riscv] " Alistair Francis 2019-01-22 9:28 ` Bastian Koppelmann [this message] 2019-01-22 9:28 ` [Qemu-riscv] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 21:32 ` [Qemu-devel] " Richard Henderson 2019-01-22 21:32 ` [Qemu-riscv] " Richard Henderson 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 21:36 ` [Qemu-devel] " Richard Henderson 2019-01-22 21:36 ` [Qemu-riscv] " Richard Henderson 2019-01-22 9:28 ` [Qemu-devel] [PATCH v5 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann 2019-01-22 9:28 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 29/35] target/riscv: Remove gen_system() Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-devel] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann 2019-01-22 9:29 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-22 21:38 ` [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree Richard Henderson 2019-01-22 21:38 ` [Qemu-riscv] " Richard Henderson 2019-01-23 9:15 ` [Qemu-devel] " Bastian Koppelmann 2019-01-23 9:15 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-23 21:22 ` Alistair Francis 2019-01-23 21:22 ` [Qemu-riscv] " Alistair Francis 2019-01-25 23:54 ` Palmer Dabbelt 2019-01-25 23:54 ` [Qemu-riscv] " Palmer Dabbelt 2019-01-26 8:51 ` [Qemu-devel] " Bastian Koppelmann 2019-01-26 8:51 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-29 19:22 ` Palmer Dabbelt 2019-01-29 19:22 ` [Qemu-riscv] " Palmer Dabbelt 2019-01-29 21:13 ` Alistair Francis 2019-01-29 21:13 ` [Qemu-riscv] " Alistair Francis 2019-01-30 9:08 ` Bastian Koppelmann 2019-01-30 9:08 ` [Qemu-riscv] " Bastian Koppelmann 2019-01-30 18:47 ` Palmer Dabbelt 2019-01-30 18:47 ` [Qemu-riscv] " Palmer Dabbelt 2019-01-31 18:06 ` no-reply 2019-01-31 18:06 ` [Qemu-riscv] " no-reply 2019-01-31 18:48 ` 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