* [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model
@ 2020-03-03 19:56 Babu Moger
2020-03-03 19:56 ` [PATCH v5 01/16] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs Babu Moger
` (17 more replies)
0 siblings, 18 replies; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:56 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
This series fixes APIC ID encoding problem reported on AMD EPYC cpu models.
https://bugzilla.redhat.com/show_bug.cgi?id=1728166
Currently, the APIC ID is decoded based on the sequence
sockets->dies->cores->threads. This works for most standard AMD and other
vendors' configurations, but this decoding sequence does not follow that of
AMD's APIC ID enumeration strictly. In some cases this can cause CPU topology
inconsistency. When booting a guest VM, the kernel tries to validate the
topology, and finds it inconsistent with the enumeration of EPYC cpu models.
To fix the problem we need to build the topology as per the Processor
Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
Processors. The documentation is available from the bugzilla Link below.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Here is the text from the PPR.
Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
number of least significant bits in the Initial APIC ID that indicate core ID
within a processor, in constructing per-core CPUID masks.
Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
(MNC) that the processor could theoretically support, not the actual number of
cores that are actually implemented or enabled on the processor, as indicated
by Core::X86::Cpuid::SizeId[NC].
Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
• ApicId[6] = Socket ID.
• ApicId[5:4] = Node ID.
• ApicId[3] = Logical CCX L3 complex ID
• ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
v5:
Generated the patches on top of git://github.com/ehabkost/qemu.git (x86-next).
Changes from v4.
1. Re-arranged the patches 2 and 4 as suggested by Igor.
2. Kept the apicid handler functions inside X86MachineState as discussed.
These handlers are loaded from X86CPUDefinitions.
3. Removed unnecessary X86CPUstate initialization from x86_cpu_new. Suggested
by Igor.
4. And other minor changes related to patch format.
v4:
https://lore.kernel.org/qemu-devel/158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com/
Changes from v3.
1. Moved the arch_id calculation inside the function x86_cpus_init. With this change,
we dont need to change common numa code.(suggested by Igor)
2. Introduced the model specific handlers inside X86CPUDefinitions.
These handlers are loaded into X86MachineState during the init.
3. Removed llc_id from x86CPU.
4. Removed init_apicid_fn hanlder from MachineClass. Kept all the code changes
inside the x86.
5. Added new handler function apicid_pkg_offset for pkg_offset calculation.
6. And some Other minor changes.
v3:
https://lore.kernel.org/qemu-devel/157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com/
1. Consolidated the topology information in structure X86CPUTopoInfo.
2. Changed the ccx_id to llc_id as commented by upstream.
3. Generalized the apic id decoding. It is mostly similar to current apic id
except that it adds new field llc_id when numa configured. Removes all the
hardcoded values.
4. Removed the earlier parse_numa split. And moved the numa node initialization
inside the numa_complete_configuration. This is bit cleaner as commented by
Eduardo.
5. Added new function init_apicid_fn inside machine_class structure. This
will be used to update the apic id handler specific to cpu model.
6. Updated the cpuid unit tests.
7. TODO : Need to figure out how to dynamically update the handlers using cpu models.
I might some guidance on that.
v2:
https://lore.kernel.org/qemu-devel/156779689013.21957.1631551572950676212.stgit@localhost.localdomain/
1. Introduced the new property epyc to enable new epyc mode.
2. Separated the epyc mode and non epyc mode function.
3. Introduced function pointers in PCMachineState to handle the
differences.
4. Mildly tested different combinations to make things are working as expected.
5. TODO : Setting the epyc feature bit needs to be worked out. This feature is
supported only on AMD EPYC models. I may need some guidance on that.
v1:
https://lore.kernel.org/qemu-devel/20190731232032.51786-1-babu.moger@amd.com/
---
Babu Moger (16):
hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
hw/i386: Introduce X86CPUTopoInfo to contain topology info
hw/i386: Consolidate topology functions
machine: Add SMP Sockets in CpuTopology
hw/i386: Remove unnecessary initialization in x86_cpu_new
hw/i386: Update structures to save the number of nodes per package
hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids
hw/386: Add EPYC mode topology decoding functions
target/i386: Cleanup and use the EPYC mode topology functions
hw/i386: Introduce apicid functions inside X86MachineState
target/i386: Load apicid model specific handlers from X86CPUDefinition
hw/i386: Use the apicid handlers from X86MachineState
target/i386: Add EPYC model specific handlers
hw/i386: Move arch_id decode inside x86_cpus_init
i386: Fix pkg_id offset for EPYC cpu models
tests: Update the Unit tests
hw/core/machine.c | 1
hw/i386/pc.c | 54 ++++++-----
hw/i386/x86.c | 72 ++++++++++----
include/hw/boards.h | 2
include/hw/i386/topology.h | 215 ++++++++++++++++++++++++++++++------------
include/hw/i386/x86.h | 12 ++
target/i386/cpu.c | 224 +++++++++++++++++---------------------------
target/i386/cpu.h | 3 +
tests/test-x86-cpuid.c | 115 +++++++++++++----------
vl.c | 1
10 files changed, 403 insertions(+), 296 deletions(-)
--
Signature
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH v5 01/16] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
@ 2020-03-03 19:56 ` Babu Moger
2020-03-03 19:57 ` [PATCH v5 02/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info Babu Moger
` (16 subsequent siblings)
17 siblings, 0 replies; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:56 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
Rename few data structures related to X86 topology. X86CPUTopoIDs will
have individual arch ids. Next patch introduces X86CPUTopoInfo which will
have all topology information(like cores, threads etc..).
Signed-off-by: Babu Moger <babu.moger@amd.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/i386/pc.c | 45 +++++++++++++++++++++++---------------------
hw/i386/x86.c | 18 +++++++++---------
include/hw/i386/topology.h | 44 +++++++++++++++++++++++--------------------
3 files changed, 57 insertions(+), 50 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 2ddce4230a..715f79f58c 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1506,7 +1506,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
int idx;
CPUState *cs;
CPUArchId *cpu_slot;
- X86CPUTopoInfo topo;
+ X86CPUTopoIDs topo_ids;
X86CPU *cpu = X86_CPU(dev);
CPUX86State *env = &cpu->env;
MachineState *ms = MACHINE(hotplug_dev);
@@ -1572,12 +1572,12 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
return;
}
- topo.pkg_id = cpu->socket_id;
- topo.die_id = cpu->die_id;
- topo.core_id = cpu->core_id;
- topo.smt_id = cpu->thread_id;
+ topo_ids.pkg_id = cpu->socket_id;
+ topo_ids.die_id = cpu->die_id;
+ topo_ids.core_id = cpu->core_id;
+ topo_ids.smt_id = cpu->thread_id;
cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,
- smp_threads, &topo);
+ smp_threads, &topo_ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
@@ -1585,11 +1585,11 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
MachineState *ms = MACHINE(pcms);
x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
- smp_cores, smp_threads, &topo);
+ smp_cores, smp_threads, &topo_ids);
error_setg(errp,
"Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
" APIC ID %" PRIu32 ", valid index range 0:%d",
- topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
+ topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id,
cpu->apic_id, ms->possible_cpus->len - 1);
return;
}
@@ -1607,34 +1607,37 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
* once -smp refactoring is complete and there will be CPU private
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
- smp_cores, smp_threads, &topo);
- if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
+ smp_cores, smp_threads, &topo_ids);
+ if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
- " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
+ " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
+ topo_ids.pkg_id);
return;
}
- cpu->socket_id = topo.pkg_id;
+ cpu->socket_id = topo_ids.pkg_id;
- if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
+ if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) {
error_setg(errp, "property die-id: %u doesn't match set apic-id:"
- " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
+ " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id);
return;
}
- cpu->die_id = topo.die_id;
+ cpu->die_id = topo_ids.die_id;
- if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
+ if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) {
error_setg(errp, "property core-id: %u doesn't match set apic-id:"
- " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
+ " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id,
+ topo_ids.core_id);
return;
}
- cpu->core_id = topo.core_id;
+ cpu->core_id = topo_ids.core_id;
- if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
+ if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) {
error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
- " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
+ " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id,
+ topo_ids.smt_id);
return;
}
- cpu->thread_id = topo.smt_id;
+ cpu->thread_id = topo_ids.smt_id;
if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
!kvm_hv_vpindex_settable()) {
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 7f38e6ba8b..322fb6abbc 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -143,14 +143,14 @@ x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
{
- X86CPUTopoInfo topo;
+ X86CPUTopoIDs topo_ids;
X86MachineState *x86ms = X86_MACHINE(ms);
assert(idx < ms->possible_cpus->len);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
x86ms->smp_dies, ms->smp.cores,
- ms->smp.threads, &topo);
- return topo.pkg_id % ms->numa_state->num_nodes;
+ ms->smp.threads, &topo_ids);
+ return topo_ids.pkg_id % ms->numa_state->num_nodes;
}
const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
@@ -172,7 +172,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
sizeof(CPUArchId) * max_cpus);
ms->possible_cpus->len = max_cpus;
for (i = 0; i < ms->possible_cpus->len; i++) {
- X86CPUTopoInfo topo;
+ X86CPUTopoIDs topo_ids;
ms->possible_cpus->cpus[i].type = ms->cpu_type;
ms->possible_cpus->cpus[i].vcpus_count = 1;
@@ -180,17 +180,17 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
x86_cpu_apic_id_from_index(x86ms, i);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
x86ms->smp_dies, ms->smp.cores,
- ms->smp.threads, &topo);
+ ms->smp.threads, &topo_ids);
ms->possible_cpus->cpus[i].props.has_socket_id = true;
- ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
+ ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
if (x86ms->smp_dies > 1) {
ms->possible_cpus->cpus[i].props.has_die_id = true;
- ms->possible_cpus->cpus[i].props.die_id = topo.die_id;
+ ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id;
}
ms->possible_cpus->cpus[i].props.has_core_id = true;
- ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
+ ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id;
ms->possible_cpus->cpus[i].props.has_thread_id = true;
- ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
+ ms->possible_cpus->cpus[i].props.thread_id = topo_ids.smt_id;
}
return ms->possible_cpus;
}
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 4ff5b2da6c..52def68610 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -45,12 +45,12 @@
*/
typedef uint32_t apic_id_t;
-typedef struct X86CPUTopoInfo {
+typedef struct X86CPUTopoIDs {
unsigned pkg_id;
unsigned die_id;
unsigned core_id;
unsigned smt_id;
-} X86CPUTopoInfo;
+} X86CPUTopoIDs;
/* Return the bit width needed for 'count' IDs
*/
@@ -122,12 +122,15 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies,
static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies,
unsigned nr_cores,
unsigned nr_threads,
- const X86CPUTopoInfo *topo)
+ const X86CPUTopoIDs *topo_ids)
{
- return (topo->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) |
- (topo->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threads)) |
- (topo->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threads)) |
- topo->smt_id;
+ return (topo_ids->pkg_id <<
+ apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) |
+ (topo_ids->die_id <<
+ apicid_die_offset(nr_dies, nr_cores, nr_threads)) |
+ (topo_ids->core_id <<
+ apicid_core_offset(nr_dies, nr_cores, nr_threads)) |
+ topo_ids->smt_id;
}
/* Calculate thread/core/package IDs for a specific topology,
@@ -137,12 +140,12 @@ static inline void x86_topo_ids_from_idx(unsigned nr_dies,
unsigned nr_cores,
unsigned nr_threads,
unsigned cpu_index,
- X86CPUTopoInfo *topo)
+ X86CPUTopoIDs *topo_ids)
{
- topo->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads);
- topo->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies;
- topo->core_id = cpu_index / nr_threads % nr_cores;
- topo->smt_id = cpu_index % nr_threads;
+ topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads);
+ topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies;
+ topo_ids->core_id = cpu_index / nr_threads % nr_cores;
+ topo_ids->smt_id = cpu_index % nr_threads;
}
/* Calculate thread/core/package IDs for a specific topology,
@@ -152,17 +155,18 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
unsigned nr_dies,
unsigned nr_cores,
unsigned nr_threads,
- X86CPUTopoInfo *topo)
+ X86CPUTopoIDs *topo_ids)
{
- topo->smt_id = apicid &
+ topo_ids->smt_id = apicid &
~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads));
- topo->core_id =
+ topo_ids->core_id =
(apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) &
~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_threads));
- topo->die_id =
+ topo_ids->die_id =
(apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) &
~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threads));
- topo->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads);
+ topo_ids->pkg_id =
+ apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads);
}
/* Make APIC ID for the CPU 'cpu_index'
@@ -174,9 +178,9 @@ static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_dies,
unsigned nr_threads,
unsigned cpu_index)
{
- X86CPUTopoInfo topo;
- x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo);
- return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo);
+ X86CPUTopoIDs topo_ids;
+ x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo_ids);
+ return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo_ids);
}
#endif /* HW_I386_TOPOLOGY_H */
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 02/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
2020-03-03 19:56 ` [PATCH v5 01/16] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs Babu Moger
@ 2020-03-03 19:57 ` Babu Moger
2020-03-09 14:10 ` Igor Mammedov
2020-03-10 23:04 ` Eduardo Habkost
2020-03-03 19:57 ` [PATCH v5 03/16] hw/i386: Consolidate topology functions Babu Moger
` (15 subsequent siblings)
17 siblings, 2 replies; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:57 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
This is an effort to re-arrange few data structure for better readability.
1. Add X86CPUTopoInfo which will have all the topology informations
required to build the cpu topology. There is no functional changes.
2. Introduce init_topo_info to initialize X86CPUTopoInfo members from
X86MachineState.
There is no functional changes.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
hw/i386/pc.c | 12 ++++++------
hw/i386/x86.c | 32 ++++++++++++++++++++++++--------
include/hw/i386/topology.h | 38 ++++++++++++++++++++++++--------------
include/hw/i386/x86.h | 3 +++
4 files changed, 57 insertions(+), 28 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 715f79f58c..ef23ae2af5 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1514,6 +1514,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
X86MachineState *x86ms = X86_MACHINE(pcms);
unsigned int smp_cores = ms->smp.cores;
unsigned int smp_threads = ms->smp.threads;
+ X86CPUTopoInfo topo_info;
if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
@@ -1521,6 +1522,8 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
return;
}
+ init_topo_info(&topo_info, x86ms);
+
env->nr_dies = x86ms->smp_dies;
/*
@@ -1576,16 +1579,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
topo_ids.die_id = cpu->die_id;
topo_ids.core_id = cpu->core_id;
topo_ids.smt_id = cpu->thread_id;
- cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,
- smp_threads, &topo_ids);
+ cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
if (!cpu_slot) {
MachineState *ms = MACHINE(pcms);
- x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
- smp_cores, smp_threads, &topo_ids);
+ x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
error_setg(errp,
"Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
" APIC ID %" PRIu32 ", valid index range 0:%d",
@@ -1606,8 +1607,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
/* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
* once -smp refactoring is complete and there will be CPU private
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
- x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
- smp_cores, smp_threads, &topo_ids);
+ x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 322fb6abbc..03b8962c98 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -57,6 +57,16 @@
/* Physical Address of PVH entry point read from kernel ELF NOTE */
static size_t pvh_start_addr;
+inline void init_topo_info(X86CPUTopoInfo *topo_info,
+ const X86MachineState *x86ms)
+{
+ MachineState *ms = MACHINE(x86ms);
+
+ topo_info->dies_per_pkg = x86ms->smp_dies;
+ topo_info->cores_per_die = ms->smp.cores;
+ topo_info->threads_per_core = ms->smp.threads;
+}
+
/*
* Calculates initial APIC ID for a specific CPU index
*
@@ -68,13 +78,14 @@ static size_t pvh_start_addr;
uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
unsigned int cpu_index)
{
- MachineState *ms = MACHINE(x86ms);
X86MachineClass *x86mc = X86_MACHINE_GET_CLASS(x86ms);
+ X86CPUTopoInfo topo_info;
uint32_t correct_id;
static bool warned;
- correct_id = x86_apicid_from_cpu_idx(x86ms->smp_dies, ms->smp.cores,
- ms->smp.threads, cpu_index);
+ init_topo_info(&topo_info, x86ms);
+
+ correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index);
if (x86mc->compat_apic_id_mode) {
if (cpu_index != correct_id && !warned && !qtest_enabled()) {
error_report("APIC IDs set in compatibility mode, "
@@ -145,19 +156,22 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
{
X86CPUTopoIDs topo_ids;
X86MachineState *x86ms = X86_MACHINE(ms);
+ X86CPUTopoInfo topo_info;
+
+ init_topo_info(&topo_info, x86ms);
assert(idx < ms->possible_cpus->len);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
- x86ms->smp_dies, ms->smp.cores,
- ms->smp.threads, &topo_ids);
+ &topo_info, &topo_ids);
return topo_ids.pkg_id % ms->numa_state->num_nodes;
}
const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
{
X86MachineState *x86ms = X86_MACHINE(ms);
- int i;
unsigned int max_cpus = ms->smp.max_cpus;
+ X86CPUTopoInfo topo_info;
+ int i;
if (ms->possible_cpus) {
/*
@@ -171,6 +185,9 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
sizeof(CPUArchId) * max_cpus);
ms->possible_cpus->len = max_cpus;
+
+ init_topo_info(&topo_info, x86ms);
+
for (i = 0; i < ms->possible_cpus->len; i++) {
X86CPUTopoIDs topo_ids;
@@ -179,8 +196,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus->cpus[i].arch_id =
x86_cpu_apic_id_from_index(x86ms, i);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
- x86ms->smp_dies, ms->smp.cores,
- ms->smp.threads, &topo_ids);
+ &topo_info, &topo_ids);
ms->possible_cpus->cpus[i].props.has_socket_id = true;
ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
if (x86ms->smp_dies > 1) {
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 52def68610..7ea507f376 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -52,6 +52,12 @@ typedef struct X86CPUTopoIDs {
unsigned smt_id;
} X86CPUTopoIDs;
+typedef struct X86CPUTopoInfo {
+ unsigned dies_per_pkg;
+ unsigned cores_per_die;
+ unsigned threads_per_core;
+} X86CPUTopoInfo;
+
/* Return the bit width needed for 'count' IDs
*/
static unsigned apicid_bitwidth_for_count(unsigned count)
@@ -119,11 +125,13 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies,
*
* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
*/
-static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads,
+static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
const X86CPUTopoIDs *topo_ids)
{
+ unsigned nr_dies = topo_info->dies_per_pkg;
+ unsigned nr_cores = topo_info->cores_per_die;
+ unsigned nr_threads = topo_info->threads_per_core;
+
return (topo_ids->pkg_id <<
apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) |
(topo_ids->die_id <<
@@ -136,12 +144,14 @@ static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies,
/* Calculate thread/core/package IDs for a specific topology,
* based on (contiguous) CPU index
*/
-static inline void x86_topo_ids_from_idx(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads,
+static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info,
unsigned cpu_index,
X86CPUTopoIDs *topo_ids)
{
+ unsigned nr_dies = topo_info->dies_per_pkg;
+ unsigned nr_cores = topo_info->cores_per_die;
+ unsigned nr_threads = topo_info->threads_per_core;
+
topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads);
topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies;
topo_ids->core_id = cpu_index / nr_threads % nr_cores;
@@ -152,11 +162,13 @@ static inline void x86_topo_ids_from_idx(unsigned nr_dies,
* based on APIC ID
*/
static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
- unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads,
+ X86CPUTopoInfo *topo_info,
X86CPUTopoIDs *topo_ids)
{
+ unsigned nr_dies = topo_info->dies_per_pkg;
+ unsigned nr_cores = topo_info->cores_per_die;
+ unsigned nr_threads = topo_info->threads_per_core;
+
topo_ids->smt_id = apicid &
~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads));
topo_ids->core_id =
@@ -173,14 +185,12 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
*
* 'cpu_index' is a sequential, contiguous ID for the CPU.
*/
-static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads,
+static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info,
unsigned cpu_index)
{
X86CPUTopoIDs topo_ids;
- x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo_ids);
- return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo_ids);
+ x86_topo_ids_from_idx(topo_info, cpu_index, &topo_ids);
+ return apicid_from_topo_ids(topo_info, &topo_ids);
}
#endif /* HW_I386_TOPOLOGY_H */
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index 41fe37b8a3..22babcb3bb 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -21,6 +21,7 @@
#include "exec/hwaddr.h"
#include "qemu/notify.h"
+#include "hw/i386/topology.h"
#include "hw/boards.h"
#include "hw/nmi.h"
#include "hw/isa/isa.h"
@@ -82,6 +83,8 @@ typedef struct {
#define X86_MACHINE_CLASS(class) \
OBJECT_CLASS_CHECK(X86MachineClass, class, TYPE_X86_MACHINE)
+void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms);
+
uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms,
unsigned int cpu_index);
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 03/16] hw/i386: Consolidate topology functions
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
2020-03-03 19:56 ` [PATCH v5 01/16] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs Babu Moger
2020-03-03 19:57 ` [PATCH v5 02/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info Babu Moger
@ 2020-03-03 19:57 ` Babu Moger
2020-03-03 19:57 ` [PATCH v5 04/16] machine: Add SMP Sockets in CpuTopology Babu Moger
` (14 subsequent siblings)
17 siblings, 0 replies; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:57 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
Now that we have all the parameters in X86CPUTopoInfo, we can just
pass the structure to calculate the offsets and width.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
include/hw/i386/topology.h | 68 ++++++++++++++------------------------------
target/i386/cpu.c | 23 +++++++--------
2 files changed, 32 insertions(+), 59 deletions(-)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 7ea507f376..ba52d49079 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -69,56 +69,42 @@ static unsigned apicid_bitwidth_for_count(unsigned count)
/* Bit width of the SMT_ID (thread ID) field on the APIC ID
*/
-static inline unsigned apicid_smt_width(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info)
{
- return apicid_bitwidth_for_count(nr_threads);
+ return apicid_bitwidth_for_count(topo_info->threads_per_core);
}
/* Bit width of the Core_ID field
*/
-static inline unsigned apicid_core_width(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info)
{
- return apicid_bitwidth_for_count(nr_cores);
+ return apicid_bitwidth_for_count(topo_info->cores_per_die);
}
/* Bit width of the Die_ID field */
-static inline unsigned apicid_die_width(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info)
{
- return apicid_bitwidth_for_count(nr_dies);
+ return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
}
/* Bit offset of the Core_ID field
*/
-static inline unsigned apicid_core_offset(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
{
- return apicid_smt_width(nr_dies, nr_cores, nr_threads);
+ return apicid_smt_width(topo_info);
}
/* Bit offset of the Die_ID field */
-static inline unsigned apicid_die_offset(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info)
{
- return apicid_core_offset(nr_dies, nr_cores, nr_threads) +
- apicid_core_width(nr_dies, nr_cores, nr_threads);
+ return apicid_core_offset(topo_info) + apicid_core_width(topo_info);
}
/* Bit offset of the Pkg_ID (socket ID) field
*/
-static inline unsigned apicid_pkg_offset(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
{
- return apicid_die_offset(nr_dies, nr_cores, nr_threads) +
- apicid_die_width(nr_dies, nr_cores, nr_threads);
+ return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
}
/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
@@ -128,16 +114,9 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies,
static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
const X86CPUTopoIDs *topo_ids)
{
- unsigned nr_dies = topo_info->dies_per_pkg;
- unsigned nr_cores = topo_info->cores_per_die;
- unsigned nr_threads = topo_info->threads_per_core;
-
- return (topo_ids->pkg_id <<
- apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) |
- (topo_ids->die_id <<
- apicid_die_offset(nr_dies, nr_cores, nr_threads)) |
- (topo_ids->core_id <<
- apicid_core_offset(nr_dies, nr_cores, nr_threads)) |
+ return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) |
+ (topo_ids->die_id << apicid_die_offset(topo_info)) |
+ (topo_ids->core_id << apicid_core_offset(topo_info)) |
topo_ids->smt_id;
}
@@ -165,20 +144,15 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
X86CPUTopoInfo *topo_info,
X86CPUTopoIDs *topo_ids)
{
- unsigned nr_dies = topo_info->dies_per_pkg;
- unsigned nr_cores = topo_info->cores_per_die;
- unsigned nr_threads = topo_info->threads_per_core;
-
topo_ids->smt_id = apicid &
- ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads));
+ ~(0xFFFFFFFFUL << apicid_smt_width(topo_info));
topo_ids->core_id =
- (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) &
- ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_threads));
+ (apicid >> apicid_core_offset(topo_info)) &
+ ~(0xFFFFFFFFUL << apicid_core_width(topo_info));
topo_ids->die_id =
- (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) &
- ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threads));
- topo_ids->pkg_id =
- apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads);
+ (apicid >> apicid_die_offset(topo_info)) &
+ ~(0xFFFFFFFFUL << apicid_die_width(topo_info));
+ topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info);
}
/* Make APIC ID for the CPU 'cpu_index'
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 92fafa2659..1263271edd 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5369,6 +5369,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
uint32_t die_offset;
uint32_t limit;
uint32_t signature[3];
+ X86CPUTopoInfo topo_info;
+
+ topo_info.dies_per_pkg = env->nr_dies;
+ topo_info.cores_per_die = cs->nr_cores;
+ topo_info.threads_per_core = cs->nr_threads;
/* Calculate & apply limits for different index ranges */
if (index >= 0xC0000000) {
@@ -5455,8 +5460,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
eax, ebx, ecx, edx);
break;
case 3: /* L3 cache info */
- die_offset = apicid_die_offset(env->nr_dies,
- cs->nr_cores, cs->nr_threads);
+ die_offset = apicid_die_offset(&topo_info);
if (cpu->enable_l3_cache) {
encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
(1 << die_offset), cs->nr_cores,
@@ -5547,14 +5551,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
switch (count) {
case 0:
- *eax = apicid_core_offset(env->nr_dies,
- cs->nr_cores, cs->nr_threads);
+ *eax = apicid_core_offset(&topo_info);
*ebx = cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
- *eax = apicid_pkg_offset(env->nr_dies,
- cs->nr_cores, cs->nr_threads);
+ *eax = apicid_pkg_offset(&topo_info);
*ebx = cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
@@ -5578,20 +5580,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*edx = cpu->apic_id;
switch (count) {
case 0:
- *eax = apicid_core_offset(env->nr_dies, cs->nr_cores,
- cs->nr_threads);
+ *eax = apicid_core_offset(&topo_info);
*ebx = cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
- *eax = apicid_die_offset(env->nr_dies, cs->nr_cores,
- cs->nr_threads);
+ *eax = apicid_die_offset(&topo_info);
*ebx = cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
case 2:
- *eax = apicid_pkg_offset(env->nr_dies, cs->nr_cores,
- cs->nr_threads);
+ *eax = apicid_pkg_offset(&topo_info);
*ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
break;
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 04/16] machine: Add SMP Sockets in CpuTopology
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (2 preceding siblings ...)
2020-03-03 19:57 ` [PATCH v5 03/16] hw/i386: Consolidate topology functions Babu Moger
@ 2020-03-03 19:57 ` Babu Moger
2020-03-09 14:17 ` Igor Mammedov
2020-03-03 19:57 ` [PATCH v5 05/16] hw/i386: Remove unnecessary initialization in x86_cpu_new Babu Moger
` (13 subsequent siblings)
17 siblings, 1 reply; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:57 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
Store the smp sockets in CpuTopology. The socket information required to
build the apic id in EPYC mode. Right now socket information is not passed
to down when decoding the apic id. Add the socket information here.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/core/machine.c | 1 +
hw/i386/pc.c | 1 +
include/hw/boards.h | 2 ++
vl.c | 1 +
4 files changed, 5 insertions(+)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index d8e30e4895..2582ce94f6 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -728,6 +728,7 @@ static void smp_parse(MachineState *ms, QemuOpts *opts)
ms->smp.cpus = cpus;
ms->smp.cores = cores;
ms->smp.threads = threads;
+ ms->smp.sockets = sockets;
}
if (ms->smp.cpus > 1) {
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index ef23ae2af5..68bf08f285 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -780,6 +780,7 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts)
ms->smp.cpus = cpus;
ms->smp.cores = cores;
ms->smp.threads = threads;
+ ms->smp.sockets = sockets;
x86ms->smp_dies = dies;
}
diff --git a/include/hw/boards.h b/include/hw/boards.h
index fb1b43d5b9..320dd14e02 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -252,12 +252,14 @@ typedef struct DeviceMemoryState {
* @cpus: the number of present logical processors on the machine
* @cores: the number of cores in one package
* @threads: the number of threads in one core
+ * @sockets: the number of sockets on the machine
* @max_cpus: the maximum number of logical processors on the machine
*/
typedef struct CpuTopology {
unsigned int cpus;
unsigned int cores;
unsigned int threads;
+ unsigned int sockets;
unsigned int max_cpus;
} CpuTopology;
diff --git a/vl.c b/vl.c
index 7dcb0879c4..f77b1285c6 100644
--- a/vl.c
+++ b/vl.c
@@ -3949,6 +3949,7 @@ int main(int argc, char **argv, char **envp)
current_machine->smp.max_cpus = machine_class->default_cpus;
current_machine->smp.cores = 1;
current_machine->smp.threads = 1;
+ current_machine->smp.sockets = 1;
machine_class->smp_parse(current_machine,
qemu_opts_find(qemu_find_opts("smp-opts"), NULL));
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 05/16] hw/i386: Remove unnecessary initialization in x86_cpu_new
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (3 preceding siblings ...)
2020-03-03 19:57 ` [PATCH v5 04/16] machine: Add SMP Sockets in CpuTopology Babu Moger
@ 2020-03-03 19:57 ` Babu Moger
2020-03-09 14:18 ` Igor Mammedov
2020-03-03 19:57 ` [PATCH v5 06/16] hw/i386: Update structures to save the number of nodes per package Babu Moger
` (12 subsequent siblings)
17 siblings, 1 reply; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:57 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
The function pc_cpu_pre_plug takes care of initialization of CPUX86State.
So, remove the initialization here.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
hw/i386/x86.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 03b8962c98..79badcc4ec 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -103,13 +103,9 @@ void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp)
{
Object *cpu = NULL;
Error *local_err = NULL;
- CPUX86State *env = NULL;
cpu = object_new(MACHINE(x86ms)->cpu_type);
- env = &X86_CPU(cpu)->env;
- env->nr_dies = x86ms->smp_dies;
-
object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
object_property_set_bool(cpu, true, "realized", &local_err);
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 06/16] hw/i386: Update structures to save the number of nodes per package
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (4 preceding siblings ...)
2020-03-03 19:57 ` [PATCH v5 05/16] hw/i386: Remove unnecessary initialization in x86_cpu_new Babu Moger
@ 2020-03-03 19:57 ` Babu Moger
2020-03-09 14:26 ` Igor Mammedov
2020-03-03 19:57 ` [PATCH v5 07/16] hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids Babu Moger
` (11 subsequent siblings)
17 siblings, 1 reply; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:57 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
Update structures X86CPUTopoIDs and CPUX86State to hold the number of
nodes per package. This is required to build EPYC mode topology.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
hw/i386/pc.c | 1 +
hw/i386/x86.c | 1 +
include/hw/i386/topology.h | 1 +
target/i386/cpu.c | 1 +
target/i386/cpu.h | 1 +
5 files changed, 5 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 68bf08f285..3d13cd46d6 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1526,6 +1526,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
init_topo_info(&topo_info, x86ms);
env->nr_dies = x86ms->smp_dies;
+ env->nr_nodes = topo_info.nodes_per_pkg;
/*
* If APIC ID is not set,
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 79badcc4ec..929b80c9c7 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -62,6 +62,7 @@ inline void init_topo_info(X86CPUTopoInfo *topo_info,
{
MachineState *ms = MACHINE(x86ms);
+ topo_info->nodes_per_pkg = ms->numa_state->num_nodes / ms->smp.sockets;
topo_info->dies_per_pkg = x86ms->smp_dies;
topo_info->cores_per_die = ms->smp.cores;
topo_info->threads_per_core = ms->smp.threads;
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index ba52d49079..04f01e2a09 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -53,6 +53,7 @@ typedef struct X86CPUTopoIDs {
} X86CPUTopoIDs;
typedef struct X86CPUTopoInfo {
+ unsigned nodes_per_pkg;
unsigned dies_per_pkg;
unsigned cores_per_die;
unsigned threads_per_core;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1263271edd..40670f8aca 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6829,6 +6829,7 @@ static void x86_cpu_initfn(Object *obj)
FeatureWord w;
env->nr_dies = 1;
+ env->nr_nodes = 1;
cpu_set_cpustate_pointers(cpu);
object_property_add(obj, "family", "int",
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 576f309bbf..20abbda647 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1607,6 +1607,7 @@ typedef struct CPUX86State {
TPRAccess tpr_access_type;
unsigned nr_dies;
+ unsigned nr_nodes;
} CPUX86State;
struct kvm_msrs;
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 07/16] hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (5 preceding siblings ...)
2020-03-03 19:57 ` [PATCH v5 06/16] hw/i386: Update structures to save the number of nodes per package Babu Moger
@ 2020-03-03 19:57 ` Babu Moger
2020-03-03 19:57 ` [PATCH v5 08/16] hw/386: Add EPYC mode topology decoding functions Babu Moger
` (10 subsequent siblings)
17 siblings, 0 replies; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:57 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
For consistancy rename apicid_from_topo_ids to x86_apicid_from_topo_ids.
No functional change.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/i386/pc.c | 2 +-
include/hw/i386/topology.h | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 3d13cd46d6..17cce3f074 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1581,7 +1581,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
topo_ids.die_id = cpu->die_id;
topo_ids.core_id = cpu->core_id;
topo_ids.smt_id = cpu->thread_id;
- cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids);
+ cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 04f01e2a09..b9593b9905 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -112,8 +112,8 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
*
* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
*/
-static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
- const X86CPUTopoIDs *topo_ids)
+static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
+ const X86CPUTopoIDs *topo_ids)
{
return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) |
(topo_ids->die_id << apicid_die_offset(topo_info)) |
@@ -165,7 +165,7 @@ static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info,
{
X86CPUTopoIDs topo_ids;
x86_topo_ids_from_idx(topo_info, cpu_index, &topo_ids);
- return apicid_from_topo_ids(topo_info, &topo_ids);
+ return x86_apicid_from_topo_ids(topo_info, &topo_ids);
}
#endif /* HW_I386_TOPOLOGY_H */
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 08/16] hw/386: Add EPYC mode topology decoding functions
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (6 preceding siblings ...)
2020-03-03 19:57 ` [PATCH v5 07/16] hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids Babu Moger
@ 2020-03-03 19:57 ` Babu Moger
2020-03-03 19:57 ` [PATCH v5 09/16] target/i386: Cleanup and use the EPYC mode topology functions Babu Moger
` (9 subsequent siblings)
17 siblings, 0 replies; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:57 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
These functions add support for building EPYC mode topology given the smp
details like numa nodes, cores, threads and sockets.
The new apic id decoding is mostly similar to current apic id decoding
except that it adds a new field node_id when numa configured. Removes all
the hardcoded values. Subsequent patches will use these functions to build
the topology.
Following functions are added.
apicid_llc_width_epyc
apicid_llc_offset_epyc
apicid_pkg_offset_epyc
apicid_from_topo_ids_epyc
x86_topo_ids_from_idx_epyc
x86_topo_ids_from_apicid_epyc
x86_apicid_from_cpu_idx_epyc
The topology details are available in Processor Programming Reference (PPR)
for AMD Family 17h Model 01h, Revision B1 Processors. The revision guides are
available from the bugzilla Link below.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger <babu.moger@amd.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
---
include/hw/i386/topology.h | 100 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index b9593b9905..07239f95f4 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -47,6 +47,7 @@ typedef uint32_t apic_id_t;
typedef struct X86CPUTopoIDs {
unsigned pkg_id;
+ unsigned node_id;
unsigned die_id;
unsigned core_id;
unsigned smt_id;
@@ -88,6 +89,11 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info)
return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
}
+/* Bit width of the node_id field per socket */
+static inline unsigned apicid_node_width_epyc(X86CPUTopoInfo *topo_info)
+{
+ return apicid_bitwidth_for_count(MAX(topo_info->nodes_per_pkg, 1));
+}
/* Bit offset of the Core_ID field
*/
static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
@@ -108,6 +114,100 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
}
+#define NODE_ID_OFFSET 3 /* Minimum node_id offset if numa configured */
+
+/*
+ * Bit offset of the node_id field
+ *
+ * Make sure nodes_per_pkg > 0 if numa configured else zero.
+ */
+static inline unsigned apicid_node_offset_epyc(X86CPUTopoInfo *topo_info)
+{
+ unsigned offset = apicid_die_offset(topo_info) +
+ apicid_die_width(topo_info);
+
+ if (topo_info->nodes_per_pkg) {
+ return MAX(NODE_ID_OFFSET, offset);
+ } else {
+ return offset;
+ }
+}
+
+/* Bit offset of the Pkg_ID (socket ID) field */
+static inline unsigned apicid_pkg_offset_epyc(X86CPUTopoInfo *topo_info)
+{
+ return apicid_node_offset_epyc(topo_info) +
+ apicid_node_width_epyc(topo_info);
+}
+
+/*
+ * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
+ *
+ * The caller must make sure core_id < nr_cores and smt_id < nr_threads.
+ */
+static inline apic_id_t
+x86_apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo_info,
+ const X86CPUTopoIDs *topo_ids)
+{
+ return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) |
+ (topo_ids->node_id << apicid_node_offset_epyc(topo_info)) |
+ (topo_ids->die_id << apicid_die_offset(topo_info)) |
+ (topo_ids->core_id << apicid_core_offset(topo_info)) |
+ topo_ids->smt_id;
+}
+
+static inline void x86_topo_ids_from_idx_epyc(X86CPUTopoInfo *topo_info,
+ unsigned cpu_index,
+ X86CPUTopoIDs *topo_ids)
+{
+ unsigned nr_nodes = MAX(topo_info->nodes_per_pkg, 1);
+ unsigned nr_dies = topo_info->dies_per_pkg;
+ unsigned nr_cores = topo_info->cores_per_die;
+ unsigned nr_threads = topo_info->threads_per_core;
+ unsigned cores_per_node = DIV_ROUND_UP((nr_dies * nr_cores * nr_threads),
+ nr_nodes);
+
+ topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads);
+ topo_ids->node_id = (cpu_index / cores_per_node) % nr_nodes;
+ topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies;
+ topo_ids->core_id = cpu_index / nr_threads % nr_cores;
+ topo_ids->smt_id = cpu_index % nr_threads;
+}
+
+/*
+ * Calculate thread/core/package IDs for a specific topology,
+ * based on APIC ID
+ */
+static inline void x86_topo_ids_from_apicid_epyc(apic_id_t apicid,
+ X86CPUTopoInfo *topo_info,
+ X86CPUTopoIDs *topo_ids)
+{
+ topo_ids->smt_id = apicid &
+ ~(0xFFFFFFFFUL << apicid_smt_width(topo_info));
+ topo_ids->core_id =
+ (apicid >> apicid_core_offset(topo_info)) &
+ ~(0xFFFFFFFFUL << apicid_core_width(topo_info));
+ topo_ids->die_id =
+ (apicid >> apicid_die_offset(topo_info)) &
+ ~(0xFFFFFFFFUL << apicid_die_width(topo_info));
+ topo_ids->node_id =
+ (apicid >> apicid_node_offset_epyc(topo_info)) &
+ ~(0xFFFFFFFFUL << apicid_node_width_epyc(topo_info));
+ topo_ids->pkg_id = apicid >> apicid_pkg_offset_epyc(topo_info);
+}
+
+/*
+ * Make APIC ID for the CPU 'cpu_index'
+ *
+ * 'cpu_index' is a sequential, contiguous ID for the CPU.
+ */
+static inline apic_id_t x86_apicid_from_cpu_idx_epyc(X86CPUTopoInfo *topo_info,
+ unsigned cpu_index)
+{
+ X86CPUTopoIDs topo_ids;
+ x86_topo_ids_from_idx_epyc(topo_info, cpu_index, &topo_ids);
+ return x86_apicid_from_topo_ids_epyc(topo_info, &topo_ids);
+}
/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
*
* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 09/16] target/i386: Cleanup and use the EPYC mode topology functions
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (7 preceding siblings ...)
2020-03-03 19:57 ` [PATCH v5 08/16] hw/386: Add EPYC mode topology decoding functions Babu Moger
@ 2020-03-03 19:57 ` Babu Moger
2020-03-03 19:57 ` [PATCH v5 10/16] hw/i386: Introduce apicid functions inside X86MachineState Babu Moger
` (8 subsequent siblings)
17 siblings, 0 replies; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:57 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
Use the new functions from topology.h and delete the unused code. Given the
sockets, nodes, cores and threads, the new functions generate apic id for EPYC
mode. Removes all the hardcoded values.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
target/i386/cpu.c | 162 +++++++++++------------------------------------------
1 file changed, 35 insertions(+), 127 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 40670f8aca..c75cf744ab 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -338,68 +338,15 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
}
}
-/*
- * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
- * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
- * Define the constants to build the cpu topology. Right now, TOPOEXT
- * feature is enabled only on EPYC. So, these constants are based on
- * EPYC supported configurations. We may need to handle the cases if
- * these values change in future.
- */
-/* Maximum core complexes in a node */
-#define MAX_CCX 2
-/* Maximum cores in a core complex */
-#define MAX_CORES_IN_CCX 4
-/* Maximum cores in a node */
-#define MAX_CORES_IN_NODE 8
-/* Maximum nodes in a socket */
-#define MAX_NODES_PER_SOCKET 4
-
-/*
- * Figure out the number of nodes required to build this config.
- * Max cores in a node is 8
- */
-static int nodes_in_socket(int nr_cores)
-{
- int nodes;
-
- nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
-
- /* Hardware does not support config with 3 nodes, return 4 in that case */
- return (nodes == 3) ? 4 : nodes;
-}
-
-/*
- * Decide the number of cores in a core complex with the given nr_cores using
- * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
- * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
- * L3 cache is shared across all cores in a core complex. So, this will also
- * tell us how many cores are sharing the L3 cache.
- */
-static int cores_in_core_complex(int nr_cores)
-{
- int nodes;
-
- /* Check if we can fit all the cores in one core complex */
- if (nr_cores <= MAX_CORES_IN_CCX) {
- return nr_cores;
- }
- /* Get the number of nodes required to build this config */
- nodes = nodes_in_socket(nr_cores);
-
- /*
- * Divide the cores accros all the core complexes
- * Return rounded up value
- */
- return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
-}
-
/* Encode cache info for CPUID[8000001D] */
-static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
- uint32_t *eax, uint32_t *ebx,
- uint32_t *ecx, uint32_t *edx)
+static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
+ X86CPUTopoInfo *topo_info,
+ uint32_t *eax, uint32_t *ebx,
+ uint32_t *ecx, uint32_t *edx)
{
uint32_t l3_cores;
+ unsigned nodes = MAX(topo_info->nodes_per_pkg, 1);
+
assert(cache->size == cache->line_size * cache->associativity *
cache->partitions * cache->sets);
@@ -408,10 +355,13 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
/* L3 is shared among multiple cores */
if (cache->level == 3) {
- l3_cores = cores_in_core_complex(cs->nr_cores);
- *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
+ l3_cores = DIV_ROUND_UP((topo_info->dies_per_pkg *
+ topo_info->cores_per_die *
+ topo_info->threads_per_core),
+ nodes);
+ *eax |= (l3_cores - 1) << 14;
} else {
- *eax |= ((cs->nr_threads - 1) << 14);
+ *eax |= ((topo_info->threads_per_core - 1) << 14);
}
assert(cache->line_size > 0);
@@ -431,55 +381,17 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
}
-/* Data structure to hold the configuration info for a given core index */
-struct core_topology {
- /* core complex id of the current core index */
- int ccx_id;
- /*
- * Adjusted core index for this core in the topology
- * This can be 0,1,2,3 with max 4 cores in a core complex
- */
- int core_id;
- /* Node id for this core index */
- int node_id;
- /* Number of nodes in this config */
- int num_nodes;
-};
-
-/*
- * Build the configuration closely match the EPYC hardware. Using the EPYC
- * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
- * right now. This could change in future.
- * nr_cores : Total number of cores in the config
- * core_id : Core index of the current CPU
- * topo : Data structure to hold all the config info for this core index
- */
-static void build_core_topology(int nr_cores, int core_id,
- struct core_topology *topo)
-{
- int nodes, cores_in_ccx;
-
- /* First get the number of nodes required */
- nodes = nodes_in_socket(nr_cores);
-
- cores_in_ccx = cores_in_core_complex(nr_cores);
-
- topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
- topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
- topo->core_id = core_id % cores_in_ccx;
- topo->num_nodes = nodes;
-}
-
/* Encode cache info for CPUID[8000001E] */
-static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
+static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *cpu,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
- struct core_topology topo = {0};
- unsigned long nodes;
+ X86CPUTopoIDs topo_ids = {0};
+ unsigned long nodes = MAX(topo_info->nodes_per_pkg, 1);
int shift;
- build_core_topology(cs->nr_cores, cpu->core_id, &topo);
+ x86_topo_ids_from_apicid_epyc(cpu->apic_id, topo_info, &topo_ids);
+
*eax = cpu->apic_id;
/*
* CPUID_Fn8000001E_EBX
@@ -496,12 +408,8 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
* 3 Core complex id
* 1:0 Core id
*/
- if (cs->nr_threads - 1) {
- *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
- (topo.ccx_id << 2) | topo.core_id;
- } else {
- *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
- }
+ *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.node_id << 3) |
+ (topo_ids.core_id);
/*
* CPUID_Fn8000001E_ECX
* 31:11 Reserved
@@ -510,9 +418,9 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
* 2 Socket id
* 1:0 Node id
*/
- if (topo.num_nodes <= 4) {
- *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
- topo.node_id;
+
+ if (nodes <= 4) {
+ *ecx = ((nodes - 1) << 8) | (topo_ids.pkg_id << 2) | topo_ids.node_id;
} else {
/*
* Node id fix up. Actual hardware supports up to 4 nodes. But with
@@ -527,10 +435,10 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
* number of nodes. find_last_bit returns last set bit(0 based). Left
* shift(+1) the socket id to represent all the nodes.
*/
- nodes = topo.num_nodes - 1;
+ nodes -= 1;
shift = find_last_bit(&nodes, 8);
- *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
- topo.node_id;
+ *ecx = (nodes << 8) | (topo_ids.pkg_id << (shift + 1)) |
+ topo_ids.node_id;
}
*edx = 0;
}
@@ -5371,6 +5279,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
uint32_t signature[3];
X86CPUTopoInfo topo_info;
+ topo_info.nodes_per_pkg = env->nr_nodes;
topo_info.dies_per_pkg = env->nr_dies;
topo_info.cores_per_die = cs->nr_cores;
topo_info.threads_per_core = cs->nr_threads;
@@ -5790,20 +5699,20 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
}
switch (count) {
case 0: /* L1 dcache info */
- encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
- eax, ebx, ecx, edx);
+ encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
+ &topo_info, eax, ebx, ecx, edx);
break;
case 1: /* L1 icache info */
- encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
- eax, ebx, ecx, edx);
+ encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
+ &topo_info, eax, ebx, ecx, edx);
break;
case 2: /* L2 cache info */
- encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
- eax, ebx, ecx, edx);
+ encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
+ &topo_info, eax, ebx, ecx, edx);
break;
case 3: /* L3 cache info */
- encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
- eax, ebx, ecx, edx);
+ encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
+ &topo_info, eax, ebx, ecx, edx);
break;
default: /* end of info */
*eax = *ebx = *ecx = *edx = 0;
@@ -5812,8 +5721,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
break;
case 0x8000001E:
assert(cpu->core_id <= 255);
- encode_topo_cpuid8000001e(cs, cpu,
- eax, ebx, ecx, edx);
+ encode_topo_cpuid8000001e(&topo_info, cpu, eax, ebx, ecx, edx);
break;
case 0xC0000000:
*eax = env->cpuid_xlevel2;
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 10/16] hw/i386: Introduce apicid functions inside X86MachineState
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (8 preceding siblings ...)
2020-03-03 19:57 ` [PATCH v5 09/16] target/i386: Cleanup and use the EPYC mode topology functions Babu Moger
@ 2020-03-03 19:57 ` Babu Moger
2020-03-09 14:34 ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 11/16] target/i386: Load apicid model specific handlers from X86CPUDefinition Babu Moger
` (7 subsequent siblings)
17 siblings, 1 reply; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:57 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
Introduce model specific apicid functions inside X86MachineState.
These functions will be loaded from X86CPUDefinition.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
hw/i386/x86.c | 5 +++++
include/hw/i386/x86.h | 9 +++++++++
2 files changed, 14 insertions(+)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 929b80c9c7..15b7815bb0 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -911,6 +911,11 @@ static void x86_machine_initfn(Object *obj)
x86ms->smm = ON_OFF_AUTO_AUTO;
x86ms->max_ram_below_4g = 0; /* use default */
x86ms->smp_dies = 1;
+
+ x86ms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx;
+ x86ms->topo_ids_from_apicid = x86_topo_ids_from_apicid;
+ x86ms->apicid_from_topo_ids = x86_apicid_from_topo_ids;
+ x86ms->apicid_pkg_offset = apicid_pkg_offset;
}
static void x86_machine_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index 22babcb3bb..2643b57629 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -65,6 +65,15 @@ typedef struct {
OnOffAuto smm;
+ /* Apic id specific handlers */
+ uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info,
+ unsigned cpu_index);
+ void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_info,
+ X86CPUTopoIDs *topo_ids);
+ apic_id_t (*apicid_from_topo_ids)(X86CPUTopoInfo *topo_info,
+ const X86CPUTopoIDs *topo_ids);
+ uint32_t (*apicid_pkg_offset)(X86CPUTopoInfo *topo_info);
+
/*
* Address space used by IOAPIC device. All IOAPIC interrupts
* will be translated to MSI messages in the address space.
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 11/16] target/i386: Load apicid model specific handlers from X86CPUDefinition
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (9 preceding siblings ...)
2020-03-03 19:57 ` [PATCH v5 10/16] hw/i386: Introduce apicid functions inside X86MachineState Babu Moger
@ 2020-03-03 19:58 ` Babu Moger
2020-03-09 14:49 ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 12/16] hw/i386: Use the apicid handlers from X86MachineState Babu Moger
` (6 subsequent siblings)
17 siblings, 1 reply; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:58 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
Load the model specific handlers if available or else default handlers
will be loaded. Add the model specific handlers if apicid decoding
differs from the standard sequential numbering.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
target/i386/cpu.c | 34 ++++++++++++++++++++++++++++++++++
target/i386/cpu.h | 1 +
2 files changed, 35 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c75cf744ab..f33d8b77f5 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -51,6 +51,7 @@
#include "sysemu/sysemu.h"
#include "sysemu/tcg.h"
#include "hw/qdev-properties.h"
+#include "hw/i386/x86.h"
#include "hw/i386/topology.h"
#ifndef CONFIG_USER_ONLY
#include "exec/address-spaces.h"
@@ -1614,6 +1615,16 @@ typedef struct X86CPUDefinition {
FeatureWordArray features;
const char *model_id;
CPUCaches *cache_info;
+
+ /* Apic id specific handlers */
+ uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info,
+ unsigned cpu_index);
+ void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_info,
+ X86CPUTopoIDs *topo_ids);
+ apic_id_t (*apicid_from_topo_ids)(X86CPUTopoInfo *topo_info,
+ const X86CPUTopoIDs *topo_ids);
+ uint32_t (*apicid_pkg_offset)(X86CPUTopoInfo *topo_info);
+
/*
* Definitions for alternative versions of CPU model.
* List is terminated by item with version == 0.
@@ -1654,6 +1665,29 @@ static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition
return def->versions ?: default_version_list;
}
+void cpu_x86_init_apicid_fns(MachineState *machine)
+{
+ X86CPUClass *xcc = X86_CPU_CLASS(object_class_by_name(machine->cpu_type));
+ X86CPUModel *model = xcc->model;
+ X86CPUDefinition *def = model->cpudef;
+ X86MachineState *x86ms = X86_MACHINE(machine);
+
+ if (def) {
+ if (def->apicid_from_cpu_idx) {
+ x86ms->apicid_from_cpu_idx = def->apicid_from_cpu_idx;
+ }
+ if (def->topo_ids_from_apicid) {
+ x86ms->topo_ids_from_apicid = def->topo_ids_from_apicid;
+ }
+ if (def->apicid_from_topo_ids) {
+ x86ms->apicid_from_topo_ids = def->apicid_from_topo_ids;
+ }
+ if (def->apicid_pkg_offset) {
+ x86ms->apicid_pkg_offset = def->apicid_pkg_offset;
+ }
+ }
+}
+
static CPUCaches epyc_cache_info = {
.l1d_cache = &(CPUCacheInfo) {
.type = DATA_CACHE,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 20abbda647..34f0d994ef 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1895,6 +1895,7 @@ void cpu_clear_apic_feature(CPUX86State *env);
void host_cpuid(uint32_t function, uint32_t count,
uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
+void cpu_x86_init_apicid_fns(MachineState *machine);
/* helper.c */
bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 12/16] hw/i386: Use the apicid handlers from X86MachineState
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (10 preceding siblings ...)
2020-03-03 19:58 ` [PATCH v5 11/16] target/i386: Load apicid model specific handlers from X86CPUDefinition Babu Moger
@ 2020-03-03 19:58 ` Babu Moger
2020-03-09 15:01 ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 13/16] target/i386: Add EPYC model specific handlers Babu Moger
` (5 subsequent siblings)
17 siblings, 1 reply; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:58 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
Check and Load the apicid handlers from X86CPUDefinition if available.
Update the calling convention for the apicid handlers.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
hw/i386/pc.c | 6 +++---
hw/i386/x86.c | 11 +++++++----
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 17cce3f074..c600ba0432 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1581,14 +1581,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
topo_ids.die_id = cpu->die_id;
topo_ids.core_id = cpu->core_id;
topo_ids.smt_id = cpu->thread_id;
- cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids);
+ cpu->apic_id = x86ms->apicid_from_topo_ids(&topo_info, &topo_ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
if (!cpu_slot) {
MachineState *ms = MACHINE(pcms);
- x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
+ x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
error_setg(errp,
"Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
" APIC ID %" PRIu32 ", valid index range 0:%d",
@@ -1609,7 +1609,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
/* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
* once -smp refactoring is complete and there will be CPU private
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
- x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
+ x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 15b7815bb0..d46dd4ad9e 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -86,7 +86,7 @@ uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
init_topo_info(&topo_info, x86ms);
- correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index);
+ correct_id = x86ms->apicid_from_cpu_idx(&topo_info, cpu_index);
if (x86mc->compat_apic_id_mode) {
if (cpu_index != correct_id && !warned && !qtest_enabled()) {
error_report("APIC IDs set in compatibility mode, "
@@ -158,8 +158,8 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
init_topo_info(&topo_info, x86ms);
assert(idx < ms->possible_cpus->len);
- x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
- &topo_info, &topo_ids);
+ x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
+ &topo_info, &topo_ids);
return topo_ids.pkg_id % ms->numa_state->num_nodes;
}
@@ -179,6 +179,9 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
return ms->possible_cpus;
}
+ /* Initialize apicid handlers */
+ cpu_x86_init_apicid_fns(ms);
+
ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
sizeof(CPUArchId) * max_cpus);
ms->possible_cpus->len = max_cpus;
@@ -192,7 +195,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus->cpus[i].vcpus_count = 1;
ms->possible_cpus->cpus[i].arch_id =
x86_cpu_apic_id_from_index(x86ms, i);
- x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
+ x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
&topo_info, &topo_ids);
ms->possible_cpus->cpus[i].props.has_socket_id = true;
ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 13/16] target/i386: Add EPYC model specific handlers
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (11 preceding siblings ...)
2020-03-03 19:58 ` [PATCH v5 12/16] hw/i386: Use the apicid handlers from X86MachineState Babu Moger
@ 2020-03-03 19:58 ` Babu Moger
2020-03-09 15:03 ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 14/16] hw/i386: Move arch_id decode inside x86_cpus_init Babu Moger
` (4 subsequent siblings)
17 siblings, 1 reply; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:58 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
Add the new EPYC model specific handlers to fix the apicid decoding.
The APIC ID is decoded based on the sequence sockets->dies->cores->threads.
This works fine for most standard AMD and other vendors' configurations,
but this decoding sequence does not follow that of AMD's APIC ID enumeration
strictly. In some cases this can cause CPU topology inconsistency.
When booting a guest VM, the kernel tries to validate the topology, and finds
it inconsistent with the enumeration of EPYC cpu models. The more details are
in the bug https://bugzilla.redhat.com/show_bug.cgi?id=1728166.
To fix the problem we need to build the topology as per the Processor
Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
Processors.
It is available at https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip
Here is the text from the PPR.
Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
number of least significant bits in the Initial APIC ID that indicate core ID
within a processor, in constructing per-core CPUID masks.
Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
(MNC) that the processor could theoretically support, not the actual number of
cores that are actually implemented or enabled on the processor, as indicated
by Core::X86::Cpuid::SizeId[NC].
Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
• ApicId[6] = Socket ID.
• ApicId[5:4] = Node ID.
• ApicId[3] = Logical CCX L3 complex ID
• ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
target/i386/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f33d8b77f5..f870f7c55b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3884,6 +3884,10 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8000001E,
.model_id = "AMD EPYC Processor",
.cache_info = &epyc_cache_info,
+ .apicid_from_cpu_idx = x86_apicid_from_cpu_idx_epyc,
+ .topo_ids_from_apicid = x86_topo_ids_from_apicid_epyc,
+ .apicid_from_topo_ids = x86_apicid_from_topo_ids_epyc,
+ .apicid_pkg_offset = apicid_pkg_offset_epyc,
.versions = (X86CPUVersionDefinition[]) {
{ .version = 1 },
{
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 14/16] hw/i386: Move arch_id decode inside x86_cpus_init
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (12 preceding siblings ...)
2020-03-03 19:58 ` [PATCH v5 13/16] target/i386: Add EPYC model specific handlers Babu Moger
@ 2020-03-03 19:58 ` Babu Moger
2020-03-09 15:21 ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 15/16] i386: Fix pkg_id offset for EPYC cpu models Babu Moger
` (3 subsequent siblings)
17 siblings, 1 reply; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:58 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
Apicid calculation depends on knowing the total number of numa nodes
for EPYC cpu models. Right now, we are calculating the arch_id while
parsing the numa(parse_numa). At this time, it is not known how many
total numa nodes are configured in the system.
Move the arch_id inside x86_cpus_init. At this time smp parameter is already
completed and numa node information is available.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
hw/i386/x86.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index d46dd4ad9e..66998b065c 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -121,6 +121,9 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
MachineState *ms = MACHINE(x86ms);
MachineClass *mc = MACHINE_GET_CLASS(x86ms);
+ /* Initialize apicid handlers first */
+ cpu_x86_init_apicid_fns(ms);
+
x86_cpu_set_default_version(default_cpu_version);
/*
@@ -134,6 +137,12 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms,
ms->smp.max_cpus - 1) + 1;
possible_cpus = mc->possible_cpu_arch_ids(ms);
+
+ for (i = 0; i < ms->smp.cpus; i++) {
+ ms->possible_cpus->cpus[i].arch_id =
+ x86_cpu_apic_id_from_index(x86ms, i);
+ }
+
for (i = 0; i < ms->smp.cpus; i++) {
x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal);
}
@@ -158,8 +167,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
init_topo_info(&topo_info, x86ms);
assert(idx < ms->possible_cpus->len);
- x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
- &topo_info, &topo_ids);
+ x86_topo_ids_from_idx(&topo_info, idx, &topo_ids);
return topo_ids.pkg_id % ms->numa_state->num_nodes;
}
@@ -193,10 +201,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus->cpus[i].type = ms->cpu_type;
ms->possible_cpus->cpus[i].vcpus_count = 1;
- ms->possible_cpus->cpus[i].arch_id =
- x86_cpu_apic_id_from_index(x86ms, i);
- x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
- &topo_info, &topo_ids);
+ x86_topo_ids_from_idx(&topo_info, i, &topo_ids);
ms->possible_cpus->cpus[i].props.has_socket_id = true;
ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
if (x86ms->smp_dies > 1) {
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 15/16] i386: Fix pkg_id offset for EPYC cpu models
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (13 preceding siblings ...)
2020-03-03 19:58 ` [PATCH v5 14/16] hw/i386: Move arch_id decode inside x86_cpus_init Babu Moger
@ 2020-03-03 19:58 ` Babu Moger
2020-03-09 15:22 ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 16/16] tests: Update the Unit tests Babu Moger
` (2 subsequent siblings)
17 siblings, 1 reply; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:58 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
If the system is numa configured the pkg_offset needs
to be adjusted for EPYC cpu models. Fix it calling the
model specific handler.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
hw/i386/pc.c | 1 +
target/i386/cpu.c | 4 ++--
target/i386/cpu.h | 1 +
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index c600ba0432..b6237a3a14 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1527,6 +1527,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
env->nr_dies = x86ms->smp_dies;
env->nr_nodes = topo_info.nodes_per_pkg;
+ env->pkg_offset = x86ms->apicid_pkg_offset(&topo_info);
/*
* If APIC ID is not set,
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f870f7c55b..9b160cbdd1 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5503,7 +5503,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
- *eax = apicid_pkg_offset(&topo_info);
+ *eax = env->pkg_offset;
*ebx = cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
@@ -5537,7 +5537,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
case 2:
- *eax = apicid_pkg_offset(&topo_info);
+ *eax = env->pkg_offset;
*ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
break;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 34f0d994ef..aac86af5cf 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1608,6 +1608,7 @@ typedef struct CPUX86State {
unsigned nr_dies;
unsigned nr_nodes;
+ unsigned pkg_offset;
} CPUX86State;
struct kvm_msrs;
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 16/16] tests: Update the Unit tests
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (14 preceding siblings ...)
2020-03-03 19:58 ` [PATCH v5 15/16] i386: Fix pkg_id offset for EPYC cpu models Babu Moger
@ 2020-03-03 19:58 ` Babu Moger
2020-03-10 23:06 ` Eduardo Habkost
2020-03-08 13:25 ` [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Michael S. Tsirkin
2020-03-10 8:40 ` Igor Mammedov
17 siblings, 1 reply; 45+ messages in thread
From: Babu Moger @ 2020-03-03 19:58 UTC (permalink / raw)
To: ehabkost, marcel.apfelbaum, pbonzini, rth, mst, imammedo; +Cc: qemu-devel
Since the topology routines have changed, update
the unit tests to use the new APIs.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
tests/test-x86-cpuid.c | 115 ++++++++++++++++++++++++++++--------------------
1 file changed, 68 insertions(+), 47 deletions(-)
diff --git a/tests/test-x86-cpuid.c b/tests/test-x86-cpuid.c
index 1942287f33..00553c1d77 100644
--- a/tests/test-x86-cpuid.c
+++ b/tests/test-x86-cpuid.c
@@ -28,79 +28,100 @@
static void test_topo_bits(void)
{
+ X86CPUTopoInfo topo_info = {0};
+
/* simple tests for 1 thread per core, 1 core per die, 1 die per package */
- g_assert_cmpuint(apicid_smt_width(1, 1, 1), ==, 0);
- g_assert_cmpuint(apicid_core_width(1, 1, 1), ==, 0);
- g_assert_cmpuint(apicid_die_width(1, 1, 1), ==, 0);
+ topo_info = (X86CPUTopoInfo) {0, 1, 1, 1};
+ g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 0);
+ g_assert_cmpuint(apicid_core_width(&topo_info), ==, 0);
+ g_assert_cmpuint(apicid_die_width(&topo_info), ==, 0);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 0), ==, 0);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 1), ==, 1);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 2), ==, 2);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 3), ==, 3);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 0), ==, 0);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), ==, 1);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), ==, 2);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 3), ==, 3);
/* Test field width calculation for multiple values
*/
- g_assert_cmpuint(apicid_smt_width(1, 1, 2), ==, 1);
- g_assert_cmpuint(apicid_smt_width(1, 1, 3), ==, 2);
- g_assert_cmpuint(apicid_smt_width(1, 1, 4), ==, 2);
-
- g_assert_cmpuint(apicid_smt_width(1, 1, 14), ==, 4);
- g_assert_cmpuint(apicid_smt_width(1, 1, 15), ==, 4);
- g_assert_cmpuint(apicid_smt_width(1, 1, 16), ==, 4);
- g_assert_cmpuint(apicid_smt_width(1, 1, 17), ==, 5);
-
-
- g_assert_cmpuint(apicid_core_width(1, 30, 2), ==, 5);
- g_assert_cmpuint(apicid_core_width(1, 31, 2), ==, 5);
- g_assert_cmpuint(apicid_core_width(1, 32, 2), ==, 5);
- g_assert_cmpuint(apicid_core_width(1, 33, 2), ==, 6);
-
- g_assert_cmpuint(apicid_die_width(1, 30, 2), ==, 0);
- g_assert_cmpuint(apicid_die_width(2, 30, 2), ==, 1);
- g_assert_cmpuint(apicid_die_width(3, 30, 2), ==, 2);
- g_assert_cmpuint(apicid_die_width(4, 30, 2), ==, 2);
+ topo_info = (X86CPUTopoInfo) {0, 1, 1, 2};
+ g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 1);
+ topo_info = (X86CPUTopoInfo) {0, 1, 1, 3};
+ g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 2);
+ topo_info = (X86CPUTopoInfo) {0, 1, 1, 4};
+ g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 2);
+
+ topo_info = (X86CPUTopoInfo) {0, 1, 1, 14};
+ g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 4);
+ topo_info = (X86CPUTopoInfo) {0, 1, 1, 15};
+ g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 4);
+ topo_info = (X86CPUTopoInfo) {0, 1, 1, 16};
+ g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 4);
+ topo_info = (X86CPUTopoInfo) {0, 1, 1, 17};
+ g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 5);
+
+
+ topo_info = (X86CPUTopoInfo) {0, 1, 30, 2};
+ g_assert_cmpuint(apicid_core_width(&topo_info), ==, 5);
+ topo_info = (X86CPUTopoInfo) {0, 1, 31, 2};
+ g_assert_cmpuint(apicid_core_width(&topo_info), ==, 5);
+ topo_info = (X86CPUTopoInfo) {0, 1, 32, 2};
+ g_assert_cmpuint(apicid_core_width(&topo_info), ==, 5);
+ topo_info = (X86CPUTopoInfo) {0, 1, 33, 2};
+ g_assert_cmpuint(apicid_core_width(&topo_info), ==, 6);
+
+ topo_info = (X86CPUTopoInfo) {0, 1, 30, 2};
+ g_assert_cmpuint(apicid_die_width(&topo_info), ==, 0);
+ topo_info = (X86CPUTopoInfo) {0, 2, 30, 2};
+ g_assert_cmpuint(apicid_die_width(&topo_info), ==, 1);
+ topo_info = (X86CPUTopoInfo) {0, 3, 30, 2};
+ g_assert_cmpuint(apicid_die_width(&topo_info), ==, 2);
+ topo_info = (X86CPUTopoInfo) {0, 4, 30, 2};
+ g_assert_cmpuint(apicid_die_width(&topo_info), ==, 2);
/* build a weird topology and see if IDs are calculated correctly
*/
/* This will use 2 bits for thread ID and 3 bits for core ID
*/
- g_assert_cmpuint(apicid_smt_width(1, 6, 3), ==, 2);
- g_assert_cmpuint(apicid_core_offset(1, 6, 3), ==, 2);
- g_assert_cmpuint(apicid_die_offset(1, 6, 3), ==, 5);
- g_assert_cmpuint(apicid_pkg_offset(1, 6, 3), ==, 5);
-
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 0), ==, 0);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1), ==, 1);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2), ==, 2);
-
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 0), ==,
+ topo_info = (X86CPUTopoInfo) {0, 1, 6, 3};
+ g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 2);
+ g_assert_cmpuint(apicid_core_offset(&topo_info), ==, 2);
+ g_assert_cmpuint(apicid_die_offset(&topo_info), ==, 5);
+ g_assert_cmpuint(apicid_pkg_offset(&topo_info), ==, 5);
+
+ topo_info = (X86CPUTopoInfo) {0, 1, 6, 3};
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 0), ==, 0);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), ==, 1);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), ==, 2);
+
+ topo_info = (X86CPUTopoInfo) {0, 1, 6, 3};
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 0), ==,
(1 << 2) | 0);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 1), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 1), ==,
(1 << 2) | 1);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 2), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 2), ==,
(1 << 2) | 2);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 0), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2 * 3 + 0), ==,
(2 << 2) | 0);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 1), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2 * 3 + 1), ==,
(2 << 2) | 1);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 2), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2 * 3 + 2), ==,
(2 << 2) | 2);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 0), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 5 * 3 + 0), ==,
(5 << 2) | 0);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 1), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 5 * 3 + 1), ==,
(5 << 2) | 1);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 2), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 5 * 3 + 2), ==,
(5 << 2) | 2);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info,
1 * 6 * 3 + 0 * 3 + 0), ==, (1 << 5));
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info,
1 * 6 * 3 + 1 * 3 + 1), ==, (1 << 5) | (1 << 2) | 1);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info,
3 * 6 * 3 + 5 * 3 + 2), ==, (3 << 5) | (5 << 2) | 2);
}
^ permalink raw reply related [flat|nested] 45+ messages in thread
* Re: [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (15 preceding siblings ...)
2020-03-03 19:58 ` [PATCH v5 16/16] tests: Update the Unit tests Babu Moger
@ 2020-03-08 13:25 ` Michael S. Tsirkin
2020-03-09 17:50 ` Babu Moger
2020-03-10 8:40 ` Igor Mammedov
17 siblings, 1 reply; 45+ messages in thread
From: Michael S. Tsirkin @ 2020-03-08 13:25 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, qemu-devel, imammedo, pbonzini, rth
On Tue, Mar 03, 2020 at 01:56:51PM -0600, Babu Moger wrote:
> This series fixes APIC ID encoding problem reported on AMD EPYC cpu models.
> https://bugzilla.redhat.com/show_bug.cgi?id=1728166
>
> Currently, the APIC ID is decoded based on the sequence
> sockets->dies->cores->threads. This works for most standard AMD and other
> vendors' configurations, but this decoding sequence does not follow that of
> AMD's APIC ID enumeration strictly. In some cases this can cause CPU topology
> inconsistency. When booting a guest VM, the kernel tries to validate the
> topology, and finds it inconsistent with the enumeration of EPYC cpu models.
>
> To fix the problem we need to build the topology as per the Processor
> Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
> Processors. The documentation is available from the bugzilla Link below.
>
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
>
> Here is the text from the PPR.
> Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
> number of least significant bits in the Initial APIC ID that indicate core ID
> within a processor, in constructing per-core CPUID masks.
> Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
> (MNC) that the processor could theoretically support, not the actual number of
> cores that are actually implemented or enabled on the processor, as indicated
> by Core::X86::Cpuid::SizeId[NC].
> Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
> • ApicId[6] = Socket ID.
> • ApicId[5:4] = Node ID.
> • ApicId[3] = Logical CCX L3 complex ID
> • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
Looks reasonable:
Acked-by: Michael S. Tsirkin <mst@redhat.com>
belongs in Eduardo's tree I guess.
> v5:
> Generated the patches on top of git://github.com/ehabkost/qemu.git (x86-next).
> Changes from v4.
> 1. Re-arranged the patches 2 and 4 as suggested by Igor.
> 2. Kept the apicid handler functions inside X86MachineState as discussed.
> These handlers are loaded from X86CPUDefinitions.
> 3. Removed unnecessary X86CPUstate initialization from x86_cpu_new. Suggested
> by Igor.
> 4. And other minor changes related to patch format.
>
> v4:
> https://lore.kernel.org/qemu-devel/158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com/
> Changes from v3.
> 1. Moved the arch_id calculation inside the function x86_cpus_init. With this change,
> we dont need to change common numa code.(suggested by Igor)
> 2. Introduced the model specific handlers inside X86CPUDefinitions.
> These handlers are loaded into X86MachineState during the init.
> 3. Removed llc_id from x86CPU.
> 4. Removed init_apicid_fn hanlder from MachineClass. Kept all the code changes
> inside the x86.
> 5. Added new handler function apicid_pkg_offset for pkg_offset calculation.
> 6. And some Other minor changes.
>
> v3:
> https://lore.kernel.org/qemu-devel/157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com/
> 1. Consolidated the topology information in structure X86CPUTopoInfo.
> 2. Changed the ccx_id to llc_id as commented by upstream.
> 3. Generalized the apic id decoding. It is mostly similar to current apic id
> except that it adds new field llc_id when numa configured. Removes all the
> hardcoded values.
> 4. Removed the earlier parse_numa split. And moved the numa node initialization
> inside the numa_complete_configuration. This is bit cleaner as commented by
> Eduardo.
> 5. Added new function init_apicid_fn inside machine_class structure. This
> will be used to update the apic id handler specific to cpu model.
> 6. Updated the cpuid unit tests.
> 7. TODO : Need to figure out how to dynamically update the handlers using cpu models.
> I might some guidance on that.
>
> v2:
> https://lore.kernel.org/qemu-devel/156779689013.21957.1631551572950676212.stgit@localhost.localdomain/
> 1. Introduced the new property epyc to enable new epyc mode.
> 2. Separated the epyc mode and non epyc mode function.
> 3. Introduced function pointers in PCMachineState to handle the
> differences.
> 4. Mildly tested different combinations to make things are working as expected.
> 5. TODO : Setting the epyc feature bit needs to be worked out. This feature is
> supported only on AMD EPYC models. I may need some guidance on that.
>
> v1:
> https://lore.kernel.org/qemu-devel/20190731232032.51786-1-babu.moger@amd.com/
>
> ---
>
> Babu Moger (16):
> hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
> hw/i386: Introduce X86CPUTopoInfo to contain topology info
> hw/i386: Consolidate topology functions
> machine: Add SMP Sockets in CpuTopology
> hw/i386: Remove unnecessary initialization in x86_cpu_new
> hw/i386: Update structures to save the number of nodes per package
> hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids
> hw/386: Add EPYC mode topology decoding functions
> target/i386: Cleanup and use the EPYC mode topology functions
> hw/i386: Introduce apicid functions inside X86MachineState
> target/i386: Load apicid model specific handlers from X86CPUDefinition
> hw/i386: Use the apicid handlers from X86MachineState
> target/i386: Add EPYC model specific handlers
> hw/i386: Move arch_id decode inside x86_cpus_init
> i386: Fix pkg_id offset for EPYC cpu models
> tests: Update the Unit tests
>
>
> hw/core/machine.c | 1
> hw/i386/pc.c | 54 ++++++-----
> hw/i386/x86.c | 72 ++++++++++----
> include/hw/boards.h | 2
> include/hw/i386/topology.h | 215 ++++++++++++++++++++++++++++++------------
> include/hw/i386/x86.h | 12 ++
> target/i386/cpu.c | 224 +++++++++++++++++---------------------------
> target/i386/cpu.h | 3 +
> tests/test-x86-cpuid.c | 115 +++++++++++++----------
> vl.c | 1
> 10 files changed, 403 insertions(+), 296 deletions(-)
>
> --
> Signature
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 02/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info
2020-03-03 19:57 ` [PATCH v5 02/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info Babu Moger
@ 2020-03-09 14:10 ` Igor Mammedov
2020-03-10 23:04 ` Eduardo Habkost
1 sibling, 0 replies; 45+ messages in thread
From: Igor Mammedov @ 2020-03-09 14:10 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On Tue, 03 Mar 2020 13:57:05 -0600
Babu Moger <babu.moger@amd.com> wrote:
> This is an effort to re-arrange few data structure for better readability.
>
> 1. Add X86CPUTopoInfo which will have all the topology informations
> required to build the cpu topology. There is no functional changes.
> 2. Introduce init_topo_info to initialize X86CPUTopoInfo members from
> X86MachineState.
>
> There is no functional changes.
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
> hw/i386/pc.c | 12 ++++++------
> hw/i386/x86.c | 32 ++++++++++++++++++++++++--------
> include/hw/i386/topology.h | 38 ++++++++++++++++++++++++--------------
> include/hw/i386/x86.h | 3 +++
> 4 files changed, 57 insertions(+), 28 deletions(-)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 715f79f58c..ef23ae2af5 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -1514,6 +1514,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
> X86MachineState *x86ms = X86_MACHINE(pcms);
> unsigned int smp_cores = ms->smp.cores;
> unsigned int smp_threads = ms->smp.threads;
> + X86CPUTopoInfo topo_info;
>
> if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
> error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
> @@ -1521,6 +1522,8 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
> return;
> }
>
> + init_topo_info(&topo_info, x86ms);
> +
> env->nr_dies = x86ms->smp_dies;
>
> /*
> @@ -1576,16 +1579,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
> topo_ids.die_id = cpu->die_id;
> topo_ids.core_id = cpu->core_id;
> topo_ids.smt_id = cpu->thread_id;
> - cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,
> - smp_threads, &topo_ids);
> + cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids);
> }
>
> cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
> if (!cpu_slot) {
> MachineState *ms = MACHINE(pcms);
>
> - x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
> - smp_cores, smp_threads, &topo_ids);
> + x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
> error_setg(errp,
> "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
> " APIC ID %" PRIu32 ", valid index range 0:%d",
> @@ -1606,8 +1607,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
> /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
> * once -smp refactoring is complete and there will be CPU private
> * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
> - x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
> - smp_cores, smp_threads, &topo_ids);
> + x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
> if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
> error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
> " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
> index 322fb6abbc..03b8962c98 100644
> --- a/hw/i386/x86.c
> +++ b/hw/i386/x86.c
> @@ -57,6 +57,16 @@
> /* Physical Address of PVH entry point read from kernel ELF NOTE */
> static size_t pvh_start_addr;
>
> +inline void init_topo_info(X86CPUTopoInfo *topo_info,
> + const X86MachineState *x86ms)
> +{
> + MachineState *ms = MACHINE(x86ms);
> +
> + topo_info->dies_per_pkg = x86ms->smp_dies;
> + topo_info->cores_per_die = ms->smp.cores;
> + topo_info->threads_per_core = ms->smp.threads;
> +}
> +
> /*
> * Calculates initial APIC ID for a specific CPU index
> *
> @@ -68,13 +78,14 @@ static size_t pvh_start_addr;
> uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
> unsigned int cpu_index)
> {
> - MachineState *ms = MACHINE(x86ms);
> X86MachineClass *x86mc = X86_MACHINE_GET_CLASS(x86ms);
> + X86CPUTopoInfo topo_info;
> uint32_t correct_id;
> static bool warned;
>
> - correct_id = x86_apicid_from_cpu_idx(x86ms->smp_dies, ms->smp.cores,
> - ms->smp.threads, cpu_index);
> + init_topo_info(&topo_info, x86ms);
> +
> + correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index);
> if (x86mc->compat_apic_id_mode) {
> if (cpu_index != correct_id && !warned && !qtest_enabled()) {
> error_report("APIC IDs set in compatibility mode, "
> @@ -145,19 +156,22 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
> {
> X86CPUTopoIDs topo_ids;
> X86MachineState *x86ms = X86_MACHINE(ms);
> + X86CPUTopoInfo topo_info;
> +
> + init_topo_info(&topo_info, x86ms);
>
> assert(idx < ms->possible_cpus->len);
> x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
> - x86ms->smp_dies, ms->smp.cores,
> - ms->smp.threads, &topo_ids);
> + &topo_info, &topo_ids);
> return topo_ids.pkg_id % ms->numa_state->num_nodes;
> }
>
> const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
> {
> X86MachineState *x86ms = X86_MACHINE(ms);
> - int i;
> unsigned int max_cpus = ms->smp.max_cpus;
> + X86CPUTopoInfo topo_info;
> + int i;
>
> if (ms->possible_cpus) {
> /*
> @@ -171,6 +185,9 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
> ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
> sizeof(CPUArchId) * max_cpus);
> ms->possible_cpus->len = max_cpus;
> +
> + init_topo_info(&topo_info, x86ms);
> +
> for (i = 0; i < ms->possible_cpus->len; i++) {
> X86CPUTopoIDs topo_ids;
>
> @@ -179,8 +196,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
> ms->possible_cpus->cpus[i].arch_id =
> x86_cpu_apic_id_from_index(x86ms, i);
> x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
> - x86ms->smp_dies, ms->smp.cores,
> - ms->smp.threads, &topo_ids);
> + &topo_info, &topo_ids);
> ms->possible_cpus->cpus[i].props.has_socket_id = true;
> ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
> if (x86ms->smp_dies > 1) {
> diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
> index 52def68610..7ea507f376 100644
> --- a/include/hw/i386/topology.h
> +++ b/include/hw/i386/topology.h
> @@ -52,6 +52,12 @@ typedef struct X86CPUTopoIDs {
> unsigned smt_id;
> } X86CPUTopoIDs;
>
> +typedef struct X86CPUTopoInfo {
> + unsigned dies_per_pkg;
> + unsigned cores_per_die;
> + unsigned threads_per_core;
> +} X86CPUTopoInfo;
> +
> /* Return the bit width needed for 'count' IDs
> */
> static unsigned apicid_bitwidth_for_count(unsigned count)
> @@ -119,11 +125,13 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies,
> *
> * The caller must make sure core_id < nr_cores and smt_id < nr_threads.
> */
> -static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies,
> - unsigned nr_cores,
> - unsigned nr_threads,
> +static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
> const X86CPUTopoIDs *topo_ids)
> {
> + unsigned nr_dies = topo_info->dies_per_pkg;
> + unsigned nr_cores = topo_info->cores_per_die;
> + unsigned nr_threads = topo_info->threads_per_core;
> +
> return (topo_ids->pkg_id <<
> apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) |
> (topo_ids->die_id <<
> @@ -136,12 +144,14 @@ static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies,
> /* Calculate thread/core/package IDs for a specific topology,
> * based on (contiguous) CPU index
> */
> -static inline void x86_topo_ids_from_idx(unsigned nr_dies,
> - unsigned nr_cores,
> - unsigned nr_threads,
> +static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info,
> unsigned cpu_index,
> X86CPUTopoIDs *topo_ids)
> {
> + unsigned nr_dies = topo_info->dies_per_pkg;
> + unsigned nr_cores = topo_info->cores_per_die;
> + unsigned nr_threads = topo_info->threads_per_core;
> +
> topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads);
> topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies;
> topo_ids->core_id = cpu_index / nr_threads % nr_cores;
> @@ -152,11 +162,13 @@ static inline void x86_topo_ids_from_idx(unsigned nr_dies,
> * based on APIC ID
> */
> static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
> - unsigned nr_dies,
> - unsigned nr_cores,
> - unsigned nr_threads,
> + X86CPUTopoInfo *topo_info,
> X86CPUTopoIDs *topo_ids)
> {
> + unsigned nr_dies = topo_info->dies_per_pkg;
> + unsigned nr_cores = topo_info->cores_per_die;
> + unsigned nr_threads = topo_info->threads_per_core;
> +
> topo_ids->smt_id = apicid &
> ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads));
> topo_ids->core_id =
> @@ -173,14 +185,12 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
> *
> * 'cpu_index' is a sequential, contiguous ID for the CPU.
> */
> -static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_dies,
> - unsigned nr_cores,
> - unsigned nr_threads,
> +static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info,
> unsigned cpu_index)
> {
> X86CPUTopoIDs topo_ids;
> - x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo_ids);
> - return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo_ids);
> + x86_topo_ids_from_idx(topo_info, cpu_index, &topo_ids);
> + return apicid_from_topo_ids(topo_info, &topo_ids);
> }
>
> #endif /* HW_I386_TOPOLOGY_H */
> diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
> index 41fe37b8a3..22babcb3bb 100644
> --- a/include/hw/i386/x86.h
> +++ b/include/hw/i386/x86.h
> @@ -21,6 +21,7 @@
> #include "exec/hwaddr.h"
> #include "qemu/notify.h"
>
> +#include "hw/i386/topology.h"
> #include "hw/boards.h"
> #include "hw/nmi.h"
> #include "hw/isa/isa.h"
> @@ -82,6 +83,8 @@ typedef struct {
> #define X86_MACHINE_CLASS(class) \
> OBJECT_CLASS_CHECK(X86MachineClass, class, TYPE_X86_MACHINE)
>
> +void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms);
> +
> uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms,
> unsigned int cpu_index);
>
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 04/16] machine: Add SMP Sockets in CpuTopology
2020-03-03 19:57 ` [PATCH v5 04/16] machine: Add SMP Sockets in CpuTopology Babu Moger
@ 2020-03-09 14:17 ` Igor Mammedov
2020-03-09 18:01 ` Babu Moger
0 siblings, 1 reply; 45+ messages in thread
From: Igor Mammedov @ 2020-03-09 14:17 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On Tue, 03 Mar 2020 13:57:18 -0600
Babu Moger <babu.moger@amd.com> wrote:
> Store the smp sockets in CpuTopology. The socket information required to
> build the apic id in EPYC mode. Right now socket information is not passed
> to down when decoding the apic id. Add the socket information here.
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
> hw/core/machine.c | 1 +
> hw/i386/pc.c | 1 +
> include/hw/boards.h | 2 ++
> vl.c | 1 +
this has been moved to softmmu, so patch needs to rebased against current master
> 4 files changed, 5 insertions(+)
>
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index d8e30e4895..2582ce94f6 100644
> --- a/hw/core/machine.c
> +++ b/hw/core/machine.c
> @@ -728,6 +728,7 @@ static void smp_parse(MachineState *ms, QemuOpts *opts)
> ms->smp.cpus = cpus;
> ms->smp.cores = cores;
> ms->smp.threads = threads;
> + ms->smp.sockets = sockets;
> }
>
> if (ms->smp.cpus > 1) {
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index ef23ae2af5..68bf08f285 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -780,6 +780,7 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts)
> ms->smp.cpus = cpus;
> ms->smp.cores = cores;
> ms->smp.threads = threads;
> + ms->smp.sockets = sockets;
> x86ms->smp_dies = dies;
> }
>
> diff --git a/include/hw/boards.h b/include/hw/boards.h
> index fb1b43d5b9..320dd14e02 100644
> --- a/include/hw/boards.h
> +++ b/include/hw/boards.h
> @@ -252,12 +252,14 @@ typedef struct DeviceMemoryState {
> * @cpus: the number of present logical processors on the machine
> * @cores: the number of cores in one package
> * @threads: the number of threads in one core
> + * @sockets: the number of sockets on the machine
> * @max_cpus: the maximum number of logical processors on the machine
> */
> typedef struct CpuTopology {
> unsigned int cpus;
> unsigned int cores;
> unsigned int threads;
> + unsigned int sockets;
> unsigned int max_cpus;
> } CpuTopology;
>
> diff --git a/vl.c b/vl.c
> index 7dcb0879c4..f77b1285c6 100644
> --- a/vl.c
> +++ b/vl.c
> @@ -3949,6 +3949,7 @@ int main(int argc, char **argv, char **envp)
> current_machine->smp.max_cpus = machine_class->default_cpus;
> current_machine->smp.cores = 1;
> current_machine->smp.threads = 1;
> + current_machine->smp.sockets = 1;
>
> machine_class->smp_parse(current_machine,
> qemu_opts_find(qemu_find_opts("smp-opts"), NULL));
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 05/16] hw/i386: Remove unnecessary initialization in x86_cpu_new
2020-03-03 19:57 ` [PATCH v5 05/16] hw/i386: Remove unnecessary initialization in x86_cpu_new Babu Moger
@ 2020-03-09 14:18 ` Igor Mammedov
0 siblings, 0 replies; 45+ messages in thread
From: Igor Mammedov @ 2020-03-09 14:18 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On Tue, 03 Mar 2020 13:57:24 -0600
Babu Moger <babu.moger@amd.com> wrote:
> The function pc_cpu_pre_plug takes care of initialization of CPUX86State.
> So, remove the initialization here.
>
> Suggested-by: Igor Mammedov <imammedo@redhat.com>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
> hw/i386/x86.c | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
> index 03b8962c98..79badcc4ec 100644
> --- a/hw/i386/x86.c
> +++ b/hw/i386/x86.c
> @@ -103,13 +103,9 @@ void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp)
> {
> Object *cpu = NULL;
> Error *local_err = NULL;
> - CPUX86State *env = NULL;
>
> cpu = object_new(MACHINE(x86ms)->cpu_type);
>
> - env = &X86_CPU(cpu)->env;
> - env->nr_dies = x86ms->smp_dies;
> -
> object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
> object_property_set_bool(cpu, true, "realized", &local_err);
>
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 06/16] hw/i386: Update structures to save the number of nodes per package
2020-03-03 19:57 ` [PATCH v5 06/16] hw/i386: Update structures to save the number of nodes per package Babu Moger
@ 2020-03-09 14:26 ` Igor Mammedov
0 siblings, 0 replies; 45+ messages in thread
From: Igor Mammedov @ 2020-03-09 14:26 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On Tue, 03 Mar 2020 13:57:30 -0600
Babu Moger <babu.moger@amd.com> wrote:
> Update structures X86CPUTopoIDs and CPUX86State to hold the number of
> nodes per package. This is required to build EPYC mode topology.
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
> hw/i386/pc.c | 1 +
> hw/i386/x86.c | 1 +
> include/hw/i386/topology.h | 1 +
> target/i386/cpu.c | 1 +
> target/i386/cpu.h | 1 +
> 5 files changed, 5 insertions(+)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 68bf08f285..3d13cd46d6 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -1526,6 +1526,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
> init_topo_info(&topo_info, x86ms);
>
> env->nr_dies = x86ms->smp_dies;
> + env->nr_nodes = topo_info.nodes_per_pkg;
>
> /*
> * If APIC ID is not set,
> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
> index 79badcc4ec..929b80c9c7 100644
> --- a/hw/i386/x86.c
> +++ b/hw/i386/x86.c
> @@ -62,6 +62,7 @@ inline void init_topo_info(X86CPUTopoInfo *topo_info,
> {
> MachineState *ms = MACHINE(x86ms);
>
> + topo_info->nodes_per_pkg = ms->numa_state->num_nodes / ms->smp.sockets;
> topo_info->dies_per_pkg = x86ms->smp_dies;
> topo_info->cores_per_die = ms->smp.cores;
> topo_info->threads_per_core = ms->smp.threads;
> diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
> index ba52d49079..04f01e2a09 100644
> --- a/include/hw/i386/topology.h
> +++ b/include/hw/i386/topology.h
> @@ -53,6 +53,7 @@ typedef struct X86CPUTopoIDs {
> } X86CPUTopoIDs;
>
> typedef struct X86CPUTopoInfo {
> + unsigned nodes_per_pkg;
> unsigned dies_per_pkg;
> unsigned cores_per_die;
> unsigned threads_per_core;
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 1263271edd..40670f8aca 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -6829,6 +6829,7 @@ static void x86_cpu_initfn(Object *obj)
> FeatureWord w;
>
> env->nr_dies = 1;
> + env->nr_nodes = 1;
> cpu_set_cpustate_pointers(cpu);
>
> object_property_add(obj, "family", "int",
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 576f309bbf..20abbda647 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1607,6 +1607,7 @@ typedef struct CPUX86State {
> TPRAccess tpr_access_type;
>
> unsigned nr_dies;
> + unsigned nr_nodes;
> } CPUX86State;
>
> struct kvm_msrs;
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 10/16] hw/i386: Introduce apicid functions inside X86MachineState
2020-03-03 19:57 ` [PATCH v5 10/16] hw/i386: Introduce apicid functions inside X86MachineState Babu Moger
@ 2020-03-09 14:34 ` Igor Mammedov
0 siblings, 0 replies; 45+ messages in thread
From: Igor Mammedov @ 2020-03-09 14:34 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On Tue, 03 Mar 2020 13:57:56 -0600
Babu Moger <babu.moger@amd.com> wrote:
> Introduce model specific apicid functions inside X86MachineState.
> These functions will be loaded from X86CPUDefinition.
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
> hw/i386/x86.c | 5 +++++
> include/hw/i386/x86.h | 9 +++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
> index 929b80c9c7..15b7815bb0 100644
> --- a/hw/i386/x86.c
> +++ b/hw/i386/x86.c
> @@ -911,6 +911,11 @@ static void x86_machine_initfn(Object *obj)
> x86ms->smm = ON_OFF_AUTO_AUTO;
> x86ms->max_ram_below_4g = 0; /* use default */
> x86ms->smp_dies = 1;
> +
> + x86ms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx;
> + x86ms->topo_ids_from_apicid = x86_topo_ids_from_apicid;
> + x86ms->apicid_from_topo_ids = x86_apicid_from_topo_ids;
> + x86ms->apicid_pkg_offset = apicid_pkg_offset;
> }
>
> static void x86_machine_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
> index 22babcb3bb..2643b57629 100644
> --- a/include/hw/i386/x86.h
> +++ b/include/hw/i386/x86.h
> @@ -65,6 +65,15 @@ typedef struct {
>
> OnOffAuto smm;
>
> + /* Apic id specific handlers */
> + uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info,
> + unsigned cpu_index);
> + void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_info,
> + X86CPUTopoIDs *topo_ids);
> + apic_id_t (*apicid_from_topo_ids)(X86CPUTopoInfo *topo_info,
> + const X86CPUTopoIDs *topo_ids);
> + uint32_t (*apicid_pkg_offset)(X86CPUTopoInfo *topo_info);
> +
> /*
> * Address space used by IOAPIC device. All IOAPIC interrupts
> * will be translated to MSI messages in the address space.
>
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 11/16] target/i386: Load apicid model specific handlers from X86CPUDefinition
2020-03-03 19:58 ` [PATCH v5 11/16] target/i386: Load apicid model specific handlers from X86CPUDefinition Babu Moger
@ 2020-03-09 14:49 ` Igor Mammedov
2020-03-09 14:55 ` Igor Mammedov
2020-03-09 19:04 ` Babu Moger
0 siblings, 2 replies; 45+ messages in thread
From: Igor Mammedov @ 2020-03-09 14:49 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On Tue, 03 Mar 2020 13:58:03 -0600
Babu Moger <babu.moger@amd.com> wrote:
> Load the model specific handlers if available or else default handlers
> will be loaded. Add the model specific handlers if apicid decoding
> differs from the standard sequential numbering.
>
this is still the old version of the patch and hadn't addressed feedback from v4
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
> target/i386/cpu.c | 34 ++++++++++++++++++++++++++++++++++
> target/i386/cpu.h | 1 +
> 2 files changed, 35 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index c75cf744ab..f33d8b77f5 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -51,6 +51,7 @@
> #include "sysemu/sysemu.h"
> #include "sysemu/tcg.h"
> #include "hw/qdev-properties.h"
> +#include "hw/i386/x86.h"
this dependency shouldn't be here, see below
> #include "hw/i386/topology.h"
> #ifndef CONFIG_USER_ONLY
> #include "exec/address-spaces.h"
[...]
> +void cpu_x86_init_apicid_fns(MachineState *machine)
it should be something like:
x86_use_epyc_apic_id_encoding(char *cpu_type)
try to avoid pulling in unnecessary dependency on Machine into cpu.c
> +{
> + X86CPUClass *xcc = X86_CPU_CLASS(object_class_by_name(machine->cpu_type));
> + X86CPUModel *model = xcc->model;
> + X86CPUDefinition *def = model->cpudef;
> + X86MachineState *x86ms = X86_MACHINE(machine);
> +
> + if (def) {
> + if (def->apicid_from_cpu_idx) {
> + x86ms->apicid_from_cpu_idx = def->apicid_from_cpu_idx;
> + }
> + if (def->topo_ids_from_apicid) {
> + x86ms->topo_ids_from_apicid = def->topo_ids_from_apicid;
> + }
> + if (def->apicid_from_topo_ids) {
> + x86ms->apicid_from_topo_ids = def->apicid_from_topo_ids;
> + }
> + if (def->apicid_pkg_offset) {
> + x86ms->apicid_pkg_offset = def->apicid_pkg_offset;
> + }
> + }
> +}
It was suggested to move defaults initialization to x86_machine_class_init()
as was suggested at
[PATCH v4 12/16] hw/i386: Use the apicid handlers from X86MachineState
and acked by Eduardo
> +
> static CPUCaches epyc_cache_info = {
> .l1d_cache = &(CPUCacheInfo) {
> .type = DATA_CACHE,
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 20abbda647..34f0d994ef 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1895,6 +1895,7 @@ void cpu_clear_apic_feature(CPUX86State *env);
> void host_cpuid(uint32_t function, uint32_t count,
> uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
> void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
> +void cpu_x86_init_apicid_fns(MachineState *machine);
>
> /* helper.c */
> bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 11/16] target/i386: Load apicid model specific handlers from X86CPUDefinition
2020-03-09 14:49 ` Igor Mammedov
@ 2020-03-09 14:55 ` Igor Mammedov
2020-03-09 19:04 ` Babu Moger
1 sibling, 0 replies; 45+ messages in thread
From: Igor Mammedov @ 2020-03-09 14:55 UTC (permalink / raw)
To: Babu Moger; +Cc: qemu-devel, pbonzini, rth, ehabkost, mst
On Mon, 9 Mar 2020 15:49:22 +0100
Igor Mammedov <imammedo@redhat.com> wrote:
> On Tue, 03 Mar 2020 13:58:03 -0600
> Babu Moger <babu.moger@amd.com> wrote:
>
> > Load the model specific handlers if available or else default handlers
> > will be loaded. Add the model specific handlers if apicid decoding
> > differs from the standard sequential numbering.
> >
>
> this is still the old version of the patch and hadn't addressed feedback from v4
>
> > Signed-off-by: Babu Moger <babu.moger@amd.com>
> > ---
> > target/i386/cpu.c | 34 ++++++++++++++++++++++++++++++++++
> > target/i386/cpu.h | 1 +
> > 2 files changed, 35 insertions(+)
> >
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index c75cf744ab..f33d8b77f5 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -51,6 +51,7 @@
> > #include "sysemu/sysemu.h"
> > #include "sysemu/tcg.h"
> > #include "hw/qdev-properties.h"
> > +#include "hw/i386/x86.h"
> this dependency shouldn't be here, see below
btw: it does break build of linux-user target
(one more reason to avoid machine deps)
>
> > #include "hw/i386/topology.h"
> > #ifndef CONFIG_USER_ONLY
> > #include "exec/address-spaces.h"
> [...]
> > +void cpu_x86_init_apicid_fns(MachineState *machine)
> it should be something like:
> x86_use_epyc_apic_id_encoding(char *cpu_type)
> try to avoid pulling in unnecessary dependency on Machine into cpu.c
>
> > +{
> > + X86CPUClass *xcc = X86_CPU_CLASS(object_class_by_name(machine->cpu_type));
> > + X86CPUModel *model = xcc->model;
> > + X86CPUDefinition *def = model->cpudef;
> > + X86MachineState *x86ms = X86_MACHINE(machine);
> > +
> > + if (def) {
> > + if (def->apicid_from_cpu_idx) {
> > + x86ms->apicid_from_cpu_idx = def->apicid_from_cpu_idx;
> > + }
> > + if (def->topo_ids_from_apicid) {
> > + x86ms->topo_ids_from_apicid = def->topo_ids_from_apicid;
> > + }
> > + if (def->apicid_from_topo_ids) {
> > + x86ms->apicid_from_topo_ids = def->apicid_from_topo_ids;
> > + }
> > + if (def->apicid_pkg_offset) {
> > + x86ms->apicid_pkg_offset = def->apicid_pkg_offset;
> > + }
> > + }
> > +}
>
> It was suggested to move defaults initialization to x86_machine_class_init()
>
> as was suggested at
> [PATCH v4 12/16] hw/i386: Use the apicid handlers from X86MachineState
> and acked by Eduardo
>
> > +
> > static CPUCaches epyc_cache_info = {
> > .l1d_cache = &(CPUCacheInfo) {
> > .type = DATA_CACHE,
> > diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> > index 20abbda647..34f0d994ef 100644
> > --- a/target/i386/cpu.h
> > +++ b/target/i386/cpu.h
> > @@ -1895,6 +1895,7 @@ void cpu_clear_apic_feature(CPUX86State *env);
> > void host_cpuid(uint32_t function, uint32_t count,
> > uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
> > void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
> > +void cpu_x86_init_apicid_fns(MachineState *machine);
> >
> > /* helper.c */
> > bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> >
>
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 12/16] hw/i386: Use the apicid handlers from X86MachineState
2020-03-03 19:58 ` [PATCH v5 12/16] hw/i386: Use the apicid handlers from X86MachineState Babu Moger
@ 2020-03-09 15:01 ` Igor Mammedov
2020-03-09 19:08 ` Babu Moger
0 siblings, 1 reply; 45+ messages in thread
From: Igor Mammedov @ 2020-03-09 15:01 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On Tue, 03 Mar 2020 13:58:10 -0600
Babu Moger <babu.moger@amd.com> wrote:
> Check and Load the apicid handlers from X86CPUDefinition if available.
> Update the calling convention for the apicid handlers.
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
> hw/i386/pc.c | 6 +++---
> hw/i386/x86.c | 11 +++++++----
> 2 files changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 17cce3f074..c600ba0432 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -1581,14 +1581,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
> topo_ids.die_id = cpu->die_id;
> topo_ids.core_id = cpu->core_id;
> topo_ids.smt_id = cpu->thread_id;
> - cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids);
> + cpu->apic_id = x86ms->apicid_from_topo_ids(&topo_info, &topo_ids);
> }
>
> cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
> if (!cpu_slot) {
> MachineState *ms = MACHINE(pcms);
>
> - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
> + x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
this (including other similar) change(s) to callbacks should go to 11/16
> error_setg(errp,
> "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
> " APIC ID %" PRIu32 ", valid index range 0:%d",
> @@ -1609,7 +1609,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
> /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
> * once -smp refactoring is complete and there will be CPU private
> * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
> - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
> + x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
> if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
> error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
> " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
> index 15b7815bb0..d46dd4ad9e 100644
> --- a/hw/i386/x86.c
> +++ b/hw/i386/x86.c
> @@ -86,7 +86,7 @@ uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
>
> init_topo_info(&topo_info, x86ms);
>
> - correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index);
> + correct_id = x86ms->apicid_from_cpu_idx(&topo_info, cpu_index);
> if (x86mc->compat_apic_id_mode) {
> if (cpu_index != correct_id && !warned && !qtest_enabled()) {
> error_report("APIC IDs set in compatibility mode, "
> @@ -158,8 +158,8 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
> init_topo_info(&topo_info, x86ms);
>
> assert(idx < ms->possible_cpus->len);
> - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
> - &topo_info, &topo_ids);
> + x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
> + &topo_info, &topo_ids);
> return topo_ids.pkg_id % ms->numa_state->num_nodes;
> }
>
> @@ -179,6 +179,9 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
> return ms->possible_cpus;
> }
>
> + /* Initialize apicid handlers */
> + cpu_x86_init_apicid_fns(ms);
> +
> ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
> sizeof(CPUArchId) * max_cpus);
> ms->possible_cpus->len = max_cpus;
> @@ -192,7 +195,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
> ms->possible_cpus->cpus[i].vcpus_count = 1;
> ms->possible_cpus->cpus[i].arch_id =
> x86_cpu_apic_id_from_index(x86ms, i);
> - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
> + x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
> &topo_info, &topo_ids);
not aligned properly
> ms->possible_cpus->cpus[i].props.has_socket_id = true;
> ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 13/16] target/i386: Add EPYC model specific handlers
2020-03-03 19:58 ` [PATCH v5 13/16] target/i386: Add EPYC model specific handlers Babu Moger
@ 2020-03-09 15:03 ` Igor Mammedov
2020-03-09 19:12 ` Babu Moger
0 siblings, 1 reply; 45+ messages in thread
From: Igor Mammedov @ 2020-03-09 15:03 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On Tue, 03 Mar 2020 13:58:16 -0600
Babu Moger <babu.moger@amd.com> wrote:
> Add the new EPYC model specific handlers to fix the apicid decoding.
>
> The APIC ID is decoded based on the sequence sockets->dies->cores->threads.
> This works fine for most standard AMD and other vendors' configurations,
> but this decoding sequence does not follow that of AMD's APIC ID enumeration
> strictly. In some cases this can cause CPU topology inconsistency.
>
> When booting a guest VM, the kernel tries to validate the topology, and finds
> it inconsistent with the enumeration of EPYC cpu models. The more details are
> in the bug https://bugzilla.redhat.com/show_bug.cgi?id=1728166.
>
> To fix the problem we need to build the topology as per the Processor
> Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
> Processors.
> It is available at https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip
>
> Here is the text from the PPR.
> Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
> number of least significant bits in the Initial APIC ID that indicate core ID
> within a processor, in constructing per-core CPUID masks.
> Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
> (MNC) that the processor could theoretically support, not the actual number of
> cores that are actually implemented or enabled on the processor, as indicated
> by Core::X86::Cpuid::SizeId[NC].
> Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
> • ApicId[6] = Socket ID.
> • ApicId[5:4] = Node ID.
> • ApicId[3] = Logical CCX L3 complex ID
> • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
> ---
> target/i386/cpu.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index f33d8b77f5..f870f7c55b 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3884,6 +3884,10 @@ static X86CPUDefinition builtin_x86_defs[] = {
> .xlevel = 0x8000001E,
> .model_id = "AMD EPYC Processor",
> .cache_info = &epyc_cache_info,
> + .apicid_from_cpu_idx = x86_apicid_from_cpu_idx_epyc,
> + .topo_ids_from_apicid = x86_topo_ids_from_apicid_epyc,
> + .apicid_from_topo_ids = x86_apicid_from_topo_ids_epyc,
> + .apicid_pkg_offset = apicid_pkg_offset_epyc,
> .versions = (X86CPUVersionDefinition[]) {
> { .version = 1 },
> {
>
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 14/16] hw/i386: Move arch_id decode inside x86_cpus_init
2020-03-03 19:58 ` [PATCH v5 14/16] hw/i386: Move arch_id decode inside x86_cpus_init Babu Moger
@ 2020-03-09 15:21 ` Igor Mammedov
2020-03-09 19:31 ` Babu Moger
0 siblings, 1 reply; 45+ messages in thread
From: Igor Mammedov @ 2020-03-09 15:21 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On Tue, 03 Mar 2020 13:58:24 -0600
Babu Moger <babu.moger@amd.com> wrote:
> Apicid calculation depends on knowing the total number of numa nodes
> for EPYC cpu models. Right now, we are calculating the arch_id while
> parsing the numa(parse_numa). At this time, it is not known how many
> total numa nodes are configured in the system.
>
> Move the arch_id inside x86_cpus_init. At this time smp parameter is already
> completed and numa node information is available.
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
> hw/i386/x86.c | 17 +++++++++++------
> 1 file changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
> index d46dd4ad9e..66998b065c 100644
> --- a/hw/i386/x86.c
> +++ b/hw/i386/x86.c
> @@ -121,6 +121,9 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
> MachineState *ms = MACHINE(x86ms);
> MachineClass *mc = MACHINE_GET_CLASS(x86ms);
>
> + /* Initialize apicid handlers first */
> + cpu_x86_init_apicid_fns(ms);
> +
> x86_cpu_set_default_version(default_cpu_version);
>
> /*
> @@ -134,6 +137,12 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
> x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms,
> ms->smp.max_cpus - 1) + 1;
> possible_cpus = mc->possible_cpu_arch_ids(ms);
> +
> + for (i = 0; i < ms->smp.cpus; i++) {
> + ms->possible_cpus->cpus[i].arch_id =
> + x86_cpu_apic_id_from_index(x86ms, i);
> + }
> +
> for (i = 0; i < ms->smp.cpus; i++) {
> x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal);
> }
> @@ -158,8 +167,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
> init_topo_info(&topo_info, x86ms);
>
> assert(idx < ms->possible_cpus->len);
> - x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
> - &topo_info, &topo_ids);
> + x86_topo_ids_from_idx(&topo_info, idx, &topo_ids);
not necessary if default x86ms->topo_ids_from_apicid were initialized from x86 machine class
I also wonder if this default contraption we have is going to work
in case of EPYC cpu (i.e. is would generate valid nodeids).
Bot instead of than trying to fix it if it's broken,
I'd rather deprecate and drop get_default_cpu_node_id() requiring users
to explicitly define CPU mapping to numa nodes.
That would be consistent with req for explicit RAM for numa nodes
(postponed till 5.1 due to libvirt not being ready),
i.e if one wants numa, one should explicitly provide necessary mapping
or machine won't start.
> return topo_ids.pkg_id % ms->numa_state->num_nodes;
> }
>
> @@ -193,10 +201,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
>
> ms->possible_cpus->cpus[i].type = ms->cpu_type;
> ms->possible_cpus->cpus[i].vcpus_count = 1;
> - ms->possible_cpus->cpus[i].arch_id =
> - x86_cpu_apic_id_from_index(x86ms, i);
> - x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
> - &topo_info, &topo_ids);
> + x86_topo_ids_from_idx(&topo_info, i, &topo_ids);
ditto
> ms->possible_cpus->cpus[i].props.has_socket_id = true;
> ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
> if (x86ms->smp_dies > 1) {
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 15/16] i386: Fix pkg_id offset for EPYC cpu models
2020-03-03 19:58 ` [PATCH v5 15/16] i386: Fix pkg_id offset for EPYC cpu models Babu Moger
@ 2020-03-09 15:22 ` Igor Mammedov
0 siblings, 0 replies; 45+ messages in thread
From: Igor Mammedov @ 2020-03-09 15:22 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On Tue, 03 Mar 2020 13:58:30 -0600
Babu Moger <babu.moger@amd.com> wrote:
> If the system is numa configured the pkg_offset needs
> to be adjusted for EPYC cpu models. Fix it calling the
> model specific handler.
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
> hw/i386/pc.c | 1 +
> target/i386/cpu.c | 4 ++--
> target/i386/cpu.h | 1 +
> 3 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index c600ba0432..b6237a3a14 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -1527,6 +1527,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
>
> env->nr_dies = x86ms->smp_dies;
> env->nr_nodes = topo_info.nodes_per_pkg;
> + env->pkg_offset = x86ms->apicid_pkg_offset(&topo_info);
>
> /*
> * If APIC ID is not set,
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index f870f7c55b..9b160cbdd1 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -5503,7 +5503,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
> *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
> break;
> case 1:
> - *eax = apicid_pkg_offset(&topo_info);
> + *eax = env->pkg_offset;
> *ebx = cs->nr_cores * cs->nr_threads;
> *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
> break;
> @@ -5537,7 +5537,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
> *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
> break;
> case 2:
> - *eax = apicid_pkg_offset(&topo_info);
> + *eax = env->pkg_offset;
> *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
> *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
> break;
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 34f0d994ef..aac86af5cf 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1608,6 +1608,7 @@ typedef struct CPUX86State {
>
> unsigned nr_dies;
> unsigned nr_nodes;
> + unsigned pkg_offset;
> } CPUX86State;
>
> struct kvm_msrs;
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model
2020-03-08 13:25 ` [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Michael S. Tsirkin
@ 2020-03-09 17:50 ` Babu Moger
0 siblings, 0 replies; 45+ messages in thread
From: Babu Moger @ 2020-03-09 17:50 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: ehabkost, qemu-devel, imammedo, pbonzini, rth
On 3/8/20 8:25 AM, Michael S. Tsirkin wrote:
> On Tue, Mar 03, 2020 at 01:56:51PM -0600, Babu Moger wrote:
>> This series fixes APIC ID encoding problem reported on AMD EPYC cpu models.
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.redhat.com%2Fshow_bug.cgi%3Fid%3D1728166&data=02%7C01%7Cbabu.moger%40amd.com%7C9176c1cef91b4ece2b5e08d7c3643a0a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637192707563033288&sdata=r%2Frpma42Ms356HFtNthqJNI3CiQBEfI%2BNWsWCr%2BabV0%3D&reserved=0
>>
>> Currently, the APIC ID is decoded based on the sequence
>> sockets->dies->cores->threads. This works for most standard AMD and other
>> vendors' configurations, but this decoding sequence does not follow that of
>> AMD's APIC ID enumeration strictly. In some cases this can cause CPU topology
>> inconsistency. When booting a guest VM, the kernel tries to validate the
>> topology, and finds it inconsistent with the enumeration of EPYC cpu models.
>>
>> To fix the problem we need to build the topology as per the Processor
>> Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
>> Processors. The documentation is available from the bugzilla Link below.
>>
>> Link: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.kernel.org%2Fshow_bug.cgi%3Fid%3D206537&data=02%7C01%7Cbabu.moger%40amd.com%7C9176c1cef91b4ece2b5e08d7c3643a0a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637192707563033288&sdata=PWj8%2FEcBYPmcJVg4qgbf%2BPZ1VbLzqXgAiQ7ujtfFp90%3D&reserved=0
>>
>> Here is the text from the PPR.
>> Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
>> number of least significant bits in the Initial APIC ID that indicate core ID
>> within a processor, in constructing per-core CPUID masks.
>> Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
>> (MNC) that the processor could theoretically support, not the actual number of
>> cores that are actually implemented or enabled on the processor, as indicated
>> by Core::X86::Cpuid::SizeId[NC].
>> Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
>> • ApicId[6] = Socket ID.
>> • ApicId[5:4] = Node ID.
>> • ApicId[3] = Logical CCX L3 complex ID
>> • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
>
>
> Looks reasonable:
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
Michael.Thanks
>
> belongs in Eduardo's tree I guess.
>
>> v5:
>> Generated the patches on top of git://github.com/ehabkost/qemu.git (x86-next).
>> Changes from v4.
>> 1. Re-arranged the patches 2 and 4 as suggested by Igor.
>> 2. Kept the apicid handler functions inside X86MachineState as discussed.
>> These handlers are loaded from X86CPUDefinitions.
>> 3. Removed unnecessary X86CPUstate initialization from x86_cpu_new. Suggested
>> by Igor.
>> 4. And other minor changes related to patch format.
>>
>> v4:
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fqemu-devel%2F158161767653.48948.10578064482878399556.stgit%40naples-babu.amd.com%2F&data=02%7C01%7Cbabu.moger%40amd.com%7C9176c1cef91b4ece2b5e08d7c3643a0a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637192707563033288&sdata=bKJ2d%2Blhxm%2Bht7hZBsQpHtFOaee3FHwA0ploz%2BNpPuw%3D&reserved=0
>> Changes from v3.
>> 1. Moved the arch_id calculation inside the function x86_cpus_init. With this change,
>> we dont need to change common numa code.(suggested by Igor)
>> 2. Introduced the model specific handlers inside X86CPUDefinitions.
>> These handlers are loaded into X86MachineState during the init.
>> 3. Removed llc_id from x86CPU.
>> 4. Removed init_apicid_fn hanlder from MachineClass. Kept all the code changes
>> inside the x86.
>> 5. Added new handler function apicid_pkg_offset for pkg_offset calculation.
>> 6. And some Other minor changes.
>>
>> v3:
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fqemu-devel%2F157541968844.46157.17994918142533791313.stgit%40naples-babu.amd.com%2F&data=02%7C01%7Cbabu.moger%40amd.com%7C9176c1cef91b4ece2b5e08d7c3643a0a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637192707563043283&sdata=90dNqhJMpQiyv4KdBfuf9hxX8EHFesJUT5jxSnuU84E%3D&reserved=0
>> 1. Consolidated the topology information in structure X86CPUTopoInfo.
>> 2. Changed the ccx_id to llc_id as commented by upstream.
>> 3. Generalized the apic id decoding. It is mostly similar to current apic id
>> except that it adds new field llc_id when numa configured. Removes all the
>> hardcoded values.
>> 4. Removed the earlier parse_numa split. And moved the numa node initialization
>> inside the numa_complete_configuration. This is bit cleaner as commented by
>> Eduardo.
>> 5. Added new function init_apicid_fn inside machine_class structure. This
>> will be used to update the apic id handler specific to cpu model.
>> 6. Updated the cpuid unit tests.
>> 7. TODO : Need to figure out how to dynamically update the handlers using cpu models.
>> I might some guidance on that.
>>
>> v2:
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fqemu-devel%2F156779689013.21957.1631551572950676212.stgit%40localhost.localdomain%2F&data=02%7C01%7Cbabu.moger%40amd.com%7C9176c1cef91b4ece2b5e08d7c3643a0a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637192707563043283&sdata=tKtt4Kz599IkFhyObyg9%2FVC3BEKPjo4KAGi%2BsdVe9zM%3D&reserved=0
>> 1. Introduced the new property epyc to enable new epyc mode.
>> 2. Separated the epyc mode and non epyc mode function.
>> 3. Introduced function pointers in PCMachineState to handle the
>> differences.
>> 4. Mildly tested different combinations to make things are working as expected.
>> 5. TODO : Setting the epyc feature bit needs to be worked out. This feature is
>> supported only on AMD EPYC models. I may need some guidance on that.
>>
>> v1:
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fqemu-devel%2F20190731232032.51786-1-babu.moger%40amd.com%2F&data=02%7C01%7Cbabu.moger%40amd.com%7C9176c1cef91b4ece2b5e08d7c3643a0a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637192707563043283&sdata=biydl3JXU0YGLK%2FY7sXtSbdCcb7P4Qjl40Kr0Fp5CEc%3D&reserved=0
>>
>> ---
>>
>> Babu Moger (16):
>> hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
>> hw/i386: Introduce X86CPUTopoInfo to contain topology info
>> hw/i386: Consolidate topology functions
>> machine: Add SMP Sockets in CpuTopology
>> hw/i386: Remove unnecessary initialization in x86_cpu_new
>> hw/i386: Update structures to save the number of nodes per package
>> hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids
>> hw/386: Add EPYC mode topology decoding functions
>> target/i386: Cleanup and use the EPYC mode topology functions
>> hw/i386: Introduce apicid functions inside X86MachineState
>> target/i386: Load apicid model specific handlers from X86CPUDefinition
>> hw/i386: Use the apicid handlers from X86MachineState
>> target/i386: Add EPYC model specific handlers
>> hw/i386: Move arch_id decode inside x86_cpus_init
>> i386: Fix pkg_id offset for EPYC cpu models
>> tests: Update the Unit tests
>>
>>
>> hw/core/machine.c | 1
>> hw/i386/pc.c | 54 ++++++-----
>> hw/i386/x86.c | 72 ++++++++++----
>> include/hw/boards.h | 2
>> include/hw/i386/topology.h | 215 ++++++++++++++++++++++++++++++------------
>> include/hw/i386/x86.h | 12 ++
>> target/i386/cpu.c | 224 +++++++++++++++++---------------------------
>> target/i386/cpu.h | 3 +
>> tests/test-x86-cpuid.c | 115 +++++++++++++----------
>> vl.c | 1
>> 10 files changed, 403 insertions(+), 296 deletions(-)
>>
>> --
>> Signature
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 04/16] machine: Add SMP Sockets in CpuTopology
2020-03-09 14:17 ` Igor Mammedov
@ 2020-03-09 18:01 ` Babu Moger
0 siblings, 0 replies; 45+ messages in thread
From: Babu Moger @ 2020-03-09 18:01 UTC (permalink / raw)
To: Igor Mammedov; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On 3/9/20 9:17 AM, Igor Mammedov wrote:
> On Tue, 03 Mar 2020 13:57:18 -0600
> Babu Moger <babu.moger@amd.com> wrote:
>
>> Store the smp sockets in CpuTopology. The socket information required to
>> build the apic id in EPYC mode. Right now socket information is not passed
>> to down when decoding the apic id. Add the socket information here.
>>
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
>> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
>> ---
>> hw/core/machine.c | 1 +
>> hw/i386/pc.c | 1 +
>> include/hw/boards.h | 2 ++
>> vl.c | 1 +
>
> this has been moved to softmmu, so patch needs to rebased against current master
Sure. Will do.
>
>> 4 files changed, 5 insertions(+)
>>
>> diff --git a/hw/core/machine.c b/hw/core/machine.c
>> index d8e30e4895..2582ce94f6 100644
>> --- a/hw/core/machine.c
>> +++ b/hw/core/machine.c
>> @@ -728,6 +728,7 @@ static void smp_parse(MachineState *ms, QemuOpts *opts)
>> ms->smp.cpus = cpus;
>> ms->smp.cores = cores;
>> ms->smp.threads = threads;
>> + ms->smp.sockets = sockets;
>> }
>>
>> if (ms->smp.cpus > 1) {
>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>> index ef23ae2af5..68bf08f285 100644
>> --- a/hw/i386/pc.c
>> +++ b/hw/i386/pc.c
>> @@ -780,6 +780,7 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts)
>> ms->smp.cpus = cpus;
>> ms->smp.cores = cores;
>> ms->smp.threads = threads;
>> + ms->smp.sockets = sockets;
>> x86ms->smp_dies = dies;
>> }
>>
>> diff --git a/include/hw/boards.h b/include/hw/boards.h
>> index fb1b43d5b9..320dd14e02 100644
>> --- a/include/hw/boards.h
>> +++ b/include/hw/boards.h
>> @@ -252,12 +252,14 @@ typedef struct DeviceMemoryState {
>> * @cpus: the number of present logical processors on the machine
>> * @cores: the number of cores in one package
>> * @threads: the number of threads in one core
>> + * @sockets: the number of sockets on the machine
>> * @max_cpus: the maximum number of logical processors on the machine
>> */
>> typedef struct CpuTopology {
>> unsigned int cpus;
>> unsigned int cores;
>> unsigned int threads;
>> + unsigned int sockets;
>> unsigned int max_cpus;
>> } CpuTopology;
>>
>> diff --git a/vl.c b/vl.c
>> index 7dcb0879c4..f77b1285c6 100644
>> --- a/vl.c
>> +++ b/vl.c
>> @@ -3949,6 +3949,7 @@ int main(int argc, char **argv, char **envp)
>> current_machine->smp.max_cpus = machine_class->default_cpus;
>> current_machine->smp.cores = 1;
>> current_machine->smp.threads = 1;
>> + current_machine->smp.sockets = 1;
>>
>> machine_class->smp_parse(current_machine,
>> qemu_opts_find(qemu_find_opts("smp-opts"), NULL));
>>
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 11/16] target/i386: Load apicid model specific handlers from X86CPUDefinition
2020-03-09 14:49 ` Igor Mammedov
2020-03-09 14:55 ` Igor Mammedov
@ 2020-03-09 19:04 ` Babu Moger
2020-03-10 8:27 ` Igor Mammedov
1 sibling, 1 reply; 45+ messages in thread
From: Babu Moger @ 2020-03-09 19:04 UTC (permalink / raw)
To: Igor Mammedov; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On 3/9/20 9:49 AM, Igor Mammedov wrote:
> On Tue, 03 Mar 2020 13:58:03 -0600
> Babu Moger <babu.moger@amd.com> wrote:
>
>> Load the model specific handlers if available or else default handlers
>> will be loaded. Add the model specific handlers if apicid decoding
>> differs from the standard sequential numbering.
>>
>
> this is still the old version of the patch and hadn't addressed feedback from v4
Yes. I was confused little bit about it. Will fix it.
>
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>> ---
>> target/i386/cpu.c | 34 ++++++++++++++++++++++++++++++++++
>> target/i386/cpu.h | 1 +
>> 2 files changed, 35 insertions(+)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index c75cf744ab..f33d8b77f5 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -51,6 +51,7 @@
>> #include "sysemu/sysemu.h"
>> #include "sysemu/tcg.h"
>> #include "hw/qdev-properties.h"
>> +#include "hw/i386/x86.h"
> this dependency shouldn't be here, see below
ok.
>
>> #include "hw/i386/topology.h"
>> #ifndef CONFIG_USER_ONLY
>> #include "exec/address-spaces.h"
> [...]
>> +void cpu_x86_init_apicid_fns(MachineState *machine)
> it should be something like:
> x86_use_epyc_apic_id_encoding(char *cpu_type)
> try to avoid pulling in unnecessary dependency on Machine into cpu.c
Ok.
>
>> +{
>> + X86CPUClass *xcc = X86_CPU_CLASS(object_class_by_name(machine->cpu_type));
>> + X86CPUModel *model = xcc->model;
>> + X86CPUDefinition *def = model->cpudef;
>> + X86MachineState *x86ms = X86_MACHINE(machine);
>> +
>> + if (def) {
>> + if (def->apicid_from_cpu_idx) {
>> + x86ms->apicid_from_cpu_idx = def->apicid_from_cpu_idx;
>> + }
>> + if (def->topo_ids_from_apicid) {
>> + x86ms->topo_ids_from_apicid = def->topo_ids_from_apicid;
>> + }
>> + if (def->apicid_from_topo_ids) {
>> + x86ms->apicid_from_topo_ids = def->apicid_from_topo_ids;
>> + }
>> + if (def->apicid_pkg_offset) {
>> + x86ms->apicid_pkg_offset = def->apicid_pkg_offset;
>> + }
>> + }
>> +}
>
> It was suggested to move defaults initialization to x86_machine_class_init()
ok. We don't need the above changes. I will use the boolean as you
suggested and call this function in x86_cpus_init() to initialize the EPYC
specific handler. Something similar like this below..
x86_use_epyc_apic_id_encoding(char *cpu_type)
{
X86CPUClass *xcc = ... cpu_type ...
return xcc->model->cpudef->use_epyc_apic_id_encoding
}
x86_cpus_init()
{
if (x86_use_epyc_apic_id_encoding(ms->cpu_type)) {
x86ms->apicid_from_cpu_idx = ...epyc...
x86ms->topo_ids_from_apicid = ...epyc...
x86ms->apicid_from_topo_ids = ...epyc...
x86ms->apicid_pkg_offset = ...epyc...
}
}
Sounds right?
>
> as was suggested at
> [PATCH v4 12/16] hw/i386: Use the apicid handlers from X86MachineState
> and acked by Eduardo
>
>> +
>> static CPUCaches epyc_cache_info = {
>> .l1d_cache = &(CPUCacheInfo) {
>> .type = DATA_CACHE,
>> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
>> index 20abbda647..34f0d994ef 100644
>> --- a/target/i386/cpu.h
>> +++ b/target/i386/cpu.h
>> @@ -1895,6 +1895,7 @@ void cpu_clear_apic_feature(CPUX86State *env);
>> void host_cpuid(uint32_t function, uint32_t count,
>> uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
>> void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
>> +void cpu_x86_init_apicid_fns(MachineState *machine);
>>
>> /* helper.c */
>> bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
>>
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 12/16] hw/i386: Use the apicid handlers from X86MachineState
2020-03-09 15:01 ` Igor Mammedov
@ 2020-03-09 19:08 ` Babu Moger
2020-03-10 8:31 ` Igor Mammedov
0 siblings, 1 reply; 45+ messages in thread
From: Babu Moger @ 2020-03-09 19:08 UTC (permalink / raw)
To: Igor Mammedov; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On 3/9/20 10:01 AM, Igor Mammedov wrote:
> On Tue, 03 Mar 2020 13:58:10 -0600
> Babu Moger <babu.moger@amd.com> wrote:
>
>> Check and Load the apicid handlers from X86CPUDefinition if available.
>> Update the calling convention for the apicid handlers.
>>
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>
>
>> ---
>> hw/i386/pc.c | 6 +++---
>> hw/i386/x86.c | 11 +++++++----
>> 2 files changed, 10 insertions(+), 7 deletions(-)
>>
>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>> index 17cce3f074..c600ba0432 100644
>> --- a/hw/i386/pc.c
>> +++ b/hw/i386/pc.c
>> @@ -1581,14 +1581,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
>> topo_ids.die_id = cpu->die_id;
>> topo_ids.core_id = cpu->core_id;
>> topo_ids.smt_id = cpu->thread_id;
>> - cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids);
>> + cpu->apic_id = x86ms->apicid_from_topo_ids(&topo_info, &topo_ids);
>> }
>>
>> cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
>> if (!cpu_slot) {
>> MachineState *ms = MACHINE(pcms);
>>
>> - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
>> + x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
> this (including other similar) change(s) to callbacks should go to 11/16
So, you mean patch #11 and #12 should be squashed together. Is that right?
>
>> error_setg(errp,
>> "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
>> " APIC ID %" PRIu32 ", valid index range 0:%d",
>> @@ -1609,7 +1609,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
>> /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
>> * once -smp refactoring is complete and there will be CPU private
>> * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
>> - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
>> + x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
>> if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
>> error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
>> " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
>> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
>> index 15b7815bb0..d46dd4ad9e 100644
>> --- a/hw/i386/x86.c
>> +++ b/hw/i386/x86.c
>> @@ -86,7 +86,7 @@ uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
>>
>> init_topo_info(&topo_info, x86ms);
>>
>> - correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index);
>> + correct_id = x86ms->apicid_from_cpu_idx(&topo_info, cpu_index);
>> if (x86mc->compat_apic_id_mode) {
>> if (cpu_index != correct_id && !warned && !qtest_enabled()) {
>> error_report("APIC IDs set in compatibility mode, "
>> @@ -158,8 +158,8 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
>> init_topo_info(&topo_info, x86ms);
>>
>> assert(idx < ms->possible_cpus->len);
>> - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
>> - &topo_info, &topo_ids);
>> + x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
>> + &topo_info, &topo_ids);
>> return topo_ids.pkg_id % ms->numa_state->num_nodes;
>> }
>>
>> @@ -179,6 +179,9 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
>> return ms->possible_cpus;
>> }
>>
>> + /* Initialize apicid handlers */
>> + cpu_x86_init_apicid_fns(ms);
>> +
>> ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
>> sizeof(CPUArchId) * max_cpus);
>> ms->possible_cpus->len = max_cpus;
>> @@ -192,7 +195,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
>> ms->possible_cpus->cpus[i].vcpus_count = 1;
>> ms->possible_cpus->cpus[i].arch_id =
>> x86_cpu_apic_id_from_index(x86ms, i);
>> - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
>> + x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
>> &topo_info, &topo_ids);
>
> not aligned properly
>
>> ms->possible_cpus->cpus[i].props.has_socket_id = true;
>> ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
>>
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 13/16] target/i386: Add EPYC model specific handlers
2020-03-09 15:03 ` Igor Mammedov
@ 2020-03-09 19:12 ` Babu Moger
2020-03-10 8:25 ` Igor Mammedov
0 siblings, 1 reply; 45+ messages in thread
From: Babu Moger @ 2020-03-09 19:12 UTC (permalink / raw)
To: Igor Mammedov; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On 3/9/20 10:03 AM, Igor Mammedov wrote:
> On Tue, 03 Mar 2020 13:58:16 -0600
> Babu Moger <babu.moger@amd.com> wrote:
>
>> Add the new EPYC model specific handlers to fix the apicid decoding.
>>
>> The APIC ID is decoded based on the sequence sockets->dies->cores->threads.
>> This works fine for most standard AMD and other vendors' configurations,
>> but this decoding sequence does not follow that of AMD's APIC ID enumeration
>> strictly. In some cases this can cause CPU topology inconsistency.
>>
>> When booting a guest VM, the kernel tries to validate the topology, and finds
>> it inconsistent with the enumeration of EPYC cpu models. The more details are
>> in the bug https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.redhat.com%2Fshow_bug.cgi%3Fid%3D1728166&data=02%7C01%7Cbabu.moger%40amd.com%7C3ddda6803d584aac171b08d7c43b0530%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637193630113242242&sdata=3TkNY2O8HWBqaOrmO8QQoxlzvIv2oEdTO1P9k6VglmU%3D&reserved=0.
>>
>> To fix the problem we need to build the topology as per the Processor
>> Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
>> Processors.
>> It is available at https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.amd.com%2Fsystem%2Ffiles%2FTechDocs%2F55570-B1_PUB.zip&data=02%7C01%7Cbabu.moger%40amd.com%7C3ddda6803d584aac171b08d7c43b0530%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637193630113242242&sdata=cPYmcthdgilh9lOiGDrwKwOt7cn%2BvBcT%2F8PhRs92x8I%3D&reserved=0
>>
>> Here is the text from the PPR.
>> Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
>> number of least significant bits in the Initial APIC ID that indicate core ID
>> within a processor, in constructing per-core CPUID masks.
>> Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
>> (MNC) that the processor could theoretically support, not the actual number of
>> cores that are actually implemented or enabled on the processor, as indicated
>> by Core::X86::Cpuid::SizeId[NC].
>> Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
>> • ApicId[6] = Socket ID.
>> • ApicId[5:4] = Node ID.
>> • ApicId[3] = Logical CCX L3 complex ID
>> • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
>>
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>
> Acked-by: Igor Mammedov <imammedo@redhat.com>
If use a boolean variable, then I dont need all these handlers in
X86CPUDefinition. I just need to set a boolean variable here.
>
>> ---
>> target/i386/cpu.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index f33d8b77f5..f870f7c55b 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -3884,6 +3884,10 @@ static X86CPUDefinition builtin_x86_defs[] = {
>> .xlevel = 0x8000001E,
>> .model_id = "AMD EPYC Processor",
>> .cache_info = &epyc_cache_info,
>> + .apicid_from_cpu_idx = x86_apicid_from_cpu_idx_epyc,
>> + .topo_ids_from_apicid = x86_topo_ids_from_apicid_epyc,
>> + .apicid_from_topo_ids = x86_apicid_from_topo_ids_epyc,
>> + .apicid_pkg_offset = apicid_pkg_offset_epyc,
>> .versions = (X86CPUVersionDefinition[]) {
>> { .version = 1 },
>> {
>>
>>
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 14/16] hw/i386: Move arch_id decode inside x86_cpus_init
2020-03-09 15:21 ` Igor Mammedov
@ 2020-03-09 19:31 ` Babu Moger
2020-03-10 8:35 ` Igor Mammedov
0 siblings, 1 reply; 45+ messages in thread
From: Babu Moger @ 2020-03-09 19:31 UTC (permalink / raw)
To: Igor Mammedov; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On 3/9/20 10:21 AM, Igor Mammedov wrote:
> On Tue, 03 Mar 2020 13:58:24 -0600
> Babu Moger <babu.moger@amd.com> wrote:
>
>> Apicid calculation depends on knowing the total number of numa nodes
>> for EPYC cpu models. Right now, we are calculating the arch_id while
>> parsing the numa(parse_numa). At this time, it is not known how many
>> total numa nodes are configured in the system.
>>
>> Move the arch_id inside x86_cpus_init. At this time smp parameter is already
>> completed and numa node information is available.
>>
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>> ---
>> hw/i386/x86.c | 17 +++++++++++------
>> 1 file changed, 11 insertions(+), 6 deletions(-)
>>
>> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
>> index d46dd4ad9e..66998b065c 100644
>> --- a/hw/i386/x86.c
>> +++ b/hw/i386/x86.c
>> @@ -121,6 +121,9 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
>> MachineState *ms = MACHINE(x86ms);
>> MachineClass *mc = MACHINE_GET_CLASS(x86ms);
>>
>> + /* Initialize apicid handlers first */
>> + cpu_x86_init_apicid_fns(ms);
>> +
>> x86_cpu_set_default_version(default_cpu_version);
>>
>> /*
>> @@ -134,6 +137,12 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
>> x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms,
>> ms->smp.max_cpus - 1) + 1;
>> possible_cpus = mc->possible_cpu_arch_ids(ms);
>> +
>> + for (i = 0; i < ms->smp.cpus; i++) {
>> + ms->possible_cpus->cpus[i].arch_id =
>> + x86_cpu_apic_id_from_index(x86ms, i);
>> + }
>> +
>> for (i = 0; i < ms->smp.cpus; i++) {
>> x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal);
>> }
>> @@ -158,8 +167,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
>> init_topo_info(&topo_info, x86ms);
>>
>> assert(idx < ms->possible_cpus->len);
>> - x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
>> - &topo_info, &topo_ids);
>> + x86_topo_ids_from_idx(&topo_info, idx, &topo_ids);
> not necessary if default x86ms->topo_ids_from_apicid were initialized from x86 machine class
>
> I also wonder if this default contraption we have is going to work
> in case of EPYC cpu (i.e. is would generate valid nodeids).
From what I understand, we call this x86_get_default_cpu_node_id only when
the user does not specify the numa binding requirements. We tried to
generate the default node it for a given config. This works fine for EPYC
also. I am not sure about changing this right now. what do you think?
>
> Bot instead of than trying to fix it if it's broken,
> I'd rather deprecate and drop get_default_cpu_node_id() requiring users
> to explicitly define CPU mapping to numa nodes.
> That would be consistent with req for explicit RAM for numa nodes
> (postponed till 5.1 due to libvirt not being ready),
> i.e if one wants numa, one should explicitly provide necessary mapping
> or machine won't start.
>
>
>> return topo_ids.pkg_id % ms->numa_state->num_nodes;
>> }
>>
>> @@ -193,10 +201,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
>>
>> ms->possible_cpus->cpus[i].type = ms->cpu_type;
>> ms->possible_cpus->cpus[i].vcpus_count = 1;
>> - ms->possible_cpus->cpus[i].arch_id =
>> - x86_cpu_apic_id_from_index(x86ms, i);
>> - x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
>> - &topo_info, &topo_ids);
>> + x86_topo_ids_from_idx(&topo_info, i, &topo_ids);
> ditto
>
>> ms->possible_cpus->cpus[i].props.has_socket_id = true;
>> ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
>> if (x86ms->smp_dies > 1) {
>>
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 13/16] target/i386: Add EPYC model specific handlers
2020-03-09 19:12 ` Babu Moger
@ 2020-03-10 8:25 ` Igor Mammedov
0 siblings, 0 replies; 45+ messages in thread
From: Igor Mammedov @ 2020-03-10 8:25 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On Mon, 9 Mar 2020 14:12:10 -0500
Babu Moger <babu.moger@amd.com> wrote:
> On 3/9/20 10:03 AM, Igor Mammedov wrote:
> > On Tue, 03 Mar 2020 13:58:16 -0600
> > Babu Moger <babu.moger@amd.com> wrote:
> >
> >> Add the new EPYC model specific handlers to fix the apicid decoding.
> >>
> >> The APIC ID is decoded based on the sequence sockets->dies->cores->threads.
> >> This works fine for most standard AMD and other vendors' configurations,
> >> but this decoding sequence does not follow that of AMD's APIC ID enumeration
> >> strictly. In some cases this can cause CPU topology inconsistency.
> >>
> >> When booting a guest VM, the kernel tries to validate the topology, and finds
> >> it inconsistent with the enumeration of EPYC cpu models. The more details are
> >> in the bug https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.redhat.com%2Fshow_bug.cgi%3Fid%3D1728166&data=02%7C01%7Cbabu.moger%40amd.com%7C3ddda6803d584aac171b08d7c43b0530%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637193630113242242&sdata=3TkNY2O8HWBqaOrmO8QQoxlzvIv2oEdTO1P9k6VglmU%3D&reserved=0.
> >>
> >> To fix the problem we need to build the topology as per the Processor
> >> Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
> >> Processors.
> >> It is available at https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.amd.com%2Fsystem%2Ffiles%2FTechDocs%2F55570-B1_PUB.zip&data=02%7C01%7Cbabu.moger%40amd.com%7C3ddda6803d584aac171b08d7c43b0530%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637193630113242242&sdata=cPYmcthdgilh9lOiGDrwKwOt7cn%2BvBcT%2F8PhRs92x8I%3D&reserved=0
> >>
> >> Here is the text from the PPR.
> >> Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
> >> number of least significant bits in the Initial APIC ID that indicate core ID
> >> within a processor, in constructing per-core CPUID masks.
> >> Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
> >> (MNC) that the processor could theoretically support, not the actual number of
> >> cores that are actually implemented or enabled on the processor, as indicated
> >> by Core::X86::Cpuid::SizeId[NC].
> >> Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
> >> • ApicId[6] = Socket ID.
> >> • ApicId[5:4] = Node ID.
> >> • ApicId[3] = Logical CCX L3 complex ID
> >> • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
> >>
> >> Signed-off-by: Babu Moger <babu.moger@amd.com>
> >
> > Acked-by: Igor Mammedov <imammedo@redhat.com>
>
> If use a boolean variable, then I dont need all these handlers in
> X86CPUDefinition. I just need to set a boolean variable here.
agreed, that would be better
> >
> >> ---
> >> target/i386/cpu.c | 4 ++++
> >> 1 file changed, 4 insertions(+)
> >>
> >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> >> index f33d8b77f5..f870f7c55b 100644
> >> --- a/target/i386/cpu.c
> >> +++ b/target/i386/cpu.c
> >> @@ -3884,6 +3884,10 @@ static X86CPUDefinition builtin_x86_defs[] = {
> >> .xlevel = 0x8000001E,
> >> .model_id = "AMD EPYC Processor",
> >> .cache_info = &epyc_cache_info,
> >> + .apicid_from_cpu_idx = x86_apicid_from_cpu_idx_epyc,
> >> + .topo_ids_from_apicid = x86_topo_ids_from_apicid_epyc,
> >> + .apicid_from_topo_ids = x86_apicid_from_topo_ids_epyc,
> >> + .apicid_pkg_offset = apicid_pkg_offset_epyc,
> >> .versions = (X86CPUVersionDefinition[]) {
> >> { .version = 1 },
> >> {
> >>
> >>
> >
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 11/16] target/i386: Load apicid model specific handlers from X86CPUDefinition
2020-03-09 19:04 ` Babu Moger
@ 2020-03-10 8:27 ` Igor Mammedov
0 siblings, 0 replies; 45+ messages in thread
From: Igor Mammedov @ 2020-03-10 8:27 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On Mon, 9 Mar 2020 14:04:39 -0500
Babu Moger <babu.moger@amd.com> wrote:
> On 3/9/20 9:49 AM, Igor Mammedov wrote:
> > On Tue, 03 Mar 2020 13:58:03 -0600
> > Babu Moger <babu.moger@amd.com> wrote:
> >
> >> Load the model specific handlers if available or else default handlers
> >> will be loaded. Add the model specific handlers if apicid decoding
> >> differs from the standard sequential numbering.
> >>
> >
> > this is still the old version of the patch and hadn't addressed feedback from v4
>
> Yes. I was confused little bit about it. Will fix it.
>
> >
> >> Signed-off-by: Babu Moger <babu.moger@amd.com>
> >> ---
> >> target/i386/cpu.c | 34 ++++++++++++++++++++++++++++++++++
> >> target/i386/cpu.h | 1 +
> >> 2 files changed, 35 insertions(+)
> >>
> >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> >> index c75cf744ab..f33d8b77f5 100644
> >> --- a/target/i386/cpu.c
> >> +++ b/target/i386/cpu.c
> >> @@ -51,6 +51,7 @@
> >> #include "sysemu/sysemu.h"
> >> #include "sysemu/tcg.h"
> >> #include "hw/qdev-properties.h"
> >> +#include "hw/i386/x86.h"
> > this dependency shouldn't be here, see below
>
> ok.
>
> >
> >> #include "hw/i386/topology.h"
> >> #ifndef CONFIG_USER_ONLY
> >> #include "exec/address-spaces.h"
> > [...]
> >> +void cpu_x86_init_apicid_fns(MachineState *machine)
> > it should be something like:
> > x86_use_epyc_apic_id_encoding(char *cpu_type)
> > try to avoid pulling in unnecessary dependency on Machine into cpu.c
>
> Ok.
>
> >
> >> +{
> >> + X86CPUClass *xcc = X86_CPU_CLASS(object_class_by_name(machine->cpu_type));
> >> + X86CPUModel *model = xcc->model;
> >> + X86CPUDefinition *def = model->cpudef;
> >> + X86MachineState *x86ms = X86_MACHINE(machine);
> >> +
> >> + if (def) {
> >> + if (def->apicid_from_cpu_idx) {
> >> + x86ms->apicid_from_cpu_idx = def->apicid_from_cpu_idx;
> >> + }
> >> + if (def->topo_ids_from_apicid) {
> >> + x86ms->topo_ids_from_apicid = def->topo_ids_from_apicid;
> >> + }
> >> + if (def->apicid_from_topo_ids) {
> >> + x86ms->apicid_from_topo_ids = def->apicid_from_topo_ids;
> >> + }
> >> + if (def->apicid_pkg_offset) {
> >> + x86ms->apicid_pkg_offset = def->apicid_pkg_offset;
> >> + }
> >> + }
> >> +}
> >
> > It was suggested to move defaults initialization to x86_machine_class_init()
>
> ok. We don't need the above changes. I will use the boolean as you
> suggested and call this function in x86_cpus_init() to initialize the EPYC
> specific handler. Something similar like this below..
>
> x86_use_epyc_apic_id_encoding(char *cpu_type)
> {
> X86CPUClass *xcc = ... cpu_type ...
> return xcc->model->cpudef->use_epyc_apic_id_encoding
> }
>
> x86_cpus_init()
> {
> if (x86_use_epyc_apic_id_encoding(ms->cpu_type)) {
> x86ms->apicid_from_cpu_idx = ...epyc...
> x86ms->topo_ids_from_apicid = ...epyc...
> x86ms->apicid_from_topo_ids = ...epyc...
> x86ms->apicid_pkg_offset = ...epyc...
> }
> }
>
> Sounds right?
yes, something like this
>
> >
> > as was suggested at
> > [PATCH v4 12/16] hw/i386: Use the apicid handlers from X86MachineState
> > and acked by Eduardo
> >
> >> +
> >> static CPUCaches epyc_cache_info = {
> >> .l1d_cache = &(CPUCacheInfo) {
> >> .type = DATA_CACHE,
> >> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> >> index 20abbda647..34f0d994ef 100644
> >> --- a/target/i386/cpu.h
> >> +++ b/target/i386/cpu.h
> >> @@ -1895,6 +1895,7 @@ void cpu_clear_apic_feature(CPUX86State *env);
> >> void host_cpuid(uint32_t function, uint32_t count,
> >> uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
> >> void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
> >> +void cpu_x86_init_apicid_fns(MachineState *machine);
> >>
> >> /* helper.c */
> >> bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> >>
> >
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 12/16] hw/i386: Use the apicid handlers from X86MachineState
2020-03-09 19:08 ` Babu Moger
@ 2020-03-10 8:31 ` Igor Mammedov
0 siblings, 0 replies; 45+ messages in thread
From: Igor Mammedov @ 2020-03-10 8:31 UTC (permalink / raw)
To: Babu Moger; +Cc: qemu-devel, pbonzini, rth, ehabkost, mst
On Mon, 9 Mar 2020 14:08:53 -0500
Babu Moger <babu.moger@amd.com> wrote:
> On 3/9/20 10:01 AM, Igor Mammedov wrote:
> > On Tue, 03 Mar 2020 13:58:10 -0600
> > Babu Moger <babu.moger@amd.com> wrote:
> >
> >> Check and Load the apicid handlers from X86CPUDefinition if available.
> >> Update the calling convention for the apicid handlers.
> >>
> >> Signed-off-by: Babu Moger <babu.moger@amd.com>
> >
> >
> >> ---
> >> hw/i386/pc.c | 6 +++---
> >> hw/i386/x86.c | 11 +++++++----
> >> 2 files changed, 10 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> >> index 17cce3f074..c600ba0432 100644
> >> --- a/hw/i386/pc.c
> >> +++ b/hw/i386/pc.c
> >> @@ -1581,14 +1581,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
> >> topo_ids.die_id = cpu->die_id;
> >> topo_ids.core_id = cpu->core_id;
> >> topo_ids.smt_id = cpu->thread_id;
> >> - cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids);
> >> + cpu->apic_id = x86ms->apicid_from_topo_ids(&topo_info, &topo_ids);
> >> }
> >>
> >> cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
> >> if (!cpu_slot) {
> >> MachineState *ms = MACHINE(pcms);
> >>
> >> - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
> >> + x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
> > this (including other similar) change(s) to callbacks should go to 11/16
>
> So, you mean patch #11 and #12 should be squashed together. Is that right?
yes, modulo cpu_x86_init_apicid_fns() which sets defaults (it should be machine's
class_init)
>
> >
> >> error_setg(errp,
> >> "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
> >> " APIC ID %" PRIu32 ", valid index range 0:%d",
> >> @@ -1609,7 +1609,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
> >> /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
> >> * once -smp refactoring is complete and there will be CPU private
> >> * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
> >> - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
> >> + x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
> >> if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
> >> error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
> >> " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
> >> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
> >> index 15b7815bb0..d46dd4ad9e 100644
> >> --- a/hw/i386/x86.c
> >> +++ b/hw/i386/x86.c
> >> @@ -86,7 +86,7 @@ uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
> >>
> >> init_topo_info(&topo_info, x86ms);
> >>
> >> - correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index);
> >> + correct_id = x86ms->apicid_from_cpu_idx(&topo_info, cpu_index);
> >> if (x86mc->compat_apic_id_mode) {
> >> if (cpu_index != correct_id && !warned && !qtest_enabled()) {
> >> error_report("APIC IDs set in compatibility mode, "
> >> @@ -158,8 +158,8 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
> >> init_topo_info(&topo_info, x86ms);
> >>
> >> assert(idx < ms->possible_cpus->len);
> >> - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
> >> - &topo_info, &topo_ids);
> >> + x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
> >> + &topo_info, &topo_ids);
> >> return topo_ids.pkg_id % ms->numa_state->num_nodes;
> >> }
> >>
> >> @@ -179,6 +179,9 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
> >> return ms->possible_cpus;
> >> }
> >>
> >> + /* Initialize apicid handlers */
> >> + cpu_x86_init_apicid_fns(ms);
> >> +
> >> ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
> >> sizeof(CPUArchId) * max_cpus);
> >> ms->possible_cpus->len = max_cpus;
> >> @@ -192,7 +195,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
> >> ms->possible_cpus->cpus[i].vcpus_count = 1;
> >> ms->possible_cpus->cpus[i].arch_id =
> >> x86_cpu_apic_id_from_index(x86ms, i);
> >> - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
> >> + x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
> >> &topo_info, &topo_ids);
> >
> > not aligned properly
> >
> >> ms->possible_cpus->cpus[i].props.has_socket_id = true;
> >> ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
> >>
> >
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 14/16] hw/i386: Move arch_id decode inside x86_cpus_init
2020-03-09 19:31 ` Babu Moger
@ 2020-03-10 8:35 ` Igor Mammedov
2020-03-10 20:05 ` Babu Moger
0 siblings, 1 reply; 45+ messages in thread
From: Igor Mammedov @ 2020-03-10 8:35 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On Mon, 9 Mar 2020 14:31:31 -0500
Babu Moger <babu.moger@amd.com> wrote:
> On 3/9/20 10:21 AM, Igor Mammedov wrote:
> > On Tue, 03 Mar 2020 13:58:24 -0600
> > Babu Moger <babu.moger@amd.com> wrote:
> >
> >> Apicid calculation depends on knowing the total number of numa nodes
> >> for EPYC cpu models. Right now, we are calculating the arch_id while
> >> parsing the numa(parse_numa). At this time, it is not known how many
> >> total numa nodes are configured in the system.
> >>
> >> Move the arch_id inside x86_cpus_init. At this time smp parameter is already
> >> completed and numa node information is available.
> >>
> >> Signed-off-by: Babu Moger <babu.moger@amd.com>
> >> ---
> >> hw/i386/x86.c | 17 +++++++++++------
> >> 1 file changed, 11 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
> >> index d46dd4ad9e..66998b065c 100644
> >> --- a/hw/i386/x86.c
> >> +++ b/hw/i386/x86.c
> >> @@ -121,6 +121,9 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
> >> MachineState *ms = MACHINE(x86ms);
> >> MachineClass *mc = MACHINE_GET_CLASS(x86ms);
> >>
> >> + /* Initialize apicid handlers first */
> >> + cpu_x86_init_apicid_fns(ms);
> >> +
> >> x86_cpu_set_default_version(default_cpu_version);
> >>
> >> /*
> >> @@ -134,6 +137,12 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
> >> x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms,
> >> ms->smp.max_cpus - 1) + 1;
> >> possible_cpus = mc->possible_cpu_arch_ids(ms);
> >> +
> >> + for (i = 0; i < ms->smp.cpus; i++) {
> >> + ms->possible_cpus->cpus[i].arch_id =
> >> + x86_cpu_apic_id_from_index(x86ms, i);
> >> + }
> >> +
> >> for (i = 0; i < ms->smp.cpus; i++) {
> >> x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal);
> >> }
> >> @@ -158,8 +167,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
> >> init_topo_info(&topo_info, x86ms);
> >>
> >> assert(idx < ms->possible_cpus->len);
> >> - x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
> >> - &topo_info, &topo_ids);
> >> + x86_topo_ids_from_idx(&topo_info, idx, &topo_ids);
> > not necessary if default x86ms->topo_ids_from_apicid were initialized from x86 machine class
> >
> > I also wonder if this default contraption we have is going to work
> > in case of EPYC cpu (i.e. is would generate valid nodeids).
>
> From what I understand, we call this x86_get_default_cpu_node_id only when
> the user does not specify the numa binding requirements. We tried to
> generate the default node it for a given config. This works fine for EPYC
> also. I am not sure about changing this right now. what do you think?
if it work for EPYC with default x86_topo_ids_from_idx() then it's fine.
Just keep callback here, given that callback is always initialized early (class_init)
there is no point to create mix of callback/non-callback usage.
> >
> > Bot instead of than trying to fix it if it's broken,
> > I'd rather deprecate and drop get_default_cpu_node_id() requiring users
> > to explicitly define CPU mapping to numa nodes.
> > That would be consistent with req for explicit RAM for numa nodes
> > (postponed till 5.1 due to libvirt not being ready),
> > i.e if one wants numa, one should explicitly provide necessary mapping
> > or machine won't start.
> >
> >
> >> return topo_ids.pkg_id % ms->numa_state->num_nodes;
> >> }
> >>
> >> @@ -193,10 +201,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
> >>
> >> ms->possible_cpus->cpus[i].type = ms->cpu_type;
> >> ms->possible_cpus->cpus[i].vcpus_count = 1;
> >> - ms->possible_cpus->cpus[i].arch_id =
> >> - x86_cpu_apic_id_from_index(x86ms, i);
> >> - x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
> >> - &topo_info, &topo_ids);
> >> + x86_topo_ids_from_idx(&topo_info, i, &topo_ids);
> > ditto
> >
> >> ms->possible_cpus->cpus[i].props.has_socket_id = true;
> >> ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
> >> if (x86ms->smp_dies > 1) {
> >>
> >
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
` (16 preceding siblings ...)
2020-03-08 13:25 ` [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Michael S. Tsirkin
@ 2020-03-10 8:40 ` Igor Mammedov
2020-03-10 20:07 ` Babu Moger
17 siblings, 1 reply; 45+ messages in thread
From: Igor Mammedov @ 2020-03-10 8:40 UTC (permalink / raw)
To: Babu Moger; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On Tue, 03 Mar 2020 13:56:51 -0600
Babu Moger <babu.moger@amd.com> wrote:
> This series fixes APIC ID encoding problem reported on AMD EPYC cpu models.
> https://bugzilla.redhat.com/show_bug.cgi?id=1728166
>
> Currently, the APIC ID is decoded based on the sequence
> sockets->dies->cores->threads. This works for most standard AMD and other
> vendors' configurations, but this decoding sequence does not follow that of
> AMD's APIC ID enumeration strictly. In some cases this can cause CPU topology
> inconsistency. When booting a guest VM, the kernel tries to validate the
> topology, and finds it inconsistent with the enumeration of EPYC cpu models.
>
> To fix the problem we need to build the topology as per the Processor
> Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
> Processors. The documentation is available from the bugzilla Link below.
>
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
>
> Here is the text from the PPR.
> Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
> number of least significant bits in the Initial APIC ID that indicate core ID
> within a processor, in constructing per-core CPUID masks.
> Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
> (MNC) that the processor could theoretically support, not the actual number of
> cores that are actually implemented or enabled on the processor, as indicated
> by Core::X86::Cpuid::SizeId[NC].
> Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
> • ApicId[6] = Socket ID.
> • ApicId[5:4] = Node ID.
> • ApicId[3] = Logical CCX L3 complex ID
> • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
>
> v5:
> Generated the patches on top of git://github.com/ehabkost/qemu.git (x86-next).
> Changes from v4.
> 1. Re-arranged the patches 2 and 4 as suggested by Igor.
> 2. Kept the apicid handler functions inside X86MachineState as discussed.
> These handlers are loaded from X86CPUDefinitions.
> 3. Removed unnecessary X86CPUstate initialization from x86_cpu_new. Suggested
> by Igor.
> 4. And other minor changes related to patch format.
>
> v4:
> https://lore.kernel.org/qemu-devel/158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com/
> Changes from v3.
> 1. Moved the arch_id calculation inside the function x86_cpus_init. With this change,
> we dont need to change common numa code.(suggested by Igor)
> 2. Introduced the model specific handlers inside X86CPUDefinitions.
> These handlers are loaded into X86MachineState during the init.
> 3. Removed llc_id from x86CPU.
> 4. Removed init_apicid_fn hanlder from MachineClass. Kept all the code changes
> inside the x86.
> 5. Added new handler function apicid_pkg_offset for pkg_offset calculation.
> 6. And some Other minor changes.
>
> v3:
> https://lore.kernel.org/qemu-devel/157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com/
> 1. Consolidated the topology information in structure X86CPUTopoInfo.
> 2. Changed the ccx_id to llc_id as commented by upstream.
> 3. Generalized the apic id decoding. It is mostly similar to current apic id
> except that it adds new field llc_id when numa configured. Removes all the
> hardcoded values.
> 4. Removed the earlier parse_numa split. And moved the numa node initialization
> inside the numa_complete_configuration. This is bit cleaner as commented by
> Eduardo.
> 5. Added new function init_apicid_fn inside machine_class structure. This
> will be used to update the apic id handler specific to cpu model.
> 6. Updated the cpuid unit tests.
> 7. TODO : Need to figure out how to dynamically update the handlers using cpu models.
> I might some guidance on that.
>
> v2:
> https://lore.kernel.org/qemu-devel/156779689013.21957.1631551572950676212.stgit@localhost.localdomain/
> 1. Introduced the new property epyc to enable new epyc mode.
> 2. Separated the epyc mode and non epyc mode function.
> 3. Introduced function pointers in PCMachineState to handle the
> differences.
> 4. Mildly tested different combinations to make things are working as expected.
> 5. TODO : Setting the epyc feature bit needs to be worked out. This feature is
> supported only on AMD EPYC models. I may need some guidance on that.
>
> v1:
> https://lore.kernel.org/qemu-devel/20190731232032.51786-1-babu.moger@amd.com/
There will be soft freeze soon,
if you respin it soon, I'll review it ASAP.
I hope there won't be anything to amend, so
we could try merging it this week (otherwise
it will be postponed till next release).
I guess it should go via Eduardo's tree.
>
> ---
>
> Babu Moger (16):
> hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
> hw/i386: Introduce X86CPUTopoInfo to contain topology info
> hw/i386: Consolidate topology functions
> machine: Add SMP Sockets in CpuTopology
> hw/i386: Remove unnecessary initialization in x86_cpu_new
> hw/i386: Update structures to save the number of nodes per package
> hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids
> hw/386: Add EPYC mode topology decoding functions
> target/i386: Cleanup and use the EPYC mode topology functions
> hw/i386: Introduce apicid functions inside X86MachineState
> target/i386: Load apicid model specific handlers from X86CPUDefinition
> hw/i386: Use the apicid handlers from X86MachineState
> target/i386: Add EPYC model specific handlers
> hw/i386: Move arch_id decode inside x86_cpus_init
> i386: Fix pkg_id offset for EPYC cpu models
> tests: Update the Unit tests
>
>
> hw/core/machine.c | 1
> hw/i386/pc.c | 54 ++++++-----
> hw/i386/x86.c | 72 ++++++++++----
> include/hw/boards.h | 2
> include/hw/i386/topology.h | 215 ++++++++++++++++++++++++++++++------------
> include/hw/i386/x86.h | 12 ++
> target/i386/cpu.c | 224 +++++++++++++++++---------------------------
> target/i386/cpu.h | 3 +
> tests/test-x86-cpuid.c | 115 +++++++++++++----------
> vl.c | 1
> 10 files changed, 403 insertions(+), 296 deletions(-)
>
> --
> Signature
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 14/16] hw/i386: Move arch_id decode inside x86_cpus_init
2020-03-10 8:35 ` Igor Mammedov
@ 2020-03-10 20:05 ` Babu Moger
0 siblings, 0 replies; 45+ messages in thread
From: Babu Moger @ 2020-03-10 20:05 UTC (permalink / raw)
To: Igor Mammedov; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On 3/10/20 3:35 AM, Igor Mammedov wrote:
> On Mon, 9 Mar 2020 14:31:31 -0500
> Babu Moger <babu.moger@amd.com> wrote:
>
>> On 3/9/20 10:21 AM, Igor Mammedov wrote:
>>> On Tue, 03 Mar 2020 13:58:24 -0600
>>> Babu Moger <babu.moger@amd.com> wrote:
>>>
>>>> Apicid calculation depends on knowing the total number of numa nodes
>>>> for EPYC cpu models. Right now, we are calculating the arch_id while
>>>> parsing the numa(parse_numa). At this time, it is not known how many
>>>> total numa nodes are configured in the system.
>>>>
>>>> Move the arch_id inside x86_cpus_init. At this time smp parameter is already
>>>> completed and numa node information is available.
>>>>
>>>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>>>> ---
>>>> hw/i386/x86.c | 17 +++++++++++------
>>>> 1 file changed, 11 insertions(+), 6 deletions(-)
>>>>
>>>> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
>>>> index d46dd4ad9e..66998b065c 100644
>>>> --- a/hw/i386/x86.c
>>>> +++ b/hw/i386/x86.c
>>>> @@ -121,6 +121,9 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
>>>> MachineState *ms = MACHINE(x86ms);
>>>> MachineClass *mc = MACHINE_GET_CLASS(x86ms);
>>>>
>>>> + /* Initialize apicid handlers first */
>>>> + cpu_x86_init_apicid_fns(ms);
>>>> +
>>>> x86_cpu_set_default_version(default_cpu_version);
>>>>
>>>> /*
>>>> @@ -134,6 +137,12 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
>>>> x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms,
>>>> ms->smp.max_cpus - 1) + 1;
>>>> possible_cpus = mc->possible_cpu_arch_ids(ms);
>>>> +
>>>> + for (i = 0; i < ms->smp.cpus; i++) {
>>>> + ms->possible_cpus->cpus[i].arch_id =
>>>> + x86_cpu_apic_id_from_index(x86ms, i);
>>>> + }
>>>> +
>>>> for (i = 0; i < ms->smp.cpus; i++) {
>>>> x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal);
>>>> }
>>>> @@ -158,8 +167,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
>>>> init_topo_info(&topo_info, x86ms);
>>>>
>>>> assert(idx < ms->possible_cpus->len);
>>>> - x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
>>>> - &topo_info, &topo_ids);
>>>> + x86_topo_ids_from_idx(&topo_info, idx, &topo_ids);
>>> not necessary if default x86ms->topo_ids_from_apicid were initialized from x86 machine class
>>>
>>> I also wonder if this default contraption we have is going to work
>>> in case of EPYC cpu (i.e. is would generate valid nodeids).
>>
>> From what I understand, we call this x86_get_default_cpu_node_id only when
>> the user does not specify the numa binding requirements. We tried to
>> generate the default node it for a given config. This works fine for EPYC
>> also. I am not sure about changing this right now. what do you think?
>
> if it work for EPYC with default x86_topo_ids_from_idx() then it's fine.
>
> Just keep callback here, given that callback is always initialized early (class_init)
> there is no point to create mix of callback/non-callback usage.
Ok. Done.
We did not have callback for x86_topo_ids_from_idx explicity. Now, I have
added this function as callback and using the callback here.
>
>>>
>>> Bot instead of than trying to fix it if it's broken,
>>> I'd rather deprecate and drop get_default_cpu_node_id() requiring users
>>> to explicitly define CPU mapping to numa nodes.
>>> That would be consistent with req for explicit RAM for numa nodes
>>> (postponed till 5.1 due to libvirt not being ready),
>>> i.e if one wants numa, one should explicitly provide necessary mapping
>>> or machine won't start.
>>>
>>>
>>>> return topo_ids.pkg_id % ms->numa_state->num_nodes;
>>>> }
>>>>
>>>> @@ -193,10 +201,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
>>>>
>>>> ms->possible_cpus->cpus[i].type = ms->cpu_type;
>>>> ms->possible_cpus->cpus[i].vcpus_count = 1;
>>>> - ms->possible_cpus->cpus[i].arch_id =
>>>> - x86_cpu_apic_id_from_index(x86ms, i);
>>>> - x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
>>>> - &topo_info, &topo_ids);
>>>> + x86_topo_ids_from_idx(&topo_info, i, &topo_ids);
>>> ditto
>>>
>>>> ms->possible_cpus->cpus[i].props.has_socket_id = true;
>>>> ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
>>>> if (x86ms->smp_dies > 1) {
>>>>
>>>
>>
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model
2020-03-10 8:40 ` Igor Mammedov
@ 2020-03-10 20:07 ` Babu Moger
0 siblings, 0 replies; 45+ messages in thread
From: Babu Moger @ 2020-03-10 20:07 UTC (permalink / raw)
To: Igor Mammedov; +Cc: ehabkost, mst, qemu-devel, pbonzini, rth
On 3/10/20 3:40 AM, Igor Mammedov wrote:
> On Tue, 03 Mar 2020 13:56:51 -0600
> Babu Moger <babu.moger@amd.com> wrote:
>
>> This series fixes APIC ID encoding problem reported on AMD EPYC cpu models.
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.redhat.com%2Fshow_bug.cgi%3Fid%3D1728166&data=02%7C01%7Cbabu.moger%40amd.com%7C45a40d6e3f3e43db7f1c08d7c4ceb6ea%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637194264422137307&sdata=aK22ORKQVO91LQg8S5HLIkwokhSr1gZtbiPBT6f1xfY%3D&reserved=0
>>
>> Currently, the APIC ID is decoded based on the sequence
>> sockets->dies->cores->threads. This works for most standard AMD and other
>> vendors' configurations, but this decoding sequence does not follow that of
>> AMD's APIC ID enumeration strictly. In some cases this can cause CPU topology
>> inconsistency. When booting a guest VM, the kernel tries to validate the
>> topology, and finds it inconsistent with the enumeration of EPYC cpu models.
>>
>> To fix the problem we need to build the topology as per the Processor
>> Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
>> Processors. The documentation is available from the bugzilla Link below.
>>
>> Link: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.kernel.org%2Fshow_bug.cgi%3Fid%3D206537&data=02%7C01%7Cbabu.moger%40amd.com%7C45a40d6e3f3e43db7f1c08d7c4ceb6ea%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637194264422137307&sdata=yRvpeioi434loufborv7ZemhIezNEF2yv9Lt1740Gn4%3D&reserved=0
>>
>> Here is the text from the PPR.
>> Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
>> number of least significant bits in the Initial APIC ID that indicate core ID
>> within a processor, in constructing per-core CPUID masks.
>> Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
>> (MNC) that the processor could theoretically support, not the actual number of
>> cores that are actually implemented or enabled on the processor, as indicated
>> by Core::X86::Cpuid::SizeId[NC].
>> Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
>> • ApicId[6] = Socket ID.
>> • ApicId[5:4] = Node ID.
>> • ApicId[3] = Logical CCX L3 complex ID
>> • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
>>
>> v5:
>> Generated the patches on top of git://github.com/ehabkost/qemu.git (x86-next).
>> Changes from v4.
>> 1. Re-arranged the patches 2 and 4 as suggested by Igor.
>> 2. Kept the apicid handler functions inside X86MachineState as discussed.
>> These handlers are loaded from X86CPUDefinitions.
>> 3. Removed unnecessary X86CPUstate initialization from x86_cpu_new. Suggested
>> by Igor.
>> 4. And other minor changes related to patch format.
>>
>> v4:
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fqemu-devel%2F158161767653.48948.10578064482878399556.stgit%40naples-babu.amd.com%2F&data=02%7C01%7Cbabu.moger%40amd.com%7C45a40d6e3f3e43db7f1c08d7c4ceb6ea%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637194264422137307&sdata=Mk0f4lBq8dqfowge9Bqab8b%2B89eGFJBU6XJs6S%2F5CKQ%3D&reserved=0
>> Changes from v3.
>> 1. Moved the arch_id calculation inside the function x86_cpus_init. With this change,
>> we dont need to change common numa code.(suggested by Igor)
>> 2. Introduced the model specific handlers inside X86CPUDefinitions.
>> These handlers are loaded into X86MachineState during the init.
>> 3. Removed llc_id from x86CPU.
>> 4. Removed init_apicid_fn hanlder from MachineClass. Kept all the code changes
>> inside the x86.
>> 5. Added new handler function apicid_pkg_offset for pkg_offset calculation.
>> 6. And some Other minor changes.
>>
>> v3:
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fqemu-devel%2F157541968844.46157.17994918142533791313.stgit%40naples-babu.amd.com%2F&data=02%7C01%7Cbabu.moger%40amd.com%7C45a40d6e3f3e43db7f1c08d7c4ceb6ea%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637194264422137307&sdata=Ha6v2Bwa%2BiIChPxIeJhuzsr%2F9VEa5%2BB73l90ABPhpgg%3D&reserved=0
>> 1. Consolidated the topology information in structure X86CPUTopoInfo.
>> 2. Changed the ccx_id to llc_id as commented by upstream.
>> 3. Generalized the apic id decoding. It is mostly similar to current apic id
>> except that it adds new field llc_id when numa configured. Removes all the
>> hardcoded values.
>> 4. Removed the earlier parse_numa split. And moved the numa node initialization
>> inside the numa_complete_configuration. This is bit cleaner as commented by
>> Eduardo.
>> 5. Added new function init_apicid_fn inside machine_class structure. This
>> will be used to update the apic id handler specific to cpu model.
>> 6. Updated the cpuid unit tests.
>> 7. TODO : Need to figure out how to dynamically update the handlers using cpu models.
>> I might some guidance on that.
>>
>> v2:
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fqemu-devel%2F156779689013.21957.1631551572950676212.stgit%40localhost.localdomain%2F&data=02%7C01%7Cbabu.moger%40amd.com%7C45a40d6e3f3e43db7f1c08d7c4ceb6ea%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637194264422137307&sdata=q1KrQrdSHBul%2F36gx5eBZZTeK%2Bv3FQWxOMi7SfVcFgY%3D&reserved=0
>> 1. Introduced the new property epyc to enable new epyc mode.
>> 2. Separated the epyc mode and non epyc mode function.
>> 3. Introduced function pointers in PCMachineState to handle the
>> differences.
>> 4. Mildly tested different combinations to make things are working as expected.
>> 5. TODO : Setting the epyc feature bit needs to be worked out. This feature is
>> supported only on AMD EPYC models. I may need some guidance on that.
>>
>> v1:
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fqemu-devel%2F20190731232032.51786-1-babu.moger%40amd.com%2F&data=02%7C01%7Cbabu.moger%40amd.com%7C45a40d6e3f3e43db7f1c08d7c4ceb6ea%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637194264422137307&sdata=0EVG%2Ba3uJHkTtYlcOyU%2F%2BMLOM7nksU3pkSG1ocZIZdU%3D&reserved=0
>
> There will be soft freeze soon,
> if you respin it soon, I'll review it ASAP.
> I hope there won't be anything to amend, so
> we could try merging it this week (otherwise
> it will be postponed till next release).
Ok. Will send it ASAP.
>
> I guess it should go via Eduardo's tree.
>
>>
>> ---
>>
>> Babu Moger (16):
>> hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
>> hw/i386: Introduce X86CPUTopoInfo to contain topology info
>> hw/i386: Consolidate topology functions
>> machine: Add SMP Sockets in CpuTopology
>> hw/i386: Remove unnecessary initialization in x86_cpu_new
>> hw/i386: Update structures to save the number of nodes per package
>> hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids
>> hw/386: Add EPYC mode topology decoding functions
>> target/i386: Cleanup and use the EPYC mode topology functions
>> hw/i386: Introduce apicid functions inside X86MachineState
>> target/i386: Load apicid model specific handlers from X86CPUDefinition
>> hw/i386: Use the apicid handlers from X86MachineState
>> target/i386: Add EPYC model specific handlers
>> hw/i386: Move arch_id decode inside x86_cpus_init
>> i386: Fix pkg_id offset for EPYC cpu models
>> tests: Update the Unit tests
>>
>>
>> hw/core/machine.c | 1
>> hw/i386/pc.c | 54 ++++++-----
>> hw/i386/x86.c | 72 ++++++++++----
>> include/hw/boards.h | 2
>> include/hw/i386/topology.h | 215 ++++++++++++++++++++++++++++++------------
>> include/hw/i386/x86.h | 12 ++
>> target/i386/cpu.c | 224 +++++++++++++++++---------------------------
>> target/i386/cpu.h | 3 +
>> tests/test-x86-cpuid.c | 115 +++++++++++++----------
>> vl.c | 1
>> 10 files changed, 403 insertions(+), 296 deletions(-)
>>
>> --
>> Signature
>>
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 02/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info
2020-03-03 19:57 ` [PATCH v5 02/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info Babu Moger
2020-03-09 14:10 ` Igor Mammedov
@ 2020-03-10 23:04 ` Eduardo Habkost
1 sibling, 0 replies; 45+ messages in thread
From: Eduardo Habkost @ 2020-03-10 23:04 UTC (permalink / raw)
To: Babu Moger; +Cc: mst, qemu-devel, imammedo, pbonzini, rth
On Tue, Mar 03, 2020 at 01:57:05PM -0600, Babu Moger wrote:
> This is an effort to re-arrange few data structure for better readability.
>
> 1. Add X86CPUTopoInfo which will have all the topology informations
> required to build the cpu topology. There is no functional changes.
> 2. Introduce init_topo_info to initialize X86CPUTopoInfo members from
> X86MachineState.
>
> There is no functional changes.
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
I was queueing this one, but I had to dequeue. You forgot to
tests/test-x86-cpuid.c to use the new X86CPUTopoInfo argument.
--
Eduardo
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 16/16] tests: Update the Unit tests
2020-03-03 19:58 ` [PATCH v5 16/16] tests: Update the Unit tests Babu Moger
@ 2020-03-10 23:06 ` Eduardo Habkost
2020-03-10 23:09 ` Moger, Babu
0 siblings, 1 reply; 45+ messages in thread
From: Eduardo Habkost @ 2020-03-10 23:06 UTC (permalink / raw)
To: Babu Moger; +Cc: mst, qemu-devel, imammedo, pbonzini, rth
On Tue, Mar 03, 2020 at 01:58:38PM -0600, Babu Moger wrote:
> Since the topology routines have changed, update
> the unit tests to use the new APIs.
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
This has to be part of the patches that changed the function
interfaces, otherwise we break bisectability.
--
Eduardo
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH v5 16/16] tests: Update the Unit tests
2020-03-10 23:06 ` Eduardo Habkost
@ 2020-03-10 23:09 ` Moger, Babu
0 siblings, 0 replies; 45+ messages in thread
From: Moger, Babu @ 2020-03-10 23:09 UTC (permalink / raw)
To: Eduardo Habkost; +Cc: mst, qemu-devel, imammedo, pbonzini, rth
[AMD Official Use Only - Internal Distribution Only]
> -----Original Message-----
> From: Eduardo Habkost <ehabkost@redhat.com>
> Sent: Tuesday, March 10, 2020 6:06 PM
> To: Moger, Babu <Babu.Moger@amd.com>
> Cc: marcel.apfelbaum@gmail.com; pbonzini@redhat.com; rth@twiddle.net;
> mst@redhat.com; imammedo@redhat.com; qemu-devel@nongnu.org
> Subject: Re: [PATCH v5 16/16] tests: Update the Unit tests
>
> On Tue, Mar 03, 2020 at 01:58:38PM -0600, Babu Moger wrote:
> > Since the topology routines have changed, update
> > the unit tests to use the new APIs.
> >
> > Signed-off-by: Babu Moger <babu.moger@amd.com>
>
> This has to be part of the patches that changed the function
> interfaces, otherwise we break bisectability.
Yes. That is right. Will quash with other patch.
>
> --
> Eduardo
^ permalink raw reply [flat|nested] 45+ messages in thread
end of thread, other threads:[~2020-03-10 23:10 UTC | newest]
Thread overview: 45+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-03 19:56 [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Babu Moger
2020-03-03 19:56 ` [PATCH v5 01/16] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs Babu Moger
2020-03-03 19:57 ` [PATCH v5 02/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info Babu Moger
2020-03-09 14:10 ` Igor Mammedov
2020-03-10 23:04 ` Eduardo Habkost
2020-03-03 19:57 ` [PATCH v5 03/16] hw/i386: Consolidate topology functions Babu Moger
2020-03-03 19:57 ` [PATCH v5 04/16] machine: Add SMP Sockets in CpuTopology Babu Moger
2020-03-09 14:17 ` Igor Mammedov
2020-03-09 18:01 ` Babu Moger
2020-03-03 19:57 ` [PATCH v5 05/16] hw/i386: Remove unnecessary initialization in x86_cpu_new Babu Moger
2020-03-09 14:18 ` Igor Mammedov
2020-03-03 19:57 ` [PATCH v5 06/16] hw/i386: Update structures to save the number of nodes per package Babu Moger
2020-03-09 14:26 ` Igor Mammedov
2020-03-03 19:57 ` [PATCH v5 07/16] hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids Babu Moger
2020-03-03 19:57 ` [PATCH v5 08/16] hw/386: Add EPYC mode topology decoding functions Babu Moger
2020-03-03 19:57 ` [PATCH v5 09/16] target/i386: Cleanup and use the EPYC mode topology functions Babu Moger
2020-03-03 19:57 ` [PATCH v5 10/16] hw/i386: Introduce apicid functions inside X86MachineState Babu Moger
2020-03-09 14:34 ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 11/16] target/i386: Load apicid model specific handlers from X86CPUDefinition Babu Moger
2020-03-09 14:49 ` Igor Mammedov
2020-03-09 14:55 ` Igor Mammedov
2020-03-09 19:04 ` Babu Moger
2020-03-10 8:27 ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 12/16] hw/i386: Use the apicid handlers from X86MachineState Babu Moger
2020-03-09 15:01 ` Igor Mammedov
2020-03-09 19:08 ` Babu Moger
2020-03-10 8:31 ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 13/16] target/i386: Add EPYC model specific handlers Babu Moger
2020-03-09 15:03 ` Igor Mammedov
2020-03-09 19:12 ` Babu Moger
2020-03-10 8:25 ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 14/16] hw/i386: Move arch_id decode inside x86_cpus_init Babu Moger
2020-03-09 15:21 ` Igor Mammedov
2020-03-09 19:31 ` Babu Moger
2020-03-10 8:35 ` Igor Mammedov
2020-03-10 20:05 ` Babu Moger
2020-03-03 19:58 ` [PATCH v5 15/16] i386: Fix pkg_id offset for EPYC cpu models Babu Moger
2020-03-09 15:22 ` Igor Mammedov
2020-03-03 19:58 ` [PATCH v5 16/16] tests: Update the Unit tests Babu Moger
2020-03-10 23:06 ` Eduardo Habkost
2020-03-10 23:09 ` Moger, Babu
2020-03-08 13:25 ` [PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model Michael S. Tsirkin
2020-03-09 17:50 ` Babu Moger
2020-03-10 8:40 ` Igor Mammedov
2020-03-10 20:07 ` Babu Moger
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