From: Sumit Garg <sumit.garg@linaro.org> To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, julien.thierry.kdev@gmail.com, dianders@chromium.org, daniel.thompson@linaro.org, jason.wessel@windriver.com, kgdb-bugreport@lists.sourceforge.net, linux-kernel@vger.kernel.org, Sumit Garg <sumit.garg@linaro.org> Subject: [RFC Patch v1 1/4] arm64: smp: Introduce a new IPI as IPI_CALL_NMI_FUNC Date: Fri, 24 Apr 2020 16:39:11 +0530 [thread overview] Message-ID: <1587726554-32018-2-git-send-email-sumit.garg@linaro.org> (raw) In-Reply-To: <1587726554-32018-1-git-send-email-sumit.garg@linaro.org> Introduce a new inter processor interrupt as IPI_CALL_NMI_FUNC that can be invoked to run special handlers in NMI context. One such handler example is kgdb_nmicallback() which is invoked in order to round up CPUs to enter kgdb context. As currently pseudo NMIs are supported on specific arm64 platforms which incorporates GICv3 or later version of interrupt controller. In case a particular platform doesn't support pseudo NMIs, IPI_CALL_NMI_FUNC will act as a normal IPI which can still be used to invoke special handlers. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> --- arch/arm64/include/asm/hardirq.h | 2 +- arch/arm64/include/asm/smp.h | 1 + arch/arm64/kernel/smp.c | 20 +++++++++++++++++++- 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/hardirq.h b/arch/arm64/include/asm/hardirq.h index 87ad961..abaa23a 100644 --- a/arch/arm64/include/asm/hardirq.h +++ b/arch/arm64/include/asm/hardirq.h @@ -13,7 +13,7 @@ #include <asm/kvm_arm.h> #include <asm/sysreg.h> -#define NR_IPI 7 +#define NR_IPI 8 typedef struct { unsigned int __softirq_pending; diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 40d5ba0..cc32776 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -108,6 +108,7 @@ extern void secondary_entry(void); extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); +extern void arch_send_call_nmi_func_ipi_mask(const struct cpumask *mask); #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL extern void arch_send_wakeup_ipi_mask(const struct cpumask *mask); diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 061f60f..42fe7bb 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -74,7 +74,8 @@ enum ipi_msg_type { IPI_CPU_CRASH_STOP, IPI_TIMER, IPI_IRQ_WORK, - IPI_WAKEUP + IPI_WAKEUP, + IPI_CALL_NMI_FUNC }; #ifdef CONFIG_HOTPLUG_CPU @@ -798,6 +799,7 @@ static const char *ipi_types[NR_IPI] __tracepoint_string = { S(IPI_TIMER, "Timer broadcast interrupts"), S(IPI_IRQ_WORK, "IRQ work interrupts"), S(IPI_WAKEUP, "CPU wake-up interrupts"), + S(IPI_CALL_NMI_FUNC, "NMI function call interrupts"), }; static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) @@ -856,6 +858,11 @@ void arch_irq_work_raise(void) } #endif +void arch_send_call_nmi_func_ipi_mask(const struct cpumask *mask) +{ + smp_cross_call(mask, IPI_CALL_NMI_FUNC); +} + static void local_cpu_stop(void) { set_cpu_online(smp_processor_id(), false); @@ -960,6 +967,17 @@ void handle_IPI(int ipinr, struct pt_regs *regs) break; #endif + case IPI_CALL_NMI_FUNC: + /* Handle it as a normal interrupt if not in NMI context */ + if (!in_nmi()) + irq_enter(); + + /* nop, IPI handlers for special features can be added here. */ + + if (!in_nmi()) + irq_exit(); + break; + default: pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); break; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Sumit Garg <sumit.garg@linaro.org> To: linux-arm-kernel@lists.infradead.org Cc: Sumit Garg <sumit.garg@linaro.org>, daniel.thompson@linaro.org, jason@lakedaemon.net, catalin.marinas@arm.com, jason.wessel@windriver.com, dianders@chromium.org, linux-kernel@vger.kernel.org, maz@kernel.org, kgdb-bugreport@lists.sourceforge.net, tglx@linutronix.de, will@kernel.org, julien.thierry.kdev@gmail.com Subject: [RFC Patch v1 1/4] arm64: smp: Introduce a new IPI as IPI_CALL_NMI_FUNC Date: Fri, 24 Apr 2020 16:39:11 +0530 [thread overview] Message-ID: <1587726554-32018-2-git-send-email-sumit.garg@linaro.org> (raw) In-Reply-To: <1587726554-32018-1-git-send-email-sumit.garg@linaro.org> Introduce a new inter processor interrupt as IPI_CALL_NMI_FUNC that can be invoked to run special handlers in NMI context. One such handler example is kgdb_nmicallback() which is invoked in order to round up CPUs to enter kgdb context. As currently pseudo NMIs are supported on specific arm64 platforms which incorporates GICv3 or later version of interrupt controller. In case a particular platform doesn't support pseudo NMIs, IPI_CALL_NMI_FUNC will act as a normal IPI which can still be used to invoke special handlers. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> --- arch/arm64/include/asm/hardirq.h | 2 +- arch/arm64/include/asm/smp.h | 1 + arch/arm64/kernel/smp.c | 20 +++++++++++++++++++- 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/hardirq.h b/arch/arm64/include/asm/hardirq.h index 87ad961..abaa23a 100644 --- a/arch/arm64/include/asm/hardirq.h +++ b/arch/arm64/include/asm/hardirq.h @@ -13,7 +13,7 @@ #include <asm/kvm_arm.h> #include <asm/sysreg.h> -#define NR_IPI 7 +#define NR_IPI 8 typedef struct { unsigned int __softirq_pending; diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 40d5ba0..cc32776 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -108,6 +108,7 @@ extern void secondary_entry(void); extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); +extern void arch_send_call_nmi_func_ipi_mask(const struct cpumask *mask); #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL extern void arch_send_wakeup_ipi_mask(const struct cpumask *mask); diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 061f60f..42fe7bb 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -74,7 +74,8 @@ enum ipi_msg_type { IPI_CPU_CRASH_STOP, IPI_TIMER, IPI_IRQ_WORK, - IPI_WAKEUP + IPI_WAKEUP, + IPI_CALL_NMI_FUNC }; #ifdef CONFIG_HOTPLUG_CPU @@ -798,6 +799,7 @@ static const char *ipi_types[NR_IPI] __tracepoint_string = { S(IPI_TIMER, "Timer broadcast interrupts"), S(IPI_IRQ_WORK, "IRQ work interrupts"), S(IPI_WAKEUP, "CPU wake-up interrupts"), + S(IPI_CALL_NMI_FUNC, "NMI function call interrupts"), }; static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) @@ -856,6 +858,11 @@ void arch_irq_work_raise(void) } #endif +void arch_send_call_nmi_func_ipi_mask(const struct cpumask *mask) +{ + smp_cross_call(mask, IPI_CALL_NMI_FUNC); +} + static void local_cpu_stop(void) { set_cpu_online(smp_processor_id(), false); @@ -960,6 +967,17 @@ void handle_IPI(int ipinr, struct pt_regs *regs) break; #endif + case IPI_CALL_NMI_FUNC: + /* Handle it as a normal interrupt if not in NMI context */ + if (!in_nmi()) + irq_enter(); + + /* nop, IPI handlers for special features can be added here. */ + + if (!in_nmi()) + irq_exit(); + break; + default: pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); break; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-04-24 11:11 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-24 11:09 [RFC Patch v1 0/4] arm64: Introduce new IPI as IPI_CALL_NMI_FUNC Sumit Garg 2020-04-24 11:09 ` Sumit Garg 2020-04-24 11:09 ` Sumit Garg [this message] 2020-04-24 11:09 ` [RFC Patch v1 1/4] arm64: smp: Introduce a " Sumit Garg 2020-04-24 11:09 ` [RFC Patch v1 2/4] irqchip/gic-v3: Add support to handle SGI as pseudo NMI Sumit Garg 2020-04-24 11:09 ` Sumit Garg 2020-04-25 10:29 ` Marc Zyngier 2020-04-25 10:29 ` Marc Zyngier 2020-04-25 14:32 ` Marc Zyngier 2020-04-25 14:32 ` Marc Zyngier 2020-04-28 14:11 ` Sumit Garg 2020-04-28 14:11 ` Sumit Garg 2020-04-29 8:23 ` Marc Zyngier 2020-04-29 8:23 ` Marc Zyngier 2020-04-30 7:20 ` Sumit Garg 2020-04-30 7:20 ` Sumit Garg 2020-04-30 9:13 ` Marc Zyngier 2020-04-30 9:13 ` Marc Zyngier 2020-04-30 12:13 ` Sumit Garg 2020-04-30 12:13 ` Sumit Garg 2020-05-01 13:03 ` Sumit Garg 2020-05-01 13:03 ` Sumit Garg 2020-05-05 4:09 ` Sumit Garg 2020-05-05 4:09 ` Sumit Garg 2020-05-05 10:08 ` Marc Zyngier 2020-05-05 10:08 ` Marc Zyngier 2020-05-05 11:33 ` Sumit Garg 2020-05-05 11:33 ` Sumit Garg 2020-05-13 10:02 ` Sumit Garg 2020-05-13 10:02 ` Sumit Garg 2020-05-19 14:51 ` Marc Zyngier 2020-05-19 14:51 ` Marc Zyngier 2020-04-24 11:09 ` [RFC Patch v1 3/4] irqchip/gic-v3: Enable arch specific IPI " Sumit Garg 2020-04-24 11:09 ` Sumit Garg 2020-04-24 11:09 ` [RFC Patch v1 4/4] arm64: kgdb: Round up cpus using IPI_CALL_NMI_FUNC Sumit Garg 2020-04-24 11:09 ` Sumit Garg 2020-04-24 20:46 ` Doug Anderson 2020-04-24 20:46 ` Doug Anderson 2020-04-27 4:52 ` Sumit Garg 2020-04-27 4:52 ` Sumit Garg 2020-04-24 20:49 ` [RFC Patch v1 0/4] arm64: Introduce new IPI as IPI_CALL_NMI_FUNC Doug Anderson 2020-04-24 20:49 ` Doug Anderson 2020-04-27 4:54 ` Sumit Garg 2020-04-27 4:54 ` Sumit Garg
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