[Intel-gfx] [PATCH v28 0/6] SAGV support for Gen12+

[Intel-gfx] [PATCH v28 0/6] SAGV support for Gen12+

[Stanislav Lisovskiy]

For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.

v25: Rebased patch series as part was merged already
v26: Had to resend the whole series as one more mid patch was added
v27: Patches 2,3,7 were pushed, have to resend the series to prevent
     build failure.
v28: PCode patch was merged, one patch was added, sent new series.

Stanislav Lisovskiy (6):
  drm/i915: Introduce skl_plane_wm_level accessor.
  drm/i915: Extract skl SAGV checking
  drm/i915: Make active_pipes check skl specific
  drm/i915: Add TGL+ SAGV support
  drm/i915: Restrict qgv points which don't have enough bandwidth.
  drm/i915: Enable SAGV support for Gen12

 drivers/gpu/drm/i915/display/intel_bw.c       | 139 ++++++++---
 drivers/gpu/drm/i915/display/intel_bw.h       |   9 +
 drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
 .../drm/i915/display/intel_display_types.h    |   5 +
 drivers/gpu/drm/i915/intel_pm.c               | 222 ++++++++++++++++--
 drivers/gpu/drm/i915/intel_pm.h               |   5 +-
 6 files changed, 334 insertions(+), 54 deletions(-)

-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v28 1/6] drm/i915: Introduce skl_plane_wm_level accessor.

[Stanislav Lisovskiy]

For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.

So this accessor will give additional flexibility
to do that.

Currently this accessor is still simply working
as "pass-through" function. This will be changed
in next coming patches from this series.

v2: - plane_id -> plane->id(Ville Syrjälä)
    - Moved wm_level var to have more local scope
      (Ville Syrjälä)
    - Renamed yuv to color_plane(Ville Syrjälä) in
      skl_plane_wm_level

v3: - plane->id -> plane_id(this time for real, Ville Syrjälä)
    - Changed colorplane id type from boolean to int as index
      (Ville Syrjälä)
    - Moved crtc_state param so that it is first now
      (Ville Syrjälä)
    - Moved wm_level declaration to tigher scope in
      skl_write_plane_wm(Ville Syrjälä)

v4: - Started to use enum values for color plane
    - Do sizeof for a type what we are memset'ing
    - Zero out wm_uv as well(Ville Syrjälä)

v5: - Fixed rebase conflict caused by COLOR_PLANE_*
      enum removal

v6: - Do not use skl_plane_wm_level accessor in skl_allocate_pipe_ddb

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 416cb1a1e7cb..8a86298962dc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4632,6 +4632,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
 	return total_data_rate;
 }
 
+static const struct skl_wm_level *
+skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
+		   enum plane_id plane_id,
+		   int level,
+		   int color_plane)
+{
+	const struct skl_plane_wm *wm =
+		&crtc_state->wm.skl.optimal.planes[plane_id];
+
+	return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
+}
+
 static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 {
@@ -5439,8 +5451,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
 		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
 
 	for (level = 0; level <= max_level; level++) {
+		const struct skl_wm_level *wm_level;
+		int color_plane = 0;
+
+		wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
+
 		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
-				   &wm->wm[level]);
+				   wm_level);
 	}
 	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
 			   &wm->trans_wm);
@@ -5473,8 +5490,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
 
 	for (level = 0; level <= max_level; level++) {
+		const struct skl_wm_level *wm_level;
+		int color_plane = 0;
+
+		wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
+
 		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
-				   &wm->wm[level]);
+				   wm_level);
 	}
 	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
 
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v28 2/6] drm/i915: Extract skl SAGV checking

[Stanislav Lisovskiy]

Introduce platform dependent SAGV checking in
combination with bandwidth state pipe SAGV mask.

This is preparation to adding TGL support, which
requires different way of SAGV checking.

v2, v3, v4, v5, v6: Fix rebase conflict

v7: - Nuke icl specific function, use skl
      for icl as well, gen specific active_pipes
      check to be added in the next patch(Ville)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8a86298962dc..3dc1ad66beb3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3804,7 +3804,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
 		intel_enable_sagv(dev_priv);
 }
 
-static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -3865,7 +3865,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 {
 	int ret;
 	struct intel_crtc *crtc;
-	struct intel_crtc_state *new_crtc_state;
+	const struct intel_crtc_state *new_crtc_state;
 	struct intel_bw_state *new_bw_state = NULL;
 	const struct intel_bw_state *old_bw_state = NULL;
 	int i;
@@ -3878,7 +3878,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 
 		old_bw_state = intel_atomic_get_old_bw_state(state);
 
-		if (intel_crtc_can_enable_sagv(new_crtc_state))
+		if (skl_crtc_can_enable_sagv(new_crtc_state))
 			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
 		else
 			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
@@ -3889,6 +3889,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 
 	new_bw_state->active_pipes =
 		intel_calc_active_pipes(state, old_bw_state->active_pipes);
+
 	if (new_bw_state->active_pipes != old_bw_state->active_pipes) {
 		ret = intel_atomic_lock_global_state(&new_bw_state->base);
 		if (ret)
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v28 3/6] drm/i915: Make active_pipes check skl specific

[Stanislav Lisovskiy]

Seems that only skl needs to have SAGV turned off
for multipipe scenarios, so lets do it this way.

If anything blows up - we can always revert this patch.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++------
 drivers/gpu/drm/i915/intel_pm.h |  3 ++-
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3dc1ad66beb3..db188efee21e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3777,7 +3777,7 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
 	if (!new_bw_state)
 		return;
 
-	if (!intel_can_enable_sagv(new_bw_state))
+	if (!intel_can_enable_sagv(dev_priv, new_bw_state))
 		intel_disable_sagv(dev_priv);
 }
 
@@ -3800,7 +3800,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
 	if (!new_bw_state)
 		return;
 
-	if (intel_can_enable_sagv(new_bw_state))
+	if (intel_can_enable_sagv(dev_priv, new_bw_state))
 		intel_enable_sagv(dev_priv);
 }
 
@@ -3853,16 +3853,19 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 	return true;
 }
 
-bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
+bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
+			   const struct intel_bw_state *bw_state)
 {
-	if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
-		return false;
+	if (INTEL_GEN(dev_priv) < 11)
+		if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
+			return false;
 
 	return bw_state->pipe_sagv_reject == 0;
 }
 
 static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 {
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	int ret;
 	struct intel_crtc *crtc;
 	const struct intel_crtc_state *new_crtc_state;
@@ -3896,7 +3899,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 			return ret;
 	}
 
-	if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
+	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {
 		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
 		if (ret)
 			return ret;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index fd1dc422e6c5..614ac7f8d4cc 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -42,7 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 			      struct skl_pipe_wm *out);
 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
-bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
+bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
+			   const struct intel_bw_state *bw_state);
 int intel_enable_sagv(struct drm_i915_private *dev_priv);
 int intel_disable_sagv(struct drm_i915_private *dev_priv);
 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v28 4/6] drm/i915: Add TGL+ SAGV support

[Stanislav Lisovskiy]

Starting from TGL we need to have a separate wm0
values for SAGV and non-SAGV which affects
how calculations are done.

v2: Remove long lines
v3: Removed COLOR_PLANE enum references
v4, v5, v6: Fixed rebase conflict
v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
    - Removed sagv_uv_wm0(Ville)
    - can_sagv->use_sagv_wm(Ville)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
 .../drm/i915/display/intel_display_types.h    |   2 +
 drivers/gpu/drm/i915/intel_pm.c               | 118 +++++++++++++++++-
 3 files changed, 121 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fd6d63b03489..be5741cb7595 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
 		/* Watermarks */
 		for (level = 0; level <= max_level; level++) {
 			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
-						&sw_plane_wm->wm[level]))
+						&sw_plane_wm->wm[level]) ||
+			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
+							       &sw_plane_wm->sagv_wm0)))
 				continue;
 
 			drm_err(&dev_priv->drm,
@@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
 		/* Watermarks */
 		for (level = 0; level <= max_level; level++) {
 			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
-						&sw_plane_wm->wm[level]))
+						&sw_plane_wm->wm[level]) ||
+			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
+							       &sw_plane_wm->sagv_wm0)))
 				continue;
 
 			drm_err(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9488449e4b94..8cede29c9562 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -688,11 +688,13 @@ struct skl_plane_wm {
 	struct skl_wm_level wm[8];
 	struct skl_wm_level uv_wm[8];
 	struct skl_wm_level trans_wm;
+	struct skl_wm_level sagv_wm0;
 	bool is_planar;
 };
 
 struct skl_pipe_wm {
 	struct skl_plane_wm planes[I915_MAX_PLANES];
+	bool use_sagv_wm;
 };
 
 enum vlv_wm_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index db188efee21e..934a686342ad 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3863,25 +3863,35 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
 	return bw_state->pipe_sagv_reject == 0;
 }
 
+static bool
+tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
+
 static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	int ret;
 	struct intel_crtc *crtc;
-	const struct intel_crtc_state *new_crtc_state;
+	struct intel_crtc_state *new_crtc_state;
 	struct intel_bw_state *new_bw_state = NULL;
 	const struct intel_bw_state *old_bw_state = NULL;
 	int i;
 
 	for_each_new_intel_crtc_in_state(state, crtc,
 					 new_crtc_state, i) {
+		bool can_sagv;
+
 		new_bw_state = intel_atomic_get_bw_state(state);
 		if (IS_ERR(new_bw_state))
 			return PTR_ERR(new_bw_state);
 
 		old_bw_state = intel_atomic_get_old_bw_state(state);
 
-		if (skl_crtc_can_enable_sagv(new_crtc_state))
+		if (INTEL_GEN(dev_priv) >= 12)
+			can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
+		else
+			can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
+
+		if (can_sagv)
 			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
 		else
 			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
@@ -3899,6 +3909,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 			return ret;
 	}
 
+	for_each_new_intel_crtc_in_state(state, crtc,
+					 new_crtc_state, i) {
+		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
+
+		/*
+		 * Due to drm limitation at commit state, when
+		 * changes are written the whole atomic state is
+		 * zeroed away => which prevents from using it,
+		 * so just sticking it into pipe wm state for
+		 * keeping it simple - anyway this is related to wm.
+		 * Proper way in ideal universe would be of course not
+		 * to lose parent atomic state object from child crtc_state,
+		 * and stick to OOP programming principles, which had been
+		 * scientifically proven to work.
+		 */
+		pipe_wm->use_sagv_wm = intel_can_enable_sagv(dev_priv, new_bw_state);
+	}
+
 	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {
 		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
 		if (ret)
@@ -4642,12 +4670,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
 		   int level,
 		   int color_plane)
 {
-	const struct skl_plane_wm *wm =
-		&crtc_state->wm.skl.optimal.planes[plane_id];
+	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+	const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+
+	if (!level) {
+		if (pipe_wm->use_sagv_wm)
+			return &wm->sagv_wm0;
+	}
 
 	return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
 }
 
+static bool
+tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum plane_id plane_id;
+
+	if (!crtc_state->hw.active)
+		return true;
+
+	for_each_plane_id_on_crtc(crtc, plane_id) {
+		const struct skl_ddb_entry *plane_alloc =
+			&crtc_state->wm.skl.plane_ddb_y[plane_id];
+		const struct skl_plane_wm *wm =
+			&crtc_state->wm.skl.optimal.planes[plane_id];
+
+		if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
+			return false;
+	}
+
+	return true;
+}
+
 static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 {
@@ -4684,7 +4739,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 							 plane_data_rate,
 							 uv_plane_data_rate);
 
-
 	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
 					   alloc, &num_active);
 	alloc_size = skl_ddb_entry_size(alloc);
@@ -5219,6 +5273,37 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
 	}
 }
 
+static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
+				const struct skl_wm_params *wm_params,
+				struct skl_plane_wm *plane_wm)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct skl_wm_level *sagv_wm = &plane_wm->sagv_wm0;
+	struct skl_wm_level *levels = plane_wm->wm;
+
+	/*
+	 * For Gen12 if it is an L0 we need to also
+	 * consider sagv_block_time when calculating
+	 * L0 watermark - we will need that when making
+	 * a decision whether enable SAGV or not.
+	 * For older gens we agreed to copy L0 value for
+	 * compatibility.
+	 */
+	if ((INTEL_GEN(dev_priv) >= 12)) {
+		u32 latency = dev_priv->wm.skl_latency[0];
+
+		latency += dev_priv->sagv_block_time_us;
+		skl_compute_plane_wm(crtc_state, 0, latency,
+				     wm_params, &levels[0],
+				     sagv_wm);
+		DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
+			      sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
+	} else {
+		/* Since all members are POD */
+		*sagv_wm = levels[0];
+	}
+}
+
 static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
 				      const struct skl_wm_params *wp,
 				      struct skl_plane_wm *wm)
@@ -5296,6 +5381,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
 		return ret;
 
 	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+	if (color_plane == 0)
+		tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
 	skl_compute_transition_wm(crtc_state, &wm_params, wm);
 
 	return 0;
@@ -5702,6 +5789,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 				    enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
 				    enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
 
+			drm_dbg_kms(&dev_priv->drm,
+				    "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
+				    plane->base.base.id, plane->base.name,
+				    old_wm->sagv_wm0.plane_res_l,
+				    new_wm->sagv_wm0.plane_res_l);
+
 			drm_dbg_kms(&dev_priv->drm,
 				    "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
 				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
@@ -5717,6 +5810,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 				    new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
 				    new_wm->trans_wm.plane_res_b);
 
+			drm_dbg_kms(&dev_priv->drm,
+				    "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
+				    plane->base.base.id, plane->base.name,
+				    old_wm->sagv_wm0.plane_res_b,
+				    new_wm->sagv_wm0.plane_res_b);
+
 			drm_dbg_kms(&dev_priv->drm,
 				    "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
 				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
@@ -5731,6 +5830,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 				    new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
 				    new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
 				    new_wm->trans_wm.min_ddb_alloc);
+
+			drm_dbg_kms(&dev_priv->drm,
+				    "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
+				    plane->base.base.id, plane->base.name,
+				    old_wm->sagv_wm0.min_ddb_alloc,
+				    new_wm->sagv_wm0.min_ddb_alloc);
 		}
 	}
 }
@@ -6023,6 +6128,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 			skl_wm_level_from_reg_val(val, &wm->wm[level]);
 		}
 
+		memcpy(&wm->sagv_wm0, &wm->wm[0],
+		       sizeof(struct skl_wm_level));
+
 		if (plane_id != PLANE_CURSOR)
 			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
 		else
-- 
2.24.1.485.gad05a3d8e5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v28 5/6] drm/i915: Restrict qgv points which don't have enough bandwidth.

[Stanislav Lisovskiy]

According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.

Currently we are just comparing against all of
those and take minimum(worst case).

v2: Fixed wrong PCode reply mask, removed hardcoded
    values.

v3: Forbid simultaneous legacy SAGV PCode requests and
    restricting qgv points. Put the actual restriction
    to commit function, added serialization(thanks to Ville)
    to prevent commit being applied out of order in case of
    nonblocking and/or nomodeset commits.

v4:
    - Minor code refactoring, fixed few typos(thanks to James Ausmus)
    - Change the naming of qgv point
      masking/unmasking functions(James Ausmus).
    - Simplify the masking/unmasking operation itself,
      as we don't need to mask only single point per request(James Ausmus)
    - Reject and stick to highest bandwidth point if SAGV
      can't be enabled(BSpec)

v5:
    - Add new mailbox reply codes, which seems to happen during boot
      time for TGL and indicate that QGV setting is not yet available.

v6:
    - Increase number of supported QGV points to be in sync with BSpec.

v7: - Rebased and resolved conflict to fix build failure.
    - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)

v8: - Don't report an error if we can't restrict qgv points, as SAGV
      can be disabled by BIOS, which is completely legal. So don't
      make CI panic. Instead if we detect that there is only 1 QGV
      point accessible just analyze if we can fit the required bandwidth
      requirements, but no need in restricting.

v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
      simultaneously.

v10: - Fix CDCLK corruption, because of global state getting serialized
       without modeset, which caused copying of non-calculated cdclk
       to be copied to dev_priv(thanks to Ville for the hint).

v11: - Remove unneeded headers and spaces(Matthew Roper)
     - Remove unneeded intel_qgv_info qi struct from bw check and zero
       out the needed one(Matthew Roper)
     - Changed QGV error message to have more clear meaning(Matthew Roper)
     - Use state->modeset_set instead of any_ms(Matthew Roper)
     - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
     - Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
     - Moved unrelated changes to other patch(using latency as parameter
       for plane wm calculation, moved to SAGV refactoring patch)

v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
     - Remove unnecessary mask being zero check when unmasking
       qgv points as this is completely legal(Matt Roper)
     - Check if we are setting the same mask as already being set
       in hardware to prevent error from PCode.
     - Fix error message when restricting/unrestricting qgv points
       to "mask/unmask" which sounds more accurate(Matt Roper)
     - Move sagv status setting to icl_get_bw_info from atomic check
       as this should be calculated only once.(Matt Roper)
     - Edited comments for the case when we can't enable SAGV and
       use only 1 QGV point with highest bandwidth to be more
       understandable.(Matt Roper)

v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
     - Changed comment for zero new_mask in qgv points masking function
       to better reflect reality(Ville Syrjälä)
     - Simplified bit mask operation in qgv points masking function
       (Ville Syrjälä)
     - Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
       however this still can't be under modeset condition(Ville Syrjälä)
     - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
       (Ville Syrjälä)
     - Extracted PCode changes to separate patch.(Ville Syrjälä)
     - Now treat num_planes 0 same as 1 to avoid confusion and
       returning max_bw as 0, which would prevent choosing QGV
       point having max bandwidth in case if SAGV is not allowed,
       as per BSpec(Ville Syrjälä)
     - Do the actual qgv_points_mask swap in the same place as
       all other global state parts like cdclk are swapped.
       In the next patch, this all will be moved to bw state as
       global state, once new global state patch series from Ville
       lands

v14: - Now using global state to serialize access to qgv points
     - Added global state locking back, otherwise we seem to read
       bw state in a wrong way.

v15: - Added TODO comment for near atomic global state locking in
       bw code.

v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
       with Jani Nikula.
     - Take bw_state_changed flag into use.

v17: - Moved qgv point related manipulations next to SAGV code, as
       those are semantically related(Ville Syrjälä)
     - Renamed those into intel_sagv_(pre)|(post)_plane_update
       (Ville Syrjälä)

v18: - Move sagv related calls from commit tail into
       intel_sagv_(pre)|(post)_plane_update(Ville Syrjälä)

v19: - Use intel_atomic_get_bw_(old)|(new)_state which is intended
       for commit tail stage.

v20: - Return max bandwidth for 0 planes(Ville)
     - Constify old_bw_state in bw_atomic_check(Ville)
     - Removed some debugs(Ville)
     - Added data rate to debug print when no QGV points(Ville)
     - Removed some comments(Ville)

v21, v22, v23: - Fixed rebase conflict

v24: - Changed PCode mask to use ICL_ prefix
v25: - Resolved rebase conflict

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c       | 139 +++++++++++++-----
 drivers/gpu/drm/i915/display/intel_bw.h       |   9 ++
 .../drm/i915/display/intel_display_types.h    |   3 +
 drivers/gpu/drm/i915/intel_pm.c               |  66 ++++++++-
 drivers/gpu/drm/i915/intel_pm.h               |   2 +
 5 files changed, 181 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 6e7cc3a4f1aa..5455420fde49 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,6 +8,9 @@
 #include "intel_bw.h"
 #include "intel_display_types.h"
 #include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
 
 /* Parameters for Qclk Geyserville (QGV) */
 struct intel_qgv_point {
@@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+				  u32 points_mask)
+{
+	int ret;
+
+	/* bspec says to keep retrying for at least 1 ms */
+	ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+				points_mask,
+				ICL_PCODE_POINTS_RESTRICTED_MASK,
+				ICL_PCODE_POINTS_RESTRICTED,
+				1);
+
+	if (ret < 0) {
+		DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
 static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
 			      struct intel_qgv_info *qi)
 {
@@ -240,6 +263,16 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
 			break;
 	}
 
+	/*
+	 * In case if SAGV is disabled in BIOS, we always get 1
+	 * SAGV point, but we can't send PCode commands to restrict it
+	 * as it will fail and pointless anyway.
+	 */
+	if (qi.num_points == 1)
+		dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+	else
+		dev_priv->sagv_status = I915_SAGV_ENABLED;
+
 	return 0;
 }
 
@@ -248,6 +281,11 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
 {
 	int i;
 
+	/*
+	 * Let's return max bw for 0 planes
+	 */
+	num_planes = max(1, num_planes);
+
 	for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
 		const struct intel_bw_info *bi =
 			&dev_priv->max_bw[i];
@@ -277,34 +315,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 		icl_get_bw_info(dev_priv, &icl_sa_info);
 }
 
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
-					int num_planes)
-{
-	if (INTEL_GEN(dev_priv) >= 11) {
-		/*
-		 * Any bw group has same amount of QGV points
-		 */
-		const struct intel_bw_info *bi =
-			&dev_priv->max_bw[0];
-		unsigned int min_bw = UINT_MAX;
-		int i;
-
-		/*
-		 * FIXME with SAGV disabled maybe we can assume
-		 * point 1 will always be used? Seems to match
-		 * the behaviour observed in the wild.
-		 */
-		for (i = 0; i < bi->num_qgv_points; i++) {
-			unsigned int bw = icl_max_bw(dev_priv, num_planes, i);
-
-			min_bw = min(bw, min_bw);
-		}
-		return min_bw;
-	} else {
-		return UINT_MAX;
-	}
-}
-
 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
 {
 	/*
@@ -415,10 +425,15 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
 	struct intel_bw_state *new_bw_state = NULL;
-	unsigned int data_rate, max_data_rate;
+	const struct intel_bw_state *old_bw_state = NULL;
+	unsigned int data_rate;
 	unsigned int num_active_planes;
 	struct intel_crtc *crtc;
 	int i, ret;
+	u32 allowed_points = 0;
+	unsigned int max_bw_point = 0, max_bw = 0;
+	unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+	u32 mask = (1 << num_qgv_points) - 1;
 
 	/* FIXME earlier gens need some checks too */
 	if (INTEL_GEN(dev_priv) < 11)
@@ -465,19 +480,73 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 		return ret;
 
 	data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+	data_rate = DIV_ROUND_UP(data_rate, 1000);
+
 	num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
 
-	max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
+	for (i = 0; i < num_qgv_points; i++) {
+		unsigned int max_data_rate;
 
-	data_rate = DIV_ROUND_UP(data_rate, 1000);
+		max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+		/*
+		 * We need to know which qgv point gives us
+		 * maximum bandwidth in order to disable SAGV
+		 * if we find that we exceed SAGV block time
+		 * with watermarks. By that moment we already
+		 * have those, as it is calculated earlier in
+		 * intel_atomic_check,
+		 */
+		if (max_data_rate > max_bw) {
+			max_bw_point = i;
+			max_bw = max_data_rate;
+		}
+		if (max_data_rate >= data_rate)
+			allowed_points |= BIT(i);
+		DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+			      i, max_data_rate, data_rate);
+	}
 
-	if (data_rate > max_data_rate) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
-			    data_rate, max_data_rate, num_active_planes);
+	/*
+	 * BSpec states that we always should have at least one allowed point
+	 * left, so if we couldn't - simply reject the configuration for obvious
+	 * reasons.
+	 */
+	if (allowed_points == 0) {
+		DRM_DEBUG_KMS("No QGV points provide sufficient memory"
+			      " bandwidth %d for display configuration.\n", data_rate);
 		return -EINVAL;
 	}
 
+	/*
+	 * Leave only single point with highest bandwidth, if
+	 * we can't enable SAGV due to the increased memory latency it may
+	 * cause.
+	 */
+	if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
+		allowed_points = BIT(max_bw_point);
+		DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
+			      max_bw_point);
+	}
+	/*
+	 * We store the ones which need to be masked as that is what PCode
+	 * actually accepts as a parameter.
+	 */
+	new_bw_state->qgv_points_mask = (~allowed_points) & mask;
+
+	old_bw_state = intel_atomic_get_old_bw_state(state);
+	if (!old_bw_state)
+		return -EINVAL;
+
+	/*
+	 * If the actual mask had changed we need to make sure that
+	 * the commits are serialized(in case this is a nomodeset, nonblocking)
+	 */
+	if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+		if (ret)
+			return ret;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 898b4a85ccab..bbcaaa73ec1b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,13 @@ struct intel_bw_state {
 	 */
 	u8 pipe_sagv_reject;
 
+	/*
+	 * Current QGV points mask, which restricts
+	 * some particular SAGV states, not to confuse
+	 * with pipe_sagv_mask.
+	 */
+	u8 qgv_points_mask;
+
 	unsigned int data_rate[I915_MAX_PIPES];
 	u8 num_active_planes[I915_MAX_PIPES];
 
@@ -47,5 +54,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
 int intel_bw_atomic_check(struct intel_atomic_state *state);
 void intel_bw_crtc_update(struct intel_bw_state *bw_state,
 			  const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+				  u32 points_mask);
 
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8cede29c9562..6edf0844f8ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -692,6 +692,9 @@ struct skl_plane_wm {
 	bool is_planar;
 };
 
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
 struct skl_pipe_wm {
 	struct skl_plane_wm planes[I915_MAX_PLANES];
 	bool use_sagv_wm;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 934a686342ad..66775d4fb1ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3761,7 +3761,10 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
 void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	int ret;
 	const struct intel_bw_state *new_bw_state;
+	const struct intel_bw_state *old_bw_state;
+	u32 new_mask = 0;
 
 	/*
 	 * Just return if we can't control SAGV or don't have it.
@@ -3777,15 +3780,48 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
 	if (!new_bw_state)
 		return;
 
-	if (!intel_can_enable_sagv(dev_priv, new_bw_state))
+	if (INTEL_GEN(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv, new_bw_state)) {
 		intel_disable_sagv(dev_priv);
+		return;
+	}
+
+	old_bw_state = intel_atomic_get_old_bw_state(state);
+	if (!old_bw_state)
+		return;
+
+	/*
+	 * Nothing to mask
+	 */
+	if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
+		return;
+
+	new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
+
+	/*
+	 * If new mask is zero - means there is nothing to mask,
+	 * we can only unmask, which should be done in unmask.
+	 */
+	if (!new_mask)
+		return;
+
+	/*
+	 * Restrict required qgv points before updating the configuration.
+	 * According to BSpec we can't mask and unmask qgv points at the same
+	 * time. Also masking should be done before updating the configuration
+	 * and unmasking afterwards.
+	 */
+	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+	if (ret < 0)
+		drm_err(&dev_priv->drm, "Could not mask required qgv points(%d)\n", ret);
 }
 
 void intel_sagv_post_plane_update(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	int ret;
 	const struct intel_bw_state *new_bw_state;
-
+	const struct intel_bw_state *old_bw_state;
+	u32 new_mask = 0;
 	/*
 	 * Just return if we can't control SAGV or don't have it.
 	 * This is different from situation when we have SAGV but just can't
@@ -3800,8 +3836,32 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
 	if (!new_bw_state)
 		return;
 
-	if (intel_can_enable_sagv(dev_priv, new_bw_state))
+	if (INTEL_GEN(dev_priv) < 11 && intel_can_enable_sagv(dev_priv, new_bw_state)) {
 		intel_enable_sagv(dev_priv);
+		return;
+	}
+
+	old_bw_state = intel_atomic_get_old_bw_state(state);
+	if (!old_bw_state)
+		return;
+
+	/*
+	 * Nothing to unmask
+	 */
+	if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
+		return;
+
+	new_mask = new_bw_state->qgv_points_mask;
+
+	/*
+	 * Allow required qgv points after updating the configuration.
+	 * According to BSpec we can't mask and unmask qgv points at the same
+	 * time. Also masking should be done before updating the configuration
+	 * and unmasking afterwards.
+	 */
+	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+	if (ret < 0)
+		drm_err(&dev_priv->drm, "Could not unmask required qgv points(%d)\n", ret);
 }
 
 static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 614ac7f8d4cc..528aba6267da 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -44,6 +44,8 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
 			   const struct intel_bw_state *bw_state);
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
+void intel_sagv_post_plane_update(struct intel_atomic_state *state);
 int intel_enable_sagv(struct drm_i915_private *dev_priv);
 int intel_disable_sagv(struct drm_i915_private *dev_priv);
 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
-- 
2.24.1.485.gad05a3d8e5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v28 6/6] drm/i915: Enable SAGV support for Gen12

[Stanislav Lisovskiy]

Flip the switch and enable SAGV support
for Gen12 also.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 66775d4fb1ae..ef2ec390b99b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3638,10 +3638,6 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
 static bool
 intel_has_sagv(struct drm_i915_private *dev_priv)
 {
-	/* HACK! */
-	if (IS_GEN(dev_priv, 12))
-		return false;
-
 	return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
 		dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
 }
-- 
2.24.1.485.gad05a3d8e5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev36)

[Patchwork]

== Series Details ==

Series: SAGV support for Gen12+ (rev36)
URL   : https://patchwork.freedesktop.org/series/75129/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
74acb8869d96 drm/i915: Introduce skl_plane_wm_level accessor.
37b1bc532f92 drm/i915: Extract skl SAGV checking
f4268af8a090 drm/i915: Make active_pipes check skl specific
-:63: WARNING:LONG_LINE: line over 100 characters
#63: FILE: drivers/gpu/drm/i915/intel_pm.c:3902:
+	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {

total: 0 errors, 1 warnings, 0 checks, 55 lines checked
1807e09ca9e6 drm/i915: Add TGL+ SAGV support
3d9400f258c5 drm/i915: Restrict qgv points which don't have enough bandwidth.
7b0099b8e0d1 drm/i915: Enable SAGV support for Gen12

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev36)

[Patchwork]

== Series Details ==

Series: SAGV support for Gen12+ (rev36)
URL   : https://patchwork.freedesktop.org/series/75129/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8444 -> Patchwork_17603
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/index.html

Known issues
------------

  Here are the changes found in Patchwork_17603 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-hsw-4770:        [SKIP][1] ([fdo#109271]) -> [PASS][2] +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/fi-hsw-4770/igt@i915_pm_rpm@basic-rte.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/fi-hsw-4770/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6700k2:      [INCOMPLETE][3] ([i915#151]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@reset:
    - fi-bwr-2160:        [INCOMPLETE][5] ([i915#489]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/fi-bwr-2160/igt@i915_selftest@live@reset.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/fi-bwr-2160/igt@i915_selftest@live@reset.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489


Participating hosts (49 -> 43)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8444 -> Patchwork_17603

  CI-20190529: 20190529
  CI_DRM_8444: 39544482386ac801dc4140df00a7e7e5bbea4d8a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5638: 50868ab3c532a86aa147fb555b69a1078c572b13 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17603: 7b0099b8e0d14efdb0b26fe1e7748e0361c00fa0 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7b0099b8e0d1 drm/i915: Enable SAGV support for Gen12
3d9400f258c5 drm/i915: Restrict qgv points which don't have enough bandwidth.
1807e09ca9e6 drm/i915: Add TGL+ SAGV support
f4268af8a090 drm/i915: Make active_pipes check skl specific
37b1bc532f92 drm/i915: Extract skl SAGV checking
74acb8869d96 drm/i915: Introduce skl_plane_wm_level accessor.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for SAGV support for Gen12+ (rev36)

[Patchwork]

== Series Details ==

Series: SAGV support for Gen12+ (rev36)
URL   : https://patchwork.freedesktop.org/series/75129/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8444_full -> Patchwork_17603_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_17603_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@kms:
    - shard-glk:          [PASS][1] -> [TIMEOUT][2] ([i915#1383])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-glk2/igt@gem_eio@kms.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-glk9/igt@gem_eio@kms.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@pipe-c-torture-move:
    - shard-iclb:         [PASS][5] -> [DMESG-WARN][6] ([i915#128])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-iclb8/igt@kms_cursor_legacy@pipe-c-torture-move.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-iclb5/igt@kms_cursor_legacy@pipe-c-torture-move.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-glk:          [PASS][7] -> [FAIL][8] ([i915#49])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-glk1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-glk7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-skl:          [PASS][9] -> [INCOMPLETE][10] ([i915#69])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-skl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-kbl:          [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [PASS][15] -> [FAIL][16] ([i915#173])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-iclb2/igt@kms_psr@no_drrs.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-iclb1/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [PASS][17] -> [SKIP][18] ([fdo#109441]) +4 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-iclb1/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_psr@suspend:
    - shard-skl:          [PASS][19] -> [INCOMPLETE][20] ([i915#198])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-skl4/igt@kms_psr@suspend.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-skl6/igt@kms_psr@suspend.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][21] -> [FAIL][22] ([i915#31])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-apl7/igt@kms_setmode@basic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-apl4/igt@kms_setmode@basic.html

  
#### Possible fixes ####

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [DMESG-WARN][23] ([i915#180]) -> [PASS][24] +3 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-apl8/igt@gem_workarounds@suspend-resume-context.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-apl1/igt@gem_workarounds@suspend-resume-context.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [FAIL][25] ([i915#72]) -> [PASS][26] +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@pipe-c-torture-bo:
    - shard-hsw:          [DMESG-WARN][27] ([i915#128]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-hsw5/igt@kms_cursor_legacy@pipe-c-torture-bo.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-hsw8/igt@kms_cursor_legacy@pipe-c-torture-bo.html

  * igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled:
    - shard-kbl:          [FAIL][29] ([i915#177] / [i915#52] / [i915#54] / [i915#93] / [i915#95]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-kbl7/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-kbl2/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html

  * {igt@kms_flip@flip-vs-rmfb-interruptible@c-vga1}:
    - shard-hsw:          [INCOMPLETE][31] ([i915#61]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-hsw4/igt@kms_flip@flip-vs-rmfb-interruptible@c-vga1.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-hsw7/igt@kms_flip@flip-vs-rmfb-interruptible@c-vga1.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         [SKIP][33] ([fdo#109441]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-iclb7/igt@kms_psr@psr2_cursor_plane_onoff.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [DMESG-WARN][35] ([i915#180]) -> [PASS][36] +5 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
    - shard-skl:          [INCOMPLETE][37] ([i915#69]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-skl4/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-skl1/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html

  * {igt@perf@blocking-parameterized}:
    - shard-hsw:          [FAIL][39] ([i915#1542]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-hsw6/igt@perf@blocking-parameterized.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-hsw2/igt@perf@blocking-parameterized.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][41] ([i915#658]) -> [SKIP][42] ([i915#588])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_content_protection@atomic:
    - shard-apl:          [FAIL][43] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][44] ([i915#1319])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-apl4/igt@kms_content_protection@atomic.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-apl2/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@lic:
    - shard-apl:          [TIMEOUT][45] ([i915#1319]) -> [FAIL][46] ([fdo#110321])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-apl2/igt@kms_content_protection@lic.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-apl6/igt@kms_content_protection@lic.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [SKIP][47] ([fdo#109642] / [fdo#111068]) -> [FAIL][48] ([i915#608])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-iclb4/igt@kms_psr2_su@page_flip.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-iclb2/igt@kms_psr2_su@page_flip.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-kbl:          [DMESG-WARN][49] ([i915#180]) -> [INCOMPLETE][50] ([i915#155] / [i915#794])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-kbl7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/shard-kbl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
  [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1383]: https://gitlab.freedesktop.org/drm/intel/issues/1383
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
  [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
  [i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
  [i915#608]: https://gitlab.freedesktop.org/drm/intel/issues/608
  [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
  [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8444 -> Patchwork_17603

  CI-20190529: 20190529
  CI_DRM_8444: 39544482386ac801dc4140df00a7e7e5bbea4d8a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5638: 50868ab3c532a86aa147fb555b69a1078c572b13 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17603: 7b0099b8e0d14efdb0b26fe1e7748e0361c00fa0 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17603/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v28 1/6] drm/i915: Introduce skl_plane_wm_level accessor.

[Ville Syrjälä]

On Thu, May 07, 2020 at 05:44:58PM +0300, Stanislav Lisovskiy wrote:
> For future Gen12 SAGV implementation we need to
> seemlessly alter wm levels calculated, depending
> on whether we are allowed to enable SAGV or not.
> 
> So this accessor will give additional flexibility
> to do that.
> 
> Currently this accessor is still simply working
> as "pass-through" function. This will be changed
> in next coming patches from this series.
> 
> v2: - plane_id -> plane->id(Ville Syrjälä)
>     - Moved wm_level var to have more local scope
>       (Ville Syrjälä)
>     - Renamed yuv to color_plane(Ville Syrjälä) in
>       skl_plane_wm_level
> 
> v3: - plane->id -> plane_id(this time for real, Ville Syrjälä)
>     - Changed colorplane id type from boolean to int as index
>       (Ville Syrjälä)
>     - Moved crtc_state param so that it is first now
>       (Ville Syrjälä)
>     - Moved wm_level declaration to tigher scope in
>       skl_write_plane_wm(Ville Syrjälä)
> 
> v4: - Started to use enum values for color plane
>     - Do sizeof for a type what we are memset'ing
>     - Zero out wm_uv as well(Ville Syrjälä)
> 
> v5: - Fixed rebase conflict caused by COLOR_PLANE_*
>       enum removal
> 
> v6: - Do not use skl_plane_wm_level accessor in skl_allocate_pipe_ddb
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 26 ++++++++++++++++++++++++--
>  1 file changed, 24 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 416cb1a1e7cb..8a86298962dc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4632,6 +4632,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
>  	return total_data_rate;
>  }
>  
> +static const struct skl_wm_level *
> +skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
> +		   enum plane_id plane_id,
> +		   int level,
> +		   int color_plane)
> +{
> +	const struct skl_plane_wm *wm =
> +		&crtc_state->wm.skl.optimal.planes[plane_id];
> +
> +	return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];

uv_wm still not a thing as far as the hw is concerned, so can't see why
we'd have this here.

> +}
> +
>  static int
>  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>  {
> @@ -5439,8 +5451,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
>  		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
>  
>  	for (level = 0; level <= max_level; level++) {
> +		const struct skl_wm_level *wm_level;
> +		int color_plane = 0;
> +
> +		wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
> +
>  		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
> -				   &wm->wm[level]);
> +				   wm_level);
>  	}
>  	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
>  			   &wm->trans_wm);
> @@ -5473,8 +5490,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
>  		&crtc_state->wm.skl.plane_ddb_y[plane_id];
>  
>  	for (level = 0; level <= max_level; level++) {
> +		const struct skl_wm_level *wm_level;
> +		int color_plane = 0;
> +
> +		wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
> +
>  		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
> -				   &wm->wm[level]);
> +				   wm_level);
>  	}
>  	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
>  
> -- 
> 2.24.1.485.gad05a3d8e5

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v28 3/6] drm/i915: Make active_pipes check skl specific

[Ville Syrjälä]

On Thu, May 07, 2020 at 05:45:00PM +0300, Stanislav Lisovskiy wrote:
> Seems that only skl needs to have SAGV turned off
> for multipipe scenarios, so lets do it this way.

It doesn't afaics. It's just someone added the check for some random
reason. So this should be reworded a bit. Also this isn't just about
skl/derivatives but all pre-icl so the <subject> is a bit misleading too.

> 
> If anything blows up - we can always revert this patch.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++------
>  drivers/gpu/drm/i915/intel_pm.h |  3 ++-
>  2 files changed, 11 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3dc1ad66beb3..db188efee21e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3777,7 +3777,7 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
>  	if (!new_bw_state)
>  		return;
>  
> -	if (!intel_can_enable_sagv(new_bw_state))
> +	if (!intel_can_enable_sagv(dev_priv, new_bw_state))
>  		intel_disable_sagv(dev_priv);
>  }
>  
> @@ -3800,7 +3800,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
>  	if (!new_bw_state)
>  		return;
>  
> -	if (intel_can_enable_sagv(new_bw_state))
> +	if (intel_can_enable_sagv(dev_priv, new_bw_state))
>  		intel_enable_sagv(dev_priv);
>  }
>  
> @@ -3853,16 +3853,19 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
>  	return true;
>  }
>  
> -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> +			   const struct intel_bw_state *bw_state)
>  {
> -	if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> -		return false;
> +	if (INTEL_GEN(dev_priv) < 11)
> +		if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))

If (a && b && c)
	return false;


> +			return false;
>  
>  	return bw_state->pipe_sagv_reject == 0;
>  }
>  
>  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	int ret;
>  	struct intel_crtc *crtc;
>  	const struct intel_crtc_state *new_crtc_state;
> @@ -3896,7 +3899,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  			return ret;
>  	}
>  
> -	if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> +	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {

>  		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
>  		if (ret)
>  			return ret;
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index fd1dc422e6c5..614ac7f8d4cc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -42,7 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>  			      struct skl_pipe_wm *out);
>  void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
>  void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> +			   const struct intel_bw_state *bw_state);
>  int intel_enable_sagv(struct drm_i915_private *dev_priv);
>  int intel_disable_sagv(struct drm_i915_private *dev_priv);
>  void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> -- 
> 2.24.1.485.gad05a3d8e5

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v28 2/6] drm/i915: Extract skl SAGV checking

[Ville Syrjälä]

On Thu, May 07, 2020 at 05:44:59PM +0300, Stanislav Lisovskiy wrote:
> Introduce platform dependent SAGV checking in
> combination with bandwidth state pipe SAGV mask.
> 
> This is preparation to adding TGL support, which
> requires different way of SAGV checking.
> 
> v2, v3, v4, v5, v6: Fix rebase conflict
> 
> v7: - Nuke icl specific function, use skl
>       for icl as well, gen specific active_pipes
>       check to be added in the next patch(Ville)
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8a86298962dc..3dc1ad66beb3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3804,7 +3804,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
>  		intel_enable_sagv(dev_priv);
>  }
>  
> -static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> +static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -3865,7 +3865,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  {
>  	int ret;
>  	struct intel_crtc *crtc;
> -	struct intel_crtc_state *new_crtc_state;
> +	const struct intel_crtc_state *new_crtc_state;
>  	struct intel_bw_state *new_bw_state = NULL;
>  	const struct intel_bw_state *old_bw_state = NULL;
>  	int i;
> @@ -3878,7 +3878,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  
>  		old_bw_state = intel_atomic_get_old_bw_state(state);
>  
> -		if (intel_crtc_can_enable_sagv(new_crtc_state))
> +		if (skl_crtc_can_enable_sagv(new_crtc_state))

I'd leave this behing as a trivial wrapper 
intel_crtc_can_enable_sagv()
{
	return skl_crtc_cna_enable_sagv();
}

so we won't need that ugly 'can_sagv' boolean when introducing the tgl
counterpart. Otherwise lgtm.

>  			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
>  		else
>  			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> @@ -3889,6 +3889,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  
>  	new_bw_state->active_pipes =
>  		intel_calc_active_pipes(state, old_bw_state->active_pipes);
> +
>  	if (new_bw_state->active_pipes != old_bw_state->active_pipes) {
>  		ret = intel_atomic_lock_global_state(&new_bw_state->base);
>  		if (ret)
> -- 
> 2.24.1.485.gad05a3d8e5

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v28 4/6] drm/i915: Add TGL+ SAGV support

[Ville Syrjälä]

On Thu, May 07, 2020 at 05:45:01PM +0300, Stanislav Lisovskiy wrote:
> Starting from TGL we need to have a separate wm0
> values for SAGV and non-SAGV which affects
> how calculations are done.
> 
> v2: Remove long lines
> v3: Removed COLOR_PLANE enum references
> v4, v5, v6: Fixed rebase conflict
> v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
>     - Removed sagv_uv_wm0(Ville)
>     - can_sagv->use_sagv_wm(Ville)
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
>  .../drm/i915/display/intel_display_types.h    |   2 +
>  drivers/gpu/drm/i915/intel_pm.c               | 118 +++++++++++++++++-
>  3 files changed, 121 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index fd6d63b03489..be5741cb7595 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  		/* Watermarks */
>  		for (level = 0; level <= max_level; level++) {
>  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> -						&sw_plane_wm->wm[level]))
> +						&sw_plane_wm->wm[level]) ||
> +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> +							       &sw_plane_wm->sagv_wm0)))
>  				continue;
>  
>  			drm_err(&dev_priv->drm,
> @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  		/* Watermarks */
>  		for (level = 0; level <= max_level; level++) {
>  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> -						&sw_plane_wm->wm[level]))
> +						&sw_plane_wm->wm[level]) ||
> +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> +							       &sw_plane_wm->sagv_wm0)))
>  				continue;
>  
>  			drm_err(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9488449e4b94..8cede29c9562 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -688,11 +688,13 @@ struct skl_plane_wm {
>  	struct skl_wm_level wm[8];
>  	struct skl_wm_level uv_wm[8];
>  	struct skl_wm_level trans_wm;
> +	struct skl_wm_level sagv_wm0;
>  	bool is_planar;
>  };
>  
>  struct skl_pipe_wm {
>  	struct skl_plane_wm planes[I915_MAX_PLANES];
> +	bool use_sagv_wm;
>  };
>  
>  enum vlv_wm_level {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index db188efee21e..934a686342ad 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3863,25 +3863,35 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
>  	return bw_state->pipe_sagv_reject == 0;
>  }
>  
> +static bool
> +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);

Just put the function here instead of adding fwd decalrations.

> +
>  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	int ret;
>  	struct intel_crtc *crtc;
> -	const struct intel_crtc_state *new_crtc_state;
> +	struct intel_crtc_state *new_crtc_state;
>  	struct intel_bw_state *new_bw_state = NULL;
>  	const struct intel_bw_state *old_bw_state = NULL;
>  	int i;
>  
>  	for_each_new_intel_crtc_in_state(state, crtc,
>  					 new_crtc_state, i) {
> +		bool can_sagv;
> +
>  		new_bw_state = intel_atomic_get_bw_state(state);
>  		if (IS_ERR(new_bw_state))
>  			return PTR_ERR(new_bw_state);
>  
>  		old_bw_state = intel_atomic_get_old_bw_state(state);
>  
> -		if (skl_crtc_can_enable_sagv(new_crtc_state))
> +		if (INTEL_GEN(dev_priv) >= 12)
> +			can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> +		else
> +			can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> +
> +		if (can_sagv)
>  			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
>  		else
>  			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> @@ -3899,6 +3909,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  			return ret;
>  	}
>  
> +	for_each_new_intel_crtc_in_state(state, crtc,
> +					 new_crtc_state, i) {
> +		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> +
> +		/*
> +		 * Due to drm limitation at commit state, when
> +		 * changes are written the whole atomic state is
> +		 * zeroed away => which prevents from using it,
> +		 * so just sticking it into pipe wm state for
> +		 * keeping it simple - anyway this is related to wm.
> +		 * Proper way in ideal universe would be of course not
> +		 * to lose parent atomic state object from child crtc_state,
> +		 * and stick to OOP programming principles, which had been
> +		 * scientifically proven to work.
> +		 */

More ramblings. Just drop this comment too imo.

> +		pipe_wm->use_sagv_wm = intel_can_enable_sagv(dev_priv, new_bw_state);

I think this should be 
gen >= 12 && intel_can_enable_sagv();

> +	}
> +
>  	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {
>  		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
>  		if (ret)
> @@ -4642,12 +4670,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
>  		   int level,
>  		   int color_plane)
>  {
> -	const struct skl_plane_wm *wm =
> -		&crtc_state->wm.skl.optimal.planes[plane_id];
> +	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> +	const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> +
> +	if (!level) {
> +		if (pipe_wm->use_sagv_wm)
> +			return &wm->sagv_wm0;
> +	}

if (level == 0 && use_sagv_wm)
	return sagv_wm0;

>  
>  	return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
>  }
>  
> +static bool
> +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	enum plane_id plane_id;
> +
> +	if (!crtc_state->hw.active)
> +		return true;
> +
> +	for_each_plane_id_on_crtc(crtc, plane_id) {
> +		const struct skl_ddb_entry *plane_alloc =
> +			&crtc_state->wm.skl.plane_ddb_y[plane_id];
> +		const struct skl_plane_wm *wm =
> +			&crtc_state->wm.skl.optimal.planes[plane_id];
> +
> +		if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
> +			return false;
> +	}
> +
> +	return true;
> +}
> +
>  static int
>  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>  {
> @@ -4684,7 +4739,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>  							 plane_data_rate,
>  							 uv_plane_data_rate);
>  
> -
>  	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
>  					   alloc, &num_active);
>  	alloc_size = skl_ddb_entry_size(alloc);
> @@ -5219,6 +5273,37 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
>  	}
>  }
>  
> +static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
> +				const struct skl_wm_params *wm_params,
> +				struct skl_plane_wm *plane_wm)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	struct skl_wm_level *sagv_wm = &plane_wm->sagv_wm0;
> +	struct skl_wm_level *levels = plane_wm->wm;
> +
> +	/*
> +	 * For Gen12 if it is an L0 we need to also
> +	 * consider sagv_block_time when calculating
> +	 * L0 watermark - we will need that when making
> +	 * a decision whether enable SAGV or not.
> +	 * For older gens we agreed to copy L0 value for
> +	 * compatibility.
> +	 */
> +	if ((INTEL_GEN(dev_priv) >= 12)) {

Drop this if-else and only call tgl_compute_sagv_wm() on tgl+.
The comment can then go as well I think.

> +		u32 latency = dev_priv->wm.skl_latency[0];
> +
> +		latency += dev_priv->sagv_block_time_us;
> +		skl_compute_plane_wm(crtc_state, 0, latency,
> +				     wm_params, &levels[0],
> +				     sagv_wm);
> +		DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
> +			      sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);

Leftover debugs. Pls remove.

> +	} else {
> +		/* Since all members are POD */
> +		*sagv_wm = levels[0];
> +	}
> +}
> +
>  static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
>  				      const struct skl_wm_params *wp,
>  				      struct skl_plane_wm *wm)
> @@ -5296,6 +5381,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
>  		return ret;
>  
>  	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> +	if (color_plane == 0)

We do want this for both the Y plane and UV plane.

> +		tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
>  	skl_compute_transition_wm(crtc_state, &wm_params, wm);
>  
>  	return 0;
> @@ -5702,6 +5789,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
>  				    enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
>  				    enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
>  
> +			drm_dbg_kms(&dev_priv->drm,
> +				    "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
> +				    plane->base.base.id, plane->base.name,
> +				    old_wm->sagv_wm0.plane_res_l,
> +				    new_wm->sagv_wm0.plane_res_l);
> +

IIRC I already suggested just slapping these onto the existing debug
prints instead of bloating the debug output with extra lines.

Ie instead of 
wms ... -> ...
sagv wm ... -> ...

we just get
wms ...,old_sagv_wm0 -> ...,new_sagv_wm0

just like we already do for eg. the transition wm.

>  			drm_dbg_kms(&dev_priv->drm,
>  				    "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
>  				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> @@ -5717,6 +5810,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
>  				    new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
>  				    new_wm->trans_wm.plane_res_b);
>  
> +			drm_dbg_kms(&dev_priv->drm,
> +				    "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
> +				    plane->base.base.id, plane->base.name,
> +				    old_wm->sagv_wm0.plane_res_b,
> +				    new_wm->sagv_wm0.plane_res_b);
> +
>  			drm_dbg_kms(&dev_priv->drm,
>  				    "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
>  				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> @@ -5731,6 +5830,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
>  				    new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
>  				    new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
>  				    new_wm->trans_wm.min_ddb_alloc);
> +
> +			drm_dbg_kms(&dev_priv->drm,
> +				    "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
> +				    plane->base.base.id, plane->base.name,
> +				    old_wm->sagv_wm0.min_ddb_alloc,
> +				    new_wm->sagv_wm0.min_ddb_alloc);
>  		}
>  	}
>  }
> @@ -6023,6 +6128,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>  			skl_wm_level_from_reg_val(val, &wm->wm[level]);
>  		}
>  
> +		memcpy(&wm->sagv_wm0, &wm->wm[0],
> +		       sizeof(struct skl_wm_level));

A simple assignment should suffice?

> +
>  		if (plane_id != PLANE_CURSOR)
>  			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
>  		else
> -- 
> 2.24.1.485.gad05a3d8e5

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v28 3/6] drm/i915: Make active_pipes check skl specific

[Lisovskiy, Stanislav]

On Tue, May 12, 2020 at 02:39:25PM +0300, Ville Syrjälä wrote:
> On Thu, May 07, 2020 at 05:45:00PM +0300, Stanislav Lisovskiy wrote:
> > Seems that only skl needs to have SAGV turned off
> > for multipipe scenarios, so lets do it this way.
> 
> It doesn't afaics. It's just someone added the check for some random
> reason. So this should be reworded a bit. Also this isn't just about
> skl/derivatives but all pre-icl so the <subject> is a bit misleading too.

This is in BSpec anyway. And it was in the code before, so I really 
don't get what do you mean here.

> 
> > 
> > If anything blows up - we can always revert this patch.
> > 
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++------
> >  drivers/gpu/drm/i915/intel_pm.h |  3 ++-
> >  2 files changed, 11 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 3dc1ad66beb3..db188efee21e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3777,7 +3777,7 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> >  	if (!new_bw_state)
> >  		return;
> >  
> > -	if (!intel_can_enable_sagv(new_bw_state))
> > +	if (!intel_can_enable_sagv(dev_priv, new_bw_state))
> >  		intel_disable_sagv(dev_priv);
> >  }
> >  
> > @@ -3800,7 +3800,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> >  	if (!new_bw_state)
> >  		return;
> >  
> > -	if (intel_can_enable_sagv(new_bw_state))
> > +	if (intel_can_enable_sagv(dev_priv, new_bw_state))
> >  		intel_enable_sagv(dev_priv);
> >  }
> >  
> > @@ -3853,16 +3853,19 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> >  	return true;
> >  }
> >  
> > -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > +			   const struct intel_bw_state *bw_state)
> >  {
> > -	if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > -		return false;
> > +	if (INTEL_GEN(dev_priv) < 11)
> > +		if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> 
> If (a && b && c)
> 	return false;

Then the line would get too long, and it does exactly same thing.
I really don't understand such comments.

Stan

> 
> 
> > +			return false;
> >  
> >  	return bw_state->pipe_sagv_reject == 0;
> >  }
> >  
> >  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> >  {
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> >  	int ret;
> >  	struct intel_crtc *crtc;
> >  	const struct intel_crtc_state *new_crtc_state;
> > @@ -3896,7 +3899,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> >  			return ret;
> >  	}
> >  
> > -	if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > +	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {
> 
> >  		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> >  		if (ret)
> >  			return ret;
> > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> > index fd1dc422e6c5..614ac7f8d4cc 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.h
> > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > @@ -42,7 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> >  			      struct skl_pipe_wm *out);
> >  void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> >  void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> > -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> > +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > +			   const struct intel_bw_state *bw_state);
> >  int intel_enable_sagv(struct drm_i915_private *dev_priv);
> >  int intel_disable_sagv(struct drm_i915_private *dev_priv);
> >  void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> > -- 
> > 2.24.1.485.gad05a3d8e5
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH v28 4/6] drm/i915: Add TGL+ SAGV support

[Lisovskiy, Stanislav]

On Tue, May 12, 2020 at 03:03:26PM +0300, Ville Syrjälä wrote:
> On Thu, May 07, 2020 at 05:45:01PM +0300, Stanislav Lisovskiy wrote:
> > Starting from TGL we need to have a separate wm0
> > values for SAGV and non-SAGV which affects
> > how calculations are done.
> > 
> > v2: Remove long lines
> > v3: Removed COLOR_PLANE enum references
> > v4, v5, v6: Fixed rebase conflict
> > v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
> >     - Removed sagv_uv_wm0(Ville)
> >     - can_sagv->use_sagv_wm(Ville)
> > 
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
> >  .../drm/i915/display/intel_display_types.h    |   2 +
> >  drivers/gpu/drm/i915/intel_pm.c               | 118 +++++++++++++++++-
> >  3 files changed, 121 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index fd6d63b03489..be5741cb7595 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> >  		/* Watermarks */
> >  		for (level = 0; level <= max_level; level++) {
> >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > -						&sw_plane_wm->wm[level]))
> > +						&sw_plane_wm->wm[level]) ||
> > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > +							       &sw_plane_wm->sagv_wm0)))
> >  				continue;
> >  
> >  			drm_err(&dev_priv->drm,
> > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> >  		/* Watermarks */
> >  		for (level = 0; level <= max_level; level++) {
> >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > -						&sw_plane_wm->wm[level]))
> > +						&sw_plane_wm->wm[level]) ||
> > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > +							       &sw_plane_wm->sagv_wm0)))
> >  				continue;
> >  
> >  			drm_err(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 9488449e4b94..8cede29c9562 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -688,11 +688,13 @@ struct skl_plane_wm {
> >  	struct skl_wm_level wm[8];
> >  	struct skl_wm_level uv_wm[8];
> >  	struct skl_wm_level trans_wm;
> > +	struct skl_wm_level sagv_wm0;
> >  	bool is_planar;
> >  };
> >  
> >  struct skl_pipe_wm {
> >  	struct skl_plane_wm planes[I915_MAX_PLANES];
> > +	bool use_sagv_wm;
> >  };
> >  
> >  enum vlv_wm_level {
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index db188efee21e..934a686342ad 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3863,25 +3863,35 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> >  	return bw_state->pipe_sagv_reject == 0;
> >  }
> >  
> > +static bool
> > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> 
> Just put the function here instead of adding fwd decalrations.
> 
> > +
> >  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> >  	int ret;
> >  	struct intel_crtc *crtc;
> > -	const struct intel_crtc_state *new_crtc_state;
> > +	struct intel_crtc_state *new_crtc_state;
> >  	struct intel_bw_state *new_bw_state = NULL;
> >  	const struct intel_bw_state *old_bw_state = NULL;
> >  	int i;
> >  
> >  	for_each_new_intel_crtc_in_state(state, crtc,
> >  					 new_crtc_state, i) {
> > +		bool can_sagv;
> > +
> >  		new_bw_state = intel_atomic_get_bw_state(state);
> >  		if (IS_ERR(new_bw_state))
> >  			return PTR_ERR(new_bw_state);
> >  
> >  		old_bw_state = intel_atomic_get_old_bw_state(state);
> >  
> > -		if (skl_crtc_can_enable_sagv(new_crtc_state))
> > +		if (INTEL_GEN(dev_priv) >= 12)
> > +			can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > +		else
> > +			can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > +
> > +		if (can_sagv)
> >  			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> >  		else
> >  			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > @@ -3899,6 +3909,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> >  			return ret;
> >  	}
> >  
> > +	for_each_new_intel_crtc_in_state(state, crtc,
> > +					 new_crtc_state, i) {
> > +		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > +
> > +		/*
> > +		 * Due to drm limitation at commit state, when
> > +		 * changes are written the whole atomic state is
> > +		 * zeroed away => which prevents from using it,
> > +		 * so just sticking it into pipe wm state for
> > +		 * keeping it simple - anyway this is related to wm.
> > +		 * Proper way in ideal universe would be of course not
> > +		 * to lose parent atomic state object from child crtc_state,
> > +		 * and stick to OOP programming principles, which had been
> > +		 * scientifically proven to work.
> > +		 */
> 
> More ramblings. Just drop this comment too imo.

As I understand what is happening here is rather weird, so I thought 
commenting is good idea.

> 
> > +		pipe_wm->use_sagv_wm = intel_can_enable_sagv(dev_priv, new_bw_state);
> 
> I think this should be 
> gen >= 12 && intel_can_enable_sagv();
> 
> > +	}
> > +
> >  	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {
> >  		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> >  		if (ret)
> > @@ -4642,12 +4670,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
> >  		   int level,
> >  		   int color_plane)
> >  {
> > -	const struct skl_plane_wm *wm =
> > -		&crtc_state->wm.skl.optimal.planes[plane_id];
> > +	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > +	const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> > +
> > +	if (!level) {
> > +		if (pipe_wm->use_sagv_wm)
> > +			return &wm->sagv_wm0;
> > +	}
> 
> if (level == 0 && use_sagv_wm)
> 	return sagv_wm0;
> 
> >  
> >  	return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
> >  }
> >  
> > +static bool
> > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	enum plane_id plane_id;
> > +
> > +	if (!crtc_state->hw.active)
> > +		return true;
> > +
> > +	for_each_plane_id_on_crtc(crtc, plane_id) {
> > +		const struct skl_ddb_entry *plane_alloc =
> > +			&crtc_state->wm.skl.plane_ddb_y[plane_id];
> > +		const struct skl_plane_wm *wm =
> > +			&crtc_state->wm.skl.optimal.planes[plane_id];
> > +
> > +		if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
> > +			return false;
> > +	}
> > +
> > +	return true;
> > +}
> > +
> >  static int
> >  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> >  {
> > @@ -4684,7 +4739,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> >  							 plane_data_rate,
> >  							 uv_plane_data_rate);
> >  
> > -
> >  	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
> >  					   alloc, &num_active);
> >  	alloc_size = skl_ddb_entry_size(alloc);
> > @@ -5219,6 +5273,37 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> >  	}
> >  }
> >  
> > +static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
> > +				const struct skl_wm_params *wm_params,
> > +				struct skl_plane_wm *plane_wm)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > +	struct skl_wm_level *sagv_wm = &plane_wm->sagv_wm0;
> > +	struct skl_wm_level *levels = plane_wm->wm;
> > +
> > +	/*
> > +	 * For Gen12 if it is an L0 we need to also
> > +	 * consider sagv_block_time when calculating
> > +	 * L0 watermark - we will need that when making
> > +	 * a decision whether enable SAGV or not.
> > +	 * For older gens we agreed to copy L0 value for
> > +	 * compatibility.
> > +	 */
> > +	if ((INTEL_GEN(dev_priv) >= 12)) {
> 
> Drop this if-else and only call tgl_compute_sagv_wm() on tgl+.
> The comment can then go as well I think.

We actually had _agreed_ with you personally that I do copy
wm0 values for other platforms for compatibility reasons.
Now after one month you say that we are going to call this
only for gen12. 

> 
> > +		u32 latency = dev_priv->wm.skl_latency[0];
> > +
> > +		latency += dev_priv->sagv_block_time_us;
> > +		skl_compute_plane_wm(crtc_state, 0, latency,
> > +				     wm_params, &levels[0],
> > +				     sagv_wm);
> > +		DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
> > +			      sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
> 
> Leftover debugs. Pls remove.

I thought this might be useful, we should have some understanding what
is happening, i.e what was the reasoning and why SAGV was switched on/off.
Not crucial, but really don't understand why this is _that_ harmful.
We have plenty of wm/ddb debugs anyway, but no way to figure out how SAGV logic is working.

> 
> > +	} else {
> > +		/* Since all members are POD */
> > +		*sagv_wm = levels[0];
> > +	}
> > +}
> > +
> >  static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> >  				      const struct skl_wm_params *wp,
> >  				      struct skl_plane_wm *wm)
> > @@ -5296,6 +5381,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> >  		return ret;
> >  
> >  	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> > +	if (color_plane == 0)
> 
> We do want this for both the Y plane and UV plane.
> 
> > +		tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
> >  	skl_compute_transition_wm(crtc_state, &wm_params, wm);
> >  
> >  	return 0;
> > @@ -5702,6 +5789,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> >  				    enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
> >  				    enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
> >  
> > +			drm_dbg_kms(&dev_priv->drm,
> > +				    "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
> > +				    plane->base.base.id, plane->base.name,
> > +				    old_wm->sagv_wm0.plane_res_l,
> > +				    new_wm->sagv_wm0.plane_res_l);
> > +
> 
> IIRC I already suggested just slapping these onto the existing debug
> prints instead of bloating the debug output with extra lines.
> 
> Ie instead of 
> wms ... -> ...
> sagv wm ... -> ...
> 
> we just get
> wms ...,old_sagv_wm0 -> ...,new_sagv_wm0
> 
> just like we already do for eg. the transition wm.

Not sure about this one. I will check, I thought you suggested the opposite,
i.e do those debugs separately.

Stan
> 
> >  			drm_dbg_kms(&dev_priv->drm,
> >  				    "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> >  				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > @@ -5717,6 +5810,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> >  				    new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
> >  				    new_wm->trans_wm.plane_res_b);
> >  
> > +			drm_dbg_kms(&dev_priv->drm,
> > +				    "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
> > +				    plane->base.base.id, plane->base.name,
> > +				    old_wm->sagv_wm0.plane_res_b,
> > +				    new_wm->sagv_wm0.plane_res_b);
> > +
> >  			drm_dbg_kms(&dev_priv->drm,
> >  				    "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> >  				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > @@ -5731,6 +5830,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> >  				    new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
> >  				    new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
> >  				    new_wm->trans_wm.min_ddb_alloc);
> > +
> > +			drm_dbg_kms(&dev_priv->drm,
> > +				    "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
> > +				    plane->base.base.id, plane->base.name,
> > +				    old_wm->sagv_wm0.min_ddb_alloc,
> > +				    new_wm->sagv_wm0.min_ddb_alloc);
> >  		}
> >  	}
> >  }
> > @@ -6023,6 +6128,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> >  			skl_wm_level_from_reg_val(val, &wm->wm[level]);
> >  		}
> >  
> > +		memcpy(&wm->sagv_wm0, &wm->wm[0],
> > +		       sizeof(struct skl_wm_level));
> 
> A simple assignment should suffice?

Agree.

> 
> > +
> >  		if (plane_id != PLANE_CURSOR)
> >  			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
> >  		else
> > -- 
> > 2.24.1.485.gad05a3d8e5
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH v28 3/6] drm/i915: Make active_pipes check skl specific

[Ville Syrjälä]

On Tue, May 12, 2020 at 03:44:06PM +0300, Lisovskiy, Stanislav wrote:
> On Tue, May 12, 2020 at 02:39:25PM +0300, Ville Syrjälä wrote:
> > On Thu, May 07, 2020 at 05:45:00PM +0300, Stanislav Lisovskiy wrote:
> > > Seems that only skl needs to have SAGV turned off
> > > for multipipe scenarios, so lets do it this way.
> > 
> > It doesn't afaics. It's just someone added the check for some random
> > reason. So this should be reworded a bit. Also this isn't just about
> > skl/derivatives but all pre-icl so the <subject> is a bit misleading too.
> 
> This is in BSpec anyway. And it was in the code before, so I really 
> don't get what do you mean here.

That's not what it says. It just suggests that if you guarantee that
you always have enough ddb for sagv in single pipe configuration then
you can just toggle sagv when transitioning between single vs. multi
pipe configurations. The implication being that you don't guarantee
enough ddb for sagv in multi pipe configurations, hence you simply
assume sagv can't be used with multiple pipes.

We don't even guarantee that out single pipe configuration has enough
ddb for sagv, hence we have to actually check the block time constraint
even in single pipe configurations. That makes the whole bspec paragraph
moot and we might as well just do the obvious thing and check the sagv
block time for all pipes (which we're already doing anyway).

> 
> > 
> > > 
> > > If anything blows up - we can always revert this patch.
> > > 
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++------
> > >  drivers/gpu/drm/i915/intel_pm.h |  3 ++-
> > >  2 files changed, 11 insertions(+), 7 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 3dc1ad66beb3..db188efee21e 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3777,7 +3777,7 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > >  	if (!new_bw_state)
> > >  		return;
> > >  
> > > -	if (!intel_can_enable_sagv(new_bw_state))
> > > +	if (!intel_can_enable_sagv(dev_priv, new_bw_state))
> > >  		intel_disable_sagv(dev_priv);
> > >  }
> > >  
> > > @@ -3800,7 +3800,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> > >  	if (!new_bw_state)
> > >  		return;
> > >  
> > > -	if (intel_can_enable_sagv(new_bw_state))
> > > +	if (intel_can_enable_sagv(dev_priv, new_bw_state))
> > >  		intel_enable_sagv(dev_priv);
> > >  }
> > >  
> > > @@ -3853,16 +3853,19 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > >  	return true;
> > >  }
> > >  
> > > -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > +			   const struct intel_bw_state *bw_state)
> > >  {
> > > -	if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > -		return false;
> > > +	if (INTEL_GEN(dev_priv) < 11)
> > > +		if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > 
> > If (a && b && c)
> > 	return false;
> 
> Then the line would get too long, and it does exactly same thing.
> I really don't understand such comments.
> 
> Stan
> 
> > 
> > 
> > > +			return false;
> > >  
> > >  	return bw_state->pipe_sagv_reject == 0;
> > >  }
> > >  
> > >  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > >  {
> > > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > >  	int ret;
> > >  	struct intel_crtc *crtc;
> > >  	const struct intel_crtc_state *new_crtc_state;
> > > @@ -3896,7 +3899,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > >  			return ret;
> > >  	}
> > >  
> > > -	if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > > +	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {
> > 
> > >  		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > >  		if (ret)
> > >  			return ret;
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> > > index fd1dc422e6c5..614ac7f8d4cc 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.h
> > > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > > @@ -42,7 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > >  			      struct skl_pipe_wm *out);
> > >  void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > >  void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> > > -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> > > +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > +			   const struct intel_bw_state *bw_state);
> > >  int intel_enable_sagv(struct drm_i915_private *dev_priv);
> > >  int intel_disable_sagv(struct drm_i915_private *dev_priv);
> > >  void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> > > -- 
> > > 2.24.1.485.gad05a3d8e5
> > 
> > -- 
> > Ville Syrjälä
> > Intel

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v28 4/6] drm/i915: Add TGL+ SAGV support

[Ville Syrjälä]

On Tue, May 12, 2020 at 03:52:27PM +0300, Lisovskiy, Stanislav wrote:
> On Tue, May 12, 2020 at 03:03:26PM +0300, Ville Syrjälä wrote:
> > On Thu, May 07, 2020 at 05:45:01PM +0300, Stanislav Lisovskiy wrote:
> > > Starting from TGL we need to have a separate wm0
> > > values for SAGV and non-SAGV which affects
> > > how calculations are done.
> > > 
> > > v2: Remove long lines
> > > v3: Removed COLOR_PLANE enum references
> > > v4, v5, v6: Fixed rebase conflict
> > > v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
> > >     - Removed sagv_uv_wm0(Ville)
> > >     - can_sagv->use_sagv_wm(Ville)
> > > 
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
> > >  .../drm/i915/display/intel_display_types.h    |   2 +
> > >  drivers/gpu/drm/i915/intel_pm.c               | 118 +++++++++++++++++-
> > >  3 files changed, 121 insertions(+), 7 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index fd6d63b03489..be5741cb7595 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > >  		/* Watermarks */
> > >  		for (level = 0; level <= max_level; level++) {
> > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > -						&sw_plane_wm->wm[level]))
> > > +						&sw_plane_wm->wm[level]) ||
> > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > +							       &sw_plane_wm->sagv_wm0)))
> > >  				continue;
> > >  
> > >  			drm_err(&dev_priv->drm,
> > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > >  		/* Watermarks */
> > >  		for (level = 0; level <= max_level; level++) {
> > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > -						&sw_plane_wm->wm[level]))
> > > +						&sw_plane_wm->wm[level]) ||
> > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > +							       &sw_plane_wm->sagv_wm0)))
> > >  				continue;
> > >  
> > >  			drm_err(&dev_priv->drm,
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 9488449e4b94..8cede29c9562 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -688,11 +688,13 @@ struct skl_plane_wm {
> > >  	struct skl_wm_level wm[8];
> > >  	struct skl_wm_level uv_wm[8];
> > >  	struct skl_wm_level trans_wm;
> > > +	struct skl_wm_level sagv_wm0;
> > >  	bool is_planar;
> > >  };
> > >  
> > >  struct skl_pipe_wm {
> > >  	struct skl_plane_wm planes[I915_MAX_PLANES];
> > > +	bool use_sagv_wm;
> > >  };
> > >  
> > >  enum vlv_wm_level {
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index db188efee21e..934a686342ad 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3863,25 +3863,35 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > >  	return bw_state->pipe_sagv_reject == 0;
> > >  }
> > >  
> > > +static bool
> > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > 
> > Just put the function here instead of adding fwd decalrations.
> > 
> > > +
> > >  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > >  {
> > >  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > >  	int ret;
> > >  	struct intel_crtc *crtc;
> > > -	const struct intel_crtc_state *new_crtc_state;
> > > +	struct intel_crtc_state *new_crtc_state;
> > >  	struct intel_bw_state *new_bw_state = NULL;
> > >  	const struct intel_bw_state *old_bw_state = NULL;
> > >  	int i;
> > >  
> > >  	for_each_new_intel_crtc_in_state(state, crtc,
> > >  					 new_crtc_state, i) {
> > > +		bool can_sagv;
> > > +
> > >  		new_bw_state = intel_atomic_get_bw_state(state);
> > >  		if (IS_ERR(new_bw_state))
> > >  			return PTR_ERR(new_bw_state);
> > >  
> > >  		old_bw_state = intel_atomic_get_old_bw_state(state);
> > >  
> > > -		if (skl_crtc_can_enable_sagv(new_crtc_state))
> > > +		if (INTEL_GEN(dev_priv) >= 12)
> > > +			can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > > +		else
> > > +			can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > +
> > > +		if (can_sagv)
> > >  			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > >  		else
> > >  			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > @@ -3899,6 +3909,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > >  			return ret;
> > >  	}
> > >  
> > > +	for_each_new_intel_crtc_in_state(state, crtc,
> > > +					 new_crtc_state, i) {
> > > +		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > +
> > > +		/*
> > > +		 * Due to drm limitation at commit state, when
> > > +		 * changes are written the whole atomic state is
> > > +		 * zeroed away => which prevents from using it,
> > > +		 * so just sticking it into pipe wm state for
> > > +		 * keeping it simple - anyway this is related to wm.
> > > +		 * Proper way in ideal universe would be of course not
> > > +		 * to lose parent atomic state object from child crtc_state,
> > > +		 * and stick to OOP programming principles, which had been
> > > +		 * scientifically proven to work.
> > > +		 */
> > 
> > More ramblings. Just drop this comment too imo.
> 
> As I understand what is happening here is rather weird, so I thought 
> commenting is good idea.

At least I have no idea what the comment is trying to say.
I see nothing weird hapening here, we're just computing the
state which is totally standard stuff.

> 
> > 
> > > +		pipe_wm->use_sagv_wm = intel_can_enable_sagv(dev_priv, new_bw_state);
> > 
> > I think this should be 
> > gen >= 12 && intel_can_enable_sagv();
> > 
> > > +	}
> > > +
> > >  	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {
> > >  		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > >  		if (ret)
> > > @@ -4642,12 +4670,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
> > >  		   int level,
> > >  		   int color_plane)
> > >  {
> > > -	const struct skl_plane_wm *wm =
> > > -		&crtc_state->wm.skl.optimal.planes[plane_id];
> > > +	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > > +	const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> > > +
> > > +	if (!level) {
> > > +		if (pipe_wm->use_sagv_wm)
> > > +			return &wm->sagv_wm0;
> > > +	}
> > 
> > if (level == 0 && use_sagv_wm)
> > 	return sagv_wm0;
> > 
> > >  
> > >  	return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
> > >  }
> > >  
> > > +static bool
> > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > +{
> > > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > +	enum plane_id plane_id;
> > > +
> > > +	if (!crtc_state->hw.active)
> > > +		return true;
> > > +
> > > +	for_each_plane_id_on_crtc(crtc, plane_id) {
> > > +		const struct skl_ddb_entry *plane_alloc =
> > > +			&crtc_state->wm.skl.plane_ddb_y[plane_id];
> > > +		const struct skl_plane_wm *wm =
> > > +			&crtc_state->wm.skl.optimal.planes[plane_id];
> > > +
> > > +		if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
> > > +			return false;
> > > +	}
> > > +
> > > +	return true;
> > > +}
> > > +
> > >  static int
> > >  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> > >  {
> > > @@ -4684,7 +4739,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> > >  							 plane_data_rate,
> > >  							 uv_plane_data_rate);
> > >  
> > > -
> > >  	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
> > >  					   alloc, &num_active);
> > >  	alloc_size = skl_ddb_entry_size(alloc);
> > > @@ -5219,6 +5273,37 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > >  	}
> > >  }
> > >  
> > > +static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
> > > +				const struct skl_wm_params *wm_params,
> > > +				struct skl_plane_wm *plane_wm)
> > > +{
> > > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > +	struct skl_wm_level *sagv_wm = &plane_wm->sagv_wm0;
> > > +	struct skl_wm_level *levels = plane_wm->wm;
> > > +
> > > +	/*
> > > +	 * For Gen12 if it is an L0 we need to also
> > > +	 * consider sagv_block_time when calculating
> > > +	 * L0 watermark - we will need that when making
> > > +	 * a decision whether enable SAGV or not.
> > > +	 * For older gens we agreed to copy L0 value for
> > > +	 * compatibility.
> > > +	 */
> > > +	if ((INTEL_GEN(dev_priv) >= 12)) {
> > 
> > Drop this if-else and only call tgl_compute_sagv_wm() on tgl+.
> > The comment can then go as well I think.
> 
> We actually had _agreed_ with you personally that I do copy
> wm0 values for other platforms for compatibility reasons.
> Now after one month you say that we are going to call this
> only for gen12. 

I see no point in having this populated for pre-tgl.

> 
> > 
> > > +		u32 latency = dev_priv->wm.skl_latency[0];
> > > +
> > > +		latency += dev_priv->sagv_block_time_us;
> > > +		skl_compute_plane_wm(crtc_state, 0, latency,
> > > +				     wm_params, &levels[0],
> > > +				     sagv_wm);
> > > +		DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
> > > +			      sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
> > 
> > Leftover debugs. Pls remove.
> 
> I thought this might be useful, we should have some understanding what
> is happening, i.e what was the reasoning and why SAGV was switched on/off.
> Not crucial, but really don't understand why this is _that_ harmful.
> We have plenty of wm/ddb debugs anyway, but no way to figure out how SAGV logic is working.

If we need more debugs they need to added carefully so as to not totally
blow up the logs. I think this here would spam the logs heavily.

> 
> > 
> > > +	} else {
> > > +		/* Since all members are POD */
> > > +		*sagv_wm = levels[0];
> > > +	}
> > > +}
> > > +
> > >  static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> > >  				      const struct skl_wm_params *wp,
> > >  				      struct skl_plane_wm *wm)
> > > @@ -5296,6 +5381,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> > >  		return ret;
> > >  
> > >  	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> > > +	if (color_plane == 0)
> > 
> > We do want this for both the Y plane and UV plane.
> > 
> > > +		tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
> > >  	skl_compute_transition_wm(crtc_state, &wm_params, wm);
> > >  
> > >  	return 0;
> > > @@ -5702,6 +5789,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > >  				    enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
> > >  				    enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
> > >  
> > > +			drm_dbg_kms(&dev_priv->drm,
> > > +				    "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
> > > +				    plane->base.base.id, plane->base.name,
> > > +				    old_wm->sagv_wm0.plane_res_l,
> > > +				    new_wm->sagv_wm0.plane_res_l);
> > > +
> > 
> > IIRC I already suggested just slapping these onto the existing debug
> > prints instead of bloating the debug output with extra lines.
> > 
> > Ie instead of 
> > wms ... -> ...
> > sagv wm ... -> ...
> > 
> > we just get
> > wms ...,old_sagv_wm0 -> ...,new_sagv_wm0
> > 
> > just like we already do for eg. the transition wm.
> 
> Not sure about this one. I will check, I thought you suggested the opposite,
> i.e do those debugs separately.
> 
> Stan
> > 
> > >  			drm_dbg_kms(&dev_priv->drm,
> > >  				    "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > >  				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > > @@ -5717,6 +5810,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > >  				    new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
> > >  				    new_wm->trans_wm.plane_res_b);
> > >  
> > > +			drm_dbg_kms(&dev_priv->drm,
> > > +				    "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
> > > +				    plane->base.base.id, plane->base.name,
> > > +				    old_wm->sagv_wm0.plane_res_b,
> > > +				    new_wm->sagv_wm0.plane_res_b);
> > > +
> > >  			drm_dbg_kms(&dev_priv->drm,
> > >  				    "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > >  				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > > @@ -5731,6 +5830,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > >  				    new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
> > >  				    new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
> > >  				    new_wm->trans_wm.min_ddb_alloc);
> > > +
> > > +			drm_dbg_kms(&dev_priv->drm,
> > > +				    "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
> > > +				    plane->base.base.id, plane->base.name,
> > > +				    old_wm->sagv_wm0.min_ddb_alloc,
> > > +				    new_wm->sagv_wm0.min_ddb_alloc);
> > >  		}
> > >  	}
> > >  }
> > > @@ -6023,6 +6128,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > >  			skl_wm_level_from_reg_val(val, &wm->wm[level]);
> > >  		}
> > >  
> > > +		memcpy(&wm->sagv_wm0, &wm->wm[0],
> > > +		       sizeof(struct skl_wm_level));
> > 
> > A simple assignment should suffice?
> 
> Agree.
> 
> > 
> > > +
> > >  		if (plane_id != PLANE_CURSOR)
> > >  			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
> > >  		else
> > > -- 
> > > 2.24.1.485.gad05a3d8e5
> > 
> > -- 
> > Ville Syrjälä
> > Intel

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v28 3/6] drm/i915: Make active_pipes check skl specific

[Ville Syrjälä]

On Tue, May 12, 2020 at 03:44:06PM +0300, Lisovskiy, Stanislav wrote:
> On Tue, May 12, 2020 at 02:39:25PM +0300, Ville Syrjälä wrote:
> > On Thu, May 07, 2020 at 05:45:00PM +0300, Stanislav Lisovskiy wrote:
> > > Seems that only skl needs to have SAGV turned off
> > > for multipipe scenarios, so lets do it this way.
> > 
> > It doesn't afaics. It's just someone added the check for some random
> > reason. So this should be reworded a bit. Also this isn't just about
> > skl/derivatives but all pre-icl so the <subject> is a bit misleading too.
> 
> This is in BSpec anyway. And it was in the code before, so I really 
> don't get what do you mean here.
> 
> > 
> > > 
> > > If anything blows up - we can always revert this patch.
> > > 
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++------
> > >  drivers/gpu/drm/i915/intel_pm.h |  3 ++-
> > >  2 files changed, 11 insertions(+), 7 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 3dc1ad66beb3..db188efee21e 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3777,7 +3777,7 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > >  	if (!new_bw_state)
> > >  		return;
> > >  
> > > -	if (!intel_can_enable_sagv(new_bw_state))
> > > +	if (!intel_can_enable_sagv(dev_priv, new_bw_state))
> > >  		intel_disable_sagv(dev_priv);
> > >  }
> > >  
> > > @@ -3800,7 +3800,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> > >  	if (!new_bw_state)
> > >  		return;
> > >  
> > > -	if (intel_can_enable_sagv(new_bw_state))
> > > +	if (intel_can_enable_sagv(dev_priv, new_bw_state))
> > >  		intel_enable_sagv(dev_priv);
> > >  }
> > >  
> > > @@ -3853,16 +3853,19 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > >  	return true;
> > >  }
> > >  
> > > -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > +			   const struct intel_bw_state *bw_state)
> > >  {
> > > -	if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > -		return false;
> > > +	if (INTEL_GEN(dev_priv) < 11)
> > > +		if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > 
> > If (a && b && c)
> > 	return false;
> 
> Then the line would get too long, and it does exactly same thing.
> I really don't understand such comments.

if (a && b &&
    c)

if (a &&
    b && c)

if (a &&
    b &&
    c)

there are plenty of options. The point is nested ifs like this
only serve to indent code needlessly deep.


> 
> Stan
> 
> > 
> > 
> > > +			return false;
> > >  
> > >  	return bw_state->pipe_sagv_reject == 0;
> > >  }
> > >  
> > >  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > >  {
> > > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > >  	int ret;
> > >  	struct intel_crtc *crtc;
> > >  	const struct intel_crtc_state *new_crtc_state;
> > > @@ -3896,7 +3899,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > >  			return ret;
> > >  	}
> > >  
> > > -	if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > > +	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {
> > 
> > >  		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > >  		if (ret)
> > >  			return ret;
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> > > index fd1dc422e6c5..614ac7f8d4cc 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.h
> > > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > > @@ -42,7 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > >  			      struct skl_pipe_wm *out);
> > >  void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > >  void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> > > -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> > > +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > +			   const struct intel_bw_state *bw_state);
> > >  int intel_enable_sagv(struct drm_i915_private *dev_priv);
> > >  int intel_disable_sagv(struct drm_i915_private *dev_priv);
> > >  void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> > > -- 
> > > 2.24.1.485.gad05a3d8e5
> > 
> > -- 
> > Ville Syrjälä
> > Intel

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v28 4/6] drm/i915: Add TGL+ SAGV support

[Lisovskiy, Stanislav]

On Tue, May 12, 2020 at 04:10:46PM +0300, Ville Syrjälä wrote:
> On Tue, May 12, 2020 at 03:52:27PM +0300, Lisovskiy, Stanislav wrote:
> > On Tue, May 12, 2020 at 03:03:26PM +0300, Ville Syrjälä wrote:
> > > On Thu, May 07, 2020 at 05:45:01PM +0300, Stanislav Lisovskiy wrote:
> > > > Starting from TGL we need to have a separate wm0
> > > > values for SAGV and non-SAGV which affects
> > > > how calculations are done.
> > > > 
> > > > v2: Remove long lines
> > > > v3: Removed COLOR_PLANE enum references
> > > > v4, v5, v6: Fixed rebase conflict
> > > > v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
> > > >     - Removed sagv_uv_wm0(Ville)
> > > >     - can_sagv->use_sagv_wm(Ville)
> > > > 
> > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
> > > >  .../drm/i915/display/intel_display_types.h    |   2 +
> > > >  drivers/gpu/drm/i915/intel_pm.c               | 118 +++++++++++++++++-
> > > >  3 files changed, 121 insertions(+), 7 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index fd6d63b03489..be5741cb7595 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > >  		/* Watermarks */
> > > >  		for (level = 0; level <= max_level; level++) {
> > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > -						&sw_plane_wm->wm[level]))
> > > > +						&sw_plane_wm->wm[level]) ||
> > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > +							       &sw_plane_wm->sagv_wm0)))
> > > >  				continue;
> > > >  
> > > >  			drm_err(&dev_priv->drm,
> > > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > >  		/* Watermarks */
> > > >  		for (level = 0; level <= max_level; level++) {
> > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > -						&sw_plane_wm->wm[level]))
> > > > +						&sw_plane_wm->wm[level]) ||
> > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > +							       &sw_plane_wm->sagv_wm0)))
> > > >  				continue;
> > > >  
> > > >  			drm_err(&dev_priv->drm,
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 9488449e4b94..8cede29c9562 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -688,11 +688,13 @@ struct skl_plane_wm {
> > > >  	struct skl_wm_level wm[8];
> > > >  	struct skl_wm_level uv_wm[8];
> > > >  	struct skl_wm_level trans_wm;
> > > > +	struct skl_wm_level sagv_wm0;
> > > >  	bool is_planar;
> > > >  };
> > > >  
> > > >  struct skl_pipe_wm {
> > > >  	struct skl_plane_wm planes[I915_MAX_PLANES];
> > > > +	bool use_sagv_wm;
> > > >  };
> > > >  
> > > >  enum vlv_wm_level {
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index db188efee21e..934a686342ad 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -3863,25 +3863,35 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > >  	return bw_state->pipe_sagv_reject == 0;
> > > >  }
> > > >  
> > > > +static bool
> > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > > 
> > > Just put the function here instead of adding fwd decalrations.
> > > 
> > > > +
> > > >  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > >  {
> > > >  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > >  	int ret;
> > > >  	struct intel_crtc *crtc;
> > > > -	const struct intel_crtc_state *new_crtc_state;
> > > > +	struct intel_crtc_state *new_crtc_state;
> > > >  	struct intel_bw_state *new_bw_state = NULL;
> > > >  	const struct intel_bw_state *old_bw_state = NULL;
> > > >  	int i;
> > > >  
> > > >  	for_each_new_intel_crtc_in_state(state, crtc,
> > > >  					 new_crtc_state, i) {
> > > > +		bool can_sagv;
> > > > +
> > > >  		new_bw_state = intel_atomic_get_bw_state(state);
> > > >  		if (IS_ERR(new_bw_state))
> > > >  			return PTR_ERR(new_bw_state);
> > > >  
> > > >  		old_bw_state = intel_atomic_get_old_bw_state(state);
> > > >  
> > > > -		if (skl_crtc_can_enable_sagv(new_crtc_state))
> > > > +		if (INTEL_GEN(dev_priv) >= 12)
> > > > +			can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > > > +		else
> > > > +			can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > > +
> > > > +		if (can_sagv)
> > > >  			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > >  		else
> > > >  			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > @@ -3899,6 +3909,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > >  			return ret;
> > > >  	}
> > > >  
> > > > +	for_each_new_intel_crtc_in_state(state, crtc,
> > > > +					 new_crtc_state, i) {
> > > > +		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > > +
> > > > +		/*
> > > > +		 * Due to drm limitation at commit state, when
> > > > +		 * changes are written the whole atomic state is
> > > > +		 * zeroed away => which prevents from using it,
> > > > +		 * so just sticking it into pipe wm state for
> > > > +		 * keeping it simple - anyway this is related to wm.
> > > > +		 * Proper way in ideal universe would be of course not
> > > > +		 * to lose parent atomic state object from child crtc_state,
> > > > +		 * and stick to OOP programming principles, which had been
> > > > +		 * scientifically proven to work.
> > > > +		 */
> > > 
> > > More ramblings. Just drop this comment too imo.
> > 
> > As I understand what is happening here is rather weird, so I thought 
> > commenting is good idea.
> 
> At least I have no idea what the comment is trying to say.
> I see nothing weird hapening here, we're just computing the
> state which is totally standard stuff.

Well I can remind, this is because there is no way to get parent state
from crtc_state, because of weird drm atomic behaviour which leaves us
with NULL parent state. So that we had to stick this boolean to some
place.
In normal code universe this wouldn't even be needed if we could
just get atomic state from crtc_state when we write wm in skl_write_plane_wm.

However probably OOP principles like parent-child hieararchy is not a thing
here. That what this comment was trying to say.

In normal OOP you can't destroy parent object _before_ destroying
child one.

Stan

> 
> > 
> > > 
> > > > +		pipe_wm->use_sagv_wm = intel_can_enable_sagv(dev_priv, new_bw_state);
> > > 
> > > I think this should be 
> > > gen >= 12 && intel_can_enable_sagv();
> > > 
> > > > +	}
> > > > +
> > > >  	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {
> > > >  		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > > >  		if (ret)
> > > > @@ -4642,12 +4670,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
> > > >  		   int level,
> > > >  		   int color_plane)
> > > >  {
> > > > -	const struct skl_plane_wm *wm =
> > > > -		&crtc_state->wm.skl.optimal.planes[plane_id];
> > > > +	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > > > +	const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> > > > +
> > > > +	if (!level) {
> > > > +		if (pipe_wm->use_sagv_wm)
> > > > +			return &wm->sagv_wm0;
> > > > +	}
> > > 
> > > if (level == 0 && use_sagv_wm)
> > > 	return sagv_wm0;
> > > 
> > > >  
> > > >  	return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
> > > >  }
> > > >  
> > > > +static bool
> > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > +{
> > > > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > +	enum plane_id plane_id;
> > > > +
> > > > +	if (!crtc_state->hw.active)
> > > > +		return true;
> > > > +
> > > > +	for_each_plane_id_on_crtc(crtc, plane_id) {
> > > > +		const struct skl_ddb_entry *plane_alloc =
> > > > +			&crtc_state->wm.skl.plane_ddb_y[plane_id];
> > > > +		const struct skl_plane_wm *wm =
> > > > +			&crtc_state->wm.skl.optimal.planes[plane_id];
> > > > +
> > > > +		if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
> > > > +			return false;
> > > > +	}
> > > > +
> > > > +	return true;
> > > > +}
> > > > +
> > > >  static int
> > > >  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> > > >  {
> > > > @@ -4684,7 +4739,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> > > >  							 plane_data_rate,
> > > >  							 uv_plane_data_rate);
> > > >  
> > > > -
> > > >  	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
> > > >  					   alloc, &num_active);
> > > >  	alloc_size = skl_ddb_entry_size(alloc);
> > > > @@ -5219,6 +5273,37 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > > >  	}
> > > >  }
> > > >  
> > > > +static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
> > > > +				const struct skl_wm_params *wm_params,
> > > > +				struct skl_plane_wm *plane_wm)
> > > > +{
> > > > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > > > +	struct skl_wm_level *sagv_wm = &plane_wm->sagv_wm0;
> > > > +	struct skl_wm_level *levels = plane_wm->wm;
> > > > +
> > > > +	/*
> > > > +	 * For Gen12 if it is an L0 we need to also
> > > > +	 * consider sagv_block_time when calculating
> > > > +	 * L0 watermark - we will need that when making
> > > > +	 * a decision whether enable SAGV or not.
> > > > +	 * For older gens we agreed to copy L0 value for
> > > > +	 * compatibility.
> > > > +	 */
> > > > +	if ((INTEL_GEN(dev_priv) >= 12)) {
> > > 
> > > Drop this if-else and only call tgl_compute_sagv_wm() on tgl+.
> > > The comment can then go as well I think.
> > 
> > We actually had _agreed_ with you personally that I do copy
> > wm0 values for other platforms for compatibility reasons.
> > Now after one month you say that we are going to call this
> > only for gen12. 
> 
> I see no point in having this populated for pre-tgl.
> 
> > 
> > > 
> > > > +		u32 latency = dev_priv->wm.skl_latency[0];
> > > > +
> > > > +		latency += dev_priv->sagv_block_time_us;
> > > > +		skl_compute_plane_wm(crtc_state, 0, latency,
> > > > +				     wm_params, &levels[0],
> > > > +				     sagv_wm);
> > > > +		DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
> > > > +			      sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
> > > 
> > > Leftover debugs. Pls remove.
> > 
> > I thought this might be useful, we should have some understanding what
> > is happening, i.e what was the reasoning and why SAGV was switched on/off.
> > Not crucial, but really don't understand why this is _that_ harmful.
> > We have plenty of wm/ddb debugs anyway, but no way to figure out how SAGV logic is working.
> 
> If we need more debugs they need to added carefully so as to not totally
> blow up the logs. I think this here would spam the logs heavily.
> 
> > 
> > > 
> > > > +	} else {
> > > > +		/* Since all members are POD */
> > > > +		*sagv_wm = levels[0];
> > > > +	}
> > > > +}
> > > > +
> > > >  static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> > > >  				      const struct skl_wm_params *wp,
> > > >  				      struct skl_plane_wm *wm)
> > > > @@ -5296,6 +5381,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> > > >  		return ret;
> > > >  
> > > >  	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> > > > +	if (color_plane == 0)
> > > 
> > > We do want this for both the Y plane and UV plane.
> > > 
> > > > +		tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
> > > >  	skl_compute_transition_wm(crtc_state, &wm_params, wm);
> > > >  
> > > >  	return 0;
> > > > @@ -5702,6 +5789,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > >  				    enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
> > > >  				    enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
> > > >  
> > > > +			drm_dbg_kms(&dev_priv->drm,
> > > > +				    "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
> > > > +				    plane->base.base.id, plane->base.name,
> > > > +				    old_wm->sagv_wm0.plane_res_l,
> > > > +				    new_wm->sagv_wm0.plane_res_l);
> > > > +
> > > 
> > > IIRC I already suggested just slapping these onto the existing debug
> > > prints instead of bloating the debug output with extra lines.
> > > 
> > > Ie instead of 
> > > wms ... -> ...
> > > sagv wm ... -> ...
> > > 
> > > we just get
> > > wms ...,old_sagv_wm0 -> ...,new_sagv_wm0
> > > 
> > > just like we already do for eg. the transition wm.
> > 
> > Not sure about this one. I will check, I thought you suggested the opposite,
> > i.e do those debugs separately.
> > 
> > Stan
> > > 
> > > >  			drm_dbg_kms(&dev_priv->drm,
> > > >  				    "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > > >  				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > > > @@ -5717,6 +5810,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > >  				    new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
> > > >  				    new_wm->trans_wm.plane_res_b);
> > > >  
> > > > +			drm_dbg_kms(&dev_priv->drm,
> > > > +				    "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
> > > > +				    plane->base.base.id, plane->base.name,
> > > > +				    old_wm->sagv_wm0.plane_res_b,
> > > > +				    new_wm->sagv_wm0.plane_res_b);
> > > > +
> > > >  			drm_dbg_kms(&dev_priv->drm,
> > > >  				    "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> > > >  				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> > > > @@ -5731,6 +5830,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> > > >  				    new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
> > > >  				    new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
> > > >  				    new_wm->trans_wm.min_ddb_alloc);
> > > > +
> > > > +			drm_dbg_kms(&dev_priv->drm,
> > > > +				    "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
> > > > +				    plane->base.base.id, plane->base.name,
> > > > +				    old_wm->sagv_wm0.min_ddb_alloc,
> > > > +				    new_wm->sagv_wm0.min_ddb_alloc);
> > > >  		}
> > > >  	}
> > > >  }
> > > > @@ -6023,6 +6128,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > > >  			skl_wm_level_from_reg_val(val, &wm->wm[level]);
> > > >  		}
> > > >  
> > > > +		memcpy(&wm->sagv_wm0, &wm->wm[0],
> > > > +		       sizeof(struct skl_wm_level));
> > > 
> > > A simple assignment should suffice?
> > 
> > Agree.
> > 
> > > 
> > > > +
> > > >  		if (plane_id != PLANE_CURSOR)
> > > >  			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
> > > >  		else
> > > > -- 
> > > > 2.24.1.485.gad05a3d8e5
> > > 
> > > -- 
> > > Ville Syrjälä
> > > Intel
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH v28 3/6] drm/i915: Make active_pipes check skl specific

[Lisovskiy, Stanislav]

On Tue, May 12, 2020 at 04:14:33PM +0300, Ville Syrjälä wrote:
> On Tue, May 12, 2020 at 03:44:06PM +0300, Lisovskiy, Stanislav wrote:
> > On Tue, May 12, 2020 at 02:39:25PM +0300, Ville Syrjälä wrote:
> > > On Thu, May 07, 2020 at 05:45:00PM +0300, Stanislav Lisovskiy wrote:
> > > > Seems that only skl needs to have SAGV turned off
> > > > for multipipe scenarios, so lets do it this way.
> > > 
> > > It doesn't afaics. It's just someone added the check for some random
> > > reason. So this should be reworded a bit. Also this isn't just about
> > > skl/derivatives but all pre-icl so the <subject> is a bit misleading too.
> > 
> > This is in BSpec anyway. And it was in the code before, so I really 
> > don't get what do you mean here.
> > 
> > > 
> > > > 
> > > > If anything blows up - we can always revert this patch.
> > > > 
> > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++------
> > > >  drivers/gpu/drm/i915/intel_pm.h |  3 ++-
> > > >  2 files changed, 11 insertions(+), 7 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index 3dc1ad66beb3..db188efee21e 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -3777,7 +3777,7 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > > >  	if (!new_bw_state)
> > > >  		return;
> > > >  
> > > > -	if (!intel_can_enable_sagv(new_bw_state))
> > > > +	if (!intel_can_enable_sagv(dev_priv, new_bw_state))
> > > >  		intel_disable_sagv(dev_priv);
> > > >  }
> > > >  
> > > > @@ -3800,7 +3800,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> > > >  	if (!new_bw_state)
> > > >  		return;
> > > >  
> > > > -	if (intel_can_enable_sagv(new_bw_state))
> > > > +	if (intel_can_enable_sagv(dev_priv, new_bw_state))
> > > >  		intel_enable_sagv(dev_priv);
> > > >  }
> > > >  
> > > > @@ -3853,16 +3853,19 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > >  	return true;
> > > >  }
> > > >  
> > > > -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > > +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > > +			   const struct intel_bw_state *bw_state)
> > > >  {
> > > > -	if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > > -		return false;
> > > > +	if (INTEL_GEN(dev_priv) < 11)
> > > > +		if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > 
> > > If (a && b && c)
> > > 	return false;
> > 
> > Then the line would get too long, and it does exactly same thing.
> > I really don't understand such comments.
> 
> if (a && b &&
>     c)
> 
> if (a &&
>     b && c)
> 
> if (a &&
>     b &&
>     c)
> 
> there are plenty of options. The point is nested ifs like this
> only serve to indent code needlessly deep.

and ifs like if (long condition1 && long condition2 && ...) make 
unnecessary "wide". 

I would understand of course if I would do something like
3-4 nested ifs sure, however that one seems to be completely similar.

I don't even get why 

if (a &&
    b && c)

reads better than

if (a)
   if(b && c)

Stan

> 
> 
> > 
> > Stan
> > 
> > > 
> > > 
> > > > +			return false;
> > > >  
> > > >  	return bw_state->pipe_sagv_reject == 0;
> > > >  }
> > > >  
> > > >  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > >  {
> > > > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > >  	int ret;
> > > >  	struct intel_crtc *crtc;
> > > >  	const struct intel_crtc_state *new_crtc_state;
> > > > @@ -3896,7 +3899,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > >  			return ret;
> > > >  	}
> > > >  
> > > > -	if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> > > > +	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {
> > > 
> > > >  		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > > >  		if (ret)
> > > >  			return ret;
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> > > > index fd1dc422e6c5..614ac7f8d4cc 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.h
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > > > @@ -42,7 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > > >  			      struct skl_pipe_wm *out);
> > > >  void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > > >  void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> > > > -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> > > > +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > > +			   const struct intel_bw_state *bw_state);
> > > >  int intel_enable_sagv(struct drm_i915_private *dev_priv);
> > > >  int intel_disable_sagv(struct drm_i915_private *dev_priv);
> > > >  void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> > > > -- 
> > > > 2.24.1.485.gad05a3d8e5
> > > 
> > > -- 
> > > Ville Syrjälä
> > > Intel
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH v28 4/6] drm/i915: Add TGL+ SAGV support

[Ville Syrjälä]

On Tue, May 12, 2020 at 04:17:34PM +0300, Lisovskiy, Stanislav wrote:
> On Tue, May 12, 2020 at 04:10:46PM +0300, Ville Syrjälä wrote:
> > On Tue, May 12, 2020 at 03:52:27PM +0300, Lisovskiy, Stanislav wrote:
> > > On Tue, May 12, 2020 at 03:03:26PM +0300, Ville Syrjälä wrote:
> > > > On Thu, May 07, 2020 at 05:45:01PM +0300, Stanislav Lisovskiy wrote:
> > > > > Starting from TGL we need to have a separate wm0
> > > > > values for SAGV and non-SAGV which affects
> > > > > how calculations are done.
> > > > > 
> > > > > v2: Remove long lines
> > > > > v3: Removed COLOR_PLANE enum references
> > > > > v4, v5, v6: Fixed rebase conflict
> > > > > v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
> > > > >     - Removed sagv_uv_wm0(Ville)
> > > > >     - can_sagv->use_sagv_wm(Ville)
> > > > > 
> > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
> > > > >  .../drm/i915/display/intel_display_types.h    |   2 +
> > > > >  drivers/gpu/drm/i915/intel_pm.c               | 118 +++++++++++++++++-
> > > > >  3 files changed, 121 insertions(+), 7 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index fd6d63b03489..be5741cb7595 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > >  		/* Watermarks */
> > > > >  		for (level = 0; level <= max_level; level++) {
> > > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > -						&sw_plane_wm->wm[level]))
> > > > > +						&sw_plane_wm->wm[level]) ||
> > > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > +							       &sw_plane_wm->sagv_wm0)))
> > > > >  				continue;
> > > > >  
> > > > >  			drm_err(&dev_priv->drm,
> > > > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > >  		/* Watermarks */
> > > > >  		for (level = 0; level <= max_level; level++) {
> > > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > -						&sw_plane_wm->wm[level]))
> > > > > +						&sw_plane_wm->wm[level]) ||
> > > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > +							       &sw_plane_wm->sagv_wm0)))
> > > > >  				continue;
> > > > >  
> > > > >  			drm_err(&dev_priv->drm,
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > index 9488449e4b94..8cede29c9562 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > @@ -688,11 +688,13 @@ struct skl_plane_wm {
> > > > >  	struct skl_wm_level wm[8];
> > > > >  	struct skl_wm_level uv_wm[8];
> > > > >  	struct skl_wm_level trans_wm;
> > > > > +	struct skl_wm_level sagv_wm0;
> > > > >  	bool is_planar;
> > > > >  };
> > > > >  
> > > > >  struct skl_pipe_wm {
> > > > >  	struct skl_plane_wm planes[I915_MAX_PLANES];
> > > > > +	bool use_sagv_wm;
> > > > >  };
> > > > >  
> > > > >  enum vlv_wm_level {
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index db188efee21e..934a686342ad 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -3863,25 +3863,35 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > > >  	return bw_state->pipe_sagv_reject == 0;
> > > > >  }
> > > > >  
> > > > > +static bool
> > > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > > > 
> > > > Just put the function here instead of adding fwd decalrations.
> > > > 
> > > > > +
> > > > >  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > >  {
> > > > >  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > >  	int ret;
> > > > >  	struct intel_crtc *crtc;
> > > > > -	const struct intel_crtc_state *new_crtc_state;
> > > > > +	struct intel_crtc_state *new_crtc_state;
> > > > >  	struct intel_bw_state *new_bw_state = NULL;
> > > > >  	const struct intel_bw_state *old_bw_state = NULL;
> > > > >  	int i;
> > > > >  
> > > > >  	for_each_new_intel_crtc_in_state(state, crtc,
> > > > >  					 new_crtc_state, i) {
> > > > > +		bool can_sagv;
> > > > > +
> > > > >  		new_bw_state = intel_atomic_get_bw_state(state);
> > > > >  		if (IS_ERR(new_bw_state))
> > > > >  			return PTR_ERR(new_bw_state);
> > > > >  
> > > > >  		old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > >  
> > > > > -		if (skl_crtc_can_enable_sagv(new_crtc_state))
> > > > > +		if (INTEL_GEN(dev_priv) >= 12)
> > > > > +			can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > > > > +		else
> > > > > +			can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > > > +
> > > > > +		if (can_sagv)
> > > > >  			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > >  		else
> > > > >  			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > > @@ -3899,6 +3909,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > >  			return ret;
> > > > >  	}
> > > > >  
> > > > > +	for_each_new_intel_crtc_in_state(state, crtc,
> > > > > +					 new_crtc_state, i) {
> > > > > +		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > > > +
> > > > > +		/*
> > > > > +		 * Due to drm limitation at commit state, when
> > > > > +		 * changes are written the whole atomic state is
> > > > > +		 * zeroed away => which prevents from using it,
> > > > > +		 * so just sticking it into pipe wm state for
> > > > > +		 * keeping it simple - anyway this is related to wm.
> > > > > +		 * Proper way in ideal universe would be of course not
> > > > > +		 * to lose parent atomic state object from child crtc_state,
> > > > > +		 * and stick to OOP programming principles, which had been
> > > > > +		 * scientifically proven to work.
> > > > > +		 */
> > > > 
> > > > More ramblings. Just drop this comment too imo.
> > > 
> > > As I understand what is happening here is rather weird, so I thought 
> > > commenting is good idea.
> > 
> > At least I have no idea what the comment is trying to say.
> > I see nothing weird hapening here, we're just computing the
> > state which is totally standard stuff.
> 
> Well I can remind, this is because there is no way to get parent state
> from crtc_state, because of weird drm atomic behaviour which leaves us
> with NULL parent state. So that we had to stick this boolean to some
> place.
> In normal code universe this wouldn't even be needed if we could
> just get atomic state from crtc_state when we write wm in skl_write_plane_wm.

Didn't get that at all from the comment. It talked about zeroing some
whole state which I took as 'memset(state, 0, sizeof(*state))'.
As that is not what's going on I just got confused by the comment.

Now that I understand what this is about I think the comment
(if we want to have one) should probably say something more like:
"we store use_sagv_wm in the crtc state rather than relying on
 the bw state since we have no convenient way to get at the
 latter from the plane commit hooks (especially in the legacy
 cursor case)".

> 
> However probably OOP principles like parent-child hieararchy is not a thing
> here. That what this comment was trying to say.
> 
> In normal OOP you can't destroy parent object _before_ destroying
> child one.

There's no parent-child relationship between the crtc state and atomic
state (which really shouldn't be called a state to begin with, rather
it should be "transaction" or something along those lines).

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v28 4/6] drm/i915: Add TGL+ SAGV support

[Lisovskiy, Stanislav]

On Tue, May 12, 2020 at 04:38:21PM +0300, Ville Syrjälä wrote:
> On Tue, May 12, 2020 at 04:17:34PM +0300, Lisovskiy, Stanislav wrote:
> > On Tue, May 12, 2020 at 04:10:46PM +0300, Ville Syrjälä wrote:
> > > On Tue, May 12, 2020 at 03:52:27PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Tue, May 12, 2020 at 03:03:26PM +0300, Ville Syrjälä wrote:
> > > > > On Thu, May 07, 2020 at 05:45:01PM +0300, Stanislav Lisovskiy wrote:
> > > > > > Starting from TGL we need to have a separate wm0
> > > > > > values for SAGV and non-SAGV which affects
> > > > > > how calculations are done.
> > > > > > 
> > > > > > v2: Remove long lines
> > > > > > v3: Removed COLOR_PLANE enum references
> > > > > > v4, v5, v6: Fixed rebase conflict
> > > > > > v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
> > > > > >     - Removed sagv_uv_wm0(Ville)
> > > > > >     - can_sagv->use_sagv_wm(Ville)
> > > > > > 
> > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
> > > > > >  .../drm/i915/display/intel_display_types.h    |   2 +
> > > > > >  drivers/gpu/drm/i915/intel_pm.c               | 118 +++++++++++++++++-
> > > > > >  3 files changed, 121 insertions(+), 7 deletions(-)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > index fd6d63b03489..be5741cb7595 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > >  		/* Watermarks */
> > > > > >  		for (level = 0; level <= max_level; level++) {
> > > > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > -						&sw_plane_wm->wm[level]))
> > > > > > +						&sw_plane_wm->wm[level]) ||
> > > > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > +							       &sw_plane_wm->sagv_wm0)))
> > > > > >  				continue;
> > > > > >  
> > > > > >  			drm_err(&dev_priv->drm,
> > > > > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > >  		/* Watermarks */
> > > > > >  		for (level = 0; level <= max_level; level++) {
> > > > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > -						&sw_plane_wm->wm[level]))
> > > > > > +						&sw_plane_wm->wm[level]) ||
> > > > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > +							       &sw_plane_wm->sagv_wm0)))
> > > > > >  				continue;
> > > > > >  
> > > > > >  			drm_err(&dev_priv->drm,
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > index 9488449e4b94..8cede29c9562 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > @@ -688,11 +688,13 @@ struct skl_plane_wm {
> > > > > >  	struct skl_wm_level wm[8];
> > > > > >  	struct skl_wm_level uv_wm[8];
> > > > > >  	struct skl_wm_level trans_wm;
> > > > > > +	struct skl_wm_level sagv_wm0;
> > > > > >  	bool is_planar;
> > > > > >  };
> > > > > >  
> > > > > >  struct skl_pipe_wm {
> > > > > >  	struct skl_plane_wm planes[I915_MAX_PLANES];
> > > > > > +	bool use_sagv_wm;
> > > > > >  };
> > > > > >  
> > > > > >  enum vlv_wm_level {
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > index db188efee21e..934a686342ad 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > @@ -3863,25 +3863,35 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > > > >  	return bw_state->pipe_sagv_reject == 0;
> > > > > >  }
> > > > > >  
> > > > > > +static bool
> > > > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > > > > 
> > > > > Just put the function here instead of adding fwd decalrations.
> > > > > 
> > > > > > +
> > > > > >  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > >  {
> > > > > >  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > >  	int ret;
> > > > > >  	struct intel_crtc *crtc;
> > > > > > -	const struct intel_crtc_state *new_crtc_state;
> > > > > > +	struct intel_crtc_state *new_crtc_state;
> > > > > >  	struct intel_bw_state *new_bw_state = NULL;
> > > > > >  	const struct intel_bw_state *old_bw_state = NULL;
> > > > > >  	int i;
> > > > > >  
> > > > > >  	for_each_new_intel_crtc_in_state(state, crtc,
> > > > > >  					 new_crtc_state, i) {
> > > > > > +		bool can_sagv;
> > > > > > +
> > > > > >  		new_bw_state = intel_atomic_get_bw_state(state);
> > > > > >  		if (IS_ERR(new_bw_state))
> > > > > >  			return PTR_ERR(new_bw_state);
> > > > > >  
> > > > > >  		old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > > >  
> > > > > > -		if (skl_crtc_can_enable_sagv(new_crtc_state))
> > > > > > +		if (INTEL_GEN(dev_priv) >= 12)
> > > > > > +			can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > +		else
> > > > > > +			can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > +
> > > > > > +		if (can_sagv)
> > > > > >  			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > >  		else
> > > > > >  			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > > > @@ -3899,6 +3909,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > >  			return ret;
> > > > > >  	}
> > > > > >  
> > > > > > +	for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > +					 new_crtc_state, i) {
> > > > > > +		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > > > > +
> > > > > > +		/*
> > > > > > +		 * Due to drm limitation at commit state, when
> > > > > > +		 * changes are written the whole atomic state is
> > > > > > +		 * zeroed away => which prevents from using it,
> > > > > > +		 * so just sticking it into pipe wm state for
> > > > > > +		 * keeping it simple - anyway this is related to wm.
> > > > > > +		 * Proper way in ideal universe would be of course not
> > > > > > +		 * to lose parent atomic state object from child crtc_state,
> > > > > > +		 * and stick to OOP programming principles, which had been
> > > > > > +		 * scientifically proven to work.
> > > > > > +		 */
> > > > > 
> > > > > More ramblings. Just drop this comment too imo.
> > > > 
> > > > As I understand what is happening here is rather weird, so I thought 
> > > > commenting is good idea.
> > > 
> > > At least I have no idea what the comment is trying to say.
> > > I see nothing weird hapening here, we're just computing the
> > > state which is totally standard stuff.
> > 
> > Well I can remind, this is because there is no way to get parent state
> > from crtc_state, because of weird drm atomic behaviour which leaves us
> > with NULL parent state. So that we had to stick this boolean to some
> > place.
> > In normal code universe this wouldn't even be needed if we could
> > just get atomic state from crtc_state when we write wm in skl_write_plane_wm.
> 
> Didn't get that at all from the comment. It talked about zeroing some
> whole state which I took as 'memset(state, 0, sizeof(*state))'.
> As that is not what's going on I just got confused by the comment.
> 
> Now that I understand what this is about I think the comment
> (if we want to have one) should probably say something more like:
> "we store use_sagv_wm in the crtc state rather than relying on
>  the bw state since we have no convenient way to get at the
>  latter from the plane commit hooks (especially in the legacy
>  cursor case)".
> 
> > 
> > However probably OOP principles like parent-child hieararchy is not a thing
> > here. That what this comment was trying to say.
> > 
> > In normal OOP you can't destroy parent object _before_ destroying
> > child one.
> 
> There's no parent-child relationship between the crtc state and atomic
> state (which really shouldn't be called a state to begin with, rather
> it should be "transaction" or something along those lines).

In practice there is. crtc_state is being aggregated and contained as 
part of more general atomic state. That is exactly what parent-child
object relation is.
If you want to decouple those, this needs to be not aggregation but a reference,
i.e atomic state would not contain those state objects, but have a pointer
instead, but then you would not be using that container_of magic.

Stan

> 
> -- 
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH v28 4/6] drm/i915: Add TGL+ SAGV support

[Ville Syrjälä]

On Tue, May 12, 2020 at 04:41:26PM +0300, Lisovskiy, Stanislav wrote:
> On Tue, May 12, 2020 at 04:38:21PM +0300, Ville Syrjälä wrote:
> > On Tue, May 12, 2020 at 04:17:34PM +0300, Lisovskiy, Stanislav wrote:
> > > On Tue, May 12, 2020 at 04:10:46PM +0300, Ville Syrjälä wrote:
> > > > On Tue, May 12, 2020 at 03:52:27PM +0300, Lisovskiy, Stanislav wrote:
> > > > > On Tue, May 12, 2020 at 03:03:26PM +0300, Ville Syrjälä wrote:
> > > > > > On Thu, May 07, 2020 at 05:45:01PM +0300, Stanislav Lisovskiy wrote:
> > > > > > > Starting from TGL we need to have a separate wm0
> > > > > > > values for SAGV and non-SAGV which affects
> > > > > > > how calculations are done.
> > > > > > > 
> > > > > > > v2: Remove long lines
> > > > > > > v3: Removed COLOR_PLANE enum references
> > > > > > > v4, v5, v6: Fixed rebase conflict
> > > > > > > v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
> > > > > > >     - Removed sagv_uv_wm0(Ville)
> > > > > > >     - can_sagv->use_sagv_wm(Ville)
> > > > > > > 
> > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > > ---
> > > > > > >  drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
> > > > > > >  .../drm/i915/display/intel_display_types.h    |   2 +
> > > > > > >  drivers/gpu/drm/i915/intel_pm.c               | 118 +++++++++++++++++-
> > > > > > >  3 files changed, 121 insertions(+), 7 deletions(-)
> > > > > > > 
> > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > index fd6d63b03489..be5741cb7595 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > > >  		/* Watermarks */
> > > > > > >  		for (level = 0; level <= max_level; level++) {
> > > > > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > -						&sw_plane_wm->wm[level]))
> > > > > > > +						&sw_plane_wm->wm[level]) ||
> > > > > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > +							       &sw_plane_wm->sagv_wm0)))
> > > > > > >  				continue;
> > > > > > >  
> > > > > > >  			drm_err(&dev_priv->drm,
> > > > > > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > > >  		/* Watermarks */
> > > > > > >  		for (level = 0; level <= max_level; level++) {
> > > > > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > -						&sw_plane_wm->wm[level]))
> > > > > > > +						&sw_plane_wm->wm[level]) ||
> > > > > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > +							       &sw_plane_wm->sagv_wm0)))
> > > > > > >  				continue;
> > > > > > >  
> > > > > > >  			drm_err(&dev_priv->drm,
> > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > index 9488449e4b94..8cede29c9562 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > @@ -688,11 +688,13 @@ struct skl_plane_wm {
> > > > > > >  	struct skl_wm_level wm[8];
> > > > > > >  	struct skl_wm_level uv_wm[8];
> > > > > > >  	struct skl_wm_level trans_wm;
> > > > > > > +	struct skl_wm_level sagv_wm0;
> > > > > > >  	bool is_planar;
> > > > > > >  };
> > > > > > >  
> > > > > > >  struct skl_pipe_wm {
> > > > > > >  	struct skl_plane_wm planes[I915_MAX_PLANES];
> > > > > > > +	bool use_sagv_wm;
> > > > > > >  };
> > > > > > >  
> > > > > > >  enum vlv_wm_level {
> > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > index db188efee21e..934a686342ad 100644
> > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > @@ -3863,25 +3863,35 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > > > > >  	return bw_state->pipe_sagv_reject == 0;
> > > > > > >  }
> > > > > > >  
> > > > > > > +static bool
> > > > > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > > > > > 
> > > > > > Just put the function here instead of adding fwd decalrations.
> > > > > > 
> > > > > > > +
> > > > > > >  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > >  {
> > > > > > >  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > > >  	int ret;
> > > > > > >  	struct intel_crtc *crtc;
> > > > > > > -	const struct intel_crtc_state *new_crtc_state;
> > > > > > > +	struct intel_crtc_state *new_crtc_state;
> > > > > > >  	struct intel_bw_state *new_bw_state = NULL;
> > > > > > >  	const struct intel_bw_state *old_bw_state = NULL;
> > > > > > >  	int i;
> > > > > > >  
> > > > > > >  	for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > >  					 new_crtc_state, i) {
> > > > > > > +		bool can_sagv;
> > > > > > > +
> > > > > > >  		new_bw_state = intel_atomic_get_bw_state(state);
> > > > > > >  		if (IS_ERR(new_bw_state))
> > > > > > >  			return PTR_ERR(new_bw_state);
> > > > > > >  
> > > > > > >  		old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > > > >  
> > > > > > > -		if (skl_crtc_can_enable_sagv(new_crtc_state))
> > > > > > > +		if (INTEL_GEN(dev_priv) >= 12)
> > > > > > > +			can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > > +		else
> > > > > > > +			can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > > +
> > > > > > > +		if (can_sagv)
> > > > > > >  			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > > >  		else
> > > > > > >  			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > > > > @@ -3899,6 +3909,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > >  			return ret;
> > > > > > >  	}
> > > > > > >  
> > > > > > > +	for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > > +					 new_crtc_state, i) {
> > > > > > > +		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > > > > > +
> > > > > > > +		/*
> > > > > > > +		 * Due to drm limitation at commit state, when
> > > > > > > +		 * changes are written the whole atomic state is
> > > > > > > +		 * zeroed away => which prevents from using it,
> > > > > > > +		 * so just sticking it into pipe wm state for
> > > > > > > +		 * keeping it simple - anyway this is related to wm.
> > > > > > > +		 * Proper way in ideal universe would be of course not
> > > > > > > +		 * to lose parent atomic state object from child crtc_state,
> > > > > > > +		 * and stick to OOP programming principles, which had been
> > > > > > > +		 * scientifically proven to work.
> > > > > > > +		 */
> > > > > > 
> > > > > > More ramblings. Just drop this comment too imo.
> > > > > 
> > > > > As I understand what is happening here is rather weird, so I thought 
> > > > > commenting is good idea.
> > > > 
> > > > At least I have no idea what the comment is trying to say.
> > > > I see nothing weird hapening here, we're just computing the
> > > > state which is totally standard stuff.
> > > 
> > > Well I can remind, this is because there is no way to get parent state
> > > from crtc_state, because of weird drm atomic behaviour which leaves us
> > > with NULL parent state. So that we had to stick this boolean to some
> > > place.
> > > In normal code universe this wouldn't even be needed if we could
> > > just get atomic state from crtc_state when we write wm in skl_write_plane_wm.
> > 
> > Didn't get that at all from the comment. It talked about zeroing some
> > whole state which I took as 'memset(state, 0, sizeof(*state))'.
> > As that is not what's going on I just got confused by the comment.
> > 
> > Now that I understand what this is about I think the comment
> > (if we want to have one) should probably say something more like:
> > "we store use_sagv_wm in the crtc state rather than relying on
> >  the bw state since we have no convenient way to get at the
> >  latter from the plane commit hooks (especially in the legacy
> >  cursor case)".
> > 
> > > 
> > > However probably OOP principles like parent-child hieararchy is not a thing
> > > here. That what this comment was trying to say.
> > > 
> > > In normal OOP you can't destroy parent object _before_ destroying
> > > child one.
> > 
> > There's no parent-child relationship between the crtc state and atomic
> > state (which really shouldn't be called a state to begin with, rather
> > it should be "transaction" or something along those lines).
> 
> In practice there is. crtc_state is being aggregated and contained as 
> part of more general atomic state. That is exactly what parent-child
> object relation is.
> If you want to decouple those, this needs to be not aggregation but a reference,
> i.e atomic state would not contain those state objects, but have a pointer
> instead, but then you would not be using that container_of magic.

Pointers is what it has. And once the atomic commit is done the 
atomic_state (ie. the object used to track the single transaction)
goes away while the crtc/plane/etc. states remain behind.

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v28 4/6] drm/i915: Add TGL+ SAGV support

[Lisovskiy, Stanislav]

On Tue, May 12, 2020 at 04:50:46PM +0300, Ville Syrjälä wrote:
> On Tue, May 12, 2020 at 04:41:26PM +0300, Lisovskiy, Stanislav wrote:
> > On Tue, May 12, 2020 at 04:38:21PM +0300, Ville Syrjälä wrote:
> > > On Tue, May 12, 2020 at 04:17:34PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Tue, May 12, 2020 at 04:10:46PM +0300, Ville Syrjälä wrote:
> > > > > On Tue, May 12, 2020 at 03:52:27PM +0300, Lisovskiy, Stanislav wrote:
> > > > > > On Tue, May 12, 2020 at 03:03:26PM +0300, Ville Syrjälä wrote:
> > > > > > > On Thu, May 07, 2020 at 05:45:01PM +0300, Stanislav Lisovskiy wrote:
> > > > > > > > Starting from TGL we need to have a separate wm0
> > > > > > > > values for SAGV and non-SAGV which affects
> > > > > > > > how calculations are done.
> > > > > > > > 
> > > > > > > > v2: Remove long lines
> > > > > > > > v3: Removed COLOR_PLANE enum references
> > > > > > > > v4, v5, v6: Fixed rebase conflict
> > > > > > > > v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
> > > > > > > >     - Removed sagv_uv_wm0(Ville)
> > > > > > > >     - can_sagv->use_sagv_wm(Ville)
> > > > > > > > 
> > > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > > > ---
> > > > > > > >  drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
> > > > > > > >  .../drm/i915/display/intel_display_types.h    |   2 +
> > > > > > > >  drivers/gpu/drm/i915/intel_pm.c               | 118 +++++++++++++++++-
> > > > > > > >  3 files changed, 121 insertions(+), 7 deletions(-)
> > > > > > > > 
> > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > > index fd6d63b03489..be5741cb7595 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > > > >  		/* Watermarks */
> > > > > > > >  		for (level = 0; level <= max_level; level++) {
> > > > > > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > -						&sw_plane_wm->wm[level]))
> > > > > > > > +						&sw_plane_wm->wm[level]) ||
> > > > > > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > +							       &sw_plane_wm->sagv_wm0)))
> > > > > > > >  				continue;
> > > > > > > >  
> > > > > > > >  			drm_err(&dev_priv->drm,
> > > > > > > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > > > >  		/* Watermarks */
> > > > > > > >  		for (level = 0; level <= max_level; level++) {
> > > > > > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > -						&sw_plane_wm->wm[level]))
> > > > > > > > +						&sw_plane_wm->wm[level]) ||
> > > > > > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > +							       &sw_plane_wm->sagv_wm0)))
> > > > > > > >  				continue;
> > > > > > > >  
> > > > > > > >  			drm_err(&dev_priv->drm,
> > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > > index 9488449e4b94..8cede29c9562 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > > @@ -688,11 +688,13 @@ struct skl_plane_wm {
> > > > > > > >  	struct skl_wm_level wm[8];
> > > > > > > >  	struct skl_wm_level uv_wm[8];
> > > > > > > >  	struct skl_wm_level trans_wm;
> > > > > > > > +	struct skl_wm_level sagv_wm0;
> > > > > > > >  	bool is_planar;
> > > > > > > >  };
> > > > > > > >  
> > > > > > > >  struct skl_pipe_wm {
> > > > > > > >  	struct skl_plane_wm planes[I915_MAX_PLANES];
> > > > > > > > +	bool use_sagv_wm;
> > > > > > > >  };
> > > > > > > >  
> > > > > > > >  enum vlv_wm_level {
> > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > index db188efee21e..934a686342ad 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > @@ -3863,25 +3863,35 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > > > > > >  	return bw_state->pipe_sagv_reject == 0;
> > > > > > > >  }
> > > > > > > >  
> > > > > > > > +static bool
> > > > > > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > > > > > > 
> > > > > > > Just put the function here instead of adding fwd decalrations.
> > > > > > > 
> > > > > > > > +
> > > > > > > >  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > >  {
> > > > > > > >  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > > > >  	int ret;
> > > > > > > >  	struct intel_crtc *crtc;
> > > > > > > > -	const struct intel_crtc_state *new_crtc_state;
> > > > > > > > +	struct intel_crtc_state *new_crtc_state;
> > > > > > > >  	struct intel_bw_state *new_bw_state = NULL;
> > > > > > > >  	const struct intel_bw_state *old_bw_state = NULL;
> > > > > > > >  	int i;
> > > > > > > >  
> > > > > > > >  	for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > > >  					 new_crtc_state, i) {
> > > > > > > > +		bool can_sagv;
> > > > > > > > +
> > > > > > > >  		new_bw_state = intel_atomic_get_bw_state(state);
> > > > > > > >  		if (IS_ERR(new_bw_state))
> > > > > > > >  			return PTR_ERR(new_bw_state);
> > > > > > > >  
> > > > > > > >  		old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > > > > >  
> > > > > > > > -		if (skl_crtc_can_enable_sagv(new_crtc_state))
> > > > > > > > +		if (INTEL_GEN(dev_priv) >= 12)
> > > > > > > > +			can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > > > +		else
> > > > > > > > +			can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > > > +
> > > > > > > > +		if (can_sagv)
> > > > > > > >  			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > > > >  		else
> > > > > > > >  			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > > > > > @@ -3899,6 +3909,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > >  			return ret;
> > > > > > > >  	}
> > > > > > > >  
> > > > > > > > +	for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > > > +					 new_crtc_state, i) {
> > > > > > > > +		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > > > > > > +
> > > > > > > > +		/*
> > > > > > > > +		 * Due to drm limitation at commit state, when
> > > > > > > > +		 * changes are written the whole atomic state is
> > > > > > > > +		 * zeroed away => which prevents from using it,
> > > > > > > > +		 * so just sticking it into pipe wm state for
> > > > > > > > +		 * keeping it simple - anyway this is related to wm.
> > > > > > > > +		 * Proper way in ideal universe would be of course not
> > > > > > > > +		 * to lose parent atomic state object from child crtc_state,
> > > > > > > > +		 * and stick to OOP programming principles, which had been
> > > > > > > > +		 * scientifically proven to work.
> > > > > > > > +		 */
> > > > > > > 
> > > > > > > More ramblings. Just drop this comment too imo.
> > > > > > 
> > > > > > As I understand what is happening here is rather weird, so I thought 
> > > > > > commenting is good idea.
> > > > > 
> > > > > At least I have no idea what the comment is trying to say.
> > > > > I see nothing weird hapening here, we're just computing the
> > > > > state which is totally standard stuff.
> > > > 
> > > > Well I can remind, this is because there is no way to get parent state
> > > > from crtc_state, because of weird drm atomic behaviour which leaves us
> > > > with NULL parent state. So that we had to stick this boolean to some
> > > > place.
> > > > In normal code universe this wouldn't even be needed if we could
> > > > just get atomic state from crtc_state when we write wm in skl_write_plane_wm.
> > > 
> > > Didn't get that at all from the comment. It talked about zeroing some
> > > whole state which I took as 'memset(state, 0, sizeof(*state))'.
> > > As that is not what's going on I just got confused by the comment.
> > > 
> > > Now that I understand what this is about I think the comment
> > > (if we want to have one) should probably say something more like:
> > > "we store use_sagv_wm in the crtc state rather than relying on
> > >  the bw state since we have no convenient way to get at the
> > >  latter from the plane commit hooks (especially in the legacy
> > >  cursor case)".
> > > 
> > > > 
> > > > However probably OOP principles like parent-child hieararchy is not a thing
> > > > here. That what this comment was trying to say.
> > > > 
> > > > In normal OOP you can't destroy parent object _before_ destroying
> > > > child one.
> > > 
> > > There's no parent-child relationship between the crtc state and atomic
> > > state (which really shouldn't be called a state to begin with, rather
> > > it should be "transaction" or something along those lines).
> > 
> > In practice there is. crtc_state is being aggregated and contained as 
> > part of more general atomic state. That is exactly what parent-child
> > object relation is.
> > If you want to decouple those, this needs to be not aggregation but a reference,
> > i.e atomic state would not contain those state objects, but have a pointer
> > instead, but then you would not be using that container_of magic.
> 
> Pointers is what it has. And once the atomic commit is done the 
> atomic_state (ie. the object used to track the single transaction)
> goes away while the crtc/plane/etc. states remain behind.

If the rest of states are independent there should be sane way
to get those without the atomic state. 

Currently bw_state, cdclk_state and co - all can be retrieved only
using atomic state, which is at some point "gone". 
Also it is actually not even gone, we just zero out a pointer
to it in drm_crtc_state. 

I know why this done as we discussed, however I would 
emphasize that the proper way would be then
to completely decouple from it, so that all required states can
be retrieved without atomic state. Because currently we are
kind of in some "fuzzy" state in between.

Stan

> 
> -- 
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH v28 4/6] drm/i915: Add TGL+ SAGV support

[Ville Syrjälä]

On Tue, May 12, 2020 at 04:59:19PM +0300, Lisovskiy, Stanislav wrote:
> On Tue, May 12, 2020 at 04:50:46PM +0300, Ville Syrjälä wrote:
> > On Tue, May 12, 2020 at 04:41:26PM +0300, Lisovskiy, Stanislav wrote:
> > > On Tue, May 12, 2020 at 04:38:21PM +0300, Ville Syrjälä wrote:
> > > > On Tue, May 12, 2020 at 04:17:34PM +0300, Lisovskiy, Stanislav wrote:
> > > > > On Tue, May 12, 2020 at 04:10:46PM +0300, Ville Syrjälä wrote:
> > > > > > On Tue, May 12, 2020 at 03:52:27PM +0300, Lisovskiy, Stanislav wrote:
> > > > > > > On Tue, May 12, 2020 at 03:03:26PM +0300, Ville Syrjälä wrote:
> > > > > > > > On Thu, May 07, 2020 at 05:45:01PM +0300, Stanislav Lisovskiy wrote:
> > > > > > > > > Starting from TGL we need to have a separate wm0
> > > > > > > > > values for SAGV and non-SAGV which affects
> > > > > > > > > how calculations are done.
> > > > > > > > > 
> > > > > > > > > v2: Remove long lines
> > > > > > > > > v3: Removed COLOR_PLANE enum references
> > > > > > > > > v4, v5, v6: Fixed rebase conflict
> > > > > > > > > v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
> > > > > > > > >     - Removed sagv_uv_wm0(Ville)
> > > > > > > > >     - can_sagv->use_sagv_wm(Ville)
> > > > > > > > > 
> > > > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > > > > ---
> > > > > > > > >  drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
> > > > > > > > >  .../drm/i915/display/intel_display_types.h    |   2 +
> > > > > > > > >  drivers/gpu/drm/i915/intel_pm.c               | 118 +++++++++++++++++-
> > > > > > > > >  3 files changed, 121 insertions(+), 7 deletions(-)
> > > > > > > > > 
> > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > > > index fd6d63b03489..be5741cb7595 100644
> > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > > > > >  		/* Watermarks */
> > > > > > > > >  		for (level = 0; level <= max_level; level++) {
> > > > > > > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > > -						&sw_plane_wm->wm[level]))
> > > > > > > > > +						&sw_plane_wm->wm[level]) ||
> > > > > > > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > > +							       &sw_plane_wm->sagv_wm0)))
> > > > > > > > >  				continue;
> > > > > > > > >  
> > > > > > > > >  			drm_err(&dev_priv->drm,
> > > > > > > > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > > > > >  		/* Watermarks */
> > > > > > > > >  		for (level = 0; level <= max_level; level++) {
> > > > > > > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > > -						&sw_plane_wm->wm[level]))
> > > > > > > > > +						&sw_plane_wm->wm[level]) ||
> > > > > > > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > > +							       &sw_plane_wm->sagv_wm0)))
> > > > > > > > >  				continue;
> > > > > > > > >  
> > > > > > > > >  			drm_err(&dev_priv->drm,
> > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > > > index 9488449e4b94..8cede29c9562 100644
> > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > > > @@ -688,11 +688,13 @@ struct skl_plane_wm {
> > > > > > > > >  	struct skl_wm_level wm[8];
> > > > > > > > >  	struct skl_wm_level uv_wm[8];
> > > > > > > > >  	struct skl_wm_level trans_wm;
> > > > > > > > > +	struct skl_wm_level sagv_wm0;
> > > > > > > > >  	bool is_planar;
> > > > > > > > >  };
> > > > > > > > >  
> > > > > > > > >  struct skl_pipe_wm {
> > > > > > > > >  	struct skl_plane_wm planes[I915_MAX_PLANES];
> > > > > > > > > +	bool use_sagv_wm;
> > > > > > > > >  };
> > > > > > > > >  
> > > > > > > > >  enum vlv_wm_level {
> > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > index db188efee21e..934a686342ad 100644
> > > > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > @@ -3863,25 +3863,35 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > > > > > > >  	return bw_state->pipe_sagv_reject == 0;
> > > > > > > > >  }
> > > > > > > > >  
> > > > > > > > > +static bool
> > > > > > > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > > > > > > > 
> > > > > > > > Just put the function here instead of adding fwd decalrations.
> > > > > > > > 
> > > > > > > > > +
> > > > > > > > >  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > > >  {
> > > > > > > > >  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > > > > >  	int ret;
> > > > > > > > >  	struct intel_crtc *crtc;
> > > > > > > > > -	const struct intel_crtc_state *new_crtc_state;
> > > > > > > > > +	struct intel_crtc_state *new_crtc_state;
> > > > > > > > >  	struct intel_bw_state *new_bw_state = NULL;
> > > > > > > > >  	const struct intel_bw_state *old_bw_state = NULL;
> > > > > > > > >  	int i;
> > > > > > > > >  
> > > > > > > > >  	for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > > > >  					 new_crtc_state, i) {
> > > > > > > > > +		bool can_sagv;
> > > > > > > > > +
> > > > > > > > >  		new_bw_state = intel_atomic_get_bw_state(state);
> > > > > > > > >  		if (IS_ERR(new_bw_state))
> > > > > > > > >  			return PTR_ERR(new_bw_state);
> > > > > > > > >  
> > > > > > > > >  		old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > > > > > >  
> > > > > > > > > -		if (skl_crtc_can_enable_sagv(new_crtc_state))
> > > > > > > > > +		if (INTEL_GEN(dev_priv) >= 12)
> > > > > > > > > +			can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > > > > +		else
> > > > > > > > > +			can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > > > > +
> > > > > > > > > +		if (can_sagv)
> > > > > > > > >  			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > > > > >  		else
> > > > > > > > >  			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > > > > > > @@ -3899,6 +3909,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > > >  			return ret;
> > > > > > > > >  	}
> > > > > > > > >  
> > > > > > > > > +	for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > > > > +					 new_crtc_state, i) {
> > > > > > > > > +		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > > > > > > > +
> > > > > > > > > +		/*
> > > > > > > > > +		 * Due to drm limitation at commit state, when
> > > > > > > > > +		 * changes are written the whole atomic state is
> > > > > > > > > +		 * zeroed away => which prevents from using it,
> > > > > > > > > +		 * so just sticking it into pipe wm state for
> > > > > > > > > +		 * keeping it simple - anyway this is related to wm.
> > > > > > > > > +		 * Proper way in ideal universe would be of course not
> > > > > > > > > +		 * to lose parent atomic state object from child crtc_state,
> > > > > > > > > +		 * and stick to OOP programming principles, which had been
> > > > > > > > > +		 * scientifically proven to work.
> > > > > > > > > +		 */
> > > > > > > > 
> > > > > > > > More ramblings. Just drop this comment too imo.
> > > > > > > 
> > > > > > > As I understand what is happening here is rather weird, so I thought 
> > > > > > > commenting is good idea.
> > > > > > 
> > > > > > At least I have no idea what the comment is trying to say.
> > > > > > I see nothing weird hapening here, we're just computing the
> > > > > > state which is totally standard stuff.
> > > > > 
> > > > > Well I can remind, this is because there is no way to get parent state
> > > > > from crtc_state, because of weird drm atomic behaviour which leaves us
> > > > > with NULL parent state. So that we had to stick this boolean to some
> > > > > place.
> > > > > In normal code universe this wouldn't even be needed if we could
> > > > > just get atomic state from crtc_state when we write wm in skl_write_plane_wm.
> > > > 
> > > > Didn't get that at all from the comment. It talked about zeroing some
> > > > whole state which I took as 'memset(state, 0, sizeof(*state))'.
> > > > As that is not what's going on I just got confused by the comment.
> > > > 
> > > > Now that I understand what this is about I think the comment
> > > > (if we want to have one) should probably say something more like:
> > > > "we store use_sagv_wm in the crtc state rather than relying on
> > > >  the bw state since we have no convenient way to get at the
> > > >  latter from the plane commit hooks (especially in the legacy
> > > >  cursor case)".
> > > > 
> > > > > 
> > > > > However probably OOP principles like parent-child hieararchy is not a thing
> > > > > here. That what this comment was trying to say.
> > > > > 
> > > > > In normal OOP you can't destroy parent object _before_ destroying
> > > > > child one.
> > > > 
> > > > There's no parent-child relationship between the crtc state and atomic
> > > > state (which really shouldn't be called a state to begin with, rather
> > > > it should be "transaction" or something along those lines).
> > > 
> > > In practice there is. crtc_state is being aggregated and contained as 
> > > part of more general atomic state. That is exactly what parent-child
> > > object relation is.
> > > If you want to decouple those, this needs to be not aggregation but a reference,
> > > i.e atomic state would not contain those state objects, but have a pointer
> > > instead, but then you would not be using that container_of magic.
> > 
> > Pointers is what it has. And once the atomic commit is done the 
> > atomic_state (ie. the object used to track the single transaction)
> > goes away while the crtc/plane/etc. states remain behind.
> 
> If the rest of states are independent there should be sane way
> to get those without the atomic state. 

How could you possibly get the right one without specifying
which transaction you want them for?

> 
> Currently bw_state, cdclk_state and co - all can be retrieved only
> using atomic state, which is at some point "gone". 
> Also it is actually not even gone, we just zero out a pointer
> to it in drm_crtc_state. 
> 
> I know why this done as we discussed, however I would 
> emphasize that the proper way would be then
> to completely decouple from it, so that all required states can
> be retrieved without atomic state. Because currently we are
> kind of in some "fuzzy" state in between.
> 
> Stan
> 
> > 
> > -- 
> > Ville Syrjälä
> > Intel

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v28 4/6] drm/i915: Add TGL+ SAGV support

[Lisovskiy, Stanislav]

On Tue, May 12, 2020 at 05:32:21PM +0300, Ville Syrjälä wrote:
> On Tue, May 12, 2020 at 04:59:19PM +0300, Lisovskiy, Stanislav wrote:
> > On Tue, May 12, 2020 at 04:50:46PM +0300, Ville Syrjälä wrote:
> > > On Tue, May 12, 2020 at 04:41:26PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Tue, May 12, 2020 at 04:38:21PM +0300, Ville Syrjälä wrote:
> > > > > On Tue, May 12, 2020 at 04:17:34PM +0300, Lisovskiy, Stanislav wrote:
> > > > > > On Tue, May 12, 2020 at 04:10:46PM +0300, Ville Syrjälä wrote:
> > > > > > > On Tue, May 12, 2020 at 03:52:27PM +0300, Lisovskiy, Stanislav wrote:
> > > > > > > > On Tue, May 12, 2020 at 03:03:26PM +0300, Ville Syrjälä wrote:
> > > > > > > > > On Thu, May 07, 2020 at 05:45:01PM +0300, Stanislav Lisovskiy wrote:
> > > > > > > > > > Starting from TGL we need to have a separate wm0
> > > > > > > > > > values for SAGV and non-SAGV which affects
> > > > > > > > > > how calculations are done.
> > > > > > > > > > 
> > > > > > > > > > v2: Remove long lines
> > > > > > > > > > v3: Removed COLOR_PLANE enum references
> > > > > > > > > > v4, v5, v6: Fixed rebase conflict
> > > > > > > > > > v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
> > > > > > > > > >     - Removed sagv_uv_wm0(Ville)
> > > > > > > > > >     - can_sagv->use_sagv_wm(Ville)
> > > > > > > > > > 
> > > > > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > > > > > ---
> > > > > > > > > >  drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
> > > > > > > > > >  .../drm/i915/display/intel_display_types.h    |   2 +
> > > > > > > > > >  drivers/gpu/drm/i915/intel_pm.c               | 118 +++++++++++++++++-
> > > > > > > > > >  3 files changed, 121 insertions(+), 7 deletions(-)
> > > > > > > > > > 
> > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > > > > index fd6d63b03489..be5741cb7595 100644
> > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > > > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > > > > > >  		/* Watermarks */
> > > > > > > > > >  		for (level = 0; level <= max_level; level++) {
> > > > > > > > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > > > -						&sw_plane_wm->wm[level]))
> > > > > > > > > > +						&sw_plane_wm->wm[level]) ||
> > > > > > > > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > > > +							       &sw_plane_wm->sagv_wm0)))
> > > > > > > > > >  				continue;
> > > > > > > > > >  
> > > > > > > > > >  			drm_err(&dev_priv->drm,
> > > > > > > > > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > > > > > >  		/* Watermarks */
> > > > > > > > > >  		for (level = 0; level <= max_level; level++) {
> > > > > > > > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > > > -						&sw_plane_wm->wm[level]))
> > > > > > > > > > +						&sw_plane_wm->wm[level]) ||
> > > > > > > > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > > > +							       &sw_plane_wm->sagv_wm0)))
> > > > > > > > > >  				continue;
> > > > > > > > > >  
> > > > > > > > > >  			drm_err(&dev_priv->drm,
> > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > > > > index 9488449e4b94..8cede29c9562 100644
> > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > > > > @@ -688,11 +688,13 @@ struct skl_plane_wm {
> > > > > > > > > >  	struct skl_wm_level wm[8];
> > > > > > > > > >  	struct skl_wm_level uv_wm[8];
> > > > > > > > > >  	struct skl_wm_level trans_wm;
> > > > > > > > > > +	struct skl_wm_level sagv_wm0;
> > > > > > > > > >  	bool is_planar;
> > > > > > > > > >  };
> > > > > > > > > >  
> > > > > > > > > >  struct skl_pipe_wm {
> > > > > > > > > >  	struct skl_plane_wm planes[I915_MAX_PLANES];
> > > > > > > > > > +	bool use_sagv_wm;
> > > > > > > > > >  };
> > > > > > > > > >  
> > > > > > > > > >  enum vlv_wm_level {
> > > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > > index db188efee21e..934a686342ad 100644
> > > > > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > > @@ -3863,25 +3863,35 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > > > > > > > >  	return bw_state->pipe_sagv_reject == 0;
> > > > > > > > > >  }
> > > > > > > > > >  
> > > > > > > > > > +static bool
> > > > > > > > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > > > > > > > > 
> > > > > > > > > Just put the function here instead of adding fwd decalrations.
> > > > > > > > > 
> > > > > > > > > > +
> > > > > > > > > >  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > > > >  {
> > > > > > > > > >  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > > > > > >  	int ret;
> > > > > > > > > >  	struct intel_crtc *crtc;
> > > > > > > > > > -	const struct intel_crtc_state *new_crtc_state;
> > > > > > > > > > +	struct intel_crtc_state *new_crtc_state;
> > > > > > > > > >  	struct intel_bw_state *new_bw_state = NULL;
> > > > > > > > > >  	const struct intel_bw_state *old_bw_state = NULL;
> > > > > > > > > >  	int i;
> > > > > > > > > >  
> > > > > > > > > >  	for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > > > > >  					 new_crtc_state, i) {
> > > > > > > > > > +		bool can_sagv;
> > > > > > > > > > +
> > > > > > > > > >  		new_bw_state = intel_atomic_get_bw_state(state);
> > > > > > > > > >  		if (IS_ERR(new_bw_state))
> > > > > > > > > >  			return PTR_ERR(new_bw_state);
> > > > > > > > > >  
> > > > > > > > > >  		old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > > > > > > >  
> > > > > > > > > > -		if (skl_crtc_can_enable_sagv(new_crtc_state))
> > > > > > > > > > +		if (INTEL_GEN(dev_priv) >= 12)
> > > > > > > > > > +			can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > > > > > +		else
> > > > > > > > > > +			can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > > > > > +
> > > > > > > > > > +		if (can_sagv)
> > > > > > > > > >  			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > > > > > >  		else
> > > > > > > > > >  			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > > > > > > > @@ -3899,6 +3909,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > > > >  			return ret;
> > > > > > > > > >  	}
> > > > > > > > > >  
> > > > > > > > > > +	for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > > > > > +					 new_crtc_state, i) {
> > > > > > > > > > +		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > > > > > > > > +
> > > > > > > > > > +		/*
> > > > > > > > > > +		 * Due to drm limitation at commit state, when
> > > > > > > > > > +		 * changes are written the whole atomic state is
> > > > > > > > > > +		 * zeroed away => which prevents from using it,
> > > > > > > > > > +		 * so just sticking it into pipe wm state for
> > > > > > > > > > +		 * keeping it simple - anyway this is related to wm.
> > > > > > > > > > +		 * Proper way in ideal universe would be of course not
> > > > > > > > > > +		 * to lose parent atomic state object from child crtc_state,
> > > > > > > > > > +		 * and stick to OOP programming principles, which had been
> > > > > > > > > > +		 * scientifically proven to work.
> > > > > > > > > > +		 */
> > > > > > > > > 
> > > > > > > > > More ramblings. Just drop this comment too imo.
> > > > > > > > 
> > > > > > > > As I understand what is happening here is rather weird, so I thought 
> > > > > > > > commenting is good idea.
> > > > > > > 
> > > > > > > At least I have no idea what the comment is trying to say.
> > > > > > > I see nothing weird hapening here, we're just computing the
> > > > > > > state which is totally standard stuff.
> > > > > > 
> > > > > > Well I can remind, this is because there is no way to get parent state
> > > > > > from crtc_state, because of weird drm atomic behaviour which leaves us
> > > > > > with NULL parent state. So that we had to stick this boolean to some
> > > > > > place.
> > > > > > In normal code universe this wouldn't even be needed if we could
> > > > > > just get atomic state from crtc_state when we write wm in skl_write_plane_wm.
> > > > > 
> > > > > Didn't get that at all from the comment. It talked about zeroing some
> > > > > whole state which I took as 'memset(state, 0, sizeof(*state))'.
> > > > > As that is not what's going on I just got confused by the comment.
> > > > > 
> > > > > Now that I understand what this is about I think the comment
> > > > > (if we want to have one) should probably say something more like:
> > > > > "we store use_sagv_wm in the crtc state rather than relying on
> > > > >  the bw state since we have no convenient way to get at the
> > > > >  latter from the plane commit hooks (especially in the legacy
> > > > >  cursor case)".
> > > > > 
> > > > > > 
> > > > > > However probably OOP principles like parent-child hieararchy is not a thing
> > > > > > here. That what this comment was trying to say.
> > > > > > 
> > > > > > In normal OOP you can't destroy parent object _before_ destroying
> > > > > > child one.
> > > > > 
> > > > > There's no parent-child relationship between the crtc state and atomic
> > > > > state (which really shouldn't be called a state to begin with, rather
> > > > > it should be "transaction" or something along those lines).
> > > > 
> > > > In practice there is. crtc_state is being aggregated and contained as 
> > > > part of more general atomic state. That is exactly what parent-child
> > > > object relation is.
> > > > If you want to decouple those, this needs to be not aggregation but a reference,
> > > > i.e atomic state would not contain those state objects, but have a pointer
> > > > instead, but then you would not be using that container_of magic.
> > > 
> > > Pointers is what it has. And once the atomic commit is done the 
> > > atomic_state (ie. the object used to track the single transaction)
> > > goes away while the crtc/plane/etc. states remain behind.
> > 
> > If the rest of states are independent there should be sane way
> > to get those without the atomic state. 
> 
> How could you possibly get the right one without specifying
> which transaction you want them for?

Then if we still need those in skl_write_plane_wm or somewhere else during commit,
transaction should not go away yet.

Otherwise there is a logical contraversy: we need those objects, but can't get
them without transaction. But transaction still goes away,
because it's kinda "separate".

Stan

> 
> > 
> > Currently bw_state, cdclk_state and co - all can be retrieved only
> > using atomic state, which is at some point "gone". 
> > Also it is actually not even gone, we just zero out a pointer
> > to it in drm_crtc_state. 
> > 
> > I know why this done as we discussed, however I would 
> > emphasize that the proper way would be then
> > to completely decouple from it, so that all required states can
> > be retrieved without atomic state. Because currently we are
> > kind of in some "fuzzy" state in between.
> > 
> > Stan
> > 
> > > 
> > > -- 
> > > Ville Syrjälä
> > > Intel
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH v28 4/6] drm/i915: Add TGL+ SAGV support

[Ville Syrjälä]

On Tue, May 12, 2020 at 06:04:45PM +0300, Lisovskiy, Stanislav wrote:
> On Tue, May 12, 2020 at 05:32:21PM +0300, Ville Syrjälä wrote:
> > On Tue, May 12, 2020 at 04:59:19PM +0300, Lisovskiy, Stanislav wrote:
> > > On Tue, May 12, 2020 at 04:50:46PM +0300, Ville Syrjälä wrote:
> > > > On Tue, May 12, 2020 at 04:41:26PM +0300, Lisovskiy, Stanislav wrote:
> > > > > On Tue, May 12, 2020 at 04:38:21PM +0300, Ville Syrjälä wrote:
> > > > > > On Tue, May 12, 2020 at 04:17:34PM +0300, Lisovskiy, Stanislav wrote:
> > > > > > > On Tue, May 12, 2020 at 04:10:46PM +0300, Ville Syrjälä wrote:
> > > > > > > > On Tue, May 12, 2020 at 03:52:27PM +0300, Lisovskiy, Stanislav wrote:
> > > > > > > > > On Tue, May 12, 2020 at 03:03:26PM +0300, Ville Syrjälä wrote:
> > > > > > > > > > On Thu, May 07, 2020 at 05:45:01PM +0300, Stanislav Lisovskiy wrote:
> > > > > > > > > > > Starting from TGL we need to have a separate wm0
> > > > > > > > > > > values for SAGV and non-SAGV which affects
> > > > > > > > > > > how calculations are done.
> > > > > > > > > > > 
> > > > > > > > > > > v2: Remove long lines
> > > > > > > > > > > v3: Removed COLOR_PLANE enum references
> > > > > > > > > > > v4, v5, v6: Fixed rebase conflict
> > > > > > > > > > > v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
> > > > > > > > > > >     - Removed sagv_uv_wm0(Ville)
> > > > > > > > > > >     - can_sagv->use_sagv_wm(Ville)
> > > > > > > > > > > 
> > > > > > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > > > > > > ---
> > > > > > > > > > >  drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
> > > > > > > > > > >  .../drm/i915/display/intel_display_types.h    |   2 +
> > > > > > > > > > >  drivers/gpu/drm/i915/intel_pm.c               | 118 +++++++++++++++++-
> > > > > > > > > > >  3 files changed, 121 insertions(+), 7 deletions(-)
> > > > > > > > > > > 
> > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > > > > > index fd6d63b03489..be5741cb7595 100644
> > > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > > > > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > > > > > > >  		/* Watermarks */
> > > > > > > > > > >  		for (level = 0; level <= max_level; level++) {
> > > > > > > > > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > > > > -						&sw_plane_wm->wm[level]))
> > > > > > > > > > > +						&sw_plane_wm->wm[level]) ||
> > > > > > > > > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > > > > +							       &sw_plane_wm->sagv_wm0)))
> > > > > > > > > > >  				continue;
> > > > > > > > > > >  
> > > > > > > > > > >  			drm_err(&dev_priv->drm,
> > > > > > > > > > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > > > > > > > > > >  		/* Watermarks */
> > > > > > > > > > >  		for (level = 0; level <= max_level; level++) {
> > > > > > > > > > >  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > > > > -						&sw_plane_wm->wm[level]))
> > > > > > > > > > > +						&sw_plane_wm->wm[level]) ||
> > > > > > > > > > > +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> > > > > > > > > > > +							       &sw_plane_wm->sagv_wm0)))
> > > > > > > > > > >  				continue;
> > > > > > > > > > >  
> > > > > > > > > > >  			drm_err(&dev_priv->drm,
> > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > > > > > index 9488449e4b94..8cede29c9562 100644
> > > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > > > > > @@ -688,11 +688,13 @@ struct skl_plane_wm {
> > > > > > > > > > >  	struct skl_wm_level wm[8];
> > > > > > > > > > >  	struct skl_wm_level uv_wm[8];
> > > > > > > > > > >  	struct skl_wm_level trans_wm;
> > > > > > > > > > > +	struct skl_wm_level sagv_wm0;
> > > > > > > > > > >  	bool is_planar;
> > > > > > > > > > >  };
> > > > > > > > > > >  
> > > > > > > > > > >  struct skl_pipe_wm {
> > > > > > > > > > >  	struct skl_plane_wm planes[I915_MAX_PLANES];
> > > > > > > > > > > +	bool use_sagv_wm;
> > > > > > > > > > >  };
> > > > > > > > > > >  
> > > > > > > > > > >  enum vlv_wm_level {
> > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > > > index db188efee21e..934a686342ad 100644
> > > > > > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > > > > > @@ -3863,25 +3863,35 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > > > > > > > > >  	return bw_state->pipe_sagv_reject == 0;
> > > > > > > > > > >  }
> > > > > > > > > > >  
> > > > > > > > > > > +static bool
> > > > > > > > > > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > > > > > > > > > 
> > > > > > > > > > Just put the function here instead of adding fwd decalrations.
> > > > > > > > > > 
> > > > > > > > > > > +
> > > > > > > > > > >  static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > > > > >  {
> > > > > > > > > > >  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > > > > > > > >  	int ret;
> > > > > > > > > > >  	struct intel_crtc *crtc;
> > > > > > > > > > > -	const struct intel_crtc_state *new_crtc_state;
> > > > > > > > > > > +	struct intel_crtc_state *new_crtc_state;
> > > > > > > > > > >  	struct intel_bw_state *new_bw_state = NULL;
> > > > > > > > > > >  	const struct intel_bw_state *old_bw_state = NULL;
> > > > > > > > > > >  	int i;
> > > > > > > > > > >  
> > > > > > > > > > >  	for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > > > > > >  					 new_crtc_state, i) {
> > > > > > > > > > > +		bool can_sagv;
> > > > > > > > > > > +
> > > > > > > > > > >  		new_bw_state = intel_atomic_get_bw_state(state);
> > > > > > > > > > >  		if (IS_ERR(new_bw_state))
> > > > > > > > > > >  			return PTR_ERR(new_bw_state);
> > > > > > > > > > >  
> > > > > > > > > > >  		old_bw_state = intel_atomic_get_old_bw_state(state);
> > > > > > > > > > >  
> > > > > > > > > > > -		if (skl_crtc_can_enable_sagv(new_crtc_state))
> > > > > > > > > > > +		if (INTEL_GEN(dev_priv) >= 12)
> > > > > > > > > > > +			can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > > > > > > +		else
> > > > > > > > > > > +			can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > > > > > > > > > +
> > > > > > > > > > > +		if (can_sagv)
> > > > > > > > > > >  			new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > > > > > > > > >  		else
> > > > > > > > > > >  			new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > > > > > > > > > @@ -3899,6 +3909,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > > > > > > > > >  			return ret;
> > > > > > > > > > >  	}
> > > > > > > > > > >  
> > > > > > > > > > > +	for_each_new_intel_crtc_in_state(state, crtc,
> > > > > > > > > > > +					 new_crtc_state, i) {
> > > > > > > > > > > +		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> > > > > > > > > > > +
> > > > > > > > > > > +		/*
> > > > > > > > > > > +		 * Due to drm limitation at commit state, when
> > > > > > > > > > > +		 * changes are written the whole atomic state is
> > > > > > > > > > > +		 * zeroed away => which prevents from using it,
> > > > > > > > > > > +		 * so just sticking it into pipe wm state for
> > > > > > > > > > > +		 * keeping it simple - anyway this is related to wm.
> > > > > > > > > > > +		 * Proper way in ideal universe would be of course not
> > > > > > > > > > > +		 * to lose parent atomic state object from child crtc_state,
> > > > > > > > > > > +		 * and stick to OOP programming principles, which had been
> > > > > > > > > > > +		 * scientifically proven to work.
> > > > > > > > > > > +		 */
> > > > > > > > > > 
> > > > > > > > > > More ramblings. Just drop this comment too imo.
> > > > > > > > > 
> > > > > > > > > As I understand what is happening here is rather weird, so I thought 
> > > > > > > > > commenting is good idea.
> > > > > > > > 
> > > > > > > > At least I have no idea what the comment is trying to say.
> > > > > > > > I see nothing weird hapening here, we're just computing the
> > > > > > > > state which is totally standard stuff.
> > > > > > > 
> > > > > > > Well I can remind, this is because there is no way to get parent state
> > > > > > > from crtc_state, because of weird drm atomic behaviour which leaves us
> > > > > > > with NULL parent state. So that we had to stick this boolean to some
> > > > > > > place.
> > > > > > > In normal code universe this wouldn't even be needed if we could
> > > > > > > just get atomic state from crtc_state when we write wm in skl_write_plane_wm.
> > > > > > 
> > > > > > Didn't get that at all from the comment. It talked about zeroing some
> > > > > > whole state which I took as 'memset(state, 0, sizeof(*state))'.
> > > > > > As that is not what's going on I just got confused by the comment.
> > > > > > 
> > > > > > Now that I understand what this is about I think the comment
> > > > > > (if we want to have one) should probably say something more like:
> > > > > > "we store use_sagv_wm in the crtc state rather than relying on
> > > > > >  the bw state since we have no convenient way to get at the
> > > > > >  latter from the plane commit hooks (especially in the legacy
> > > > > >  cursor case)".
> > > > > > 
> > > > > > > 
> > > > > > > However probably OOP principles like parent-child hieararchy is not a thing
> > > > > > > here. That what this comment was trying to say.
> > > > > > > 
> > > > > > > In normal OOP you can't destroy parent object _before_ destroying
> > > > > > > child one.
> > > > > > 
> > > > > > There's no parent-child relationship between the crtc state and atomic
> > > > > > state (which really shouldn't be called a state to begin with, rather
> > > > > > it should be "transaction" or something along those lines).
> > > > > 
> > > > > In practice there is. crtc_state is being aggregated and contained as 
> > > > > part of more general atomic state. That is exactly what parent-child
> > > > > object relation is.
> > > > > If you want to decouple those, this needs to be not aggregation but a reference,
> > > > > i.e atomic state would not contain those state objects, but have a pointer
> > > > > instead, but then you would not be using that container_of magic.
> > > > 
> > > > Pointers is what it has. And once the atomic commit is done the 
> > > > atomic_state (ie. the object used to track the single transaction)
> > > > goes away while the crtc/plane/etc. states remain behind.
> > > 
> > > If the rest of states are independent there should be sane way
> > > to get those without the atomic state. 
> > 
> > How could you possibly get the right one without specifying
> > which transaction you want them for?
> 
> Then if we still need those in skl_write_plane_wm or somewhere else during commit,
> transaction should not go away yet.

IMO those backpointers shouldn't perhaps exist at all and instead we
should just plumb the atomic state through everywhere. But you tried
that and it kinda failed thanks to the legacy cursor hacks, so here
we are.

> 
> Otherwise there is a logical contraversy: we need those objects, but can't get
> them without transaction. But transaction still goes away,
> because it's kinda "separate".

It's a pre-existing issue with the atomic core/helpers. Changing
that is a lot of work, as we discused before a few times.

> 
> Stan
> 
> > 
> > > 
> > > Currently bw_state, cdclk_state and co - all can be retrieved only
> > > using atomic state, which is at some point "gone". 
> > > Also it is actually not even gone, we just zero out a pointer
> > > to it in drm_crtc_state. 
> > > 
> > > I know why this done as we discussed, however I would 
> > > emphasize that the proper way would be then
> > > to completely decouple from it, so that all required states can
> > > be retrieved without atomic state. Because currently we are
> > > kind of in some "fuzzy" state in between.
> > > 
> > > Stan
> > > 
> > > > 
> > > > -- 
> > > > Ville Syrjälä
> > > > Intel
> > 
> > -- 
> > Ville Syrjälä
> > Intel

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v28 3/6] drm/i915: Make active_pipes check skl specific

[Ville Syrjälä]

On Tue, May 12, 2020 at 04:26:53PM +0300, Lisovskiy, Stanislav wrote:
> On Tue, May 12, 2020 at 04:14:33PM +0300, Ville Syrjälä wrote:
> > On Tue, May 12, 2020 at 03:44:06PM +0300, Lisovskiy, Stanislav wrote:
> > > On Tue, May 12, 2020 at 02:39:25PM +0300, Ville Syrjälä wrote:
> > > > On Thu, May 07, 2020 at 05:45:00PM +0300, Stanislav Lisovskiy wrote:
> > > > > Seems that only skl needs to have SAGV turned off
> > > > > for multipipe scenarios, so lets do it this way.
> > > > 
> > > > It doesn't afaics. It's just someone added the check for some random
> > > > reason. So this should be reworded a bit. Also this isn't just about
> > > > skl/derivatives but all pre-icl so the <subject> is a bit misleading too.
> > > 
> > > This is in BSpec anyway. And it was in the code before, so I really 
> > > don't get what do you mean here.
> > > 
> > > > 
> > > > > 
> > > > > If anything blows up - we can always revert this patch.
> > > > > 
> > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++------
> > > > >  drivers/gpu/drm/i915/intel_pm.h |  3 ++-
> > > > >  2 files changed, 11 insertions(+), 7 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index 3dc1ad66beb3..db188efee21e 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -3777,7 +3777,7 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > > > >  	if (!new_bw_state)
> > > > >  		return;
> > > > >  
> > > > > -	if (!intel_can_enable_sagv(new_bw_state))
> > > > > +	if (!intel_can_enable_sagv(dev_priv, new_bw_state))
> > > > >  		intel_disable_sagv(dev_priv);
> > > > >  }
> > > > >  
> > > > > @@ -3800,7 +3800,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> > > > >  	if (!new_bw_state)
> > > > >  		return;
> > > > >  
> > > > > -	if (intel_can_enable_sagv(new_bw_state))
> > > > > +	if (intel_can_enable_sagv(dev_priv, new_bw_state))
> > > > >  		intel_enable_sagv(dev_priv);
> > > > >  }
> > > > >  
> > > > > @@ -3853,16 +3853,19 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > >  	return true;
> > > > >  }
> > > > >  
> > > > > -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > > > +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > > > +			   const struct intel_bw_state *bw_state)
> > > > >  {
> > > > > -	if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > > > -		return false;
> > > > > +	if (INTEL_GEN(dev_priv) < 11)
> > > > > +		if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > > 
> > > > If (a && b && c)
> > > > 	return false;
> > > 
> > > Then the line would get too long, and it does exactly same thing.
> > > I really don't understand such comments.
> > 
> > if (a && b &&
> >     c)
> > 
> > if (a &&
> >     b && c)
> > 
> > if (a &&
> >     b &&
> >     c)
> > 
> > there are plenty of options. The point is nested ifs like this
> > only serve to indent code needlessly deep.
> 
> and ifs like if (long condition1 && long condition2 && ...) make 
> unnecessary "wide". 
> 
> I would understand of course if I would do something like
> 3-4 nested ifs sure, however that one seems to be completely similar.
> 
> I don't even get why 
> 
> if (a &&
>     b && c)

"if a and b and c then do stuff"

> 
> reads better than
> 
> if (a)
>    if(b && c)

"if a then if b and c then do stuff"

The first one definitely sounds better to my ears. Not sure
the second one can even be called English.

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v28 5/6] drm/i915: Restrict qgv points which don't have enough bandwidth.

[Ville Syrjälä]

On Thu, May 07, 2020 at 05:45:02PM +0300, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
> 
> Currently we are just comparing against all of
> those and take minimum(worst case).
> 
> v2: Fixed wrong PCode reply mask, removed hardcoded
>     values.
> 
> v3: Forbid simultaneous legacy SAGV PCode requests and
>     restricting qgv points. Put the actual restriction
>     to commit function, added serialization(thanks to Ville)
>     to prevent commit being applied out of order in case of
>     nonblocking and/or nomodeset commits.
> 
> v4:
>     - Minor code refactoring, fixed few typos(thanks to James Ausmus)
>     - Change the naming of qgv point
>       masking/unmasking functions(James Ausmus).
>     - Simplify the masking/unmasking operation itself,
>       as we don't need to mask only single point per request(James Ausmus)
>     - Reject and stick to highest bandwidth point if SAGV
>       can't be enabled(BSpec)
> 
> v5:
>     - Add new mailbox reply codes, which seems to happen during boot
>       time for TGL and indicate that QGV setting is not yet available.
> 
> v6:
>     - Increase number of supported QGV points to be in sync with BSpec.
> 
> v7: - Rebased and resolved conflict to fix build failure.
>     - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
> 
> v8: - Don't report an error if we can't restrict qgv points, as SAGV
>       can be disabled by BIOS, which is completely legal. So don't
>       make CI panic. Instead if we detect that there is only 1 QGV
>       point accessible just analyze if we can fit the required bandwidth
>       requirements, but no need in restricting.
> 
> v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
>       simultaneously.
> 
> v10: - Fix CDCLK corruption, because of global state getting serialized
>        without modeset, which caused copying of non-calculated cdclk
>        to be copied to dev_priv(thanks to Ville for the hint).
> 
> v11: - Remove unneeded headers and spaces(Matthew Roper)
>      - Remove unneeded intel_qgv_info qi struct from bw check and zero
>        out the needed one(Matthew Roper)
>      - Changed QGV error message to have more clear meaning(Matthew Roper)
>      - Use state->modeset_set instead of any_ms(Matthew Roper)
>      - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
>      - Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
>      - Moved unrelated changes to other patch(using latency as parameter
>        for plane wm calculation, moved to SAGV refactoring patch)
> 
> v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
>      - Remove unnecessary mask being zero check when unmasking
>        qgv points as this is completely legal(Matt Roper)
>      - Check if we are setting the same mask as already being set
>        in hardware to prevent error from PCode.
>      - Fix error message when restricting/unrestricting qgv points
>        to "mask/unmask" which sounds more accurate(Matt Roper)
>      - Move sagv status setting to icl_get_bw_info from atomic check
>        as this should be calculated only once.(Matt Roper)
>      - Edited comments for the case when we can't enable SAGV and
>        use only 1 QGV point with highest bandwidth to be more
>        understandable.(Matt Roper)
> 
> v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
>      - Changed comment for zero new_mask in qgv points masking function
>        to better reflect reality(Ville Syrjälä)
>      - Simplified bit mask operation in qgv points masking function
>        (Ville Syrjälä)
>      - Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
>        however this still can't be under modeset condition(Ville Syrjälä)
>      - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
>        (Ville Syrjälä)
>      - Extracted PCode changes to separate patch.(Ville Syrjälä)
>      - Now treat num_planes 0 same as 1 to avoid confusion and
>        returning max_bw as 0, which would prevent choosing QGV
>        point having max bandwidth in case if SAGV is not allowed,
>        as per BSpec(Ville Syrjälä)
>      - Do the actual qgv_points_mask swap in the same place as
>        all other global state parts like cdclk are swapped.
>        In the next patch, this all will be moved to bw state as
>        global state, once new global state patch series from Ville
>        lands
> 
> v14: - Now using global state to serialize access to qgv points
>      - Added global state locking back, otherwise we seem to read
>        bw state in a wrong way.
> 
> v15: - Added TODO comment for near atomic global state locking in
>        bw code.
> 
> v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
>        with Jani Nikula.
>      - Take bw_state_changed flag into use.
> 
> v17: - Moved qgv point related manipulations next to SAGV code, as
>        those are semantically related(Ville Syrjälä)
>      - Renamed those into intel_sagv_(pre)|(post)_plane_update
>        (Ville Syrjälä)
> 
> v18: - Move sagv related calls from commit tail into
>        intel_sagv_(pre)|(post)_plane_update(Ville Syrjälä)
> 
> v19: - Use intel_atomic_get_bw_(old)|(new)_state which is intended
>        for commit tail stage.
> 
> v20: - Return max bandwidth for 0 planes(Ville)
>      - Constify old_bw_state in bw_atomic_check(Ville)
>      - Removed some debugs(Ville)
>      - Added data rate to debug print when no QGV points(Ville)
>      - Removed some comments(Ville)
> 
> v21, v22, v23: - Fixed rebase conflict
> 
> v24: - Changed PCode mask to use ICL_ prefix
> v25: - Resolved rebase conflict
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c       | 139 +++++++++++++-----
>  drivers/gpu/drm/i915/display/intel_bw.h       |   9 ++
>  .../drm/i915/display/intel_display_types.h    |   3 +
>  drivers/gpu/drm/i915/intel_pm.c               |  66 ++++++++-
>  drivers/gpu/drm/i915/intel_pm.h               |   2 +
>  5 files changed, 181 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 6e7cc3a4f1aa..5455420fde49 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -8,6 +8,9 @@
>  #include "intel_bw.h"
>  #include "intel_display_types.h"
>  #include "intel_sideband.h"
> +#include "intel_atomic.h"
> +#include "intel_pm.h"
> +
>  
>  /* Parameters for Qclk Geyserville (QGV) */
>  struct intel_qgv_point {
> @@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
>  	return 0;
>  }
>  
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> +				  u32 points_mask)
> +{
> +	int ret;
> +
> +	/* bspec says to keep retrying for at least 1 ms */
> +	ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> +				points_mask,
> +				ICL_PCODE_POINTS_RESTRICTED_MASK,
> +				ICL_PCODE_POINTS_RESTRICTED,
> +				1);
> +
> +	if (ret < 0) {
> +		DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
>  static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
>  			      struct intel_qgv_info *qi)
>  {
> @@ -240,6 +263,16 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
>  			break;
>  	}
>  
> +	/*
> +	 * In case if SAGV is disabled in BIOS, we always get 1
> +	 * SAGV point, but we can't send PCode commands to restrict it
> +	 * as it will fail and pointless anyway.
> +	 */
> +	if (qi.num_points == 1)
> +		dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
> +	else
> +		dev_priv->sagv_status = I915_SAGV_ENABLED;
> +
>  	return 0;
>  }
>  
> @@ -248,6 +281,11 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
>  {
>  	int i;
>  
> +	/*
> +	 * Let's return max bw for 0 planes
> +	 */
> +	num_planes = max(1, num_planes);
> +
>  	for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
>  		const struct intel_bw_info *bi =
>  			&dev_priv->max_bw[i];
> @@ -277,34 +315,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
>  		icl_get_bw_info(dev_priv, &icl_sa_info);
>  }
>  
> -static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
> -					int num_planes)
> -{
> -	if (INTEL_GEN(dev_priv) >= 11) {
> -		/*
> -		 * Any bw group has same amount of QGV points
> -		 */
> -		const struct intel_bw_info *bi =
> -			&dev_priv->max_bw[0];
> -		unsigned int min_bw = UINT_MAX;
> -		int i;
> -
> -		/*
> -		 * FIXME with SAGV disabled maybe we can assume
> -		 * point 1 will always be used? Seems to match
> -		 * the behaviour observed in the wild.
> -		 */
> -		for (i = 0; i < bi->num_qgv_points; i++) {
> -			unsigned int bw = icl_max_bw(dev_priv, num_planes, i);
> -
> -			min_bw = min(bw, min_bw);
> -		}
> -		return min_bw;
> -	} else {
> -		return UINT_MAX;
> -	}
> -}
> -
>  static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
>  {
>  	/*
> @@ -415,10 +425,15 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
>  	struct intel_bw_state *new_bw_state = NULL;
> -	unsigned int data_rate, max_data_rate;
> +	const struct intel_bw_state *old_bw_state = NULL;
> +	unsigned int data_rate;
>  	unsigned int num_active_planes;
>  	struct intel_crtc *crtc;
>  	int i, ret;
> +	u32 allowed_points = 0;
> +	unsigned int max_bw_point = 0, max_bw = 0;
> +	unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
> +	u32 mask = (1 << num_qgv_points) - 1;
>  
>  	/* FIXME earlier gens need some checks too */
>  	if (INTEL_GEN(dev_priv) < 11)
> @@ -465,19 +480,73 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
>  		return ret;
>  
>  	data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
> +	data_rate = DIV_ROUND_UP(data_rate, 1000);
> +
>  	num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
>  
> -	max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
> +	for (i = 0; i < num_qgv_points; i++) {
> +		unsigned int max_data_rate;
>  
> -	data_rate = DIV_ROUND_UP(data_rate, 1000);
> +		max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
> +		/*
> +		 * We need to know which qgv point gives us
> +		 * maximum bandwidth in order to disable SAGV
> +		 * if we find that we exceed SAGV block time
> +		 * with watermarks. By that moment we already
> +		 * have those, as it is calculated earlier in
> +		 * intel_atomic_check,
> +		 */
> +		if (max_data_rate > max_bw) {
> +			max_bw_point = i;
> +			max_bw = max_data_rate;
> +		}
> +		if (max_data_rate >= data_rate)
> +			allowed_points |= BIT(i);
> +		DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
> +			      i, max_data_rate, data_rate);
> +	}
>  
> -	if (data_rate > max_data_rate) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
> -			    data_rate, max_data_rate, num_active_planes);
> +	/*
> +	 * BSpec states that we always should have at least one allowed point
> +	 * left, so if we couldn't - simply reject the configuration for obvious
> +	 * reasons.
> +	 */
> +	if (allowed_points == 0) {
> +		DRM_DEBUG_KMS("No QGV points provide sufficient memory"
> +			      " bandwidth %d for display configuration.\n", data_rate);

Please use the drm_dbg_kms() & co. so as to not undo the changes other
people did to convert over to the per-device debugs/errors.

We also seem to lose the num_active_planes part of this debug message.
I think that might still be a nice piece of infomation to have around
when this fails.

>  		return -EINVAL;
>  	}
>  
> +	/*
> +	 * Leave only single point with highest bandwidth, if
> +	 * we can't enable SAGV due to the increased memory latency it may
> +	 * cause.
> +	 */
> +	if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
> +		allowed_points = BIT(max_bw_point);
> +		DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
> +			      max_bw_point);
> +	}
> +	/*
> +	 * We store the ones which need to be masked as that is what PCode
> +	 * actually accepts as a parameter.
> +	 */
> +	new_bw_state->qgv_points_mask = (~allowed_points) & mask;

Pointless parens.

> +
> +	old_bw_state = intel_atomic_get_old_bw_state(state);
> +	if (!old_bw_state)
> +		return -EINVAL;

This can't fail since you already have the new bw state.

> +
> +	/*
> +	 * If the actual mask had changed we need to make sure that
> +	 * the commits are serialized(in case this is a nomodeset, nonblocking)
> +	 */
> +	if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
> +		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> +		if (ret)
> +			return ret;
> +	}
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index 898b4a85ccab..bbcaaa73ec1b 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -24,6 +24,13 @@ struct intel_bw_state {
>  	 */
>  	u8 pipe_sagv_reject;
>  
> +	/*
> +	 * Current QGV points mask, which restricts
> +	 * some particular SAGV states, not to confuse
> +	 * with pipe_sagv_mask.
> +	 */
> +	u8 qgv_points_mask;
> +
>  	unsigned int data_rate[I915_MAX_PIPES];
>  	u8 num_active_planes[I915_MAX_PIPES];
>  
> @@ -47,5 +54,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
>  int intel_bw_atomic_check(struct intel_atomic_state *state);
>  void intel_bw_crtc_update(struct intel_bw_state *bw_state,
>  			  const struct intel_crtc_state *crtc_state);
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> +				  u32 points_mask);
>  
>  #endif /* __INTEL_BW_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8cede29c9562..6edf0844f8ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -692,6 +692,9 @@ struct skl_plane_wm {
>  	bool is_planar;
>  };
>  
> +/* BSpec precisely defines this */
> +#define NUM_SAGV_POINTS 8
> +
>  struct skl_pipe_wm {
>  	struct skl_plane_wm planes[I915_MAX_PLANES];
>  	bool use_sagv_wm;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 934a686342ad..66775d4fb1ae 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3761,7 +3761,10 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
>  void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	int ret;
>  	const struct intel_bw_state *new_bw_state;
> +	const struct intel_bw_state *old_bw_state;
> +	u32 new_mask = 0;
>  
>  	/*
>  	 * Just return if we can't control SAGV or don't have it.
> @@ -3777,15 +3780,48 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
>  	if (!new_bw_state)
>  		return;
>  
> -	if (!intel_can_enable_sagv(dev_priv, new_bw_state))
> +	if (INTEL_GEN(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv, new_bw_state)) {
>  		intel_disable_sagv(dev_priv);
> +		return;
> +	}
> +
> +	old_bw_state = intel_atomic_get_old_bw_state(state);
> +	if (!old_bw_state)
> +		return;

This too can't fail since we already checked that we have the
new_bw_state.

> +
> +	/*
> +	 * Nothing to mask
> +	 */
> +	if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
> +		return;
> +
> +	new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
> +
> +	/*
> +	 * If new mask is zero - means there is nothing to mask,
> +	 * we can only unmask, which should be done in unmask.
> +	 */
> +	if (!new_mask)
> +		return;
> +
> +	/*
> +	 * Restrict required qgv points before updating the configuration.
> +	 * According to BSpec we can't mask and unmask qgv points at the same
> +	 * time. Also masking should be done before updating the configuration
> +	 * and unmasking afterwards.
> +	 */
> +	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> +	if (ret < 0)
> +		drm_err(&dev_priv->drm, "Could not mask required qgv points(%d)\n", ret);

I think we now have double error prints. One here, the other inside
icl_pcode_restrict_qgv_points(). Pls nuke one of them so we don't have
redundant error prints.

>  }
>  
>  void intel_sagv_post_plane_update(struct intel_atomic_state *state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	int ret;
>  	const struct intel_bw_state *new_bw_state;
> -
> +	const struct intel_bw_state *old_bw_state;
> +	u32 new_mask = 0;
>  	/*
>  	 * Just return if we can't control SAGV or don't have it.
>  	 * This is different from situation when we have SAGV but just can't
> @@ -3800,8 +3836,32 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
>  	if (!new_bw_state)
>  		return;
>  
> -	if (intel_can_enable_sagv(dev_priv, new_bw_state))
> +	if (INTEL_GEN(dev_priv) < 11 && intel_can_enable_sagv(dev_priv, new_bw_state)) {
>  		intel_enable_sagv(dev_priv);
> +		return;
> +	}
> +
> +	old_bw_state = intel_atomic_get_old_bw_state(state);
> +	if (!old_bw_state)
> +		return;

can't fail.

> +
> +	/*
> +	 * Nothing to unmask
> +	 */
> +	if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
> +		return;
> +
> +	new_mask = new_bw_state->qgv_points_mask;
> +
> +	/*
> +	 * Allow required qgv points after updating the configuration.
> +	 * According to BSpec we can't mask and unmask qgv points at the same
> +	 * time. Also masking should be done before updating the configuration
> +	 * and unmasking afterwards.
> +	 */
> +	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> +	if (ret < 0)
> +		drm_err(&dev_priv->drm, "Could not unmask required qgv points(%d)\n", ret);

Another double error print.

Apart from those issues this looks nice.


>  }
>  
>  static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index 614ac7f8d4cc..528aba6267da 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -44,6 +44,8 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
>  void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
>  bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
>  			   const struct intel_bw_state *bw_state);
> +void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> +void intel_sagv_post_plane_update(struct intel_atomic_state *state);
>  int intel_enable_sagv(struct drm_i915_private *dev_priv);
>  int intel_disable_sagv(struct drm_i915_private *dev_priv);
>  void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> -- 
> 2.24.1.485.gad05a3d8e5

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v28 3/6] drm/i915: Make active_pipes check skl specific

[Lisovskiy, Stanislav]

On Tue, May 12, 2020 at 06:32:38PM +0300, Ville Syrjälä wrote:
> On Tue, May 12, 2020 at 04:26:53PM +0300, Lisovskiy, Stanislav wrote:
> > On Tue, May 12, 2020 at 04:14:33PM +0300, Ville Syrjälä wrote:
> > > On Tue, May 12, 2020 at 03:44:06PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Tue, May 12, 2020 at 02:39:25PM +0300, Ville Syrjälä wrote:
> > > > > On Thu, May 07, 2020 at 05:45:00PM +0300, Stanislav Lisovskiy wrote:
> > > > > > Seems that only skl needs to have SAGV turned off
> > > > > > for multipipe scenarios, so lets do it this way.
> > > > > 
> > > > > It doesn't afaics. It's just someone added the check for some random
> > > > > reason. So this should be reworded a bit. Also this isn't just about
> > > > > skl/derivatives but all pre-icl so the <subject> is a bit misleading too.
> > > > 
> > > > This is in BSpec anyway. And it was in the code before, so I really 
> > > > don't get what do you mean here.
> > > > 
> > > > > 
> > > > > > 
> > > > > > If anything blows up - we can always revert this patch.
> > > > > > 
> > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++------
> > > > > >  drivers/gpu/drm/i915/intel_pm.h |  3 ++-
> > > > > >  2 files changed, 11 insertions(+), 7 deletions(-)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > index 3dc1ad66beb3..db188efee21e 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > @@ -3777,7 +3777,7 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > > > > >  	if (!new_bw_state)
> > > > > >  		return;
> > > > > >  
> > > > > > -	if (!intel_can_enable_sagv(new_bw_state))
> > > > > > +	if (!intel_can_enable_sagv(dev_priv, new_bw_state))
> > > > > >  		intel_disable_sagv(dev_priv);
> > > > > >  }
> > > > > >  
> > > > > > @@ -3800,7 +3800,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> > > > > >  	if (!new_bw_state)
> > > > > >  		return;
> > > > > >  
> > > > > > -	if (intel_can_enable_sagv(new_bw_state))
> > > > > > +	if (intel_can_enable_sagv(dev_priv, new_bw_state))
> > > > > >  		intel_enable_sagv(dev_priv);
> > > > > >  }
> > > > > >  
> > > > > > @@ -3853,16 +3853,19 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > > > >  	return true;
> > > > > >  }
> > > > > >  
> > > > > > -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > > > > +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> > > > > > +			   const struct intel_bw_state *bw_state)
> > > > > >  {
> > > > > > -	if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > > > > -		return false;
> > > > > > +	if (INTEL_GEN(dev_priv) < 11)
> > > > > > +		if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > > > 
> > > > > If (a && b && c)
> > > > > 	return false;
> > > > 
> > > > Then the line would get too long, and it does exactly same thing.
> > > > I really don't understand such comments.
> > > 
> > > if (a && b &&
> > >     c)
> > > 
> > > if (a &&
> > >     b && c)
> > > 
> > > if (a &&
> > >     b &&
> > >     c)
> > > 
> > > there are plenty of options. The point is nested ifs like this
> > > only serve to indent code needlessly deep.
> > 
> > and ifs like if (long condition1 && long condition2 && ...) make 
> > unnecessary "wide". 
> > 
> > I would understand of course if I would do something like
> > 3-4 nested ifs sure, however that one seems to be completely similar.
> > 
> > I don't even get why 
> > 
> > if (a &&
> >     b && c)
> 
> "if a and b and c then do stuff"
> 
> > 
> > reads better than
> > 
> > if (a)
> >    if(b && c)
> 
> "if a then if b and c then do stuff"
> 
> The first one definitely sounds better to my ears. Not sure
> the second one can even be called English.

It is just a game of words here. You can also spell logical
expression like a && b && c, as "if a evaluates to True then
if b evaluates to true then if c evaluates to true, then do stuff".

Those expressions most likely produce same assembly even,
so basically you can spell both same way either.

So this arguing is honestly all about your personal matter of taste.
Which is fine I mean, everyone can write code according to own
preference unless it violates some _well known_ and _formal_ conventions.

Like of course I do realize that doing something like:

if (a)
  if(b)
    if(c)
      ...

is stupid, however that would be exaggeration to say
that I'm doing something like this here.

For example I really don't like long lines in 
conditions like (if verylongstuff && verylongstuff2 && ..)
neither those hanging && like

if (somestuff &&
    somestuff2 ||
    somestuff3)

to me the latter is way more horrible than

if (somestuff)
   if (somestuff2 || somestuff3)

which looks much more clear to me. Again imho..

Stan

> 
> -- 
> Ville Syrjälä
> Intel
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