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* [Intel-gfx] [PATCH] drm/i915/tgl+: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
@ 2020-07-14 16:32 Imre Deak
  2020-07-14 19:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
                   ` (5 more replies)
  0 siblings, 6 replies; 11+ messages in thread
From: Imre Deak @ 2020-07-14 16:32 UTC (permalink / raw)
  To: intel-gfx

Apply Display WA #22010492432 for combo PHY PLLs too. This should fix a
problem where the PLL output frequency is slightly off with the current
PLL fractional divider value.

I haven't seen an actual case where this causes a problem, but let's
follow the spec. It's also needed on some EHL platforms, but for that we
also need a way to distinguish the affected EHL SKUs, so I leave that
for a follow-up.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 54 +++++++++++++++++--
 1 file changed, 49 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index aeb6ee395cce..aee9101f5e7c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2887,7 +2887,7 @@ static const struct icl_combo_pll_params icl_dp_combo_pll_24MHz_values[] = {
 };
 
 
-/* Also used for 38.4 MHz values. */
+/* On ICL also used for 38.4 MHz values. */
 static const struct icl_combo_pll_params icl_dp_combo_pll_19_2MHz_values[] = {
 	{ 540000,
 	  { .dco_integer = 0x1A5, .dco_fraction = 0x7000,		/* [0]: 5.4 */
@@ -2915,6 +2915,37 @@ static const struct icl_combo_pll_params icl_dp_combo_pll_19_2MHz_values[] = {
 	    .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
 };
 
+/*
+ * Display WA #22010492432: tgl
+ * Divide the nominal .dco_fraction value by 2.
+ */
+static const struct icl_combo_pll_params tgl_dp_combo_pll_38_4MHz_values[] = {
+	{ 540000,
+	  { .dco_integer = 0x1A5, .dco_fraction = 0x3800,		/* [0]: 5.4 */
+	    .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
+	{ 270000,
+	  { .dco_integer = 0x1A5, .dco_fraction = 0x3800,		/* [1]: 2.7 */
+	    .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
+	{ 162000,
+	  { .dco_integer = 0x1A5, .dco_fraction = 0x3800,		/* [2]: 1.62 */
+	    .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
+	{ 324000,
+	  { .dco_integer = 0x1A5, .dco_fraction = 0x3800,		/* [3]: 3.24 */
+	    .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
+	{ 216000,
+	  { .dco_integer = 0x1C2, .dco_fraction = 0x0000,		/* [4]: 2.16 */
+	    .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2, }, },
+	{ 432000,
+	  { .dco_integer = 0x1C2, .dco_fraction = 0x0000,		/* [5]: 4.32 */
+	    .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
+	{ 648000,
+	  { .dco_integer = 0x1FA, .dco_fraction = 0x1000,		/* [6]: 6.48 */
+	    .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
+	{ 810000,
+	  { .dco_integer = 0x1A5, .dco_fraction = 0x3800,		/* [7]: 8.1 */
+	    .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
+};
+
 static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
 	.dco_integer = 0x151, .dco_fraction = 0x4000,
 	.pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
@@ -2950,13 +2981,26 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
 				  struct skl_wrpll_params *pll_params)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	const struct icl_combo_pll_params *params =
-		dev_priv->dpll.ref_clks.nssc == 24000 ?
-		icl_dp_combo_pll_24MHz_values :
-		icl_dp_combo_pll_19_2MHz_values;
+	const struct icl_combo_pll_params *params;
 	int clock = crtc_state->port_clock;
 	int i;
 
+	switch (dev_priv->dpll.ref_clks.nssc) {
+	case 19200:
+		params = icl_dp_combo_pll_19_2MHz_values;
+		break;
+	case 24000:
+		params = icl_dp_combo_pll_24MHz_values;
+		break;
+	case 38400:
+		/* TODO: Apply WA #22010492432 on EHL too. */
+		if (IS_TIGERLAKE(dev_priv))
+			params = tgl_dp_combo_pll_38_4MHz_values;
+		else
+			params = icl_dp_combo_pll_19_2MHz_values;
+		break;
+	}
+
 	for (i = 0; i < ARRAY_SIZE(icl_dp_combo_pll_24MHz_values); i++) {
 		if (clock == params[i].clock) {
 			*pll_params = params[i].wrpll;
-- 
2.23.1

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^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
@ 2020-10-03  0:18 Imre Deak
  2020-10-03  0:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2) Patchwork
  0 siblings, 1 reply; 11+ messages in thread
From: Imre Deak @ 2020-10-03  0:18 UTC (permalink / raw)
  To: intel-gfx

This patchset replaces [1]. That version's solution to work around
broken TGL A BIOSes turned out to be papering over something. The real
root cause was the lack of a full encoder recompute/modeset during the
initial commit and leaking the incorrect link rate into the PLL
frequency calculation code. So instead of making the PLL code aware of
incorrect link rates, this patchset forces a full modeset which will
recompute the correct link rate.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

[1] https://patchwork.freedesktop.org/series/82173/

Imre Deak (5):
  drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
  drm/i915: Move the initial fastset commit check to encoder hooks
  drm/i915: Check for unsupported DP link rates during initial commit
  drm/i915: Add an encoder hook to sanitize its state during init/resume
  drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref
    clock

 drivers/gpu/drm/i915/display/icl_dsi.c        | 14 ++++
 drivers/gpu/drm/i915/display/intel_ddi.c      | 18 +++++
 drivers/gpu/drm/i915/display/intel_display.c  | 33 +++++-----
 .../drm/i915/display/intel_display_types.h    | 15 +++++
 drivers/gpu/drm/i915/display/intel_dp.c       | 65 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h       |  5 ++
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 20 ++++++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 55 +++++++++++-----
 drivers/gpu/drm/i915/i915_reg.h               |  1 +
 9 files changed, 194 insertions(+), 32 deletions(-)

-- 
2.25.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-10-03  0:58 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-14 16:32 [Intel-gfx] [PATCH] drm/i915/tgl+: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
2020-07-14 19:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2020-07-15  0:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-07-17 16:10 ` [Intel-gfx] [PATCH] " Ville Syrjälä
2020-07-17 17:37   ` Imre Deak
2020-07-17 18:17     ` Ville Syrjälä
2020-08-17 18:08 ` [Intel-gfx] [PATCH v2] " Imre Deak
2020-08-17 18:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl+: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2) Patchwork
2020-08-17 21:17 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-08-18 14:07   ` Imre Deak
2020-10-03  0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
2020-10-03  0:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2) Patchwork

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