Re: [RFC PATCH v3 00/31] CXL 2.0 Support

[no-reply@patchew.org]

Patchew URL: https://patchew.org/QEMU/20210202005948.241655-1-ben.widawsky@intel.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210202005948.241655-1-ben.widawsky@intel.com
Subject: [RFC PATCH v3 00/31] CXL 2.0 Support

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20210202005948.241655-1-ben.widawsky@intel.com -> patchew/20210202005948.241655-1-ben.widawsky@intel.com
Switched to a new branch 'test'
e26ed22 WIP: i386/cxl: Initialize a host bridge
9329c2b qtest/cxl: Add very basic sanity tests
c140fd9 hw/cxl/device: Implement get/set LSA
8ed7755 hw/cxl/device: Plumb real LSA sizing
5f683ab hw/cxl/device: Add some trivial commands
4399501 tests/acpi: Add new CEDT files
6c13c92 acpi/cxl: Create the CEDT (9.14.1)
04a874a tests/acpi: allow CEDT table addition
50f82e6 acpi/cxl: Add _OSC implementation (9.14.2)
7eb8038 hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12)
ba80470 hw/cxl/device: Add a memory device (8.2.8.5)
54b9662 hw/cxl/rp: Add a root port
e70de08 hw/pxb/cxl: Add "windows" for host bridges
606831a acpi/pxb/cxl: Reserve host bridge MMIO
29a562b hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)
32e7bdd hw/pci: Plumb _UID through host bridges
6651f84 tests/acpi: remove stale allowed tables
24837fc acpi/pci: Consolidate host bridge setup
52f548c qtest: allow DSDT acpi table changes
bdcd7d9 hw/pxb: Allow creation of a CXL PXB (host bridge)
5d67d7e hw/pci/cxl: Create a CXL bus type
3b0d310 hw/pxb: Use a type for realizing expanders
5ccf850 hw/cxl/device: Add log commands (8.2.9.4) + CEL
892e722 hw/cxl/device: Timestamp implementation (8.2.9.3)
f2444bb hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1)
67fa438 hw/cxl/device: Add memory device utilities
cfa875c hw/cxl/device: Implement basic mailbox (8.2.8.4)
bdd7975 hw/cxl/device: Implement the CAP array (8.2.8.1-2)
c9e87d1 hw/cxl/device: Introduce a CXL device (8.2.8)
1cc9e2a hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)
7b0e042 hw/pci/cxl: Add a CXL component type (interface)

=== OUTPUT BEGIN ===
1/31 Checking commit 7b0e042bc22b (hw/pci/cxl: Add a CXL component type (interface))
2/31 Checking commit 1cc9e2a0a6d5 (hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5))
WARNING: line over 80 characters
#187: FILE: hw/cxl/cxl-component-utils.c:101:
+    reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0; /* CXL switches and devices must set */

WARNING: line over 80 characters
#193: FILE: hw/cxl/cxl-component-utils.c:107:
+    ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODER_ENABLE, 0);

WARNING: line over 80 characters
#406: FILE: include/hw/cxl/cxl_component.h:62:
+#define CXL_RAS_REGISTERS_OFFSET 0x80 /* Give ample space for caps before this */

WARNING: line over 80 characters
#417: FILE: include/hw/cxl/cxl_component.h:73:
+#define CXL_SEC_REGISTERS_OFFSET (CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGISTERS_SIZE)

WARNING: line over 80 characters
#421: FILE: include/hw/cxl/cxl_component.h:77:
+#define CXL_LINK_REGISTERS_OFFSET (CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE)

WARNING: line over 80 characters
#465: FILE: include/hw/cxl/cxl_component.h:121:
+#define CXL_EXTSEC_REGISTERS_OFFSET (CXL_HDM_REGISTERS_OFFSET + CXL_HDM_REGISTERS_SIZE)

WARNING: line over 80 characters
#469: FILE: include/hw/cxl/cxl_component.h:125:
+#define CXL_IDE_REGISTERS_OFFSET (CXL_EXTSEC_REGISTERS_OFFSET + CXL_EXTSEC_REGISTERS_SIZE)

WARNING: line over 80 characters
#473: FILE: include/hw/cxl/cxl_component.h:129:
+#define CXL_SNOOP_REGISTERS_OFFSET (CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE)

total: 0 errors, 8 warnings, 582 lines checked

Patch 2/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/31 Checking commit c9e87d150708 (hw/cxl/device: Introduce a CXL device (8.2.8))
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#36: 
new file mode 100644

WARNING: line over 80 characters
#156: FILE: include/hw/cxl/cxl_device.h:116:
+#define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset)                            \

total: 0 errors, 2 warnings, 162 lines checked

Patch 3/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/31 Checking commit bdd7975aa4bc (hw/cxl/device: Implement the CAP array (8.2.8.1-2))
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#23: 
new file mode 100644

ERROR: Macros with complex values should be enclosed in parenthesis
#159: FILE: include/hw/cxl/cxl_device.h:75:
+#define CXL_MMIO_SIZE                                       \
+    CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_REGISTERS_LENGTH + \
+        CXL_MAILBOX_REGISTERS_LENGTH

WARNING: line over 80 characters
#179: FILE: include/hw/cxl/cxl_device.h:138:
+#define cxl_device_cap_init(dstate, reg, cap_id)                                   \

WARNING: line over 80 characters
#180: FILE: include/hw/cxl/cxl_device.h:139:
+    do {                                                                           \

WARNING: line over 80 characters
#181: FILE: include/hw/cxl/cxl_device.h:140:
+        uint32_t *cap_hdrs = dstate->caps_reg_state32;                             \

WARNING: line over 80 characters
#182: FILE: include/hw/cxl/cxl_device.h:141:
+        int which = R_CXL_DEV_##reg##_CAP_HDR0;                                    \

WARNING: line over 80 characters
#183: FILE: include/hw/cxl/cxl_device.h:142:
+        cap_hdrs[which] =                                                          \

WARNING: line over 80 characters
#184: FILE: include/hw/cxl/cxl_device.h:143:
+            FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_ID, cap_id); \

WARNING: line over 80 characters
#185: FILE: include/hw/cxl/cxl_device.h:144:
+        cap_hdrs[which] = FIELD_DP32(                                              \

WARNING: line over 80 characters
#186: FILE: include/hw/cxl/cxl_device.h:145:
+            cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, 1);            \

WARNING: line over 80 characters
#187: FILE: include/hw/cxl/cxl_device.h:146:
+        cap_hdrs[which + 1] =                                                      \

WARNING: line over 80 characters
#188: FILE: include/hw/cxl/cxl_device.h:147:
+            FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1,              \

WARNING: line over 80 characters
#189: FILE: include/hw/cxl/cxl_device.h:148:
+                       CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET);                  \

WARNING: line over 80 characters
#190: FILE: include/hw/cxl/cxl_device.h:149:
+        cap_hdrs[which + 2] =                                                      \

WARNING: line over 80 characters
#191: FILE: include/hw/cxl/cxl_device.h:150:
+            FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2,              \

WARNING: line over 80 characters
#192: FILE: include/hw/cxl/cxl_device.h:151:
+                       CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH);                  \

total: 1 errors, 15 warnings, 158 lines checked

Patch 4/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

5/31 Checking commit cfa875c3c48b (hw/cxl/device: Implement basic mailbox (8.2.8.4))
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#191: 
new file mode 100644

ERROR: space prohibited between function name and open parenthesis '('
#264: FILE: hw/cxl/cxl-mailbox-utils.c:69:
+typedef ret_code (*opcode_handler)(struct cxl_cmd *cmd,

total: 1 errors, 1 warnings, 416 lines checked

Patch 5/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

6/31 Checking commit 67fa4383326f (hw/cxl/device: Add memory device utilities)
7/31 Checking commit f2444bba9cd7 (hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1))
8/31 Checking commit 892e722ede17 (hw/cxl/device: Timestamp implementation (8.2.9.3))
9/31 Checking commit 5ccf850db462 (hw/cxl/device: Add log commands (8.2.9.4) + CEL)
10/31 Checking commit 3b0d3108b26c (hw/pxb: Use a type for realizing expanders)
11/31 Checking commit 5d67d7eb3d82 (hw/pci/cxl: Create a CXL bus type)
12/31 Checking commit bdcd7d995e9f (hw/pxb: Allow creation of a CXL PXB (host bridge))
13/31 Checking commit 52f548ca385d (qtest: allow DSDT acpi table changes)
14/31 Checking commit 24837fc1bb0e (acpi/pci: Consolidate host bridge setup)
15/31 Checking commit 6651f845de76 (tests/acpi: remove stale allowed tables)
16/31 Checking commit 32e7bdd7607d (hw/pci: Plumb _UID through host bridges)
WARNING: line over 80 characters
#113: FILE: hw/pci-bridge/pci_expander_bridge.c:422:
+        error_setg(errp, "pxb-cxl devices must have a valid uid (0-2147483647)");

total: 0 errors, 1 warnings, 113 lines checked

Patch 16/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/31 Checking commit 29a562ba112f (hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142))
18/31 Checking commit 606831a33eda (acpi/pxb/cxl: Reserve host bridge MMIO)
19/31 Checking commit e70de0847b95 (hw/pxb/cxl: Add "windows" for host bridges)
WARNING: line over 80 characters
#133: FILE: hw/pci-bridge/pci_expander_bridge.c:516:
+        warn_report("memory-windows should be set when creating CXL host bridges");

total: 0 errors, 1 warnings, 127 lines checked

Patch 19/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
20/31 Checking commit 54b96623ffd8 (hw/cxl/rp: Add a root port)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42: 
new file mode 100644

total: 0 errors, 1 warnings, 268 lines checked

Patch 20/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/31 Checking commit ba804700c6a6 (hw/cxl/device: Add a memory device (8.2.8.5))
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#155: 
new file mode 100644

WARNING: line over 80 characters
#272: FILE: hw/mem/cxl_type3.c:113:
+                   "Not enough free space (%zd) required for device (%" PRId64  ")",

total: 0 errors, 2 warnings, 501 lines checked

Patch 21/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
22/31 Checking commit 7eb80384a516 (hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12))
WARNING: line over 80 characters
#92: FILE: hw/mem/cxl_type3.c:113:
+static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value, unsigned size)

total: 0 errors, 1 warnings, 114 lines checked

Patch 22/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
23/31 Checking commit 50f82e6dddb1 (acpi/cxl: Add _OSC implementation (9.14.2))
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#45: 
new file mode 100644

WARNING: Block comments use a leading /* on a separate line
#188: FILE: hw/i386/acpi-build.c:1210:
+    } else /* CXL */ {

total: 0 errors, 2 warnings, 176 lines checked

Patch 23/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
24/31 Checking commit 04a874a8d982 (tests/acpi: allow CEDT table addition)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16: 
new file mode 100644

total: 0 errors, 1 warnings, 3 lines checked

Patch 24/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
25/31 Checking commit 6c13c9205746 (acpi/cxl: Create the CEDT (9.14.1))
26/31 Checking commit 43995014aa28 (tests/acpi: Add new CEDT files)
27/31 Checking commit 5f683ab6ee1a (hw/cxl/device: Add some trivial commands)
28/31 Checking commit 8ed7755c7a36 (hw/cxl/device: Plumb real LSA sizing)
29/31 Checking commit c140fd9d4517 (hw/cxl/device: Implement get/set LSA)
30/31 Checking commit 9329c2b72e7f (qtest/cxl: Add very basic sanity tests)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15: 
new file mode 100644

WARNING: line over 80 characters
#36: FILE: tests/qtest/cxl-test.c:17:
+#define QEMU_T3D "-device cxl-type3,bus=rp0,memdev=cxl-mem1,id=cxl-pmem0,size=256M"

total: 0 errors, 2 warnings, 109 lines checked

Patch 30/31 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
31/31 Checking commit e26ed228d062 (WIP: i386/cxl: Initialize a host bridge)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20210202005948.241655-1-ben.widawsky@intel.com/testing.checkpatch/?type=message.
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