From: Ben Widawsky <ben.widawsky@intel.com> To: qemu-devel@nongnu.org Cc: "Ben Widawsky" <ben.widawsky@intel.com>, linux-cxl@vger.kernel.org, "Chris Browy" <cbrowy@avery-design.com>, "Dan Williams" <dan.j.williams@intel.com>, "David Hildenbrand" <david@redhat.com>, "Igor Mammedov" <imammedo@redhat.com>, "Ira Weiny" <ira.weiny@intel.com>, "Jonathan Cameron" <Jonathan.Cameron@Huawei.com>, "Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>, "Markus Armbruster" <armbru@redhat.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, "Vishal Verma" <vishal.l.verma@intel.com>, "John Groves (jgroves)" <jgroves@micron.com>, "Michael S. Tsirkin" <mst@redhat.com> Subject: [RFC PATCH v3 11/31] hw/pci/cxl: Create a CXL bus type Date: Mon, 1 Feb 2021 16:59:28 -0800 [thread overview] Message-ID: <20210202005948.241655-12-ben.widawsky@intel.com> (raw) In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> The easiest way to differentiate a CXL bus, and a PCIE bus is using a flag. A CXL bus, in hardware, is backward compatible with PCIE, and therefore the code tries pretty hard to keep them in sync as much as possible. The other way to implement this would be to try to cast the bus to the correct type. This is less code and useful for debugging via simply looking at the flags. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> --- hw/pci-bridge/pci_expander_bridge.c | 9 ++++++++- include/hw/pci/pci_bus.h | 7 +++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c index 232b7ce305..88c45dc3b5 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -24,7 +24,7 @@ #include "hw/boards.h" #include "qom/object.h" -enum BusType { PCI, PCIE }; +enum BusType { PCI, PCIE, CXL }; #define TYPE_PXB_BUS "pxb-bus" typedef struct PXBBus PXBBus; @@ -35,6 +35,10 @@ DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS, DECLARE_INSTANCE_CHECKER(PXBBus, PXB_PCIE_BUS, TYPE_PXB_PCIE_BUS) +#define TYPE_PXB_CXL_BUS "pxb-cxl-bus" +DECLARE_INSTANCE_CHECKER(PXBBus, PXB_CXL_BUS, + TYPE_PXB_CXL_BUS) + struct PXBBus { /*< private >*/ PCIBus parent_obj; @@ -244,6 +248,9 @@ static void pxb_dev_realize_common(PCIDevice *dev, enum BusType type, ds = qdev_new(TYPE_PXB_HOST); if (type == PCIE) { bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS); + } else if (type == CXL) { + bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_CXL_BUS); + bus->flags |= PCI_BUS_CXL; } else { bus = pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_PXB_BUS); bds = qdev_new("pci-bridge"); diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index 347440d42c..eb94e7e85c 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -24,6 +24,8 @@ enum PCIBusFlags { PCI_BUS_IS_ROOT = 0x0001, /* PCIe extended configuration space is accessible on this bus */ PCI_BUS_EXTENDED_CONFIG_SPACE = 0x0002, + /* This is a CXL Type BUS */ + PCI_BUS_CXL = 0x0004, }; struct PCIBus { @@ -53,6 +55,11 @@ struct PCIBus { Notifier machine_done; }; +static inline bool pci_bus_is_cxl(PCIBus *bus) +{ + return !!(bus->flags & PCI_BUS_CXL); +} + static inline bool pci_bus_is_root(PCIBus *bus) { return !!(bus->flags & PCI_BUS_IS_ROOT); -- 2.30.0
WARNING: multiple messages have this Message-ID (diff)
From: Ben Widawsky <ben.widawsky@intel.com> To: qemu-devel@nongnu.org Cc: "Ben Widawsky" <ben.widawsky@intel.com>, "David Hildenbrand" <david@redhat.com>, "Vishal Verma" <vishal.l.verma@intel.com>, "John Groves (jgroves)" <jgroves@micron.com>, "Chris Browy" <cbrowy@avery-design.com>, "Markus Armbruster" <armbru@redhat.com>, linux-cxl@vger.kernel.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, "Michael S. Tsirkin" <mst@redhat.com>, "Jonathan Cameron" <Jonathan.Cameron@Huawei.com>, "Igor Mammedov" <imammedo@redhat.com>, "Dan Williams" <dan.j.williams@intel.com>, "Ira Weiny" <ira.weiny@intel.com> Subject: [RFC PATCH v3 11/31] hw/pci/cxl: Create a CXL bus type Date: Mon, 1 Feb 2021 16:59:28 -0800 [thread overview] Message-ID: <20210202005948.241655-12-ben.widawsky@intel.com> (raw) In-Reply-To: <20210202005948.241655-1-ben.widawsky@intel.com> The easiest way to differentiate a CXL bus, and a PCIE bus is using a flag. A CXL bus, in hardware, is backward compatible with PCIE, and therefore the code tries pretty hard to keep them in sync as much as possible. The other way to implement this would be to try to cast the bus to the correct type. This is less code and useful for debugging via simply looking at the flags. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> --- hw/pci-bridge/pci_expander_bridge.c | 9 ++++++++- include/hw/pci/pci_bus.h | 7 +++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c index 232b7ce305..88c45dc3b5 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -24,7 +24,7 @@ #include "hw/boards.h" #include "qom/object.h" -enum BusType { PCI, PCIE }; +enum BusType { PCI, PCIE, CXL }; #define TYPE_PXB_BUS "pxb-bus" typedef struct PXBBus PXBBus; @@ -35,6 +35,10 @@ DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS, DECLARE_INSTANCE_CHECKER(PXBBus, PXB_PCIE_BUS, TYPE_PXB_PCIE_BUS) +#define TYPE_PXB_CXL_BUS "pxb-cxl-bus" +DECLARE_INSTANCE_CHECKER(PXBBus, PXB_CXL_BUS, + TYPE_PXB_CXL_BUS) + struct PXBBus { /*< private >*/ PCIBus parent_obj; @@ -244,6 +248,9 @@ static void pxb_dev_realize_common(PCIDevice *dev, enum BusType type, ds = qdev_new(TYPE_PXB_HOST); if (type == PCIE) { bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS); + } else if (type == CXL) { + bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_CXL_BUS); + bus->flags |= PCI_BUS_CXL; } else { bus = pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_PXB_BUS); bds = qdev_new("pci-bridge"); diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index 347440d42c..eb94e7e85c 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -24,6 +24,8 @@ enum PCIBusFlags { PCI_BUS_IS_ROOT = 0x0001, /* PCIe extended configuration space is accessible on this bus */ PCI_BUS_EXTENDED_CONFIG_SPACE = 0x0002, + /* This is a CXL Type BUS */ + PCI_BUS_CXL = 0x0004, }; struct PCIBus { @@ -53,6 +55,11 @@ struct PCIBus { Notifier machine_done; }; +static inline bool pci_bus_is_cxl(PCIBus *bus) +{ + return !!(bus->flags & PCI_BUS_CXL); +} + static inline bool pci_bus_is_root(PCIBus *bus) { return !!(bus->flags & PCI_BUS_IS_ROOT); -- 2.30.0
next prev parent reply other threads:[~2021-02-02 1:01 UTC|newest] Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-02 0:59 [RFC PATCH v3 00/31] CXL 2.0 Support Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 01/31] hw/pci/cxl: Add a CXL component type (interface) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 02/31] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 11:48 ` Jonathan Cameron 2021-02-02 11:48 ` Jonathan Cameron 2021-02-17 18:36 ` Ben Widawsky 2021-02-11 17:08 ` Jonathan Cameron 2021-02-11 17:08 ` Jonathan Cameron 2021-02-17 16:40 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 03/31] hw/cxl/device: Introduce a CXL device (8.2.8) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 12:03 ` Jonathan Cameron 2021-02-02 12:03 ` Jonathan Cameron 2021-02-02 0:59 ` [RFC PATCH v3 04/31] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 12:23 ` Jonathan Cameron 2021-02-02 12:23 ` Jonathan Cameron 2021-02-17 22:15 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 05/31] hw/cxl/device: Implement basic mailbox (8.2.8.4) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 14:58 ` Jonathan Cameron 2021-02-02 14:58 ` Jonathan Cameron 2021-02-11 17:46 ` Jonathan Cameron 2021-02-18 0:55 ` Ben Widawsky 2021-02-18 16:50 ` Jonathan Cameron 2021-02-11 18:09 ` Jonathan Cameron 2021-02-11 18:09 ` Jonathan Cameron 2021-02-02 0:59 ` [RFC PATCH v3 06/31] hw/cxl/device: Add memory device utilities Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 07/31] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 13:44 ` Jonathan Cameron 2021-02-02 13:44 ` Jonathan Cameron 2021-02-11 17:59 ` Jonathan Cameron 2021-02-11 17:59 ` Jonathan Cameron 2021-02-02 0:59 ` [RFC PATCH v3 08/31] hw/cxl/device: Timestamp implementation (8.2.9.3) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 09/31] hw/cxl/device: Add log commands (8.2.9.4) + CEL Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 10/31] hw/pxb: Use a type for realizing expanders Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 13:50 ` Jonathan Cameron 2021-02-02 13:50 ` Jonathan Cameron 2021-02-02 0:59 ` Ben Widawsky [this message] 2021-02-02 0:59 ` [RFC PATCH v3 11/31] hw/pci/cxl: Create a CXL bus type Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 12/31] hw/pxb: Allow creation of a CXL PXB (host bridge) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 13/31] qtest: allow DSDT acpi table changes Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 14/31] acpi/pci: Consolidate host bridge setup Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 13:56 ` Jonathan Cameron 2021-02-02 13:56 ` Jonathan Cameron 2021-12-02 10:32 ` Jonathan Cameron 2021-12-02 10:32 ` Jonathan Cameron via 2021-02-02 0:59 ` [RFC PATCH v3 15/31] tests/acpi: remove stale allowed tables Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 16/31] hw/pci: Plumb _UID through host bridges Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 15:00 ` Jonathan Cameron 2021-02-02 15:00 ` Jonathan Cameron 2021-02-02 15:24 ` Michael S. Tsirkin 2021-02-02 15:24 ` Michael S. Tsirkin 2021-02-02 15:42 ` Ben Widawsky 2021-02-02 15:42 ` Ben Widawsky 2021-02-02 15:51 ` Michael S. Tsirkin 2021-02-02 15:51 ` Michael S. Tsirkin 2021-02-02 16:20 ` Ben Widawsky 2021-02-02 16:20 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 17/31] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 19:21 ` Jonathan Cameron 2021-02-02 19:21 ` Jonathan Cameron 2021-02-02 19:45 ` Ben Widawsky 2021-02-02 20:43 ` Jonathan Cameron 2021-02-02 21:03 ` Ben Widawsky 2021-02-02 22:06 ` Jonathan Cameron 2021-02-02 0:59 ` [RFC PATCH v3 18/31] acpi/pxb/cxl: Reserve host bridge MMIO Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 19/31] hw/pxb/cxl: Add "windows" for host bridges Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 20/31] hw/cxl/rp: Add a root port Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 21/31] hw/cxl/device: Add a memory device (8.2.8.5) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 14:26 ` Eric Blake 2021-02-02 15:06 ` Ben Widawsky 2021-02-02 15:06 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 22/31] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 23/31] acpi/cxl: Add _OSC implementation (9.14.2) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 24/31] tests/acpi: allow CEDT table addition Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 25/31] acpi/cxl: Create the CEDT (9.14.1) Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 26/31] tests/acpi: Add new CEDT files Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 27/31] hw/cxl/device: Add some trivial commands Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 28/31] hw/cxl/device: Plumb real LSA sizing Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 29/31] hw/cxl/device: Implement get/set LSA Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 30/31] qtest/cxl: Add very basic sanity tests Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 0:59 ` [RFC PATCH v3 31/31] WIP: i386/cxl: Initialize a host bridge Ben Widawsky 2021-02-02 0:59 ` Ben Widawsky 2021-02-02 1:33 ` [RFC PATCH v3 00/31] CXL 2.0 Support no-reply 2021-02-02 1:33 ` no-reply 2021-02-03 17:42 ` Ben Widawsky 2021-02-11 18:51 ` Jonathan Cameron 2021-02-11 18:51 ` Jonathan Cameron 2021-03-11 23:27 ` [RFC PATCH] hw/mem/cxl_type3: Go back to subregions Ben Widawsky
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