* [Intel-gfx] [PATCH 0/8] i915: Introduce Xe_HP compute engines
@ 2021-09-07 17:19 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Matt Roper
The Xe_HP architecture introduces compute engines as a new engine class.
These compute command streamers (CCS) are similar to the render engine,
except that they're intended for GPGPU usage and lack support for the 3D
pipeline.
The definition of I915_ENGINE_CLASS_COMPUTE is new ABI; see below for a
link to a UMD (compute) merge request that utilizes the new ABI.
This series adds some of the basic enablement for the CCS engines, but
does not yet add them to the engine list for the relevant platforms
(XeHP SDV and DG2); that will be handled in future series.
UMD (compute): https://github.com/intel/compute-runtime/pull/451
Daniele Ceraolo Spurio (1):
drm/i915/xehp: compute engine pipe_control
John Harrison (1):
drm/i915/xehp: Extend uninterruptible OpenCL workloads to CCS
Matt Roper (6):
drm/i915/xehp: Define compute class and engine
drm/i915/xehp: CCS shares the render reset domain
drm/i915/xehp: Add Compute CS IRQ handlers
drm/i915/xehp: CCS should use RCS setup functions
drm/i915/xehp: Define context scheduling attributes in lrc descriptor
drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE
.../drm/i915/gem/selftests/i915_gem_context.c | 8 ++--
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 31 ++++++++++-----
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 39 ++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 11 +++++-
drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 ++-
.../drm/i915/gt/intel_execlists_submission.c | 34 +++++++++++++++-
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 +++++++
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 15 ++++++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
drivers/gpu/drm/i915/gt/intel_lrc.h | 10 +++++
drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 13 ++++---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 28 ++++++++++++-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_perf.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++-
include/uapi/drm/i915_drm.h | 1 +
17 files changed, 215 insertions(+), 29 deletions(-)
--
2.25.4
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 1/8] drm/i915/xehp: Define compute class and engine
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
@ 2021-09-07 17:19 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Matt Roper, Daniele Ceraolo Spurio, Tvrtko Ursulin,
Vinay Belgaumkar, Szymon Morek, Rodrigo Vivi, Aravind Iddamsetty
Introduce a Compute Command Streamer (CCS), which has access to
the media and GPGPU pipelines (but not the 3D pipeline).
To begin with, define the compute class/engine common functions, based
on the existing render ones.
Bspec: 46167, 45544
Original-patch-by: Michel Thierry
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Szymon Morek <szymon.morek@intel.com>
UMD (compute): https://github.com/intel/compute-runtime/pull/451
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 28 ++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 ++++++-
drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 +++-
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 13 +++++----
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++
include/uapi/drm/i915_drm.h | 1 +
6 files changed, 57 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 332efea696a5..69944bd8c19d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -153,6 +153,34 @@ static const struct engine_info intel_engines[] = {
{ .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
},
},
+ [CCS0] = {
+ .class = COMPUTE_CLASS,
+ .instance = 0,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
+ }
+ },
+ [CCS1] = {
+ .class = COMPUTE_CLASS,
+ .instance = 1,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
+ }
+ },
+ [CCS2] = {
+ .class = COMPUTE_CLASS,
+ .instance = 2,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
+ }
+ },
+ [CCS3] = {
+ .class = COMPUTE_CLASS,
+ .instance = 3,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
+ }
+ },
};
/**
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index bfbfe53c23dd..dcb9d8b2362a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -33,7 +33,8 @@
#define VIDEO_ENHANCEMENT_CLASS 2
#define COPY_ENGINE_CLASS 3
#define OTHER_CLASS 4
-#define MAX_ENGINE_CLASS 4
+#define COMPUTE_CLASS 5
+#define MAX_ENGINE_CLASS 5
#define MAX_ENGINE_INSTANCE 7
#define I915_MAX_SLICES 3
@@ -95,6 +96,7 @@ struct i915_ctx_workarounds {
#define I915_MAX_VCS 8
#define I915_MAX_VECS 4
+#define I915_MAX_CCS 4
/*
* Engine IDs definitions.
@@ -117,6 +119,11 @@ enum intel_engine_id {
VECS2,
VECS3,
#define _VECS(n) (VECS0 + (n))
+ CCS0,
+ CCS1,
+ CCS2,
+ CCS3,
+#define _CCS(n) (CCS0 + (n))
I915_NUM_ENGINES
#define INVALID_ENGINE ((enum intel_engine_id)-1)
};
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 8f8bea08e734..d981621a7c30 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -47,6 +47,7 @@ static const u8 uabi_classes[] = {
[COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
[VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
[VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
+ [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
};
static int engine_cmp(void *priv, const struct list_head *A,
@@ -139,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
[COPY_ENGINE_CLASS] = "bcs",
[VIDEO_DECODE_CLASS] = "vcs",
[VIDEO_ENHANCEMENT_CLASS] = "vecs",
+ [COMPUTE_CLASS] = "ccs",
};
if (class >= ARRAY_SIZE(uabi_names) || !uabi_names[class])
@@ -162,6 +164,7 @@ static int legacy_ring_idx(const struct legacy_ring *ring)
[COPY_ENGINE_CLASS] = { BCS0, 1 },
[VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS },
[VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS },
+ [COMPUTE_CLASS] = { CCS0, I915_MAX_CCS },
};
if (GEM_DEBUG_WARN_ON(ring->class >= ARRAY_SIZE(map)))
@@ -190,7 +193,7 @@ static void add_legacy_ring(struct legacy_ring *ring,
void intel_engines_driver_register(struct drm_i915_private *i915)
{
struct legacy_ring ring = {};
- u8 uabi_instances[4] = {};
+ u8 uabi_instances[5] = {};
struct list_head *it, *next;
struct rb_node **p, *prev;
LIST_HEAD(engines);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index fa4be13c8854..3f9007e4e895 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -45,8 +45,8 @@
#define GUC_VIDEO_CLASS 1
#define GUC_VIDEOENHANCE_CLASS 2
#define GUC_BLITTER_CLASS 3
-#define GUC_RESERVED_CLASS 4
-#define GUC_LAST_ENGINE_CLASS GUC_RESERVED_CLASS
+#define GUC_COMPUTE_CLASS 4
+#define GUC_LAST_ENGINE_CLASS GUC_COMPUTE_CLASS
#define GUC_MAX_ENGINE_CLASSES 16
#define GUC_MAX_INSTANCES_PER_CLASS 32
@@ -154,17 +154,20 @@ static inline u8 engine_class_to_guc_class(u8 class)
BUILD_BUG_ON(GUC_BLITTER_CLASS != COPY_ENGINE_CLASS);
BUILD_BUG_ON(GUC_VIDEO_CLASS != VIDEO_DECODE_CLASS);
BUILD_BUG_ON(GUC_VIDEOENHANCE_CLASS != VIDEO_ENHANCEMENT_CLASS);
+ BUILD_BUG_ON(GUC_COMPUTE_CLASS != (COMPUTE_CLASS - 1));
GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
- return class;
+ /* the GuC arrays don't include OTHER_CLASS */
+ return class < OTHER_CLASS ? class : class - 1;
}
static inline u8 guc_class_to_engine_class(u8 guc_class)
{
+ BUILD_BUG_ON(GUC_COMPUTE_CLASS != OTHER_CLASS);
+ BUILD_BUG_ON(GUC_LAST_ENGINE_CLASS != (MAX_ENGINE_CLASS - 1));
GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS);
- GEM_BUG_ON(guc_class == GUC_RESERVED_CLASS);
- return guc_class;
+ return guc_class < GUC_COMPUTE_CLASS ? guc_class : guc_class + 1;
}
/* Work item for submitting workloads into work queue of GuC. */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2853cc005ee..33d6aa0b07c1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2528,6 +2528,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN11_VEBOX2_RING_BASE 0x1d8000
#define XEHP_VEBOX3_RING_BASE 0x1e8000
#define XEHP_VEBOX4_RING_BASE 0x1f8000
+#define GEN12_COMPUTE0_RING_BASE 0x1a000
+#define GEN12_COMPUTE1_RING_BASE 0x1c000
+#define GEN12_COMPUTE2_RING_BASE 0x1e000
+#define GEN12_COMPUTE3_RING_BASE 0x26000
#define BLT_RING_BASE 0x22000
#define RING_TAIL(base) _MMIO((base) + 0x30)
#define RING_HEAD(base) _MMIO((base) + 0x34)
@@ -8100,6 +8104,10 @@ enum {
#define GEN11_KCR (19)
#define GEN11_GTPM (16)
#define GEN11_BCS (15)
+#define GEN12_CCS3 (7)
+#define GEN12_CCS2 (6)
+#define GEN12_CCS1 (5)
+#define GEN12_CCS0 (4)
#define GEN11_RCS0 (0)
#define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index bde5860b3686..9540f33523d8 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -166,6 +166,7 @@ enum drm_i915_gem_engine_class {
I915_ENGINE_CLASS_COPY = 1,
I915_ENGINE_CLASS_VIDEO = 2,
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
+ I915_ENGINE_CLASS_COMPUTE = 4,
/* should be kept compact */
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread* [Intel-gfx] [PATCH 1/8] drm/i915/xehp: Define compute class and engine
@ 2021-09-07 17:19 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Matt Roper, Daniele Ceraolo Spurio, Tvrtko Ursulin,
Vinay Belgaumkar, Szymon Morek, Rodrigo Vivi, Aravind Iddamsetty
Introduce a Compute Command Streamer (CCS), which has access to
the media and GPGPU pipelines (but not the 3D pipeline).
To begin with, define the compute class/engine common functions, based
on the existing render ones.
Bspec: 46167, 45544
Original-patch-by: Michel Thierry
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Szymon Morek <szymon.morek@intel.com>
UMD (compute): https://github.com/intel/compute-runtime/pull/451
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 28 ++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 ++++++-
drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 +++-
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 13 +++++----
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++
include/uapi/drm/i915_drm.h | 1 +
6 files changed, 57 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 332efea696a5..69944bd8c19d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -153,6 +153,34 @@ static const struct engine_info intel_engines[] = {
{ .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
},
},
+ [CCS0] = {
+ .class = COMPUTE_CLASS,
+ .instance = 0,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
+ }
+ },
+ [CCS1] = {
+ .class = COMPUTE_CLASS,
+ .instance = 1,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
+ }
+ },
+ [CCS2] = {
+ .class = COMPUTE_CLASS,
+ .instance = 2,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
+ }
+ },
+ [CCS3] = {
+ .class = COMPUTE_CLASS,
+ .instance = 3,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
+ }
+ },
};
/**
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index bfbfe53c23dd..dcb9d8b2362a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -33,7 +33,8 @@
#define VIDEO_ENHANCEMENT_CLASS 2
#define COPY_ENGINE_CLASS 3
#define OTHER_CLASS 4
-#define MAX_ENGINE_CLASS 4
+#define COMPUTE_CLASS 5
+#define MAX_ENGINE_CLASS 5
#define MAX_ENGINE_INSTANCE 7
#define I915_MAX_SLICES 3
@@ -95,6 +96,7 @@ struct i915_ctx_workarounds {
#define I915_MAX_VCS 8
#define I915_MAX_VECS 4
+#define I915_MAX_CCS 4
/*
* Engine IDs definitions.
@@ -117,6 +119,11 @@ enum intel_engine_id {
VECS2,
VECS3,
#define _VECS(n) (VECS0 + (n))
+ CCS0,
+ CCS1,
+ CCS2,
+ CCS3,
+#define _CCS(n) (CCS0 + (n))
I915_NUM_ENGINES
#define INVALID_ENGINE ((enum intel_engine_id)-1)
};
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 8f8bea08e734..d981621a7c30 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -47,6 +47,7 @@ static const u8 uabi_classes[] = {
[COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
[VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
[VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
+ [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
};
static int engine_cmp(void *priv, const struct list_head *A,
@@ -139,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
[COPY_ENGINE_CLASS] = "bcs",
[VIDEO_DECODE_CLASS] = "vcs",
[VIDEO_ENHANCEMENT_CLASS] = "vecs",
+ [COMPUTE_CLASS] = "ccs",
};
if (class >= ARRAY_SIZE(uabi_names) || !uabi_names[class])
@@ -162,6 +164,7 @@ static int legacy_ring_idx(const struct legacy_ring *ring)
[COPY_ENGINE_CLASS] = { BCS0, 1 },
[VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS },
[VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS },
+ [COMPUTE_CLASS] = { CCS0, I915_MAX_CCS },
};
if (GEM_DEBUG_WARN_ON(ring->class >= ARRAY_SIZE(map)))
@@ -190,7 +193,7 @@ static void add_legacy_ring(struct legacy_ring *ring,
void intel_engines_driver_register(struct drm_i915_private *i915)
{
struct legacy_ring ring = {};
- u8 uabi_instances[4] = {};
+ u8 uabi_instances[5] = {};
struct list_head *it, *next;
struct rb_node **p, *prev;
LIST_HEAD(engines);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index fa4be13c8854..3f9007e4e895 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -45,8 +45,8 @@
#define GUC_VIDEO_CLASS 1
#define GUC_VIDEOENHANCE_CLASS 2
#define GUC_BLITTER_CLASS 3
-#define GUC_RESERVED_CLASS 4
-#define GUC_LAST_ENGINE_CLASS GUC_RESERVED_CLASS
+#define GUC_COMPUTE_CLASS 4
+#define GUC_LAST_ENGINE_CLASS GUC_COMPUTE_CLASS
#define GUC_MAX_ENGINE_CLASSES 16
#define GUC_MAX_INSTANCES_PER_CLASS 32
@@ -154,17 +154,20 @@ static inline u8 engine_class_to_guc_class(u8 class)
BUILD_BUG_ON(GUC_BLITTER_CLASS != COPY_ENGINE_CLASS);
BUILD_BUG_ON(GUC_VIDEO_CLASS != VIDEO_DECODE_CLASS);
BUILD_BUG_ON(GUC_VIDEOENHANCE_CLASS != VIDEO_ENHANCEMENT_CLASS);
+ BUILD_BUG_ON(GUC_COMPUTE_CLASS != (COMPUTE_CLASS - 1));
GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
- return class;
+ /* the GuC arrays don't include OTHER_CLASS */
+ return class < OTHER_CLASS ? class : class - 1;
}
static inline u8 guc_class_to_engine_class(u8 guc_class)
{
+ BUILD_BUG_ON(GUC_COMPUTE_CLASS != OTHER_CLASS);
+ BUILD_BUG_ON(GUC_LAST_ENGINE_CLASS != (MAX_ENGINE_CLASS - 1));
GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS);
- GEM_BUG_ON(guc_class == GUC_RESERVED_CLASS);
- return guc_class;
+ return guc_class < GUC_COMPUTE_CLASS ? guc_class : guc_class + 1;
}
/* Work item for submitting workloads into work queue of GuC. */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2853cc005ee..33d6aa0b07c1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2528,6 +2528,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN11_VEBOX2_RING_BASE 0x1d8000
#define XEHP_VEBOX3_RING_BASE 0x1e8000
#define XEHP_VEBOX4_RING_BASE 0x1f8000
+#define GEN12_COMPUTE0_RING_BASE 0x1a000
+#define GEN12_COMPUTE1_RING_BASE 0x1c000
+#define GEN12_COMPUTE2_RING_BASE 0x1e000
+#define GEN12_COMPUTE3_RING_BASE 0x26000
#define BLT_RING_BASE 0x22000
#define RING_TAIL(base) _MMIO((base) + 0x30)
#define RING_HEAD(base) _MMIO((base) + 0x34)
@@ -8100,6 +8104,10 @@ enum {
#define GEN11_KCR (19)
#define GEN11_GTPM (16)
#define GEN11_BCS (15)
+#define GEN12_CCS3 (7)
+#define GEN12_CCS2 (6)
+#define GEN12_CCS1 (5)
+#define GEN12_CCS0 (4)
#define GEN11_RCS0 (0)
#define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index bde5860b3686..9540f33523d8 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -166,6 +166,7 @@ enum drm_i915_gem_engine_class {
I915_ENGINE_CLASS_COPY = 1,
I915_ENGINE_CLASS_VIDEO = 2,
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
+ I915_ENGINE_CLASS_COMPUTE = 4,
/* should be kept compact */
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 1/8] drm/i915/xehp: Define compute class and engine
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
@ 2021-09-08 9:46 ` Tvrtko Ursulin
-1 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 9:46 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: dri-devel, Daniele Ceraolo Spurio, Vinay Belgaumkar,
Szymon Morek, Rodrigo Vivi, Aravind Iddamsetty
On 07/09/2021 18:19, Matt Roper wrote:
> Introduce a Compute Command Streamer (CCS), which has access to
> the media and GPGPU pipelines (but not the 3D pipeline).
>
> To begin with, define the compute class/engine common functions, based
> on the existing render ones.
>
> Bspec: 46167, 45544
> Original-patch-by: Michel Thierry
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Szymon Morek <szymon.morek@intel.com>
> UMD (compute): https://github.com/intel/compute-runtime/pull/451
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 28 ++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 ++++++-
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 +++-
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 13 +++++----
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++
> include/uapi/drm/i915_drm.h | 1 +
> 6 files changed, 57 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 332efea696a5..69944bd8c19d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -153,6 +153,34 @@ static const struct engine_info intel_engines[] = {
> { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
> },
> },
> + [CCS0] = {
> + .class = COMPUTE_CLASS,
> + .instance = 0,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
> + }
> + },
> + [CCS1] = {
> + .class = COMPUTE_CLASS,
> + .instance = 1,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
> + }
> + },
> + [CCS2] = {
> + .class = COMPUTE_CLASS,
> + .instance = 2,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
> + }
> + },
> + [CCS3] = {
> + .class = COMPUTE_CLASS,
> + .instance = 3,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
> + }
> + },
> };
>
> /**
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index bfbfe53c23dd..dcb9d8b2362a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -33,7 +33,8 @@
> #define VIDEO_ENHANCEMENT_CLASS 2
> #define COPY_ENGINE_CLASS 3
> #define OTHER_CLASS 4
> -#define MAX_ENGINE_CLASS 4
> +#define COMPUTE_CLASS 5
> +#define MAX_ENGINE_CLASS 5
> #define MAX_ENGINE_INSTANCE 7
>
> #define I915_MAX_SLICES 3
> @@ -95,6 +96,7 @@ struct i915_ctx_workarounds {
>
> #define I915_MAX_VCS 8
> #define I915_MAX_VECS 4
> +#define I915_MAX_CCS 4
>
> /*
> * Engine IDs definitions.
> @@ -117,6 +119,11 @@ enum intel_engine_id {
> VECS2,
> VECS3,
> #define _VECS(n) (VECS0 + (n))
> + CCS0,
> + CCS1,
> + CCS2,
> + CCS3,
> +#define _CCS(n) (CCS0 + (n))
> I915_NUM_ENGINES
> #define INVALID_ENGINE ((enum intel_engine_id)-1)
> };
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 8f8bea08e734..d981621a7c30 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -47,6 +47,7 @@ static const u8 uabi_classes[] = {
> [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
> [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
> [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
> + [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
> };
>
> static int engine_cmp(void *priv, const struct list_head *A,
> @@ -139,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
> [COPY_ENGINE_CLASS] = "bcs",
> [VIDEO_DECODE_CLASS] = "vcs",
> [VIDEO_ENHANCEMENT_CLASS] = "vecs",
> + [COMPUTE_CLASS] = "ccs",
> };
>
> if (class >= ARRAY_SIZE(uabi_names) || !uabi_names[class])
> @@ -162,6 +164,7 @@ static int legacy_ring_idx(const struct legacy_ring *ring)
> [COPY_ENGINE_CLASS] = { BCS0, 1 },
> [VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS },
> [VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS },
> + [COMPUTE_CLASS] = { CCS0, I915_MAX_CCS },
> };
>
> if (GEM_DEBUG_WARN_ON(ring->class >= ARRAY_SIZE(map)))
> @@ -190,7 +193,7 @@ static void add_legacy_ring(struct legacy_ring *ring,
> void intel_engines_driver_register(struct drm_i915_private *i915)
> {
> struct legacy_ring ring = {};
> - u8 uabi_instances[4] = {};
> + u8 uabi_instances[5] = {};
> struct list_head *it, *next;
> struct rb_node **p, *prev;
> LIST_HEAD(engines);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index fa4be13c8854..3f9007e4e895 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -45,8 +45,8 @@
> #define GUC_VIDEO_CLASS 1
> #define GUC_VIDEOENHANCE_CLASS 2
> #define GUC_BLITTER_CLASS 3
> -#define GUC_RESERVED_CLASS 4
> -#define GUC_LAST_ENGINE_CLASS GUC_RESERVED_CLASS
> +#define GUC_COMPUTE_CLASS 4
> +#define GUC_LAST_ENGINE_CLASS GUC_COMPUTE_CLASS
> #define GUC_MAX_ENGINE_CLASSES 16
> #define GUC_MAX_INSTANCES_PER_CLASS 32
>
> @@ -154,17 +154,20 @@ static inline u8 engine_class_to_guc_class(u8 class)
> BUILD_BUG_ON(GUC_BLITTER_CLASS != COPY_ENGINE_CLASS);
> BUILD_BUG_ON(GUC_VIDEO_CLASS != VIDEO_DECODE_CLASS);
> BUILD_BUG_ON(GUC_VIDEOENHANCE_CLASS != VIDEO_ENHANCEMENT_CLASS);
> + BUILD_BUG_ON(GUC_COMPUTE_CLASS != (COMPUTE_CLASS - 1));
> GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
>
> - return class;
> + /* the GuC arrays don't include OTHER_CLASS */
> + return class < OTHER_CLASS ? class : class - 1;
> }
>
> static inline u8 guc_class_to_engine_class(u8 guc_class)
> {
> + BUILD_BUG_ON(GUC_COMPUTE_CLASS != OTHER_CLASS);
In engine_class_to_guc_class we have:
BUILD_BUG_ON(GUC_COMPUTE_CLASS != (COMPUTE_CLASS - 1));
Maybe there's a reason why two "flavours" are used, like to convey
something semantically? (I know the value is the same, it's just a bit
confusing.)
Overall I would perhaps consider tables for both transformations. Not
because of runtime concerns since neither seem on a hot path, but to
avoid a "table" (of sorts) expressed with BUILD_BUG_ONs, followed by
transform functions. Table would simply express both in one block.
> + BUILD_BUG_ON(GUC_LAST_ENGINE_CLASS != (MAX_ENGINE_CLASS - 1));
> GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS);
> - GEM_BUG_ON(guc_class == GUC_RESERVED_CLASS);
>
> - return guc_class;
> + return guc_class < GUC_COMPUTE_CLASS ? guc_class : guc_class + 1;
> }
>
> /* Work item for submitting workloads into work queue of GuC. */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c2853cc005ee..33d6aa0b07c1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2528,6 +2528,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN11_VEBOX2_RING_BASE 0x1d8000
> #define XEHP_VEBOX3_RING_BASE 0x1e8000
> #define XEHP_VEBOX4_RING_BASE 0x1f8000
> +#define GEN12_COMPUTE0_RING_BASE 0x1a000
> +#define GEN12_COMPUTE1_RING_BASE 0x1c000
> +#define GEN12_COMPUTE2_RING_BASE 0x1e000
> +#define GEN12_COMPUTE3_RING_BASE 0x26000
> #define BLT_RING_BASE 0x22000
> #define RING_TAIL(base) _MMIO((base) + 0x30)
> #define RING_HEAD(base) _MMIO((base) + 0x34)
> @@ -8100,6 +8104,10 @@ enum {
> #define GEN11_KCR (19)
> #define GEN11_GTPM (16)
> #define GEN11_BCS (15)
> +#define GEN12_CCS3 (7)
> +#define GEN12_CCS2 (6)
> +#define GEN12_CCS1 (5)
> +#define GEN12_CCS0 (4)
> #define GEN11_RCS0 (0)
>
> #define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index bde5860b3686..9540f33523d8 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -166,6 +166,7 @@ enum drm_i915_gem_engine_class {
> I915_ENGINE_CLASS_COPY = 1,
> I915_ENGINE_CLASS_VIDEO = 2,
> I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
> + I915_ENGINE_CLASS_COMPUTE = 4,
>
> /* should be kept compact */
>
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [Intel-gfx] [PATCH 1/8] drm/i915/xehp: Define compute class and engine
@ 2021-09-08 9:46 ` Tvrtko Ursulin
0 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 9:46 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: dri-devel, Daniele Ceraolo Spurio, Vinay Belgaumkar,
Szymon Morek, Rodrigo Vivi, Aravind Iddamsetty
On 07/09/2021 18:19, Matt Roper wrote:
> Introduce a Compute Command Streamer (CCS), which has access to
> the media and GPGPU pipelines (but not the 3D pipeline).
>
> To begin with, define the compute class/engine common functions, based
> on the existing render ones.
>
> Bspec: 46167, 45544
> Original-patch-by: Michel Thierry
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Szymon Morek <szymon.morek@intel.com>
> UMD (compute): https://github.com/intel/compute-runtime/pull/451
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 28 ++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 ++++++-
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 +++-
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 13 +++++----
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++
> include/uapi/drm/i915_drm.h | 1 +
> 6 files changed, 57 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 332efea696a5..69944bd8c19d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -153,6 +153,34 @@ static const struct engine_info intel_engines[] = {
> { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
> },
> },
> + [CCS0] = {
> + .class = COMPUTE_CLASS,
> + .instance = 0,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
> + }
> + },
> + [CCS1] = {
> + .class = COMPUTE_CLASS,
> + .instance = 1,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
> + }
> + },
> + [CCS2] = {
> + .class = COMPUTE_CLASS,
> + .instance = 2,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
> + }
> + },
> + [CCS3] = {
> + .class = COMPUTE_CLASS,
> + .instance = 3,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
> + }
> + },
> };
>
> /**
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index bfbfe53c23dd..dcb9d8b2362a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -33,7 +33,8 @@
> #define VIDEO_ENHANCEMENT_CLASS 2
> #define COPY_ENGINE_CLASS 3
> #define OTHER_CLASS 4
> -#define MAX_ENGINE_CLASS 4
> +#define COMPUTE_CLASS 5
> +#define MAX_ENGINE_CLASS 5
> #define MAX_ENGINE_INSTANCE 7
>
> #define I915_MAX_SLICES 3
> @@ -95,6 +96,7 @@ struct i915_ctx_workarounds {
>
> #define I915_MAX_VCS 8
> #define I915_MAX_VECS 4
> +#define I915_MAX_CCS 4
>
> /*
> * Engine IDs definitions.
> @@ -117,6 +119,11 @@ enum intel_engine_id {
> VECS2,
> VECS3,
> #define _VECS(n) (VECS0 + (n))
> + CCS0,
> + CCS1,
> + CCS2,
> + CCS3,
> +#define _CCS(n) (CCS0 + (n))
> I915_NUM_ENGINES
> #define INVALID_ENGINE ((enum intel_engine_id)-1)
> };
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 8f8bea08e734..d981621a7c30 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -47,6 +47,7 @@ static const u8 uabi_classes[] = {
> [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
> [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
> [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
> + [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
> };
>
> static int engine_cmp(void *priv, const struct list_head *A,
> @@ -139,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
> [COPY_ENGINE_CLASS] = "bcs",
> [VIDEO_DECODE_CLASS] = "vcs",
> [VIDEO_ENHANCEMENT_CLASS] = "vecs",
> + [COMPUTE_CLASS] = "ccs",
> };
>
> if (class >= ARRAY_SIZE(uabi_names) || !uabi_names[class])
> @@ -162,6 +164,7 @@ static int legacy_ring_idx(const struct legacy_ring *ring)
> [COPY_ENGINE_CLASS] = { BCS0, 1 },
> [VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS },
> [VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS },
> + [COMPUTE_CLASS] = { CCS0, I915_MAX_CCS },
> };
>
> if (GEM_DEBUG_WARN_ON(ring->class >= ARRAY_SIZE(map)))
> @@ -190,7 +193,7 @@ static void add_legacy_ring(struct legacy_ring *ring,
> void intel_engines_driver_register(struct drm_i915_private *i915)
> {
> struct legacy_ring ring = {};
> - u8 uabi_instances[4] = {};
> + u8 uabi_instances[5] = {};
> struct list_head *it, *next;
> struct rb_node **p, *prev;
> LIST_HEAD(engines);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index fa4be13c8854..3f9007e4e895 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -45,8 +45,8 @@
> #define GUC_VIDEO_CLASS 1
> #define GUC_VIDEOENHANCE_CLASS 2
> #define GUC_BLITTER_CLASS 3
> -#define GUC_RESERVED_CLASS 4
> -#define GUC_LAST_ENGINE_CLASS GUC_RESERVED_CLASS
> +#define GUC_COMPUTE_CLASS 4
> +#define GUC_LAST_ENGINE_CLASS GUC_COMPUTE_CLASS
> #define GUC_MAX_ENGINE_CLASSES 16
> #define GUC_MAX_INSTANCES_PER_CLASS 32
>
> @@ -154,17 +154,20 @@ static inline u8 engine_class_to_guc_class(u8 class)
> BUILD_BUG_ON(GUC_BLITTER_CLASS != COPY_ENGINE_CLASS);
> BUILD_BUG_ON(GUC_VIDEO_CLASS != VIDEO_DECODE_CLASS);
> BUILD_BUG_ON(GUC_VIDEOENHANCE_CLASS != VIDEO_ENHANCEMENT_CLASS);
> + BUILD_BUG_ON(GUC_COMPUTE_CLASS != (COMPUTE_CLASS - 1));
> GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
>
> - return class;
> + /* the GuC arrays don't include OTHER_CLASS */
> + return class < OTHER_CLASS ? class : class - 1;
> }
>
> static inline u8 guc_class_to_engine_class(u8 guc_class)
> {
> + BUILD_BUG_ON(GUC_COMPUTE_CLASS != OTHER_CLASS);
In engine_class_to_guc_class we have:
BUILD_BUG_ON(GUC_COMPUTE_CLASS != (COMPUTE_CLASS - 1));
Maybe there's a reason why two "flavours" are used, like to convey
something semantically? (I know the value is the same, it's just a bit
confusing.)
Overall I would perhaps consider tables for both transformations. Not
because of runtime concerns since neither seem on a hot path, but to
avoid a "table" (of sorts) expressed with BUILD_BUG_ONs, followed by
transform functions. Table would simply express both in one block.
> + BUILD_BUG_ON(GUC_LAST_ENGINE_CLASS != (MAX_ENGINE_CLASS - 1));
> GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS);
> - GEM_BUG_ON(guc_class == GUC_RESERVED_CLASS);
>
> - return guc_class;
> + return guc_class < GUC_COMPUTE_CLASS ? guc_class : guc_class + 1;
> }
>
> /* Work item for submitting workloads into work queue of GuC. */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c2853cc005ee..33d6aa0b07c1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2528,6 +2528,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN11_VEBOX2_RING_BASE 0x1d8000
> #define XEHP_VEBOX3_RING_BASE 0x1e8000
> #define XEHP_VEBOX4_RING_BASE 0x1f8000
> +#define GEN12_COMPUTE0_RING_BASE 0x1a000
> +#define GEN12_COMPUTE1_RING_BASE 0x1c000
> +#define GEN12_COMPUTE2_RING_BASE 0x1e000
> +#define GEN12_COMPUTE3_RING_BASE 0x26000
> #define BLT_RING_BASE 0x22000
> #define RING_TAIL(base) _MMIO((base) + 0x30)
> #define RING_HEAD(base) _MMIO((base) + 0x34)
> @@ -8100,6 +8104,10 @@ enum {
> #define GEN11_KCR (19)
> #define GEN11_GTPM (16)
> #define GEN11_BCS (15)
> +#define GEN12_CCS3 (7)
> +#define GEN12_CCS2 (6)
> +#define GEN12_CCS1 (5)
> +#define GEN12_CCS0 (4)
> #define GEN11_RCS0 (0)
>
> #define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index bde5860b3686..9540f33523d8 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -166,6 +166,7 @@ enum drm_i915_gem_engine_class {
> I915_ENGINE_CLASS_COPY = 1,
> I915_ENGINE_CLASS_VIDEO = 2,
> I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
> + I915_ENGINE_CLASS_COMPUTE = 4,
>
> /* should be kept compact */
>
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH 1/8] drm/i915/xehp: Define compute class and engine
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
(?)
(?)
@ 2021-09-08 16:42 ` Daniel Vetter
-1 siblings, 0 replies; 43+ messages in thread
From: Daniel Vetter @ 2021-09-08 16:42 UTC (permalink / raw)
To: Matt Roper
Cc: intel-gfx, dri-devel, Daniele Ceraolo Spurio, Tvrtko Ursulin,
Vinay Belgaumkar, Szymon Morek, Rodrigo Vivi, Aravind Iddamsetty
On Tue, Sep 07, 2021 at 10:19:09AM -0700, Matt Roper wrote:
> Introduce a Compute Command Streamer (CCS), which has access to
> the media and GPGPU pipelines (but not the 3D pipeline).
>
> To begin with, define the compute class/engine common functions, based
> on the existing render ones.
>
> Bspec: 46167, 45544
> Original-patch-by: Michel Thierry
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Szymon Morek <szymon.morek@intel.com>
> UMD (compute): https://github.com/intel/compute-runtime/pull/451
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 28 ++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 ++++++-
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 +++-
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 13 +++++----
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++
> include/uapi/drm/i915_drm.h | 1 +
> 6 files changed, 57 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 332efea696a5..69944bd8c19d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -153,6 +153,34 @@ static const struct engine_info intel_engines[] = {
> { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
> },
> },
> + [CCS0] = {
> + .class = COMPUTE_CLASS,
> + .instance = 0,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
> + }
> + },
> + [CCS1] = {
> + .class = COMPUTE_CLASS,
> + .instance = 1,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
> + }
> + },
> + [CCS2] = {
> + .class = COMPUTE_CLASS,
> + .instance = 2,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
> + }
> + },
> + [CCS3] = {
> + .class = COMPUTE_CLASS,
> + .instance = 3,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
> + }
> + },
> };
>
> /**
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index bfbfe53c23dd..dcb9d8b2362a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -33,7 +33,8 @@
> #define VIDEO_ENHANCEMENT_CLASS 2
> #define COPY_ENGINE_CLASS 3
> #define OTHER_CLASS 4
> -#define MAX_ENGINE_CLASS 4
> +#define COMPUTE_CLASS 5
> +#define MAX_ENGINE_CLASS 5
> #define MAX_ENGINE_INSTANCE 7
>
> #define I915_MAX_SLICES 3
> @@ -95,6 +96,7 @@ struct i915_ctx_workarounds {
>
> #define I915_MAX_VCS 8
> #define I915_MAX_VECS 4
> +#define I915_MAX_CCS 4
>
> /*
> * Engine IDs definitions.
> @@ -117,6 +119,11 @@ enum intel_engine_id {
> VECS2,
> VECS3,
> #define _VECS(n) (VECS0 + (n))
> + CCS0,
> + CCS1,
> + CCS2,
> + CCS3,
> +#define _CCS(n) (CCS0 + (n))
> I915_NUM_ENGINES
> #define INVALID_ENGINE ((enum intel_engine_id)-1)
> };
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 8f8bea08e734..d981621a7c30 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -47,6 +47,7 @@ static const u8 uabi_classes[] = {
> [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
> [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
> [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
> + [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
> };
>
> static int engine_cmp(void *priv, const struct list_head *A,
> @@ -139,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
> [COPY_ENGINE_CLASS] = "bcs",
> [VIDEO_DECODE_CLASS] = "vcs",
> [VIDEO_ENHANCEMENT_CLASS] = "vecs",
> + [COMPUTE_CLASS] = "ccs",
> };
>
> if (class >= ARRAY_SIZE(uabi_names) || !uabi_names[class])
> @@ -162,6 +164,7 @@ static int legacy_ring_idx(const struct legacy_ring *ring)
> [COPY_ENGINE_CLASS] = { BCS0, 1 },
> [VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS },
> [VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS },
> + [COMPUTE_CLASS] = { CCS0, I915_MAX_CCS },
> };
>
> if (GEM_DEBUG_WARN_ON(ring->class >= ARRAY_SIZE(map)))
> @@ -190,7 +193,7 @@ static void add_legacy_ring(struct legacy_ring *ring,
> void intel_engines_driver_register(struct drm_i915_private *i915)
> {
> struct legacy_ring ring = {};
> - u8 uabi_instances[4] = {};
> + u8 uabi_instances[5] = {};
> struct list_head *it, *next;
> struct rb_node **p, *prev;
> LIST_HEAD(engines);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index fa4be13c8854..3f9007e4e895 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -45,8 +45,8 @@
> #define GUC_VIDEO_CLASS 1
> #define GUC_VIDEOENHANCE_CLASS 2
> #define GUC_BLITTER_CLASS 3
> -#define GUC_RESERVED_CLASS 4
> -#define GUC_LAST_ENGINE_CLASS GUC_RESERVED_CLASS
> +#define GUC_COMPUTE_CLASS 4
> +#define GUC_LAST_ENGINE_CLASS GUC_COMPUTE_CLASS
> #define GUC_MAX_ENGINE_CLASSES 16
> #define GUC_MAX_INSTANCES_PER_CLASS 32
>
> @@ -154,17 +154,20 @@ static inline u8 engine_class_to_guc_class(u8 class)
> BUILD_BUG_ON(GUC_BLITTER_CLASS != COPY_ENGINE_CLASS);
> BUILD_BUG_ON(GUC_VIDEO_CLASS != VIDEO_DECODE_CLASS);
> BUILD_BUG_ON(GUC_VIDEOENHANCE_CLASS != VIDEO_ENHANCEMENT_CLASS);
> + BUILD_BUG_ON(GUC_COMPUTE_CLASS != (COMPUTE_CLASS - 1));
> GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
>
> - return class;
> + /* the GuC arrays don't include OTHER_CLASS */
> + return class < OTHER_CLASS ? class : class - 1;
> }
>
> static inline u8 guc_class_to_engine_class(u8 guc_class)
> {
> + BUILD_BUG_ON(GUC_COMPUTE_CLASS != OTHER_CLASS);
> + BUILD_BUG_ON(GUC_LAST_ENGINE_CLASS != (MAX_ENGINE_CLASS - 1));
> GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS);
> - GEM_BUG_ON(guc_class == GUC_RESERVED_CLASS);
>
> - return guc_class;
> + return guc_class < GUC_COMPUTE_CLASS ? guc_class : guc_class + 1;
> }
>
> /* Work item for submitting workloads into work queue of GuC. */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c2853cc005ee..33d6aa0b07c1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2528,6 +2528,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN11_VEBOX2_RING_BASE 0x1d8000
> #define XEHP_VEBOX3_RING_BASE 0x1e8000
> #define XEHP_VEBOX4_RING_BASE 0x1f8000
> +#define GEN12_COMPUTE0_RING_BASE 0x1a000
> +#define GEN12_COMPUTE1_RING_BASE 0x1c000
> +#define GEN12_COMPUTE2_RING_BASE 0x1e000
> +#define GEN12_COMPUTE3_RING_BASE 0x26000
> #define BLT_RING_BASE 0x22000
> #define RING_TAIL(base) _MMIO((base) + 0x30)
> #define RING_HEAD(base) _MMIO((base) + 0x34)
> @@ -8100,6 +8104,10 @@ enum {
> #define GEN11_KCR (19)
> #define GEN11_GTPM (16)
> #define GEN11_BCS (15)
> +#define GEN12_CCS3 (7)
> +#define GEN12_CCS2 (6)
> +#define GEN12_CCS1 (5)
> +#define GEN12_CCS0 (4)
> #define GEN11_RCS0 (0)
>
> #define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index bde5860b3686..9540f33523d8 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -166,6 +166,7 @@ enum drm_i915_gem_engine_class {
Please add kerneldoc for any updated/new uapi.
-Daniel
> I915_ENGINE_CLASS_COPY = 1,
> I915_ENGINE_CLASS_VIDEO = 2,
> I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
> + I915_ENGINE_CLASS_COMPUTE = 4,
>
> /* should be kept compact */
>
> --
> 2.25.4
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
@ 2021-09-07 17:19 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Matt Roper, Tvrtko Ursulin, Vinay Belgaumkar,
Daniele Ceraolo Spurio, Aravind Iddamsetty
The reset domain is shared between render and all compute engines,
so resetting one will affect the others.
Note: Before performing a reset on an RCS or CCS engine, the GuC will
attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
impacting other clients (since some shared modules will be reset). If
other engines are executing non-preemptable workloads, the impact is
unavoidable and some work may be lost.
Bspec: 52549
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 91200c43951f..30598c1d070c 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt,
[VECS1] = GEN11_GRDOM_VECS2,
[VECS2] = GEN11_GRDOM_VECS3,
[VECS3] = GEN11_GRDOM_VECS4,
+ [CCS0] = GEN11_GRDOM_RENDER,
+ [CCS1] = GEN11_GRDOM_RENDER,
+ [CCS2] = GEN11_GRDOM_RENDER,
+ [CCS3] = GEN11_GRDOM_RENDER,
};
struct intel_engine_cs *engine;
intel_engine_mask_t tmp;
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain
@ 2021-09-07 17:19 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Matt Roper, Tvrtko Ursulin, Vinay Belgaumkar,
Daniele Ceraolo Spurio, Aravind Iddamsetty
The reset domain is shared between render and all compute engines,
so resetting one will affect the others.
Note: Before performing a reset on an RCS or CCS engine, the GuC will
attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
impacting other clients (since some shared modules will be reset). If
other engines are executing non-preemptable workloads, the impact is
unavoidable and some work may be lost.
Bspec: 52549
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 91200c43951f..30598c1d070c 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt,
[VECS1] = GEN11_GRDOM_VECS2,
[VECS2] = GEN11_GRDOM_VECS3,
[VECS3] = GEN11_GRDOM_VECS4,
+ [CCS0] = GEN11_GRDOM_RENDER,
+ [CCS1] = GEN11_GRDOM_RENDER,
+ [CCS2] = GEN11_GRDOM_RENDER,
+ [CCS3] = GEN11_GRDOM_RENDER,
};
struct intel_engine_cs *engine;
intel_engine_mask_t tmp;
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
@ 2021-09-08 10:07 ` Tvrtko Ursulin
-1 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 10:07 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: dri-devel, Vinay Belgaumkar, Daniele Ceraolo Spurio, Aravind Iddamsetty
On 07/09/2021 18:19, Matt Roper wrote:
> The reset domain is shared between render and all compute engines,
> so resetting one will affect the others.
>
> Note: Before performing a reset on an RCS or CCS engine, the GuC will
> attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
> impacting other clients (since some shared modules will be reset). If
> other engines are executing non-preemptable workloads, the impact is
> unavoidable and some work may be lost.
Since here it talks about engine reset, should this patch add warning if
same is attempted by i915 on a GuC platform - to document it is not
implemented/supported? Or perhaps later in the series, or future series
works better.
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
> Bspec: 52549
> Original-patch-by: Michel Thierry
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 91200c43951f..30598c1d070c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt,
> [VECS1] = GEN11_GRDOM_VECS2,
> [VECS2] = GEN11_GRDOM_VECS3,
> [VECS3] = GEN11_GRDOM_VECS4,
> + [CCS0] = GEN11_GRDOM_RENDER,
> + [CCS1] = GEN11_GRDOM_RENDER,
> + [CCS2] = GEN11_GRDOM_RENDER,
> + [CCS3] = GEN11_GRDOM_RENDER,
> };
> struct intel_engine_cs *engine;
> intel_engine_mask_t tmp;
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain
@ 2021-09-08 10:07 ` Tvrtko Ursulin
0 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 10:07 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: dri-devel, Vinay Belgaumkar, Daniele Ceraolo Spurio, Aravind Iddamsetty
On 07/09/2021 18:19, Matt Roper wrote:
> The reset domain is shared between render and all compute engines,
> so resetting one will affect the others.
>
> Note: Before performing a reset on an RCS or CCS engine, the GuC will
> attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
> impacting other clients (since some shared modules will be reset). If
> other engines are executing non-preemptable workloads, the impact is
> unavoidable and some work may be lost.
Since here it talks about engine reset, should this patch add warning if
same is attempted by i915 on a GuC platform - to document it is not
implemented/supported? Or perhaps later in the series, or future series
works better.
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
> Bspec: 52549
> Original-patch-by: Michel Thierry
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 91200c43951f..30598c1d070c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt,
> [VECS1] = GEN11_GRDOM_VECS2,
> [VECS2] = GEN11_GRDOM_VECS3,
> [VECS3] = GEN11_GRDOM_VECS4,
> + [CCS0] = GEN11_GRDOM_RENDER,
> + [CCS1] = GEN11_GRDOM_RENDER,
> + [CCS2] = GEN11_GRDOM_RENDER,
> + [CCS3] = GEN11_GRDOM_RENDER,
> };
> struct intel_engine_cs *engine;
> intel_engine_mask_t tmp;
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain
2021-09-08 10:07 ` [Intel-gfx] " Tvrtko Ursulin
@ 2021-09-08 20:23 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-08 20:23 UTC (permalink / raw)
To: Tvrtko Ursulin
Cc: intel-gfx, dri-devel, Vinay Belgaumkar, Daniele Ceraolo Spurio,
Aravind Iddamsetty
On Wed, Sep 08, 2021 at 11:07:07AM +0100, Tvrtko Ursulin wrote:
>
> On 07/09/2021 18:19, Matt Roper wrote:
> > The reset domain is shared between render and all compute engines,
> > so resetting one will affect the others.
> >
> > Note: Before performing a reset on an RCS or CCS engine, the GuC will
> > attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
> > impacting other clients (since some shared modules will be reset). If
> > other engines are executing non-preemptable workloads, the impact is
> > unavoidable and some work may be lost.
>
> Since here it talks about engine reset, should this patch add warning if
> same is attempted by i915 on a GuC platform - to document it is not
Did you mean "on a *non* GuC platform" here? We aren't going to have
compute engine support on any platforms where GuC submission isn't the
default operating model, so the only way to get compute engines +
execlist submission is to force an override via module parameters (e.g.,
enable_guc=0). Doing so will taint the kernel, so I think the current
consensus from offline discussion is that the user has already put
themselves into a configuration where it's easier than usual to shoot
themselves in the foot; it's not too much different than the kind of
trouble a user could get themselves into if they loaded the driver with
hangcheck disabled or something.
Matt
> implemented/supported? Or perhaps later in the series, or future series
> works better.
>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Regards,
>
> Tvrtko
>
> > Bspec: 52549
> > Original-patch-by: Michel Thierry
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> > index 91200c43951f..30598c1d070c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > @@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt,
> > [VECS1] = GEN11_GRDOM_VECS2,
> > [VECS2] = GEN11_GRDOM_VECS3,
> > [VECS3] = GEN11_GRDOM_VECS4,
> > + [CCS0] = GEN11_GRDOM_RENDER,
> > + [CCS1] = GEN11_GRDOM_RENDER,
> > + [CCS2] = GEN11_GRDOM_RENDER,
> > + [CCS3] = GEN11_GRDOM_RENDER,
> > };
> > struct intel_engine_cs *engine;
> > intel_engine_mask_t tmp;
> >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain
@ 2021-09-08 20:23 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-08 20:23 UTC (permalink / raw)
To: Tvrtko Ursulin
Cc: intel-gfx, dri-devel, Vinay Belgaumkar, Daniele Ceraolo Spurio,
Aravind Iddamsetty
On Wed, Sep 08, 2021 at 11:07:07AM +0100, Tvrtko Ursulin wrote:
>
> On 07/09/2021 18:19, Matt Roper wrote:
> > The reset domain is shared between render and all compute engines,
> > so resetting one will affect the others.
> >
> > Note: Before performing a reset on an RCS or CCS engine, the GuC will
> > attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
> > impacting other clients (since some shared modules will be reset). If
> > other engines are executing non-preemptable workloads, the impact is
> > unavoidable and some work may be lost.
>
> Since here it talks about engine reset, should this patch add warning if
> same is attempted by i915 on a GuC platform - to document it is not
Did you mean "on a *non* GuC platform" here? We aren't going to have
compute engine support on any platforms where GuC submission isn't the
default operating model, so the only way to get compute engines +
execlist submission is to force an override via module parameters (e.g.,
enable_guc=0). Doing so will taint the kernel, so I think the current
consensus from offline discussion is that the user has already put
themselves into a configuration where it's easier than usual to shoot
themselves in the foot; it's not too much different than the kind of
trouble a user could get themselves into if they loaded the driver with
hangcheck disabled or something.
Matt
> implemented/supported? Or perhaps later in the series, or future series
> works better.
>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Regards,
>
> Tvrtko
>
> > Bspec: 52549
> > Original-patch-by: Michel Thierry
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> > index 91200c43951f..30598c1d070c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > @@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt,
> > [VECS1] = GEN11_GRDOM_VECS2,
> > [VECS2] = GEN11_GRDOM_VECS3,
> > [VECS3] = GEN11_GRDOM_VECS4,
> > + [CCS0] = GEN11_GRDOM_RENDER,
> > + [CCS1] = GEN11_GRDOM_RENDER,
> > + [CCS2] = GEN11_GRDOM_RENDER,
> > + [CCS3] = GEN11_GRDOM_RENDER,
> > };
> > struct intel_engine_cs *engine;
> > intel_engine_mask_t tmp;
> >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain
2021-09-08 20:23 ` [Intel-gfx] " Matt Roper
@ 2021-09-09 8:11 ` Tvrtko Ursulin
-1 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-09 8:11 UTC (permalink / raw)
To: Matt Roper
Cc: intel-gfx, dri-devel, Vinay Belgaumkar, Daniele Ceraolo Spurio,
Aravind Iddamsetty
On 08/09/2021 21:23, Matt Roper wrote:
> On Wed, Sep 08, 2021 at 11:07:07AM +0100, Tvrtko Ursulin wrote:
>>
>> On 07/09/2021 18:19, Matt Roper wrote:
>>> The reset domain is shared between render and all compute engines,
>>> so resetting one will affect the others.
>>>
>>> Note: Before performing a reset on an RCS or CCS engine, the GuC will
>>> attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
>>> impacting other clients (since some shared modules will be reset). If
>>> other engines are executing non-preemptable workloads, the impact is
>>> unavoidable and some work may be lost.
>>
>> Since here it talks about engine reset, should this patch add warning if
>> same is attempted by i915 on a GuC platform - to document it is not
>
> Did you mean "on a *non* GuC platform" here? We aren't going to have
> compute engine support on any platforms where GuC submission isn't the
> default operating model, so the only way to get compute engines +
> execlist submission is to force an override via module parameters (e.g.,
> enable_guc=0). Doing so will taint the kernel, so I think the current
> consensus from offline discussion is that the user has already put
> themselves into a configuration where it's easier than usual to shoot
> themselves in the foot; it's not too much different than the kind of
> trouble a user could get themselves into if they loaded the driver with
> hangcheck disabled or something.
Yes I meant non GuC. :)
Okay..ish, although I think an explicit warn would still be better.
Because it is one thing to taint and another to actively allow something
which we know cannot work.
Unless we could hide the CCS engine until GuC gets loaded, which would
make i915.enable_guc=0 safe. Hm.. should be doable actually to skip
intel_engine_add_user in the engine init phase and do the CCS ones after
GuC has been loaded. Would that make sense?
Regards,
Tvrtko
>> implemented/supported? Or perhaps later in the series, or future series
>> works better.
>>
>> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Regards,
>>
>> Tvrtko
>>
>>> Bspec: 52549
>>> Original-patch-by: Michel Thierry
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>>> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++++
>>> 1 file changed, 4 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
>>> index 91200c43951f..30598c1d070c 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>>> @@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt,
>>> [VECS1] = GEN11_GRDOM_VECS2,
>>> [VECS2] = GEN11_GRDOM_VECS3,
>>> [VECS3] = GEN11_GRDOM_VECS4,
>>> + [CCS0] = GEN11_GRDOM_RENDER,
>>> + [CCS1] = GEN11_GRDOM_RENDER,
>>> + [CCS2] = GEN11_GRDOM_RENDER,
>>> + [CCS3] = GEN11_GRDOM_RENDER,
>>> };
>>> struct intel_engine_cs *engine;
>>> intel_engine_mask_t tmp;
>>>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain
@ 2021-09-09 8:11 ` Tvrtko Ursulin
0 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-09 8:11 UTC (permalink / raw)
To: Matt Roper
Cc: intel-gfx, dri-devel, Vinay Belgaumkar, Daniele Ceraolo Spurio,
Aravind Iddamsetty
On 08/09/2021 21:23, Matt Roper wrote:
> On Wed, Sep 08, 2021 at 11:07:07AM +0100, Tvrtko Ursulin wrote:
>>
>> On 07/09/2021 18:19, Matt Roper wrote:
>>> The reset domain is shared between render and all compute engines,
>>> so resetting one will affect the others.
>>>
>>> Note: Before performing a reset on an RCS or CCS engine, the GuC will
>>> attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
>>> impacting other clients (since some shared modules will be reset). If
>>> other engines are executing non-preemptable workloads, the impact is
>>> unavoidable and some work may be lost.
>>
>> Since here it talks about engine reset, should this patch add warning if
>> same is attempted by i915 on a GuC platform - to document it is not
>
> Did you mean "on a *non* GuC platform" here? We aren't going to have
> compute engine support on any platforms where GuC submission isn't the
> default operating model, so the only way to get compute engines +
> execlist submission is to force an override via module parameters (e.g.,
> enable_guc=0). Doing so will taint the kernel, so I think the current
> consensus from offline discussion is that the user has already put
> themselves into a configuration where it's easier than usual to shoot
> themselves in the foot; it's not too much different than the kind of
> trouble a user could get themselves into if they loaded the driver with
> hangcheck disabled or something.
Yes I meant non GuC. :)
Okay..ish, although I think an explicit warn would still be better.
Because it is one thing to taint and another to actively allow something
which we know cannot work.
Unless we could hide the CCS engine until GuC gets loaded, which would
make i915.enable_guc=0 safe. Hm.. should be doable actually to skip
intel_engine_add_user in the engine init phase and do the CCS ones after
GuC has been loaded. Would that make sense?
Regards,
Tvrtko
>> implemented/supported? Or perhaps later in the series, or future series
>> works better.
>>
>> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Regards,
>>
>> Tvrtko
>>
>>> Bspec: 52549
>>> Original-patch-by: Michel Thierry
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>>> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++++
>>> 1 file changed, 4 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
>>> index 91200c43951f..30598c1d070c 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>>> @@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt,
>>> [VECS1] = GEN11_GRDOM_VECS2,
>>> [VECS2] = GEN11_GRDOM_VECS3,
>>> [VECS3] = GEN11_GRDOM_VECS4,
>>> + [CCS0] = GEN11_GRDOM_RENDER,
>>> + [CCS1] = GEN11_GRDOM_RENDER,
>>> + [CCS2] = GEN11_GRDOM_RENDER,
>>> + [CCS3] = GEN11_GRDOM_RENDER,
>>> };
>>> struct intel_engine_cs *engine;
>>> intel_engine_mask_t tmp;
>>>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
(?)
(?)
@ 2021-09-08 16:46 ` Daniel Vetter
-1 siblings, 0 replies; 43+ messages in thread
From: Daniel Vetter @ 2021-09-08 16:46 UTC (permalink / raw)
To: Matt Roper
Cc: intel-gfx, dri-devel, Tvrtko Ursulin, Vinay Belgaumkar,
Daniele Ceraolo Spurio, Aravind Iddamsetty
On Tue, Sep 07, 2021 at 10:19:10AM -0700, Matt Roper wrote:
> The reset domain is shared between render and all compute engines,
> so resetting one will affect the others.
>
> Note: Before performing a reset on an RCS or CCS engine, the GuC will
> attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
> impacting other clients (since some shared modules will be reset). If
> other engines are executing non-preemptable workloads, the impact is
> unavoidable and some work may be lost.
>
> Bspec: 52549
> Original-patch-by: Michel Thierry
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Do we have igts validating this all properly?
Specifically that the reset stats are incremented correctly for guilty
respectively victimized contexts.
This is necessary if it doesn't exist yet.
Also you need a patch set here that fixes up the igts which have wrong
assumptions about context isolation.
-Daniel
> ---
> drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 91200c43951f..30598c1d070c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt,
> [VECS1] = GEN11_GRDOM_VECS2,
> [VECS2] = GEN11_GRDOM_VECS3,
> [VECS3] = GEN11_GRDOM_VECS4,
> + [CCS0] = GEN11_GRDOM_RENDER,
> + [CCS1] = GEN11_GRDOM_RENDER,
> + [CCS2] = GEN11_GRDOM_RENDER,
> + [CCS3] = GEN11_GRDOM_RENDER,
> };
> struct intel_engine_cs *engine;
> intel_engine_mask_t tmp;
> --
> 2.25.4
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 3/8] drm/i915/xehp: Add Compute CS IRQ handlers
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
@ 2021-09-07 17:19 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Matt Roper, Tvrtko Ursulin, Vinay Belgaumkar,
Daniele Ceraolo Spurio, Aravind Iddamsetty
Add execlists and GuC interrupts for compute CS into existing IRQ handlers.
All compute command streamers belong to the same compute class, so the
only change needed to enable their interrupts is to program their GT engine
interrupt mask registers.
CCS0 shares the register with CCS1, while CCS2 and CCS3 are in a new one.
BSpec: 50844, 54029, 54030, 53223, 53224.
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 15 ++++++++++++++-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index b2de83be4d97..612281d47513 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -96,7 +96,7 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
if (unlikely(!intr))
return;
- if (class <= COPY_ENGINE_CLASS)
+ if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
return gen11_engine_irq_handler(gt, class, instance, intr);
if (class == OTHER_CLASS)
@@ -178,6 +178,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
/* Disable RCS, BCS, VCS and VECS class engines. */
intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0);
+ if (CCS_MASK(gt))
+ intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0);
@@ -191,6 +193,10 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0);
if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0);
+ if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
+ intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
+ if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
+ intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
@@ -218,6 +224,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
/* Enable RCS, BCS, VCS and VECS class interrupts. */
intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask);
intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
+ if (CCS_MASK(gt))
+ intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
@@ -231,6 +239,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask);
if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask);
+ if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
+ intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
+ if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
+ intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
+
/*
* RPS interrupts will get enabled/disabled on demand when RPS itself
* is enabled/disabled.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1fd3040b6771..5b6eee5d8ade 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1573,6 +1573,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
#define VEBOX_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
+#define CCS_MASK(gt) \
+ ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
/*
* The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 33d6aa0b07c1..31e9c2cc4c0c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8139,6 +8139,7 @@ enum {
#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
#define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
#define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
+#define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048)
#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
@@ -8152,6 +8153,8 @@ enum {
#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
+#define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100)
+#define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104)
#define ENGINE1_MASK REG_GENMASK(31, 16)
#define ENGINE0_MASK REG_GENMASK(15, 0)
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread* [Intel-gfx] [PATCH 3/8] drm/i915/xehp: Add Compute CS IRQ handlers
@ 2021-09-07 17:19 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Matt Roper, Tvrtko Ursulin, Vinay Belgaumkar,
Daniele Ceraolo Spurio, Aravind Iddamsetty
Add execlists and GuC interrupts for compute CS into existing IRQ handlers.
All compute command streamers belong to the same compute class, so the
only change needed to enable their interrupts is to program their GT engine
interrupt mask registers.
CCS0 shares the register with CCS1, while CCS2 and CCS3 are in a new one.
BSpec: 50844, 54029, 54030, 53223, 53224.
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 15 ++++++++++++++-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index b2de83be4d97..612281d47513 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -96,7 +96,7 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
if (unlikely(!intr))
return;
- if (class <= COPY_ENGINE_CLASS)
+ if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
return gen11_engine_irq_handler(gt, class, instance, intr);
if (class == OTHER_CLASS)
@@ -178,6 +178,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
/* Disable RCS, BCS, VCS and VECS class engines. */
intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0);
+ if (CCS_MASK(gt))
+ intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0);
@@ -191,6 +193,10 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0);
if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0);
+ if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
+ intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
+ if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
+ intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
@@ -218,6 +224,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
/* Enable RCS, BCS, VCS and VECS class interrupts. */
intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask);
intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
+ if (CCS_MASK(gt))
+ intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
@@ -231,6 +239,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask);
if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask);
+ if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
+ intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
+ if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
+ intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
+
/*
* RPS interrupts will get enabled/disabled on demand when RPS itself
* is enabled/disabled.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1fd3040b6771..5b6eee5d8ade 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1573,6 +1573,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
#define VEBOX_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
+#define CCS_MASK(gt) \
+ ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
/*
* The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 33d6aa0b07c1..31e9c2cc4c0c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8139,6 +8139,7 @@ enum {
#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
#define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
#define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
+#define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048)
#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
@@ -8152,6 +8153,8 @@ enum {
#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
+#define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100)
+#define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104)
#define ENGINE1_MASK REG_GENMASK(31, 16)
#define ENGINE0_MASK REG_GENMASK(15, 0)
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 3/8] drm/i915/xehp: Add Compute CS IRQ handlers
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
@ 2021-09-08 10:09 ` Tvrtko Ursulin
-1 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 10:09 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: dri-devel, Vinay Belgaumkar, Daniele Ceraolo Spurio, Aravind Iddamsetty
On 07/09/2021 18:19, Matt Roper wrote:
> Add execlists and GuC interrupts for compute CS into existing IRQ handlers.
>
> All compute command streamers belong to the same compute class, so the
> only change needed to enable their interrupts is to program their GT engine
> interrupt mask registers.
>
> CCS0 shares the register with CCS1, while CCS2 and CCS3 are in a new one.
>
> BSpec: 50844, 54029, 54030, 53223, 53224.
> Original-patch-by: Michel Thierry
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 15 ++++++++++++++-
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 3 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index b2de83be4d97..612281d47513 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -96,7 +96,7 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
> if (unlikely(!intr))
> return;
>
> - if (class <= COPY_ENGINE_CLASS)
> + if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
> return gen11_engine_irq_handler(gt, class, instance, intr);
>
> if (class == OTHER_CLASS)
> @@ -178,6 +178,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> /* Disable RCS, BCS, VCS and VECS class engines. */
> intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0);
> intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0);
> + if (CCS_MASK(gt))
> + intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
>
> /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0);
> @@ -191,6 +193,10 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0);
> if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
> intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0);
> + if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
> + intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
> + if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
> + intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
>
> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> @@ -218,6 +224,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> /* Enable RCS, BCS, VCS and VECS class interrupts. */
> intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask);
> intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
> + if (CCS_MASK(gt))
> + intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
>
> /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
> intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
> @@ -231,6 +239,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask);
> if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
> intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask);
> + if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
> + intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
> + if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
> + intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
> +
> /*
> * RPS interrupts will get enabled/disabled on demand when RPS itself
> * is enabled/disabled.
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1fd3040b6771..5b6eee5d8ade 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1573,6 +1573,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
> #define VEBOX_MASK(gt) \
> ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
> +#define CCS_MASK(gt) \
> + ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
>
> /*
> * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 33d6aa0b07c1..31e9c2cc4c0c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8139,6 +8139,7 @@ enum {
> #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
> #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
> #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
> +#define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048)
>
> #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
> #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
> @@ -8152,6 +8153,8 @@ enum {
> #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
> #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
> #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
> +#define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100)
> +#define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104)
>
> #define ENGINE1_MASK REG_GENMASK(31, 16)
> #define ENGINE0_MASK REG_GENMASK(15, 0)
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [Intel-gfx] [PATCH 3/8] drm/i915/xehp: Add Compute CS IRQ handlers
@ 2021-09-08 10:09 ` Tvrtko Ursulin
0 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 10:09 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: dri-devel, Vinay Belgaumkar, Daniele Ceraolo Spurio, Aravind Iddamsetty
On 07/09/2021 18:19, Matt Roper wrote:
> Add execlists and GuC interrupts for compute CS into existing IRQ handlers.
>
> All compute command streamers belong to the same compute class, so the
> only change needed to enable their interrupts is to program their GT engine
> interrupt mask registers.
>
> CCS0 shares the register with CCS1, while CCS2 and CCS3 are in a new one.
>
> BSpec: 50844, 54029, 54030, 53223, 53224.
> Original-patch-by: Michel Thierry
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 15 ++++++++++++++-
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 3 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index b2de83be4d97..612281d47513 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -96,7 +96,7 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
> if (unlikely(!intr))
> return;
>
> - if (class <= COPY_ENGINE_CLASS)
> + if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
> return gen11_engine_irq_handler(gt, class, instance, intr);
>
> if (class == OTHER_CLASS)
> @@ -178,6 +178,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> /* Disable RCS, BCS, VCS and VECS class engines. */
> intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0);
> intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0);
> + if (CCS_MASK(gt))
> + intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
>
> /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0);
> @@ -191,6 +193,10 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0);
> if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
> intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0);
> + if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
> + intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
> + if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
> + intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
>
> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> @@ -218,6 +224,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> /* Enable RCS, BCS, VCS and VECS class interrupts. */
> intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask);
> intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
> + if (CCS_MASK(gt))
> + intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
>
> /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
> intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
> @@ -231,6 +239,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask);
> if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
> intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask);
> + if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
> + intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
> + if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
> + intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
> +
> /*
> * RPS interrupts will get enabled/disabled on demand when RPS itself
> * is enabled/disabled.
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1fd3040b6771..5b6eee5d8ade 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1573,6 +1573,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
> #define VEBOX_MASK(gt) \
> ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
> +#define CCS_MASK(gt) \
> + ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
>
> /*
> * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 33d6aa0b07c1..31e9c2cc4c0c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8139,6 +8139,7 @@ enum {
> #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
> #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
> #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
> +#define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048)
>
> #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
> #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
> @@ -8152,6 +8153,8 @@ enum {
> #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
> #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
> #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
> +#define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100)
> +#define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104)
>
> #define ENGINE1_MASK REG_GENMASK(31, 16)
> #define ENGINE0_MASK REG_GENMASK(15, 0)
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 4/8] drm/i915/xehp: CCS should use RCS setup functions
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
@ 2021-09-07 17:19 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Matt Roper, Tvrtko Ursulin, Daniele Ceraolo Spurio,
Aravind Iddamsetty
The compute engine handles the same commands the render engine can
(except 3D pipeline), so it makes sense that CCS is more similar to RCS
than non-render engines.
The CCS context state (lrc) is also similar to the render one, so reuse
it. Note that the compute engine has its own CTX_R_PWR_CLK_STATE
register.
In order to avoid having multiple RCS && CCS checks, add the following
engine flag:
- I915_ENGINE_HAS_RCS_REG_STATE - use the render (larger) reg state ctx.
BSpec: 46260
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 8 +++++---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++++++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 +-
8 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index b32f7fed2d9c..fbe10783628b 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -883,7 +883,9 @@ static int igt_shared_ctx_exec(void *arg)
return err;
}
-static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *vma)
+static int rpcs_query_batch(struct drm_i915_gem_object *rpcs,
+ struct i915_vma *vma,
+ struct intel_engine_cs *engine)
{
u32 *cmd;
@@ -894,7 +896,7 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v
return PTR_ERR(cmd);
*cmd++ = MI_STORE_REGISTER_MEM_GEN8;
- *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
+ *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));
*cmd++ = lower_32_bits(vma->node.start);
*cmd++ = upper_32_bits(vma->node.start);
*cmd = MI_BATCH_BUFFER_END;
@@ -955,7 +957,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
if (err)
goto err_vma;
- err = rpcs_query_batch(rpcs, vma);
+ err = rpcs_query_batch(rpcs, vma, ce->engine);
if (err)
goto err_batch;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 69944bd8c19d..b346b946602d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -205,6 +205,8 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
switch (class) {
+ case COMPUTE_CLASS:
+ fallthrough;
case RENDER_CLASS:
switch (GRAPHICS_VER(gt->i915)) {
default:
@@ -379,6 +381,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
engine->props.preempt_timeout_ms = 0;
+ /* features common between engines sharing EUs */
+ if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
+ engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
+
engine->defaults = engine->props; /* never to change again */
engine->context_size = intel_engine_context_size(gt, engine->class);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index dcb9d8b2362a..30a0c69c36c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -454,6 +454,7 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
#define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
+#define I915_ENGINE_HAS_RCS_REG_STATE BIT(9)
unsigned int flags;
/*
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index de5f9c86b9a4..4c600c46414d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3406,7 +3406,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
logical_ring_default_vfuncs(engine);
logical_ring_default_irqs(engine);
- if (engine->class == RENDER_CLASS)
+ if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
rcs_submission_override(engine);
lrc_init_wa_ctx(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6ba8daea2f56..6490dce0a73f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -619,7 +619,7 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
!intel_engine_has_relative_mmio(engine));
- if (engine->class == RENDER_CLASS) {
+ if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_rcs_offsets;
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
@@ -1572,7 +1572,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
unsigned int i;
int err;
- if (engine->class != RENDER_CLASS)
+ if (!(engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
return;
switch (GRAPHICS_VER(engine->i915)) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 87d8dc8f51b9..2f5bf7aa7e3b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2517,7 +2517,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
guc_default_irqs(engine);
guc_init_breadcrumbs(engine);
- if (engine->class == RENDER_CLASS)
+ if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
rcs_submission_override(engine);
lrc_init_wa_ctx(engine);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2f01b8c0284c..5e12a9726c43 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2418,7 +2418,7 @@ gen12_configure_all_contexts(struct i915_perf_stream *stream,
{
struct flex regs[] = {
{
- GEN8_R_PWR_CLK_STATE,
+ GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
CTX_R_PWR_CLK_STATE,
},
};
@@ -2438,7 +2438,7 @@ lrc_configure_all_contexts(struct i915_perf_stream *stream,
#define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
struct flex regs[] = {
{
- GEN8_R_PWR_CLK_STATE,
+ GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
CTX_R_PWR_CLK_STATE,
},
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31e9c2cc4c0c..0bb185ce9529 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -441,7 +441,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
-#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
+#define GEN8_R_PWR_CLK_STATE(base) _MMIO((base)+0xc8)
#define GEN8_RPCS_ENABLE (1 << 31)
#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
#define GEN8_RPCS_S_CNT_SHIFT 15
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread* [Intel-gfx] [PATCH 4/8] drm/i915/xehp: CCS should use RCS setup functions
@ 2021-09-07 17:19 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Matt Roper, Tvrtko Ursulin, Daniele Ceraolo Spurio,
Aravind Iddamsetty
The compute engine handles the same commands the render engine can
(except 3D pipeline), so it makes sense that CCS is more similar to RCS
than non-render engines.
The CCS context state (lrc) is also similar to the render one, so reuse
it. Note that the compute engine has its own CTX_R_PWR_CLK_STATE
register.
In order to avoid having multiple RCS && CCS checks, add the following
engine flag:
- I915_ENGINE_HAS_RCS_REG_STATE - use the render (larger) reg state ctx.
BSpec: 46260
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 8 +++++---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++++++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 +-
8 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index b32f7fed2d9c..fbe10783628b 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -883,7 +883,9 @@ static int igt_shared_ctx_exec(void *arg)
return err;
}
-static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *vma)
+static int rpcs_query_batch(struct drm_i915_gem_object *rpcs,
+ struct i915_vma *vma,
+ struct intel_engine_cs *engine)
{
u32 *cmd;
@@ -894,7 +896,7 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v
return PTR_ERR(cmd);
*cmd++ = MI_STORE_REGISTER_MEM_GEN8;
- *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
+ *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));
*cmd++ = lower_32_bits(vma->node.start);
*cmd++ = upper_32_bits(vma->node.start);
*cmd = MI_BATCH_BUFFER_END;
@@ -955,7 +957,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
if (err)
goto err_vma;
- err = rpcs_query_batch(rpcs, vma);
+ err = rpcs_query_batch(rpcs, vma, ce->engine);
if (err)
goto err_batch;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 69944bd8c19d..b346b946602d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -205,6 +205,8 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
switch (class) {
+ case COMPUTE_CLASS:
+ fallthrough;
case RENDER_CLASS:
switch (GRAPHICS_VER(gt->i915)) {
default:
@@ -379,6 +381,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
engine->props.preempt_timeout_ms = 0;
+ /* features common between engines sharing EUs */
+ if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
+ engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
+
engine->defaults = engine->props; /* never to change again */
engine->context_size = intel_engine_context_size(gt, engine->class);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index dcb9d8b2362a..30a0c69c36c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -454,6 +454,7 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
#define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
+#define I915_ENGINE_HAS_RCS_REG_STATE BIT(9)
unsigned int flags;
/*
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index de5f9c86b9a4..4c600c46414d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3406,7 +3406,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
logical_ring_default_vfuncs(engine);
logical_ring_default_irqs(engine);
- if (engine->class == RENDER_CLASS)
+ if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
rcs_submission_override(engine);
lrc_init_wa_ctx(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6ba8daea2f56..6490dce0a73f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -619,7 +619,7 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
!intel_engine_has_relative_mmio(engine));
- if (engine->class == RENDER_CLASS) {
+ if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_rcs_offsets;
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
@@ -1572,7 +1572,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
unsigned int i;
int err;
- if (engine->class != RENDER_CLASS)
+ if (!(engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
return;
switch (GRAPHICS_VER(engine->i915)) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 87d8dc8f51b9..2f5bf7aa7e3b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2517,7 +2517,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
guc_default_irqs(engine);
guc_init_breadcrumbs(engine);
- if (engine->class == RENDER_CLASS)
+ if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
rcs_submission_override(engine);
lrc_init_wa_ctx(engine);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2f01b8c0284c..5e12a9726c43 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2418,7 +2418,7 @@ gen12_configure_all_contexts(struct i915_perf_stream *stream,
{
struct flex regs[] = {
{
- GEN8_R_PWR_CLK_STATE,
+ GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
CTX_R_PWR_CLK_STATE,
},
};
@@ -2438,7 +2438,7 @@ lrc_configure_all_contexts(struct i915_perf_stream *stream,
#define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
struct flex regs[] = {
{
- GEN8_R_PWR_CLK_STATE,
+ GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
CTX_R_PWR_CLK_STATE,
},
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31e9c2cc4c0c..0bb185ce9529 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -441,7 +441,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
-#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
+#define GEN8_R_PWR_CLK_STATE(base) _MMIO((base)+0xc8)
#define GEN8_RPCS_ENABLE (1 << 31)
#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
#define GEN8_RPCS_S_CNT_SHIFT 15
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 4/8] drm/i915/xehp: CCS should use RCS setup functions
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
@ 2021-09-08 10:13 ` Tvrtko Ursulin
-1 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 10:13 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: dri-devel, Daniele Ceraolo Spurio, Aravind Iddamsetty
On 07/09/2021 18:19, Matt Roper wrote:
> The compute engine handles the same commands the render engine can
> (except 3D pipeline), so it makes sense that CCS is more similar to RCS
> than non-render engines.
>
> The CCS context state (lrc) is also similar to the render one, so reuse
> it. Note that the compute engine has its own CTX_R_PWR_CLK_STATE
> register.
>
> In order to avoid having multiple RCS && CCS checks, add the following
> engine flag:
> - I915_ENGINE_HAS_RCS_REG_STATE - use the render (larger) reg state ctx.
>
> BSpec: 46260
> Original-patch-by: Michel Thierry
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 8 +++++---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++++++
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 8 files changed, 19 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> index b32f7fed2d9c..fbe10783628b 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> @@ -883,7 +883,9 @@ static int igt_shared_ctx_exec(void *arg)
> return err;
> }
>
> -static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *vma)
> +static int rpcs_query_batch(struct drm_i915_gem_object *rpcs,
> + struct i915_vma *vma,
> + struct intel_engine_cs *engine)
> {
> u32 *cmd;
>
> @@ -894,7 +896,7 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v
> return PTR_ERR(cmd);
>
> *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
> - *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
> + *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));
> *cmd++ = lower_32_bits(vma->node.start);
> *cmd++ = upper_32_bits(vma->node.start);
> *cmd = MI_BATCH_BUFFER_END;
> @@ -955,7 +957,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
> if (err)
> goto err_vma;
>
> - err = rpcs_query_batch(rpcs, vma);
> + err = rpcs_query_batch(rpcs, vma, ce->engine);
> if (err)
> goto err_batch;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 69944bd8c19d..b346b946602d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -205,6 +205,8 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
> BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
>
> switch (class) {
> + case COMPUTE_CLASS:
> + fallthrough;
> case RENDER_CLASS:
> switch (GRAPHICS_VER(gt->i915)) {
> default:
> @@ -379,6 +381,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
> if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
> engine->props.preempt_timeout_ms = 0;
>
> + /* features common between engines sharing EUs */
> + if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
> + engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
> +
> engine->defaults = engine->props; /* never to change again */
>
> engine->context_size = intel_engine_context_size(gt, engine->class);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index dcb9d8b2362a..30a0c69c36c8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -454,6 +454,7 @@ struct intel_engine_cs {
> #define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
> #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
> #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
> +#define I915_ENGINE_HAS_RCS_REG_STATE BIT(9)
> unsigned int flags;
>
> /*
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index de5f9c86b9a4..4c600c46414d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3406,7 +3406,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
> logical_ring_default_vfuncs(engine);
> logical_ring_default_irqs(engine);
>
> - if (engine->class == RENDER_CLASS)
> + if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
> rcs_submission_override(engine);
Hm, what do pipe control flushes which relate to 3d pipeline end up
doing on CCS engines?
Regards,
Tvrtko
>
> lrc_init_wa_ctx(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 6ba8daea2f56..6490dce0a73f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -619,7 +619,7 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
> !intel_engine_has_relative_mmio(engine));
>
> - if (engine->class == RENDER_CLASS) {
> + if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
> if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return dg2_rcs_offsets;
> else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> @@ -1572,7 +1572,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
> unsigned int i;
> int err;
>
> - if (engine->class != RENDER_CLASS)
> + if (!(engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
> return;
>
> switch (GRAPHICS_VER(engine->i915)) {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 87d8dc8f51b9..2f5bf7aa7e3b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -2517,7 +2517,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
> guc_default_irqs(engine);
> guc_init_breadcrumbs(engine);
>
> - if (engine->class == RENDER_CLASS)
> + if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
> rcs_submission_override(engine);
>
> lrc_init_wa_ctx(engine);
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 2f01b8c0284c..5e12a9726c43 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2418,7 +2418,7 @@ gen12_configure_all_contexts(struct i915_perf_stream *stream,
> {
> struct flex regs[] = {
> {
> - GEN8_R_PWR_CLK_STATE,
> + GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
> CTX_R_PWR_CLK_STATE,
> },
> };
> @@ -2438,7 +2438,7 @@ lrc_configure_all_contexts(struct i915_perf_stream *stream,
> #define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
> struct flex regs[] = {
> {
> - GEN8_R_PWR_CLK_STATE,
> + GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
> CTX_R_PWR_CLK_STATE,
> },
> {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 31e9c2cc4c0c..0bb185ce9529 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -441,7 +441,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
> #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
>
> -#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
> +#define GEN8_R_PWR_CLK_STATE(base) _MMIO((base)+0xc8)
> #define GEN8_RPCS_ENABLE (1 << 31)
> #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
> #define GEN8_RPCS_S_CNT_SHIFT 15
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [Intel-gfx] [PATCH 4/8] drm/i915/xehp: CCS should use RCS setup functions
@ 2021-09-08 10:13 ` Tvrtko Ursulin
0 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 10:13 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: dri-devel, Daniele Ceraolo Spurio, Aravind Iddamsetty
On 07/09/2021 18:19, Matt Roper wrote:
> The compute engine handles the same commands the render engine can
> (except 3D pipeline), so it makes sense that CCS is more similar to RCS
> than non-render engines.
>
> The CCS context state (lrc) is also similar to the render one, so reuse
> it. Note that the compute engine has its own CTX_R_PWR_CLK_STATE
> register.
>
> In order to avoid having multiple RCS && CCS checks, add the following
> engine flag:
> - I915_ENGINE_HAS_RCS_REG_STATE - use the render (larger) reg state ctx.
>
> BSpec: 46260
> Original-patch-by: Michel Thierry
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 8 +++++---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++++++
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 8 files changed, 19 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> index b32f7fed2d9c..fbe10783628b 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> @@ -883,7 +883,9 @@ static int igt_shared_ctx_exec(void *arg)
> return err;
> }
>
> -static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *vma)
> +static int rpcs_query_batch(struct drm_i915_gem_object *rpcs,
> + struct i915_vma *vma,
> + struct intel_engine_cs *engine)
> {
> u32 *cmd;
>
> @@ -894,7 +896,7 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v
> return PTR_ERR(cmd);
>
> *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
> - *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
> + *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));
> *cmd++ = lower_32_bits(vma->node.start);
> *cmd++ = upper_32_bits(vma->node.start);
> *cmd = MI_BATCH_BUFFER_END;
> @@ -955,7 +957,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
> if (err)
> goto err_vma;
>
> - err = rpcs_query_batch(rpcs, vma);
> + err = rpcs_query_batch(rpcs, vma, ce->engine);
> if (err)
> goto err_batch;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 69944bd8c19d..b346b946602d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -205,6 +205,8 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
> BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
>
> switch (class) {
> + case COMPUTE_CLASS:
> + fallthrough;
> case RENDER_CLASS:
> switch (GRAPHICS_VER(gt->i915)) {
> default:
> @@ -379,6 +381,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
> if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
> engine->props.preempt_timeout_ms = 0;
>
> + /* features common between engines sharing EUs */
> + if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
> + engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
> +
> engine->defaults = engine->props; /* never to change again */
>
> engine->context_size = intel_engine_context_size(gt, engine->class);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index dcb9d8b2362a..30a0c69c36c8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -454,6 +454,7 @@ struct intel_engine_cs {
> #define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
> #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
> #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
> +#define I915_ENGINE_HAS_RCS_REG_STATE BIT(9)
> unsigned int flags;
>
> /*
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index de5f9c86b9a4..4c600c46414d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3406,7 +3406,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
> logical_ring_default_vfuncs(engine);
> logical_ring_default_irqs(engine);
>
> - if (engine->class == RENDER_CLASS)
> + if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
> rcs_submission_override(engine);
Hm, what do pipe control flushes which relate to 3d pipeline end up
doing on CCS engines?
Regards,
Tvrtko
>
> lrc_init_wa_ctx(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 6ba8daea2f56..6490dce0a73f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -619,7 +619,7 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
> !intel_engine_has_relative_mmio(engine));
>
> - if (engine->class == RENDER_CLASS) {
> + if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
> if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return dg2_rcs_offsets;
> else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> @@ -1572,7 +1572,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
> unsigned int i;
> int err;
>
> - if (engine->class != RENDER_CLASS)
> + if (!(engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
> return;
>
> switch (GRAPHICS_VER(engine->i915)) {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 87d8dc8f51b9..2f5bf7aa7e3b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -2517,7 +2517,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
> guc_default_irqs(engine);
> guc_init_breadcrumbs(engine);
>
> - if (engine->class == RENDER_CLASS)
> + if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
> rcs_submission_override(engine);
>
> lrc_init_wa_ctx(engine);
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 2f01b8c0284c..5e12a9726c43 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2418,7 +2418,7 @@ gen12_configure_all_contexts(struct i915_perf_stream *stream,
> {
> struct flex regs[] = {
> {
> - GEN8_R_PWR_CLK_STATE,
> + GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
> CTX_R_PWR_CLK_STATE,
> },
> };
> @@ -2438,7 +2438,7 @@ lrc_configure_all_contexts(struct i915_perf_stream *stream,
> #define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
> struct flex regs[] = {
> {
> - GEN8_R_PWR_CLK_STATE,
> + GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
> CTX_R_PWR_CLK_STATE,
> },
> {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 31e9c2cc4c0c..0bb185ce9529 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -441,7 +441,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
> #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
>
> -#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
> +#define GEN8_R_PWR_CLK_STATE(base) _MMIO((base)+0xc8)
> #define GEN8_RPCS_ENABLE (1 << 31)
> #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
> #define GEN8_RPCS_S_CNT_SHIFT 15
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH 4/8] drm/i915/xehp: CCS should use RCS setup functions
2021-09-08 10:13 ` [Intel-gfx] " Tvrtko Ursulin
@ 2021-09-08 13:57 ` Tvrtko Ursulin
-1 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 13:57 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: dri-devel, Daniele Ceraolo Spurio, Aravind Iddamsetty
On 08/09/2021 11:13, Tvrtko Ursulin wrote:
>
> On 07/09/2021 18:19, Matt Roper wrote:
>> The compute engine handles the same commands the render engine can
>> (except 3D pipeline), so it makes sense that CCS is more similar to RCS
>> than non-render engines.
>>
>> The CCS context state (lrc) is also similar to the render one, so reuse
>> it. Note that the compute engine has its own CTX_R_PWR_CLK_STATE
>> register.
>>
>> In order to avoid having multiple RCS && CCS checks, add the following
>> engine flag:
>> - I915_ENGINE_HAS_RCS_REG_STATE - use the render (larger) reg state
>> ctx.
>>
>> BSpec: 46260
>> Original-patch-by: Michel Thierry
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> ---
>> drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 8 +++++---
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++++++
>> drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
>> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
>> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
>> drivers/gpu/drm/i915/i915_perf.c | 4 ++--
>> drivers/gpu/drm/i915/i915_reg.h | 2 +-
>> 8 files changed, 19 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> index b32f7fed2d9c..fbe10783628b 100644
>> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> @@ -883,7 +883,9 @@ static int igt_shared_ctx_exec(void *arg)
>> return err;
>> }
>> -static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct
>> i915_vma *vma)
>> +static int rpcs_query_batch(struct drm_i915_gem_object *rpcs,
>> + struct i915_vma *vma,
>> + struct intel_engine_cs *engine)
>> {
>> u32 *cmd;
>> @@ -894,7 +896,7 @@ static int rpcs_query_batch(struct
>> drm_i915_gem_object *rpcs, struct i915_vma *v
>> return PTR_ERR(cmd);
>> *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
>> - *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
>> + *cmd++ =
>> i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));
>> *cmd++ = lower_32_bits(vma->node.start);
>> *cmd++ = upper_32_bits(vma->node.start);
>> *cmd = MI_BATCH_BUFFER_END;
>> @@ -955,7 +957,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
>> if (err)
>> goto err_vma;
>> - err = rpcs_query_batch(rpcs, vma);
>> + err = rpcs_query_batch(rpcs, vma, ce->engine);
>> if (err)
>> goto err_batch;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 69944bd8c19d..b346b946602d 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -205,6 +205,8 @@ u32 intel_engine_context_size(struct intel_gt *gt,
>> u8 class)
>> BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
>> switch (class) {
>> + case COMPUTE_CLASS:
>> + fallthrough;
>> case RENDER_CLASS:
>> switch (GRAPHICS_VER(gt->i915)) {
>> default:
>> @@ -379,6 +381,10 @@ static int intel_engine_setup(struct intel_gt
>> *gt, enum intel_engine_id id)
>> if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
>> engine->props.preempt_timeout_ms = 0;
>> + /* features common between engines sharing EUs */
>> + if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
>> + engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
>> +
>> engine->defaults = engine->props; /* never to change again */
>> engine->context_size = intel_engine_context_size(gt,
>> engine->class);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> index dcb9d8b2362a..30a0c69c36c8 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> @@ -454,6 +454,7 @@ struct intel_engine_cs {
>> #define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
>> #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
>> #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
>> +#define I915_ENGINE_HAS_RCS_REG_STATE BIT(9)
>> unsigned int flags;
>> /*
>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> index de5f9c86b9a4..4c600c46414d 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> @@ -3406,7 +3406,7 @@ int intel_execlists_submission_setup(struct
>> intel_engine_cs *engine)
>> logical_ring_default_vfuncs(engine);
>> logical_ring_default_irqs(engine);
>> - if (engine->class == RENDER_CLASS)
>> + if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
>> rcs_submission_override(engine);
>
> Hm, what do pipe control flushes which relate to 3d pipeline end up
> doing on CCS engines?
Right, answer found in the following patch.
Ideally the two would swap places in the series so by the time vfunc are
assigned to the engines they actually handle them correctly. It's a
minor point since it's all disabled until the very end of the series so
either way:
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
>
> Regards,
>
> Tvrtko
>
>> lrc_init_wa_ctx(engine);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> index 6ba8daea2f56..6490dce0a73f 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> @@ -619,7 +619,7 @@ static const u8 *reg_offsets(const struct
>> intel_engine_cs *engine)
>> GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
>> !intel_engine_has_relative_mmio(engine));
>> - if (engine->class == RENDER_CLASS) {
>> + if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
>> if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
>> return dg2_rcs_offsets;
>> else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
>> @@ -1572,7 +1572,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs
>> *engine)
>> unsigned int i;
>> int err;
>> - if (engine->class != RENDER_CLASS)
>> + if (!(engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
>> return;
>> switch (GRAPHICS_VER(engine->i915)) {
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> index 87d8dc8f51b9..2f5bf7aa7e3b 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> @@ -2517,7 +2517,7 @@ int intel_guc_submission_setup(struct
>> intel_engine_cs *engine)
>> guc_default_irqs(engine);
>> guc_init_breadcrumbs(engine);
>> - if (engine->class == RENDER_CLASS)
>> + if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
>> rcs_submission_override(engine);
>> lrc_init_wa_ctx(engine);
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c
>> b/drivers/gpu/drm/i915/i915_perf.c
>> index 2f01b8c0284c..5e12a9726c43 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -2418,7 +2418,7 @@ gen12_configure_all_contexts(struct
>> i915_perf_stream *stream,
>> {
>> struct flex regs[] = {
>> {
>> - GEN8_R_PWR_CLK_STATE,
>> + GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
>> CTX_R_PWR_CLK_STATE,
>> },
>> };
>> @@ -2438,7 +2438,7 @@ lrc_configure_all_contexts(struct
>> i915_perf_stream *stream,
>> #define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
>> struct flex regs[] = {
>> {
>> - GEN8_R_PWR_CLK_STATE,
>> + GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
>> CTX_R_PWR_CLK_STATE,
>> },
>> {
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 31e9c2cc4c0c..0bb185ce9529 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -441,7 +441,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t
>> reg)
>> #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8
>> + 4)
>> #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
>> -#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
>> +#define GEN8_R_PWR_CLK_STATE(base) _MMIO((base)+0xc8)
>> #define GEN8_RPCS_ENABLE (1 << 31)
>> #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
>> #define GEN8_RPCS_S_CNT_SHIFT 15
>>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [Intel-gfx] [PATCH 4/8] drm/i915/xehp: CCS should use RCS setup functions
@ 2021-09-08 13:57 ` Tvrtko Ursulin
0 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 13:57 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: dri-devel, Daniele Ceraolo Spurio, Aravind Iddamsetty
On 08/09/2021 11:13, Tvrtko Ursulin wrote:
>
> On 07/09/2021 18:19, Matt Roper wrote:
>> The compute engine handles the same commands the render engine can
>> (except 3D pipeline), so it makes sense that CCS is more similar to RCS
>> than non-render engines.
>>
>> The CCS context state (lrc) is also similar to the render one, so reuse
>> it. Note that the compute engine has its own CTX_R_PWR_CLK_STATE
>> register.
>>
>> In order to avoid having multiple RCS && CCS checks, add the following
>> engine flag:
>> - I915_ENGINE_HAS_RCS_REG_STATE - use the render (larger) reg state
>> ctx.
>>
>> BSpec: 46260
>> Original-patch-by: Michel Thierry
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> ---
>> drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 8 +++++---
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++++++
>> drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
>> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
>> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
>> drivers/gpu/drm/i915/i915_perf.c | 4 ++--
>> drivers/gpu/drm/i915/i915_reg.h | 2 +-
>> 8 files changed, 19 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> index b32f7fed2d9c..fbe10783628b 100644
>> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>> @@ -883,7 +883,9 @@ static int igt_shared_ctx_exec(void *arg)
>> return err;
>> }
>> -static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct
>> i915_vma *vma)
>> +static int rpcs_query_batch(struct drm_i915_gem_object *rpcs,
>> + struct i915_vma *vma,
>> + struct intel_engine_cs *engine)
>> {
>> u32 *cmd;
>> @@ -894,7 +896,7 @@ static int rpcs_query_batch(struct
>> drm_i915_gem_object *rpcs, struct i915_vma *v
>> return PTR_ERR(cmd);
>> *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
>> - *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
>> + *cmd++ =
>> i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));
>> *cmd++ = lower_32_bits(vma->node.start);
>> *cmd++ = upper_32_bits(vma->node.start);
>> *cmd = MI_BATCH_BUFFER_END;
>> @@ -955,7 +957,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
>> if (err)
>> goto err_vma;
>> - err = rpcs_query_batch(rpcs, vma);
>> + err = rpcs_query_batch(rpcs, vma, ce->engine);
>> if (err)
>> goto err_batch;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 69944bd8c19d..b346b946602d 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -205,6 +205,8 @@ u32 intel_engine_context_size(struct intel_gt *gt,
>> u8 class)
>> BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
>> switch (class) {
>> + case COMPUTE_CLASS:
>> + fallthrough;
>> case RENDER_CLASS:
>> switch (GRAPHICS_VER(gt->i915)) {
>> default:
>> @@ -379,6 +381,10 @@ static int intel_engine_setup(struct intel_gt
>> *gt, enum intel_engine_id id)
>> if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
>> engine->props.preempt_timeout_ms = 0;
>> + /* features common between engines sharing EUs */
>> + if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
>> + engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
>> +
>> engine->defaults = engine->props; /* never to change again */
>> engine->context_size = intel_engine_context_size(gt,
>> engine->class);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> index dcb9d8b2362a..30a0c69c36c8 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> @@ -454,6 +454,7 @@ struct intel_engine_cs {
>> #define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
>> #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
>> #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
>> +#define I915_ENGINE_HAS_RCS_REG_STATE BIT(9)
>> unsigned int flags;
>> /*
>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> index de5f9c86b9a4..4c600c46414d 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> @@ -3406,7 +3406,7 @@ int intel_execlists_submission_setup(struct
>> intel_engine_cs *engine)
>> logical_ring_default_vfuncs(engine);
>> logical_ring_default_irqs(engine);
>> - if (engine->class == RENDER_CLASS)
>> + if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
>> rcs_submission_override(engine);
>
> Hm, what do pipe control flushes which relate to 3d pipeline end up
> doing on CCS engines?
Right, answer found in the following patch.
Ideally the two would swap places in the series so by the time vfunc are
assigned to the engines they actually handle them correctly. It's a
minor point since it's all disabled until the very end of the series so
either way:
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
>
> Regards,
>
> Tvrtko
>
>> lrc_init_wa_ctx(engine);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> index 6ba8daea2f56..6490dce0a73f 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> @@ -619,7 +619,7 @@ static const u8 *reg_offsets(const struct
>> intel_engine_cs *engine)
>> GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
>> !intel_engine_has_relative_mmio(engine));
>> - if (engine->class == RENDER_CLASS) {
>> + if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
>> if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
>> return dg2_rcs_offsets;
>> else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
>> @@ -1572,7 +1572,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs
>> *engine)
>> unsigned int i;
>> int err;
>> - if (engine->class != RENDER_CLASS)
>> + if (!(engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
>> return;
>> switch (GRAPHICS_VER(engine->i915)) {
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> index 87d8dc8f51b9..2f5bf7aa7e3b 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> @@ -2517,7 +2517,7 @@ int intel_guc_submission_setup(struct
>> intel_engine_cs *engine)
>> guc_default_irqs(engine);
>> guc_init_breadcrumbs(engine);
>> - if (engine->class == RENDER_CLASS)
>> + if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
>> rcs_submission_override(engine);
>> lrc_init_wa_ctx(engine);
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c
>> b/drivers/gpu/drm/i915/i915_perf.c
>> index 2f01b8c0284c..5e12a9726c43 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -2418,7 +2418,7 @@ gen12_configure_all_contexts(struct
>> i915_perf_stream *stream,
>> {
>> struct flex regs[] = {
>> {
>> - GEN8_R_PWR_CLK_STATE,
>> + GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
>> CTX_R_PWR_CLK_STATE,
>> },
>> };
>> @@ -2438,7 +2438,7 @@ lrc_configure_all_contexts(struct
>> i915_perf_stream *stream,
>> #define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
>> struct flex regs[] = {
>> {
>> - GEN8_R_PWR_CLK_STATE,
>> + GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
>> CTX_R_PWR_CLK_STATE,
>> },
>> {
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 31e9c2cc4c0c..0bb185ce9529 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -441,7 +441,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t
>> reg)
>> #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8
>> + 4)
>> #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
>> -#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
>> +#define GEN8_R_PWR_CLK_STATE(base) _MMIO((base)+0xc8)
>> #define GEN8_RPCS_ENABLE (1 << 31)
>> #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
>> #define GEN8_RPCS_S_CNT_SHIFT 15
>>
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 5/8] drm/i915/xehp: compute engine pipe_control
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
@ 2021-09-07 17:19 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Daniele Ceraolo Spurio, Vinay Belgaumkar,
Aravind Iddamsetty, Matt Roper
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
CCS re-uses the RCS functions for breadcrumb and flush emission.
However, CCS pipe_control has additional programming restrictions:
- Command Streamer Stall Enable must be always set
- Post Sync Operations must not be set to Write PS Depth Count
- 3D-related bits must not be set
Bspec: 47112
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 31 ++++++++++++++------
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 ++++++++++
2 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 461844dffd7e..bf79e5ee3e45 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -200,6 +200,8 @@ static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
{
+ struct intel_engine_cs *engine = rq->engine;
+
if (mode & EMIT_FLUSH) {
u32 flags = 0;
u32 *cs;
@@ -218,6 +220,9 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_CS_STALL;
+ if (engine->class == COMPUTE_CLASS)
+ flags &= ~PIPE_CONTROL_RENDER_ONLY_FLAGS;
+
cs = intel_ring_begin(rq, 6);
if (IS_ERR(cs))
return PTR_ERR(cs);
@@ -245,6 +250,9 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_CS_STALL;
+ if (engine->class == COMPUTE_CLASS)
+ flags &= ~PIPE_CONTROL_RENDER_ONLY_FLAGS;
+
cs = intel_ring_begin(rq, 8 + 4);
if (IS_ERR(cs))
return PTR_ERR(cs);
@@ -617,19 +625,24 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{
+ u32 flags = (PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_TILE_CACHE_FLUSH |
+ PIPE_CONTROL_FLUSH_L3 |
+ PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ /* Wa_1409600907:tgl,rkl,dg1,adl-p */
+ PIPE_CONTROL_DEPTH_STALL |
+ PIPE_CONTROL_DC_FLUSH_ENABLE |
+ PIPE_CONTROL_FLUSH_ENABLE);
+
+ if (rq->engine->class == COMPUTE_CLASS)
+ flags &= ~PIPE_CONTROL_RENDER_ONLY_FLAGS;
+
cs = gen12_emit_ggtt_write_rcs(cs,
rq->fence.seqno,
hwsp_offset(rq),
PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
- PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_TILE_CACHE_FLUSH |
- PIPE_CONTROL_FLUSH_L3 |
- PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- /* Wa_1409600907:tgl */
- PIPE_CONTROL_DEPTH_STALL |
- PIPE_CONTROL_DC_FLUSH_ENABLE |
- PIPE_CONTROL_FLUSH_ENABLE);
+ flags);
return gen12_emit_fini_breadcrumb_tail(rq, cs);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 1c3af0fc0456..a3c1047a2c71 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -223,11 +223,14 @@
#define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29) /* gen11+ */
#define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28) /* gen11+ */
#define PIPE_CONTROL_FLUSH_L3 (1<<27)
+#define PIPE_CONTROL_AMFS_FLUSH (1<<25) /* gen12+ */
#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
#define PIPE_CONTROL_MMIO_WRITE (1<<23)
#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
#define PIPE_CONTROL_CS_STALL (1<<20)
+#define PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET (1<<19)
#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
+#define PIPE_CONTROL_PSD_SYNC (1<<17) /* gen11+ */
#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
#define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
#define PIPE_CONTROL_QW_WRITE (1<<14)
@@ -249,6 +252,18 @@
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
+/* 3D-related flags can't be set on compute engine */
+#define PIPE_CONTROL_RENDER_ONLY_FLAGS (\
+ PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
+ PIPE_CONTROL_TILE_CACHE_FLUSH | \
+ PIPE_CONTROL_DEPTH_STALL | \
+ PIPE_CONTROL_STALL_AT_SCOREBOARD | \
+ PIPE_CONTROL_PSD_SYNC | \
+ PIPE_CONTROL_AMFS_FLUSH | \
+ PIPE_CONTROL_VF_CACHE_INVALIDATE | \
+ PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
+
#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
/* Opcodes for MI_MATH_INSTR */
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread* [Intel-gfx] [PATCH 5/8] drm/i915/xehp: compute engine pipe_control
@ 2021-09-07 17:19 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Daniele Ceraolo Spurio, Vinay Belgaumkar,
Aravind Iddamsetty, Matt Roper
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
CCS re-uses the RCS functions for breadcrumb and flush emission.
However, CCS pipe_control has additional programming restrictions:
- Command Streamer Stall Enable must be always set
- Post Sync Operations must not be set to Write PS Depth Count
- 3D-related bits must not be set
Bspec: 47112
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 31 ++++++++++++++------
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 ++++++++++
2 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 461844dffd7e..bf79e5ee3e45 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -200,6 +200,8 @@ static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
{
+ struct intel_engine_cs *engine = rq->engine;
+
if (mode & EMIT_FLUSH) {
u32 flags = 0;
u32 *cs;
@@ -218,6 +220,9 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_CS_STALL;
+ if (engine->class == COMPUTE_CLASS)
+ flags &= ~PIPE_CONTROL_RENDER_ONLY_FLAGS;
+
cs = intel_ring_begin(rq, 6);
if (IS_ERR(cs))
return PTR_ERR(cs);
@@ -245,6 +250,9 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_CS_STALL;
+ if (engine->class == COMPUTE_CLASS)
+ flags &= ~PIPE_CONTROL_RENDER_ONLY_FLAGS;
+
cs = intel_ring_begin(rq, 8 + 4);
if (IS_ERR(cs))
return PTR_ERR(cs);
@@ -617,19 +625,24 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{
+ u32 flags = (PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_TILE_CACHE_FLUSH |
+ PIPE_CONTROL_FLUSH_L3 |
+ PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ /* Wa_1409600907:tgl,rkl,dg1,adl-p */
+ PIPE_CONTROL_DEPTH_STALL |
+ PIPE_CONTROL_DC_FLUSH_ENABLE |
+ PIPE_CONTROL_FLUSH_ENABLE);
+
+ if (rq->engine->class == COMPUTE_CLASS)
+ flags &= ~PIPE_CONTROL_RENDER_ONLY_FLAGS;
+
cs = gen12_emit_ggtt_write_rcs(cs,
rq->fence.seqno,
hwsp_offset(rq),
PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
- PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_TILE_CACHE_FLUSH |
- PIPE_CONTROL_FLUSH_L3 |
- PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- /* Wa_1409600907:tgl */
- PIPE_CONTROL_DEPTH_STALL |
- PIPE_CONTROL_DC_FLUSH_ENABLE |
- PIPE_CONTROL_FLUSH_ENABLE);
+ flags);
return gen12_emit_fini_breadcrumb_tail(rq, cs);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 1c3af0fc0456..a3c1047a2c71 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -223,11 +223,14 @@
#define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29) /* gen11+ */
#define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28) /* gen11+ */
#define PIPE_CONTROL_FLUSH_L3 (1<<27)
+#define PIPE_CONTROL_AMFS_FLUSH (1<<25) /* gen12+ */
#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
#define PIPE_CONTROL_MMIO_WRITE (1<<23)
#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
#define PIPE_CONTROL_CS_STALL (1<<20)
+#define PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET (1<<19)
#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
+#define PIPE_CONTROL_PSD_SYNC (1<<17) /* gen11+ */
#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
#define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
#define PIPE_CONTROL_QW_WRITE (1<<14)
@@ -249,6 +252,18 @@
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
+/* 3D-related flags can't be set on compute engine */
+#define PIPE_CONTROL_RENDER_ONLY_FLAGS (\
+ PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
+ PIPE_CONTROL_TILE_CACHE_FLUSH | \
+ PIPE_CONTROL_DEPTH_STALL | \
+ PIPE_CONTROL_STALL_AT_SCOREBOARD | \
+ PIPE_CONTROL_PSD_SYNC | \
+ PIPE_CONTROL_AMFS_FLUSH | \
+ PIPE_CONTROL_VF_CACHE_INVALIDATE | \
+ PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
+
#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
/* Opcodes for MI_MATH_INSTR */
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 6/8] drm/i915/xehp: Define context scheduling attributes in lrc descriptor
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
@ 2021-09-07 17:19 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Matt Roper, Tvrtko Ursulin, Aravind Iddamsetty,
Prasad Nallani
In Dual Context mode the EUs are shared between render and compute
command streamers. The hardware provides a field in the lrc descriptor
to indicate the prioritization of the thread dispatch associated to the
corresponding context.
The context priority is set to 'low' at creation time and relies on the
existing context priority to set it to low/normal/high.
HSDES: 1604462009
Bspec: 46145, 46260
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Prasad Nallani <prasad.nallani@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +++-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 6 +++++-
drivers/gpu/drm/i915/gt/intel_lrc.h | 10 ++++++++++
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
5 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index b346b946602d..2f719f0ecac3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -382,8 +382,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
engine->props.preempt_timeout_ms = 0;
/* features common between engines sharing EUs */
- if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
+ if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
+ engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
+ }
engine->defaults = engine->props; /* never to change again */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 30a0c69c36c8..00bf0296b28a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -455,6 +455,7 @@ struct intel_engine_cs {
#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
#define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
#define I915_ENGINE_HAS_RCS_REG_STATE BIT(9)
+#define I915_ENGINE_HAS_EU_PRIORITY BIT(10)
unsigned int flags;
/*
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 4c600c46414d..2b36ec7f3a04 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -662,9 +662,13 @@ static inline void execlists_schedule_out(struct i915_request *rq)
static u64 execlists_update_context(struct i915_request *rq)
{
struct intel_context *ce = rq->context;
- u64 desc = ce->lrc.desc;
+ u64 desc;
u32 tail, prev;
+ desc = ce->lrc.desc;
+ if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
+ desc |= lrc_desc_priority(rq_prio(rq));
+
/*
* WaIdleLiteRestore:bdw,skl
*
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 7f697845c4cf..d3f2096b3d51 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -79,4 +79,14 @@ static inline u32 lrc_get_runtime(const struct intel_context *ce)
return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
}
+static inline u32 lrc_desc_priority(int prio)
+{
+ if (prio > I915_PRIORITY_NORMAL)
+ return GEN12_CTX_PRIORITY_HIGH;
+ else if (prio < I915_PRIORITY_NORMAL)
+ return GEN12_CTX_PRIORITY_LOW;
+ else
+ return GEN12_CTX_PRIORITY_NORMAL;
+}
+
#endif /* __INTEL_LRC_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bb185ce9529..5b68c02c35af 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4212,6 +4212,10 @@ enum {
#define GEN8_CTX_L3LLC_COHERENT (1 << 5)
#define GEN8_CTX_PRIVILEGE (1 << 8)
#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
+#define GEN12_CTX_PRIORITY_MASK REG_GENMASK(10, 9)
+#define GEN12_CTX_PRIORITY_HIGH REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 2)
+#define GEN12_CTX_PRIORITY_NORMAL REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 1)
+#define GEN12_CTX_PRIORITY_LOW REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 0)
#define GEN8_CTX_ID_SHIFT 32
#define GEN8_CTX_ID_WIDTH 21
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread* [Intel-gfx] [PATCH 6/8] drm/i915/xehp: Define context scheduling attributes in lrc descriptor
@ 2021-09-07 17:19 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Matt Roper, Tvrtko Ursulin, Aravind Iddamsetty,
Prasad Nallani
In Dual Context mode the EUs are shared between render and compute
command streamers. The hardware provides a field in the lrc descriptor
to indicate the prioritization of the thread dispatch associated to the
corresponding context.
The context priority is set to 'low' at creation time and relies on the
existing context priority to set it to low/normal/high.
HSDES: 1604462009
Bspec: 46145, 46260
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Prasad Nallani <prasad.nallani@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +++-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 6 +++++-
drivers/gpu/drm/i915/gt/intel_lrc.h | 10 ++++++++++
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
5 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index b346b946602d..2f719f0ecac3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -382,8 +382,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
engine->props.preempt_timeout_ms = 0;
/* features common between engines sharing EUs */
- if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
+ if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
+ engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
+ }
engine->defaults = engine->props; /* never to change again */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 30a0c69c36c8..00bf0296b28a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -455,6 +455,7 @@ struct intel_engine_cs {
#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
#define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
#define I915_ENGINE_HAS_RCS_REG_STATE BIT(9)
+#define I915_ENGINE_HAS_EU_PRIORITY BIT(10)
unsigned int flags;
/*
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 4c600c46414d..2b36ec7f3a04 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -662,9 +662,13 @@ static inline void execlists_schedule_out(struct i915_request *rq)
static u64 execlists_update_context(struct i915_request *rq)
{
struct intel_context *ce = rq->context;
- u64 desc = ce->lrc.desc;
+ u64 desc;
u32 tail, prev;
+ desc = ce->lrc.desc;
+ if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
+ desc |= lrc_desc_priority(rq_prio(rq));
+
/*
* WaIdleLiteRestore:bdw,skl
*
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 7f697845c4cf..d3f2096b3d51 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -79,4 +79,14 @@ static inline u32 lrc_get_runtime(const struct intel_context *ce)
return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
}
+static inline u32 lrc_desc_priority(int prio)
+{
+ if (prio > I915_PRIORITY_NORMAL)
+ return GEN12_CTX_PRIORITY_HIGH;
+ else if (prio < I915_PRIORITY_NORMAL)
+ return GEN12_CTX_PRIORITY_LOW;
+ else
+ return GEN12_CTX_PRIORITY_NORMAL;
+}
+
#endif /* __INTEL_LRC_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bb185ce9529..5b68c02c35af 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4212,6 +4212,10 @@ enum {
#define GEN8_CTX_L3LLC_COHERENT (1 << 5)
#define GEN8_CTX_PRIVILEGE (1 << 8)
#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
+#define GEN12_CTX_PRIORITY_MASK REG_GENMASK(10, 9)
+#define GEN12_CTX_PRIORITY_HIGH REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 2)
+#define GEN12_CTX_PRIORITY_NORMAL REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 1)
+#define GEN12_CTX_PRIORITY_LOW REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 0)
#define GEN8_CTX_ID_SHIFT 32
#define GEN8_CTX_ID_WIDTH 21
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 6/8] drm/i915/xehp: Define context scheduling attributes in lrc descriptor
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
@ 2021-09-08 14:01 ` Tvrtko Ursulin
-1 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 14:01 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel, Aravind Iddamsetty, Prasad Nallani
On 07/09/2021 18:19, Matt Roper wrote:
> In Dual Context mode the EUs are shared between render and compute
> command streamers. The hardware provides a field in the lrc descriptor
> to indicate the prioritization of the thread dispatch associated to the
> corresponding context.
>
> The context priority is set to 'low' at creation time and relies on the
> existing context priority to set it to low/normal/high.
>
> HSDES: 1604462009
> Bspec: 46145, 46260
> Original-patch-by: Michel Thierry
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Prasad Nallani <prasad.nallani@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +++-
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 6 +++++-
> drivers/gpu/drm/i915/gt/intel_lrc.h | 10 ++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 5 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index b346b946602d..2f719f0ecac3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -382,8 +382,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
> engine->props.preempt_timeout_ms = 0;
>
> /* features common between engines sharing EUs */
> - if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
> + if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
> engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
> + engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
> + }
>
> engine->defaults = engine->props; /* never to change again */
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 30a0c69c36c8..00bf0296b28a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -455,6 +455,7 @@ struct intel_engine_cs {
> #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
> #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
> #define I915_ENGINE_HAS_RCS_REG_STATE BIT(9)
> +#define I915_ENGINE_HAS_EU_PRIORITY BIT(10)
> unsigned int flags;
>
> /*
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 4c600c46414d..2b36ec7f3a04 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -662,9 +662,13 @@ static inline void execlists_schedule_out(struct i915_request *rq)
> static u64 execlists_update_context(struct i915_request *rq)
> {
> struct intel_context *ce = rq->context;
> - u64 desc = ce->lrc.desc;
> + u64 desc;
> u32 tail, prev;
>
> + desc = ce->lrc.desc;
> + if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
> + desc |= lrc_desc_priority(rq_prio(rq));
> +
> /*
> * WaIdleLiteRestore:bdw,skl
> *
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
> index 7f697845c4cf..d3f2096b3d51 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
> @@ -79,4 +79,14 @@ static inline u32 lrc_get_runtime(const struct intel_context *ce)
> return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
> }
>
> +static inline u32 lrc_desc_priority(int prio)
> +{
> + if (prio > I915_PRIORITY_NORMAL)
> + return GEN12_CTX_PRIORITY_HIGH;
> + else if (prio < I915_PRIORITY_NORMAL)
> + return GEN12_CTX_PRIORITY_LOW;
> + else
> + return GEN12_CTX_PRIORITY_NORMAL;
> +}
> +
> #endif /* __INTEL_LRC_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0bb185ce9529..5b68c02c35af 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4212,6 +4212,10 @@ enum {
> #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
> #define GEN8_CTX_PRIVILEGE (1 << 8)
> #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
> +#define GEN12_CTX_PRIORITY_MASK REG_GENMASK(10, 9)
> +#define GEN12_CTX_PRIORITY_HIGH REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 2)
> +#define GEN12_CTX_PRIORITY_NORMAL REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 1)
> +#define GEN12_CTX_PRIORITY_LOW REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 0)
>
> #define GEN8_CTX_ID_SHIFT 32
> #define GEN8_CTX_ID_WIDTH 21
>
Haven't checked bspec to check the bitfield but the mechanics look good.
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [Intel-gfx] [PATCH 6/8] drm/i915/xehp: Define context scheduling attributes in lrc descriptor
@ 2021-09-08 14:01 ` Tvrtko Ursulin
0 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 14:01 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel, Aravind Iddamsetty, Prasad Nallani
On 07/09/2021 18:19, Matt Roper wrote:
> In Dual Context mode the EUs are shared between render and compute
> command streamers. The hardware provides a field in the lrc descriptor
> to indicate the prioritization of the thread dispatch associated to the
> corresponding context.
>
> The context priority is set to 'low' at creation time and relies on the
> existing context priority to set it to low/normal/high.
>
> HSDES: 1604462009
> Bspec: 46145, 46260
> Original-patch-by: Michel Thierry
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Prasad Nallani <prasad.nallani@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +++-
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 6 +++++-
> drivers/gpu/drm/i915/gt/intel_lrc.h | 10 ++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 5 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index b346b946602d..2f719f0ecac3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -382,8 +382,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
> engine->props.preempt_timeout_ms = 0;
>
> /* features common between engines sharing EUs */
> - if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
> + if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
> engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
> + engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
> + }
>
> engine->defaults = engine->props; /* never to change again */
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 30a0c69c36c8..00bf0296b28a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -455,6 +455,7 @@ struct intel_engine_cs {
> #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
> #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
> #define I915_ENGINE_HAS_RCS_REG_STATE BIT(9)
> +#define I915_ENGINE_HAS_EU_PRIORITY BIT(10)
> unsigned int flags;
>
> /*
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 4c600c46414d..2b36ec7f3a04 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -662,9 +662,13 @@ static inline void execlists_schedule_out(struct i915_request *rq)
> static u64 execlists_update_context(struct i915_request *rq)
> {
> struct intel_context *ce = rq->context;
> - u64 desc = ce->lrc.desc;
> + u64 desc;
> u32 tail, prev;
>
> + desc = ce->lrc.desc;
> + if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
> + desc |= lrc_desc_priority(rq_prio(rq));
> +
> /*
> * WaIdleLiteRestore:bdw,skl
> *
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
> index 7f697845c4cf..d3f2096b3d51 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
> @@ -79,4 +79,14 @@ static inline u32 lrc_get_runtime(const struct intel_context *ce)
> return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
> }
>
> +static inline u32 lrc_desc_priority(int prio)
> +{
> + if (prio > I915_PRIORITY_NORMAL)
> + return GEN12_CTX_PRIORITY_HIGH;
> + else if (prio < I915_PRIORITY_NORMAL)
> + return GEN12_CTX_PRIORITY_LOW;
> + else
> + return GEN12_CTX_PRIORITY_NORMAL;
> +}
> +
> #endif /* __INTEL_LRC_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0bb185ce9529..5b68c02c35af 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4212,6 +4212,10 @@ enum {
> #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
> #define GEN8_CTX_PRIVILEGE (1 << 8)
> #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
> +#define GEN12_CTX_PRIORITY_MASK REG_GENMASK(10, 9)
> +#define GEN12_CTX_PRIORITY_HIGH REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 2)
> +#define GEN12_CTX_PRIORITY_NORMAL REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 1)
> +#define GEN12_CTX_PRIORITY_LOW REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 0)
>
> #define GEN8_CTX_ID_SHIFT 32
> #define GEN8_CTX_ID_WIDTH 21
>
Haven't checked bspec to check the bitfield but the mechanics look good.
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 7/8] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
@ 2021-09-07 17:19 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Matt Roper, Daniele Ceraolo Spurio, Tvrtko Ursulin,
Vinay Belgaumkar, Aravind Iddamsetty
We have to specify in the Render Control Unit Mode register
when CCS is enabled.
Bspec: 46034
Original-patch-by: Michel Thierry
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../drm/i915/gt/intel_execlists_submission.c | 26 +++++++++++++++++++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26 +++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 2b36ec7f3a04..046f7da67ba6 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2874,6 +2874,29 @@ static int execlists_resume(struct intel_engine_cs *engine)
return 0;
}
+static int gen12_rcs_resume(struct intel_engine_cs *engine)
+{
+ int ret;
+
+ ret = execlists_resume(engine);
+ if (ret)
+ return ret;
+
+ /*
+ * Multi Context programming.
+ * just need to program this register once no matter how many CCS
+ * engines there are. Since some of the CCS engines might be fused off,
+ * we can't do this as part of the init of a specific CCS and we do
+ * it during RCS init instead. RCS and all CCS engines are reset
+ * together, so post-reset re-init is covered as well.
+ */
+ if (CCS_MASK(engine->gt))
+ intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
+ _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
+
+ return 0;
+}
+
static void execlists_reset_prepare(struct intel_engine_cs *engine)
{
ENGINE_TRACE(engine, "depth<-%d\n",
@@ -3394,6 +3417,9 @@ static void rcs_submission_override(struct intel_engine_cs *engine)
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
break;
}
+
+ if (engine->class == RENDER_CLASS)
+ engine->resume = gen12_rcs_resume;
}
int intel_execlists_submission_setup(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 2f5bf7aa7e3b..db956255d076 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2350,6 +2350,29 @@ static bool guc_sched_engine_disabled(struct i915_sched_engine *sched_engine)
return !sched_engine->tasklet.callback;
}
+static int gen12_rcs_resume(struct intel_engine_cs *engine)
+{
+ int ret;
+
+ ret = guc_resume(engine);
+ if (ret)
+ return ret;
+
+ /*
+ * Multi Context programming.
+ * just need to program this register once no matter how many CCS
+ * engines there are. Since some of the CCS engines might be fused off,
+ * we can't do this as part of the init of a specific CCS and we do
+ * it during RCS init instead. RCS and all CCS engines are reset
+ * together, so post-reset re-init is covered as well.
+ */
+ if (CCS_MASK(engine->gt))
+ intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
+ _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
+
+ return 0;
+}
+
static void guc_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = guc_submit_request;
@@ -2464,6 +2487,9 @@ static void rcs_submission_override(struct intel_engine_cs *engine)
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
break;
}
+
+ if (engine->class == RENDER_CLASS)
+ engine->resume = gen12_rcs_resume;
}
static inline void guc_default_irqs(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5b68c02c35af..57f9456f8c61 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -498,6 +498,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define ECOBITS_PPGTT_CACHE64B (3 << 8)
#define ECOBITS_PPGTT_CACHE4B (0 << 8)
+#define GEN12_RCU_MODE _MMIO(0x14800)
+#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
+
#define GAB_CTL _MMIO(0x24000)
#define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread* [Intel-gfx] [PATCH 7/8] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE
@ 2021-09-07 17:19 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Matt Roper, Daniele Ceraolo Spurio, Tvrtko Ursulin,
Vinay Belgaumkar, Aravind Iddamsetty
We have to specify in the Render Control Unit Mode register
when CCS is enabled.
Bspec: 46034
Original-patch-by: Michel Thierry
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../drm/i915/gt/intel_execlists_submission.c | 26 +++++++++++++++++++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26 +++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 2b36ec7f3a04..046f7da67ba6 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2874,6 +2874,29 @@ static int execlists_resume(struct intel_engine_cs *engine)
return 0;
}
+static int gen12_rcs_resume(struct intel_engine_cs *engine)
+{
+ int ret;
+
+ ret = execlists_resume(engine);
+ if (ret)
+ return ret;
+
+ /*
+ * Multi Context programming.
+ * just need to program this register once no matter how many CCS
+ * engines there are. Since some of the CCS engines might be fused off,
+ * we can't do this as part of the init of a specific CCS and we do
+ * it during RCS init instead. RCS and all CCS engines are reset
+ * together, so post-reset re-init is covered as well.
+ */
+ if (CCS_MASK(engine->gt))
+ intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
+ _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
+
+ return 0;
+}
+
static void execlists_reset_prepare(struct intel_engine_cs *engine)
{
ENGINE_TRACE(engine, "depth<-%d\n",
@@ -3394,6 +3417,9 @@ static void rcs_submission_override(struct intel_engine_cs *engine)
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
break;
}
+
+ if (engine->class == RENDER_CLASS)
+ engine->resume = gen12_rcs_resume;
}
int intel_execlists_submission_setup(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 2f5bf7aa7e3b..db956255d076 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2350,6 +2350,29 @@ static bool guc_sched_engine_disabled(struct i915_sched_engine *sched_engine)
return !sched_engine->tasklet.callback;
}
+static int gen12_rcs_resume(struct intel_engine_cs *engine)
+{
+ int ret;
+
+ ret = guc_resume(engine);
+ if (ret)
+ return ret;
+
+ /*
+ * Multi Context programming.
+ * just need to program this register once no matter how many CCS
+ * engines there are. Since some of the CCS engines might be fused off,
+ * we can't do this as part of the init of a specific CCS and we do
+ * it during RCS init instead. RCS and all CCS engines are reset
+ * together, so post-reset re-init is covered as well.
+ */
+ if (CCS_MASK(engine->gt))
+ intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
+ _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
+
+ return 0;
+}
+
static void guc_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = guc_submit_request;
@@ -2464,6 +2487,9 @@ static void rcs_submission_override(struct intel_engine_cs *engine)
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
break;
}
+
+ if (engine->class == RENDER_CLASS)
+ engine->resume = gen12_rcs_resume;
}
static inline void guc_default_irqs(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5b68c02c35af..57f9456f8c61 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -498,6 +498,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define ECOBITS_PPGTT_CACHE64B (3 << 8)
#define ECOBITS_PPGTT_CACHE4B (0 << 8)
+#define GEN12_RCU_MODE _MMIO(0x14800)
+#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
+
#define GAB_CTL _MMIO(0x24000)
#define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH 7/8] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
@ 2021-09-08 14:10 ` Tvrtko Ursulin
-1 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 14:10 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: dri-devel, Daniele Ceraolo Spurio, Vinay Belgaumkar, Aravind Iddamsetty
On 07/09/2021 18:19, Matt Roper wrote:
> We have to specify in the Render Control Unit Mode register
> when CCS is enabled.
>
> Bspec: 46034
> Original-patch-by: Michel Thierry
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> .../drm/i915/gt/intel_execlists_submission.c | 26 +++++++++++++++++++
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26 +++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 3 files changed, 55 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 2b36ec7f3a04..046f7da67ba6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2874,6 +2874,29 @@ static int execlists_resume(struct intel_engine_cs *engine)
> return 0;
> }
>
> +static int gen12_rcs_resume(struct intel_engine_cs *engine)
> +{
> + int ret;
> +
> + ret = execlists_resume(engine);
> + if (ret)
> + return ret;
> +
> + /*
> + * Multi Context programming.
> + * just need to program this register once no matter how many CCS
Just
> + * engines there are. Since some of the CCS engines might be fused off,
> + * we can't do this as part of the init of a specific CCS and we do
> + * it during RCS init instead. RCS and all CCS engines are reset
I don't really understand the "can't" part - clearly it would be doable
if a specific vfunc was assigned to one ccs only, the one which is
present of course. Not saying that would be nicer since I think it has
it's own downside.
Perhaps nicest solution is to add an engine flag saying "enables rcu"
and then execlists and guc resume check that and do stuff?
No strong opinion yet, just discussing.
> + * together, so post-reset re-init is covered as well.
> + */
> + if (CCS_MASK(engine->gt))
> + intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
> + _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
> +
> + return 0;
> +}
> +
> static void execlists_reset_prepare(struct intel_engine_cs *engine)
> {
> ENGINE_TRACE(engine, "depth<-%d\n",
> @@ -3394,6 +3417,9 @@ static void rcs_submission_override(struct intel_engine_cs *engine)
> engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
> break;
> }
> +
> + if (engine->class == RENDER_CLASS)
> + engine->resume = gen12_rcs_resume;
> }
>
> int intel_execlists_submission_setup(struct intel_engine_cs *engine)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 2f5bf7aa7e3b..db956255d076 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -2350,6 +2350,29 @@ static bool guc_sched_engine_disabled(struct i915_sched_engine *sched_engine)
> return !sched_engine->tasklet.callback;
> }
>
> +static int gen12_rcs_resume(struct intel_engine_cs *engine)
> +{
> + int ret;
> +
> + ret = guc_resume(engine);
> + if (ret)
> + return ret;
> +
> + /*
> + * Multi Context programming.
> + * just need to program this register once no matter how many CCS
> + * engines there are. Since some of the CCS engines might be fused off,
> + * we can't do this as part of the init of a specific CCS and we do
> + * it during RCS init instead. RCS and all CCS engines are reset
> + * together, so post-reset re-init is covered as well.
> + */
> + if (CCS_MASK(engine->gt))
> + intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
> + _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
Duplicating the write from gen12_rcs_resume looks passable but when with
the whole comment then hmm.. How about a helper is added which both
would call? Like intel_engine_enable_rcu_mode() or something?
Regards,
Tvrtko
> +
> + return 0;
> +}
> +
> static void guc_set_default_submission(struct intel_engine_cs *engine)
> {
> engine->submit_request = guc_submit_request;
> @@ -2464,6 +2487,9 @@ static void rcs_submission_override(struct intel_engine_cs *engine)
> engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
> break;
> }
> +
> + if (engine->class == RENDER_CLASS)
> + engine->resume = gen12_rcs_resume;
> }
>
> static inline void guc_default_irqs(struct intel_engine_cs *engine)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5b68c02c35af..57f9456f8c61 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -498,6 +498,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define ECOBITS_PPGTT_CACHE64B (3 << 8)
> #define ECOBITS_PPGTT_CACHE4B (0 << 8)
>
> +#define GEN12_RCU_MODE _MMIO(0x14800)
> +#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
> +
> #define GAB_CTL _MMIO(0x24000)
> #define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [Intel-gfx] [PATCH 7/8] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE
@ 2021-09-08 14:10 ` Tvrtko Ursulin
0 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 14:10 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: dri-devel, Daniele Ceraolo Spurio, Vinay Belgaumkar, Aravind Iddamsetty
On 07/09/2021 18:19, Matt Roper wrote:
> We have to specify in the Render Control Unit Mode register
> when CCS is enabled.
>
> Bspec: 46034
> Original-patch-by: Michel Thierry
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> .../drm/i915/gt/intel_execlists_submission.c | 26 +++++++++++++++++++
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26 +++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 3 files changed, 55 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 2b36ec7f3a04..046f7da67ba6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2874,6 +2874,29 @@ static int execlists_resume(struct intel_engine_cs *engine)
> return 0;
> }
>
> +static int gen12_rcs_resume(struct intel_engine_cs *engine)
> +{
> + int ret;
> +
> + ret = execlists_resume(engine);
> + if (ret)
> + return ret;
> +
> + /*
> + * Multi Context programming.
> + * just need to program this register once no matter how many CCS
Just
> + * engines there are. Since some of the CCS engines might be fused off,
> + * we can't do this as part of the init of a specific CCS and we do
> + * it during RCS init instead. RCS and all CCS engines are reset
I don't really understand the "can't" part - clearly it would be doable
if a specific vfunc was assigned to one ccs only, the one which is
present of course. Not saying that would be nicer since I think it has
it's own downside.
Perhaps nicest solution is to add an engine flag saying "enables rcu"
and then execlists and guc resume check that and do stuff?
No strong opinion yet, just discussing.
> + * together, so post-reset re-init is covered as well.
> + */
> + if (CCS_MASK(engine->gt))
> + intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
> + _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
> +
> + return 0;
> +}
> +
> static void execlists_reset_prepare(struct intel_engine_cs *engine)
> {
> ENGINE_TRACE(engine, "depth<-%d\n",
> @@ -3394,6 +3417,9 @@ static void rcs_submission_override(struct intel_engine_cs *engine)
> engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
> break;
> }
> +
> + if (engine->class == RENDER_CLASS)
> + engine->resume = gen12_rcs_resume;
> }
>
> int intel_execlists_submission_setup(struct intel_engine_cs *engine)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 2f5bf7aa7e3b..db956255d076 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -2350,6 +2350,29 @@ static bool guc_sched_engine_disabled(struct i915_sched_engine *sched_engine)
> return !sched_engine->tasklet.callback;
> }
>
> +static int gen12_rcs_resume(struct intel_engine_cs *engine)
> +{
> + int ret;
> +
> + ret = guc_resume(engine);
> + if (ret)
> + return ret;
> +
> + /*
> + * Multi Context programming.
> + * just need to program this register once no matter how many CCS
> + * engines there are. Since some of the CCS engines might be fused off,
> + * we can't do this as part of the init of a specific CCS and we do
> + * it during RCS init instead. RCS and all CCS engines are reset
> + * together, so post-reset re-init is covered as well.
> + */
> + if (CCS_MASK(engine->gt))
> + intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
> + _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
Duplicating the write from gen12_rcs_resume looks passable but when with
the whole comment then hmm.. How about a helper is added which both
would call? Like intel_engine_enable_rcu_mode() or something?
Regards,
Tvrtko
> +
> + return 0;
> +}
> +
> static void guc_set_default_submission(struct intel_engine_cs *engine)
> {
> engine->submit_request = guc_submit_request;
> @@ -2464,6 +2487,9 @@ static void rcs_submission_override(struct intel_engine_cs *engine)
> engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
> break;
> }
> +
> + if (engine->class == RENDER_CLASS)
> + engine->resume = gen12_rcs_resume;
> }
>
> static inline void guc_default_irqs(struct intel_engine_cs *engine)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5b68c02c35af..57f9456f8c61 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -498,6 +498,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define ECOBITS_PPGTT_CACHE64B (3 << 8)
> #define ECOBITS_PPGTT_CACHE4B (0 << 8)
>
> +#define GEN12_RCU_MODE _MMIO(0x14800)
> +#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
> +
> #define GAB_CTL _MMIO(0x24000)
> #define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 8/8] drm/i915/xehp: Extend uninterruptible OpenCL workloads to CCS
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
@ 2021-09-07 17:19 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, John Harrison, Matt Roper
From: John Harrison <John.C.Harrison@Intel.com>
Now that OpenCL workloads can run on the compute engine, we need to set
preempt_timeout_ms = 0 on the CCS engines too.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 2f719f0ecac3..7e6ac0ae1f07 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -377,16 +377,17 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
engine->props.timeslice_duration_ms =
CONFIG_DRM_I915_TIMESLICE_DURATION;
- /* Override to uninterruptible for OpenCL workloads. */
- if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
- engine->props.preempt_timeout_ms = 0;
-
/* features common between engines sharing EUs */
if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
}
+ /* Override to uninterruptible for OpenCL workloads. */
+ if (GRAPHICS_VER(i915) == 12 &&
+ engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
+ engine->props.preempt_timeout_ms = 0;
+
engine->defaults = engine->props; /* never to change again */
engine->context_size = intel_engine_context_size(gt, engine->class);
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread* [Intel-gfx] [PATCH 8/8] drm/i915/xehp: Extend uninterruptible OpenCL workloads to CCS
@ 2021-09-07 17:19 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2021-09-07 17:19 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, John Harrison, Matt Roper
From: John Harrison <John.C.Harrison@Intel.com>
Now that OpenCL workloads can run on the compute engine, we need to set
preempt_timeout_ms = 0 on the CCS engines too.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 2f719f0ecac3..7e6ac0ae1f07 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -377,16 +377,17 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
engine->props.timeslice_duration_ms =
CONFIG_DRM_I915_TIMESLICE_DURATION;
- /* Override to uninterruptible for OpenCL workloads. */
- if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
- engine->props.preempt_timeout_ms = 0;
-
/* features common between engines sharing EUs */
if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
}
+ /* Override to uninterruptible for OpenCL workloads. */
+ if (GRAPHICS_VER(i915) == 12 &&
+ engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
+ engine->props.preempt_timeout_ms = 0;
+
engine->defaults = engine->props; /* never to change again */
engine->context_size = intel_engine_context_size(gt, engine->class);
--
2.25.4
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [Intel-gfx] [PATCH 8/8] drm/i915/xehp: Extend uninterruptible OpenCL workloads to CCS
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
(?)
@ 2021-09-08 14:15 ` Tvrtko Ursulin
-1 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2021-09-08 14:15 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel, John Harrison
On 07/09/2021 18:19, Matt Roper wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Now that OpenCL workloads can run on the compute engine, we need to set
> preempt_timeout_ms = 0 on the CCS engines too.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 2f719f0ecac3..7e6ac0ae1f07 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -377,16 +377,17 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
> engine->props.timeslice_duration_ms =
> CONFIG_DRM_I915_TIMESLICE_DURATION;
>
> - /* Override to uninterruptible for OpenCL workloads. */
> - if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
> - engine->props.preempt_timeout_ms = 0;
> -
> /* features common between engines sharing EUs */
> if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
> engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
> engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
> }
>
> + /* Override to uninterruptible for OpenCL workloads. */
> + if (GRAPHICS_VER(i915) == 12 &&
> + engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
> + engine->props.preempt_timeout_ms = 0;
> +
> engine->defaults = engine->props; /* never to change again */
>
> engine->context_size = intel_engine_context_size(gt, engine->class);
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Xe_HP compute engines
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
` (8 preceding siblings ...)
(?)
@ 2021-09-07 20:21 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2021-09-07 20:21 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: Introduce Xe_HP compute engines
URL : https://patchwork.freedesktop.org/series/94450/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f33a9b39f861 drm/i915/xehp: Define compute class and engine
-:13: WARNING:BAD_SIGN_OFF: Non-standard signature: Original-patch-by:
#13:
Original-patch-by: Michel Thierry
-:13: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Michel Thierry'
#13:
Original-patch-by: Michel Thierry
total: 1 errors, 1 warnings, 0 checks, 150 lines checked
5f332495a86f drm/i915/xehp: CCS shares the render reset domain
-:16: WARNING:BAD_SIGN_OFF: Non-standard signature: Original-patch-by:
#16:
Original-patch-by: Michel Thierry
-:16: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Michel Thierry'
#16:
Original-patch-by: Michel Thierry
total: 1 errors, 1 warnings, 0 checks, 10 lines checked
0b6621dcfaa4 drm/i915/xehp: Add Compute CS IRQ handlers
-:15: WARNING:BAD_SIGN_OFF: Non-standard signature: Original-patch-by:
#15:
Original-patch-by: Michel Thierry
-:15: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Michel Thierry'
#15:
Original-patch-by: Michel Thierry
total: 1 errors, 1 warnings, 0 checks, 68 lines checked
d2323e9fcd91 drm/i915/xehp: CCS should use RCS setup functions
-:19: WARNING:BAD_SIGN_OFF: Non-standard signature: Original-patch-by:
#19:
Original-patch-by: Michel Thierry
-:19: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Michel Thierry'
#19:
Original-patch-by: Michel Thierry
-:173: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#173: FILE: drivers/gpu/drm/i915/i915_reg.h:444:
+#define GEN8_R_PWR_CLK_STATE(base) _MMIO((base)+0xc8)
^
total: 1 errors, 1 warnings, 1 checks, 107 lines checked
cdf7c042c226 drm/i915/xehp: compute engine pipe_control
-:94: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#94: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:226:
+#define PIPE_CONTROL_AMFS_FLUSH (1<<25) /* gen12+ */
^
-:99: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#99: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:231:
+#define PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET (1<<19)
^
-:101: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#101: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:233:
+#define PIPE_CONTROL_PSD_SYNC (1<<17) /* gen11+ */
^
total: 0 errors, 0 warnings, 3 checks, 91 lines checked
f496f5a5ad27 drm/i915/xehp: Define context scheduling attributes in lrc descriptor
-:17: WARNING:BAD_SIGN_OFF: Non-standard signature: Original-patch-by:
#17:
Original-patch-by: Michel Thierry
-:17: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Michel Thierry'
#17:
Original-patch-by: Michel Thierry
total: 1 errors, 1 warnings, 0 checks, 56 lines checked
95bf9aa2b2bc drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE
-:10: WARNING:BAD_SIGN_OFF: Non-standard signature: Original-patch-by:
#10:
Original-patch-by: Michel Thierry
-:10: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Michel Thierry'
#10:
Original-patch-by: Michel Thierry
-:44: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#44: FILE: drivers/gpu/drm/i915/gt/intel_execlists_submission.c:2895:
+ intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
+ _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
-:88: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#88: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2371:
+ intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
+ _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
total: 1 errors, 1 warnings, 2 checks, 85 lines checked
a90e6b8ea6b8 drm/i915/xehp: Extend uninterruptible OpenCL workloads to CCS
^ permalink raw reply [flat|nested] 43+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Introduce Xe_HP compute engines
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
` (9 preceding siblings ...)
(?)
@ 2021-09-07 20:23 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2021-09-07 20:23 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: Introduce Xe_HP compute engines
URL : https://patchwork.freedesktop.org/series/94450/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
^ permalink raw reply [flat|nested] 43+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for i915: Introduce Xe_HP compute engines
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
` (10 preceding siblings ...)
(?)
@ 2021-09-07 20:53 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2021-09-07 20:53 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5958 bytes --]
== Series Details ==
Series: i915: Introduce Xe_HP compute engines
URL : https://patchwork.freedesktop.org/series/94450/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10558 -> Patchwork_20981
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/index.html
Known issues
------------
Here are the changes found in Patchwork_20981 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/fi-rkl-guc/igt@amdgpu/amd_basic@cs-gfx.html
* igt@i915_pm_rpm@module-reload:
- fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#1982] / [i915#2411])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/fi-tgl-y/igt@i915_pm_rpm@module-reload.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/fi-tgl-y/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [PASS][4] -> [INCOMPLETE][5] ([i915#2940])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: NOTRUN -> [DMESG-WARN][6] ([i915#3958])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: NOTRUN -> [INCOMPLETE][7] ([i915#3921])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600: NOTRUN -> [SKIP][8] ([fdo#109271]) +19 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/fi-snb-2600/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/fi-snb-2600/igt@kms_chamelium@hdmi-crc-fast.html
* igt@runner@aborted:
- fi-bsw-n3050: NOTRUN -> [FAIL][10] ([fdo#109271] / [i915#1436] / [i915#3428])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/fi-bsw-n3050/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4: [FAIL][11] ([i915#1888]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
* igt@i915_selftest@live@execlists:
- {fi-tgl-dsi}: [DMESG-FAIL][13] ([i915#1993]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/fi-tgl-dsi/igt@i915_selftest@live@execlists.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/fi-tgl-dsi/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_timelines:
- fi-rkl-guc: [INCOMPLETE][15] ([i915#4034]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3958]: https://gitlab.freedesktop.org/drm/intel/issues/3958
[i915#4034]: https://gitlab.freedesktop.org/drm/intel/issues/4034
Participating hosts (47 -> 40)
------------------------------
Additional (1): fi-snb-2600
Missing (8): fi-ilk-m540 bat-adls-5 bat-dg1-6 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10558 -> Patchwork_20981
CI-20190529: 20190529
CI_DRM_10558: 64862f208feb1857d95f2633da6b135b9c3e16cf @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6198: 0f17f38c3e5e2139e59f1458c149bb7a93c88bbf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20981: a90e6b8ea6b83f47749da478fd2714a1f7696cb9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a90e6b8ea6b8 drm/i915/xehp: Extend uninterruptible OpenCL workloads to CCS
95bf9aa2b2bc drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE
f496f5a5ad27 drm/i915/xehp: Define context scheduling attributes in lrc descriptor
cdf7c042c226 drm/i915/xehp: compute engine pipe_control
d2323e9fcd91 drm/i915/xehp: CCS should use RCS setup functions
0b6621dcfaa4 drm/i915/xehp: Add Compute CS IRQ handlers
5f332495a86f drm/i915/xehp: CCS shares the render reset domain
f33a9b39f861 drm/i915/xehp: Define compute class and engine
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/index.html
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^ permalink raw reply [flat|nested] 43+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for i915: Introduce Xe_HP compute engines
2021-09-07 17:19 ` [Intel-gfx] " Matt Roper
` (11 preceding siblings ...)
(?)
@ 2021-09-08 0:00 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2021-09-08 0:00 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30260 bytes --]
== Series Details ==
Series: i915: Introduce Xe_HP compute engines
URL : https://patchwork.freedesktop.org/series/94450/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10558_full -> Patchwork_20981_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_20981_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-snb: NOTRUN -> [DMESG-WARN][1] ([i915#3002])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-snb6/igt@gem_create@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: NOTRUN -> [DMESG-WARN][2] ([i915#180]) +1 similar issue
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-apl1/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl8/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +5 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-snb5/igt@gem_ctx_persistence@legacy-engines-mixed.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][6] -> [TIMEOUT][7] ([i915#2369] / [i915#3063] / [i915#3648])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-tglb7/igt@gem_eio@unwedge-stress.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_endless@dispatch@rcs0:
- shard-tglb: [PASS][8] -> [INCOMPLETE][9] ([i915#3778])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-tglb6/igt@gem_exec_endless@dispatch@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb6/igt@gem_exec_endless@dispatch@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: NOTRUN -> [FAIL][12] ([i915#2842]) +4 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb1/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-iclb7/igt@gem_exec_fair@basic-pace@vecs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb1/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2428])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-iclb6/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb2/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][18] ([i915#2658])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl3/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@access-control:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#3297])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb1/igt@gem_userptr_blits@access-control.html
* igt@gen9_exec_parse@basic-rejected:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#2856]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb2/igt@gen9_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@bb-start-out:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#2856])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb7/igt@gen9_exec_parse@bb-start-out.html
* igt@i915_pm_lpsp@screens-disabled:
- shard-tglb: NOTRUN -> [SKIP][22] ([i915#1902])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb1/igt@i915_pm_lpsp@screens-disabled.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][23] ([i915#3722])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3777]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
- shard-iclb: NOTRUN -> [SKIP][25] ([fdo#110723])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb7/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-tglb: NOTRUN -> [SKIP][26] ([fdo#111615])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb1/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3886]) +11 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl3/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][28] ([fdo#109278] / [i915#3886]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb7/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-aux-stride-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][29] ([i915#3689])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb2/igt@kms_ccs@pipe-d-bad-aux-stride-yf_tiled_ccs.html
* igt@kms_chamelium@hdmi-crc-fast:
- shard-iclb: NOTRUN -> [SKIP][30] ([fdo#109284] / [fdo#111827]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb2/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +18 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl3/igt@kms_chamelium@vga-hpd.html
* igt@kms_color_chamelium@pipe-a-ctm-0-25:
- shard-snb: NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827]) +14 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-snb5/igt@kms_color_chamelium@pipe-a-ctm-0-25.html
* igt@kms_color_chamelium@pipe-b-ctm-0-75:
- shard-tglb: NOTRUN -> [SKIP][33] ([fdo#109284] / [fdo#111827]) +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb1/igt@kms_color_chamelium@pipe-b-ctm-0-75.html
* igt@kms_color_chamelium@pipe-d-ctm-0-75:
- shard-iclb: NOTRUN -> [SKIP][34] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb7/igt@kms_color_chamelium@pipe-d-ctm-0-75.html
* igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
- shard-skl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl9/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-iclb: NOTRUN -> [SKIP][36] ([i915#3116])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb2/igt@kms_content_protection@dp-mst-type-1.html
- shard-tglb: NOTRUN -> [SKIP][37] ([i915#3116])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb2/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@srm:
- shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109300] / [fdo#111066])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb7/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109278] / [fdo#109279])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [PASS][40] -> [INCOMPLETE][41] ([i915#146] / [i915#300])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-512x170-onscreen:
- shard-tglb: NOTRUN -> [SKIP][42] ([fdo#109279] / [i915#3359])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-512x170-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-64x64-random:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109278]) +4 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb7/igt@kms_cursor_crc@pipe-d-cursor-64x64-random.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][44] -> [FAIL][45] ([i915#2346] / [i915#533])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-tglb: [PASS][46] -> [FAIL][47] ([i915#2346])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-tglb8/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb8/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-tglb: [PASS][48] -> [INCOMPLETE][49] ([i915#2411] / [i915#456])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-tglb1/igt@kms_fbcon_fbt@psr-suspend.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb7/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
- shard-skl: [PASS][50] -> [FAIL][51] ([i915#2122])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl5/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#2672])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-snb: NOTRUN -> [SKIP][53] ([fdo#109271]) +257 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-snb6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- shard-iclb: [PASS][54] -> [SKIP][55] ([i915#3701])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-skl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#2672])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-tglb: NOTRUN -> [SKIP][57] ([fdo#111825]) +12 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt:
- shard-skl: NOTRUN -> [SKIP][58] ([fdo#109271]) +23 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271]) +195 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109280]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][61] -> [FAIL][62] ([i915#1188])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][63] ([fdo#108145] / [i915#265]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][64] ([i915#265])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl7/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][66] ([fdo#112054])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb2/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5:
- shard-iclb: NOTRUN -> [SKIP][67] ([i915#658])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#658]) +3 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-tglb: NOTRUN -> [SKIP][69] ([i915#2920]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
- shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#658])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][71] -> [SKIP][72] ([fdo#109441]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb5/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-skl: [PASS][73] -> [INCOMPLETE][74] ([i915#198] / [i915#2828])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@nouveau_crc@pipe-b-source-outp-inactive:
- shard-iclb: NOTRUN -> [SKIP][75] ([i915#2530])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb7/igt@nouveau_crc@pipe-b-source-outp-inactive.html
* igt@nouveau_crc@pipe-d-source-rg:
- shard-tglb: NOTRUN -> [SKIP][76] ([i915#2530]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb2/igt@nouveau_crc@pipe-d-source-rg.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][77] -> [FAIL][78] ([i915#1542])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl3/igt@perf@polling-parameterized.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl9/igt@perf@polling-parameterized.html
* igt@runner@aborted:
- shard-snb: NOTRUN -> [FAIL][79] ([i915#3002])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-snb6/igt@runner@aborted.html
* igt@sysfs_clients@busy:
- shard-skl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2994])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl9/igt@sysfs_clients@busy.html
* igt@sysfs_clients@recycle-many:
- shard-apl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#2994])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl3/igt@sysfs_clients@recycle-many.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- shard-skl: [TIMEOUT][82] ([i915#2369] / [i915#3063]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl1/igt@gem_eio@unwedge-stress.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl4/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][84] ([i915#2842]) -> [PASS][85] +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][86] ([i915#2842]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [SKIP][88] ([fdo#109271]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-kbl3/igt@gem_exec_fair@basic-pace@rcs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-apl: [DMESG-WARN][90] ([i915#180]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-apl3/igt@gem_exec_suspend@basic-s3.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl3/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_whisper@basic-sync:
- shard-skl: [INCOMPLETE][92] ([i915#2944]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl1/igt@gem_exec_whisper@basic-sync.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl4/igt@gem_exec_whisper@basic-sync.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][94] ([i915#2190]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-tglb7/igt@gem_huc_copy@huc-copy.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb5/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap_offset@clear:
- shard-skl: [FAIL][96] ([i915#1888] / [i915#3160]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl7/igt@gem_mmap_offset@clear.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl7/igt@gem_mmap_offset@clear.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-skl: [DMESG-WARN][98] ([i915#1982]) -> [PASS][99] +3 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl7/igt@i915_module_load@reload-with-fault-injection.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl8/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][100] ([i915#454]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb4/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][102] ([i915#3921]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-snb5/igt@i915_selftest@live@hangcheck.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-snb5/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@forcewake:
- shard-tglb: [INCOMPLETE][104] ([i915#2411] / [i915#456]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-tglb7/igt@i915_suspend@forcewake.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-tglb1/igt@i915_suspend@forcewake.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][106] ([i915#2346]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled:
- shard-iclb: [DMESG-WARN][108] -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-iclb2/igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb7/igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [FAIL][110] ([i915#79]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [FAIL][112] ([i915#2122]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-iclb: [SKIP][114] ([i915#3701]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][116] ([fdo#108145] / [i915#265]) -> [PASS][117] +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][118] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][119] +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-iclb4/igt@kms_psr2_su@frontbuffer.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [SKIP][120] ([fdo#109441]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-iclb4/igt@kms_psr@psr2_sprite_render.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
#### Warnings ####
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-kbl: [INCOMPLETE][122] ([i915#794]) -> [DMESG-WARN][123] ([i915#180])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-iclb: [SKIP][124] ([i915#658]) -> [SKIP][125] ([i915#2920])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-iclb6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][126] ([i915#2920]) -> [SKIP][127] ([i915#658]) +2 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][128], [FAIL][129]) ([i915#3002] / [i915#3363]) -> ([FAIL][130], [FAIL][131], [FAIL][132]) ([i915#1436] / [i915#180] / [i915#3002] / [i915#3363])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-kbl1/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-kbl7/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-kbl7/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-kbl2/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-kbl2/igt@runner@aborted.html
- shard-apl: ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][138], [FAIL][139], [FAIL][140]) ([i915#180] / [i915#3002] / [i915#3363])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-apl3/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-apl3/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-apl2/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-apl3/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-apl2/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl7/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl8/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-apl6/igt@runner@aborted.html
- shard-skl: ([FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144]) ([i915#2029] / [i915#2263] / [i915#2722] / [i915#3002] / [i915#3363]) -> [FAIL][145] ([i915#3002] / [i915#3363])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl3/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl7/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl1/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10558/shard-skl1/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/shard-skl7/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20981/index.html
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