[PATCH v3 8/9] arm64: dts: imx8mm-evk: add the pcie support on imx8mm evk board

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From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, tharvey@gateworks.com, kishon@ti.com,
	vkoul@kernel.org, robh@kernel.org, galak@kernel.crashing.org,
	shawnguo@kernel.org
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@pengutronix.de,
	linux-imx@nxp.com, Richard Zhu <hongxing.zhu@nxp.com>
Subject: [PATCH v3 8/9] arm64: dts: imx8mm-evk: add the pcie support on imx8mm evk board
Date: Tue, 12 Oct 2021 16:41:17 +0800	[thread overview]
Message-ID: <1634028078-2387-9-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1634028078-2387-1-git-send-email-hongxing.zhu@nxp.com>

Add the PCIe support on i.MX8MM EVK board.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 2d0684ac82f6..5ce43daa0c8b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -31,6 +31,23 @@ status {
 		};
 	};
 
+	pcie0_refclk: pcie0-refclk {
+		compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+	};
+
+	reg_pcie0_gpio: regulator-pcie-gpio {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pcie0_reg>;
+		regulator-name = "MPCIE_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2 {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
@@ -296,6 +313,22 @@ &pcie_phy {
 	status = "okay";
 };
 
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
+		 <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>;
+	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
+	assigned-clock-rates = <10000000>, <250000000>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+				 <&clk IMX8MM_SYS_PLL2_250M>;
+	vpcie-supply = <&reg_pcie0_gpio>;
+	status = "okay";
+};
+
 &sai3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sai3>;
@@ -413,6 +446,19 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
 		>;
 	};
 
+	pinctrl_pcie0: pcie0grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61
+			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41
+		>;
+	};
+
+	pinctrl_pcie0_reg: pcie0reggrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x41
+		>;
+	};
+
 	pinctrl_pmic: pmicirqgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141
-- 
2.25.1

WARNING: multiple messages have this Message-ID (diff)

From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, tharvey@gateworks.com, kishon@ti.com,
	vkoul@kernel.org, robh@kernel.org, galak@kernel.crashing.org,
	shawnguo@kernel.org
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@pengutronix.de,
	linux-imx@nxp.com, Richard Zhu <hongxing.zhu@nxp.com>
Subject: [PATCH v3 8/9] arm64: dts: imx8mm-evk: add the pcie support on imx8mm evk board
Date: Tue, 12 Oct 2021 16:41:17 +0800	[thread overview]
Message-ID: <1634028078-2387-9-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1634028078-2387-1-git-send-email-hongxing.zhu@nxp.com>

Add the PCIe support on i.MX8MM EVK board.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 2d0684ac82f6..5ce43daa0c8b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -31,6 +31,23 @@ status {
 		};
 	};
 
+	pcie0_refclk: pcie0-refclk {
+		compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+	};
+
+	reg_pcie0_gpio: regulator-pcie-gpio {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pcie0_reg>;
+		regulator-name = "MPCIE_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2 {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
@@ -296,6 +313,22 @@ &pcie_phy {
 	status = "okay";
 };
 
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
+		 <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>;
+	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
+	assigned-clock-rates = <10000000>, <250000000>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+				 <&clk IMX8MM_SYS_PLL2_250M>;
+	vpcie-supply = <&reg_pcie0_gpio>;
+	status = "okay";
+};
+
 &sai3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sai3>;
@@ -413,6 +446,19 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
 		>;
 	};
 
+	pinctrl_pcie0: pcie0grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61
+			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41
+		>;
+	};
+
+	pinctrl_pcie0_reg: pcie0reggrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x41
+		>;
+	};
+
 	pinctrl_pmic: pmicirqgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141
-- 
2.25.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)

From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, tharvey@gateworks.com, kishon@ti.com,
	vkoul@kernel.org, robh@kernel.org, galak@kernel.crashing.org,
	shawnguo@kernel.org
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@pengutronix.de,
	linux-imx@nxp.com, Richard Zhu <hongxing.zhu@nxp.com>
Subject: [PATCH v3 8/9] arm64: dts: imx8mm-evk: add the pcie support on imx8mm evk board
Date: Tue, 12 Oct 2021 16:41:17 +0800	[thread overview]
Message-ID: <1634028078-2387-9-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1634028078-2387-1-git-send-email-hongxing.zhu@nxp.com>

Add the PCIe support on i.MX8MM EVK board.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 2d0684ac82f6..5ce43daa0c8b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -31,6 +31,23 @@ status {
 		};
 	};
 
+	pcie0_refclk: pcie0-refclk {
+		compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+	};
+
+	reg_pcie0_gpio: regulator-pcie-gpio {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pcie0_reg>;
+		regulator-name = "MPCIE_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2 {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
@@ -296,6 +313,22 @@ &pcie_phy {
 	status = "okay";
 };
 
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
+		 <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>;
+	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
+	assigned-clock-rates = <10000000>, <250000000>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+				 <&clk IMX8MM_SYS_PLL2_250M>;
+	vpcie-supply = <&reg_pcie0_gpio>;
+	status = "okay";
+};
+
 &sai3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sai3>;
@@ -413,6 +446,19 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
 		>;
 	};
 
+	pinctrl_pcie0: pcie0grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61
+			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41
+		>;
+	};
+
+	pinctrl_pcie0_reg: pcie0reggrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x41
+		>;
+	};
+
 	pinctrl_pmic: pmicirqgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141
-- 
2.25.1


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

next prev parent reply	other threads:[~2021-10-12  9:06 UTC|newest]

Thread overview: 144+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-12  8:41 [PATCH v3 0/9] add the imx8m pcie phy driver and imx8mm pcie support Richard Zhu
2021-10-12  8:41 ` Richard Zhu
2021-10-12  8:41 ` Richard Zhu
2021-10-12  8:41 ` [PATCH v3 1/9] dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phy Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-12  8:41 ` [PATCH v3 2/9] dt-bindings: phy: add imx8 pcie phy driver support Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-12 13:18   ` Rob Herring
2021-10-12 13:18     ` Rob Herring
2021-10-12 13:18     ` Rob Herring
2021-10-12 23:46     ` Richard Zhu
2021-10-12 23:46       ` Richard Zhu
2021-10-12 23:46       ` Richard Zhu
2021-10-12  8:41 ` [PATCH v3 3/9] arm64: dts: imx8mm: add the pcie phy support Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-15 18:30   ` Lucas Stach
2021-10-15 18:30     ` Lucas Stach
2021-10-15 18:30     ` Lucas Stach
2021-10-22  1:57     ` Richard Zhu
2021-10-22  1:57       ` Richard Zhu
2021-10-22  1:57       ` Richard Zhu
2021-10-12  8:41 ` [PATCH v3 4/9] arm64: dts: imx8mm-evk: " Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-15 18:32   ` Lucas Stach
2021-10-15 18:32     ` Lucas Stach
2021-10-15 18:32     ` Lucas Stach
2021-10-22  1:58     ` Richard Zhu
2021-10-22  1:58       ` Richard Zhu
2021-10-22  1:58       ` Richard Zhu
2021-10-12  8:41 ` [PATCH v3 5/9] phy: freescale: pcie: initialize the imx8 pcie standalone phy driver Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-15 18:55   ` Lucas Stach
2021-10-15 18:55     ` Lucas Stach
2021-10-15 18:55     ` Lucas Stach
2021-10-22  4:30     ` Richard Zhu
2021-10-22  4:30       ` Richard Zhu
2021-10-22  4:30       ` Richard Zhu
2021-10-21 16:00   ` Tim Harvey
2021-10-21 16:00     ` Tim Harvey
2021-10-21 16:00     ` Tim Harvey
2021-10-22  0:54     ` Richard Zhu
2021-10-22  0:54       ` Richard Zhu
2021-10-22  0:54       ` Richard Zhu
2021-10-12  8:41 ` [PATCH v3 6/9] dt-bindings: imx6q-pcie: Add PHY phandles and name properties Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-18 19:18   ` Rob Herring
2021-10-18 19:18     ` Rob Herring
2021-10-18 19:18     ` Rob Herring
2021-10-22  2:04     ` Richard Zhu
2021-10-22  2:04       ` Richard Zhu
2021-10-22  2:04       ` Richard Zhu
2021-10-12  8:41 ` [PATCH v3 7/9] arm64: dts: imx8mm: add the pcie support Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-12  8:41 ` Richard Zhu [this message]
2021-10-12  8:41   ` [PATCH v3 8/9] arm64: dts: imx8mm-evk: add the pcie support on imx8mm evk board Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-15 19:03   ` Lucas Stach
2021-10-15 19:03     ` Lucas Stach
2021-10-15 19:03     ` Lucas Stach
2021-10-22  2:07     ` Richard Zhu
2021-10-22  2:07       ` Richard Zhu
2021-10-22  2:07       ` Richard Zhu
2021-10-12  8:41 ` [PATCH v3 9/9] PCI: imx: add the imx8mm pcie support Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-12  8:41   ` Richard Zhu
2021-10-13 12:45   ` Matthias Schiffer
2021-10-13 12:45     ` Matthias Schiffer
2021-10-13 12:45     ` Matthias Schiffer
2021-10-14  1:20     ` Richard Zhu
2021-10-14  1:20       ` Richard Zhu
2021-10-14  1:20       ` Richard Zhu
2021-10-15 19:00   ` Lucas Stach
2021-10-15 19:00     ` Lucas Stach
2021-10-15 19:00     ` Lucas Stach
2021-10-22  2:06     ` Richard Zhu
2021-10-22  2:06       ` Richard Zhu
2021-10-22  2:06       ` Richard Zhu
2021-10-15 19:58 ` [PATCH v3 0/9] add the imx8m pcie phy driver and " Tim Harvey
2021-10-15 19:58   ` Tim Harvey
2021-10-15 19:58   ` Tim Harvey
2021-10-19  2:10   ` Richard Zhu
2021-10-19  2:10     ` Richard Zhu
2021-10-19  2:10     ` Richard Zhu
2021-10-19 15:52     ` Tim Harvey
2021-10-19 15:52       ` Tim Harvey
2021-10-19 15:52       ` Tim Harvey
2021-10-20  2:10       ` Richard Zhu
2021-10-20  2:10         ` Richard Zhu
2021-10-20  2:10         ` Richard Zhu
2021-10-20 21:22         ` Tim Harvey
2021-10-20 21:22           ` Tim Harvey
2021-10-20 21:22           ` Tim Harvey
2021-10-21  3:32           ` Richard Zhu
2021-10-21  3:32             ` Richard Zhu
2021-10-21  3:32             ` Richard Zhu
2021-10-21 16:25             ` Tim Harvey
2021-10-21 16:25               ` Tim Harvey
2021-10-21 16:25               ` Tim Harvey
2021-10-22  0:43               ` Richard Zhu
2021-10-22  0:43                 ` Richard Zhu
2021-10-22  0:43                 ` Richard Zhu
2021-10-22 15:59                 ` Tim Harvey
2021-10-22 15:59                   ` Tim Harvey
2021-10-22 15:59                   ` Tim Harvey
2021-10-22 16:55                   ` Tim Harvey
2021-10-22 16:55                     ` Tim Harvey
2021-10-22 16:55                     ` Tim Harvey
2021-10-25  2:12                     ` Richard Zhu
2021-10-25  2:12                       ` Richard Zhu
2021-10-25  2:12                       ` Richard Zhu
2021-10-25  7:23                       ` Richard Zhu
2021-10-25  7:23                         ` Richard Zhu
2021-10-25  7:23                         ` Richard Zhu
2021-10-25 17:14                         ` Tim Harvey
2021-10-25 17:14                           ` Tim Harvey
2021-10-25 17:14                           ` Tim Harvey
2021-10-26  5:41                           ` Richard Zhu
2021-10-26  5:41                             ` Richard Zhu
2021-10-26  5:41                             ` Richard Zhu
2021-10-26 16:06                             ` Tim Harvey
2021-10-26 16:06                               ` Tim Harvey
2021-10-26 16:06                               ` Tim Harvey
2021-10-27  6:18                               ` Richard Zhu
2021-10-27  6:18                                 ` Richard Zhu
2021-10-27  6:18                                 ` Richard Zhu
2021-10-27 15:40                                 ` Tim Harvey
2021-10-27 15:40                                   ` Tim Harvey
2021-10-27 15:40                                   ` Tim Harvey
2021-10-28  1:51                                   ` Richard Zhu
2021-10-28  1:51                                     ` Richard Zhu
2021-10-28  1:51                                     ` Richard Zhu
2021-10-26 15:56 ` Marcel Ziswiler
2021-10-26 15:56   ` Marcel Ziswiler
2021-10-26 15:56   ` Marcel Ziswiler
2021-10-27  1:39   ` Richard Zhu
2021-10-27  1:39     ` Richard Zhu
2021-10-27  1:39     ` Richard Zhu

find likely ancestor, descendant, or conflicting patches for this message:
dfblob:2d0684ac82f dfblob:2d0684ac82f dfblob:2d0684ac82f
dfblob:5ce43daa0c8 dfblob:5ce43daa0c8 dfblob:5ce43daa0c8
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