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* [PATCH v5 0/5] Use drm_clflush* instead of clflush
@ 2022-02-04 16:37 ` Michael Cheng
  0 siblings, 0 replies; 24+ messages in thread
From: Michael Cheng @ 2022-02-04 16:37 UTC (permalink / raw)
  To: intel-gfx
  Cc: tvrtko.ursulin, michael.cheng, wayne.boyer, casey.g.bowman,
	lucas.demarchi, dri-devel

This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.

v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)

v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran

v4: Remove extra memory barriers 

v5: s/cache_clflush_range/drm_clflush_virt_range

Michael Cheng (5):
  drm/i915/gt: Re-work intel_write_status_page
  drm/i915/gt: Drop invalidate_csb_entries
  drm/i915/gt: Re-work reset_csb
  drm/i915/: Re-work clflush_write32
  drm/i915/gt: replace cache_clflush_range

 .../gpu/drm/i915/gem/i915_gem_execbuffer.c    |  8 +++-----
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c          | 12 ++++++------
 drivers/gpu/drm/i915/gt/intel_engine.h        | 13 ++++---------
 .../drm/i915/gt/intel_execlists_submission.c  | 19 ++++++-------------
 drivers/gpu/drm/i915/gt/intel_gtt.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c         |  2 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
 7 files changed, 22 insertions(+), 36 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH v5 0/5] Use drm_clflush* instead of clflush
@ 2022-02-04 16:37 ` Michael Cheng
  0 siblings, 0 replies; 24+ messages in thread
From: Michael Cheng @ 2022-02-04 16:37 UTC (permalink / raw)
  To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel

This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.

v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)

v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran

v4: Remove extra memory barriers 

v5: s/cache_clflush_range/drm_clflush_virt_range

Michael Cheng (5):
  drm/i915/gt: Re-work intel_write_status_page
  drm/i915/gt: Drop invalidate_csb_entries
  drm/i915/gt: Re-work reset_csb
  drm/i915/: Re-work clflush_write32
  drm/i915/gt: replace cache_clflush_range

 .../gpu/drm/i915/gem/i915_gem_execbuffer.c    |  8 +++-----
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c          | 12 ++++++------
 drivers/gpu/drm/i915/gt/intel_engine.h        | 13 ++++---------
 .../drm/i915/gt/intel_execlists_submission.c  | 19 ++++++-------------
 drivers/gpu/drm/i915/gt/intel_gtt.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c         |  2 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
 7 files changed, 22 insertions(+), 36 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 24+ messages in thread
* [PATCH v5 1/5] drm/i915/gt: Re-work intel_write_status_page
  2022-02-04 16:37 ` [Intel-gfx] " Michael Cheng
@ 2022-02-04 16:37   ` Michael Cheng
  -1 siblings, 0 replies; 24+ messages in thread
From: Michael Cheng @ 2022-02-04 16:37 UTC (permalink / raw)
  To: intel-gfx
  Cc: tvrtko.ursulin, michael.cheng, wayne.boyer, casey.g.bowman,
	lucas.demarchi, dri-devel

Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 0e353d8c2bc8..986777c2430d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -4,6 +4,7 @@
 
 #include <asm/cacheflush.h>
 #include <drm/drm_util.h>
+#include <drm/drm_cache.h>
 
 #include <linux/hashtable.h>
 #include <linux/irq_work.h>
@@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
 	 * of extra paranoia to try and ensure that the HWS takes the value
 	 * we give and that it doesn't end up trapped inside the CPU!
 	 */
-	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
-		mb();
-		clflush(&engine->status_page.addr[reg]);
-		engine->status_page.addr[reg] = value;
-		clflush(&engine->status_page.addr[reg]);
-		mb();
-	} else {
-		WRITE_ONCE(engine->status_page.addr[reg], value);
-	}
+	drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
+	WRITE_ONCE(engine->status_page.addr[reg], value);
+	drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
 }
 
 /*
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH v5 1/5] drm/i915/gt: Re-work intel_write_status_page
@ 2022-02-04 16:37   ` Michael Cheng
  0 siblings, 0 replies; 24+ messages in thread
From: Michael Cheng @ 2022-02-04 16:37 UTC (permalink / raw)
  To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel

Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 0e353d8c2bc8..986777c2430d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -4,6 +4,7 @@
 
 #include <asm/cacheflush.h>
 #include <drm/drm_util.h>
+#include <drm/drm_cache.h>
 
 #include <linux/hashtable.h>
 #include <linux/irq_work.h>
@@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
 	 * of extra paranoia to try and ensure that the HWS takes the value
 	 * we give and that it doesn't end up trapped inside the CPU!
 	 */
-	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
-		mb();
-		clflush(&engine->status_page.addr[reg]);
-		engine->status_page.addr[reg] = value;
-		clflush(&engine->status_page.addr[reg]);
-		mb();
-	} else {
-		WRITE_ONCE(engine->status_page.addr[reg], value);
-	}
+	drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
+	WRITE_ONCE(engine->status_page.addr[reg], value);
+	drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
 }
 
 /*
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 2/5] drm/i915/gt: Drop invalidate_csb_entries
  2022-02-04 16:37 ` [Intel-gfx] " Michael Cheng
@ 2022-02-04 16:37   ` Michael Cheng
  -1 siblings, 0 replies; 24+ messages in thread
From: Michael Cheng @ 2022-02-04 16:37 UTC (permalink / raw)
  To: intel-gfx
  Cc: tvrtko.ursulin, michael.cheng, wayne.boyer, casey.g.bowman,
	lucas.demarchi, dri-devel

Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.

v2(Michael Cheng): Drop invalidate_csb_entries function and directly
		   invoke drm_clflush_virt_range. Thanks to Tvrtko for the
		   sugguestion.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9bb7c863172f..7500c06562da 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
 	return inactive;
 }
 
-static void invalidate_csb_entries(const u64 *first, const u64 *last)
-{
-	clflush((void *)first);
-	clflush((void *)last);
-}
-
 /*
  * Starting with Gen12, the status has a new format:
  *
@@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
 	 * the wash as hardware, working or not, will need to do the
 	 * invalidation before.
 	 */
-	invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
+	drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
 
 	/*
 	 * We assume that any event reflects a change in context flow
@@ -2783,8 +2777,8 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
 
 	/* Check that the GPU does indeed update the CSB entries! */
 	memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
-	invalidate_csb_entries(&execlists->csb_status[0],
-			       &execlists->csb_status[reset_value]);
+	drm_clflush_virt_range(&execlists->csb_status[0],
+				sizeof(&execlists->csb_status[reset_value]));
 
 	/* Once more for luck and our trusty paranoia */
 	ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH v5 2/5] drm/i915/gt: Drop invalidate_csb_entries
@ 2022-02-04 16:37   ` Michael Cheng
  0 siblings, 0 replies; 24+ messages in thread
From: Michael Cheng @ 2022-02-04 16:37 UTC (permalink / raw)
  To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel

Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.

v2(Michael Cheng): Drop invalidate_csb_entries function and directly
		   invoke drm_clflush_virt_range. Thanks to Tvrtko for the
		   sugguestion.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9bb7c863172f..7500c06562da 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
 	return inactive;
 }
 
-static void invalidate_csb_entries(const u64 *first, const u64 *last)
-{
-	clflush((void *)first);
-	clflush((void *)last);
-}
-
 /*
  * Starting with Gen12, the status has a new format:
  *
@@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
 	 * the wash as hardware, working or not, will need to do the
 	 * invalidation before.
 	 */
-	invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
+	drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
 
 	/*
 	 * We assume that any event reflects a change in context flow
@@ -2783,8 +2777,8 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
 
 	/* Check that the GPU does indeed update the CSB entries! */
 	memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
-	invalidate_csb_entries(&execlists->csb_status[0],
-			       &execlists->csb_status[reset_value]);
+	drm_clflush_virt_range(&execlists->csb_status[0],
+				sizeof(&execlists->csb_status[reset_value]));
 
 	/* Once more for luck and our trusty paranoia */
 	ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 3/5] drm/i915/gt: Re-work reset_csb
  2022-02-04 16:37 ` [Intel-gfx] " Michael Cheng
@ 2022-02-04 16:37   ` Michael Cheng
  -1 siblings, 0 replies; 24+ messages in thread
From: Michael Cheng @ 2022-02-04 16:37 UTC (permalink / raw)
  To: intel-gfx
  Cc: tvrtko.ursulin, michael.cheng, wayne.boyer, casey.g.bowman,
	lucas.demarchi, dri-devel

Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.

v2(Michael Cheng): Remove extra clflush

v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
		   takes care of it.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 7500c06562da..22505aa428d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2944,9 +2944,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
 {
 	struct intel_engine_execlists * const execlists = &engine->execlists;
 
-	mb(); /* paranoia: read the CSB pointers from after the reset */
-	clflush(execlists->csb_write);
-	mb();
+	drm_clflush_virt_range(execlists->csb_write,
+			sizeof(execlists->csb_write));
 
 	inactive = process_csb(engine, inactive); /* drain preemption events */
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH v5 3/5] drm/i915/gt: Re-work reset_csb
@ 2022-02-04 16:37   ` Michael Cheng
  0 siblings, 0 replies; 24+ messages in thread
From: Michael Cheng @ 2022-02-04 16:37 UTC (permalink / raw)
  To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel

Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.

v2(Michael Cheng): Remove extra clflush

v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
		   takes care of it.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 7500c06562da..22505aa428d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2944,9 +2944,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
 {
 	struct intel_engine_execlists * const execlists = &engine->execlists;
 
-	mb(); /* paranoia: read the CSB pointers from after the reset */
-	clflush(execlists->csb_write);
-	mb();
+	drm_clflush_virt_range(execlists->csb_write,
+			sizeof(execlists->csb_write));
 
 	inactive = process_csb(engine, inactive); /* drain preemption events */
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 4/5] drm/i915/: Re-work clflush_write32
  2022-02-04 16:37 ` [Intel-gfx] " Michael Cheng
@ 2022-02-04 16:37   ` Michael Cheng
  -1 siblings, 0 replies; 24+ messages in thread
From: Michael Cheng @ 2022-02-04 16:37 UTC (permalink / raw)
  To: intel-gfx
  Cc: tvrtko.ursulin, michael.cheng, wayne.boyer, casey.g.bowman,
	lucas.demarchi, dri-devel

Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..0854276ff7ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 {
 	if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
-		if (flushes & CLFLUSH_BEFORE) {
-			clflushopt(addr);
-			mb();
-		}
+		if (flushes & CLFLUSH_BEFORE)
+			drm_clflush_virt_range(addr, sizeof(addr));
 
 		*addr = value;
 
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 		 * to ensure ordering of clflush wrt to the system.
 		 */
 		if (flushes & CLFLUSH_AFTER)
-			clflushopt(addr);
+			drm_clflush_virt_range(addr, sizeof(addr));
 	} else
 		*addr = value;
 }
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH v5 4/5] drm/i915/: Re-work clflush_write32
@ 2022-02-04 16:37   ` Michael Cheng
  0 siblings, 0 replies; 24+ messages in thread
From: Michael Cheng @ 2022-02-04 16:37 UTC (permalink / raw)
  To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel

Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..0854276ff7ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 {
 	if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
-		if (flushes & CLFLUSH_BEFORE) {
-			clflushopt(addr);
-			mb();
-		}
+		if (flushes & CLFLUSH_BEFORE)
+			drm_clflush_virt_range(addr, sizeof(addr));
 
 		*addr = value;
 
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 		 * to ensure ordering of clflush wrt to the system.
 		 */
 		if (flushes & CLFLUSH_AFTER)
-			clflushopt(addr);
+			drm_clflush_virt_range(addr, sizeof(addr));
 	} else
 		*addr = value;
 }
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH v5 5/5] drm/i915/gt: replace cache_clflush_range
  2022-02-04 16:37 ` [Intel-gfx] " Michael Cheng
@ 2022-02-04 16:37   ` Michael Cheng
  -1 siblings, 0 replies; 24+ messages in thread
From: Michael Cheng @ 2022-02-04 16:37 UTC (permalink / raw)
  To: intel-gfx
  Cc: tvrtko.ursulin, michael.cheng, wayne.boyer, casey.g.bowman,
	lucas.demarchi, dri-devel

Replace all occurance of cache_clflush_range with
drm_clflush_virt_range. This will prevent compile errors on non-x86
platforms.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c                 | 12 ++++++------
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_gtt.c                  |  2 +-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c                |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c    |  2 +-
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index c43e724afa9f..d0999e92621b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -444,11 +444,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
 				pd = pdp->entry[gen8_pd_index(idx, 2)];
 			}
 
-			clflush_cache_range(vaddr, PAGE_SIZE);
+			drm_clflush_virt_range(vaddr, PAGE_SIZE);
 			vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
 		}
 	} while (1);
-	clflush_cache_range(vaddr, PAGE_SIZE);
+	drm_clflush_virt_range(vaddr, PAGE_SIZE);
 
 	return idx;
 }
@@ -532,7 +532,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
 			}
 		} while (rem >= page_size && index < I915_PDES);
 
-		clflush_cache_range(vaddr, PAGE_SIZE);
+		drm_clflush_virt_range(vaddr, PAGE_SIZE);
 
 		/*
 		 * Is it safe to mark the 2M block as 64K? -- Either we have
@@ -548,7 +548,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
 					      I915_GTT_PAGE_SIZE_2M)))) {
 			vaddr = px_vaddr(pd);
 			vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
-			clflush_cache_range(vaddr, PAGE_SIZE);
+			drm_clflush_virt_range(vaddr, PAGE_SIZE);
 			page_size = I915_GTT_PAGE_SIZE_64K;
 
 			/*
@@ -569,7 +569,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
 				for (i = 1; i < index; i += 16)
 					memset64(vaddr + i, encode, 15);
 
-				clflush_cache_range(vaddr, PAGE_SIZE);
+				drm_clflush_virt_range(vaddr, PAGE_SIZE);
 			}
 		}
 
@@ -617,7 +617,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
 
 	vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
 	vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
-	clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
+	drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
 }
 
 static int gen8_init_scratch(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 22505aa428d9..5e74c99d5929 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2822,7 +2822,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
 	sanitize_hwsp(engine);
 
 	/* And scrub the dirty cachelines for the HWSP */
-	clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+	drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
 
 	intel_engine_reset_pinned_contexts(engine);
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 0d6bbc8c57f2..9b594be9102f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -255,7 +255,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count)
 	void *vaddr = __px_vaddr(p);
 
 	memset64(vaddr, val, count);
-	clflush_cache_range(vaddr, PAGE_SIZE);
+	drm_clflush_virt_range(vaddr, PAGE_SIZE);
 }
 
 static void poison_scratch_page(struct drm_i915_gem_object *scratch)
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 48e6e2f87700..bd474a5123cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -90,7 +90,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma,
 	u64 * const vaddr = __px_vaddr(pdma);
 
 	vaddr[idx] = encoded_entry;
-	clflush_cache_range(&vaddr[idx], sizeof(u64));
+	drm_clflush_virt_range(&vaddr[idx], sizeof(u64));
 }
 
 void
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0d..89020706adc4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3573,7 +3573,7 @@ static void guc_sanitize(struct intel_engine_cs *engine)
 	sanitize_hwsp(engine);
 
 	/* And scrub the dirty cachelines for the HWSP */
-	clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+	drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
 
 	intel_engine_reset_pinned_contexts(engine);
 }
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [Intel-gfx] [PATCH v5 5/5] drm/i915/gt: replace cache_clflush_range
@ 2022-02-04 16:37   ` Michael Cheng
  0 siblings, 0 replies; 24+ messages in thread
From: Michael Cheng @ 2022-02-04 16:37 UTC (permalink / raw)
  To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel

Replace all occurance of cache_clflush_range with
drm_clflush_virt_range. This will prevent compile errors on non-x86
platforms.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c                 | 12 ++++++------
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_gtt.c                  |  2 +-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c                |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c    |  2 +-
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index c43e724afa9f..d0999e92621b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -444,11 +444,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
 				pd = pdp->entry[gen8_pd_index(idx, 2)];
 			}
 
-			clflush_cache_range(vaddr, PAGE_SIZE);
+			drm_clflush_virt_range(vaddr, PAGE_SIZE);
 			vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
 		}
 	} while (1);
-	clflush_cache_range(vaddr, PAGE_SIZE);
+	drm_clflush_virt_range(vaddr, PAGE_SIZE);
 
 	return idx;
 }
@@ -532,7 +532,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
 			}
 		} while (rem >= page_size && index < I915_PDES);
 
-		clflush_cache_range(vaddr, PAGE_SIZE);
+		drm_clflush_virt_range(vaddr, PAGE_SIZE);
 
 		/*
 		 * Is it safe to mark the 2M block as 64K? -- Either we have
@@ -548,7 +548,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
 					      I915_GTT_PAGE_SIZE_2M)))) {
 			vaddr = px_vaddr(pd);
 			vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
-			clflush_cache_range(vaddr, PAGE_SIZE);
+			drm_clflush_virt_range(vaddr, PAGE_SIZE);
 			page_size = I915_GTT_PAGE_SIZE_64K;
 
 			/*
@@ -569,7 +569,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
 				for (i = 1; i < index; i += 16)
 					memset64(vaddr + i, encode, 15);
 
-				clflush_cache_range(vaddr, PAGE_SIZE);
+				drm_clflush_virt_range(vaddr, PAGE_SIZE);
 			}
 		}
 
@@ -617,7 +617,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
 
 	vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
 	vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
-	clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
+	drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
 }
 
 static int gen8_init_scratch(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 22505aa428d9..5e74c99d5929 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2822,7 +2822,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
 	sanitize_hwsp(engine);
 
 	/* And scrub the dirty cachelines for the HWSP */
-	clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+	drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
 
 	intel_engine_reset_pinned_contexts(engine);
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 0d6bbc8c57f2..9b594be9102f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -255,7 +255,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count)
 	void *vaddr = __px_vaddr(p);
 
 	memset64(vaddr, val, count);
-	clflush_cache_range(vaddr, PAGE_SIZE);
+	drm_clflush_virt_range(vaddr, PAGE_SIZE);
 }
 
 static void poison_scratch_page(struct drm_i915_gem_object *scratch)
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 48e6e2f87700..bd474a5123cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -90,7 +90,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma,
 	u64 * const vaddr = __px_vaddr(pdma);
 
 	vaddr[idx] = encoded_entry;
-	clflush_cache_range(&vaddr[idx], sizeof(u64));
+	drm_clflush_virt_range(&vaddr[idx], sizeof(u64));
 }
 
 void
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0d..89020706adc4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3573,7 +3573,7 @@ static void guc_sanitize(struct intel_engine_cs *engine)
 	sanitize_hwsp(engine);
 
 	/* And scrub the dirty cachelines for the HWSP */
-	clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+	drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
 
 	intel_engine_reset_pinned_contexts(engine);
 }
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev4)
  2022-02-04 16:37 ` [Intel-gfx] " Michael Cheng
                   ` (5 preceding siblings ...)
  (?)
@ 2022-02-04 16:53 ` Patchwork
  -1 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2022-02-04 16:53 UTC (permalink / raw)
  To: Michael Cheng; +Cc: intel-gfx

== Series Details ==

Series: Use drm_clflush* instead of clflush (rev4)
URL   : https://patchwork.freedesktop.org/series/99450/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
09b1c8ee43ad drm/i915/gt: Re-work intel_write_status_page
3f38f2a1e91d drm/i915/gt: Drop invalidate_csb_entries
-:49: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#49: FILE: drivers/gpu/drm/i915/gt/intel_execlists_submission.c:2781:
+	drm_clflush_virt_range(&execlists->csb_status[0],
+				sizeof(&execlists->csb_status[reset_value]));

-:49: WARNING:SIZEOF_ADDRESS: sizeof(& should be avoided
#49: FILE: drivers/gpu/drm/i915/gt/intel_execlists_submission.c:2781:
+				sizeof(&execlists->csb_status[reset_value]));

total: 0 errors, 1 warnings, 1 checks, 30 lines checked
a18f55ff9cbc drm/i915/gt: Re-work reset_csb
-:28: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#28: FILE: drivers/gpu/drm/i915/gt/intel_execlists_submission.c:2948:
+	drm_clflush_virt_range(execlists->csb_write,
+			sizeof(execlists->csb_write));

total: 0 errors, 0 warnings, 1 checks, 11 lines checked
fab67357e34d drm/i915/: Re-work clflush_write32
0ba361b324ae drm/i915/gt: replace cache_clflush_range
-:6: WARNING:TYPO_SPELLING: 'occurance' may be misspelled - perhaps 'occurrence'?
#6: 
Replace all occurance of cache_clflush_range with
            ^^^^^^^^^

total: 0 errors, 1 warnings, 0 checks, 77 lines checked



^ permalink raw reply	[flat|nested] 24+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Use drm_clflush* instead of clflush (rev4)
  2022-02-04 16:37 ` [Intel-gfx] " Michael Cheng
                   ` (6 preceding siblings ...)
  (?)
@ 2022-02-04 16:55 ` Patchwork
  -1 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2022-02-04 16:55 UTC (permalink / raw)
  To: Michael Cheng; +Cc: intel-gfx

== Series Details ==

Series: Use drm_clflush* instead of clflush (rev4)
URL   : https://patchwork.freedesktop.org/series/99450/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.



^ permalink raw reply	[flat|nested] 24+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Use drm_clflush* instead of clflush (rev4)
  2022-02-04 16:37 ` [Intel-gfx] " Michael Cheng
                   ` (7 preceding siblings ...)
  (?)
@ 2022-02-04 17:27 ` Patchwork
  -1 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2022-02-04 17:27 UTC (permalink / raw)
  To: Michael Cheng; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 7856 bytes --]

== Series Details ==

Series: Use drm_clflush* instead of clflush (rev4)
URL   : https://patchwork.freedesktop.org/series/99450/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11189 -> Patchwork_22178
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/index.html

Participating hosts (47 -> 44)
------------------------------

  Additional (1): fi-kbl-soraka 
  Missing    (4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u 

Known issues
------------

  Here are the changes found in Patchwork_22178 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@nop-compute0:
    - fi-pnv-d510:        NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-pnv-d510/igt@amdgpu/amd_cs_nop@nop-compute0.html

  * igt@gem_exec_fence@basic-busy@bcs0:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][2] ([fdo#109271]) +8 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-kbl-soraka/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#2291])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
    - bat-dg1-6:          [PASS][6] -> [DMESG-FAIL][7] ([i915#4494] / [i915#4957])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
    - fi-hsw-4770:        [PASS][8] -> [INCOMPLETE][9] ([i915#4785])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html

  * igt@kms_chamelium@dp-edid-read:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-kbl-soraka/igt@kms_chamelium@dp-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-b:
    - fi-cfl-8109u:       [PASS][12] -> [DMESG-WARN][13] ([i915#295]) +12 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html

  * igt@prime_vgem@basic-userptr:
    - fi-skl-6600u:       NOTRUN -> [SKIP][14] ([fdo#109271]) +18 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-skl-6600u/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - fi-hsw-4770:        NOTRUN -> [FAIL][15] ([fdo#109271] / [i915#1436] / [i915#4312])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-hsw-4770/igt@runner@aborted.html
    - fi-bdw-5557u:       NOTRUN -> [FAIL][16] ([i915#2426] / [i915#4312])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-bdw-5557u/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3@smem:
    - fi-bdw-5557u:       [INCOMPLETE][17] ([i915#146]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@i915_selftest@live@requests:
    - fi-pnv-d510:        [DMESG-FAIL][19] ([i915#2927] / [i915#4528]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/fi-pnv-d510/igt@i915_selftest@live@requests.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-pnv-d510/igt@i915_selftest@live@requests.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-cml-u2:          [DMESG-WARN][21] ([i915#4269]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_psr@primary_page_flip:
    - fi-skl-6600u:       [FAIL][23] ([i915#4547]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/fi-skl-6600u/igt@kms_psr@primary_page_flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * Linux: CI_DRM_11189 -> Patchwork_22178

  CI-20190529: 20190529
  CI_DRM_11189: c0fc917bc92837300b1991d53b835c6876f465a2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6339: 9cd99d763440ae75d9981ce4e361d3deb5edb4e4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22178: 0ba361b324ae100fe0314048dad9968b66e0383c @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

0ba361b324ae drm/i915/gt: replace cache_clflush_range
fab67357e34d drm/i915/: Re-work clflush_write32
a18f55ff9cbc drm/i915/gt: Re-work reset_csb
3f38f2a1e91d drm/i915/gt: Drop invalidate_csb_entries
09b1c8ee43ad drm/i915/gt: Re-work intel_write_status_page

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/index.html

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^ permalink raw reply	[flat|nested] 24+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Use drm_clflush* instead of clflush (rev4)
  2022-02-04 16:37 ` [Intel-gfx] " Michael Cheng
                   ` (8 preceding siblings ...)
  (?)
@ 2022-02-04 18:53 ` Patchwork
  -1 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2022-02-04 18:53 UTC (permalink / raw)
  To: Michael Cheng; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 30264 bytes --]

== Series Details ==

Series: Use drm_clflush* instead of clflush (rev4)
URL   : https://patchwork.freedesktop.org/series/99450/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11189_full -> Patchwork_22178_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_22178_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22178_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 13)
------------------------------

  Additional (2): shard-rkl shard-dg1 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_22178_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_fence_thrash@bo-write-verify-y:
    - shard-skl:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-skl9/igt@gem_fence_thrash@bo-write-verify-y.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl3/igt@gem_fence_thrash@bo-write-verify-y.html

  * igt@i915_selftest@mock@vma:
    - shard-skl:          NOTRUN -> [INCOMPLETE][3] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl3/igt@i915_selftest@mock@vma.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_schedule@u-submit-early-slice@vcs1:
    - {shard-dg1}:        NOTRUN -> [INCOMPLETE][4]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-dg1-12/igt@gem_exec_schedule@u-submit-early-slice@vcs1.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen:
    - {shard-dg1}:        NOTRUN -> [DMESG-WARN][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-dg1-12/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html

  
Known issues
------------

  Here are the changes found in Patchwork_22178_full that come from known issues:

### CI changes ###

#### Issues hit ####

  * boot:
    - shard-apl:          ([PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30]) -> ([PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [FAIL][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55]) ([i915#4386])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl2/boot.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl2/boot.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl2/boot.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl3/boot.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl3/boot.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl3/boot.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl4/boot.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl4/boot.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl4/boot.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl6/boot.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl6/boot.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl6/boot.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl6/boot.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl6/boot.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl7/boot.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl7/boot.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl7/boot.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl8/boot.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl8/boot.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl8/boot.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl1/boot.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl1/boot.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl1/boot.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl1/boot.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl2/boot.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl1/boot.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl1/boot.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl1/boot.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl1/boot.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl2/boot.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl2/boot.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl2/boot.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl2/boot.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl3/boot.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl3/boot.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl3/boot.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl4/boot.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl4/boot.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl4/boot.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl6/boot.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl6/boot.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl6/boot.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl6/boot.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl7/boot.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl7/boot.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl7/boot.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl7/boot.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl8/boot.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl8/boot.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl8/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@legacy-engines-hang:
    - shard-snb:          NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#1099])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-snb6/igt@gem_ctx_persistence@legacy-engines-hang.html

  * igt@gem_ctx_shared@q-in-order:
    - shard-snb:          NOTRUN -> [SKIP][57] ([fdo#109271]) +108 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-snb6/igt@gem_ctx_shared@q-in-order.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-iclb:         [PASS][58] -> [SKIP][59] ([i915#4525])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-iclb1/igt@gem_exec_balancer@parallel-keep-in-fence.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-iclb6/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_capture@pi@rcs0:
    - shard-skl:          [PASS][60] -> [INCOMPLETE][61] ([i915#4547])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-skl8/igt@gem_exec_capture@pi@rcs0.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl2/igt@gem_exec_capture@pi@rcs0.html

  * igt@gem_exec_endless@dispatch@bcs0:
    - shard-tglb:         [PASS][62] -> [INCOMPLETE][63] ([i915#3778])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-tglb7/igt@gem_exec_endless@dispatch@bcs0.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-tglb1/igt@gem_exec_endless@dispatch@bcs0.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         [PASS][64] -> [FAIL][65] ([i915#2842])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-glk:          [PASS][66] -> [FAIL][67] ([i915#2842])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-glk7/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-kbl:          [PASS][68] -> [FAIL][69] ([i915#2842])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [PASS][70] -> [SKIP][71] ([i915#2190])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-tglb1/igt@gem_huc_copy@huc-copy.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-tglb6/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-skl:          NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#4613]) +1 similar issue
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl3/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_userptr_blits@input-checking:
    - shard-skl:          NOTRUN -> [DMESG-WARN][73] ([i915#4990])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl4/igt@gem_userptr_blits@input-checking.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-skl:          NOTRUN -> [FAIL][74] ([i915#454])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl9/igt@i915_pm_dc@dc6-dpms.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-skl:          NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3777]) +5 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl9/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][76] ([i915#3743]) +2 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#3886]) +3 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl8/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#3886]) +6 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl9/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_chamelium@hdmi-hpd-storm-disable:
    - shard-skl:          NOTRUN -> [SKIP][79] ([fdo#109271] / [fdo#111827]) +18 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl6/igt@kms_chamelium@hdmi-hpd-storm-disable.html

  * igt@kms_chamelium@vga-hpd-without-ddc:
    - shard-snb:          NOTRUN -> [SKIP][80] ([fdo#109271] / [fdo#111827]) +6 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-snb6/igt@kms_chamelium@vga-hpd-without-ddc.html

  * igt@kms_color_chamelium@pipe-b-ctm-0-5:
    - shard-apl:          NOTRUN -> [SKIP][81] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl8/igt@kms_color_chamelium@pipe-b-ctm-0-5.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-apl:          NOTRUN -> [TIMEOUT][82] ([i915#1319])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl8/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [PASS][83] -> [DMESG-WARN][84] ([i915#180]) +2 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          NOTRUN -> [FAIL][85] ([i915#2346])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          NOTRUN -> [FAIL][86] ([i915#2346] / [i915#533])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
    - shard-skl:          NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#533]) +1 similar issue
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl9/igt@kms_cursor_legacy@pipe-d-torture-bo.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-glk:          [PASS][88] -> [FAIL][89] ([i915#64])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-glk1/igt@kms_fbcon_fbt@fbc.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-glk2/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
    - shard-kbl:          [PASS][90] -> [FAIL][91] ([i915#79])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-kbl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [PASS][92] -> [DMESG-WARN][93] ([i915#180])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
    - shard-skl:          [PASS][94] -> [FAIL][95] ([i915#2122]) +1 similar issue
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-skl7/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-iclb:         [PASS][96] -> [SKIP][97] ([i915#3701])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-iclb6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
    - shard-glk:          [PASS][98] -> [FAIL][99] ([i915#4911])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-glk4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt:
    - shard-tglb:         NOTRUN -> [SKIP][100] ([fdo#109280] / [fdo#111825])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_hdr@bpc-switch:
    - shard-skl:          [PASS][101] -> [FAIL][102] ([i915#1188])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-skl7/igt@kms_hdr@bpc-switch.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl7/igt@kms_hdr@bpc-switch.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          NOTRUN -> [FAIL][103] ([i915#1188]) +1 similar issue
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#533])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl8/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][105] ([i915#265])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-skl:          NOTRUN -> [FAIL][106] ([fdo#108145] / [i915#265]) +3 similar issues
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][107] -> [FAIL][108] ([fdo#108145] / [i915#265])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-skl:          NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#2733])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl3/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
    - shard-skl:          NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#658]) +2 similar issues
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [PASS][111] -> [SKIP][112] ([fdo#109441])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-iclb1/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_setmode@basic:
    - shard-glk:          [PASS][113] -> [FAIL][114] ([i915#31])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-glk3/igt@kms_setmode@basic.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-glk4/igt@kms_setmode@basic.html
    - shard-snb:          NOTRUN -> [FAIL][115] ([i915#31])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-snb6/igt@kms_setmode@basic.html

  * igt@nouveau_crc@pipe-d-ctx-flip-detection:
    - shard-skl:          NOTRUN -> [SKIP][116] ([fdo#109271]) +235 similar issues
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl4/igt@nouveau_crc@pipe-d-ctx-flip-detection.html

  * igt@perf@polling-parameterized:
    - shard-glk:          [PASS][117] -> [FAIL][118] ([i915#1542])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-glk2/igt@perf@polling-parameterized.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-glk3/igt@perf@polling-parameterized.html

  * igt@prime_vgem@fence-write-hang:
    - shard-apl:          NOTRUN -> [SKIP][119] ([fdo#109271]) +54 similar issues
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl8/igt@prime_vgem@fence-write-hang.html

  * igt@sysfs_clients@fair-0:
    - shard-apl:          NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#2994])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl8/igt@sysfs_clients@fair-0.html

  * igt@sysfs_clients@split-10:
    - shard-skl:          NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#2994]) +4 similar issues
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl9/igt@sysfs_clients@split-10.html

  
#### Possible fixes ####

  * igt@gem_eio@kms:
    - shard-tglb:         [FAIL][122] ([i915#232]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-tglb3/igt@gem_eio@kms.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-tglb7/igt@gem_eio@kms.html

  * igt@gem_eio@unwedge-stress:
    - {shard-tglu}:       [TIMEOUT][124] ([i915#3063] / [i915#3648]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-tglu-5/igt@gem_eio@unwedge-stress.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-tglu-2/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - shard-apl:          [FAIL][126] ([i915#2842]) -> [PASS][127]
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl2/igt@gem_exec_fair@basic-none@vecs0.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl6/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [FAIL][128] ([i915#2842]) -> [PASS][129]
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          [FAIL][130] ([i915#2842]) -> [PASS][131] +2 similar issues
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_softpin@allocator-evict-all-engines:
    - shard-glk:          [FAIL][132] ([i915#4171]) -> [PASS][133]
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-glk3/igt@gem_softpin@allocator-evict-all-engines.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-glk4/igt@gem_softpin@allocator-evict-all-engines.html

  * igt@i915_selftest@live@guc:
    - shard-skl:          [INCOMPLETE][134] -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-skl4/igt@i915_selftest@live@guc.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl8/igt@i915_selftest@live@guc.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-skl:          [INCOMPLETE][136] ([i915#2828] / [i915#300]) -> [PASS][137]
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
    - shard-iclb:         [FAIL][138] -> [PASS][139]
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-iclb6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html

  * igt@kms_fbcon_fbt@fbc:
    - {shard-tglu}:       [FAIL][140] ([i915#64]) -> [PASS][141]
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-tglu-1/igt@kms_fbcon_fbt@fbc.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-tglu-3/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-skl:          [FAIL][142] ([i915#79]) -> [PASS][143] +1 similar issue
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-fences-interruptible@b-vga1:
    - shard-snb:          [INCOMPLETE][144] -> [PASS][145] +1 similar issue
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-snb2/igt@kms_flip@flip-vs-fences-interruptible@b-vga1.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-snb6/igt@kms_flip@flip-vs-fences-interruptible@b-vga1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [DMESG-WARN][146] ([i915#180]) -> [PASS][147] +2 similar issues
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][148] ([fdo#109441]) -> [PASS][149] +2 similar issues
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  
#### Warnings ####

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-glk:          [SKIP][150] ([fdo#109271] / [i915#3777]) -> [SKIP][151] ([fdo#109271] / [i915#1888] / [i915#3777])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-glk6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-glk3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_psr2_sf@cursor-plane-update-sf:
    - shard-iclb:         [SKIP][152] ([i915#2920]) -> [SKIP][153] ([fdo#111068] / [i915#658])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-iclb1/igt@kms_psr2_sf@cursor-plane-update-sf.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-iclb:         [FAIL][154] ([i915#4148]) -> [SKIP][155] ([fdo#109642] / [fdo#111068] / [i915#658])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-iclb7/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-iclb:         [SKIP][156] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][157] ([i915#4148])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-iclb4/igt@kms_psr2_su@page_flip-xrgb8888.html
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-iclb2/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][158], [FAIL][159]) ([i915#3002] / [i915#4312]) -> ([FAIL][160], [FAIL][161], [FAIL][162]) ([i915#180] / [i915#3002] / [i915#4312])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-kbl4/igt@runner@aborted.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-kbl6/igt@runner@aborted.html
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-kbl6/igt@runner@aborted.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-kbl1/igt@runner@aborted.html
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-kbl7/igt@runner@aborted.html
    - shard-apl:          ([FAIL][163], [FAIL][164], [FAIL][165], [FAIL][166], [FAIL][167]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#4312]) -> ([FAIL][168], [FAIL][169], [FAIL][170], [FAIL][171], [FAIL][172]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#4312])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl8/igt@runner@aborted.html
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl6/igt@runner@aborted.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl2/igt@runner@aborted.html
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl6/igt@runner@aborted.html
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11189/shard-apl8/igt@runner@aborted.html
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl6/igt@runner@aborted.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl4/igt@runner@aborted.html
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl4/igt@runner@aborted.html
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl7/igt@runner@aborted.html
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/shard-apl7/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22178/index.html

[-- Attachment #2: Type: text/html, Size: 33180 bytes --]

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v5 2/5] drm/i915/gt: Drop invalidate_csb_entries
  2022-02-04 16:37   ` [Intel-gfx] " Michael Cheng
@ 2022-02-07 11:57     ` Tvrtko Ursulin
  -1 siblings, 0 replies; 24+ messages in thread
From: Tvrtko Ursulin @ 2022-02-07 11:57 UTC (permalink / raw)
  To: Michael Cheng, intel-gfx
  Cc: casey.g.bowman, lucas.demarchi, dri-devel, wayne.boyer


On 04/02/2022 16:37, Michael Cheng wrote:
> Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
> This allows for one less function call, and prevent complier errors when
> building for non-x86 architectures.
> 
> v2(Michael Cheng): Drop invalidate_csb_entries function and directly
> 		   invoke drm_clflush_virt_range. Thanks to Tvrtko for the
> 		   sugguestion.
> 
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 12 +++---------
>   1 file changed, 3 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 9bb7c863172f..7500c06562da 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
>   	return inactive;
>   }
>   
> -static void invalidate_csb_entries(const u64 *first, const u64 *last)
> -{
> -	clflush((void *)first);
> -	clflush((void *)last);
> -}
> -
>   /*
>    * Starting with Gen12, the status has a new format:
>    *
> @@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
>   	 * the wash as hardware, working or not, will need to do the
>   	 * invalidation before.
>   	 */
> -	invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
> +	drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
>   
>   	/*
>   	 * We assume that any event reflects a change in context flow
> @@ -2783,8 +2777,8 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
>   
>   	/* Check that the GPU does indeed update the CSB entries! */
>   	memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
> -	invalidate_csb_entries(&execlists->csb_status[0],
> -			       &execlists->csb_status[reset_value]);
> +	drm_clflush_virt_range(&execlists->csb_status[0],
> +				sizeof(&execlists->csb_status[reset_value]));

Hm I thought we covered this already, should be:

drm_clflush_virt_range(&execlists->csb_status[0],
		       execlists->csb_size * sizeof(execlists->csb_status[0]));

Regards,

Tvrtko

>   
>   	/* Once more for luck and our trusty paranoia */
>   	ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v5 2/5] drm/i915/gt: Drop invalidate_csb_entries
@ 2022-02-07 11:57     ` Tvrtko Ursulin
  0 siblings, 0 replies; 24+ messages in thread
From: Tvrtko Ursulin @ 2022-02-07 11:57 UTC (permalink / raw)
  To: Michael Cheng, intel-gfx; +Cc: lucas.demarchi, dri-devel


On 04/02/2022 16:37, Michael Cheng wrote:
> Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
> This allows for one less function call, and prevent complier errors when
> building for non-x86 architectures.
> 
> v2(Michael Cheng): Drop invalidate_csb_entries function and directly
> 		   invoke drm_clflush_virt_range. Thanks to Tvrtko for the
> 		   sugguestion.
> 
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 12 +++---------
>   1 file changed, 3 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 9bb7c863172f..7500c06562da 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
>   	return inactive;
>   }
>   
> -static void invalidate_csb_entries(const u64 *first, const u64 *last)
> -{
> -	clflush((void *)first);
> -	clflush((void *)last);
> -}
> -
>   /*
>    * Starting with Gen12, the status has a new format:
>    *
> @@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
>   	 * the wash as hardware, working or not, will need to do the
>   	 * invalidation before.
>   	 */
> -	invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
> +	drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
>   
>   	/*
>   	 * We assume that any event reflects a change in context flow
> @@ -2783,8 +2777,8 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
>   
>   	/* Check that the GPU does indeed update the CSB entries! */
>   	memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
> -	invalidate_csb_entries(&execlists->csb_status[0],
> -			       &execlists->csb_status[reset_value]);
> +	drm_clflush_virt_range(&execlists->csb_status[0],
> +				sizeof(&execlists->csb_status[reset_value]));

Hm I thought we covered this already, should be:

drm_clflush_virt_range(&execlists->csb_status[0],
		       execlists->csb_size * sizeof(execlists->csb_status[0]));

Regards,

Tvrtko

>   
>   	/* Once more for luck and our trusty paranoia */
>   	ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v5 0/5] Use drm_clflush* instead of clflush
  2022-02-04 16:37 ` [Intel-gfx] " Michael Cheng
@ 2022-02-07 12:03   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 24+ messages in thread
From: Tvrtko Ursulin @ 2022-02-07 12:03 UTC (permalink / raw)
  To: Michael Cheng, intel-gfx
  Cc: casey.g.bowman, lucas.demarchi, dri-devel, wayne.boyer


On 04/02/2022 16:37, Michael Cheng wrote:
> This patch series re-work a few i915 functions to use drm_clflush_virt_range
> instead of calling clflush or clflushopt directly. This will prevent errors
> when building for non-x86 architectures.
> 
> v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
> more patches to convert additional clflush/clflushopt to use drm_clflush*.
> (Michael Cheng)
> 
> v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
> 
> v4: Remove extra memory barriers
> 
> v5: s/cache_clflush_range/drm_clflush_virt_range

Is anyone interested in this story noticing my open? I will repeat:

How about we add i915_clflush_virt_range as static inline and by doing 
so avoid adding function calls to code paths which are impossible on Arm 
builds? Case in point relocations, probably execlists backend as well.

Downside would be effectively duplicating drm_clfush_virt_range code. 
But for me, (Also considering no other driver calls it so why it is 
there? Should it be deleted?), that would be okay.

Regards,

Tvrtko

> Michael Cheng (5):
>    drm/i915/gt: Re-work intel_write_status_page
>    drm/i915/gt: Drop invalidate_csb_entries
>    drm/i915/gt: Re-work reset_csb
>    drm/i915/: Re-work clflush_write32
>    drm/i915/gt: replace cache_clflush_range
> 
>   .../gpu/drm/i915/gem/i915_gem_execbuffer.c    |  8 +++-----
>   drivers/gpu/drm/i915/gt/gen8_ppgtt.c          | 12 ++++++------
>   drivers/gpu/drm/i915/gt/intel_engine.h        | 13 ++++---------
>   .../drm/i915/gt/intel_execlists_submission.c  | 19 ++++++-------------
>   drivers/gpu/drm/i915/gt/intel_gtt.c           |  2 +-
>   drivers/gpu/drm/i915/gt/intel_ppgtt.c         |  2 +-
>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
>   7 files changed, 22 insertions(+), 36 deletions(-)
> 

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v5 0/5] Use drm_clflush* instead of clflush
@ 2022-02-07 12:03   ` Tvrtko Ursulin
  0 siblings, 0 replies; 24+ messages in thread
From: Tvrtko Ursulin @ 2022-02-07 12:03 UTC (permalink / raw)
  To: Michael Cheng, intel-gfx; +Cc: lucas.demarchi, dri-devel


On 04/02/2022 16:37, Michael Cheng wrote:
> This patch series re-work a few i915 functions to use drm_clflush_virt_range
> instead of calling clflush or clflushopt directly. This will prevent errors
> when building for non-x86 architectures.
> 
> v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
> more patches to convert additional clflush/clflushopt to use drm_clflush*.
> (Michael Cheng)
> 
> v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
> 
> v4: Remove extra memory barriers
> 
> v5: s/cache_clflush_range/drm_clflush_virt_range

Is anyone interested in this story noticing my open? I will repeat:

How about we add i915_clflush_virt_range as static inline and by doing 
so avoid adding function calls to code paths which are impossible on Arm 
builds? Case in point relocations, probably execlists backend as well.

Downside would be effectively duplicating drm_clfush_virt_range code. 
But for me, (Also considering no other driver calls it so why it is 
there? Should it be deleted?), that would be okay.

Regards,

Tvrtko

> Michael Cheng (5):
>    drm/i915/gt: Re-work intel_write_status_page
>    drm/i915/gt: Drop invalidate_csb_entries
>    drm/i915/gt: Re-work reset_csb
>    drm/i915/: Re-work clflush_write32
>    drm/i915/gt: replace cache_clflush_range
> 
>   .../gpu/drm/i915/gem/i915_gem_execbuffer.c    |  8 +++-----
>   drivers/gpu/drm/i915/gt/gen8_ppgtt.c          | 12 ++++++------
>   drivers/gpu/drm/i915/gt/intel_engine.h        | 13 ++++---------
>   .../drm/i915/gt/intel_execlists_submission.c  | 19 ++++++-------------
>   drivers/gpu/drm/i915/gt/intel_gtt.c           |  2 +-
>   drivers/gpu/drm/i915/gt/intel_ppgtt.c         |  2 +-
>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
>   7 files changed, 22 insertions(+), 36 deletions(-)
> 

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v5 0/5] Use drm_clflush* instead of clflush
  2022-02-07 12:03   ` [Intel-gfx] " Tvrtko Ursulin
  (?)
@ 2022-02-07 12:44   ` Jani Nikula
  2022-02-08  9:02     ` Tvrtko Ursulin
  -1 siblings, 1 reply; 24+ messages in thread
From: Jani Nikula @ 2022-02-07 12:44 UTC (permalink / raw)
  To: Tvrtko Ursulin, Michael Cheng, intel-gfx; +Cc: lucas.demarchi, dri-devel

On Mon, 07 Feb 2022, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> On 04/02/2022 16:37, Michael Cheng wrote:
>> This patch series re-work a few i915 functions to use drm_clflush_virt_range
>> instead of calling clflush or clflushopt directly. This will prevent errors
>> when building for non-x86 architectures.
>> 
>> v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
>> more patches to convert additional clflush/clflushopt to use drm_clflush*.
>> (Michael Cheng)
>> 
>> v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
>> 
>> v4: Remove extra memory barriers
>> 
>> v5: s/cache_clflush_range/drm_clflush_virt_range
>
> Is anyone interested in this story noticing my open? I will repeat:
>
> How about we add i915_clflush_virt_range as static inline and by doing 
> so avoid adding function calls to code paths which are impossible on Arm 
> builds? Case in point relocations, probably execlists backend as well.
>
> Downside would be effectively duplicating drm_clfush_virt_range code. 
> But for me, (Also considering no other driver calls it so why it is 
> there? Should it be deleted?), that would be okay.

Keep it simple first, optimize later if necessary?

BR,
Jani.


>
> Regards,
>
> Tvrtko
>
>> Michael Cheng (5):
>>    drm/i915/gt: Re-work intel_write_status_page
>>    drm/i915/gt: Drop invalidate_csb_entries
>>    drm/i915/gt: Re-work reset_csb
>>    drm/i915/: Re-work clflush_write32
>>    drm/i915/gt: replace cache_clflush_range
>> 
>>   .../gpu/drm/i915/gem/i915_gem_execbuffer.c    |  8 +++-----
>>   drivers/gpu/drm/i915/gt/gen8_ppgtt.c          | 12 ++++++------
>>   drivers/gpu/drm/i915/gt/intel_engine.h        | 13 ++++---------
>>   .../drm/i915/gt/intel_execlists_submission.c  | 19 ++++++-------------
>>   drivers/gpu/drm/i915/gt/intel_gtt.c           |  2 +-
>>   drivers/gpu/drm/i915/gt/intel_ppgtt.c         |  2 +-
>>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
>>   7 files changed, 22 insertions(+), 36 deletions(-)
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v5 2/5] drm/i915/gt: Drop invalidate_csb_entries
  2022-02-07 11:57     ` [Intel-gfx] " Tvrtko Ursulin
@ 2022-02-07 18:47       ` Michael Cheng
  -1 siblings, 0 replies; 24+ messages in thread
From: Michael Cheng @ 2022-02-07 18:47 UTC (permalink / raw)
  To: Tvrtko Ursulin, intel-gfx
  Cc: casey.g.bowman, lucas.demarchi, dri-devel, wayne.boyer

Ah, sorry thanks for pointing that out. We did discuss previously. I 
will go ahead and change it.

On 2022-02-07 3:57 a.m., Tvrtko Ursulin wrote:
>
> On 04/02/2022 16:37, Michael Cheng wrote:
>> Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
>> This allows for one less function call, and prevent complier errors when
>> building for non-x86 architectures.
>>
>> v2(Michael Cheng): Drop invalidate_csb_entries function and directly
>>            invoke drm_clflush_virt_range. Thanks to Tvrtko for the
>>            sugguestion.
>>
>> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 12 +++---------
>>   1 file changed, 3 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> index 9bb7c863172f..7500c06562da 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> @@ -1646,12 +1646,6 @@ cancel_port_requests(struct 
>> intel_engine_execlists * const execlists,
>>       return inactive;
>>   }
>>   -static void invalidate_csb_entries(const u64 *first, const u64 *last)
>> -{
>> -    clflush((void *)first);
>> -    clflush((void *)last);
>> -}
>> -
>>   /*
>>    * Starting with Gen12, the status has a new format:
>>    *
>> @@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, 
>> struct i915_request **inactive)
>>        * the wash as hardware, working or not, will need to do the
>>        * invalidation before.
>>        */
>> -    invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
>> +    drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
>>         /*
>>        * We assume that any event reflects a change in context flow
>> @@ -2783,8 +2777,8 @@ static void reset_csb_pointers(struct 
>> intel_engine_cs *engine)
>>         /* Check that the GPU does indeed update the CSB entries! */
>>       memset(execlists->csb_status, -1, (reset_value + 1) * 
>> sizeof(u64));
>> -    invalidate_csb_entries(&execlists->csb_status[0],
>> -                   &execlists->csb_status[reset_value]);
>> +    drm_clflush_virt_range(&execlists->csb_status[0],
>> + sizeof(&execlists->csb_status[reset_value]));
>
> Hm I thought we covered this already, should be:
>
> drm_clflush_virt_range(&execlists->csb_status[0],
>                execlists->csb_size * sizeof(execlists->csb_status[0]));
>
> Regards,
>
> Tvrtko
>
>>         /* Once more for luck and our trusty paranoia */
>>       ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v5 2/5] drm/i915/gt: Drop invalidate_csb_entries
@ 2022-02-07 18:47       ` Michael Cheng
  0 siblings, 0 replies; 24+ messages in thread
From: Michael Cheng @ 2022-02-07 18:47 UTC (permalink / raw)
  To: Tvrtko Ursulin, intel-gfx; +Cc: lucas.demarchi, dri-devel

Ah, sorry thanks for pointing that out. We did discuss previously. I 
will go ahead and change it.

On 2022-02-07 3:57 a.m., Tvrtko Ursulin wrote:
>
> On 04/02/2022 16:37, Michael Cheng wrote:
>> Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
>> This allows for one less function call, and prevent complier errors when
>> building for non-x86 architectures.
>>
>> v2(Michael Cheng): Drop invalidate_csb_entries function and directly
>>            invoke drm_clflush_virt_range. Thanks to Tvrtko for the
>>            sugguestion.
>>
>> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 12 +++---------
>>   1 file changed, 3 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> index 9bb7c863172f..7500c06562da 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> @@ -1646,12 +1646,6 @@ cancel_port_requests(struct 
>> intel_engine_execlists * const execlists,
>>       return inactive;
>>   }
>>   -static void invalidate_csb_entries(const u64 *first, const u64 *last)
>> -{
>> -    clflush((void *)first);
>> -    clflush((void *)last);
>> -}
>> -
>>   /*
>>    * Starting with Gen12, the status has a new format:
>>    *
>> @@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, 
>> struct i915_request **inactive)
>>        * the wash as hardware, working or not, will need to do the
>>        * invalidation before.
>>        */
>> -    invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
>> +    drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
>>         /*
>>        * We assume that any event reflects a change in context flow
>> @@ -2783,8 +2777,8 @@ static void reset_csb_pointers(struct 
>> intel_engine_cs *engine)
>>         /* Check that the GPU does indeed update the CSB entries! */
>>       memset(execlists->csb_status, -1, (reset_value + 1) * 
>> sizeof(u64));
>> -    invalidate_csb_entries(&execlists->csb_status[0],
>> -                   &execlists->csb_status[reset_value]);
>> +    drm_clflush_virt_range(&execlists->csb_status[0],
>> + sizeof(&execlists->csb_status[reset_value]));
>
> Hm I thought we covered this already, should be:
>
> drm_clflush_virt_range(&execlists->csb_status[0],
>                execlists->csb_size * sizeof(execlists->csb_status[0]));
>
> Regards,
>
> Tvrtko
>
>>         /* Once more for luck and our trusty paranoia */
>>       ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [Intel-gfx] [PATCH v5 0/5] Use drm_clflush* instead of clflush
  2022-02-07 12:44   ` Jani Nikula
@ 2022-02-08  9:02     ` Tvrtko Ursulin
  0 siblings, 0 replies; 24+ messages in thread
From: Tvrtko Ursulin @ 2022-02-08  9:02 UTC (permalink / raw)
  To: Jani Nikula, Michael Cheng, intel-gfx; +Cc: lucas.demarchi, dri-devel


On 07/02/2022 12:44, Jani Nikula wrote:
> On Mon, 07 Feb 2022, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> On 04/02/2022 16:37, Michael Cheng wrote:
>>> This patch series re-work a few i915 functions to use drm_clflush_virt_range
>>> instead of calling clflush or clflushopt directly. This will prevent errors
>>> when building for non-x86 architectures.
>>>
>>> v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
>>> more patches to convert additional clflush/clflushopt to use drm_clflush*.
>>> (Michael Cheng)
>>>
>>> v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
>>>
>>> v4: Remove extra memory barriers
>>>
>>> v5: s/cache_clflush_range/drm_clflush_virt_range
>>
>> Is anyone interested in this story noticing my open? I will repeat:
>>
>> How about we add i915_clflush_virt_range as static inline and by doing
>> so avoid adding function calls to code paths which are impossible on Arm
>> builds? Case in point relocations, probably execlists backend as well.
>>
>> Downside would be effectively duplicating drm_clfush_virt_range code.
>> But for me, (Also considering no other driver calls it so why it is
>> there? Should it be deleted?), that would be okay.
> 
> Keep it simple first, optimize later if necessary?

I don't think it would ever happen unless done from the start. :/

Regards,

Tvrtko

^ permalink raw reply	[flat|nested] 24+ messages in thread
end of thread, other threads:[~2022-02-08  9:03 UTC | newest]

Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-04 16:37 [PATCH v5 0/5] Use drm_clflush* instead of clflush Michael Cheng
2022-02-04 16:37 ` [Intel-gfx] " Michael Cheng
2022-02-04 16:37 ` [PATCH v5 1/5] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-02-04 16:37   ` [Intel-gfx] " Michael Cheng
2022-02-04 16:37 ` [PATCH v5 2/5] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
2022-02-04 16:37   ` [Intel-gfx] " Michael Cheng
2022-02-07 11:57   ` Tvrtko Ursulin
2022-02-07 11:57     ` [Intel-gfx] " Tvrtko Ursulin
2022-02-07 18:47     ` Michael Cheng
2022-02-07 18:47       ` [Intel-gfx] " Michael Cheng
2022-02-04 16:37 ` [PATCH v5 3/5] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-02-04 16:37   ` [Intel-gfx] " Michael Cheng
2022-02-04 16:37 ` [PATCH v5 4/5] drm/i915/: Re-work clflush_write32 Michael Cheng
2022-02-04 16:37   ` [Intel-gfx] " Michael Cheng
2022-02-04 16:37 ` [PATCH v5 5/5] drm/i915/gt: replace cache_clflush_range Michael Cheng
2022-02-04 16:37   ` [Intel-gfx] " Michael Cheng
2022-02-04 16:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev4) Patchwork
2022-02-04 16:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-04 17:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-04 18:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-02-07 12:03 ` [PATCH v5 0/5] Use drm_clflush* instead of clflush Tvrtko Ursulin
2022-02-07 12:03   ` [Intel-gfx] " Tvrtko Ursulin
2022-02-07 12:44   ` Jani Nikula
2022-02-08  9:02     ` Tvrtko Ursulin

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