[PATCH 0/8] phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY

[PATCH 0/8] phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY

[Samuel Holland]

This series adds support for the updated DPHY found in a couple of
recent Allwinner SoCs. The first three patches fix an omission in the
existing binding. The remaining patches add the new hardware variant.


Samuel Holland (8):
  dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property
  ARM: dts: sun8i: a33: Add DPHY interrupt
  arm64: dts: allwinner: a64: Add DPHY interrupt
  dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant
  phy: allwinner: phy-sun6i-mipi-dphy: Make RX support optional
  phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last
  phy: allwinner: phy-sun6i-mipi-dphy: Add a variant power-on hook
  phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY variant

 .../phy/allwinner,sun6i-a31-mipi-dphy.yaml    |   8 +
 arch/arm/boot/dts/sun8i-a33.dtsi              |   1 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi |   1 +
 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c   | 235 +++++++++++++++---
 4 files changed, 214 insertions(+), 31 deletions(-)

-- 
2.35.1

[PATCH 0/8] phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY

[Samuel Holland]

This series adds support for the updated DPHY found in a couple of
recent Allwinner SoCs. The first three patches fix an omission in the
existing binding. The remaining patches add the new hardware variant.


Samuel Holland (8):
  dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property
  ARM: dts: sun8i: a33: Add DPHY interrupt
  arm64: dts: allwinner: a64: Add DPHY interrupt
  dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant
  phy: allwinner: phy-sun6i-mipi-dphy: Make RX support optional
  phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last
  phy: allwinner: phy-sun6i-mipi-dphy: Add a variant power-on hook
  phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY variant

 .../phy/allwinner,sun6i-a31-mipi-dphy.yaml    |   8 +
 arch/arm/boot/dts/sun8i-a33.dtsi              |   1 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi |   1 +
 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c   | 235 +++++++++++++++---
 4 files changed, 214 insertions(+), 31 deletions(-)

-- 
2.35.1


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[PATCH 0/8] phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY

[Samuel Holland]

This series adds support for the updated DPHY found in a couple of
recent Allwinner SoCs. The first three patches fix an omission in the
existing binding. The remaining patches add the new hardware variant.


Samuel Holland (8):
  dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property
  ARM: dts: sun8i: a33: Add DPHY interrupt
  arm64: dts: allwinner: a64: Add DPHY interrupt
  dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant
  phy: allwinner: phy-sun6i-mipi-dphy: Make RX support optional
  phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last
  phy: allwinner: phy-sun6i-mipi-dphy: Add a variant power-on hook
  phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY variant

 .../phy/allwinner,sun6i-a31-mipi-dphy.yaml    |   8 +
 arch/arm/boot/dts/sun8i-a33.dtsi              |   1 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi |   1 +
 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c   | 235 +++++++++++++++---
 4 files changed, 214 insertions(+), 31 deletions(-)

-- 
2.35.1


-- 
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[PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Samuel Holland]

The sun6i DPHY can generate several interrupts, mostly for reporting
error conditions, but also for detecting BTA and UPLS sequences.
Document this capability in order to accurately describe the hardware.

The DPHY has no interrupt number provided in the vendor documentation
because its interrupt line is shared with the DSI controller.

Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
index 22636c9fdab8..cf49bd99b3e2 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
@@ -24,6 +24,9 @@ properties:
   reg:
     maxItems: 1
 
+  interrupts:
+    maxItems: 1
+
   clocks:
     items:
       - description: Bus Clock
@@ -53,6 +56,7 @@ required:
   - "#phy-cells"
   - compatible
   - reg
+  - interrupts
   - clocks
   - clock-names
   - resets
-- 
2.35.1

[PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Samuel Holland]

The sun6i DPHY can generate several interrupts, mostly for reporting
error conditions, but also for detecting BTA and UPLS sequences.
Document this capability in order to accurately describe the hardware.

The DPHY has no interrupt number provided in the vendor documentation
because its interrupt line is shared with the DSI controller.

Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
index 22636c9fdab8..cf49bd99b3e2 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
@@ -24,6 +24,9 @@ properties:
   reg:
     maxItems: 1
 
+  interrupts:
+    maxItems: 1
+
   clocks:
     items:
       - description: Bus Clock
@@ -53,6 +56,7 @@ required:
   - "#phy-cells"
   - compatible
   - reg
+  - interrupts
   - clocks
   - clock-names
   - resets
-- 
2.35.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Samuel Holland]

The sun6i DPHY can generate several interrupts, mostly for reporting
error conditions, but also for detecting BTA and UPLS sequences.
Document this capability in order to accurately describe the hardware.

The DPHY has no interrupt number provided in the vendor documentation
because its interrupt line is shared with the DSI controller.

Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
index 22636c9fdab8..cf49bd99b3e2 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
@@ -24,6 +24,9 @@ properties:
   reg:
     maxItems: 1
 
+  interrupts:
+    maxItems: 1
+
   clocks:
     items:
       - description: Bus Clock
@@ -53,6 +56,7 @@ required:
   - "#phy-cells"
   - compatible
   - reg
+  - interrupts
   - clocks
   - clock-names
   - resets
-- 
2.35.1


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[PATCH 2/8] ARM: dts: sun8i: a33: Add DPHY interrupt

[Samuel Holland]

The DPHY has an interrupt line which is shared with the DSI controller.

Fixes: 88fe315d2c0a ("ARM: dts: sun8i: a33: Add the DSI-related nodes")
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 arch/arm/boot/dts/sun8i-a33.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index b3d1bdfb5118..30fdd2703b1f 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -278,6 +278,7 @@ dsi_in_tcon0: endpoint {
 		dphy: d-phy@1ca1000 {
 			compatible = "allwinner,sun6i-a31-mipi-dphy";
 			reg = <0x01ca1000 0x1000>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_MIPI_DSI>,
 				 <&ccu CLK_DSI_DPHY>;
 			clock-names = "bus", "mod";
-- 
2.35.1

[PATCH 2/8] ARM: dts: sun8i: a33: Add DPHY interrupt

[Samuel Holland]

The DPHY has an interrupt line which is shared with the DSI controller.

Fixes: 88fe315d2c0a ("ARM: dts: sun8i: a33: Add the DSI-related nodes")
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 arch/arm/boot/dts/sun8i-a33.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index b3d1bdfb5118..30fdd2703b1f 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -278,6 +278,7 @@ dsi_in_tcon0: endpoint {
 		dphy: d-phy@1ca1000 {
 			compatible = "allwinner,sun6i-a31-mipi-dphy";
 			reg = <0x01ca1000 0x1000>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_MIPI_DSI>,
 				 <&ccu CLK_DSI_DPHY>;
 			clock-names = "bus", "mod";
-- 
2.35.1


_______________________________________________
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[PATCH 2/8] ARM: dts: sun8i: a33: Add DPHY interrupt

[Samuel Holland]

The DPHY has an interrupt line which is shared with the DSI controller.

Fixes: 88fe315d2c0a ("ARM: dts: sun8i: a33: Add the DSI-related nodes")
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 arch/arm/boot/dts/sun8i-a33.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index b3d1bdfb5118..30fdd2703b1f 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -278,6 +278,7 @@ dsi_in_tcon0: endpoint {
 		dphy: d-phy@1ca1000 {
 			compatible = "allwinner,sun6i-a31-mipi-dphy";
 			reg = <0x01ca1000 0x1000>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_MIPI_DSI>,
 				 <&ccu CLK_DSI_DPHY>;
 			clock-names = "bus", "mod";
-- 
2.35.1


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https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH 3/8] arm64: dts: allwinner: a64: Add DPHY interrupt

[Samuel Holland]

The DPHY has an interrupt line which is shared with the DSI controller.

Fixes: 16c8ff571a16 ("arm64: dts: allwinner: a64: Add MIPI DSI pipeline")
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 77b5349f6087..62f45f71ec65 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -1199,6 +1199,7 @@ dphy: d-phy@1ca1000 {
 			compatible = "allwinner,sun50i-a64-mipi-dphy",
 				     "allwinner,sun6i-a31-mipi-dphy";
 			reg = <0x01ca1000 0x1000>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_MIPI_DSI>,
 				 <&ccu CLK_DSI_DPHY>;
 			clock-names = "bus", "mod";
-- 
2.35.1

[PATCH 3/8] arm64: dts: allwinner: a64: Add DPHY interrupt

[Samuel Holland]

The DPHY has an interrupt line which is shared with the DSI controller.

Fixes: 16c8ff571a16 ("arm64: dts: allwinner: a64: Add MIPI DSI pipeline")
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 77b5349f6087..62f45f71ec65 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -1199,6 +1199,7 @@ dphy: d-phy@1ca1000 {
 			compatible = "allwinner,sun50i-a64-mipi-dphy",
 				     "allwinner,sun6i-a31-mipi-dphy";
 			reg = <0x01ca1000 0x1000>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_MIPI_DSI>,
 				 <&ccu CLK_DSI_DPHY>;
 			clock-names = "bus", "mod";
-- 
2.35.1


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[PATCH 3/8] arm64: dts: allwinner: a64: Add DPHY interrupt

[Samuel Holland]

The DPHY has an interrupt line which is shared with the DSI controller.

Fixes: 16c8ff571a16 ("arm64: dts: allwinner: a64: Add MIPI DSI pipeline")
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 77b5349f6087..62f45f71ec65 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -1199,6 +1199,7 @@ dphy: d-phy@1ca1000 {
 			compatible = "allwinner,sun50i-a64-mipi-dphy",
 				     "allwinner,sun6i-a31-mipi-dphy";
 			reg = <0x01ca1000 0x1000>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_MIPI_DSI>,
 				 <&ccu CLK_DSI_DPHY>;
 			clock-names = "bus", "mod";
-- 
2.35.1


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[PATCH 4/8] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant

[Samuel Holland]

A100 features an updated DPHY, which moves PLL control inside the DPHY
register space. (Previously PLL-MIPI was controlled from the CCU. This
does not affect the "clocks" property because the link between PLL-MIPI
and the DPHY was never represented in the devicetree.) It also requires
a modified analog power-on sequence. Finally, the new DPHY adds support
for operating as an LVDS PHY. D1 uses this same variant.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
index cf49bd99b3e2..b88c4b52af7d 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
@@ -17,9 +17,13 @@ properties:
   compatible:
     oneOf:
       - const: allwinner,sun6i-a31-mipi-dphy
+      - const: allwinner,sun50i-a100-mipi-dphy
       - items:
           - const: allwinner,sun50i-a64-mipi-dphy
           - const: allwinner,sun6i-a31-mipi-dphy
+      - items:
+          - const: allwinner,sun20i-d1-mipi-dphy
+          - const: allwinner,sun50i-a100-mipi-dphy
 
   reg:
     maxItems: 1
-- 
2.35.1

[PATCH 4/8] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant

[Samuel Holland]

A100 features an updated DPHY, which moves PLL control inside the DPHY
register space. (Previously PLL-MIPI was controlled from the CCU. This
does not affect the "clocks" property because the link between PLL-MIPI
and the DPHY was never represented in the devicetree.) It also requires
a modified analog power-on sequence. Finally, the new DPHY adds support
for operating as an LVDS PHY. D1 uses this same variant.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
index cf49bd99b3e2..b88c4b52af7d 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
@@ -17,9 +17,13 @@ properties:
   compatible:
     oneOf:
       - const: allwinner,sun6i-a31-mipi-dphy
+      - const: allwinner,sun50i-a100-mipi-dphy
       - items:
           - const: allwinner,sun50i-a64-mipi-dphy
           - const: allwinner,sun6i-a31-mipi-dphy
+      - items:
+          - const: allwinner,sun20i-d1-mipi-dphy
+          - const: allwinner,sun50i-a100-mipi-dphy
 
   reg:
     maxItems: 1
-- 
2.35.1


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[PATCH 4/8] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant

[Samuel Holland]

A100 features an updated DPHY, which moves PLL control inside the DPHY
register space. (Previously PLL-MIPI was controlled from the CCU. This
does not affect the "clocks" property because the link between PLL-MIPI
and the DPHY was never represented in the devicetree.) It also requires
a modified analog power-on sequence. Finally, the new DPHY adds support
for operating as an LVDS PHY. D1 uses this same variant.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
index cf49bd99b3e2..b88c4b52af7d 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
@@ -17,9 +17,13 @@ properties:
   compatible:
     oneOf:
       - const: allwinner,sun6i-a31-mipi-dphy
+      - const: allwinner,sun50i-a100-mipi-dphy
       - items:
           - const: allwinner,sun50i-a64-mipi-dphy
           - const: allwinner,sun6i-a31-mipi-dphy
+      - items:
+          - const: allwinner,sun20i-d1-mipi-dphy
+          - const: allwinner,sun50i-a100-mipi-dphy
 
   reg:
     maxItems: 1
-- 
2.35.1


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[PATCH 5/8] phy: allwinner: phy-sun6i-mipi-dphy: Make RX support optional

[Samuel Holland]

While all variants of the DPHY likely support RX mode, the new variant
in the A100 is not used in this direction by the BSP, and it has some
analog register changes, so its RX power-on sequence is unknown. To be
safe, limit RX support to variants where the power-on sequence is known.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 25 +++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 3900f1650851..625c6e1e9990 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -114,6 +114,10 @@ enum sun6i_dphy_direction {
 	SUN6I_DPHY_DIRECTION_RX,
 };
 
+struct sun6i_dphy_variant {
+	bool	supports_rx;
+};
+
 struct sun6i_dphy {
 	struct clk				*bus_clk;
 	struct clk				*mod_clk;
@@ -123,6 +127,7 @@ struct sun6i_dphy {
 	struct phy				*phy;
 	struct phy_configure_opts_mipi_dphy	config;
 
+	const struct sun6i_dphy_variant		*variant;
 	enum sun6i_dphy_direction		direction;
 };
 
@@ -409,6 +414,10 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
 	if (!dphy)
 		return -ENOMEM;
 
+	dphy->variant = device_get_match_data(&pdev->dev);
+	if (!dphy->variant)
+		return -EINVAL;
+
 	regs = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(regs)) {
 		dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
@@ -445,8 +454,13 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
 	ret = of_property_read_string(pdev->dev.of_node, "allwinner,direction",
 				      &direction);
 
-	if (!ret && !strncmp(direction, "rx", 2))
+	if (!ret && !strncmp(direction, "rx", 2)) {
+		if (!dphy->variant->supports_rx) {
+			dev_err(&pdev->dev, "RX not supported on this variant\n");
+			return -EOPNOTSUPP;
+		}
 		dphy->direction = SUN6I_DPHY_DIRECTION_RX;
+	}
 
 	phy_set_drvdata(dphy->phy, dphy);
 	phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
@@ -454,8 +468,15 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
 	return PTR_ERR_OR_ZERO(phy_provider);
 }
 
+static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
+	.supports_rx	= true,
+};
+
 static const struct of_device_id sun6i_dphy_of_table[] = {
-	{ .compatible = "allwinner,sun6i-a31-mipi-dphy" },
+	{
+		.compatible	= "allwinner,sun6i-a31-mipi-dphy",
+		.data		= &sun6i_a31_mipi_dphy_variant,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
-- 
2.35.1

[PATCH 5/8] phy: allwinner: phy-sun6i-mipi-dphy: Make RX support optional

[Samuel Holland]

While all variants of the DPHY likely support RX mode, the new variant
in the A100 is not used in this direction by the BSP, and it has some
analog register changes, so its RX power-on sequence is unknown. To be
safe, limit RX support to variants where the power-on sequence is known.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 25 +++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 3900f1650851..625c6e1e9990 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -114,6 +114,10 @@ enum sun6i_dphy_direction {
 	SUN6I_DPHY_DIRECTION_RX,
 };
 
+struct sun6i_dphy_variant {
+	bool	supports_rx;
+};
+
 struct sun6i_dphy {
 	struct clk				*bus_clk;
 	struct clk				*mod_clk;
@@ -123,6 +127,7 @@ struct sun6i_dphy {
 	struct phy				*phy;
 	struct phy_configure_opts_mipi_dphy	config;
 
+	const struct sun6i_dphy_variant		*variant;
 	enum sun6i_dphy_direction		direction;
 };
 
@@ -409,6 +414,10 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
 	if (!dphy)
 		return -ENOMEM;
 
+	dphy->variant = device_get_match_data(&pdev->dev);
+	if (!dphy->variant)
+		return -EINVAL;
+
 	regs = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(regs)) {
 		dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
@@ -445,8 +454,13 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
 	ret = of_property_read_string(pdev->dev.of_node, "allwinner,direction",
 				      &direction);
 
-	if (!ret && !strncmp(direction, "rx", 2))
+	if (!ret && !strncmp(direction, "rx", 2)) {
+		if (!dphy->variant->supports_rx) {
+			dev_err(&pdev->dev, "RX not supported on this variant\n");
+			return -EOPNOTSUPP;
+		}
 		dphy->direction = SUN6I_DPHY_DIRECTION_RX;
+	}
 
 	phy_set_drvdata(dphy->phy, dphy);
 	phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
@@ -454,8 +468,15 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
 	return PTR_ERR_OR_ZERO(phy_provider);
 }
 
+static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
+	.supports_rx	= true,
+};
+
 static const struct of_device_id sun6i_dphy_of_table[] = {
-	{ .compatible = "allwinner,sun6i-a31-mipi-dphy" },
+	{
+		.compatible	= "allwinner,sun6i-a31-mipi-dphy",
+		.data		= &sun6i_a31_mipi_dphy_variant,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
-- 
2.35.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH 5/8] phy: allwinner: phy-sun6i-mipi-dphy: Make RX support optional

[Samuel Holland]

While all variants of the DPHY likely support RX mode, the new variant
in the A100 is not used in this direction by the BSP, and it has some
analog register changes, so its RX power-on sequence is unknown. To be
safe, limit RX support to variants where the power-on sequence is known.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 25 +++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 3900f1650851..625c6e1e9990 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -114,6 +114,10 @@ enum sun6i_dphy_direction {
 	SUN6I_DPHY_DIRECTION_RX,
 };
 
+struct sun6i_dphy_variant {
+	bool	supports_rx;
+};
+
 struct sun6i_dphy {
 	struct clk				*bus_clk;
 	struct clk				*mod_clk;
@@ -123,6 +127,7 @@ struct sun6i_dphy {
 	struct phy				*phy;
 	struct phy_configure_opts_mipi_dphy	config;
 
+	const struct sun6i_dphy_variant		*variant;
 	enum sun6i_dphy_direction		direction;
 };
 
@@ -409,6 +414,10 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
 	if (!dphy)
 		return -ENOMEM;
 
+	dphy->variant = device_get_match_data(&pdev->dev);
+	if (!dphy->variant)
+		return -EINVAL;
+
 	regs = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(regs)) {
 		dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
@@ -445,8 +454,13 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
 	ret = of_property_read_string(pdev->dev.of_node, "allwinner,direction",
 				      &direction);
 
-	if (!ret && !strncmp(direction, "rx", 2))
+	if (!ret && !strncmp(direction, "rx", 2)) {
+		if (!dphy->variant->supports_rx) {
+			dev_err(&pdev->dev, "RX not supported on this variant\n");
+			return -EOPNOTSUPP;
+		}
 		dphy->direction = SUN6I_DPHY_DIRECTION_RX;
+	}
 
 	phy_set_drvdata(dphy->phy, dphy);
 	phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
@@ -454,8 +468,15 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
 	return PTR_ERR_OR_ZERO(phy_provider);
 }
 
+static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
+	.supports_rx	= true,
+};
+
 static const struct of_device_id sun6i_dphy_of_table[] = {
-	{ .compatible = "allwinner,sun6i-a31-mipi-dphy" },
+	{
+		.compatible	= "allwinner,sun6i-a31-mipi-dphy",
+		.data		= &sun6i_a31_mipi_dphy_variant,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
-- 
2.35.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last

[Samuel Holland]

The A100 variant of the DPHY requires configuring the analog registers
before setting the global enable bit. Since this order also works on the
other variants, always use it, to minimize the differences between them.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 625c6e1e9990..9698d68d0db7 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
 		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
 		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
 
-	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
-		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
-		     SUN6I_DPHY_GCTL_EN);
-
 	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
 		     SUN6I_DPHY_ANA0_REG_PWS |
 		     SUN6I_DPHY_ANA0_REG_DMPC |
@@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
 			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
 			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
 
+	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
+		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
+		     SUN6I_DPHY_GCTL_EN);
+
 	return 0;
 }
 
-- 
2.35.1

[PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last

[Samuel Holland]

The A100 variant of the DPHY requires configuring the analog registers
before setting the global enable bit. Since this order also works on the
other variants, always use it, to minimize the differences between them.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 625c6e1e9990..9698d68d0db7 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
 		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
 		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
 
-	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
-		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
-		     SUN6I_DPHY_GCTL_EN);
-
 	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
 		     SUN6I_DPHY_ANA0_REG_PWS |
 		     SUN6I_DPHY_ANA0_REG_DMPC |
@@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
 			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
 			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
 
+	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
+		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
+		     SUN6I_DPHY_GCTL_EN);
+
 	return 0;
 }
 
-- 
2.35.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last

[Samuel Holland]

The A100 variant of the DPHY requires configuring the analog registers
before setting the global enable bit. Since this order also works on the
other variants, always use it, to minimize the differences between them.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 625c6e1e9990..9698d68d0db7 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
 		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
 		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
 
-	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
-		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
-		     SUN6I_DPHY_GCTL_EN);
-
 	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
 		     SUN6I_DPHY_ANA0_REG_PWS |
 		     SUN6I_DPHY_ANA0_REG_DMPC |
@@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
 			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
 			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
 
+	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
+		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
+		     SUN6I_DPHY_GCTL_EN);
+
 	return 0;
 }
 
-- 
2.35.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH 7/8] phy: allwinner: phy-sun6i-mipi-dphy: Add a variant power-on hook

[Samuel Holland]

The A100 variant uses the same values for the timing registers, and it
uses the same final power-on sequence, but it needs a different analog
register configuration in the middle. Support this by moving the
variant-specific parts to a hook provided by the variant.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 59 ++++++++++++---------
 1 file changed, 35 insertions(+), 24 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 9698d68d0db7..6a1993c434e8 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -114,7 +114,10 @@ enum sun6i_dphy_direction {
 	SUN6I_DPHY_DIRECTION_RX,
 };
 
+struct sun6i_dphy;
+
 struct sun6i_dphy_variant {
+	void	(*tx_power_on)(struct sun6i_dphy *dphy);
 	bool	supports_rx;
 };
 
@@ -156,33 +159,10 @@ static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
 	return 0;
 }
 
-static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
+static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
 {
 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
 
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
-		     SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
-		     SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
-		     SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
-		     SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
-		     SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
-		     SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
-		     SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
-		     SUN6I_DPHY_TX_TIME1_CLK_POST(10));
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
-		     SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
-		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
-		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
-
 	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
 		     SUN6I_DPHY_ANA0_REG_PWS |
 		     SUN6I_DPHY_ANA0_REG_DMPC |
@@ -214,6 +194,36 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
 		     SUN6I_DPHY_ANA3_EN_LDOC |
 		     SUN6I_DPHY_ANA3_EN_LDOD);
 	udelay(1);
+}
+
+static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
+{
+	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
+		     SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
+		     SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
+		     SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
+		     SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
+		     SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
+		     SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
+		     SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
+		     SUN6I_DPHY_TX_TIME1_CLK_POST(10));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
+		     SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
+		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
+		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
+
+	dphy->variant->tx_power_on(dphy);
 
 	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
 			   SUN6I_DPHY_ANA3_EN_VTTC |
@@ -469,6 +479,7 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
 }
 
 static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
+	.tx_power_on	= sun6i_a31_mipi_dphy_tx_power_on,
 	.supports_rx	= true,
 };
 
-- 
2.35.1

[PATCH 7/8] phy: allwinner: phy-sun6i-mipi-dphy: Add a variant power-on hook

[Samuel Holland]

The A100 variant uses the same values for the timing registers, and it
uses the same final power-on sequence, but it needs a different analog
register configuration in the middle. Support this by moving the
variant-specific parts to a hook provided by the variant.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 59 ++++++++++++---------
 1 file changed, 35 insertions(+), 24 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 9698d68d0db7..6a1993c434e8 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -114,7 +114,10 @@ enum sun6i_dphy_direction {
 	SUN6I_DPHY_DIRECTION_RX,
 };
 
+struct sun6i_dphy;
+
 struct sun6i_dphy_variant {
+	void	(*tx_power_on)(struct sun6i_dphy *dphy);
 	bool	supports_rx;
 };
 
@@ -156,33 +159,10 @@ static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
 	return 0;
 }
 
-static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
+static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
 {
 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
 
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
-		     SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
-		     SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
-		     SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
-		     SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
-		     SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
-		     SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
-		     SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
-		     SUN6I_DPHY_TX_TIME1_CLK_POST(10));
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
-		     SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
-		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
-		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
-
 	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
 		     SUN6I_DPHY_ANA0_REG_PWS |
 		     SUN6I_DPHY_ANA0_REG_DMPC |
@@ -214,6 +194,36 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
 		     SUN6I_DPHY_ANA3_EN_LDOC |
 		     SUN6I_DPHY_ANA3_EN_LDOD);
 	udelay(1);
+}
+
+static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
+{
+	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
+		     SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
+		     SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
+		     SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
+		     SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
+		     SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
+		     SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
+		     SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
+		     SUN6I_DPHY_TX_TIME1_CLK_POST(10));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
+		     SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
+		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
+		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
+
+	dphy->variant->tx_power_on(dphy);
 
 	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
 			   SUN6I_DPHY_ANA3_EN_VTTC |
@@ -469,6 +479,7 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
 }
 
 static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
+	.tx_power_on	= sun6i_a31_mipi_dphy_tx_power_on,
 	.supports_rx	= true,
 };
 
-- 
2.35.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 7/8] phy: allwinner: phy-sun6i-mipi-dphy: Add a variant power-on hook

[Samuel Holland]

The A100 variant uses the same values for the timing registers, and it
uses the same final power-on sequence, but it needs a different analog
register configuration in the middle. Support this by moving the
variant-specific parts to a hook provided by the variant.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 59 ++++++++++++---------
 1 file changed, 35 insertions(+), 24 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 9698d68d0db7..6a1993c434e8 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -114,7 +114,10 @@ enum sun6i_dphy_direction {
 	SUN6I_DPHY_DIRECTION_RX,
 };
 
+struct sun6i_dphy;
+
 struct sun6i_dphy_variant {
+	void	(*tx_power_on)(struct sun6i_dphy *dphy);
 	bool	supports_rx;
 };
 
@@ -156,33 +159,10 @@ static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
 	return 0;
 }
 
-static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
+static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
 {
 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
 
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
-		     SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
-		     SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
-		     SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
-		     SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
-		     SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
-		     SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
-		     SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
-		     SUN6I_DPHY_TX_TIME1_CLK_POST(10));
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
-		     SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
-
-	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
-		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
-		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
-
 	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
 		     SUN6I_DPHY_ANA0_REG_PWS |
 		     SUN6I_DPHY_ANA0_REG_DMPC |
@@ -214,6 +194,36 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
 		     SUN6I_DPHY_ANA3_EN_LDOC |
 		     SUN6I_DPHY_ANA3_EN_LDOD);
 	udelay(1);
+}
+
+static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
+{
+	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
+		     SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
+		     SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
+		     SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
+		     SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
+		     SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
+		     SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
+		     SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
+		     SUN6I_DPHY_TX_TIME1_CLK_POST(10));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
+		     SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
+		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
+		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
+
+	dphy->variant->tx_power_on(dphy);
 
 	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
 			   SUN6I_DPHY_ANA3_EN_VTTC |
@@ -469,6 +479,7 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
 }
 
 static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
+	.tx_power_on	= sun6i_a31_mipi_dphy_tx_power_on,
 	.supports_rx	= true,
 };
 
-- 
2.35.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH 8/8] phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY variant

[Samuel Holland]

A100 features an updated DPHY, which moves PLL control inside the DPHY
register space (previously the PLL was controlled from the CCU). It also
requires a modified analog power-on sequence. This "combo PHY" can also
be used as an LVDS PHY, but that is not yet supported by the driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 143 +++++++++++++++++++-
 1 file changed, 142 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 6a1993c434e8..9911c4a5c318 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -70,11 +70,19 @@
 
 #define SUN6I_DPHY_ANA0_REG		0x4c
 #define SUN6I_DPHY_ANA0_REG_PWS			BIT(31)
+#define SUN6I_DPHY_ANA0_REG_PWEND		BIT(30)
+#define SUN6I_DPHY_ANA0_REG_PWENC		BIT(29)
 #define SUN6I_DPHY_ANA0_REG_DMPC		BIT(28)
 #define SUN6I_DPHY_ANA0_REG_DMPD(n)		(((n) & 0xf) << 24)
+#define SUN6I_DPHY_ANA0_REG_SRXDT(n)		(((n) & 0xf) << 20)
+#define SUN6I_DPHY_ANA0_REG_SRXCK(n)		(((n) & 0xf) << 16)
+#define SUN6I_DPHY_ANA0_REG_SDIV2		BIT(15)
 #define SUN6I_DPHY_ANA0_REG_SLV(n)		(((n) & 7) << 12)
 #define SUN6I_DPHY_ANA0_REG_DEN(n)		(((n) & 0xf) << 8)
+#define SUN6I_DPHY_ANA0_REG_PLR(n)		(((n) & 0xf) << 4)
 #define SUN6I_DPHY_ANA0_REG_SFB(n)		(((n) & 3) << 2)
+#define SUN6I_DPHY_ANA0_REG_RSD			BIT(1)
+#define SUN6I_DPHY_ANA0_REG_SELSCK		BIT(0)
 
 #define SUN6I_DPHY_ANA1_REG		0x50
 #define SUN6I_DPHY_ANA1_REG_VTTMODE		BIT(31)
@@ -97,8 +105,13 @@
 #define SUN6I_DPHY_ANA3_EN_LDOR			BIT(18)
 
 #define SUN6I_DPHY_ANA4_REG		0x5c
+#define SUN6I_DPHY_ANA4_REG_EN_MIPI		BIT(31)
+#define SUN6I_DPHY_ANA4_REG_EN_COMTEST		BIT(30)
+#define SUN6I_DPHY_ANA4_REG_COMTEST(n)		(((n) & 3) << 28)
+#define SUN6I_DPHY_ANA4_REG_IB(n)		(((n) & 3) << 25)
 #define SUN6I_DPHY_ANA4_REG_DMPLVC		BIT(24)
 #define SUN6I_DPHY_ANA4_REG_DMPLVD(n)		(((n) & 0xf) << 20)
+#define SUN6I_DPHY_ANA4_REG_VTT_SET(n)		(((n) & 0x7) << 17)
 #define SUN6I_DPHY_ANA4_REG_CKDV(n)		(((n) & 0x1f) << 12)
 #define SUN6I_DPHY_ANA4_REG_TMSC(n)		(((n) & 3) << 10)
 #define SUN6I_DPHY_ANA4_REG_TMSD(n)		(((n) & 3) << 8)
@@ -109,6 +122,56 @@
 
 #define SUN6I_DPHY_DBG5_REG		0xf4
 
+#define SUN50I_DPHY_TX_SLEW_REG0	0xf8
+#define SUN50I_DPHY_TX_SLEW_REG1	0xfc
+#define SUN50I_DPHY_TX_SLEW_REG2	0x100
+
+#define SUN50I_DPHY_PLL_REG0		0x104
+#define SUN50I_DPHY_PLL_REG0_CP36_EN		BIT(23)
+#define SUN50I_DPHY_PLL_REG0_LDO_EN		BIT(22)
+#define SUN50I_DPHY_PLL_REG0_EN_LVS		BIT(21)
+#define SUN50I_DPHY_PLL_REG0_PLL_EN		BIT(20)
+#define SUN50I_DPHY_PLL_REG0_P(n)		(((n) & 0xf) << 16)
+#define SUN50I_DPHY_PLL_REG0_N(n)		(((n) & 0xff) << 8)
+#define SUN50I_DPHY_PLL_REG0_NDET		BIT(7)
+#define SUN50I_DPHY_PLL_REG0_TDIV		BIT(6)
+#define SUN50I_DPHY_PLL_REG0_M0(n)		(((n) & 3) << 4)
+#define SUN50I_DPHY_PLL_REG0_M1(n)		((n) & 0xf)
+
+#define SUN50I_DPHY_PLL_REG1		0x108
+#define SUN50I_DPHY_PLL_REG1_UNLOCK_MDSEL(n)	(((n) & 3) << 14)
+#define SUN50I_DPHY_PLL_REG1_LOCKMDSEL		BIT(13)
+#define SUN50I_DPHY_PLL_REG1_LOCKDET_EN		BIT(12)
+#define SUN50I_DPHY_PLL_REG1_VSETA(n)		(((n) & 0x7) << 9)
+#define SUN50I_DPHY_PLL_REG1_VSETD(n)		(((n) & 0x7) << 6)
+#define SUN50I_DPHY_PLL_REG1_LPF_SW		BIT(5)
+#define SUN50I_DPHY_PLL_REG1_ICP_SEL(n)		(((n) & 3) << 3)
+#define SUN50I_DPHY_PLL_REG1_ATEST_SEL(n)	(((n) & 3) << 1)
+#define SUN50I_DPHY_PLL_REG1_TEST_EN		BIT(0)
+
+#define SUN50I_DPHY_PLL_REG2		0x10c
+#define SUN50I_DPHY_PLL_REG2_SDM_EN		BIT(31)
+#define SUN50I_DPHY_PLL_REG2_FF_EN		BIT(30)
+#define SUN50I_DPHY_PLL_REG2_SS_EN		BIT(29)
+#define SUN50I_DPHY_PLL_REG2_SS_FRAC(n)		(((n) & 0x1ff) << 20)
+#define SUN50I_DPHY_PLL_REG2_SS_INT(n)		(((n) & 0xff) << 12)
+#define SUN50I_DPHY_PLL_REG2_FRAC(n)		((n) & 0xfff)
+
+#define SUN50I_COMBO_PHY_REG0		0x110
+#define SUN50I_COMBO_PHY_REG0_EN_TEST_COMBOLDO	BIT(5)
+#define SUN50I_COMBO_PHY_REG0_EN_TEST_0P8	BIT(4)
+#define SUN50I_COMBO_PHY_REG0_EN_MIPI		BIT(3)
+#define SUN50I_COMBO_PHY_REG0_EN_LVDS		BIT(2)
+#define SUN50I_COMBO_PHY_REG0_EN_COMBOLDO	BIT(1)
+#define SUN50I_COMBO_PHY_REG0_EN_CP		BIT(0)
+
+#define SUN50I_COMBO_PHY_REG1		0x114
+#define SUN50I_COMBO_PHY_REG2_REG_VREF1P6(n)	(((n) & 0x7) << 4)
+#define SUN50I_COMBO_PHY_REG2_REG_VREF0P8(n)	((n) & 0x7)
+
+#define SUN50I_COMBO_PHY_REG2		0x118
+#define SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(n)	((n) & 0xff)
+
 enum sun6i_dphy_direction {
 	SUN6I_DPHY_DIRECTION_TX,
 	SUN6I_DPHY_DIRECTION_RX,
@@ -196,6 +259,76 @@ static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
 	udelay(1);
 }
 
+static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
+{
+	unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
+	unsigned int div, n;
+
+	regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
+		     SUN6I_DPHY_ANA4_REG_IB(2) |
+		     SUN6I_DPHY_ANA4_REG_DMPLVD(4) |
+		     SUN6I_DPHY_ANA4_REG_VTT_SET(3) |
+		     SUN6I_DPHY_ANA4_REG_CKDV(3) |
+		     SUN6I_DPHY_ANA4_REG_TMSD(1) |
+		     SUN6I_DPHY_ANA4_REG_TMSC(1) |
+		     SUN6I_DPHY_ANA4_REG_TXPUSD(2) |
+		     SUN6I_DPHY_ANA4_REG_TXPUSC(3) |
+		     SUN6I_DPHY_ANA4_REG_TXDNSD(2) |
+		     SUN6I_DPHY_ANA4_REG_TXDNSC(3));
+
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
+			   SUN6I_DPHY_ANA2_EN_CK_CPU,
+			   SUN6I_DPHY_ANA2_EN_CK_CPU);
+
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
+			   SUN6I_DPHY_ANA2_REG_ENIB,
+			   SUN6I_DPHY_ANA2_REG_ENIB);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
+		     SUN6I_DPHY_ANA3_EN_LDOR |
+		     SUN6I_DPHY_ANA3_EN_LDOC |
+		     SUN6I_DPHY_ANA3_EN_LDOD);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
+		     SUN6I_DPHY_ANA0_REG_PLR(4) |
+		     SUN6I_DPHY_ANA0_REG_SFB(1));
+
+	regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0,
+		     SUN50I_COMBO_PHY_REG0_EN_CP);
+
+	/* Choose a divider to limit the VCO frequency to around 2 GHz. */
+	div = 16 >> order_base_2(DIV_ROUND_UP(mipi_symbol_rate, 264000000));
+	n = mipi_symbol_rate * div / 24000000;
+
+	regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG0,
+		     SUN50I_DPHY_PLL_REG0_CP36_EN |
+		     SUN50I_DPHY_PLL_REG0_LDO_EN |
+		     SUN50I_DPHY_PLL_REG0_EN_LVS |
+		     SUN50I_DPHY_PLL_REG0_PLL_EN |
+		     SUN50I_DPHY_PLL_REG0_NDET |
+		     SUN50I_DPHY_PLL_REG0_P((div - 1) % 8) |
+		     SUN50I_DPHY_PLL_REG0_N(n) |
+		     SUN50I_DPHY_PLL_REG0_M0((div - 1) / 8) |
+		     SUN50I_DPHY_PLL_REG0_M1(2));
+
+	/* Disable sigma-delta modulation. */
+	regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0);
+
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
+			   SUN6I_DPHY_ANA4_REG_EN_MIPI,
+			   SUN6I_DPHY_ANA4_REG_EN_MIPI);
+
+	regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
+			   SUN50I_COMBO_PHY_REG0_EN_MIPI |
+			   SUN50I_COMBO_PHY_REG0_EN_COMBOLDO,
+			   SUN50I_COMBO_PHY_REG0_EN_MIPI |
+			   SUN50I_COMBO_PHY_REG0_EN_COMBOLDO);
+
+	regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG2,
+		     SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(20));
+	udelay(1);
+}
+
 static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
 {
 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
@@ -408,7 +541,7 @@ static const struct regmap_config sun6i_dphy_regmap_config = {
 	.reg_bits	= 32,
 	.val_bits	= 32,
 	.reg_stride	= 4,
-	.max_register	= SUN6I_DPHY_DBG5_REG,
+	.max_register	= SUN50I_COMBO_PHY_REG2,
 	.name		= "mipi-dphy",
 };
 
@@ -483,11 +616,19 @@ static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
 	.supports_rx	= true,
 };
 
+static const struct sun6i_dphy_variant sun50i_a100_mipi_dphy_variant = {
+	.tx_power_on	= sun50i_a100_mipi_dphy_tx_power_on,
+};
+
 static const struct of_device_id sun6i_dphy_of_table[] = {
 	{
 		.compatible	= "allwinner,sun6i-a31-mipi-dphy",
 		.data		= &sun6i_a31_mipi_dphy_variant,
 	},
+	{
+		.compatible	= "allwinner,sun50i-a100-mipi-dphy",
+		.data		= &sun50i_a100_mipi_dphy_variant,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
-- 
2.35.1

[PATCH 8/8] phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY variant

[Samuel Holland]

A100 features an updated DPHY, which moves PLL control inside the DPHY
register space (previously the PLL was controlled from the CCU). It also
requires a modified analog power-on sequence. This "combo PHY" can also
be used as an LVDS PHY, but that is not yet supported by the driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 143 +++++++++++++++++++-
 1 file changed, 142 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 6a1993c434e8..9911c4a5c318 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -70,11 +70,19 @@
 
 #define SUN6I_DPHY_ANA0_REG		0x4c
 #define SUN6I_DPHY_ANA0_REG_PWS			BIT(31)
+#define SUN6I_DPHY_ANA0_REG_PWEND		BIT(30)
+#define SUN6I_DPHY_ANA0_REG_PWENC		BIT(29)
 #define SUN6I_DPHY_ANA0_REG_DMPC		BIT(28)
 #define SUN6I_DPHY_ANA0_REG_DMPD(n)		(((n) & 0xf) << 24)
+#define SUN6I_DPHY_ANA0_REG_SRXDT(n)		(((n) & 0xf) << 20)
+#define SUN6I_DPHY_ANA0_REG_SRXCK(n)		(((n) & 0xf) << 16)
+#define SUN6I_DPHY_ANA0_REG_SDIV2		BIT(15)
 #define SUN6I_DPHY_ANA0_REG_SLV(n)		(((n) & 7) << 12)
 #define SUN6I_DPHY_ANA0_REG_DEN(n)		(((n) & 0xf) << 8)
+#define SUN6I_DPHY_ANA0_REG_PLR(n)		(((n) & 0xf) << 4)
 #define SUN6I_DPHY_ANA0_REG_SFB(n)		(((n) & 3) << 2)
+#define SUN6I_DPHY_ANA0_REG_RSD			BIT(1)
+#define SUN6I_DPHY_ANA0_REG_SELSCK		BIT(0)
 
 #define SUN6I_DPHY_ANA1_REG		0x50
 #define SUN6I_DPHY_ANA1_REG_VTTMODE		BIT(31)
@@ -97,8 +105,13 @@
 #define SUN6I_DPHY_ANA3_EN_LDOR			BIT(18)
 
 #define SUN6I_DPHY_ANA4_REG		0x5c
+#define SUN6I_DPHY_ANA4_REG_EN_MIPI		BIT(31)
+#define SUN6I_DPHY_ANA4_REG_EN_COMTEST		BIT(30)
+#define SUN6I_DPHY_ANA4_REG_COMTEST(n)		(((n) & 3) << 28)
+#define SUN6I_DPHY_ANA4_REG_IB(n)		(((n) & 3) << 25)
 #define SUN6I_DPHY_ANA4_REG_DMPLVC		BIT(24)
 #define SUN6I_DPHY_ANA4_REG_DMPLVD(n)		(((n) & 0xf) << 20)
+#define SUN6I_DPHY_ANA4_REG_VTT_SET(n)		(((n) & 0x7) << 17)
 #define SUN6I_DPHY_ANA4_REG_CKDV(n)		(((n) & 0x1f) << 12)
 #define SUN6I_DPHY_ANA4_REG_TMSC(n)		(((n) & 3) << 10)
 #define SUN6I_DPHY_ANA4_REG_TMSD(n)		(((n) & 3) << 8)
@@ -109,6 +122,56 @@
 
 #define SUN6I_DPHY_DBG5_REG		0xf4
 
+#define SUN50I_DPHY_TX_SLEW_REG0	0xf8
+#define SUN50I_DPHY_TX_SLEW_REG1	0xfc
+#define SUN50I_DPHY_TX_SLEW_REG2	0x100
+
+#define SUN50I_DPHY_PLL_REG0		0x104
+#define SUN50I_DPHY_PLL_REG0_CP36_EN		BIT(23)
+#define SUN50I_DPHY_PLL_REG0_LDO_EN		BIT(22)
+#define SUN50I_DPHY_PLL_REG0_EN_LVS		BIT(21)
+#define SUN50I_DPHY_PLL_REG0_PLL_EN		BIT(20)
+#define SUN50I_DPHY_PLL_REG0_P(n)		(((n) & 0xf) << 16)
+#define SUN50I_DPHY_PLL_REG0_N(n)		(((n) & 0xff) << 8)
+#define SUN50I_DPHY_PLL_REG0_NDET		BIT(7)
+#define SUN50I_DPHY_PLL_REG0_TDIV		BIT(6)
+#define SUN50I_DPHY_PLL_REG0_M0(n)		(((n) & 3) << 4)
+#define SUN50I_DPHY_PLL_REG0_M1(n)		((n) & 0xf)
+
+#define SUN50I_DPHY_PLL_REG1		0x108
+#define SUN50I_DPHY_PLL_REG1_UNLOCK_MDSEL(n)	(((n) & 3) << 14)
+#define SUN50I_DPHY_PLL_REG1_LOCKMDSEL		BIT(13)
+#define SUN50I_DPHY_PLL_REG1_LOCKDET_EN		BIT(12)
+#define SUN50I_DPHY_PLL_REG1_VSETA(n)		(((n) & 0x7) << 9)
+#define SUN50I_DPHY_PLL_REG1_VSETD(n)		(((n) & 0x7) << 6)
+#define SUN50I_DPHY_PLL_REG1_LPF_SW		BIT(5)
+#define SUN50I_DPHY_PLL_REG1_ICP_SEL(n)		(((n) & 3) << 3)
+#define SUN50I_DPHY_PLL_REG1_ATEST_SEL(n)	(((n) & 3) << 1)
+#define SUN50I_DPHY_PLL_REG1_TEST_EN		BIT(0)
+
+#define SUN50I_DPHY_PLL_REG2		0x10c
+#define SUN50I_DPHY_PLL_REG2_SDM_EN		BIT(31)
+#define SUN50I_DPHY_PLL_REG2_FF_EN		BIT(30)
+#define SUN50I_DPHY_PLL_REG2_SS_EN		BIT(29)
+#define SUN50I_DPHY_PLL_REG2_SS_FRAC(n)		(((n) & 0x1ff) << 20)
+#define SUN50I_DPHY_PLL_REG2_SS_INT(n)		(((n) & 0xff) << 12)
+#define SUN50I_DPHY_PLL_REG2_FRAC(n)		((n) & 0xfff)
+
+#define SUN50I_COMBO_PHY_REG0		0x110
+#define SUN50I_COMBO_PHY_REG0_EN_TEST_COMBOLDO	BIT(5)
+#define SUN50I_COMBO_PHY_REG0_EN_TEST_0P8	BIT(4)
+#define SUN50I_COMBO_PHY_REG0_EN_MIPI		BIT(3)
+#define SUN50I_COMBO_PHY_REG0_EN_LVDS		BIT(2)
+#define SUN50I_COMBO_PHY_REG0_EN_COMBOLDO	BIT(1)
+#define SUN50I_COMBO_PHY_REG0_EN_CP		BIT(0)
+
+#define SUN50I_COMBO_PHY_REG1		0x114
+#define SUN50I_COMBO_PHY_REG2_REG_VREF1P6(n)	(((n) & 0x7) << 4)
+#define SUN50I_COMBO_PHY_REG2_REG_VREF0P8(n)	((n) & 0x7)
+
+#define SUN50I_COMBO_PHY_REG2		0x118
+#define SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(n)	((n) & 0xff)
+
 enum sun6i_dphy_direction {
 	SUN6I_DPHY_DIRECTION_TX,
 	SUN6I_DPHY_DIRECTION_RX,
@@ -196,6 +259,76 @@ static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
 	udelay(1);
 }
 
+static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
+{
+	unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
+	unsigned int div, n;
+
+	regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
+		     SUN6I_DPHY_ANA4_REG_IB(2) |
+		     SUN6I_DPHY_ANA4_REG_DMPLVD(4) |
+		     SUN6I_DPHY_ANA4_REG_VTT_SET(3) |
+		     SUN6I_DPHY_ANA4_REG_CKDV(3) |
+		     SUN6I_DPHY_ANA4_REG_TMSD(1) |
+		     SUN6I_DPHY_ANA4_REG_TMSC(1) |
+		     SUN6I_DPHY_ANA4_REG_TXPUSD(2) |
+		     SUN6I_DPHY_ANA4_REG_TXPUSC(3) |
+		     SUN6I_DPHY_ANA4_REG_TXDNSD(2) |
+		     SUN6I_DPHY_ANA4_REG_TXDNSC(3));
+
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
+			   SUN6I_DPHY_ANA2_EN_CK_CPU,
+			   SUN6I_DPHY_ANA2_EN_CK_CPU);
+
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
+			   SUN6I_DPHY_ANA2_REG_ENIB,
+			   SUN6I_DPHY_ANA2_REG_ENIB);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
+		     SUN6I_DPHY_ANA3_EN_LDOR |
+		     SUN6I_DPHY_ANA3_EN_LDOC |
+		     SUN6I_DPHY_ANA3_EN_LDOD);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
+		     SUN6I_DPHY_ANA0_REG_PLR(4) |
+		     SUN6I_DPHY_ANA0_REG_SFB(1));
+
+	regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0,
+		     SUN50I_COMBO_PHY_REG0_EN_CP);
+
+	/* Choose a divider to limit the VCO frequency to around 2 GHz. */
+	div = 16 >> order_base_2(DIV_ROUND_UP(mipi_symbol_rate, 264000000));
+	n = mipi_symbol_rate * div / 24000000;
+
+	regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG0,
+		     SUN50I_DPHY_PLL_REG0_CP36_EN |
+		     SUN50I_DPHY_PLL_REG0_LDO_EN |
+		     SUN50I_DPHY_PLL_REG0_EN_LVS |
+		     SUN50I_DPHY_PLL_REG0_PLL_EN |
+		     SUN50I_DPHY_PLL_REG0_NDET |
+		     SUN50I_DPHY_PLL_REG0_P((div - 1) % 8) |
+		     SUN50I_DPHY_PLL_REG0_N(n) |
+		     SUN50I_DPHY_PLL_REG0_M0((div - 1) / 8) |
+		     SUN50I_DPHY_PLL_REG0_M1(2));
+
+	/* Disable sigma-delta modulation. */
+	regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0);
+
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
+			   SUN6I_DPHY_ANA4_REG_EN_MIPI,
+			   SUN6I_DPHY_ANA4_REG_EN_MIPI);
+
+	regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
+			   SUN50I_COMBO_PHY_REG0_EN_MIPI |
+			   SUN50I_COMBO_PHY_REG0_EN_COMBOLDO,
+			   SUN50I_COMBO_PHY_REG0_EN_MIPI |
+			   SUN50I_COMBO_PHY_REG0_EN_COMBOLDO);
+
+	regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG2,
+		     SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(20));
+	udelay(1);
+}
+
 static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
 {
 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
@@ -408,7 +541,7 @@ static const struct regmap_config sun6i_dphy_regmap_config = {
 	.reg_bits	= 32,
 	.val_bits	= 32,
 	.reg_stride	= 4,
-	.max_register	= SUN6I_DPHY_DBG5_REG,
+	.max_register	= SUN50I_COMBO_PHY_REG2,
 	.name		= "mipi-dphy",
 };
 
@@ -483,11 +616,19 @@ static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
 	.supports_rx	= true,
 };
 
+static const struct sun6i_dphy_variant sun50i_a100_mipi_dphy_variant = {
+	.tx_power_on	= sun50i_a100_mipi_dphy_tx_power_on,
+};
+
 static const struct of_device_id sun6i_dphy_of_table[] = {
 	{
 		.compatible	= "allwinner,sun6i-a31-mipi-dphy",
 		.data		= &sun6i_a31_mipi_dphy_variant,
 	},
+	{
+		.compatible	= "allwinner,sun50i-a100-mipi-dphy",
+		.data		= &sun50i_a100_mipi_dphy_variant,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
-- 
2.35.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH 8/8] phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY variant

[Samuel Holland]

A100 features an updated DPHY, which moves PLL control inside the DPHY
register space (previously the PLL was controlled from the CCU). It also
requires a modified analog power-on sequence. This "combo PHY" can also
be used as an LVDS PHY, but that is not yet supported by the driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 143 +++++++++++++++++++-
 1 file changed, 142 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 6a1993c434e8..9911c4a5c318 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -70,11 +70,19 @@
 
 #define SUN6I_DPHY_ANA0_REG		0x4c
 #define SUN6I_DPHY_ANA0_REG_PWS			BIT(31)
+#define SUN6I_DPHY_ANA0_REG_PWEND		BIT(30)
+#define SUN6I_DPHY_ANA0_REG_PWENC		BIT(29)
 #define SUN6I_DPHY_ANA0_REG_DMPC		BIT(28)
 #define SUN6I_DPHY_ANA0_REG_DMPD(n)		(((n) & 0xf) << 24)
+#define SUN6I_DPHY_ANA0_REG_SRXDT(n)		(((n) & 0xf) << 20)
+#define SUN6I_DPHY_ANA0_REG_SRXCK(n)		(((n) & 0xf) << 16)
+#define SUN6I_DPHY_ANA0_REG_SDIV2		BIT(15)
 #define SUN6I_DPHY_ANA0_REG_SLV(n)		(((n) & 7) << 12)
 #define SUN6I_DPHY_ANA0_REG_DEN(n)		(((n) & 0xf) << 8)
+#define SUN6I_DPHY_ANA0_REG_PLR(n)		(((n) & 0xf) << 4)
 #define SUN6I_DPHY_ANA0_REG_SFB(n)		(((n) & 3) << 2)
+#define SUN6I_DPHY_ANA0_REG_RSD			BIT(1)
+#define SUN6I_DPHY_ANA0_REG_SELSCK		BIT(0)
 
 #define SUN6I_DPHY_ANA1_REG		0x50
 #define SUN6I_DPHY_ANA1_REG_VTTMODE		BIT(31)
@@ -97,8 +105,13 @@
 #define SUN6I_DPHY_ANA3_EN_LDOR			BIT(18)
 
 #define SUN6I_DPHY_ANA4_REG		0x5c
+#define SUN6I_DPHY_ANA4_REG_EN_MIPI		BIT(31)
+#define SUN6I_DPHY_ANA4_REG_EN_COMTEST		BIT(30)
+#define SUN6I_DPHY_ANA4_REG_COMTEST(n)		(((n) & 3) << 28)
+#define SUN6I_DPHY_ANA4_REG_IB(n)		(((n) & 3) << 25)
 #define SUN6I_DPHY_ANA4_REG_DMPLVC		BIT(24)
 #define SUN6I_DPHY_ANA4_REG_DMPLVD(n)		(((n) & 0xf) << 20)
+#define SUN6I_DPHY_ANA4_REG_VTT_SET(n)		(((n) & 0x7) << 17)
 #define SUN6I_DPHY_ANA4_REG_CKDV(n)		(((n) & 0x1f) << 12)
 #define SUN6I_DPHY_ANA4_REG_TMSC(n)		(((n) & 3) << 10)
 #define SUN6I_DPHY_ANA4_REG_TMSD(n)		(((n) & 3) << 8)
@@ -109,6 +122,56 @@
 
 #define SUN6I_DPHY_DBG5_REG		0xf4
 
+#define SUN50I_DPHY_TX_SLEW_REG0	0xf8
+#define SUN50I_DPHY_TX_SLEW_REG1	0xfc
+#define SUN50I_DPHY_TX_SLEW_REG2	0x100
+
+#define SUN50I_DPHY_PLL_REG0		0x104
+#define SUN50I_DPHY_PLL_REG0_CP36_EN		BIT(23)
+#define SUN50I_DPHY_PLL_REG0_LDO_EN		BIT(22)
+#define SUN50I_DPHY_PLL_REG0_EN_LVS		BIT(21)
+#define SUN50I_DPHY_PLL_REG0_PLL_EN		BIT(20)
+#define SUN50I_DPHY_PLL_REG0_P(n)		(((n) & 0xf) << 16)
+#define SUN50I_DPHY_PLL_REG0_N(n)		(((n) & 0xff) << 8)
+#define SUN50I_DPHY_PLL_REG0_NDET		BIT(7)
+#define SUN50I_DPHY_PLL_REG0_TDIV		BIT(6)
+#define SUN50I_DPHY_PLL_REG0_M0(n)		(((n) & 3) << 4)
+#define SUN50I_DPHY_PLL_REG0_M1(n)		((n) & 0xf)
+
+#define SUN50I_DPHY_PLL_REG1		0x108
+#define SUN50I_DPHY_PLL_REG1_UNLOCK_MDSEL(n)	(((n) & 3) << 14)
+#define SUN50I_DPHY_PLL_REG1_LOCKMDSEL		BIT(13)
+#define SUN50I_DPHY_PLL_REG1_LOCKDET_EN		BIT(12)
+#define SUN50I_DPHY_PLL_REG1_VSETA(n)		(((n) & 0x7) << 9)
+#define SUN50I_DPHY_PLL_REG1_VSETD(n)		(((n) & 0x7) << 6)
+#define SUN50I_DPHY_PLL_REG1_LPF_SW		BIT(5)
+#define SUN50I_DPHY_PLL_REG1_ICP_SEL(n)		(((n) & 3) << 3)
+#define SUN50I_DPHY_PLL_REG1_ATEST_SEL(n)	(((n) & 3) << 1)
+#define SUN50I_DPHY_PLL_REG1_TEST_EN		BIT(0)
+
+#define SUN50I_DPHY_PLL_REG2		0x10c
+#define SUN50I_DPHY_PLL_REG2_SDM_EN		BIT(31)
+#define SUN50I_DPHY_PLL_REG2_FF_EN		BIT(30)
+#define SUN50I_DPHY_PLL_REG2_SS_EN		BIT(29)
+#define SUN50I_DPHY_PLL_REG2_SS_FRAC(n)		(((n) & 0x1ff) << 20)
+#define SUN50I_DPHY_PLL_REG2_SS_INT(n)		(((n) & 0xff) << 12)
+#define SUN50I_DPHY_PLL_REG2_FRAC(n)		((n) & 0xfff)
+
+#define SUN50I_COMBO_PHY_REG0		0x110
+#define SUN50I_COMBO_PHY_REG0_EN_TEST_COMBOLDO	BIT(5)
+#define SUN50I_COMBO_PHY_REG0_EN_TEST_0P8	BIT(4)
+#define SUN50I_COMBO_PHY_REG0_EN_MIPI		BIT(3)
+#define SUN50I_COMBO_PHY_REG0_EN_LVDS		BIT(2)
+#define SUN50I_COMBO_PHY_REG0_EN_COMBOLDO	BIT(1)
+#define SUN50I_COMBO_PHY_REG0_EN_CP		BIT(0)
+
+#define SUN50I_COMBO_PHY_REG1		0x114
+#define SUN50I_COMBO_PHY_REG2_REG_VREF1P6(n)	(((n) & 0x7) << 4)
+#define SUN50I_COMBO_PHY_REG2_REG_VREF0P8(n)	((n) & 0x7)
+
+#define SUN50I_COMBO_PHY_REG2		0x118
+#define SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(n)	((n) & 0xff)
+
 enum sun6i_dphy_direction {
 	SUN6I_DPHY_DIRECTION_TX,
 	SUN6I_DPHY_DIRECTION_RX,
@@ -196,6 +259,76 @@ static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
 	udelay(1);
 }
 
+static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
+{
+	unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
+	unsigned int div, n;
+
+	regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
+		     SUN6I_DPHY_ANA4_REG_IB(2) |
+		     SUN6I_DPHY_ANA4_REG_DMPLVD(4) |
+		     SUN6I_DPHY_ANA4_REG_VTT_SET(3) |
+		     SUN6I_DPHY_ANA4_REG_CKDV(3) |
+		     SUN6I_DPHY_ANA4_REG_TMSD(1) |
+		     SUN6I_DPHY_ANA4_REG_TMSC(1) |
+		     SUN6I_DPHY_ANA4_REG_TXPUSD(2) |
+		     SUN6I_DPHY_ANA4_REG_TXPUSC(3) |
+		     SUN6I_DPHY_ANA4_REG_TXDNSD(2) |
+		     SUN6I_DPHY_ANA4_REG_TXDNSC(3));
+
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
+			   SUN6I_DPHY_ANA2_EN_CK_CPU,
+			   SUN6I_DPHY_ANA2_EN_CK_CPU);
+
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
+			   SUN6I_DPHY_ANA2_REG_ENIB,
+			   SUN6I_DPHY_ANA2_REG_ENIB);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
+		     SUN6I_DPHY_ANA3_EN_LDOR |
+		     SUN6I_DPHY_ANA3_EN_LDOC |
+		     SUN6I_DPHY_ANA3_EN_LDOD);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
+		     SUN6I_DPHY_ANA0_REG_PLR(4) |
+		     SUN6I_DPHY_ANA0_REG_SFB(1));
+
+	regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0,
+		     SUN50I_COMBO_PHY_REG0_EN_CP);
+
+	/* Choose a divider to limit the VCO frequency to around 2 GHz. */
+	div = 16 >> order_base_2(DIV_ROUND_UP(mipi_symbol_rate, 264000000));
+	n = mipi_symbol_rate * div / 24000000;
+
+	regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG0,
+		     SUN50I_DPHY_PLL_REG0_CP36_EN |
+		     SUN50I_DPHY_PLL_REG0_LDO_EN |
+		     SUN50I_DPHY_PLL_REG0_EN_LVS |
+		     SUN50I_DPHY_PLL_REG0_PLL_EN |
+		     SUN50I_DPHY_PLL_REG0_NDET |
+		     SUN50I_DPHY_PLL_REG0_P((div - 1) % 8) |
+		     SUN50I_DPHY_PLL_REG0_N(n) |
+		     SUN50I_DPHY_PLL_REG0_M0((div - 1) / 8) |
+		     SUN50I_DPHY_PLL_REG0_M1(2));
+
+	/* Disable sigma-delta modulation. */
+	regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0);
+
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
+			   SUN6I_DPHY_ANA4_REG_EN_MIPI,
+			   SUN6I_DPHY_ANA4_REG_EN_MIPI);
+
+	regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
+			   SUN50I_COMBO_PHY_REG0_EN_MIPI |
+			   SUN50I_COMBO_PHY_REG0_EN_COMBOLDO,
+			   SUN50I_COMBO_PHY_REG0_EN_MIPI |
+			   SUN50I_COMBO_PHY_REG0_EN_COMBOLDO);
+
+	regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG2,
+		     SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(20));
+	udelay(1);
+}
+
 static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
 {
 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
@@ -408,7 +541,7 @@ static const struct regmap_config sun6i_dphy_regmap_config = {
 	.reg_bits	= 32,
 	.val_bits	= 32,
 	.reg_stride	= 4,
-	.max_register	= SUN6I_DPHY_DBG5_REG,
+	.max_register	= SUN50I_COMBO_PHY_REG2,
 	.name		= "mipi-dphy",
 };
 
@@ -483,11 +616,19 @@ static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
 	.supports_rx	= true,
 };
 
+static const struct sun6i_dphy_variant sun50i_a100_mipi_dphy_variant = {
+	.tx_power_on	= sun50i_a100_mipi_dphy_tx_power_on,
+};
+
 static const struct of_device_id sun6i_dphy_of_table[] = {
 	{
 		.compatible	= "allwinner,sun6i-a31-mipi-dphy",
 		.data		= &sun6i_a31_mipi_dphy_variant,
 	},
+	{
+		.compatible	= "allwinner,sun50i-a100-mipi-dphy",
+		.data		= &sun50i_a100_mipi_dphy_variant,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
-- 
2.35.1


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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Krzysztof Kozlowski]

On 12/08/2022 10:55, Samuel Holland wrote:
> The sun6i DPHY can generate several interrupts, mostly for reporting
> error conditions, but also for detecting BTA and UPLS sequences.
> Document this capability in order to accurately describe the hardware.
> 
> The DPHY has no interrupt number provided in the vendor documentation
> because its interrupt line is shared with the DSI controller.
> 
> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")

I don't understand what is being fixed in that commit. That commit did
not have interrupts in D-PHY, so what was broken by it?

The Fixes tag annotates the commit which introduced a bug.

Best regards,
Krzysztof

Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Krzysztof Kozlowski]

On 12/08/2022 10:55, Samuel Holland wrote:
> The sun6i DPHY can generate several interrupts, mostly for reporting
> error conditions, but also for detecting BTA and UPLS sequences.
> Document this capability in order to accurately describe the hardware.
> 
> The DPHY has no interrupt number provided in the vendor documentation
> because its interrupt line is shared with the DSI controller.
> 
> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")

I don't understand what is being fixed in that commit. That commit did
not have interrupts in D-PHY, so what was broken by it?

The Fixes tag annotates the commit which introduced a bug.

Best regards,
Krzysztof

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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Krzysztof Kozlowski]

On 12/08/2022 10:55, Samuel Holland wrote:
> The sun6i DPHY can generate several interrupts, mostly for reporting
> error conditions, but also for detecting BTA and UPLS sequences.
> Document this capability in order to accurately describe the hardware.
> 
> The DPHY has no interrupt number provided in the vendor documentation
> because its interrupt line is shared with the DSI controller.
> 
> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")

I don't understand what is being fixed in that commit. That commit did
not have interrupts in D-PHY, so what was broken by it?

The Fixes tag annotates the commit which introduced a bug.

Best regards,
Krzysztof

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Re: [PATCH 4/8] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant

[Krzysztof Kozlowski]

On 12/08/2022 10:55, Samuel Holland wrote:
> A100 features an updated DPHY, which moves PLL control inside the DPHY
> register space. (Previously PLL-MIPI was controlled from the CCU. This
> does not affect the "clocks" property because the link between PLL-MIPI
> and the DPHY was never represented in the devicetree.) It also requires

Misplaced '.'.

With above:

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH 4/8] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant

[Krzysztof Kozlowski]

On 12/08/2022 10:55, Samuel Holland wrote:
> A100 features an updated DPHY, which moves PLL control inside the DPHY
> register space. (Previously PLL-MIPI was controlled from the CCU. This
> does not affect the "clocks" property because the link between PLL-MIPI
> and the DPHY was never represented in the devicetree.) It also requires

Misplaced '.'.

With above:

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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Re: [PATCH 4/8] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant

[Krzysztof Kozlowski]

On 12/08/2022 10:55, Samuel Holland wrote:
> A100 features an updated DPHY, which moves PLL control inside the DPHY
> register space. (Previously PLL-MIPI was controlled from the CCU. This
> does not affect the "clocks" property because the link between PLL-MIPI
> and the DPHY was never represented in the devicetree.) It also requires

Misplaced '.'.

With above:

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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Re: [PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last

[Paul Kocialkowski]

[-- Attachment #1: Type: text/plain, Size: 1943 bytes --]

Hi Samuel,

On Fri 12 Aug 22, 02:56, Samuel Holland wrote:
> The A100 variant of the DPHY requires configuring the analog registers
> before setting the global enable bit. Since this order also works on the
> other variants, always use it, to minimize the differences between them.

Did you get a chance to actually test this with either DSI/CSI-2 hardware?
I vaguely remember that the order mattered. Do you have an idea of what the
Allwinner BSP does too?

Otherwise I could give it a try, at least with my MIPI CSI-2 setup
that uses the driver.

Cheers,

Pau

> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> index 625c6e1e9990..9698d68d0db7 100644
> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> @@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
>  
> -	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> -		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> -		     SUN6I_DPHY_GCTL_EN);
> -
>  	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
>  		     SUN6I_DPHY_ANA0_REG_PWS |
>  		     SUN6I_DPHY_ANA0_REG_DMPC |
> @@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
>  
> +	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> +		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> +		     SUN6I_DPHY_GCTL_EN);
> +
>  	return 0;
>  }
>  
> -- 
> 2.35.1
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last

[Paul Kocialkowski]

[-- Attachment #1.1: Type: text/plain, Size: 1943 bytes --]

Hi Samuel,

On Fri 12 Aug 22, 02:56, Samuel Holland wrote:
> The A100 variant of the DPHY requires configuring the analog registers
> before setting the global enable bit. Since this order also works on the
> other variants, always use it, to minimize the differences between them.

Did you get a chance to actually test this with either DSI/CSI-2 hardware?
I vaguely remember that the order mattered. Do you have an idea of what the
Allwinner BSP does too?

Otherwise I could give it a try, at least with my MIPI CSI-2 setup
that uses the driver.

Cheers,

Pau

> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> index 625c6e1e9990..9698d68d0db7 100644
> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> @@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
>  
> -	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> -		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> -		     SUN6I_DPHY_GCTL_EN);
> -
>  	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
>  		     SUN6I_DPHY_ANA0_REG_PWS |
>  		     SUN6I_DPHY_ANA0_REG_DMPC |
> @@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
>  
> +	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> +		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> +		     SUN6I_DPHY_GCTL_EN);
> +
>  	return 0;
>  }
>  
> -- 
> 2.35.1
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last

[Paul Kocialkowski]

[-- Attachment #1.1: Type: text/plain, Size: 1943 bytes --]

Hi Samuel,

On Fri 12 Aug 22, 02:56, Samuel Holland wrote:
> The A100 variant of the DPHY requires configuring the analog registers
> before setting the global enable bit. Since this order also works on the
> other variants, always use it, to minimize the differences between them.

Did you get a chance to actually test this with either DSI/CSI-2 hardware?
I vaguely remember that the order mattered. Do you have an idea of what the
Allwinner BSP does too?

Otherwise I could give it a try, at least with my MIPI CSI-2 setup
that uses the driver.

Cheers,

Pau

> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> index 625c6e1e9990..9698d68d0db7 100644
> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> @@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
>  
> -	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> -		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> -		     SUN6I_DPHY_GCTL_EN);
> -
>  	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
>  		     SUN6I_DPHY_ANA0_REG_PWS |
>  		     SUN6I_DPHY_ANA0_REG_DMPC |
> @@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
>  
> +	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> +		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> +		     SUN6I_DPHY_GCTL_EN);
> +
>  	return 0;
>  }
>  
> -- 
> 2.35.1
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Paul Kocialkowski]

[-- Attachment #1: Type: text/plain, Size: 2026 bytes --]

Hi Samuel,

On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
> The sun6i DPHY can generate several interrupts, mostly for reporting
> error conditions, but also for detecting BTA and UPLS sequences.
> Document this capability in order to accurately describe the hardware.
> 
> The DPHY has no interrupt number provided in the vendor documentation
> because its interrupt line is shared with the DSI controller.

Interesting! I do see DPHY_INT_EN*/PD* in the Allwinner BSP's
drivers/media/video/sunxi-vfe/mipi_csi/dphy/dphy_reg_i.h

Maybe it would be useful to import the fields in the driver so that the
next person who'll try to debug DSI can use them directly?

You might also want to submit a patch as [PATCH NOT FOR MERGE] that
adds an interrupt routine and some useful debugging.

Do you think this is also available without a DSI controller?
I could just give it a try on V3/A83t here and find out :)

Cheers,

Paul

> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> index 22636c9fdab8..cf49bd99b3e2 100644
> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> @@ -24,6 +24,9 @@ properties:
>    reg:
>      maxItems: 1
>  
> +  interrupts:
> +    maxItems: 1
> +
>    clocks:
>      items:
>        - description: Bus Clock
> @@ -53,6 +56,7 @@ required:
>    - "#phy-cells"
>    - compatible
>    - reg
> +  - interrupts
>    - clocks
>    - clock-names
>    - resets
> -- 
> 2.35.1
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Paul Kocialkowski]

[-- Attachment #1.1: Type: text/plain, Size: 2026 bytes --]

Hi Samuel,

On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
> The sun6i DPHY can generate several interrupts, mostly for reporting
> error conditions, but also for detecting BTA and UPLS sequences.
> Document this capability in order to accurately describe the hardware.
> 
> The DPHY has no interrupt number provided in the vendor documentation
> because its interrupt line is shared with the DSI controller.

Interesting! I do see DPHY_INT_EN*/PD* in the Allwinner BSP's
drivers/media/video/sunxi-vfe/mipi_csi/dphy/dphy_reg_i.h

Maybe it would be useful to import the fields in the driver so that the
next person who'll try to debug DSI can use them directly?

You might also want to submit a patch as [PATCH NOT FOR MERGE] that
adds an interrupt routine and some useful debugging.

Do you think this is also available without a DSI controller?
I could just give it a try on V3/A83t here and find out :)

Cheers,

Paul

> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> index 22636c9fdab8..cf49bd99b3e2 100644
> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> @@ -24,6 +24,9 @@ properties:
>    reg:
>      maxItems: 1
>  
> +  interrupts:
> +    maxItems: 1
> +
>    clocks:
>      items:
>        - description: Bus Clock
> @@ -53,6 +56,7 @@ required:
>    - "#phy-cells"
>    - compatible
>    - reg
> +  - interrupts
>    - clocks
>    - clock-names
>    - resets
> -- 
> 2.35.1
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Paul Kocialkowski]

[-- Attachment #1.1: Type: text/plain, Size: 2026 bytes --]

Hi Samuel,

On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
> The sun6i DPHY can generate several interrupts, mostly for reporting
> error conditions, but also for detecting BTA and UPLS sequences.
> Document this capability in order to accurately describe the hardware.
> 
> The DPHY has no interrupt number provided in the vendor documentation
> because its interrupt line is shared with the DSI controller.

Interesting! I do see DPHY_INT_EN*/PD* in the Allwinner BSP's
drivers/media/video/sunxi-vfe/mipi_csi/dphy/dphy_reg_i.h

Maybe it would be useful to import the fields in the driver so that the
next person who'll try to debug DSI can use them directly?

You might also want to submit a patch as [PATCH NOT FOR MERGE] that
adds an interrupt routine and some useful debugging.

Do you think this is also available without a DSI controller?
I could just give it a try on V3/A83t here and find out :)

Cheers,

Paul

> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> index 22636c9fdab8..cf49bd99b3e2 100644
> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> @@ -24,6 +24,9 @@ properties:
>    reg:
>      maxItems: 1
>  
> +  interrupts:
> +    maxItems: 1
> +
>    clocks:
>      items:
>        - description: Bus Clock
> @@ -53,6 +56,7 @@ required:
>    - "#phy-cells"
>    - compatible
>    - reg
> +  - interrupts
>    - clocks
>    - clock-names
>    - resets
> -- 
> 2.35.1
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Rob Herring]

On Fri, 12 Aug 2022 02:55:56 -0500, Samuel Holland wrote:
> The sun6i DPHY can generate several interrupts, mostly for reporting
> error conditions, but also for detecting BTA and UPLS sequences.
> Document this capability in order to accurately describe the hardware.
> 
> The DPHY has no interrupt number provided in the vendor documentation
> because its interrupt line is shared with the DSI controller.
> 
> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>  1 file changed, 4 insertions(+)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.example.dtb: d-phy@1ca1000: 'oneOf' conditional failed, one must be fixed:
	'interrupts' is a required property
	'interrupts-extended' is a required property
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Rob Herring]

On Fri, 12 Aug 2022 02:55:56 -0500, Samuel Holland wrote:
> The sun6i DPHY can generate several interrupts, mostly for reporting
> error conditions, but also for detecting BTA and UPLS sequences.
> Document this capability in order to accurately describe the hardware.
> 
> The DPHY has no interrupt number provided in the vendor documentation
> because its interrupt line is shared with the DSI controller.
> 
> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>  1 file changed, 4 insertions(+)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.example.dtb: d-phy@1ca1000: 'oneOf' conditional failed, one must be fixed:
	'interrupts' is a required property
	'interrupts-extended' is a required property
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Rob Herring]

On Fri, 12 Aug 2022 02:55:56 -0500, Samuel Holland wrote:
> The sun6i DPHY can generate several interrupts, mostly for reporting
> error conditions, but also for detecting BTA and UPLS sequences.
> Document this capability in order to accurately describe the hardware.
> 
> The DPHY has no interrupt number provided in the vendor documentation
> because its interrupt line is shared with the DSI controller.
> 
> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>  1 file changed, 4 insertions(+)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.example.dtb: d-phy@1ca1000: 'oneOf' conditional failed, one must be fixed:
	'interrupts' is a required property
	'interrupts-extended' is a required property
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Samuel Holland]

On 8/12/22 5:45 AM, Krzysztof Kozlowski wrote:
> On 12/08/2022 10:55, Samuel Holland wrote:
>> The sun6i DPHY can generate several interrupts, mostly for reporting
>> error conditions, but also for detecting BTA and UPLS sequences.
>> Document this capability in order to accurately describe the hardware.
>>
>> The DPHY has no interrupt number provided in the vendor documentation
>> because its interrupt line is shared with the DSI controller.
>>
>> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> 
> I don't understand what is being fixed in that commit. That commit did
> not have interrupts in D-PHY, so what was broken by it?
> 
> The Fixes tag annotates the commit which introduced a bug.

The binding had a bug because it did not accurately describe the hardware. If
you don't think this warrants a Fixes tag, I can remove it. Or are you
suggesting that the Fixes tag should instead reference the commit adding the
original .txt binding?

Regards,
Samuel

Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Samuel Holland]

On 8/12/22 5:45 AM, Krzysztof Kozlowski wrote:
> On 12/08/2022 10:55, Samuel Holland wrote:
>> The sun6i DPHY can generate several interrupts, mostly for reporting
>> error conditions, but also for detecting BTA and UPLS sequences.
>> Document this capability in order to accurately describe the hardware.
>>
>> The DPHY has no interrupt number provided in the vendor documentation
>> because its interrupt line is shared with the DSI controller.
>>
>> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> 
> I don't understand what is being fixed in that commit. That commit did
> not have interrupts in D-PHY, so what was broken by it?
> 
> The Fixes tag annotates the commit which introduced a bug.

The binding had a bug because it did not accurately describe the hardware. If
you don't think this warrants a Fixes tag, I can remove it. Or are you
suggesting that the Fixes tag should instead reference the commit adding the
original .txt binding?

Regards,
Samuel

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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Samuel Holland]

On 8/12/22 5:45 AM, Krzysztof Kozlowski wrote:
> On 12/08/2022 10:55, Samuel Holland wrote:
>> The sun6i DPHY can generate several interrupts, mostly for reporting
>> error conditions, but also for detecting BTA and UPLS sequences.
>> Document this capability in order to accurately describe the hardware.
>>
>> The DPHY has no interrupt number provided in the vendor documentation
>> because its interrupt line is shared with the DSI controller.
>>
>> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> 
> I don't understand what is being fixed in that commit. That commit did
> not have interrupts in D-PHY, so what was broken by it?
> 
> The Fixes tag annotates the commit which introduced a bug.

The binding had a bug because it did not accurately describe the hardware. If
you don't think this warrants a Fixes tag, I can remove it. Or are you
suggesting that the Fixes tag should instead reference the commit adding the
original .txt binding?

Regards,
Samuel

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Re: [PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last

[Samuel Holland]

Hi Paul,

On 8/12/22 7:03 AM, Paul Kocialkowski wrote:
> On Fri 12 Aug 22, 02:56, Samuel Holland wrote:
>> The A100 variant of the DPHY requires configuring the analog registers
>> before setting the global enable bit. Since this order also works on the
>> other variants, always use it, to minimize the differences between them.
> 
> Did you get a chance to actually test this with either DSI/CSI-2 hardware?

I have tested DSI output with the Clockwork DevTerm (D1 SoC) and Pine64
PinePhone (A64 SoC). I do not have any MIPI CSI hardware to test with.

> I vaguely remember that the order mattered. Do you have an idea of what the
> Allwinner BSP does too?

The Allwinner BSP makes the same change as this commit in its "lowlevel_v2x"
copy of the code, which is used for R40 and T7 (original DPHY) and A100 and D1
(updated DPHY). It does not make the change in "lowlevel_sun50iw1" (A64 SoC,
original DPHY), but I tested A64 with this change, and it works fine.

> Otherwise I could give it a try, at least with my MIPI CSI-2 setup
> that uses the driver.

This commit only changes sun6i_dphy_tx_power_on(). The code for RX is unchanged
-- in fact, it already sets SUN6I_DPHY_GCTL_REG last.

Regards,
Samuel

>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>> ---
>>
>>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
>> index 625c6e1e9990..9698d68d0db7 100644
>> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
>> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
>> @@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
>>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
>>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
>>  
>> -	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
>> -		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
>> -		     SUN6I_DPHY_GCTL_EN);
>> -
>>  	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
>>  		     SUN6I_DPHY_ANA0_REG_PWS |
>>  		     SUN6I_DPHY_ANA0_REG_DMPC |
>> @@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
>>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
>>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
>>  
>> +	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
>> +		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
>> +		     SUN6I_DPHY_GCTL_EN);
>> +
>>  	return 0;
>>  }
>>  
>> -- 
>> 2.35.1
>>
> 

Re: [PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last

[Samuel Holland]

Hi Paul,

On 8/12/22 7:03 AM, Paul Kocialkowski wrote:
> On Fri 12 Aug 22, 02:56, Samuel Holland wrote:
>> The A100 variant of the DPHY requires configuring the analog registers
>> before setting the global enable bit. Since this order also works on the
>> other variants, always use it, to minimize the differences between them.
> 
> Did you get a chance to actually test this with either DSI/CSI-2 hardware?

I have tested DSI output with the Clockwork DevTerm (D1 SoC) and Pine64
PinePhone (A64 SoC). I do not have any MIPI CSI hardware to test with.

> I vaguely remember that the order mattered. Do you have an idea of what the
> Allwinner BSP does too?

The Allwinner BSP makes the same change as this commit in its "lowlevel_v2x"
copy of the code, which is used for R40 and T7 (original DPHY) and A100 and D1
(updated DPHY). It does not make the change in "lowlevel_sun50iw1" (A64 SoC,
original DPHY), but I tested A64 with this change, and it works fine.

> Otherwise I could give it a try, at least with my MIPI CSI-2 setup
> that uses the driver.

This commit only changes sun6i_dphy_tx_power_on(). The code for RX is unchanged
-- in fact, it already sets SUN6I_DPHY_GCTL_REG last.

Regards,
Samuel

>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>> ---
>>
>>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
>> index 625c6e1e9990..9698d68d0db7 100644
>> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
>> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
>> @@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
>>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
>>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
>>  
>> -	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
>> -		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
>> -		     SUN6I_DPHY_GCTL_EN);
>> -
>>  	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
>>  		     SUN6I_DPHY_ANA0_REG_PWS |
>>  		     SUN6I_DPHY_ANA0_REG_DMPC |
>> @@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
>>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
>>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
>>  
>> +	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
>> +		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
>> +		     SUN6I_DPHY_GCTL_EN);
>> +
>>  	return 0;
>>  }
>>  
>> -- 
>> 2.35.1
>>
> 


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Re: [PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last

[Samuel Holland]

Hi Paul,

On 8/12/22 7:03 AM, Paul Kocialkowski wrote:
> On Fri 12 Aug 22, 02:56, Samuel Holland wrote:
>> The A100 variant of the DPHY requires configuring the analog registers
>> before setting the global enable bit. Since this order also works on the
>> other variants, always use it, to minimize the differences between them.
> 
> Did you get a chance to actually test this with either DSI/CSI-2 hardware?

I have tested DSI output with the Clockwork DevTerm (D1 SoC) and Pine64
PinePhone (A64 SoC). I do not have any MIPI CSI hardware to test with.

> I vaguely remember that the order mattered. Do you have an idea of what the
> Allwinner BSP does too?

The Allwinner BSP makes the same change as this commit in its "lowlevel_v2x"
copy of the code, which is used for R40 and T7 (original DPHY) and A100 and D1
(updated DPHY). It does not make the change in "lowlevel_sun50iw1" (A64 SoC,
original DPHY), but I tested A64 with this change, and it works fine.

> Otherwise I could give it a try, at least with my MIPI CSI-2 setup
> that uses the driver.

This commit only changes sun6i_dphy_tx_power_on(). The code for RX is unchanged
-- in fact, it already sets SUN6I_DPHY_GCTL_REG last.

Regards,
Samuel

>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>> ---
>>
>>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
>> index 625c6e1e9990..9698d68d0db7 100644
>> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
>> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
>> @@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
>>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
>>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
>>  
>> -	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
>> -		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
>> -		     SUN6I_DPHY_GCTL_EN);
>> -
>>  	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
>>  		     SUN6I_DPHY_ANA0_REG_PWS |
>>  		     SUN6I_DPHY_ANA0_REG_DMPC |
>> @@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
>>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
>>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
>>  
>> +	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
>> +		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
>> +		     SUN6I_DPHY_GCTL_EN);
>> +
>>  	return 0;
>>  }
>>  
>> -- 
>> 2.35.1
>>
> 


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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Samuel Holland]

Hi Paul,

On 8/12/22 7:22 AM, Paul Kocialkowski wrote:
> On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
>> The sun6i DPHY can generate several interrupts, mostly for reporting
>> error conditions, but also for detecting BTA and UPLS sequences.
>> Document this capability in order to accurately describe the hardware.
>>
>> The DPHY has no interrupt number provided in the vendor documentation
>> because its interrupt line is shared with the DSI controller.
> 
> Interesting! I do see DPHY_INT_EN*/PD* in the Allwinner BSP's
> drivers/media/video/sunxi-vfe/mipi_csi/dphy/dphy_reg_i.h

You can also find some bit of documentation in the T7 User Manual.

> Maybe it would be useful to import the fields in the driver so that the
> next person who'll try to debug DSI can use them directly?
> 
> You might also want to submit a patch as [PATCH NOT FOR MERGE] that
> adds an interrupt routine and some useful debugging.

I think this would be more interesting to someone who knew more about MIPI
CSI/DSI and understood what those errors meant. :)

I'm mostly concerned with bringing up the D1 SoC at the moment.

> Do you think this is also available without a DSI controller?
> I could just give it a try on V3/A83t here and find out :)

I would assume so. It could possibly be shared with the MIPI CSI interrupt (SPI
90) or keep its position at SPI 89.

Regards,
Samuel

>> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>> ---
>>
>>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> index 22636c9fdab8..cf49bd99b3e2 100644
>> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> @@ -24,6 +24,9 @@ properties:
>>    reg:
>>      maxItems: 1
>>  
>> +  interrupts:
>> +    maxItems: 1
>> +
>>    clocks:
>>      items:
>>        - description: Bus Clock
>> @@ -53,6 +56,7 @@ required:
>>    - "#phy-cells"
>>    - compatible
>>    - reg
>> +  - interrupts
>>    - clocks
>>    - clock-names
>>    - resets
>> -- 
>> 2.35.1
>>
> 

Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Samuel Holland]

Hi Paul,

On 8/12/22 7:22 AM, Paul Kocialkowski wrote:
> On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
>> The sun6i DPHY can generate several interrupts, mostly for reporting
>> error conditions, but also for detecting BTA and UPLS sequences.
>> Document this capability in order to accurately describe the hardware.
>>
>> The DPHY has no interrupt number provided in the vendor documentation
>> because its interrupt line is shared with the DSI controller.
> 
> Interesting! I do see DPHY_INT_EN*/PD* in the Allwinner BSP's
> drivers/media/video/sunxi-vfe/mipi_csi/dphy/dphy_reg_i.h

You can also find some bit of documentation in the T7 User Manual.

> Maybe it would be useful to import the fields in the driver so that the
> next person who'll try to debug DSI can use them directly?
> 
> You might also want to submit a patch as [PATCH NOT FOR MERGE] that
> adds an interrupt routine and some useful debugging.

I think this would be more interesting to someone who knew more about MIPI
CSI/DSI and understood what those errors meant. :)

I'm mostly concerned with bringing up the D1 SoC at the moment.

> Do you think this is also available without a DSI controller?
> I could just give it a try on V3/A83t here and find out :)

I would assume so. It could possibly be shared with the MIPI CSI interrupt (SPI
90) or keep its position at SPI 89.

Regards,
Samuel

>> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>> ---
>>
>>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> index 22636c9fdab8..cf49bd99b3e2 100644
>> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> @@ -24,6 +24,9 @@ properties:
>>    reg:
>>      maxItems: 1
>>  
>> +  interrupts:
>> +    maxItems: 1
>> +
>>    clocks:
>>      items:
>>        - description: Bus Clock
>> @@ -53,6 +56,7 @@ required:
>>    - "#phy-cells"
>>    - compatible
>>    - reg
>> +  - interrupts
>>    - clocks
>>    - clock-names
>>    - resets
>> -- 
>> 2.35.1
>>
> 


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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Samuel Holland]

Hi Paul,

On 8/12/22 7:22 AM, Paul Kocialkowski wrote:
> On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
>> The sun6i DPHY can generate several interrupts, mostly for reporting
>> error conditions, but also for detecting BTA and UPLS sequences.
>> Document this capability in order to accurately describe the hardware.
>>
>> The DPHY has no interrupt number provided in the vendor documentation
>> because its interrupt line is shared with the DSI controller.
> 
> Interesting! I do see DPHY_INT_EN*/PD* in the Allwinner BSP's
> drivers/media/video/sunxi-vfe/mipi_csi/dphy/dphy_reg_i.h

You can also find some bit of documentation in the T7 User Manual.

> Maybe it would be useful to import the fields in the driver so that the
> next person who'll try to debug DSI can use them directly?
> 
> You might also want to submit a patch as [PATCH NOT FOR MERGE] that
> adds an interrupt routine and some useful debugging.

I think this would be more interesting to someone who knew more about MIPI
CSI/DSI and understood what those errors meant. :)

I'm mostly concerned with bringing up the D1 SoC at the moment.

> Do you think this is also available without a DSI controller?
> I could just give it a try on V3/A83t here and find out :)

I would assume so. It could possibly be shared with the MIPI CSI interrupt (SPI
90) or keep its position at SPI 89.

Regards,
Samuel

>> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>> ---
>>
>>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> index 22636c9fdab8..cf49bd99b3e2 100644
>> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> @@ -24,6 +24,9 @@ properties:
>>    reg:
>>      maxItems: 1
>>  
>> +  interrupts:
>> +    maxItems: 1
>> +
>>    clocks:
>>      items:
>>        - description: Bus Clock
>> @@ -53,6 +56,7 @@ required:
>>    - "#phy-cells"
>>    - compatible
>>    - reg
>> +  - interrupts
>>    - clocks
>>    - clock-names
>>    - resets
>> -- 
>> 2.35.1
>>
> 


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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Krzysztof Kozlowski]

On 13/08/2022 01:19, Samuel Holland wrote:
> On 8/12/22 5:45 AM, Krzysztof Kozlowski wrote:
>> On 12/08/2022 10:55, Samuel Holland wrote:
>>> The sun6i DPHY can generate several interrupts, mostly for reporting
>>> error conditions, but also for detecting BTA and UPLS sequences.
>>> Document this capability in order to accurately describe the hardware.
>>>
>>> The DPHY has no interrupt number provided in the vendor documentation
>>> because its interrupt line is shared with the DSI controller.
>>>
>>> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
>>
>> I don't understand what is being fixed in that commit. That commit did
>> not have interrupts in D-PHY, so what was broken by it?
>>
>> The Fixes tag annotates the commit which introduced a bug.
> 
> The binding had a bug because it did not accurately describe the hardware. If
> you don't think this warrants a Fixes tag, I can remove it. Or are you
> suggesting that the Fixes tag should instead reference the commit adding the
> original .txt binding?

Yes, the latter. If original binding were not complete (although just
"incompleteness" is not really a bug, unless it is something
serious/obvious etc), then TXT commit should be the fixed one.

The backports of course will not go that deep, but Fixes tag is used
also for statistics which kernel release actually brought the bug.
Therefore adjusting Fixes just for sake of backporting is not good -
messes up with statistics.


Best regards,
Krzysztof

Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Krzysztof Kozlowski]

On 13/08/2022 01:19, Samuel Holland wrote:
> On 8/12/22 5:45 AM, Krzysztof Kozlowski wrote:
>> On 12/08/2022 10:55, Samuel Holland wrote:
>>> The sun6i DPHY can generate several interrupts, mostly for reporting
>>> error conditions, but also for detecting BTA and UPLS sequences.
>>> Document this capability in order to accurately describe the hardware.
>>>
>>> The DPHY has no interrupt number provided in the vendor documentation
>>> because its interrupt line is shared with the DSI controller.
>>>
>>> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
>>
>> I don't understand what is being fixed in that commit. That commit did
>> not have interrupts in D-PHY, so what was broken by it?
>>
>> The Fixes tag annotates the commit which introduced a bug.
> 
> The binding had a bug because it did not accurately describe the hardware. If
> you don't think this warrants a Fixes tag, I can remove it. Or are you
> suggesting that the Fixes tag should instead reference the commit adding the
> original .txt binding?

Yes, the latter. If original binding were not complete (although just
"incompleteness" is not really a bug, unless it is something
serious/obvious etc), then TXT commit should be the fixed one.

The backports of course will not go that deep, but Fixes tag is used
also for statistics which kernel release actually brought the bug.
Therefore adjusting Fixes just for sake of backporting is not good -
messes up with statistics.


Best regards,
Krzysztof

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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Krzysztof Kozlowski]

On 13/08/2022 01:19, Samuel Holland wrote:
> On 8/12/22 5:45 AM, Krzysztof Kozlowski wrote:
>> On 12/08/2022 10:55, Samuel Holland wrote:
>>> The sun6i DPHY can generate several interrupts, mostly for reporting
>>> error conditions, but also for detecting BTA and UPLS sequences.
>>> Document this capability in order to accurately describe the hardware.
>>>
>>> The DPHY has no interrupt number provided in the vendor documentation
>>> because its interrupt line is shared with the DSI controller.
>>>
>>> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
>>
>> I don't understand what is being fixed in that commit. That commit did
>> not have interrupts in D-PHY, so what was broken by it?
>>
>> The Fixes tag annotates the commit which introduced a bug.
> 
> The binding had a bug because it did not accurately describe the hardware. If
> you don't think this warrants a Fixes tag, I can remove it. Or are you
> suggesting that the Fixes tag should instead reference the commit adding the
> original .txt binding?

Yes, the latter. If original binding were not complete (although just
"incompleteness" is not really a bug, unless it is something
serious/obvious etc), then TXT commit should be the fixed one.

The backports of course will not go that deep, but Fixes tag is used
also for statistics which kernel release actually brought the bug.
Therefore adjusting Fixes just for sake of backporting is not good -
messes up with statistics.


Best regards,
Krzysztof

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Re: [PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last

[Paul Kocialkowski]

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Hi Samuel,

On Fri 12 Aug 22, 17:31, Samuel Holland wrote:
> Hi Paul,
> 
> On 8/12/22 7:03 AM, Paul Kocialkowski wrote:
> > On Fri 12 Aug 22, 02:56, Samuel Holland wrote:
> >> The A100 variant of the DPHY requires configuring the analog registers
> >> before setting the global enable bit. Since this order also works on the
> >> other variants, always use it, to minimize the differences between them.
> > 
> > Did you get a chance to actually test this with either DSI/CSI-2 hardware?
> 
> I have tested DSI output with the Clockwork DevTerm (D1 SoC) and Pine64
> PinePhone (A64 SoC). I do not have any MIPI CSI hardware to test with.

Sounds good to me then!

> > I vaguely remember that the order mattered. Do you have an idea of what the
> > Allwinner BSP does too?
> 
> The Allwinner BSP makes the same change as this commit in its "lowlevel_v2x"
> copy of the code, which is used for R40 and T7 (original DPHY) and A100 and D1
> (updated DPHY). It does not make the change in "lowlevel_sun50iw1" (A64 SoC,
> original DPHY), but I tested A64 with this change, and it works fine.

Great, thanks for details.

> > Otherwise I could give it a try, at least with my MIPI CSI-2 setup
> > that uses the driver.
> 
> This commit only changes sun6i_dphy_tx_power_on(). The code for RX is unchanged
> -- in fact, it already sets SUN6I_DPHY_GCTL_REG last.

Ah yes you're right, actually I remember being tempted to change this too when
adding the rx path, but didn't have hardware to easily test.

Thanks for the details, this is:

Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>

Cheers,

Paul

> Regards,
> Samuel
> 
> >> Signed-off-by: Samuel Holland <samuel@sholland.org>
> >> ---
> >>
> >>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
> >>  1 file changed, 4 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> >> index 625c6e1e9990..9698d68d0db7 100644
> >> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> >> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> >> @@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
> >>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
> >>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
> >>  
> >> -	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> >> -		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> >> -		     SUN6I_DPHY_GCTL_EN);
> >> -
> >>  	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
> >>  		     SUN6I_DPHY_ANA0_REG_PWS |
> >>  		     SUN6I_DPHY_ANA0_REG_DMPC |
> >> @@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
> >>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
> >>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
> >>  
> >> +	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> >> +		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> >> +		     SUN6I_DPHY_GCTL_EN);
> >> +
> >>  	return 0;
> >>  }
> >>  
> >> -- 
> >> 2.35.1
> >>
> > 
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last

[Paul Kocialkowski]

[-- Attachment #1.1: Type: text/plain, Size: 3152 bytes --]

Hi Samuel,

On Fri 12 Aug 22, 17:31, Samuel Holland wrote:
> Hi Paul,
> 
> On 8/12/22 7:03 AM, Paul Kocialkowski wrote:
> > On Fri 12 Aug 22, 02:56, Samuel Holland wrote:
> >> The A100 variant of the DPHY requires configuring the analog registers
> >> before setting the global enable bit. Since this order also works on the
> >> other variants, always use it, to minimize the differences between them.
> > 
> > Did you get a chance to actually test this with either DSI/CSI-2 hardware?
> 
> I have tested DSI output with the Clockwork DevTerm (D1 SoC) and Pine64
> PinePhone (A64 SoC). I do not have any MIPI CSI hardware to test with.

Sounds good to me then!

> > I vaguely remember that the order mattered. Do you have an idea of what the
> > Allwinner BSP does too?
> 
> The Allwinner BSP makes the same change as this commit in its "lowlevel_v2x"
> copy of the code, which is used for R40 and T7 (original DPHY) and A100 and D1
> (updated DPHY). It does not make the change in "lowlevel_sun50iw1" (A64 SoC,
> original DPHY), but I tested A64 with this change, and it works fine.

Great, thanks for details.

> > Otherwise I could give it a try, at least with my MIPI CSI-2 setup
> > that uses the driver.
> 
> This commit only changes sun6i_dphy_tx_power_on(). The code for RX is unchanged
> -- in fact, it already sets SUN6I_DPHY_GCTL_REG last.

Ah yes you're right, actually I remember being tempted to change this too when
adding the rx path, but didn't have hardware to easily test.

Thanks for the details, this is:

Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>

Cheers,

Paul

> Regards,
> Samuel
> 
> >> Signed-off-by: Samuel Holland <samuel@sholland.org>
> >> ---
> >>
> >>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
> >>  1 file changed, 4 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> >> index 625c6e1e9990..9698d68d0db7 100644
> >> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> >> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> >> @@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
> >>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
> >>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
> >>  
> >> -	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> >> -		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> >> -		     SUN6I_DPHY_GCTL_EN);
> >> -
> >>  	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
> >>  		     SUN6I_DPHY_ANA0_REG_PWS |
> >>  		     SUN6I_DPHY_ANA0_REG_DMPC |
> >> @@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
> >>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
> >>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
> >>  
> >> +	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> >> +		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> >> +		     SUN6I_DPHY_GCTL_EN);
> >> +
> >>  	return 0;
> >>  }
> >>  
> >> -- 
> >> 2.35.1
> >>
> > 
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 6/8] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit last

[Paul Kocialkowski]

[-- Attachment #1.1: Type: text/plain, Size: 3152 bytes --]

Hi Samuel,

On Fri 12 Aug 22, 17:31, Samuel Holland wrote:
> Hi Paul,
> 
> On 8/12/22 7:03 AM, Paul Kocialkowski wrote:
> > On Fri 12 Aug 22, 02:56, Samuel Holland wrote:
> >> The A100 variant of the DPHY requires configuring the analog registers
> >> before setting the global enable bit. Since this order also works on the
> >> other variants, always use it, to minimize the differences between them.
> > 
> > Did you get a chance to actually test this with either DSI/CSI-2 hardware?
> 
> I have tested DSI output with the Clockwork DevTerm (D1 SoC) and Pine64
> PinePhone (A64 SoC). I do not have any MIPI CSI hardware to test with.

Sounds good to me then!

> > I vaguely remember that the order mattered. Do you have an idea of what the
> > Allwinner BSP does too?
> 
> The Allwinner BSP makes the same change as this commit in its "lowlevel_v2x"
> copy of the code, which is used for R40 and T7 (original DPHY) and A100 and D1
> (updated DPHY). It does not make the change in "lowlevel_sun50iw1" (A64 SoC,
> original DPHY), but I tested A64 with this change, and it works fine.

Great, thanks for details.

> > Otherwise I could give it a try, at least with my MIPI CSI-2 setup
> > that uses the driver.
> 
> This commit only changes sun6i_dphy_tx_power_on(). The code for RX is unchanged
> -- in fact, it already sets SUN6I_DPHY_GCTL_REG last.

Ah yes you're right, actually I remember being tempted to change this too when
adding the rx path, but didn't have hardware to easily test.

Thanks for the details, this is:

Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>

Cheers,

Paul

> Regards,
> Samuel
> 
> >> Signed-off-by: Samuel Holland <samuel@sholland.org>
> >> ---
> >>
> >>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
> >>  1 file changed, 4 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> >> index 625c6e1e9990..9698d68d0db7 100644
> >> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> >> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> >> @@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
> >>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
> >>  		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
> >>  
> >> -	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> >> -		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> >> -		     SUN6I_DPHY_GCTL_EN);
> >> -
> >>  	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
> >>  		     SUN6I_DPHY_ANA0_REG_PWS |
> >>  		     SUN6I_DPHY_ANA0_REG_DMPC |
> >> @@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
> >>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
> >>  			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
> >>  
> >> +	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> >> +		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> >> +		     SUN6I_DPHY_GCTL_EN);
> >> +
> >>  	return 0;
> >>  }
> >>  
> >> -- 
> >> 2.35.1
> >>
> > 
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 4/8] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant

[Paul Kocialkowski]

[-- Attachment #1: Type: text/plain, Size: 2099 bytes --]

Hi Samuel,

On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
> A100 features an updated DPHY, which moves PLL control inside the DPHY
> register space. (Previously PLL-MIPI was controlled from the CCU. This
> does not affect the "clocks" property because the link between PLL-MIPI
> and the DPHY was never represented in the devicetree.) It also requires
> a modified analog power-on sequence. Finally, the new DPHY adds support
> for operating as an LVDS PHY. D1 uses this same variant.

Do you have some pointers about that? I'd be surprised that this PHY is now
used for "traditional" LVDS display output, which is usually done with a simpler
LVDS phy attached to the display controller.

However I've seen that some new Allwinner SoCs come with sub-LVDS camera input,
which typically requires a more complex PHY due to the high number of lanes.

Anyway for now this is:
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>

Cheers,

Paul

> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> index cf49bd99b3e2..b88c4b52af7d 100644
> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> @@ -17,9 +17,13 @@ properties:
>    compatible:
>      oneOf:
>        - const: allwinner,sun6i-a31-mipi-dphy
> +      - const: allwinner,sun50i-a100-mipi-dphy
>        - items:
>            - const: allwinner,sun50i-a64-mipi-dphy
>            - const: allwinner,sun6i-a31-mipi-dphy
> +      - items:
> +          - const: allwinner,sun20i-d1-mipi-dphy
> +          - const: allwinner,sun50i-a100-mipi-dphy
>  
>    reg:
>      maxItems: 1
> -- 
> 2.35.1
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 4/8] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant

[Paul Kocialkowski]

[-- Attachment #1.1: Type: text/plain, Size: 2099 bytes --]

Hi Samuel,

On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
> A100 features an updated DPHY, which moves PLL control inside the DPHY
> register space. (Previously PLL-MIPI was controlled from the CCU. This
> does not affect the "clocks" property because the link between PLL-MIPI
> and the DPHY was never represented in the devicetree.) It also requires
> a modified analog power-on sequence. Finally, the new DPHY adds support
> for operating as an LVDS PHY. D1 uses this same variant.

Do you have some pointers about that? I'd be surprised that this PHY is now
used for "traditional" LVDS display output, which is usually done with a simpler
LVDS phy attached to the display controller.

However I've seen that some new Allwinner SoCs come with sub-LVDS camera input,
which typically requires a more complex PHY due to the high number of lanes.

Anyway for now this is:
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>

Cheers,

Paul

> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> index cf49bd99b3e2..b88c4b52af7d 100644
> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> @@ -17,9 +17,13 @@ properties:
>    compatible:
>      oneOf:
>        - const: allwinner,sun6i-a31-mipi-dphy
> +      - const: allwinner,sun50i-a100-mipi-dphy
>        - items:
>            - const: allwinner,sun50i-a64-mipi-dphy
>            - const: allwinner,sun6i-a31-mipi-dphy
> +      - items:
> +          - const: allwinner,sun20i-d1-mipi-dphy
> +          - const: allwinner,sun50i-a100-mipi-dphy
>  
>    reg:
>      maxItems: 1
> -- 
> 2.35.1
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
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Re: [PATCH 4/8] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant

[Paul Kocialkowski]

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Hi Samuel,

On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
> A100 features an updated DPHY, which moves PLL control inside the DPHY
> register space. (Previously PLL-MIPI was controlled from the CCU. This
> does not affect the "clocks" property because the link between PLL-MIPI
> and the DPHY was never represented in the devicetree.) It also requires
> a modified analog power-on sequence. Finally, the new DPHY adds support
> for operating as an LVDS PHY. D1 uses this same variant.

Do you have some pointers about that? I'd be surprised that this PHY is now
used for "traditional" LVDS display output, which is usually done with a simpler
LVDS phy attached to the display controller.

However I've seen that some new Allwinner SoCs come with sub-LVDS camera input,
which typically requires a more complex PHY due to the high number of lanes.

Anyway for now this is:
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>

Cheers,

Paul

> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> index cf49bd99b3e2..b88c4b52af7d 100644
> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> @@ -17,9 +17,13 @@ properties:
>    compatible:
>      oneOf:
>        - const: allwinner,sun6i-a31-mipi-dphy
> +      - const: allwinner,sun50i-a100-mipi-dphy
>        - items:
>            - const: allwinner,sun50i-a64-mipi-dphy
>            - const: allwinner,sun6i-a31-mipi-dphy
> +      - items:
> +          - const: allwinner,sun20i-d1-mipi-dphy
> +          - const: allwinner,sun50i-a100-mipi-dphy
>  
>    reg:
>      maxItems: 1
> -- 
> 2.35.1
> 

-- 
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Re: [PATCH 4/8] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant

[Samuel Holland]

On 8/25/22 5:41 AM, Paul Kocialkowski wrote:
> Hi Samuel,
> 
> On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
>> A100 features an updated DPHY, which moves PLL control inside the DPHY
>> register space. (Previously PLL-MIPI was controlled from the CCU. This
>> does not affect the "clocks" property because the link between PLL-MIPI
>> and the DPHY was never represented in the devicetree.) It also requires
>> a modified analog power-on sequence. Finally, the new DPHY adds support
>> for operating as an LVDS PHY. D1 uses this same variant.
> 
> Do you have some pointers about that? I'd be surprised that this PHY is now
> used for "traditional" LVDS display output, which is usually done with a simpler
> LVDS phy attached to the display controller.

Yes, this is documented in the A133 User Manual. As for the BSP code, see:

https://github.com/Tina-Linux/tina-d1x-linux-5.4/blob/master/drivers/video/fbdev/sunxi/disp2/disp/de/lowlevel_v2x/de_dsi.c#L773
https://github.com/Tina-Linux/tina-d1x-linux-5.4/blob/master/drivers/video/fbdev/sunxi/disp2/disp/de/lowlevel_v2x/de_lcd_sun50iw10.c#L390
https://github.com/Tina-Linux/tina-d1x-linux-5.4/blob/master/drivers/video/fbdev/sunxi/disp2/disp/de/disp_lcd.c#L786

Regards,
Samuel

> However I've seen that some new Allwinner SoCs come with sub-LVDS camera input,
> which typically requires a more complex PHY due to the high number of lanes.
> 
> Anyway for now this is:
> Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> 
> Cheers,
> 
> Paul
> 
>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>> ---
>>
>>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> index cf49bd99b3e2..b88c4b52af7d 100644
>> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> @@ -17,9 +17,13 @@ properties:
>>    compatible:
>>      oneOf:
>>        - const: allwinner,sun6i-a31-mipi-dphy
>> +      - const: allwinner,sun50i-a100-mipi-dphy
>>        - items:
>>            - const: allwinner,sun50i-a64-mipi-dphy
>>            - const: allwinner,sun6i-a31-mipi-dphy
>> +      - items:
>> +          - const: allwinner,sun20i-d1-mipi-dphy
>> +          - const: allwinner,sun50i-a100-mipi-dphy
>>  
>>    reg:
>>      maxItems: 1
>> -- 
>> 2.35.1
>>
> 

Re: [PATCH 4/8] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant

[Samuel Holland]

On 8/25/22 5:41 AM, Paul Kocialkowski wrote:
> Hi Samuel,
> 
> On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
>> A100 features an updated DPHY, which moves PLL control inside the DPHY
>> register space. (Previously PLL-MIPI was controlled from the CCU. This
>> does not affect the "clocks" property because the link between PLL-MIPI
>> and the DPHY was never represented in the devicetree.) It also requires
>> a modified analog power-on sequence. Finally, the new DPHY adds support
>> for operating as an LVDS PHY. D1 uses this same variant.
> 
> Do you have some pointers about that? I'd be surprised that this PHY is now
> used for "traditional" LVDS display output, which is usually done with a simpler
> LVDS phy attached to the display controller.

Yes, this is documented in the A133 User Manual. As for the BSP code, see:

https://github.com/Tina-Linux/tina-d1x-linux-5.4/blob/master/drivers/video/fbdev/sunxi/disp2/disp/de/lowlevel_v2x/de_dsi.c#L773
https://github.com/Tina-Linux/tina-d1x-linux-5.4/blob/master/drivers/video/fbdev/sunxi/disp2/disp/de/lowlevel_v2x/de_lcd_sun50iw10.c#L390
https://github.com/Tina-Linux/tina-d1x-linux-5.4/blob/master/drivers/video/fbdev/sunxi/disp2/disp/de/disp_lcd.c#L786

Regards,
Samuel

> However I've seen that some new Allwinner SoCs come with sub-LVDS camera input,
> which typically requires a more complex PHY due to the high number of lanes.
> 
> Anyway for now this is:
> Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> 
> Cheers,
> 
> Paul
> 
>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>> ---
>>
>>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> index cf49bd99b3e2..b88c4b52af7d 100644
>> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> @@ -17,9 +17,13 @@ properties:
>>    compatible:
>>      oneOf:
>>        - const: allwinner,sun6i-a31-mipi-dphy
>> +      - const: allwinner,sun50i-a100-mipi-dphy
>>        - items:
>>            - const: allwinner,sun50i-a64-mipi-dphy
>>            - const: allwinner,sun6i-a31-mipi-dphy
>> +      - items:
>> +          - const: allwinner,sun20i-d1-mipi-dphy
>> +          - const: allwinner,sun50i-a100-mipi-dphy
>>  
>>    reg:
>>      maxItems: 1
>> -- 
>> 2.35.1
>>
> 


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Re: [PATCH 4/8] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant

[Samuel Holland]

On 8/25/22 5:41 AM, Paul Kocialkowski wrote:
> Hi Samuel,
> 
> On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
>> A100 features an updated DPHY, which moves PLL control inside the DPHY
>> register space. (Previously PLL-MIPI was controlled from the CCU. This
>> does not affect the "clocks" property because the link between PLL-MIPI
>> and the DPHY was never represented in the devicetree.) It also requires
>> a modified analog power-on sequence. Finally, the new DPHY adds support
>> for operating as an LVDS PHY. D1 uses this same variant.
> 
> Do you have some pointers about that? I'd be surprised that this PHY is now
> used for "traditional" LVDS display output, which is usually done with a simpler
> LVDS phy attached to the display controller.

Yes, this is documented in the A133 User Manual. As for the BSP code, see:

https://github.com/Tina-Linux/tina-d1x-linux-5.4/blob/master/drivers/video/fbdev/sunxi/disp2/disp/de/lowlevel_v2x/de_dsi.c#L773
https://github.com/Tina-Linux/tina-d1x-linux-5.4/blob/master/drivers/video/fbdev/sunxi/disp2/disp/de/lowlevel_v2x/de_lcd_sun50iw10.c#L390
https://github.com/Tina-Linux/tina-d1x-linux-5.4/blob/master/drivers/video/fbdev/sunxi/disp2/disp/de/disp_lcd.c#L786

Regards,
Samuel

> However I've seen that some new Allwinner SoCs come with sub-LVDS camera input,
> which typically requires a more complex PHY due to the high number of lanes.
> 
> Anyway for now this is:
> Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> 
> Cheers,
> 
> Paul
> 
>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>> ---
>>
>>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> index cf49bd99b3e2..b88c4b52af7d 100644
>> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>> @@ -17,9 +17,13 @@ properties:
>>    compatible:
>>      oneOf:
>>        - const: allwinner,sun6i-a31-mipi-dphy
>> +      - const: allwinner,sun50i-a100-mipi-dphy
>>        - items:
>>            - const: allwinner,sun50i-a64-mipi-dphy
>>            - const: allwinner,sun6i-a31-mipi-dphy
>> +      - items:
>> +          - const: allwinner,sun20i-d1-mipi-dphy
>> +          - const: allwinner,sun50i-a100-mipi-dphy
>>  
>>    reg:
>>      maxItems: 1
>> -- 
>> 2.35.1
>>
> 


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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Paul Kocialkowski]

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Hi Samuel,

On Fri 12 Aug 22, 17:19, Samuel Holland wrote:
> On 8/12/22 5:45 AM, Krzysztof Kozlowski wrote:
> > On 12/08/2022 10:55, Samuel Holland wrote:
> >> The sun6i DPHY can generate several interrupts, mostly for reporting
> >> error conditions, but also for detecting BTA and UPLS sequences.
> >> Document this capability in order to accurately describe the hardware.
> >>
> >> The DPHY has no interrupt number provided in the vendor documentation
> >> because its interrupt line is shared with the DSI controller.
> >>
> >> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> > 
> > I don't understand what is being fixed in that commit. That commit did
> > not have interrupts in D-PHY, so what was broken by it?
> > 
> > The Fixes tag annotates the commit which introduced a bug.
> 
> The binding had a bug because it did not accurately describe the hardware.

[...]

Coming back to this series, I don't really get the point of introducing the
interrupt in the bindings and the device-tree sources if the interrupt is not
required for normal operation. I would just drop it.

I recall I was in the same situation for the MIPI CSI-2 controllers, which also
have a dedicated interrupt but only useful for debugging/error reporting.
I was asked not to introduce it back then, so I suppose the same should apply.

What do you think?

Cheers,

Paul

-- 
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https://bootlin.com

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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Paul Kocialkowski]

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Hi Samuel,

On Fri 12 Aug 22, 17:19, Samuel Holland wrote:
> On 8/12/22 5:45 AM, Krzysztof Kozlowski wrote:
> > On 12/08/2022 10:55, Samuel Holland wrote:
> >> The sun6i DPHY can generate several interrupts, mostly for reporting
> >> error conditions, but also for detecting BTA and UPLS sequences.
> >> Document this capability in order to accurately describe the hardware.
> >>
> >> The DPHY has no interrupt number provided in the vendor documentation
> >> because its interrupt line is shared with the DSI controller.
> >>
> >> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> > 
> > I don't understand what is being fixed in that commit. That commit did
> > not have interrupts in D-PHY, so what was broken by it?
> > 
> > The Fixes tag annotates the commit which introduced a bug.
> 
> The binding had a bug because it did not accurately describe the hardware.

[...]

Coming back to this series, I don't really get the point of introducing the
interrupt in the bindings and the device-tree sources if the interrupt is not
required for normal operation. I would just drop it.

I recall I was in the same situation for the MIPI CSI-2 controllers, which also
have a dedicated interrupt but only useful for debugging/error reporting.
I was asked not to introduce it back then, so I suppose the same should apply.

What do you think?

Cheers,

Paul

-- 
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Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Paul Kocialkowski]

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Hi Samuel,

On Fri 12 Aug 22, 17:19, Samuel Holland wrote:
> On 8/12/22 5:45 AM, Krzysztof Kozlowski wrote:
> > On 12/08/2022 10:55, Samuel Holland wrote:
> >> The sun6i DPHY can generate several interrupts, mostly for reporting
> >> error conditions, but also for detecting BTA and UPLS sequences.
> >> Document this capability in order to accurately describe the hardware.
> >>
> >> The DPHY has no interrupt number provided in the vendor documentation
> >> because its interrupt line is shared with the DSI controller.
> >>
> >> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> > 
> > I don't understand what is being fixed in that commit. That commit did
> > not have interrupts in D-PHY, so what was broken by it?
> > 
> > The Fixes tag annotates the commit which introduced a bug.
> 
> The binding had a bug because it did not accurately describe the hardware.

[...]

Coming back to this series, I don't really get the point of introducing the
interrupt in the bindings and the device-tree sources if the interrupt is not
required for normal operation. I would just drop it.

I recall I was in the same situation for the MIPI CSI-2 controllers, which also
have a dedicated interrupt but only useful for debugging/error reporting.
I was asked not to introduce it back then, so I suppose the same should apply.

What do you think?

Cheers,

Paul

-- 
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Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 5/8] phy: allwinner: phy-sun6i-mipi-dphy: Make RX support optional

[Paul Kocialkowski]

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Hi Samuel,

On Fri 12 Aug 22, 02:56, Samuel Holland wrote:
> While all variants of the DPHY likely support RX mode, the new variant
> in the A100 is not used in this direction by the BSP, and it has some
> analog register changes, so its RX power-on sequence is unknown. To be
> safe, limit RX support to variants where the power-on sequence is known.

Coming back to this series, with some minor cosmetic suggestions.

> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 25 +++++++++++++++++++--
>  1 file changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> index 3900f1650851..625c6e1e9990 100644
> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> @@ -114,6 +114,10 @@ enum sun6i_dphy_direction {
>  	SUN6I_DPHY_DIRECTION_RX,
>  };
>  
> +struct sun6i_dphy_variant {
> +	bool	supports_rx;

Since you're introducing a "tx_power_on" field later on, it would be more
consistent to call this one "rx_supported".

> +};
> +
>  struct sun6i_dphy {
>  	struct clk				*bus_clk;
>  	struct clk				*mod_clk;
> @@ -123,6 +127,7 @@ struct sun6i_dphy {
>  	struct phy				*phy;
>  	struct phy_configure_opts_mipi_dphy	config;
>  
> +	const struct sun6i_dphy_variant		*variant;
>  	enum sun6i_dphy_direction		direction;
>  };
>  
> @@ -409,6 +414,10 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
>  	if (!dphy)
>  		return -ENOMEM;
>  
> +	dphy->variant = device_get_match_data(&pdev->dev);
> +	if (!dphy->variant)
> +		return -EINVAL;
> +
>  	regs = devm_platform_ioremap_resource(pdev, 0);
>  	if (IS_ERR(regs)) {
>  		dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
> @@ -445,8 +454,13 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
>  	ret = of_property_read_string(pdev->dev.of_node, "allwinner,direction",
>  				      &direction);
>  
> -	if (!ret && !strncmp(direction, "rx", 2))
> +	if (!ret && !strncmp(direction, "rx", 2)) {
> +		if (!dphy->variant->supports_rx) {
> +			dev_err(&pdev->dev, "RX not supported on this variant\n");
> +			return -EOPNOTSUPP;
> +		}

Maybe add a blank line here for readability.

Looks good to me otherwise!

Paul

>  		dphy->direction = SUN6I_DPHY_DIRECTION_RX;
> +	}
>  
>  	phy_set_drvdata(dphy->phy, dphy);
>  	phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
> @@ -454,8 +468,15 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
>  	return PTR_ERR_OR_ZERO(phy_provider);
>  }
>  
> +static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
> +	.supports_rx	= true,
> +};
> +
>  static const struct of_device_id sun6i_dphy_of_table[] = {
> -	{ .compatible = "allwinner,sun6i-a31-mipi-dphy" },
> +	{
> +		.compatible	= "allwinner,sun6i-a31-mipi-dphy",
> +		.data		= &sun6i_a31_mipi_dphy_variant,
> +	},
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
> -- 
> 2.35.1
> 

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Re: [PATCH 5/8] phy: allwinner: phy-sun6i-mipi-dphy: Make RX support optional

[Paul Kocialkowski]

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Hi Samuel,

On Fri 12 Aug 22, 02:56, Samuel Holland wrote:
> While all variants of the DPHY likely support RX mode, the new variant
> in the A100 is not used in this direction by the BSP, and it has some
> analog register changes, so its RX power-on sequence is unknown. To be
> safe, limit RX support to variants where the power-on sequence is known.

Coming back to this series, with some minor cosmetic suggestions.

> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 25 +++++++++++++++++++--
>  1 file changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> index 3900f1650851..625c6e1e9990 100644
> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> @@ -114,6 +114,10 @@ enum sun6i_dphy_direction {
>  	SUN6I_DPHY_DIRECTION_RX,
>  };
>  
> +struct sun6i_dphy_variant {
> +	bool	supports_rx;

Since you're introducing a "tx_power_on" field later on, it would be more
consistent to call this one "rx_supported".

> +};
> +
>  struct sun6i_dphy {
>  	struct clk				*bus_clk;
>  	struct clk				*mod_clk;
> @@ -123,6 +127,7 @@ struct sun6i_dphy {
>  	struct phy				*phy;
>  	struct phy_configure_opts_mipi_dphy	config;
>  
> +	const struct sun6i_dphy_variant		*variant;
>  	enum sun6i_dphy_direction		direction;
>  };
>  
> @@ -409,6 +414,10 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
>  	if (!dphy)
>  		return -ENOMEM;
>  
> +	dphy->variant = device_get_match_data(&pdev->dev);
> +	if (!dphy->variant)
> +		return -EINVAL;
> +
>  	regs = devm_platform_ioremap_resource(pdev, 0);
>  	if (IS_ERR(regs)) {
>  		dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
> @@ -445,8 +454,13 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
>  	ret = of_property_read_string(pdev->dev.of_node, "allwinner,direction",
>  				      &direction);
>  
> -	if (!ret && !strncmp(direction, "rx", 2))
> +	if (!ret && !strncmp(direction, "rx", 2)) {
> +		if (!dphy->variant->supports_rx) {
> +			dev_err(&pdev->dev, "RX not supported on this variant\n");
> +			return -EOPNOTSUPP;
> +		}

Maybe add a blank line here for readability.

Looks good to me otherwise!

Paul

>  		dphy->direction = SUN6I_DPHY_DIRECTION_RX;
> +	}
>  
>  	phy_set_drvdata(dphy->phy, dphy);
>  	phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
> @@ -454,8 +468,15 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
>  	return PTR_ERR_OR_ZERO(phy_provider);
>  }
>  
> +static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
> +	.supports_rx	= true,
> +};
> +
>  static const struct of_device_id sun6i_dphy_of_table[] = {
> -	{ .compatible = "allwinner,sun6i-a31-mipi-dphy" },
> +	{
> +		.compatible	= "allwinner,sun6i-a31-mipi-dphy",
> +		.data		= &sun6i_a31_mipi_dphy_variant,
> +	},
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
> -- 
> 2.35.1
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 5/8] phy: allwinner: phy-sun6i-mipi-dphy: Make RX support optional

[Paul Kocialkowski]

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Hi Samuel,

On Fri 12 Aug 22, 02:56, Samuel Holland wrote:
> While all variants of the DPHY likely support RX mode, the new variant
> in the A100 is not used in this direction by the BSP, and it has some
> analog register changes, so its RX power-on sequence is unknown. To be
> safe, limit RX support to variants where the power-on sequence is known.

Coming back to this series, with some minor cosmetic suggestions.

> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 25 +++++++++++++++++++--
>  1 file changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> index 3900f1650851..625c6e1e9990 100644
> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> @@ -114,6 +114,10 @@ enum sun6i_dphy_direction {
>  	SUN6I_DPHY_DIRECTION_RX,
>  };
>  
> +struct sun6i_dphy_variant {
> +	bool	supports_rx;

Since you're introducing a "tx_power_on" field later on, it would be more
consistent to call this one "rx_supported".

> +};
> +
>  struct sun6i_dphy {
>  	struct clk				*bus_clk;
>  	struct clk				*mod_clk;
> @@ -123,6 +127,7 @@ struct sun6i_dphy {
>  	struct phy				*phy;
>  	struct phy_configure_opts_mipi_dphy	config;
>  
> +	const struct sun6i_dphy_variant		*variant;
>  	enum sun6i_dphy_direction		direction;
>  };
>  
> @@ -409,6 +414,10 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
>  	if (!dphy)
>  		return -ENOMEM;
>  
> +	dphy->variant = device_get_match_data(&pdev->dev);
> +	if (!dphy->variant)
> +		return -EINVAL;
> +
>  	regs = devm_platform_ioremap_resource(pdev, 0);
>  	if (IS_ERR(regs)) {
>  		dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
> @@ -445,8 +454,13 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
>  	ret = of_property_read_string(pdev->dev.of_node, "allwinner,direction",
>  				      &direction);
>  
> -	if (!ret && !strncmp(direction, "rx", 2))
> +	if (!ret && !strncmp(direction, "rx", 2)) {
> +		if (!dphy->variant->supports_rx) {
> +			dev_err(&pdev->dev, "RX not supported on this variant\n");
> +			return -EOPNOTSUPP;
> +		}

Maybe add a blank line here for readability.

Looks good to me otherwise!

Paul

>  		dphy->direction = SUN6I_DPHY_DIRECTION_RX;
> +	}
>  
>  	phy_set_drvdata(dphy->phy, dphy);
>  	phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
> @@ -454,8 +468,15 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
>  	return PTR_ERR_OR_ZERO(phy_provider);
>  }
>  
> +static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
> +	.supports_rx	= true,
> +};
> +
>  static const struct of_device_id sun6i_dphy_of_table[] = {
> -	{ .compatible = "allwinner,sun6i-a31-mipi-dphy" },
> +	{
> +		.compatible	= "allwinner,sun6i-a31-mipi-dphy",
> +		.data		= &sun6i_a31_mipi_dphy_variant,
> +	},
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
> -- 
> 2.35.1
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Paul Kocialkowski]

[-- Attachment #1: Type: text/plain, Size: 1887 bytes --]

Hi,

On Mon 26 Sep 22, 11:28, Paul Kocialkowski wrote:
> Hi Samuel,
> 
> On Fri 12 Aug 22, 17:19, Samuel Holland wrote:
> > On 8/12/22 5:45 AM, Krzysztof Kozlowski wrote:
> > > On 12/08/2022 10:55, Samuel Holland wrote:
> > >> The sun6i DPHY can generate several interrupts, mostly for reporting
> > >> error conditions, but also for detecting BTA and UPLS sequences.
> > >> Document this capability in order to accurately describe the hardware.
> > >>
> > >> The DPHY has no interrupt number provided in the vendor documentation
> > >> because its interrupt line is shared with the DSI controller.
> > >>
> > >> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> > > 
> > > I don't understand what is being fixed in that commit. That commit did
> > > not have interrupts in D-PHY, so what was broken by it?
> > > 
> > > The Fixes tag annotates the commit which introduced a bug.
> > 
> > The binding had a bug because it did not accurately describe the hardware.
> 
> [...]
> 
> Coming back to this series, I don't really get the point of introducing the
> interrupt in the bindings and the device-tree sources if the interrupt is not
> required for normal operation. I would just drop it.
> 
> I recall I was in the same situation for the MIPI CSI-2 controllers, which also
> have a dedicated interrupt but only useful for debugging/error reporting.
> I was asked not to introduce it back then, so I suppose the same should apply.

Coming back to this, my memories were wrong and the interrupt was in fact added
to the binding and the dt description.

Nevermind my previous comment, I guess it does make sense to have it in the dt
hardware description even if the driver does not use it.

Sorry for the noise,

Paul

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Paul Kocialkowski]

[-- Attachment #1.1: Type: text/plain, Size: 1887 bytes --]

Hi,

On Mon 26 Sep 22, 11:28, Paul Kocialkowski wrote:
> Hi Samuel,
> 
> On Fri 12 Aug 22, 17:19, Samuel Holland wrote:
> > On 8/12/22 5:45 AM, Krzysztof Kozlowski wrote:
> > > On 12/08/2022 10:55, Samuel Holland wrote:
> > >> The sun6i DPHY can generate several interrupts, mostly for reporting
> > >> error conditions, but also for detecting BTA and UPLS sequences.
> > >> Document this capability in order to accurately describe the hardware.
> > >>
> > >> The DPHY has no interrupt number provided in the vendor documentation
> > >> because its interrupt line is shared with the DSI controller.
> > >>
> > >> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> > > 
> > > I don't understand what is being fixed in that commit. That commit did
> > > not have interrupts in D-PHY, so what was broken by it?
> > > 
> > > The Fixes tag annotates the commit which introduced a bug.
> > 
> > The binding had a bug because it did not accurately describe the hardware.
> 
> [...]
> 
> Coming back to this series, I don't really get the point of introducing the
> interrupt in the bindings and the device-tree sources if the interrupt is not
> required for normal operation. I would just drop it.
> 
> I recall I was in the same situation for the MIPI CSI-2 controllers, which also
> have a dedicated interrupt but only useful for debugging/error reporting.
> I was asked not to introduce it back then, so I suppose the same should apply.

Coming back to this, my memories were wrong and the interrupt was in fact added
to the binding and the dt description.

Nevermind my previous comment, I guess it does make sense to have it in the dt
hardware description even if the driver does not use it.

Sorry for the noise,

Paul

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Paul Kocialkowski]

[-- Attachment #1.1: Type: text/plain, Size: 1887 bytes --]

Hi,

On Mon 26 Sep 22, 11:28, Paul Kocialkowski wrote:
> Hi Samuel,
> 
> On Fri 12 Aug 22, 17:19, Samuel Holland wrote:
> > On 8/12/22 5:45 AM, Krzysztof Kozlowski wrote:
> > > On 12/08/2022 10:55, Samuel Holland wrote:
> > >> The sun6i DPHY can generate several interrupts, mostly for reporting
> > >> error conditions, but also for detecting BTA and UPLS sequences.
> > >> Document this capability in order to accurately describe the hardware.
> > >>
> > >> The DPHY has no interrupt number provided in the vendor documentation
> > >> because its interrupt line is shared with the DSI controller.
> > >>
> > >> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
> > > 
> > > I don't understand what is being fixed in that commit. That commit did
> > > not have interrupts in D-PHY, so what was broken by it?
> > > 
> > > The Fixes tag annotates the commit which introduced a bug.
> > 
> > The binding had a bug because it did not accurately describe the hardware.
> 
> [...]
> 
> Coming back to this series, I don't really get the point of introducing the
> interrupt in the bindings and the device-tree sources if the interrupt is not
> required for normal operation. I would just drop it.
> 
> I recall I was in the same situation for the MIPI CSI-2 controllers, which also
> have a dedicated interrupt but only useful for debugging/error reporting.
> I was asked not to introduce it back then, so I suppose the same should apply.

Coming back to this, my memories were wrong and the interrupt was in fact added
to the binding and the dt description.

Nevermind my previous comment, I guess it does make sense to have it in the dt
hardware description even if the driver does not use it.

Sorry for the noise,

Paul

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Samuel Holland]

Hi Paul,

On 8/12/22 17:44, Samuel Holland wrote:
> On 8/12/22 7:22 AM, Paul Kocialkowski wrote:
>> On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
>>> The sun6i DPHY can generate several interrupts, mostly for reporting
>>> error conditions, but also for detecting BTA and UPLS sequences.
>>> Document this capability in order to accurately describe the hardware.
>>>
>>> The DPHY has no interrupt number provided in the vendor documentation
>>> because its interrupt line is shared with the DSI controller.
>>
>> Interesting! I do see DPHY_INT_EN*/PD* in the Allwinner BSP's
>> drivers/media/video/sunxi-vfe/mipi_csi/dphy/dphy_reg_i.h
> 
> You can also find some bit of documentation in the T7 User Manual.
> 
>> Maybe it would be useful to import the fields in the driver so that the
>> next person who'll try to debug DSI can use them directly?
>>
>> You might also want to submit a patch as [PATCH NOT FOR MERGE] that
>> adds an interrupt routine and some useful debugging.
> 
> I think this would be more interesting to someone who knew more about MIPI
> CSI/DSI and understood what those errors meant. :)
> 
> I'm mostly concerned with bringing up the D1 SoC at the moment.

I added a trivial IRQ handler that dumps the status registers, just to
verify the interrupt number, and I got several interrupts during DSI
panel setup (so during DCS commands), mostly with DPHY_INT_PD0_REG =
0x03000000, signaling some sort of contention detection.

>> Do you think this is also available without a DSI controller?
>> I could just give it a try on V3/A83t here and find out :)
> 
> I would assume so. It could possibly be shared with the MIPI CSI interrupt (SPI
> 90) or keep its position at SPI 89.

Did you get a chance to try this? I am about to send v2 of this series.
I wonder if I should keep the interrupts property as required, since I
don't know if the interrupt is actually hooked up on SoCs with CSI only.

Regards,
Samuel

>>> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
>>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>>> ---
>>>
>>>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>>>  1 file changed, 4 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>>> index 22636c9fdab8..cf49bd99b3e2 100644
>>> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>>> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>>> @@ -24,6 +24,9 @@ properties:
>>>    reg:
>>>      maxItems: 1
>>>  
>>> +  interrupts:
>>> +    maxItems: 1
>>> +
>>>    clocks:
>>>      items:
>>>        - description: Bus Clock
>>> @@ -53,6 +56,7 @@ required:
>>>    - "#phy-cells"
>>>    - compatible
>>>    - reg
>>> +  - interrupts
>>>    - clocks
>>>    - clock-names
>>>    - resets
>>> -- 
>>> 2.35.1
>>>
>>
> 
> 

Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Samuel Holland]

Hi Paul,

On 8/12/22 17:44, Samuel Holland wrote:
> On 8/12/22 7:22 AM, Paul Kocialkowski wrote:
>> On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
>>> The sun6i DPHY can generate several interrupts, mostly for reporting
>>> error conditions, but also for detecting BTA and UPLS sequences.
>>> Document this capability in order to accurately describe the hardware.
>>>
>>> The DPHY has no interrupt number provided in the vendor documentation
>>> because its interrupt line is shared with the DSI controller.
>>
>> Interesting! I do see DPHY_INT_EN*/PD* in the Allwinner BSP's
>> drivers/media/video/sunxi-vfe/mipi_csi/dphy/dphy_reg_i.h
> 
> You can also find some bit of documentation in the T7 User Manual.
> 
>> Maybe it would be useful to import the fields in the driver so that the
>> next person who'll try to debug DSI can use them directly?
>>
>> You might also want to submit a patch as [PATCH NOT FOR MERGE] that
>> adds an interrupt routine and some useful debugging.
> 
> I think this would be more interesting to someone who knew more about MIPI
> CSI/DSI and understood what those errors meant. :)
> 
> I'm mostly concerned with bringing up the D1 SoC at the moment.

I added a trivial IRQ handler that dumps the status registers, just to
verify the interrupt number, and I got several interrupts during DSI
panel setup (so during DCS commands), mostly with DPHY_INT_PD0_REG =
0x03000000, signaling some sort of contention detection.

>> Do you think this is also available without a DSI controller?
>> I could just give it a try on V3/A83t here and find out :)
> 
> I would assume so. It could possibly be shared with the MIPI CSI interrupt (SPI
> 90) or keep its position at SPI 89.

Did you get a chance to try this? I am about to send v2 of this series.
I wonder if I should keep the interrupts property as required, since I
don't know if the interrupt is actually hooked up on SoCs with CSI only.

Regards,
Samuel

>>> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
>>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>>> ---
>>>
>>>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>>>  1 file changed, 4 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>>> index 22636c9fdab8..cf49bd99b3e2 100644
>>> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>>> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>>> @@ -24,6 +24,9 @@ properties:
>>>    reg:
>>>      maxItems: 1
>>>  
>>> +  interrupts:
>>> +    maxItems: 1
>>> +
>>>    clocks:
>>>      items:
>>>        - description: Bus Clock
>>> @@ -53,6 +56,7 @@ required:
>>>    - "#phy-cells"
>>>    - compatible
>>>    - reg
>>> +  - interrupts
>>>    - clocks
>>>    - clock-names
>>>    - resets
>>> -- 
>>> 2.35.1
>>>
>>
> 
> 


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Re: [PATCH 1/8] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property

[Samuel Holland]

Hi Paul,

On 8/12/22 17:44, Samuel Holland wrote:
> On 8/12/22 7:22 AM, Paul Kocialkowski wrote:
>> On Fri 12 Aug 22, 02:55, Samuel Holland wrote:
>>> The sun6i DPHY can generate several interrupts, mostly for reporting
>>> error conditions, but also for detecting BTA and UPLS sequences.
>>> Document this capability in order to accurately describe the hardware.
>>>
>>> The DPHY has no interrupt number provided in the vendor documentation
>>> because its interrupt line is shared with the DSI controller.
>>
>> Interesting! I do see DPHY_INT_EN*/PD* in the Allwinner BSP's
>> drivers/media/video/sunxi-vfe/mipi_csi/dphy/dphy_reg_i.h
> 
> You can also find some bit of documentation in the T7 User Manual.
> 
>> Maybe it would be useful to import the fields in the driver so that the
>> next person who'll try to debug DSI can use them directly?
>>
>> You might also want to submit a patch as [PATCH NOT FOR MERGE] that
>> adds an interrupt routine and some useful debugging.
> 
> I think this would be more interesting to someone who knew more about MIPI
> CSI/DSI and understood what those errors meant. :)
> 
> I'm mostly concerned with bringing up the D1 SoC at the moment.

I added a trivial IRQ handler that dumps the status registers, just to
verify the interrupt number, and I got several interrupts during DSI
panel setup (so during DCS commands), mostly with DPHY_INT_PD0_REG =
0x03000000, signaling some sort of contention detection.

>> Do you think this is also available without a DSI controller?
>> I could just give it a try on V3/A83t here and find out :)
> 
> I would assume so. It could possibly be shared with the MIPI CSI interrupt (SPI
> 90) or keep its position at SPI 89.

Did you get a chance to try this? I am about to send v2 of this series.
I wonder if I should keep the interrupts property as required, since I
don't know if the interrupt is actually hooked up on SoCs with CSI only.

Regards,
Samuel

>>> Fixes: c25b84c00826 ("dt-bindings: display: Convert Allwinner DSI to a schema")
>>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>>> ---
>>>
>>>  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
>>>  1 file changed, 4 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>>> index 22636c9fdab8..cf49bd99b3e2 100644
>>> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>>> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
>>> @@ -24,6 +24,9 @@ properties:
>>>    reg:
>>>      maxItems: 1
>>>  
>>> +  interrupts:
>>> +    maxItems: 1
>>> +
>>>    clocks:
>>>      items:
>>>        - description: Bus Clock
>>> @@ -53,6 +56,7 @@ required:
>>>    - "#phy-cells"
>>>    - compatible
>>>    - reg
>>> +  - interrupts
>>>    - clocks
>>>    - clock-names
>>>    - resets
>>> -- 
>>> 2.35.1
>>>
>>
> 
> 


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