* [PATCH] zynq-fpga: Only route PR via PCAP when required @ 2018-10-23 6:31 ` Mike Looijmans 0 siblings, 0 replies; 20+ messages in thread From: Mike Looijmans @ 2018-10-23 6:31 UTC (permalink / raw) To: linux-fpga Cc: linux-arm-kernel, linux-kernel, michal.simek, mdf, atull, Mike Looijmans The Xilinx Zynq FPGA driver takes ownership of the PR interface, making it impossible to use the ICAP interface for partial reconfiguration. This patch changes the driver to only activate PR over PCAP while the device is actively being accessed by the driver for programming. This allows both PCAP and ICAP interfaces to be used for PR. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> --- drivers/fpga/zynq-fpga.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index 3110e00..f6c205a 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, int err; u32 intr_status; + /* Release 'PR' control back to the ICAP */ + zynq_fpga_write(priv, CTRL_OFFSET, + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); + err = clk_enable(priv->clk); if (err) return err; -- 1.9.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH] zynq-fpga: Only route PR via PCAP when required @ 2018-10-23 6:31 ` Mike Looijmans 0 siblings, 0 replies; 20+ messages in thread From: Mike Looijmans @ 2018-10-23 6:31 UTC (permalink / raw) To: linux-arm-kernel The Xilinx Zynq FPGA driver takes ownership of the PR interface, making it impossible to use the ICAP interface for partial reconfiguration. This patch changes the driver to only activate PR over PCAP while the device is actively being accessed by the driver for programming. This allows both PCAP and ICAP interfaces to be used for PR. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> --- drivers/fpga/zynq-fpga.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index 3110e00..f6c205a 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, int err; u32 intr_status; + /* Release 'PR' control back to the ICAP */ + zynq_fpga_write(priv, CTRL_OFFSET, + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); + err = clk_enable(priv->clk); if (err) return err; -- 1.9.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH] zynq-fpga: Only route PR via PCAP when required 2018-10-23 6:31 ` Mike Looijmans @ 2018-10-23 9:01 ` Moritz Fischer -1 siblings, 0 replies; 20+ messages in thread From: Moritz Fischer @ 2018-10-23 9:01 UTC (permalink / raw) To: Mike Looijmans Cc: linux-fpga, linux-arm-kernel, linux-kernel, michal.simek, mdf, atull Hi Mike, seems like a good usecase (though uncommon), question below On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote: > The Xilinx Zynq FPGA driver takes ownership of the PR interface, making > it impossible to use the ICAP interface for partial reconfiguration. > > This patch changes the driver to only activate PR over PCAP while the > device is actively being accessed by the driver for programming. > > This allows both PCAP and ICAP interfaces to be used for PR. > > Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> > --- > drivers/fpga/zynq-fpga.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c > index 3110e00..f6c205a 100644 > --- a/drivers/fpga/zynq-fpga.c > +++ b/drivers/fpga/zynq-fpga.c > @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, > int err; > u32 intr_status; > > + /* Release 'PR' control back to the ICAP */ > + zynq_fpga_write(priv, CTRL_OFFSET, > + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); > + Shouldn't that be after the below stanza that enables the clock? > err = clk_enable(priv->clk); > if (err) > return err; > -- > 1.9.1 > Cheers, Moritz ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH] zynq-fpga: Only route PR via PCAP when required @ 2018-10-23 9:01 ` Moritz Fischer 0 siblings, 0 replies; 20+ messages in thread From: Moritz Fischer @ 2018-10-23 9:01 UTC (permalink / raw) To: linux-arm-kernel Hi Mike, seems like a good usecase (though uncommon), question below On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote: > The Xilinx Zynq FPGA driver takes ownership of the PR interface, making > it impossible to use the ICAP interface for partial reconfiguration. > > This patch changes the driver to only activate PR over PCAP while the > device is actively being accessed by the driver for programming. > > This allows both PCAP and ICAP interfaces to be used for PR. > > Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> > --- > drivers/fpga/zynq-fpga.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c > index 3110e00..f6c205a 100644 > --- a/drivers/fpga/zynq-fpga.c > +++ b/drivers/fpga/zynq-fpga.c > @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, > int err; > u32 intr_status; > > + /* Release 'PR' control back to the ICAP */ > + zynq_fpga_write(priv, CTRL_OFFSET, > + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); > + Shouldn't that be after the below stanza that enables the clock? > err = clk_enable(priv->clk); > if (err) > return err; > -- > 1.9.1 > Cheers, Moritz ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] zynq-fpga: Only route PR via PCAP when required 2018-10-23 9:01 ` Moritz Fischer (?) @ 2018-10-23 10:53 ` Mike Looijmans -1 siblings, 0 replies; 20+ messages in thread From: Mike Looijmans @ 2018-10-23 10:53 UTC (permalink / raw) To: Moritz Fischer Cc: linux-fpga, linux-arm-kernel, linux-kernel, michal.simek, atull On 23-10-18 11:01, Moritz Fischer wrote: > Hi Mike, > > seems like a good usecase (though uncommon), question below Usecases for ICAP: - It's considerably faster than PCAP - Self-repairing logic (e.g. single-event upsets) - Being programmed from a remote FPGA - Programming through another bus (e.g. PCIe) > > On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote: >> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making >> it impossible to use the ICAP interface for partial reconfiguration. >> >> This patch changes the driver to only activate PR over PCAP while the >> device is actively being accessed by the driver for programming. >> >> This allows both PCAP and ICAP interfaces to be used for PR. >> >> Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> >> --- >> drivers/fpga/zynq-fpga.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c >> index 3110e00..f6c205a 100644 >> --- a/drivers/fpga/zynq-fpga.c >> +++ b/drivers/fpga/zynq-fpga.c >> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, >> int err; >> u32 intr_status; >> >> + /* Release 'PR' control back to the ICAP */ >> + zynq_fpga_write(priv, CTRL_OFFSET, >> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); >> + > > Shouldn't that be after the below stanza that enables the clock? I'm actually not sure, and I did not encounter any problems while testing this, but it's easier to just move it than to find out, so I'll go for "yes, let's enable the clock first". I'll await a bit more feedback and post a v2 for that. > >> err = clk_enable(priv->clk); >> if (err) >> return err; >> -- >> 1.9.1 >> > > Cheers, > > Moritz > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH] zynq-fpga: Only route PR via PCAP when required @ 2018-10-23 10:53 ` Mike Looijmans 0 siblings, 0 replies; 20+ messages in thread From: Mike Looijmans @ 2018-10-23 10:53 UTC (permalink / raw) To: linux-arm-kernel On 23-10-18 11:01, Moritz Fischer wrote: > Hi Mike, > > seems like a good usecase (though uncommon), question below Usecases for ICAP: - It's considerably faster than PCAP - Self-repairing logic (e.g. single-event upsets) - Being programmed from a remote FPGA - Programming through another bus (e.g. PCIe) > > On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote: >> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making >> it impossible to use the ICAP interface for partial reconfiguration. >> >> This patch changes the driver to only activate PR over PCAP while the >> device is actively being accessed by the driver for programming. >> >> This allows both PCAP and ICAP interfaces to be used for PR. >> >> Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> >> --- >> drivers/fpga/zynq-fpga.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c >> index 3110e00..f6c205a 100644 >> --- a/drivers/fpga/zynq-fpga.c >> +++ b/drivers/fpga/zynq-fpga.c >> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, >> int err; >> u32 intr_status; >> >> + /* Release 'PR' control back to the ICAP */ >> + zynq_fpga_write(priv, CTRL_OFFSET, >> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); >> + > > Shouldn't that be after the below stanza that enables the clock? I'm actually not sure, and I did not encounter any problems while testing this, but it's easier to just move it than to find out, so I'll go for "yes, let's enable the clock first". I'll await a bit more feedback and post a v2 for that. > >> err = clk_enable(priv->clk); >> if (err) >> return err; >> -- >> 1.9.1 >> > > Cheers, > > Moritz > ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] zynq-fpga: Only route PR via PCAP when required @ 2018-10-23 10:53 ` Mike Looijmans 0 siblings, 0 replies; 20+ messages in thread From: Mike Looijmans @ 2018-10-23 10:53 UTC (permalink / raw) To: Moritz Fischer Cc: linux-fpga, linux-arm-kernel, linux-kernel, michal.simek, atull On 23-10-18 11:01, Moritz Fischer wrote: > Hi Mike, > > seems like a good usecase (though uncommon), question below Usecases for ICAP: - It's considerably faster than PCAP - Self-repairing logic (e.g. single-event upsets) - Being programmed from a remote FPGA - Programming through another bus (e.g. PCIe) > > On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote: >> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making >> it impossible to use the ICAP interface for partial reconfiguration. >> >> This patch changes the driver to only activate PR over PCAP while the >> device is actively being accessed by the driver for programming. >> >> This allows both PCAP and ICAP interfaces to be used for PR. >> >> Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> >> --- >> drivers/fpga/zynq-fpga.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c >> index 3110e00..f6c205a 100644 >> --- a/drivers/fpga/zynq-fpga.c >> +++ b/drivers/fpga/zynq-fpga.c >> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, >> int err; >> u32 intr_status; >> >> + /* Release 'PR' control back to the ICAP */ >> + zynq_fpga_write(priv, CTRL_OFFSET, >> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); >> + > > Shouldn't that be after the below stanza that enables the clock? I'm actually not sure, and I did not encounter any problems while testing this, but it's easier to just move it than to find out, so I'll go for "yes, let's enable the clock first". I'll await a bit more feedback and post a v2 for that. > >> err = clk_enable(priv->clk); >> if (err) >> return err; >> -- >> 1.9.1 >> > > Cheers, > > Moritz > ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] zynq-fpga: Only route PR via PCAP when required 2018-10-23 10:53 ` Mike Looijmans (?) @ 2018-10-23 11:04 ` Moritz Fischer -1 siblings, 0 replies; 20+ messages in thread From: Moritz Fischer @ 2018-10-23 11:04 UTC (permalink / raw) To: Mike Looijmans Cc: Moritz Fischer, linux-fpga, linux-arm-kernel, linux-kernel, michal.simek, atull Hi Mike, On Tue, Oct 23, 2018 at 10:53:50AM +0000, Mike Looijmans wrote: > On 23-10-18 11:01, Moritz Fischer wrote: > > Hi Mike, > > > > seems like a good usecase (though uncommon), question below > > Usecases for ICAP: > - It's considerably faster than PCAP > - Self-repairing logic (e.g. single-event upsets) > - Being programmed from a remote FPGA > - Programming through another bus (e.g. PCIe) Yeah, I wasn't saying it's a bad usecase, just not super common :) > > > > > > On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote: > >> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making > >> it impossible to use the ICAP interface for partial reconfiguration. > >> > >> This patch changes the driver to only activate PR over PCAP while the > >> device is actively being accessed by the driver for programming. > >> > >> This allows both PCAP and ICAP interfaces to be used for PR. > >> > >> Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> > >> --- > >> drivers/fpga/zynq-fpga.c | 4 ++++ > >> 1 file changed, 4 insertions(+) > >> > >> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c > >> index 3110e00..f6c205a 100644 > >> --- a/drivers/fpga/zynq-fpga.c > >> +++ b/drivers/fpga/zynq-fpga.c > >> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, > >> int err; > >> u32 intr_status; > >> > >> + /* Release 'PR' control back to the ICAP */ > >> + zynq_fpga_write(priv, CTRL_OFFSET, > >> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); > >> + > > > > Shouldn't that be after the below stanza that enables the clock? > > I'm actually not sure, and I did not encounter any problems while testing > this, but it's easier to just move it than to find out, so I'll go for "yes, > let's enable the clock first". > I'll await a bit more feedback and post a v2 for that. Ok, I had suspected you tested it and probably didn't run into issues, but just wanted to make sure we think about it. If you don't mind, swap it around as I suggested just to be safe. With that change feel free to add my Reviewed-by: Moritz Fischer <mdf@kernel.org> in your v2. Thanks for the patch, Moritz ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH] zynq-fpga: Only route PR via PCAP when required @ 2018-10-23 11:04 ` Moritz Fischer 0 siblings, 0 replies; 20+ messages in thread From: Moritz Fischer @ 2018-10-23 11:04 UTC (permalink / raw) To: linux-arm-kernel Hi Mike, On Tue, Oct 23, 2018 at 10:53:50AM +0000, Mike Looijmans wrote: > On 23-10-18 11:01, Moritz Fischer wrote: > > Hi Mike, > > > > seems like a good usecase (though uncommon), question below > > Usecases for ICAP: > - It's considerably faster than PCAP > - Self-repairing logic (e.g. single-event upsets) > - Being programmed from a remote FPGA > - Programming through another bus (e.g. PCIe) Yeah, I wasn't saying it's a bad usecase, just not super common :) > > > > > > On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote: > >> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making > >> it impossible to use the ICAP interface for partial reconfiguration. > >> > >> This patch changes the driver to only activate PR over PCAP while the > >> device is actively being accessed by the driver for programming. > >> > >> This allows both PCAP and ICAP interfaces to be used for PR. > >> > >> Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> > >> --- > >> drivers/fpga/zynq-fpga.c | 4 ++++ > >> 1 file changed, 4 insertions(+) > >> > >> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c > >> index 3110e00..f6c205a 100644 > >> --- a/drivers/fpga/zynq-fpga.c > >> +++ b/drivers/fpga/zynq-fpga.c > >> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, > >> int err; > >> u32 intr_status; > >> > >> + /* Release 'PR' control back to the ICAP */ > >> + zynq_fpga_write(priv, CTRL_OFFSET, > >> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); > >> + > > > > Shouldn't that be after the below stanza that enables the clock? > > I'm actually not sure, and I did not encounter any problems while testing > this, but it's easier to just move it than to find out, so I'll go for "yes, > let's enable the clock first". > I'll await a bit more feedback and post a v2 for that. Ok, I had suspected you tested it and probably didn't run into issues, but just wanted to make sure we think about it. If you don't mind, swap it around as I suggested just to be safe. With that change feel free to add my Reviewed-by: Moritz Fischer <mdf@kernel.org> in your v2. Thanks for the patch, Moritz ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] zynq-fpga: Only route PR via PCAP when required @ 2018-10-23 11:04 ` Moritz Fischer 0 siblings, 0 replies; 20+ messages in thread From: Moritz Fischer @ 2018-10-23 11:04 UTC (permalink / raw) To: Mike Looijmans Cc: Moritz Fischer, linux-fpga, linux-arm-kernel, linux-kernel, michal.simek, atull Hi Mike, On Tue, Oct 23, 2018 at 10:53:50AM +0000, Mike Looijmans wrote: > On 23-10-18 11:01, Moritz Fischer wrote: > > Hi Mike, > > > > seems like a good usecase (though uncommon), question below > > Usecases for ICAP: > - It's considerably faster than PCAP > - Self-repairing logic (e.g. single-event upsets) > - Being programmed from a remote FPGA > - Programming through another bus (e.g. PCIe) Yeah, I wasn't saying it's a bad usecase, just not super common :) > > > > > > On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote: > >> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making > >> it impossible to use the ICAP interface for partial reconfiguration. > >> > >> This patch changes the driver to only activate PR over PCAP while the > >> device is actively being accessed by the driver for programming. > >> > >> This allows both PCAP and ICAP interfaces to be used for PR. > >> > >> Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> > >> --- > >> drivers/fpga/zynq-fpga.c | 4 ++++ > >> 1 file changed, 4 insertions(+) > >> > >> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c > >> index 3110e00..f6c205a 100644 > >> --- a/drivers/fpga/zynq-fpga.c > >> +++ b/drivers/fpga/zynq-fpga.c > >> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, > >> int err; > >> u32 intr_status; > >> > >> + /* Release 'PR' control back to the ICAP */ > >> + zynq_fpga_write(priv, CTRL_OFFSET, > >> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); > >> + > > > > Shouldn't that be after the below stanza that enables the clock? > > I'm actually not sure, and I did not encounter any problems while testing > this, but it's easier to just move it than to find out, so I'll go for "yes, > let's enable the clock first". > I'll await a bit more feedback and post a v2 for that. Ok, I had suspected you tested it and probably didn't run into issues, but just wanted to make sure we think about it. If you don't mind, swap it around as I suggested just to be safe. With that change feel free to add my Reviewed-by: Moritz Fischer <mdf@kernel.org> in your v2. Thanks for the patch, Moritz ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] zynq-fpga: Only route PR via PCAP when required 2018-10-23 11:04 ` Moritz Fischer (?) @ 2018-10-26 7:54 ` Michal Simek -1 siblings, 0 replies; 20+ messages in thread From: Michal Simek @ 2018-10-26 7:54 UTC (permalink / raw) To: Moritz Fischer, Mike Looijmans Cc: linux-fpga, linux-arm-kernel, linux-kernel, michal.simek, atull On 23. 10. 18 13:04, Moritz Fischer wrote: > Hi Mike, > > On Tue, Oct 23, 2018 at 10:53:50AM +0000, Mike Looijmans wrote: >> On 23-10-18 11:01, Moritz Fischer wrote: >>> Hi Mike, >>> >>> seems like a good usecase (though uncommon), question below >> >> Usecases for ICAP: >> - It's considerably faster than PCAP >> - Self-repairing logic (e.g. single-event upsets) >> - Being programmed from a remote FPGA >> - Programming through another bus (e.g. PCIe) > > Yeah, I wasn't saying it's a bad usecase, just not super common :) > >> >> >>> >>> On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote: >>>> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making >>>> it impossible to use the ICAP interface for partial reconfiguration. >>>> >>>> This patch changes the driver to only activate PR over PCAP while the >>>> device is actively being accessed by the driver for programming. >>>> >>>> This allows both PCAP and ICAP interfaces to be used for PR. >>>> >>>> Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> >>>> --- >>>> drivers/fpga/zynq-fpga.c | 4 ++++ >>>> 1 file changed, 4 insertions(+) >>>> >>>> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c >>>> index 3110e00..f6c205a 100644 >>>> --- a/drivers/fpga/zynq-fpga.c >>>> +++ b/drivers/fpga/zynq-fpga.c >>>> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, >>>> int err; >>>> u32 intr_status; >>>> >>>> + /* Release 'PR' control back to the ICAP */ >>>> + zynq_fpga_write(priv, CTRL_OFFSET, >>>> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); >>>> + >>> >>> Shouldn't that be after the below stanza that enables the clock? >> >> I'm actually not sure, and I did not encounter any problems while testing >> this, but it's easier to just move it than to find out, so I'll go for "yes, >> let's enable the clock first". >> I'll await a bit more feedback and post a v2 for that. > > Ok, I had suspected you tested it and probably didn't run into issues, > but just wanted to make sure we think about it. If you don't mind, swap > it around as I suggested just to be safe. > > With that change feel free to add my Reviewed-by: Moritz Fischer > <mdf@kernel.org> in your v2. That clock can be used by something else that's why you didn't observe any issue. Anyway I have no problem with reverting that setting back that icap can be used. In general there should be synchronization mechanism for this. And also driver "feature" not to enable access from icap for security reason. But that's something what should be done in other patch. Thanks, Michal ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH] zynq-fpga: Only route PR via PCAP when required @ 2018-10-26 7:54 ` Michal Simek 0 siblings, 0 replies; 20+ messages in thread From: Michal Simek @ 2018-10-26 7:54 UTC (permalink / raw) To: linux-arm-kernel On 23. 10. 18 13:04, Moritz Fischer wrote: > Hi Mike, > > On Tue, Oct 23, 2018 at 10:53:50AM +0000, Mike Looijmans wrote: >> On 23-10-18 11:01, Moritz Fischer wrote: >>> Hi Mike, >>> >>> seems like a good usecase (though uncommon), question below >> >> Usecases for ICAP: >> - It's considerably faster than PCAP >> - Self-repairing logic (e.g. single-event upsets) >> - Being programmed from a remote FPGA >> - Programming through another bus (e.g. PCIe) > > Yeah, I wasn't saying it's a bad usecase, just not super common :) > >> >> >>> >>> On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote: >>>> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making >>>> it impossible to use the ICAP interface for partial reconfiguration. >>>> >>>> This patch changes the driver to only activate PR over PCAP while the >>>> device is actively being accessed by the driver for programming. >>>> >>>> This allows both PCAP and ICAP interfaces to be used for PR. >>>> >>>> Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> >>>> --- >>>> drivers/fpga/zynq-fpga.c | 4 ++++ >>>> 1 file changed, 4 insertions(+) >>>> >>>> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c >>>> index 3110e00..f6c205a 100644 >>>> --- a/drivers/fpga/zynq-fpga.c >>>> +++ b/drivers/fpga/zynq-fpga.c >>>> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, >>>> int err; >>>> u32 intr_status; >>>> >>>> + /* Release 'PR' control back to the ICAP */ >>>> + zynq_fpga_write(priv, CTRL_OFFSET, >>>> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); >>>> + >>> >>> Shouldn't that be after the below stanza that enables the clock? >> >> I'm actually not sure, and I did not encounter any problems while testing >> this, but it's easier to just move it than to find out, so I'll go for "yes, >> let's enable the clock first". >> I'll await a bit more feedback and post a v2 for that. > > Ok, I had suspected you tested it and probably didn't run into issues, > but just wanted to make sure we think about it. If you don't mind, swap > it around as I suggested just to be safe. > > With that change feel free to add my Reviewed-by: Moritz Fischer > <mdf@kernel.org> in your v2. That clock can be used by something else that's why you didn't observe any issue. Anyway I have no problem with reverting that setting back that icap can be used. In general there should be synchronization mechanism for this. And also driver "feature" not to enable access from icap for security reason. But that's something what should be done in other patch. Thanks, Michal ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] zynq-fpga: Only route PR via PCAP when required @ 2018-10-26 7:54 ` Michal Simek 0 siblings, 0 replies; 20+ messages in thread From: Michal Simek @ 2018-10-26 7:54 UTC (permalink / raw) To: Moritz Fischer, Mike Looijmans Cc: linux-fpga, linux-arm-kernel, linux-kernel, michal.simek, atull On 23. 10. 18 13:04, Moritz Fischer wrote: > Hi Mike, > > On Tue, Oct 23, 2018 at 10:53:50AM +0000, Mike Looijmans wrote: >> On 23-10-18 11:01, Moritz Fischer wrote: >>> Hi Mike, >>> >>> seems like a good usecase (though uncommon), question below >> >> Usecases for ICAP: >> - It's considerably faster than PCAP >> - Self-repairing logic (e.g. single-event upsets) >> - Being programmed from a remote FPGA >> - Programming through another bus (e.g. PCIe) > > Yeah, I wasn't saying it's a bad usecase, just not super common :) > >> >> >>> >>> On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote: >>>> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making >>>> it impossible to use the ICAP interface for partial reconfiguration. >>>> >>>> This patch changes the driver to only activate PR over PCAP while the >>>> device is actively being accessed by the driver for programming. >>>> >>>> This allows both PCAP and ICAP interfaces to be used for PR. >>>> >>>> Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> >>>> --- >>>> drivers/fpga/zynq-fpga.c | 4 ++++ >>>> 1 file changed, 4 insertions(+) >>>> >>>> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c >>>> index 3110e00..f6c205a 100644 >>>> --- a/drivers/fpga/zynq-fpga.c >>>> +++ b/drivers/fpga/zynq-fpga.c >>>> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, >>>> int err; >>>> u32 intr_status; >>>> >>>> + /* Release 'PR' control back to the ICAP */ >>>> + zynq_fpga_write(priv, CTRL_OFFSET, >>>> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); >>>> + >>> >>> Shouldn't that be after the below stanza that enables the clock? >> >> I'm actually not sure, and I did not encounter any problems while testing >> this, but it's easier to just move it than to find out, so I'll go for "yes, >> let's enable the clock first". >> I'll await a bit more feedback and post a v2 for that. > > Ok, I had suspected you tested it and probably didn't run into issues, > but just wanted to make sure we think about it. If you don't mind, swap > it around as I suggested just to be safe. > > With that change feel free to add my Reviewed-by: Moritz Fischer > <mdf@kernel.org> in your v2. That clock can be used by something else that's why you didn't observe any issue. Anyway I have no problem with reverting that setting back that icap can be used. In general there should be synchronization mechanism for this. And also driver "feature" not to enable access from icap for security reason. But that's something what should be done in other patch. Thanks, Michal ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] zynq-fpga: Only route PR via PCAP when required 2018-10-26 7:54 ` Michal Simek @ 2018-10-26 17:04 ` Moritz Fischer -1 siblings, 0 replies; 20+ messages in thread From: Moritz Fischer @ 2018-10-26 17:04 UTC (permalink / raw) To: Michal Simek Cc: mike.looijmans, linux-fpga, linux-arm-kernel, Linux Kernel Mailing List, Alan Tull Hi Michal, On Fri, Oct 26, 2018 at 12:54 AM Michal Simek <michal.simek@xilinx.com> wrote: > > Ok, I had suspected you tested it and probably didn't run into issues, > > but just wanted to make sure we think about it. If you don't mind, swap > > it around as I suggested just to be safe. > > > > With that change feel free to add my Reviewed-by: Moritz Fischer > > <mdf@kernel.org> in your v2. > > That clock can be used by something else that's why you didn't observe > any issue. Anyway I have no problem with reverting that setting back > that icap can be used. Ok, thanks for clarification, that was what I assumed :) > In general there should be synchronization mechanism for this. And also > driver "feature" not to enable access from icap for security reason. But > that's something what should be done in other patch. Yeah I'll have to look at remote notifications for FPGA managers soon-ish for another project as discussed at ELCE. Part of that would be synchronization I guess :) Umhh, based on the secure state read from CTRL_SEC_EN bit, or did you think along the lines of "xlnx,no-icap" property that your bootloader / dt would provide? Cheers, Moritz ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH] zynq-fpga: Only route PR via PCAP when required @ 2018-10-26 17:04 ` Moritz Fischer 0 siblings, 0 replies; 20+ messages in thread From: Moritz Fischer @ 2018-10-26 17:04 UTC (permalink / raw) To: linux-arm-kernel Hi Michal, On Fri, Oct 26, 2018 at 12:54 AM Michal Simek <michal.simek@xilinx.com> wrote: > > Ok, I had suspected you tested it and probably didn't run into issues, > > but just wanted to make sure we think about it. If you don't mind, swap > > it around as I suggested just to be safe. > > > > With that change feel free to add my Reviewed-by: Moritz Fischer > > <mdf@kernel.org> in your v2. > > That clock can be used by something else that's why you didn't observe > any issue. Anyway I have no problem with reverting that setting back > that icap can be used. Ok, thanks for clarification, that was what I assumed :) > In general there should be synchronization mechanism for this. And also > driver "feature" not to enable access from icap for security reason. But > that's something what should be done in other patch. Yeah I'll have to look at remote notifications for FPGA managers soon-ish for another project as discussed at ELCE. Part of that would be synchronization I guess :) Umhh, based on the secure state read from CTRL_SEC_EN bit, or did you think along the lines of "xlnx,no-icap" property that your bootloader / dt would provide? Cheers, Moritz ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2] zynq-fpga: Only route PR via PCAP when required 2018-10-23 6:31 ` Mike Looijmans @ 2018-10-24 7:53 ` Mike Looijmans -1 siblings, 0 replies; 20+ messages in thread From: Mike Looijmans @ 2018-10-24 7:53 UTC (permalink / raw) To: linux-fpga Cc: linux-arm-kernel, linux-kernel, michal.simek, mdf, atull, git, Mike Looijmans The Xilinx Zynq FPGA driver takes ownership of the PR interface, making it impossible to use the ICAP interface for partial reconfiguration. This patch changes the driver to only activate PR over PCAP while the device is actively being accessed by the driver for programming. This allows both PCAP and ICAP interfaces to be used for PR. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Reviewed-by: Moritz Fischer <mdf@kernel.org> --- v2: Move the register setting in between the clock enable/disable drivers/fpga/zynq-fpga.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index 3110e00..ff3a427 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -501,6 +501,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, if (err) return err; + /* Release 'PR' control back to the ICAP */ + zynq_fpga_write(priv, CTRL_OFFSET, + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); + err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, intr_status & IXR_PCFG_DONE_MASK, INIT_POLL_DELAY, -- 1.9.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2] zynq-fpga: Only route PR via PCAP when required @ 2018-10-24 7:53 ` Mike Looijmans 0 siblings, 0 replies; 20+ messages in thread From: Mike Looijmans @ 2018-10-24 7:53 UTC (permalink / raw) To: linux-arm-kernel The Xilinx Zynq FPGA driver takes ownership of the PR interface, making it impossible to use the ICAP interface for partial reconfiguration. This patch changes the driver to only activate PR over PCAP while the device is actively being accessed by the driver for programming. This allows both PCAP and ICAP interfaces to be used for PR. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Reviewed-by: Moritz Fischer <mdf@kernel.org> --- v2: Move the register setting in between the clock enable/disable drivers/fpga/zynq-fpga.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index 3110e00..ff3a427 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -501,6 +501,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, if (err) return err; + /* Release 'PR' control back to the ICAP */ + zynq_fpga_write(priv, CTRL_OFFSET, + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); + err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, intr_status & IXR_PCFG_DONE_MASK, INIT_POLL_DELAY, -- 1.9.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v2] zynq-fpga: Only route PR via PCAP when required 2018-10-24 7:53 ` Mike Looijmans (?) @ 2018-11-01 18:33 ` Alan Tull -1 siblings, 0 replies; 20+ messages in thread From: Alan Tull @ 2018-11-01 18:33 UTC (permalink / raw) To: mike.looijmans Cc: linux-fpga, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-kernel, Michal Simek, Moritz Fischer, git On Wed, Oct 24, 2018 at 2:53 AM Mike Looijmans <mike.looijmans@topic.nl> wrote: Hi Mike, > > The Xilinx Zynq FPGA driver takes ownership of the PR interface, making > it impossible to use the ICAP interface for partial reconfiguration. > > This patch changes the driver to only activate PR over PCAP while the > device is actively being accessed by the driver for programming. > > This allows both PCAP and ICAP interfaces to be used for PR. > > Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> > Reviewed-by: Moritz Fischer <mdf@kernel.org> Acked-by: Alan Tull <atull@kernel.org> Thanks for submitting! Alan > --- > v2: Move the register setting in between the clock enable/disable > > drivers/fpga/zynq-fpga.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c > index 3110e00..ff3a427 100644 > --- a/drivers/fpga/zynq-fpga.c > +++ b/drivers/fpga/zynq-fpga.c > @@ -501,6 +501,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, > if (err) > return err; > > + /* Release 'PR' control back to the ICAP */ > + zynq_fpga_write(priv, CTRL_OFFSET, > + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); > + > err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, > intr_status & IXR_PCFG_DONE_MASK, > INIT_POLL_DELAY, > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2] zynq-fpga: Only route PR via PCAP when required @ 2018-11-01 18:33 ` Alan Tull 0 siblings, 0 replies; 20+ messages in thread From: Alan Tull @ 2018-11-01 18:33 UTC (permalink / raw) To: linux-arm-kernel On Wed, Oct 24, 2018 at 2:53 AM Mike Looijmans <mike.looijmans@topic.nl> wrote: Hi Mike, > > The Xilinx Zynq FPGA driver takes ownership of the PR interface, making > it impossible to use the ICAP interface for partial reconfiguration. > > This patch changes the driver to only activate PR over PCAP while the > device is actively being accessed by the driver for programming. > > This allows both PCAP and ICAP interfaces to be used for PR. > > Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> > Reviewed-by: Moritz Fischer <mdf@kernel.org> Acked-by: Alan Tull <atull@kernel.org> Thanks for submitting! Alan > --- > v2: Move the register setting in between the clock enable/disable > > drivers/fpga/zynq-fpga.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c > index 3110e00..ff3a427 100644 > --- a/drivers/fpga/zynq-fpga.c > +++ b/drivers/fpga/zynq-fpga.c > @@ -501,6 +501,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, > if (err) > return err; > > + /* Release 'PR' control back to the ICAP */ > + zynq_fpga_write(priv, CTRL_OFFSET, > + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); > + > err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, > intr_status & IXR_PCFG_DONE_MASK, > INIT_POLL_DELAY, > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2] zynq-fpga: Only route PR via PCAP when required @ 2018-11-01 18:33 ` Alan Tull 0 siblings, 0 replies; 20+ messages in thread From: Alan Tull @ 2018-11-01 18:33 UTC (permalink / raw) To: mike.looijmans Cc: linux-fpga, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-kernel, Michal Simek, Moritz Fischer, git On Wed, Oct 24, 2018 at 2:53 AM Mike Looijmans <mike.looijmans@topic.nl> wrote: Hi Mike, > > The Xilinx Zynq FPGA driver takes ownership of the PR interface, making > it impossible to use the ICAP interface for partial reconfiguration. > > This patch changes the driver to only activate PR over PCAP while the > device is actively being accessed by the driver for programming. > > This allows both PCAP and ICAP interfaces to be used for PR. > > Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> > Reviewed-by: Moritz Fischer <mdf@kernel.org> Acked-by: Alan Tull <atull@kernel.org> Thanks for submitting! Alan > --- > v2: Move the register setting in between the clock enable/disable > > drivers/fpga/zynq-fpga.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c > index 3110e00..ff3a427 100644 > --- a/drivers/fpga/zynq-fpga.c > +++ b/drivers/fpga/zynq-fpga.c > @@ -501,6 +501,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, > if (err) > return err; > > + /* Release 'PR' control back to the ICAP */ > + zynq_fpga_write(priv, CTRL_OFFSET, > + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); > + > err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, > intr_status & IXR_PCFG_DONE_MASK, > INIT_POLL_DELAY, > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2018-11-01 18:34 UTC | newest] Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-10-23 6:31 [PATCH] zynq-fpga: Only route PR via PCAP when required Mike Looijmans 2018-10-23 6:31 ` Mike Looijmans 2018-10-23 9:01 ` Moritz Fischer 2018-10-23 9:01 ` Moritz Fischer 2018-10-23 10:53 ` Mike Looijmans 2018-10-23 10:53 ` Mike Looijmans 2018-10-23 10:53 ` Mike Looijmans 2018-10-23 11:04 ` Moritz Fischer 2018-10-23 11:04 ` Moritz Fischer 2018-10-23 11:04 ` Moritz Fischer 2018-10-26 7:54 ` Michal Simek 2018-10-26 7:54 ` Michal Simek 2018-10-26 7:54 ` Michal Simek 2018-10-26 17:04 ` Moritz Fischer 2018-10-26 17:04 ` Moritz Fischer 2018-10-24 7:53 ` [PATCH v2] " Mike Looijmans 2018-10-24 7:53 ` Mike Looijmans 2018-11-01 18:33 ` Alan Tull 2018-11-01 18:33 ` Alan Tull 2018-11-01 18:33 ` Alan Tull
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.