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From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: Sagar Kadam <sagar.kadam@sifive.com>,
	Atish Patra <atishp@atishpatra.org>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Rob Herring <robh+dt@kernel.org>, Conor Dooley <mail@conchuod.ie>
Subject: Re: [PATCH 2/2] riscv: dts: microchip: use an mpfs specific l2 compatible
Date: Thu, 25 Aug 2022 21:51:46 +0200	[thread overview]
Message-ID: <18f0c833-94c6-616c-ce21-384492945240@canonical.com> (raw)
In-Reply-To: <20220825180417.1259360-3-mail@conchuod.ie>



On 8/25/22 20:04, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> PolarFire SoC does not have the same l2 cache controller as the fu540,
> featuring an extra interrupt. Appease the devicetree checker overlords
> by adding a PolarFire SoC specific compatible to fix the below sort of
> warnings:
> 
> mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long
> 
> Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
> Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts")
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>

WARNING: multiple messages have this Message-ID (diff)
From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: Sagar Kadam <sagar.kadam@sifive.com>,
	Atish Patra <atishp@atishpatra.org>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Rob Herring <robh+dt@kernel.org>, Conor Dooley <mail@conchuod.ie>
Subject: Re: [PATCH 2/2] riscv: dts: microchip: use an mpfs specific l2 compatible
Date: Thu, 25 Aug 2022 21:51:46 +0200	[thread overview]
Message-ID: <18f0c833-94c6-616c-ce21-384492945240@canonical.com> (raw)
In-Reply-To: <20220825180417.1259360-3-mail@conchuod.ie>



On 8/25/22 20:04, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> PolarFire SoC does not have the same l2 cache controller as the fu540,
> featuring an extra interrupt. Appease the devicetree checker overlords
> by adding a PolarFire SoC specific compatible to fix the below sort of
> warnings:
> 
> mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long
> 
> Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
> Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts")
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>

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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2022-08-25 19:52 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-25 18:04 [PATCH 0/2] Add a PolarFire SoC l2 compatible Conor Dooley
2022-08-25 18:04 ` Conor Dooley
2022-08-25 18:04 ` [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible Conor Dooley
2022-08-25 18:04   ` Conor Dooley
2022-08-25 18:36   ` Heinrich Schuchardt
2022-08-25 18:36     ` Heinrich Schuchardt
2022-08-25 18:56     ` Conor.Dooley
2022-08-25 18:56       ` Conor.Dooley
2022-08-25 19:49       ` Heinrich Schuchardt
2022-08-25 19:49         ` Heinrich Schuchardt
2022-08-25 20:03         ` Conor.Dooley
2022-08-25 20:03           ` Conor.Dooley
2022-08-30 20:57     ` Rob Herring
2022-08-30 20:57       ` Rob Herring
2022-08-30 21:59   ` Rob Herring
2022-08-30 21:59     ` Rob Herring
2022-08-25 18:04 ` [PATCH 2/2] riscv: dts: microchip: use an mpfs specific l2 compatible Conor Dooley
2022-08-25 18:04   ` Conor Dooley
2022-08-25 19:51   ` Heinrich Schuchardt [this message]
2022-08-25 19:51     ` Heinrich Schuchardt
2022-08-31 16:13 ` [PATCH 0/2] Add a PolarFire SoC " Conor Dooley
2022-08-31 16:13   ` Conor Dooley

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