From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> To: Conor Dooley <conor.dooley@microchip.com> Cc: Sagar Kadam <sagar.kadam@sifive.com>, Atish Patra <atishp@atishpatra.org>, Paul Walmsley <paul.walmsley@sifive.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>, Daire McNamara <daire.mcnamara@microchip.com>, Palmer Dabbelt <palmer@dabbelt.com>, Rob Herring <robh+dt@kernel.org>, Conor Dooley <mail@conchuod.ie> Subject: Re: [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible Date: Thu, 25 Aug 2022 20:36:49 +0200 [thread overview] Message-ID: <5f00ab85-d5ac-728d-2157-e70f2a46cc90@canonical.com> (raw) In-Reply-To: <20220825180417.1259360-2-mail@conchuod.ie> On 8/25/22 20:04, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The l2 cache on PolarFire SoC is cross between that of the fu540 and > the fu740. It has the extra interrupt from the fu740 but the lower > number of cache-sets. Add a specific compatible to avoid the likes > of: > > mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long Where is such a message written? I couldn't find the string in next-20220825 (git grep -n 'is too long"'). Why should a different number of cache sets require an extra compatible string. cache-size is simply a parameter going with the existing compatible strings. I would assume that you only need an extra compatible string if there is a functional difference that can not be expressed with the existing parameters. > > Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts") > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../bindings/riscv/sifive-l2-cache.yaml | 79 ++++++++++++------- > 1 file changed, 49 insertions(+), 30 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > index 69cdab18d629..ca3b9be58058 100644 > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > @@ -17,9 +17,6 @@ description: > acts as directory-based coherency manager. > All the properties in ePAPR/DeviceTree specification applies for this platform. > > -allOf: > - - $ref: /schemas/cache-controller.yaml# > - > select: > properties: > compatible: > @@ -33,11 +30,16 @@ select: > > properties: > compatible: > - items: > - - enum: > - - sifive,fu540-c000-ccache > - - sifive,fu740-c000-ccache Why can't you simply add microchip,mpfs-ccache here? > - - const: cache > + oneOf: > + - items: > + - enum: > + - sifive,fu540-c000-ccache > + - sifive,fu740-c000-ccache > + - const: cache > + - items: > + - const: microchip,mpfs-ccache > + - const: sifive,fu540-c000-ccache Why do we need 'sifive,fu540-c000-ccache' twice? Best regards Heinrich > + - const: cache > > cache-block-size: > const: 64 > @@ -72,29 +74,46 @@ properties: > The reference to the reserved-memory for the L2 Loosely Integrated Memory region. > The reserved memory node should be defined as per the bindings in reserved-memory.txt. > > -if: > - properties: > - compatible: > - contains: > - const: sifive,fu540-c000-ccache > +allOf: > + - $ref: /schemas/cache-controller.yaml# > > -then: > - properties: > - interrupts: > - description: | > - Must contain entries for DirError, DataError and DataFail signals. > - maxItems: 3 > - cache-sets: > - const: 1024 > - > -else: > - properties: > - interrupts: > - description: | > - Must contain entries for DirError, DataError, DataFail, DirFail signals. > - minItems: 4 > - cache-sets: > - const: 2048 > + - if: > + properties: > + compatible: > + contains: > + enum: > + - sifive,fu740-c000-ccache > + - microchip,mpfs-ccache > + > + then: > + properties: > + interrupts: > + description: | > + Must contain entries for DirError, DataError, DataFail, DirFail signals. > + minItems: 4 > + > + else: > + properties: > + interrupts: > + description: | > + Must contain entries for DirError, DataError and DataFail signals. > + maxItems: 3 > + > + - if: > + properties: > + compatible: > + contains: > + const: sifive,fu740-c000-ccache > + > + then: > + properties: > + cache-sets: > + const: 2048 > + > + else: > + properties: > + cache-sets: > + const: 1024 > > additionalProperties: false >
WARNING: multiple messages have this Message-ID (diff)
From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> To: Conor Dooley <conor.dooley@microchip.com> Cc: Sagar Kadam <sagar.kadam@sifive.com>, Atish Patra <atishp@atishpatra.org>, Paul Walmsley <paul.walmsley@sifive.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>, Daire McNamara <daire.mcnamara@microchip.com>, Palmer Dabbelt <palmer@dabbelt.com>, Rob Herring <robh+dt@kernel.org>, Conor Dooley <mail@conchuod.ie> Subject: Re: [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible Date: Thu, 25 Aug 2022 20:36:49 +0200 [thread overview] Message-ID: <5f00ab85-d5ac-728d-2157-e70f2a46cc90@canonical.com> (raw) In-Reply-To: <20220825180417.1259360-2-mail@conchuod.ie> On 8/25/22 20:04, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The l2 cache on PolarFire SoC is cross between that of the fu540 and > the fu740. It has the extra interrupt from the fu740 but the lower > number of cache-sets. Add a specific compatible to avoid the likes > of: > > mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long Where is such a message written? I couldn't find the string in next-20220825 (git grep -n 'is too long"'). Why should a different number of cache sets require an extra compatible string. cache-size is simply a parameter going with the existing compatible strings. I would assume that you only need an extra compatible string if there is a functional difference that can not be expressed with the existing parameters. > > Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts") > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../bindings/riscv/sifive-l2-cache.yaml | 79 ++++++++++++------- > 1 file changed, 49 insertions(+), 30 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > index 69cdab18d629..ca3b9be58058 100644 > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > @@ -17,9 +17,6 @@ description: > acts as directory-based coherency manager. > All the properties in ePAPR/DeviceTree specification applies for this platform. > > -allOf: > - - $ref: /schemas/cache-controller.yaml# > - > select: > properties: > compatible: > @@ -33,11 +30,16 @@ select: > > properties: > compatible: > - items: > - - enum: > - - sifive,fu540-c000-ccache > - - sifive,fu740-c000-ccache Why can't you simply add microchip,mpfs-ccache here? > - - const: cache > + oneOf: > + - items: > + - enum: > + - sifive,fu540-c000-ccache > + - sifive,fu740-c000-ccache > + - const: cache > + - items: > + - const: microchip,mpfs-ccache > + - const: sifive,fu540-c000-ccache Why do we need 'sifive,fu540-c000-ccache' twice? Best regards Heinrich > + - const: cache > > cache-block-size: > const: 64 > @@ -72,29 +74,46 @@ properties: > The reference to the reserved-memory for the L2 Loosely Integrated Memory region. > The reserved memory node should be defined as per the bindings in reserved-memory.txt. > > -if: > - properties: > - compatible: > - contains: > - const: sifive,fu540-c000-ccache > +allOf: > + - $ref: /schemas/cache-controller.yaml# > > -then: > - properties: > - interrupts: > - description: | > - Must contain entries for DirError, DataError and DataFail signals. > - maxItems: 3 > - cache-sets: > - const: 1024 > - > -else: > - properties: > - interrupts: > - description: | > - Must contain entries for DirError, DataError, DataFail, DirFail signals. > - minItems: 4 > - cache-sets: > - const: 2048 > + - if: > + properties: > + compatible: > + contains: > + enum: > + - sifive,fu740-c000-ccache > + - microchip,mpfs-ccache > + > + then: > + properties: > + interrupts: > + description: | > + Must contain entries for DirError, DataError, DataFail, DirFail signals. > + minItems: 4 > + > + else: > + properties: > + interrupts: > + description: | > + Must contain entries for DirError, DataError and DataFail signals. > + maxItems: 3 > + > + - if: > + properties: > + compatible: > + contains: > + const: sifive,fu740-c000-ccache > + > + then: > + properties: > + cache-sets: > + const: 2048 > + > + else: > + properties: > + cache-sets: > + const: 1024 > > additionalProperties: false > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-08-25 18:37 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-25 18:04 [PATCH 0/2] Add a PolarFire SoC l2 compatible Conor Dooley 2022-08-25 18:04 ` Conor Dooley 2022-08-25 18:04 ` [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible Conor Dooley 2022-08-25 18:04 ` Conor Dooley 2022-08-25 18:36 ` Heinrich Schuchardt [this message] 2022-08-25 18:36 ` Heinrich Schuchardt 2022-08-25 18:56 ` Conor.Dooley 2022-08-25 18:56 ` Conor.Dooley 2022-08-25 19:49 ` Heinrich Schuchardt 2022-08-25 19:49 ` Heinrich Schuchardt 2022-08-25 20:03 ` Conor.Dooley 2022-08-25 20:03 ` Conor.Dooley 2022-08-30 20:57 ` Rob Herring 2022-08-30 20:57 ` Rob Herring 2022-08-30 21:59 ` Rob Herring 2022-08-30 21:59 ` Rob Herring 2022-08-25 18:04 ` [PATCH 2/2] riscv: dts: microchip: use an mpfs specific l2 compatible Conor Dooley 2022-08-25 18:04 ` Conor Dooley 2022-08-25 19:51 ` Heinrich Schuchardt 2022-08-25 19:51 ` Heinrich Schuchardt 2022-08-31 16:13 ` [PATCH 0/2] Add a PolarFire SoC " Conor Dooley 2022-08-31 16:13 ` Conor Dooley
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