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From: Rob Herring <robh@kernel.org>
To: Conor Dooley <mail@conchuod.ie>
Cc: Daire McNamara <daire.mcnamara@microchip.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	linux-riscv@lists.infradead.org,
	Sagar Kadam <sagar.kadam@sifive.com>,
	Atish Patra <atishp@atishpatra.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Rob Herring <robh+dt@kernel.org>,
	Conor Dooley <conor.dooley@microchip.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Subject: Re: [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible
Date: Tue, 30 Aug 2022 16:59:00 -0500	[thread overview]
Message-ID: <20220830215900.GA2162133-robh@kernel.org> (raw)
In-Reply-To: <20220825180417.1259360-2-mail@conchuod.ie>

On Thu, 25 Aug 2022 19:04:17 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> The l2 cache on PolarFire SoC is cross between that of the fu540 and
> the fu740. It has the extra interrupt from the fu740 but the lower
> number of cache-sets. Add a specific compatible to avoid the likes
> of:
> 
> mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long
> 
> Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts")
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../bindings/riscv/sifive-l2-cache.yaml       | 79 ++++++++++++-------
>  1 file changed, 49 insertions(+), 30 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Conor Dooley <mail@conchuod.ie>
Cc: Daire McNamara <daire.mcnamara@microchip.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	linux-riscv@lists.infradead.org,
	Sagar Kadam <sagar.kadam@sifive.com>,
	Atish Patra <atishp@atishpatra.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Rob Herring <robh+dt@kernel.org>,
	Conor Dooley <conor.dooley@microchip.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Subject: Re: [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible
Date: Tue, 30 Aug 2022 16:59:00 -0500	[thread overview]
Message-ID: <20220830215900.GA2162133-robh@kernel.org> (raw)
In-Reply-To: <20220825180417.1259360-2-mail@conchuod.ie>

On Thu, 25 Aug 2022 19:04:17 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> The l2 cache on PolarFire SoC is cross between that of the fu540 and
> the fu740. It has the extra interrupt from the fu740 but the lower
> number of cache-sets. Add a specific compatible to avoid the likes
> of:
> 
> mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long
> 
> Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts")
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../bindings/riscv/sifive-l2-cache.yaml       | 79 ++++++++++++-------
>  1 file changed, 49 insertions(+), 30 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

  parent reply	other threads:[~2022-08-30 21:59 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-25 18:04 [PATCH 0/2] Add a PolarFire SoC l2 compatible Conor Dooley
2022-08-25 18:04 ` Conor Dooley
2022-08-25 18:04 ` [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible Conor Dooley
2022-08-25 18:04   ` Conor Dooley
2022-08-25 18:36   ` Heinrich Schuchardt
2022-08-25 18:36     ` Heinrich Schuchardt
2022-08-25 18:56     ` Conor.Dooley
2022-08-25 18:56       ` Conor.Dooley
2022-08-25 19:49       ` Heinrich Schuchardt
2022-08-25 19:49         ` Heinrich Schuchardt
2022-08-25 20:03         ` Conor.Dooley
2022-08-25 20:03           ` Conor.Dooley
2022-08-30 20:57     ` Rob Herring
2022-08-30 20:57       ` Rob Herring
2022-08-30 21:59   ` Rob Herring [this message]
2022-08-30 21:59     ` Rob Herring
2022-08-25 18:04 ` [PATCH 2/2] riscv: dts: microchip: use an mpfs specific l2 compatible Conor Dooley
2022-08-25 18:04   ` Conor Dooley
2022-08-25 19:51   ` Heinrich Schuchardt
2022-08-25 19:51     ` Heinrich Schuchardt
2022-08-31 16:13 ` [PATCH 0/2] Add a PolarFire SoC " Conor Dooley
2022-08-31 16:13   ` Conor Dooley

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